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Jorge9314/ElectronicaDigital | Impresora2D/TB_Divisor_Frecuencia.vhd | 1 | 975 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY TB_Divisor_Frecuencia IS
END TB_Divisor_Frecuencia;
ARCHITECTURE behavior OF TB_Divisor_Frecuencia IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Divisor_Frecuencia
PORT(
clk : IN std_logic;
Salida : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
--Outputs
signal Salida : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Divisor_Frecuencia PORT MAP (
clk => clk,
Salida => Salida
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait;
end process;
END;
| gpl-3.0 | 2184b0d73e971639fe98fce0e62bd365 | 0.580513 | 4.079498 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/vhdlFile/component_instantiation_statement/classification_test_input.vhd | 1 | 3,385 |
architecture ARCH of ENTITY is
begin
-- Component instantiation without component keyword.
U_INST1 : INST1
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : INST1
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
);
U_INST1 : INST1;
-- Component instantiation with component keyword.
U_INST1 : component INST1
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : component INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : component INST1
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
);
U_INST1 : component INST1;
-- entity without architecture identifier
U_INST1 : entity INST1
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : entity INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : entity INST1
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
);
U_INST1 : entity INST1;
-- entity without architecture identifier and with library identifier
U_INST1 : entity my_lib.INST1
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : entity my_lib.INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : entity my_lib.INST1
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
);
U_INST1 : entity my_lib.INST1;
-- entity with architecture identifier
U_INST1 : entity INST1 (rtl)
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : entity INST1 (rtl)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : entity INST1 (rtl)
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
);
U_INST1 : entity INST1 (rtl);
-- configuration
U_INST1 : configuration INST1
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : configuration INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : configuration INST1
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
);
U_INST1 : configuration INST1;
end architecture ARCH;
| gpl-3.0 | fb96ad87416a117d4b62a969f5d5a75f | 0.489217 | 2.788303 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/generic/rule_007_test_input.fixed_upper.vhd | 1 | 1,897 |
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32;
PREFIX_GENERIC_SUFFIX : integer := 20
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32;
PREFIX_GENERIC_SUFFIX : integer := 20
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32;
PREFIX_GENERIC_SUFFIX : integer := 20
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32;
PREFIX_GENERIC_SUFFIX : integer := 20
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
entity FIFO is
generic(G_SIZE : integer := 10;
G_WIDTH : integer := 256;
G_DEPTH : integer := 32;
PREFIX_GENERIC_SUFFIX : integer := 20
);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
entity FIFO is
generic(G_SIZE : integer := 10;
G_WIDTH : integer := 256;
G_DEPTH : integer := 32;
PREFIX_GENERIC_SUFFIX : integer := 20
);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
entity FIFO is
generic(G_SIZE : integer := 10;
G_WIDTH : integer := 256;
G_DEPTH : integer := 32;
PREFIX_GENERIC_SUFFIX : integer := 20
);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
entity FIFO is
generic(G_SIZE : integer := 10;
G_WIDTH : integer := 256;
G_DEPTH : integer := 32;
PREFIX_GENERIC_SUFFIX : integer := 20
);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
| gpl-3.0 | c22e8ecb2d45f57b922330c49fdaff71 | 0.573537 | 3.120066 | false | false | false | false |
NicoLedwith/Dr.AluOpysel | RAT_MCU/Wrapper.vhd | 1 | 5,606 | -------------------------------------------------------------------------------
-- Company: RAT Technologies
-- Engineer: Various RAT rats
--
-- Create Date: 1/31/2012
-- Design Name:
-- Module Name: RAT_wrapper - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Wrapper for RAT MCU. This model provides a template to
-- interface the RAT MCU to the Nexys2 development board.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RAT_wrapper is
Port ( LEDS : out STD_LOGIC_VECTOR (7 downto 0);
SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0);
DISP_EN : out STD_LOGIC_VECTOR (3 downto 0);
SWITCHES : in STD_LOGIC_VECTOR (7 downto 0);
BUTTONS : in STD_LOGIC_VECTOR (3 downto 0);
RESET : in STD_LOGIC;
CLK : in STD_LOGIC);
end RAT_wrapper;
architecture Behavioral of RAT_wrapper is
-------------------------------------------------------------------------------
-- INPUT PORT IDS -------------------------------------------------------------
CONSTANT SWITCHES_ID : STD_LOGIC_VECTOR (7 downto 0) := X"20";
CONSTANT BUTTONS_ID : STD_LOGIC_VECTOR (7 downto 0) := X"24";
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- OUTPUT PORT IDS ------------------------------------------------------------
CONSTANT LEDS_ID : STD_LOGIC_VECTOR (7 downto 0) := X"40";
CONSTANT SEGMENTS_ID : STD_LOGIC_VECTOR (7 downto 0) := X"82";
CONSTANT DISP_EN_ID : STD_LOGIC_VECTOR (7 downto 0) := X"83";
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Declare RAT_MCU ------------------------------------------------------------
component RAT_MCU
Port ( IN_PORT : in STD_LOGIC_VECTOR (7 downto 0);
OUT_PORT : out STD_LOGIC_VECTOR (7 downto 0);
PORT_ID : out STD_LOGIC_VECTOR (7 downto 0);
IO_STRB : out STD_LOGIC;
RESET : in STD_LOGIC;
INT : in STD_LOGIC;
CLK : in STD_LOGIC);
end component RAT_MCU;
-------------------------------------------------------------------------------
-- Signals for connecting RAT_MCU to RAT_wrapper -------------------------------
signal s_input_port : std_logic_vector (7 downto 0);
signal s_output_port : std_logic_vector (7 downto 0);
signal s_port_id : std_logic_vector (7 downto 0);
signal s_load : std_logic;
--signal s_interrupt : std_logic; -- not yet used
-- Register definitions for output devices ------------------------------------
signal r_LEDS : std_logic_vector (7 downto 0) := (others => '0');
signal r_SEGMENTS : std_logic_vector (7 downto 0) := (others => '0');
signal r_DISP_EN : std_logic_vector (3 downto 0) := (others => '0');
-------------------------------------------------------------------------------
begin
-- Instantiate RAT_MCU --------------------------------------------------------
MCU: RAT_MCU
port map( IN_PORT => s_input_port,
OUT_PORT => s_output_port,
PORT_ID => s_port_id,
RESET => RESET,
IO_STRB => s_load,
INT => BUTTONS(3),
CLK => CLK);
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- MUX for selecting what input to read
-------------------------------------------------------------------------------
inputs: process(s_port_id, SWITCHES, BUTTONS)
begin
if (s_port_id = SWITCHES_ID) then
s_input_port <= SWITCHES;
elsif (s_port_id = BUTTONS_ID) then
s_input_port <= "00000" & BUTTONS(2 downto 0);
else
s_input_port <= x"00";
end if;
end process inputs;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Decoder for updating output registers
-- Register updates depend on rising clock edge and asserted load signal
-------------------------------------------------------------------------------
outputs: process(CLK, s_load, s_port_id)
begin
if (rising_edge(CLK)) then
if (s_load = '1') then
if (s_port_id = LEDS_ID) then
r_LEDS <= s_output_port;
elsif (s_port_id = SEGMENTS_ID) then
r_SEGMENTS <= s_output_port;
elsif (s_port_id = DISP_EN_ID) then
r_DISP_EN <= s_output_port(3 downto 0);
end if;
end if;
end if;
end process outputs;
-------------------------------------------------------------------------------
-- Register Interface Assignments ---------------------------------------------
LEDS <= r_LEDS;
SEGMENTS <= r_SEGMENTS;
DISP_EN <= r_DISP_EN;
-------------------------------------------------------------------------------
end Behavioral;
| mit | de96de4465c867c18771ac5a5c63f5da | 0.385123 | 4.974268 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/generic/rule_006_test_input.vhd | 1 | 428 |
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
-- Violation below
entity FIFO is
generic(G_SIZE : integer := 10;
G_WIDTH : integer :=256;
G_DEPTH : integer := 32
);
port (
I_PORT1 : in std_logic := '0';
I_PORT2 : out std_logic :='1'
);
end entity FIFO;
| gpl-3.0 | ac7c3b283105b3a5d82fd9d2db10800c | 0.537383 | 3.079137 | false | false | false | false |
sahandKashani/DE1-SoC | DE0_Nano_SoC/DE0_Nano_SoC_demo/hw/hdl/DE0_Nano_SoC_top_level.vhd | 1 | 15,077 | -- #############################################################################
-- DE0_Nano_SoC_top_level.vhd
--
-- BOARD : DE0-Nano-SoC from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.0
-- Creation date : 11/06/2015
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE0_Nano_SoC_top_level is
port(
-- ADC
-- ADC_CONVST : out std_logic;
-- ADC_SCK : out std_logic;
-- ADC_SDI : out std_logic;
-- ADC_SDO : in std_logic;
-- ARDUINO
-- ARDUINO_IO : inout std_logic_vector(15 downto 0);
-- ARDUINO_RESET_N : inout std_logic;
-- CLOCK
FPGA_CLK1_50 : in std_logic;
-- FPGA_CLK2_50 : in std_logic;
-- FPGA_CLK3_50 : in std_logic;
-- KEY
KEY_N : in std_logic_vector(1 downto 0);
-- LED
LED : out std_logic_vector(7 downto 0);
-- SW
-- SW : in std_logic_vector(3 downto 0);
-- GPIO_0
-- GPIO_0 : inout std_logic_vector(35 downto 0);
-- GPIO_1
-- GPIO_1 : inout std_logic_vector(35 downto 0);
-- HPS
HPS_CONV_USB_N : inout std_logic;
HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
HPS_DDR3_BA : out std_logic_vector(2 downto 0);
HPS_DDR3_CAS_N : out std_logic;
HPS_DDR3_CK_N : out std_logic;
HPS_DDR3_CK_P : out std_logic;
HPS_DDR3_CKE : out std_logic;
HPS_DDR3_CS_N : out std_logic;
HPS_DDR3_DM : out std_logic_vector(3 downto 0);
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
HPS_DDR3_ODT : out std_logic;
HPS_DDR3_RAS_N : out std_logic;
HPS_DDR3_RESET_N : out std_logic;
HPS_DDR3_RZQ : in std_logic;
HPS_DDR3_WE_N : out std_logic;
HPS_ENET_GTX_CLK : out std_logic;
HPS_ENET_INT_N : inout std_logic;
HPS_ENET_MDC : out std_logic;
HPS_ENET_MDIO : inout std_logic;
HPS_ENET_RX_CLK : in std_logic;
HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
HPS_ENET_RX_DV : in std_logic;
HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
HPS_ENET_TX_EN : out std_logic;
HPS_GSENSOR_INT : inout std_logic;
HPS_I2C0_SCLK : inout std_logic;
HPS_I2C0_SDAT : inout std_logic;
HPS_I2C1_SCLK : inout std_logic;
HPS_I2C1_SDAT : inout std_logic;
HPS_KEY_N : inout std_logic;
HPS_LED : inout std_logic;
HPS_LTC_GPIO : inout std_logic;
HPS_SD_CLK : out std_logic;
HPS_SD_CMD : inout std_logic;
HPS_SD_DATA : inout std_logic_vector(3 downto 0);
HPS_SPIM_CLK : out std_logic;
HPS_SPIM_MISO : in std_logic;
HPS_SPIM_MOSI : out std_logic;
HPS_SPIM_SS : inout std_logic;
HPS_UART_RX : in std_logic;
HPS_UART_TX : out std_logic;
HPS_USB_CLKOUT : in std_logic;
HPS_USB_DATA : inout std_logic_vector(7 downto 0);
HPS_USB_DIR : in std_logic;
HPS_USB_NXT : in std_logic;
HPS_USB_STP : out std_logic
);
end entity DE0_Nano_SoC_top_level;
architecture rtl of DE0_Nano_SoC_top_level is
component soc_system is
port(
clk_clk : in std_logic := 'X';
hps_0_ddr_mem_a : out std_logic_vector(14 downto 0);
hps_0_ddr_mem_ba : out std_logic_vector(2 downto 0);
hps_0_ddr_mem_ck : out std_logic;
hps_0_ddr_mem_ck_n : out std_logic;
hps_0_ddr_mem_cke : out std_logic;
hps_0_ddr_mem_cs_n : out std_logic;
hps_0_ddr_mem_ras_n : out std_logic;
hps_0_ddr_mem_cas_n : out std_logic;
hps_0_ddr_mem_we_n : out std_logic;
hps_0_ddr_mem_reset_n : out std_logic;
hps_0_ddr_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X');
hps_0_ddr_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X');
hps_0_ddr_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X');
hps_0_ddr_mem_odt : out std_logic;
hps_0_ddr_mem_dm : out std_logic_vector(3 downto 0);
hps_0_ddr_oct_rzqin : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_TX_CLK : out std_logic;
hps_0_io_hps_io_emac1_inst_TX_CTL : out std_logic;
hps_0_io_hps_io_emac1_inst_TXD0 : out std_logic;
hps_0_io_hps_io_emac1_inst_TXD1 : out std_logic;
hps_0_io_hps_io_emac1_inst_TXD2 : out std_logic;
hps_0_io_hps_io_emac1_inst_TXD3 : out std_logic;
hps_0_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X';
hps_0_io_hps_io_emac1_inst_MDC : out std_logic;
hps_0_io_hps_io_sdio_inst_CLK : out std_logic;
hps_0_io_hps_io_sdio_inst_CMD : inout std_logic := 'X';
hps_0_io_hps_io_sdio_inst_D0 : inout std_logic := 'X';
hps_0_io_hps_io_sdio_inst_D1 : inout std_logic := 'X';
hps_0_io_hps_io_sdio_inst_D2 : inout std_logic := 'X';
hps_0_io_hps_io_sdio_inst_D3 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_CLK : in std_logic := 'X';
hps_0_io_hps_io_usb1_inst_STP : out std_logic;
hps_0_io_hps_io_usb1_inst_DIR : in std_logic := 'X';
hps_0_io_hps_io_usb1_inst_NXT : in std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D0 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D1 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D2 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D3 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D4 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D5 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D6 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D7 : inout std_logic := 'X';
hps_0_io_hps_io_spim1_inst_CLK : out std_logic;
hps_0_io_hps_io_spim1_inst_MOSI : out std_logic;
hps_0_io_hps_io_spim1_inst_MISO : in std_logic := 'X';
hps_0_io_hps_io_spim1_inst_SS0 : out std_logic;
hps_0_io_hps_io_uart0_inst_RX : in std_logic := 'X';
hps_0_io_hps_io_uart0_inst_TX : out std_logic;
hps_0_io_hps_io_i2c0_inst_SDA : inout std_logic := 'X';
hps_0_io_hps_io_i2c0_inst_SCL : inout std_logic := 'X';
hps_0_io_hps_io_i2c1_inst_SDA : inout std_logic := 'X';
hps_0_io_hps_io_i2c1_inst_SCL : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO09 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO35 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO40 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO54 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO61 : inout std_logic := 'X';
hps_fpga_leds_external_connection_export : out std_logic_vector(3 downto 0);
nios_leds_external_connection_export : out std_logic_vector(3 downto 0);
reset_reset_n : in std_logic := 'X'
);
end component soc_system;
begin
soc_system_inst : component soc_system
port map(
clk_clk => FPGA_CLK1_50,
hps_0_ddr_mem_a => HPS_DDR3_ADDR,
hps_0_ddr_mem_ba => HPS_DDR3_BA,
hps_0_ddr_mem_ck => HPS_DDR3_CK_P,
hps_0_ddr_mem_ck_n => HPS_DDR3_CK_N,
hps_0_ddr_mem_cke => HPS_DDR3_CKE,
hps_0_ddr_mem_cs_n => HPS_DDR3_CS_N,
hps_0_ddr_mem_ras_n => HPS_DDR3_RAS_N,
hps_0_ddr_mem_cas_n => HPS_DDR3_CAS_N,
hps_0_ddr_mem_we_n => HPS_DDR3_WE_N,
hps_0_ddr_mem_reset_n => HPS_DDR3_RESET_N,
hps_0_ddr_mem_dq => HPS_DDR3_DQ,
hps_0_ddr_mem_dqs => HPS_DDR3_DQS_P,
hps_0_ddr_mem_dqs_n => HPS_DDR3_DQS_N,
hps_0_ddr_mem_odt => HPS_DDR3_ODT,
hps_0_ddr_mem_dm => HPS_DDR3_DM,
hps_0_ddr_oct_rzqin => HPS_DDR3_RZQ,
hps_0_io_hps_io_emac1_inst_TX_CLK => HPS_ENET_GTX_CLK,
hps_0_io_hps_io_emac1_inst_TX_CTL => HPS_ENET_TX_EN,
hps_0_io_hps_io_emac1_inst_TXD0 => HPS_ENET_TX_DATA(0),
hps_0_io_hps_io_emac1_inst_TXD1 => HPS_ENET_TX_DATA(1),
hps_0_io_hps_io_emac1_inst_TXD2 => HPS_ENET_TX_DATA(2),
hps_0_io_hps_io_emac1_inst_TXD3 => HPS_ENET_TX_DATA(3),
hps_0_io_hps_io_emac1_inst_RX_CLK => HPS_ENET_RX_CLK,
hps_0_io_hps_io_emac1_inst_RX_CTL => HPS_ENET_RX_DV,
hps_0_io_hps_io_emac1_inst_RXD0 => HPS_ENET_RX_DATA(0),
hps_0_io_hps_io_emac1_inst_RXD1 => HPS_ENET_RX_DATA(1),
hps_0_io_hps_io_emac1_inst_RXD2 => HPS_ENET_RX_DATA(2),
hps_0_io_hps_io_emac1_inst_RXD3 => HPS_ENET_RX_DATA(3),
hps_0_io_hps_io_emac1_inst_MDIO => HPS_ENET_MDIO,
hps_0_io_hps_io_emac1_inst_MDC => HPS_ENET_MDC,
hps_0_io_hps_io_sdio_inst_CLK => HPS_SD_CLK,
hps_0_io_hps_io_sdio_inst_CMD => HPS_SD_CMD,
hps_0_io_hps_io_sdio_inst_D0 => HPS_SD_DATA(0),
hps_0_io_hps_io_sdio_inst_D1 => HPS_SD_DATA(1),
hps_0_io_hps_io_sdio_inst_D2 => HPS_SD_DATA(2),
hps_0_io_hps_io_sdio_inst_D3 => HPS_SD_DATA(3),
hps_0_io_hps_io_usb1_inst_CLK => HPS_USB_CLKOUT,
hps_0_io_hps_io_usb1_inst_STP => HPS_USB_STP,
hps_0_io_hps_io_usb1_inst_DIR => HPS_USB_DIR,
hps_0_io_hps_io_usb1_inst_NXT => HPS_USB_NXT,
hps_0_io_hps_io_usb1_inst_D0 => HPS_USB_DATA(0),
hps_0_io_hps_io_usb1_inst_D1 => HPS_USB_DATA(1),
hps_0_io_hps_io_usb1_inst_D2 => HPS_USB_DATA(2),
hps_0_io_hps_io_usb1_inst_D3 => HPS_USB_DATA(3),
hps_0_io_hps_io_usb1_inst_D4 => HPS_USB_DATA(4),
hps_0_io_hps_io_usb1_inst_D5 => HPS_USB_DATA(5),
hps_0_io_hps_io_usb1_inst_D6 => HPS_USB_DATA(6),
hps_0_io_hps_io_usb1_inst_D7 => HPS_USB_DATA(7),
hps_0_io_hps_io_spim1_inst_CLK => HPS_SPIM_CLK,
hps_0_io_hps_io_spim1_inst_MOSI => HPS_SPIM_MOSI,
hps_0_io_hps_io_spim1_inst_MISO => HPS_SPIM_MISO,
hps_0_io_hps_io_spim1_inst_SS0 => HPS_SPIM_SS,
hps_0_io_hps_io_uart0_inst_RX => HPS_UART_RX,
hps_0_io_hps_io_uart0_inst_TX => HPS_UART_TX,
hps_0_io_hps_io_i2c0_inst_SDA => HPS_I2C0_SDAT,
hps_0_io_hps_io_i2c0_inst_SCL => HPS_I2C0_SCLK,
hps_0_io_hps_io_i2c1_inst_SDA => HPS_I2C1_SDAT,
hps_0_io_hps_io_i2c1_inst_SCL => HPS_I2C1_SCLK,
hps_0_io_hps_io_gpio_inst_GPIO09 => HPS_CONV_USB_N,
hps_0_io_hps_io_gpio_inst_GPIO35 => HPS_ENET_INT_N,
hps_0_io_hps_io_gpio_inst_GPIO40 => HPS_LTC_GPIO,
hps_0_io_hps_io_gpio_inst_GPIO53 => HPS_LED,
hps_0_io_hps_io_gpio_inst_GPIO54 => HPS_KEY_N,
hps_0_io_hps_io_gpio_inst_GPIO61 => HPS_GSENSOR_INT,
hps_fpga_leds_external_connection_export => LED(7 downto 4),
nios_leds_external_connection_export => LED(3 downto 0),
reset_reset_n => KEY_N(0)
);
end;
| unlicense | e3d77790e2d9593b99d6988ad468a02a | 0.431784 | 3.15881 | false | false | false | false |
Yarr/Yarr-fw | rtl/kintex7/wbexp-core/gn4124_core_pkg.vhd | 1 | 4,964 | --==============================================================================
--! @file gn4124_core_pkg_s6.vhd
--==============================================================================
--! Standard library
library IEEE;
--! Standard packages
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Package for gn4124 core
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--! @brief
--! Package for components declaration and core wide constants.
--! Spartan6 FPGAs version.
--------------------------------------------------------------------------------
--! @version
--! 0.1 | mc | 01.09.2010 | File creation and Doxygen comments
--!
--! @author
--! mc : Matthieu Cattin, CERN (BE-CO-HT)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
--==============================================================================
--! Package declaration
--==============================================================================
package gn4124_core_pkg is
--==============================================================================
--! Constants declaration
--==============================================================================
constant c_RST_ACTIVE : std_logic := '0';
--==============================================================================
--! Functions declaration
--==============================================================================
function f_byte_swap (
constant enable : boolean;
signal din : std_logic_vector(31 downto 0);
signal byte_swap : std_logic_vector(1 downto 0))
return std_logic_vector;
function log2_ceil(N : natural) return positive;
--==============================================================================
--! Components declaration
--==============================================================================
end gn4124_core_pkg;
package body gn4124_core_pkg is
-----------------------------------------------------------------------------
-- Byte swap function
--
-- enable | byte_swap | din | dout
-- false | XX | ABCD | ABCD
-- true | 00 | ABCD | ABCD
-- true | 01 | ABCD | BADC
-- true | 10 | ABCD | CDAB
-- true | 11 | ABCD | DCBA
-----------------------------------------------------------------------------
function f_byte_swap (
constant enable : boolean;
signal din : std_logic_vector(31 downto 0);
signal byte_swap : std_logic_vector(1 downto 0))
return std_logic_vector is
variable dout : std_logic_vector(31 downto 0) := din;
begin
if (enable = true) then
case byte_swap is
when "00" =>
dout := din;
when "01" =>
dout := din(23 downto 16)
& din(31 downto 24)
& din(7 downto 0)
& din(15 downto 8);
when "10" =>
dout := din(15 downto 0)
& din(31 downto 16);
when "11" =>
dout := din(7 downto 0)
& din(15 downto 8)
& din(23 downto 16)
& din(31 downto 24);
when others =>
dout := din;
end case;
else
dout := din;
end if;
return dout;
end function f_byte_swap;
-----------------------------------------------------------------------------
-- Returns log of 2 of a natural number
-----------------------------------------------------------------------------
function log2_ceil(N : natural) return positive is
begin
if N <= 2 then
return 1;
elsif N mod 2 = 0 then
return 1 + log2_ceil(N/2);
else
return 1 + log2_ceil((N+1)/2);
end if;
end;
end gn4124_core_pkg;
| gpl-3.0 | 586303cc026fea92e58475c0b4308ce3 | 0.379734 | 5.660205 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_dma_v7_1/hdl/src/vhdl/axi_dma_s2mm_sm.vhd | 1 | 50,863 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_sm.vhd
-- Description: This entity contains the S2MM DMA Controller State Machine
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_sm is
generic (
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Width of Buffer Length, Transferred Bytes, and BTT fields
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1
-- Depth of DataMover command FIFO
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
s2mm_stop : in std_logic ; --
--
-- S2MM Control and Status --
s2mm_run_stop : in std_logic ; --
s2mm_keyhole : in std_logic ; --
s2mm_ftch_idle : in std_logic ; --
s2mm_desc_flush : in std_logic ; --
s2mm_cmnd_idle : out std_logic ; --
s2mm_sts_idle : out std_logic ; --
s2mm_eof_set : out std_logic ; --
s2mm_eof_micro : in std_logic ; --
s2mm_sof_micro : in std_logic ; --
--
-- S2MM Descriptor Fetch Request --
desc_fetch_req : out std_logic ; --
desc_fetch_done : in std_logic ; --
desc_update_done : in std_logic ; --
updt_pending : in std_logic ;
desc_available : in std_logic ; --
--
-- S2MM Status Stream RX Length --
s2mm_rxlength_valid : in std_logic ; --
s2mm_rxlength_clr : out std_logic ; --
s2mm_rxlength : in std_logic_vector --
(C_SG_LENGTH_WIDTH - 1 downto 0) ; --
--
-- DataMover Command --
s2mm_cmnd_wr : out std_logic ; --
s2mm_cmnd_data : out std_logic_vector --
((2*C_M_AXI_S2MM_ADDR_WIDTH+CMD_BASE_WIDTH+46)-1 downto 0); --
s2mm_cmnd_pending : in std_logic ; --
--
-- Descriptor Fields --
s2mm_desc_info : in std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
s2mm_desc_baddress : in std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
s2mm_desc_blength : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0); --
s2mm_desc_blength_v : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0); --
s2mm_desc_blength_s : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) --
);
end axi_dma_s2mm_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Commmand TAG
constant S2MM_CMD_TAG : std_logic_vector(2 downto 0) := (others => '0');
-- DataMover Command Destination Stream Offset
constant S2MM_CMD_DSA : std_logic_vector(5 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant S2MM_CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_S2MM_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_S2MM_ADDR_WIDTH)
:= (others => '0');
-- Queued commands counter width
constant COUNTER_WIDTH : integer := clog2(C_PRMY_CMDFIFO_DEPTH+1);
-- Queued commands zero count
constant ZERO_COUNT : std_logic_vector(COUNTER_WIDTH - 1 downto 0)
:= (others => '0');
-- Zero buffer length error - compare value
constant ZERO_LENGTH : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0)
:= (others => '0');
constant ZERO_BUFFER : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- State Machine Signals
signal desc_fetch_req_cmb : std_logic := '0';
signal write_cmnd_cmb : std_logic := '0';
signal s2mm_rxlength_clr_cmb : std_logic := '0';
signal rxlength : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_rxlength_set : std_logic := '0';
signal blength_grtr_rxlength : std_logic := '0';
signal rxlength_fetched : std_logic := '0';
signal cmnds_queued : std_logic_vector(COUNTER_WIDTH - 1 downto 0) := (others => '0');
signal cmnds_queued_shift : std_logic_vector(C_PRMY_CMDFIFO_DEPTH - 1 downto 0) := (others => '0');
signal count_incr : std_logic := '0';
signal count_decr : std_logic := '0';
signal desc_fetch_done_d1 : std_logic := '0';
signal zero_length_error : std_logic := '0';
signal s2mm_eof_set_i : std_logic := '0';
signal queue_more : std_logic := '0';
signal burst_type : std_logic;
signal eof_micro : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
EN_MICRO_DMA : if C_MICRO_DMA = 1 generate
begin
eof_micro <= s2mm_eof_micro;
end generate EN_MICRO_DMA;
NO_MICRO_DMA : if C_MICRO_DMA = 0 generate
begin
eof_micro <= '0';
end generate NO_MICRO_DMA;
s2mm_eof_set <= s2mm_eof_set_i;
burst_type <= '1' and (not s2mm_keyhole);
-- A 0 s2mm_keyhole means incremental burst
-- a 1 s2mm_keyhole means fixed burst
-------------------------------------------------------------------------------
-- Not using rx length from status stream - (indeterminate length mode)
-------------------------------------------------------------------------------
GEN_SM_FOR_NO_LENGTH : if (C_SG_USE_STSAPP_LENGTH = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_ENABLE_MULTI_CHANNEL = 1) generate
type SG_S2MM_STATE_TYPE is (
IDLE,
FETCH_DESCRIPTOR,
-- EXECUTE_XFER,
WAIT_STATUS
);
signal s2mm_cs : SG_S2MM_STATE_TYPE;
signal s2mm_ns : SG_S2MM_STATE_TYPE;
begin
-- For no status stream or not using length in status app field then eof set is
-- generated from datamover status (see axi_dma_s2mm_cmdsts_if.vhd)
s2mm_eof_set_i <= '0';
-------------------------------------------------------------------------------
-- S2MM Transfer State Machine
-------------------------------------------------------------------------------
S2MM_MACHINE : process(s2mm_cs,
s2mm_run_stop,
desc_available,
desc_fetch_done,
desc_update_done,
s2mm_cmnd_pending,
s2mm_stop,
s2mm_desc_flush,
updt_pending
-- queue_more
)
begin
-- Default signal assignment
desc_fetch_req_cmb <= '0';
write_cmnd_cmb <= '0';
s2mm_cmnd_idle <= '0';
s2mm_ns <= s2mm_cs;
case s2mm_cs is
-------------------------------------------------------------------
when IDLE =>
-- fetch descriptor if desc available, not stopped and running
-- if (updt_pending = '1') then
-- s2mm_ns <= WAIT_STATUS;
if(s2mm_run_stop = '1' and desc_available = '1'
-- and s2mm_stop = '0' and queue_more = '1' and updt_pending = '0')then
and s2mm_stop = '0' and updt_pending = '0')then
if (C_SG_INCLUDE_DESC_QUEUE = 1) then
s2mm_ns <= FETCH_DESCRIPTOR;
desc_fetch_req_cmb <= '1';
else
s2mm_ns <= WAIT_STATUS;
write_cmnd_cmb <= '1';
end if;
else
s2mm_cmnd_idle <= '1';
s2mm_ns <= IDLE;
end if;
-------------------------------------------------------------------
when FETCH_DESCRIPTOR =>
-- exit if error or descriptor flushed
if(s2mm_desc_flush = '1' or s2mm_stop = '1')then
s2mm_ns <= IDLE;
-- wait until fetch complete then execute
-- elsif(desc_fetch_done = '1')then
-- desc_fetch_req_cmb <= '0';
-- s2mm_ns <= EXECUTE_XFER;
elsif (s2mm_cmnd_pending = '0')then
desc_fetch_req_cmb <= '0';
if (updt_pending = '0') then
if(C_SG_INCLUDE_DESC_QUEUE = 1)then
s2mm_ns <= IDLE;
write_cmnd_cmb <= '1';
else
s2mm_ns <= WAIT_STATUS;
end if;
end if;
else
s2mm_ns <= FETCH_DESCRIPTOR;
end if;
-------------------------------------------------------------------
-- when EXECUTE_XFER =>
-- -- if error exit
-- if(s2mm_stop = '1')then
-- s2mm_ns <= IDLE;
-- -- Write another command if there is not one already pending
-- elsif(s2mm_cmnd_pending = '0')then
-- if (updt_pending = '0') then
-- write_cmnd_cmb <= '1';
-- end if;
-- if(C_SG_INCLUDE_DESC_QUEUE = 1)then
-- s2mm_ns <= IDLE;
-- else
-- s2mm_ns <= WAIT_STATUS;
-- end if;
-- else
-- s2mm_ns <= EXECUTE_XFER;
-- end if;
-------------------------------------------------------------------
when WAIT_STATUS =>
-- for no Q wait until desc updated
if(desc_update_done = '1' or s2mm_stop = '1')then
s2mm_ns <= IDLE;
else
s2mm_ns <= WAIT_STATUS;
end if;
-------------------------------------------------------------------
-- coverage off
when others =>
s2mm_ns <= IDLE;
-- coverage on
end case;
end process S2MM_MACHINE;
-------------------------------------------------------------------------------
-- Register State Machine Statues
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_cs <= IDLE;
else
s2mm_cs <= s2mm_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- Register State Machine Signalse
-------------------------------------------------------------------------------
-- SM_SIG_REGISTER : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- desc_fetch_req <= '0' ;
-- else
-- if (C_SG_INCLUDE_DESC_QUEUE = 0) then
-- desc_fetch_req <= '1';
-- else
-- desc_fetch_req <= desc_fetch_req_cmb ;
-- end if;
-- end if;
-- end if;
-- end process SM_SIG_REGISTER;
desc_fetch_req <= '1' when (C_SG_INCLUDE_DESC_QUEUE = 0) else
desc_fetch_req_cmb ;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- If Bytes To Transfer (BTT) width less than 23, need to add pad
GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
-- When command by sm, drive command to s2mm_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_cmnd_wr <= '0';
-- s2mm_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
elsif(write_cmnd_cmb = '1')then
s2mm_cmnd_wr <= '1';
-- s2mm_cmnd_data <= s2mm_desc_info
-- & s2mm_desc_blength_v
-- & s2mm_desc_blength_s
-- & S2MM_CMD_RSVD
-- & "0000" -- Cat IOC to CMD TAG
-- & s2mm_desc_baddress
-- & '1' -- Always reset DRE
-- & '0' -- For Indeterminate BTT mode do not set EOF
-- & S2MM_CMD_DSA
-- & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
-- & PAD_VALUE
-- & s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
else
s2mm_cmnd_wr <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
s2mm_cmnd_data <= s2mm_desc_info
& s2mm_desc_blength_v
& s2mm_desc_blength_s
& S2MM_CMD_RSVD
& "00" & eof_micro & eof_micro --00" -- Cat IOC to CMD TAG
& s2mm_desc_baddress
& '1' -- Always reset DRE
& eof_micro --'0' -- For Indeterminate BTT mode do not set EOF
& S2MM_CMD_DSA
& burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
& PAD_VALUE
& s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
end generate GEN_CMD_BTT_LESS_23;
-- If Bytes To Transfer (BTT) width equal 23, no required pad
GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate
begin
-- When command by sm, drive command to s2mm_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_cmnd_wr <= '0';
-- s2mm_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
elsif(write_cmnd_cmb = '1')then
s2mm_cmnd_wr <= '1';
-- s2mm_cmnd_data <= s2mm_desc_info
-- & s2mm_desc_blength_v
-- & s2mm_desc_blength_s
-- & S2MM_CMD_RSVD
-- & "0000" -- Cat IOC to CMD TAG
-- & s2mm_desc_baddress
-- & '1' -- Always reset DRE
-- & '0' -- For indeterminate BTT mode do not set EOF
-- & S2MM_CMD_DSA
-- & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
-- & s2mm_desc_blength;
else
s2mm_cmnd_wr <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
s2mm_cmnd_data <= s2mm_desc_info
& s2mm_desc_blength_v
& s2mm_desc_blength_s
& S2MM_CMD_RSVD
& "00" & eof_micro & eof_micro -- "0000" -- Cat IOC to CMD TAG
& s2mm_desc_baddress
& '1' -- Always reset DRE
& eof_micro -- For indeterminate BTT mode do not set EOF
& S2MM_CMD_DSA
& burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
& s2mm_desc_blength;
end generate GEN_CMD_BTT_EQL_23;
-- Drive unused output to zero
s2mm_rxlength_clr <= '0';
end generate GEN_SM_FOR_NO_LENGTH;
-------------------------------------------------------------------------------
-- Generate state machine and support logic for Using RX Length from Status
-- Stream
-------------------------------------------------------------------------------
-- this would not hold good for MCDMA
GEN_SM_FOR_LENGTH : if (C_SG_USE_STSAPP_LENGTH = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate
type SG_S2MM_STATE_TYPE is (
IDLE,
FETCH_DESCRIPTOR,
GET_RXLENGTH,
CMPR_LENGTH,
EXECUTE_XFER,
WAIT_STATUS
);
signal s2mm_cs : SG_S2MM_STATE_TYPE;
signal s2mm_ns : SG_S2MM_STATE_TYPE;
begin
-------------------------------------------------------------------------------
-- S2MM Transfer State Machine
-------------------------------------------------------------------------------
S2MM_MACHINE : process(s2mm_cs,
s2mm_run_stop,
desc_available,
desc_update_done,
-- desc_fetch_done,
updt_pending,
s2mm_rxlength_valid,
rxlength_fetched,
s2mm_cmnd_pending,
zero_length_error,
s2mm_stop,
s2mm_desc_flush
-- queue_more
)
begin
-- Default signal assignment
desc_fetch_req_cmb <= '0';
s2mm_rxlength_clr_cmb <= '0';
write_cmnd_cmb <= '0';
s2mm_cmnd_idle <= '0';
s2mm_rxlength_set <= '0';
--rxlength_fetched_clr <= '0';
s2mm_ns <= s2mm_cs;
case s2mm_cs is
-------------------------------------------------------------------
when IDLE =>
if(s2mm_run_stop = '1' and desc_available = '1'
-- and s2mm_stop = '0' and queue_more = '1' and updt_pending = '0')then
and s2mm_stop = '0' and updt_pending = '0')then
if (C_SG_INCLUDE_DESC_QUEUE = 0) then
if(rxlength_fetched = '0')then
s2mm_ns <= GET_RXLENGTH;
else
s2mm_ns <= CMPR_LENGTH;
end if;
else
s2mm_ns <= FETCH_DESCRIPTOR;
desc_fetch_req_cmb <= '1';
end if;
else
s2mm_cmnd_idle <= '1';
s2mm_ns <= IDLE; --FETCH_DESCRIPTOR;
end if;
-------------------------------------------------------------------
when FETCH_DESCRIPTOR =>
desc_fetch_req_cmb <= '0';
-- exit if error or descriptor flushed
if(s2mm_desc_flush = '1')then
s2mm_ns <= IDLE;
-- Descriptor fetch complete
else --if(desc_fetch_done = '1')then
-- desc_fetch_req_cmb <= '0';
if(rxlength_fetched = '0')then
s2mm_ns <= GET_RXLENGTH;
else
s2mm_ns <= CMPR_LENGTH;
end if;
-- else
-- desc_fetch_req_cmb <= '1';
end if;
-------------------------------------------------------------------
WHEN GET_RXLENGTH =>
if(s2mm_stop = '1')then
s2mm_ns <= IDLE;
-- Buffer length zero, do not compare lengths, execute
-- command to force datamover to issue interror
elsif(zero_length_error = '1')then
s2mm_ns <= EXECUTE_XFER;
elsif(s2mm_rxlength_valid = '1')then
s2mm_rxlength_set <= '1';
s2mm_rxlength_clr_cmb <= '1';
s2mm_ns <= CMPR_LENGTH;
else
s2mm_ns <= GET_RXLENGTH;
end if;
-------------------------------------------------------------------
WHEN CMPR_LENGTH =>
s2mm_ns <= EXECUTE_XFER;
-------------------------------------------------------------------
when EXECUTE_XFER =>
if(s2mm_stop = '1')then
s2mm_ns <= IDLE;
-- write new command if one is not already pending
elsif(s2mm_cmnd_pending = '0')then
write_cmnd_cmb <= '1';
-- If descriptor queuing enabled then
-- do NOT need to wait for status
if(C_SG_INCLUDE_DESC_QUEUE = 1)then
s2mm_ns <= IDLE;
-- No queuing therefore must wait for
-- status before issuing next command
else
s2mm_ns <= WAIT_STATUS;
end if;
else
s2mm_ns <= EXECUTE_XFER;
end if;
-------------------------------------------------------------------
when WAIT_STATUS =>
if(desc_update_done = '1' or s2mm_stop = '1')then
s2mm_ns <= IDLE;
else
s2mm_ns <= WAIT_STATUS;
end if;
-------------------------------------------------------------------
-- coverage off
when others =>
s2mm_ns <= IDLE;
-- coverage on
end case;
end process S2MM_MACHINE;
-------------------------------------------------------------------------------
-- Register state machine states
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_cs <= IDLE;
else
s2mm_cs <= s2mm_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- Register state machine signals
-------------------------------------------------------------------------------
SM_SIG_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_fetch_req <= '0' ;
s2mm_rxlength_clr <= '0' ;
else
if (C_SG_INCLUDE_DESC_QUEUE = 0) then
desc_fetch_req <= '1';
else
desc_fetch_req <= desc_fetch_req_cmb ;
end if;
s2mm_rxlength_clr <= s2mm_rxlength_clr_cmb;
end if;
end if;
end process SM_SIG_REGISTER;
-------------------------------------------------------------------------------
-- Check for a ZERO value in descriptor buffer length. If there is
-- then flag an error and skip waiting for valid rxlength. cmnd will
-- get written to datamover with BTT=0 and datamover will flag dmaint error
-- which will be logged in desc, reset required to clear error
-------------------------------------------------------------------------------
REG_ALIGN_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_fetch_done_d1 <= '0';
else
desc_fetch_done_d1 <= desc_fetch_done;
end if;
end if;
end process REG_ALIGN_DONE;
-------------------------------------------------------------------------------
-- Zero length error detection - for determinate mode, detect early to prevent
-- rxlength calcuation from first taking place. This will force a 0 BTT
-- command to be issued to the datamover causing an internal error.
-------------------------------------------------------------------------------
REG_ZERO_LNGTH_ERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
zero_length_error <= '0';
elsif(desc_fetch_done_d1 = '1'
and s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0) = ZERO_LENGTH)then
zero_length_error <= '1';
end if;
end if;
end process REG_ZERO_LNGTH_ERR;
-------------------------------------------------------------------------------
-- Capture/Hold receive length from status stream. Also decrement length
-- based on if received length is greater than descriptor buffer size. (i.e. is
-- the case where multiple descriptors/buffers are used to describe one packet)
-------------------------------------------------------------------------------
REG_RXLENGTH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
rxlength <= (others => '0');
-- If command register rxlength from status stream fifo
elsif(s2mm_rxlength_set = '1')then
rxlength <= s2mm_rxlength;
-- On command write if current desc buffer size not greater
-- than current rxlength then decrement rxlength in preperations
-- for subsequent commands
elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '0')then
rxlength <= std_logic_vector(unsigned(rxlength(C_SG_LENGTH_WIDTH-1 downto 0))
- unsigned(s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0)));
end if;
end if;
end process REG_RXLENGTH;
-------------------------------------------------------------------------------
-- Calculate if Descriptor Buffer Length is 'Greater Than' or 'Equal To'
-- Received Length value
-------------------------------------------------------------------------------
REG_BLENGTH_GRTR_RXLNGTH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
blength_grtr_rxlength <= '0';
elsif(s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0) >= rxlength)then
blength_grtr_rxlength <= '1';
else
blength_grtr_rxlength <= '0';
end if;
end if;
end process REG_BLENGTH_GRTR_RXLNGTH;
-------------------------------------------------------------------------------
-- On command assert rxlength fetched flag indicating length grabbed from
-- status stream fifo
-------------------------------------------------------------------------------
RXLENGTH_FTCHED_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_eof_set_i = '1')then
rxlength_fetched <= '0';
elsif(s2mm_rxlength_set = '1')then
rxlength_fetched <= '1';
end if;
end if;
end process RXLENGTH_FTCHED_PROCESS;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- If Bytes To Transfer (BTT) width less than 23, need to add pad
GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
-- When command by sm, drive command to s2mm_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_cmnd_wr <= '0';
s2mm_cmnd_data <= (others => '0');
s2mm_eof_set_i <= '0';
-- Current Desc Buffer will NOT hold entire rxlength of data therefore
-- set EOF = based on Desc.EOF and pass buffer length for BTT
elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '0')then
s2mm_cmnd_wr <= '1';
s2mm_cmnd_data <= s2mm_desc_info
& ZERO_BUFFER
& ZERO_BUFFER
& S2MM_CMD_RSVD
-- Command Tag
& '0'
& '0'
& '0' -- Cat. EOF=0 to CMD Tag
& '0' -- Cat. IOC to CMD TAG
-- Command
& s2mm_desc_baddress
& '1' -- Always reset DRE
& '0' -- Not End of Frame
& S2MM_CMD_DSA
& burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
& PAD_VALUE
& s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
s2mm_eof_set_i <= '0';
-- Current Desc Buffer will hold entire rxlength of data therefore
-- set EOF = 1 and pass rxlength for BTT
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in s2mm_sg_if.
elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '1')then
s2mm_cmnd_wr <= '1';
s2mm_cmnd_data <= s2mm_desc_info
& ZERO_BUFFER
& ZERO_BUFFER
& S2MM_CMD_RSVD
-- Command Tag
& '0'
& '0'
& '1' -- Cat. EOF=1 to CMD Tag
& '1' -- Cat. IOC to CMD TAG
-- Command
& s2mm_desc_baddress
& '1' -- Always reset DRE
& '1' -- Set EOF=1
& S2MM_CMD_DSA
& burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
& PAD_VALUE
& rxlength;
s2mm_eof_set_i <= '1';
else
-- s2mm_cmnd_data <= (others => '0');
s2mm_cmnd_wr <= '0';
s2mm_eof_set_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_CMD_BTT_LESS_23;
-- If Bytes To Transfer (BTT) width equal 23, no required pad
GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate
begin
-- When command by sm, drive command to s2mm_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_cmnd_wr <= '0';
s2mm_cmnd_data <= (others => '0');
s2mm_eof_set_i <= '0';
-- Current Desc Buffer will NOT hold entire rxlength of data therefore
-- set EOF = based on Desc.EOF and pass buffer length for BTT
elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '0')then
s2mm_cmnd_wr <= '1';
s2mm_cmnd_data <= s2mm_desc_info
& ZERO_BUFFER
& ZERO_BUFFER
& S2MM_CMD_RSVD
--& S2MM_CMD_TAG & s2mm_desc_ioc -- Cat IOC to CMD TAG
-- Command Tag
& '0'
& '0'
& '0' -- Cat. EOF='0' to CMD Tag
& '0' -- Cat. IOC='0' to CMD TAG
-- Command
& s2mm_desc_baddress
& '1' -- Always reset DRE
& '0' -- Not End of Frame
& S2MM_CMD_DSA
& burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
& s2mm_desc_blength;
s2mm_eof_set_i <= '0';
-- Current Desc Buffer will hold entire rxlength of data therefore
-- set EOF = 1 and pass rxlength for BTT
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in s2mm_sg_if.
elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '1')then
s2mm_cmnd_wr <= '1';
s2mm_cmnd_data <= s2mm_desc_info
& ZERO_BUFFER
& ZERO_BUFFER
& S2MM_CMD_RSVD
--& S2MM_CMD_TAG & s2mm_desc_ioc -- Cat IOC to CMD TAG
-- Command Tag
& '0'
& '0'
& '1' -- Cat. EOF='1' to CMD Tag
& '1' -- Cat. IOC='1' to CMD TAG
-- Command
& s2mm_desc_baddress
& '1' -- Always reset DRE
& '1' -- End of Frame
& S2MM_CMD_DSA
& burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
& rxlength;
s2mm_eof_set_i <= '1';
else
-- s2mm_cmnd_data <= (others => '0');
s2mm_cmnd_wr <= '0';
s2mm_eof_set_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_CMD_BTT_EQL_23;
end generate GEN_SM_FOR_LENGTH;
-------------------------------------------------------------------------------
-- Counter for keepting track of pending commands/status in primary datamover
-- Use this to determine if primary datamover for s2mm is Idle.
-------------------------------------------------------------------------------
-- Increment queue count for each command written if not occuring at
-- same time a status from DM being updated to SG engine
count_incr <= '1' when write_cmnd_cmb = '1' and desc_update_done = '0'
else '0';
-- Decrement queue count for each status update to SG engine if not occuring
-- at same time as command being written to DM
count_decr <= '1' when write_cmnd_cmb = '0' and desc_update_done = '1'
else '0';
-- keep track of number queue commands
--CMD2STS_COUNTER : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0' or s2mm_stop = '1')then
-- cmnds_queued <= (others => '0');
-- elsif(count_incr = '1')then
-- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) + 1);
-- elsif(count_decr = '1')then
-- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) - 1);
-- end if;
-- end if;
-- end process CMD2STS_COUNTER;
QUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
begin
CMD2STS_COUNTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_stop = '1')then
cmnds_queued_shift <= (others => '0');
elsif(count_incr = '1')then
cmnds_queued_shift <= cmnds_queued_shift (2 downto 0) & '1';
elsif(count_decr = '1')then
cmnds_queued_shift <= '0' & cmnds_queued_shift (3 downto 1);
end if;
end if;
end process CMD2STS_COUNTER1;
end generate QUEUE_COUNT;
NOQUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
CMD2STS_COUNTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_stop = '1')then
cmnds_queued_shift (0) <= '0';
elsif(count_incr = '1')then
cmnds_queued_shift (0) <= '1';
elsif(count_decr = '1')then
cmnds_queued_shift (0) <= '0';
end if;
end if;
end process CMD2STS_COUNTER1;
end generate NOQUEUE_COUNT;
-- indicate idle when no more queued commands
--s2mm_sts_idle <= '1' when cmnds_queued_shift = "0000"
-- else '0';
s2mm_sts_idle <= not cmnds_queued_shift(0);
-------------------------------------------------------------------------------
-- Queue only the amount of commands that can be queued on descriptor update
-- else lock up can occur. Note datamover command fifo depth is set to number
-- of descriptors to queue.
-------------------------------------------------------------------------------
--QUEUE_MORE_PROCESS : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- queue_more <= '0';
-- elsif(cmnds_queued < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then
-- queue_more <= '1';
-- else
-- queue_more <= '0';
-- end if;
-- end if;
-- end process QUEUE_MORE_PROCESS;
QUEUE_MORE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
queue_more <= '0';
-- elsif(cmnds_queued < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then
-- queue_more <= '1';
else
queue_more <= not (cmnds_queued_shift (C_PRMY_CMDFIFO_DEPTH-1)); --'0';
end if;
end if;
end process QUEUE_MORE_PROCESS;
end implementation;
| bsd-2-clause | eead9ed0f1cb29ddf265260a92f676c2 | 0.376207 | 4.90293 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_bram_ctrl_0_0/sim/daala_zynq_axi_bram_ctrl_0_0.vhd | 1 | 16,729 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:3.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v3_0;
USE axi_bram_ctrl_v3_0.axi_bram_ctrl;
ENTITY daala_zynq_axi_bram_ctrl_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END daala_zynq_axi_bram_ctrl_0_0;
ARCHITECTURE daala_zynq_axi_bram_ctrl_0_0_arch OF daala_zynq_axi_bram_ctrl_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF daala_zynq_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_MEMORY_DEPTH : INTEGER;
C_BRAM_INST_MODE : STRING;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_MEMORY_DEPTH => 1024,
C_BRAM_INST_MODE => "EXTERNAL",
C_BRAM_ADDR_WIDTH => 10,
C_S_AXI_ADDR_WIDTH => 13,
C_S_AXI_DATA_WIDTH => 64,
C_S_AXI_ID_WIDTH => 1,
C_S_AXI_PROTOCOL => "AXI4",
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
C_SINGLE_PORT_BRAM => 0,
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rst_a => bram_rst_a,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a,
bram_rst_b => bram_rst_b,
bram_clk_b => bram_clk_b,
bram_en_b => bram_en_b,
bram_we_b => bram_we_b,
bram_addr_b => bram_addr_b,
bram_wrdata_b => bram_wrdata_b,
bram_rddata_b => bram_rddata_b
);
END daala_zynq_axi_bram_ctrl_0_0_arch;
| bsd-2-clause | 02977610f92b95d1d18d1025308973fe | 0.673202 | 3.085393 | false | false | false | false |
Yarr/Yarr-fw | rtl/common/wb_spi.vhd | 1 | 4,531 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity wb_spi is
generic (
g_CLK_DIVIDER : positive := 10
);
port (
-- Sys Connect
wb_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
-- SPI out
scl_o : out std_logic;
sda_o : out std_logic;
sdi_i : in std_logic;
latch_o : out std_logic
);
end wb_spi;
architecture rtl of wb_spi is
signal data_word : std_logic_vector(31 downto 0);
signal sreg : std_logic_vector(31 downto 0);
signal shift_cnt : unsigned(7 downto 0);
signal wait_cnt : unsigned(7 downto 0);
signal start : std_logic;
signal busy : std_logic;
signal data_in : std_logic_vector(31 downto 0);
begin
wb_proc: process(wb_clk_i, rst_n_i)
begin
if (rst_n_i ='0') then
data_word <= (others => '0');
start <= '0';
wb_ack_o <= '0';
wb_dat_o <= (others => '0');
elsif rising_edge(wb_clk_i) then
wb_ack_o <= '0';
start <= '0';
if (wb_cyc_i = '1' and wb_stb_i = '1') then
if (wb_we_i = '1') then
case (wb_adr_i(3 downto 0)) is
when x"0" =>
data_word <= wb_dat_i;
wb_ack_o <= '1';
when x"1" =>
start <= wb_dat_i(0);
wb_ack_o <= '1';
when others =>
wb_ack_o <= '1';
end case;
else
case (wb_adr_i(3 downto 0)) is
when x"1" =>
wb_dat_o(31 downto 1) <= (others => '0');
wb_dat_o(0) <= busy;
wb_ack_o <= '1';
when x"2" =>
wb_dat_o <= data_in;
wb_ack_o <= '1';
when others =>
wb_dat_o <= x"DEADBEEF";
wb_ack_o <= '1';
end case;
end if;
end if;
end if;
end process wb_proc;
spi_proc: process(wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
busy <= '0';
shift_cnt <= (others => '0');
wait_cnt <= (others => '0');
sreg <= (others => '0');
scl_o <= '0';
sda_o <= '0';
latch_o <= '0';
data_in <= (others => '0');
elsif rising_edge(wb_clk_i) then
if (start = '1') then
sreg <= data_word;
shift_cnt <= to_unsigned(34, 8);
busy <= '1';
end if;
sda_o <= sreg(31);
latch_o <= '0';
if (shift_cnt > 2) then
if (wait_cnt = to_unsigned(g_CLK_DIVIDER, 8)) then
wait_cnt <= (others => '0');
scl_o <= '0';
sreg <= sreg(30 downto 0) & '0';
shift_cnt <= shift_cnt - 1;
data_in <= data_in(30 downto 0) & sdi_i;
elsif (wait_cnt=to_unsigned(g_CLK_DIVIDER/2, 8)) then
scl_o <= '1';
wait_cnt <= wait_cnt + 1;
else
wait_cnt <= wait_cnt + 1;
end if;
elsif (shift_cnt > 1) then
if (wait_cnt = to_unsigned(g_CLK_DIVIDER, 8)) then
wait_cnt <= (others => '0');
shift_cnt <= shift_cnt - 1;
else
wait_cnt <= wait_cnt + 1;
end if;
elsif (shift_cnt > 0) then
if (wait_cnt = to_unsigned(g_CLK_DIVIDER, 8)) then
wait_cnt <= (others => '0');
shift_cnt <= shift_cnt - 1;
latch_o <= '1';
busy <= '0';
else
wait_cnt <= wait_cnt + 1;
latch_o <= '1';
end if;
end if;
end if;
end process;
end rtl;
| gpl-3.0 | 4bf097fc176aed4e371376cd281039b7 | 0.381152 | 3.707856 | false | false | false | false |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/fir_compiler_v7_1/hdl/transpose_interpolation.vhd | 2 | 169,577 | `protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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PXyLcQ7iFrFDt/O8+r//7ipGmN6fndQgYqjBKguwa5B+1CDh9RSAVlILht2pp5umRXx/ttoZXGWb
pYIXl4eF3BUTubkCGwRn8fguG7oKSXJ4kmUfqeeFgspooYPUjNTnZiyE2YOQXkzj3uYsSGXR3LMd
quv1AOvFiEyZxcD8KNAGiKTz31h7ijVfL1ZuW4nmY9xFomdCszXtsDB8O2p9
`protect end_protected
| mit | 33a579ed2f1fcc32a6fa8d6ae52d71d5 | 0.953938 | 1.811681 | false | false | false | false |
kb3gtn/mojo_dactest | src/dac_test.vhd | 1 | 3,099 | ----------------------------------------------------------
-- DAC_TEST.VHD
--
-- Simple module to generate a cosine wave using a NCO
-- and a lookup table.
--
-- Goal is to generate a 16bit sinewave.
--
-- We will use the top N-bits as needed for each sample
-- depending on dac depth.
--
---------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.math_real.ALL;
entity dac_test is
port (
i_clk : in std_logic;
i_rst : in std_logic;
------------------------------------------
o_dac_cmode : out std_logic;
o_dac_mode : out std_logic;
o_dac_reset : out std_logic;
o_dac_sleep : out std_logic;
o_dac_clk : out std_logic;
o_dac_db : out signed(11 downto 0);
------------------------------------------
i_nco_ftw : in unsigned(31 downto 0) -- 32bit nco word
);
end entity dac_test;
architecture rtl of dac_test is
constant SAMPLE_WIDTH : integer := 12; -- 12 bit samples ( 11 downto 0 )
constant MEM_DEPTH : integer := 2**SAMPLE_WIDTH; -- number of lookup table points needed.
type mem_type is array ( 0 to MEM_DEPTH-1) of signed(SAMPLE_WIDTH-1 downto 0); -- define memory data type
-- function to fill memory with cos table (at compile time)
function init_lookuptable return mem_type is
constant SCALE : real := 2**(real(SAMPLE_WIDTH-1));
constant STEP : real := 1.0/real(MEM_DEPTH);
variable temp_mem : mem_type;
begin
for i in 0 to MEM_DEPTH-1 loop
temp_mem(i) := to_signed( integer(cos(2.0*MATH_PI*real(i)*STEP)*SCALE), SAMPLE_WIDTH);
end loop;
return temp_mem;
end;
-- constant rom of cos lookup table for 2^11 entries.. (2048x12b)
-- initalized at compile time.
constant cos_lookup : mem_type := init_lookuptable;
-- address for the sample we want to send to the DAC
signal lookup_addr : unsigned( 31 downto 0 );
signal sample_out : signed( 11 downto 0 );
begin
o_dac_cmode <= '1'; -- '1' for differential clocking
o_dac_mode <= '1'; -- '1' = 2's compliment samples
o_dac_sleep <= '0'; -- forces dac to run, set to '1' to place dac in sleep
o_dac_reset <= '1'; -- (pin) forces dac into pin operation mode.. (spi is disabled)
-- output clock for sample generation
o_dac_clk <= i_clk;
o_dac_db <= sample_out;
dac_nco : process( i_clk )
begin
if ( rising_edge(i_clk) ) then
if ( i_rst = '1' ) then
lookup_addr <= (others=>'0');
sample_out <= cos_lookup(to_integer(lookup_addr(31 downto 31-SAMPLE_WIDTH)));
else
lookup_addr <= lookup_addr + i_nco_ftw;
sample_out <= cos_lookup(to_integer(lookup_addr(31 downto 31-SAMPLE_WIDTH)));
end if;
end if;
end process;
end architecture;
| apache-2.0 | dd401065f80ee8363a663621a228fa74 | 0.527912 | 3.788509 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/when/rule_001_test_input.fixed.vhd | 1 | 655 |
architecture ARCH of ENTITY is
begin
a <= sig1 when b = '1' else
sig2 when b = '0' else
sig3;
process
begin
d <= sig1 when b = '1' else--This is a comment
sig2 when c = '0' else -- This is a comment
sig3 when d = '1' else
sig4;
end process;
-- Violations below
a <= sig1 when b = '1' else
sig2 when b = '0' else
sig3;
process
begin
d <= sig1 when b = '1' else--This is a comment
sig2 when c = '0' else -- This is a comment
sig3 when d = '1' else
sig4;
end process;
a <= b when (c = '1')else d;
a <= b when (c = '1'else d;
end architecture ARCH;
| gpl-3.0 | 7e31d369e6577b4520deb955a0286f25 | 0.535878 | 3.119048 | false | false | false | false |
Yarr/Yarr-fw | rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/example_design/rtl/example_top.vhd | 2 | 45,380 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : example_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is the design top level. which instantiates top wrapper,
-- test bench top and infrastructure modules.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity example_top is
generic
(
C3_P0_MASK_SIZE : integer := 8;
C3_P0_DATA_PORT_SIZE : integer := 64;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 3000;
-- Memory data transfer clock period.
C3_RST_ACT_LOW : integer := 0;
-- # = 1 for active low reset,
-- # = 0 for active high reset.
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
-- input clock type DIFFERENTIAL or SINGLE_ENDED.
C3_CALIB_SOFT_IP : string := "TRUE";
-- # = TRUE, Enables the soft calibration logic,
-- # = FALSE, Disables the soft calibration logic.
C3_SIMULATION : string := "FALSE";
-- # = TRUE, Simulating the design. Useful to reduce the simulation time,
-- # = FALSE, Implementing the design.
C3_HW_TESTING : string := "FALSE";
-- Determines the address space accessed by the traffic generator,
-- # = FALSE, Smaller address space,
-- # = TRUE, Large address space.
DEBUG_EN : integer := 0;
-- # = 1, Enable debug signals/controls,
-- = 0, Disable debug signals/controls.
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
-- The order in which user address is provided to the memory controller,
-- ROW_BANK_COLUMN or BANK_ROW_COLUMN.
C3_NUM_DQ_PINS : integer := 16;
-- External memory data width.
C3_MEM_ADDR_WIDTH : integer := 14;
-- External memory address width.
C3_MEM_BANKADDR_WIDTH : integer := 3
-- External memory bank address width.
);
port
(
calib_done : out std_logic;
error : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic
);
end example_top;
architecture arc of example_top is
component memc3_infrastructure is
generic (
C_RST_ACT_LOW : integer;
C_INPUT_CLK_TYPE : string;
C_CLKOUT0_DIVIDE : integer;
C_CLKOUT1_DIVIDE : integer;
C_CLKOUT2_DIVIDE : integer;
C_CLKOUT3_DIVIDE : integer;
C_CLKFBOUT_MULT : integer;
C_DIVCLK_DIVIDE : integer;
C_INCLK_PERIOD : integer
);
port (
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_i : in std_logic;
clk0 : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic;
mcb_drp_clk : out std_logic
);
end component;
component memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer;
C_CALIB_SOFT_IP : string;
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(5 downto 0);
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_MEM_ADDR_ORDER : string;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_DDR3_ODS : string;
C_MEM_DDR3_RTT : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_MOBILE_PA_SR : string;
C_MEM_MDDR_ODS : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_LDQSP_TAP_DELAY_VAL : integer;
C_LDQSN_TAP_DELAY_VAL : integer;
C_UDQSP_TAP_DELAY_VAL : integer;
C_UDQSN_TAP_DELAY_VAL : integer;
C_DQ0_TAP_DELAY_VAL : integer;
C_DQ1_TAP_DELAY_VAL : integer;
C_DQ2_TAP_DELAY_VAL : integer;
C_DQ3_TAP_DELAY_VAL : integer;
C_DQ4_TAP_DELAY_VAL : integer;
C_DQ5_TAP_DELAY_VAL : integer;
C_DQ6_TAP_DELAY_VAL : integer;
C_DQ7_TAP_DELAY_VAL : integer;
C_DQ8_TAP_DELAY_VAL : integer;
C_DQ9_TAP_DELAY_VAL : integer;
C_DQ10_TAP_DELAY_VAL : integer;
C_DQ11_TAP_DELAY_VAL : integer;
C_DQ12_TAP_DELAY_VAL : integer;
C_DQ13_TAP_DELAY_VAL : integer;
C_DQ14_TAP_DELAY_VAL : integer;
C_DQ15_TAP_DELAY_VAL : integer
);
port (
mcb3_dram_dq : inout std_logic_vector((C_NUM_DQ_PINS-1) downto 0);
mcb3_dram_a : out std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0);
mcb3_dram_ba : out std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_dram_udm : out std_logic;
calib_done : out std_logic;
async_rst : in std_logic;
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
mcb_drp_clk : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0);
p0_cmd_bl : in std_logic_vector(5 downto 0);
p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 downto 0);
p1_cmd_bl : in std_logic_vector(5 downto 0);
p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 downto 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 downto 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
component memc3_tb_top is
generic (
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_NUM_DQ_PINS : integer;
C_MEM_BURST_LEN : integer;
C_MEM_NUM_COL_BITS : integer;
C_SMALL_DEVICE : string;
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0);
C_p0_DATA_MODE : std_logic_vector(3 downto 0);
C_p0_END_ADDRESS : std_logic_vector(31 downto 0);
C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0);
C_p1_BEGIN_ADDRESS : std_logic_vector(31 downto 0);
C_p1_DATA_MODE : std_logic_vector(3 downto 0);
C_p1_END_ADDRESS : std_logic_vector(31 downto 0);
C_p1_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
C_p1_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0)
);
port (
error : out std_logic;
calib_done : in std_logic;
clk0 : in std_logic;
rst0 : in std_logic;
cmp_error : out std_logic;
cmp_data_valid : out std_logic;
vio_modify_enable : in std_logic;
error_status : out std_logic_vector(191 downto 0);
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_data : out std_logic_vector(31 downto 0);
p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;
p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p1_mcb_cmd_en_o : out std_logic;
p1_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p1_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p1_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p1_mcb_cmd_full_i : in std_logic;
p1_mcb_wr_en_o : out std_logic;
p1_mcb_wr_mask_o : out std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
p1_mcb_wr_data_o : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_mcb_wr_full_i : in std_logic;
p1_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p1_mcb_rd_en_o : out std_logic;
p1_mcb_rd_data_i : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_mcb_rd_empty_i : in std_logic;
p1_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0)
);
end component;
function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C3_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
constant C3_CLKOUT0_DIVIDE : integer := 1;
constant C3_CLKOUT1_DIVIDE : integer := 1;
constant C3_CLKOUT2_DIVIDE : integer := 16;
constant C3_CLKOUT3_DIVIDE : integer := 8;
constant C3_CLKFBOUT_MULT : integer := 2;
constant C3_DIVCLK_DIVIDE : integer := 1;
constant C3_INCLK_PERIOD : integer := ((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2));
constant C3_ARB_NUM_TIME_SLOTS : integer := 12;
constant C3_ARB_TIME_SLOT_0 : bit_vector(5 downto 0) := o"02";
constant C3_ARB_TIME_SLOT_1 : bit_vector(5 downto 0) := o"20";
constant C3_ARB_TIME_SLOT_2 : bit_vector(5 downto 0) := o"02";
constant C3_ARB_TIME_SLOT_3 : bit_vector(5 downto 0) := o"20";
constant C3_ARB_TIME_SLOT_4 : bit_vector(5 downto 0) := o"02";
constant C3_ARB_TIME_SLOT_5 : bit_vector(5 downto 0) := o"20";
constant C3_ARB_TIME_SLOT_6 : bit_vector(5 downto 0) := o"02";
constant C3_ARB_TIME_SLOT_7 : bit_vector(5 downto 0) := o"20";
constant C3_ARB_TIME_SLOT_8 : bit_vector(5 downto 0) := o"02";
constant C3_ARB_TIME_SLOT_9 : bit_vector(5 downto 0) := o"20";
constant C3_ARB_TIME_SLOT_10 : bit_vector(5 downto 0) := o"02";
constant C3_ARB_TIME_SLOT_11 : bit_vector(5 downto 0) := o"20";
constant C3_MEM_TRAS : integer := 36000;
constant C3_MEM_TRCD : integer := 13500;
constant C3_MEM_TREFI : integer := 7800000;
constant C3_MEM_TRFC : integer := 160000;
constant C3_MEM_TRP : integer := 13500;
constant C3_MEM_TWR : integer := 15000;
constant C3_MEM_TRTP : integer := 7500;
constant C3_MEM_TWTR : integer := 7500;
constant C3_MEM_TYPE : string := "DDR3";
constant C3_MEM_DENSITY : string := "2Gb";
constant C3_MEM_BURST_LEN : integer := 8;
constant C3_MEM_CAS_LATENCY : integer := 6;
constant C3_MEM_NUM_COL_BITS : integer := 10;
constant C3_MEM_DDR1_2_ODS : string := "FULL";
constant C3_MEM_DDR2_RTT : string := "50OHMS";
constant C3_MEM_DDR2_DIFF_DQS_EN : string := "YES";
constant C3_MEM_DDR2_3_PA_SR : string := "FULL";
constant C3_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
constant C3_MEM_DDR3_CAS_LATENCY : integer := 6;
constant C3_MEM_DDR3_ODS : string := "DIV6";
constant C3_MEM_DDR3_RTT : string := "DIV4";
constant C3_MEM_DDR3_CAS_WR_LATENCY : integer := 5;
constant C3_MEM_DDR3_AUTO_SR : string := "ENABLED";
constant C3_MEM_MOBILE_PA_SR : string := "FULL";
constant C3_MEM_MDDR_ODS : string := "FULL";
constant C3_MC_CALIB_BYPASS : string := "NO";
constant C3_MC_CALIBRATION_MODE : string := "CALIBRATION";
constant C3_MC_CALIBRATION_DELAY : string := "HALF";
constant C3_SKIP_IN_TERM_CAL : integer := 1;
constant C3_SKIP_DYNAMIC_CAL : integer := 0;
constant C3_LDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_LDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_DQ0_TAP_DELAY_VAL : integer := 0;
constant C3_DQ1_TAP_DELAY_VAL : integer := 0;
constant C3_DQ2_TAP_DELAY_VAL : integer := 0;
constant C3_DQ3_TAP_DELAY_VAL : integer := 0;
constant C3_DQ4_TAP_DELAY_VAL : integer := 0;
constant C3_DQ5_TAP_DELAY_VAL : integer := 0;
constant C3_DQ6_TAP_DELAY_VAL : integer := 0;
constant C3_DQ7_TAP_DELAY_VAL : integer := 0;
constant C3_DQ8_TAP_DELAY_VAL : integer := 0;
constant C3_DQ9_TAP_DELAY_VAL : integer := 0;
constant C3_DQ10_TAP_DELAY_VAL : integer := 0;
constant C3_DQ11_TAP_DELAY_VAL : integer := 0;
constant C3_DQ12_TAP_DELAY_VAL : integer := 0;
constant C3_DQ13_TAP_DELAY_VAL : integer := 0;
constant C3_DQ14_TAP_DELAY_VAL : integer := 0;
constant C3_DQ15_TAP_DELAY_VAL : integer := 0;
constant C3_SMALL_DEVICE : string := "FALSE"; -- The parameter is set to TRUE for all packages of xc6slx9 device
-- as most of them cannot fit the complete example design when the
-- Chip scope modules are enabled
constant C3_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000200", x"01000000");
constant C3_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C3_p0_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000003ff", x"02ffffff");
constant C3_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffff800", x"fc000000");
constant C3_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000200", x"01000000");
constant C3_p1_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000400", x"03000000");
constant C3_p1_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C3_p1_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000005ff", x"04ffffff");
constant C3_p1_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffff000", x"f8000000");
constant C3_p1_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000400", x"03000000");
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
signal c3_error : std_logic;
signal c3_calib_done : std_logic;
signal c3_clk0 : std_logic;
signal c3_rst0 : std_logic;
signal c3_async_rst : std_logic;
signal c3_sysclk_2x : std_logic;
signal c3_sysclk_2x_180 : std_logic;
signal c3_pll_ce_0 : std_logic;
signal c3_pll_ce_90 : std_logic;
signal c3_pll_lock : std_logic;
signal c3_mcb_drp_clk : std_logic;
signal c3_cmp_error : std_logic;
signal c3_cmp_data_valid : std_logic;
signal c3_vio_modify_enable : std_logic;
signal c3_error_status : std_logic_vector(191 downto 0);
signal c3_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal c3_cmp_data : std_logic_vector(31 downto 0);
signal c3_p0_cmd_en : std_logic;
signal c3_p0_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p0_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p0_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p0_cmd_empty : std_logic;
signal c3_p0_cmd_full : std_logic;
signal c3_p0_wr_en : std_logic;
signal c3_p0_wr_mask : std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
signal c3_p0_wr_data : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
signal c3_p0_wr_full : std_logic;
signal c3_p0_wr_empty : std_logic;
signal c3_p0_wr_count : std_logic_vector(6 downto 0);
signal c3_p0_wr_underrun : std_logic;
signal c3_p0_wr_error : std_logic;
signal c3_p0_rd_en : std_logic;
signal c3_p0_rd_data : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
signal c3_p0_rd_full : std_logic;
signal c3_p0_rd_empty : std_logic;
signal c3_p0_rd_count : std_logic_vector(6 downto 0);
signal c3_p0_rd_overflow : std_logic;
signal c3_p0_rd_error : std_logic;
signal c3_p1_cmd_en : std_logic;
signal c3_p1_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p1_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p1_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p1_cmd_empty : std_logic;
signal c3_p1_cmd_full : std_logic;
signal c3_p1_wr_en : std_logic;
signal c3_p1_wr_mask : std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
signal c3_p1_wr_data : std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
signal c3_p1_wr_full : std_logic;
signal c3_p1_wr_empty : std_logic;
signal c3_p1_wr_count : std_logic_vector(6 downto 0);
signal c3_p1_wr_underrun : std_logic;
signal c3_p1_wr_error : std_logic;
signal c3_p1_rd_en : std_logic;
signal c3_p1_rd_data : std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
signal c3_p1_rd_full : std_logic;
signal c3_p1_rd_empty : std_logic;
signal c3_p1_rd_count : std_logic_vector(6 downto 0);
signal c3_p1_rd_overflow : std_logic;
signal c3_p1_rd_error : std_logic;
signal c3_selfrefresh_enter : std_logic;
signal c3_selfrefresh_mode : std_logic;
begin
error <= c3_error;
calib_done <= c3_calib_done;
c3_sys_clk_p <= '0';
c3_sys_clk_n <= '0';
c3_selfrefresh_enter <= '0';
memc3_infrastructure_inst : memc3_infrastructure
generic map
(
C_RST_ACT_LOW => C3_RST_ACT_LOW,
C_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
C_CLKOUT0_DIVIDE => C3_CLKOUT0_DIVIDE,
C_CLKOUT1_DIVIDE => C3_CLKOUT1_DIVIDE,
C_CLKOUT2_DIVIDE => C3_CLKOUT2_DIVIDE,
C_CLKOUT3_DIVIDE => C3_CLKOUT3_DIVIDE,
C_CLKFBOUT_MULT => C3_CLKFBOUT_MULT,
C_DIVCLK_DIVIDE => C3_DIVCLK_DIVIDE,
C_INCLK_PERIOD => C3_INCLK_PERIOD
)
port map
(
sys_clk_p => c3_sys_clk_p,
sys_clk_n => c3_sys_clk_n,
sys_clk => c3_sys_clk,
sys_rst_i => c3_sys_rst_i,
clk0 => c3_clk0,
rst0 => c3_rst0,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk
);
-- wrapper instantiation
memc3_wrapper_inst : memc3_wrapper
generic map
(
C_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C_CALIB_SOFT_IP => C3_CALIB_SOFT_IP,
C_SIMULATION => C3_SIMULATION,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C3_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => C3_ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => C3_ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => C3_ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => C3_ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => C3_ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => C3_ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => C3_ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => C3_ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => C3_ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => C3_ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => C3_ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => C3_ARB_TIME_SLOT_11,
C_MEM_TRAS => C3_MEM_TRAS,
C_MEM_TRCD => C3_MEM_TRCD,
C_MEM_TREFI => C3_MEM_TREFI,
C_MEM_TRFC => C3_MEM_TRFC,
C_MEM_TRP => C3_MEM_TRP,
C_MEM_TWR => C3_MEM_TWR,
C_MEM_TRTP => C3_MEM_TRTP,
C_MEM_TWTR => C3_MEM_TWTR,
C_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_TYPE => C3_MEM_TYPE,
C_MEM_DENSITY => C3_MEM_DENSITY,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C3_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C3_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C3_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C3_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C3_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C3_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C3_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C3_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C3_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C3_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C3_MEM_DDR3_AUTO_SR,
C_MEM_MOBILE_PA_SR => C3_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C3_MEM_MDDR_ODS,
C_MC_CALIB_BYPASS => C3_MC_CALIB_BYPASS,
C_MC_CALIBRATION_MODE => C3_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C3_MC_CALIBRATION_DELAY,
C_SKIP_IN_TERM_CAL => C3_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C3_SKIP_DYNAMIC_CAL,
C_LDQSP_TAP_DELAY_VAL => C3_LDQSP_TAP_DELAY_VAL,
C_LDQSN_TAP_DELAY_VAL => C3_LDQSN_TAP_DELAY_VAL,
C_UDQSP_TAP_DELAY_VAL => C3_UDQSP_TAP_DELAY_VAL,
C_UDQSN_TAP_DELAY_VAL => C3_UDQSN_TAP_DELAY_VAL,
C_DQ0_TAP_DELAY_VAL => C3_DQ0_TAP_DELAY_VAL,
C_DQ1_TAP_DELAY_VAL => C3_DQ1_TAP_DELAY_VAL,
C_DQ2_TAP_DELAY_VAL => C3_DQ2_TAP_DELAY_VAL,
C_DQ3_TAP_DELAY_VAL => C3_DQ3_TAP_DELAY_VAL,
C_DQ4_TAP_DELAY_VAL => C3_DQ4_TAP_DELAY_VAL,
C_DQ5_TAP_DELAY_VAL => C3_DQ5_TAP_DELAY_VAL,
C_DQ6_TAP_DELAY_VAL => C3_DQ6_TAP_DELAY_VAL,
C_DQ7_TAP_DELAY_VAL => C3_DQ7_TAP_DELAY_VAL,
C_DQ8_TAP_DELAY_VAL => C3_DQ8_TAP_DELAY_VAL,
C_DQ9_TAP_DELAY_VAL => C3_DQ9_TAP_DELAY_VAL,
C_DQ10_TAP_DELAY_VAL => C3_DQ10_TAP_DELAY_VAL,
C_DQ11_TAP_DELAY_VAL => C3_DQ11_TAP_DELAY_VAL,
C_DQ12_TAP_DELAY_VAL => C3_DQ12_TAP_DELAY_VAL,
C_DQ13_TAP_DELAY_VAL => C3_DQ13_TAP_DELAY_VAL,
C_DQ14_TAP_DELAY_VAL => C3_DQ14_TAP_DELAY_VAL,
C_DQ15_TAP_DELAY_VAL => C3_DQ15_TAP_DELAY_VAL
)
port map
(
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_reset_n => mcb3_dram_reset_n,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_rzq => mcb3_rzq,
mcb3_dram_udm => mcb3_dram_udm,
calib_done => c3_calib_done,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
p0_cmd_clk => c3_clk0,
p0_cmd_en => c3_p0_cmd_en,
p0_cmd_instr => c3_p0_cmd_instr,
p0_cmd_bl => c3_p0_cmd_bl,
p0_cmd_byte_addr => c3_p0_cmd_byte_addr,
p0_cmd_empty => c3_p0_cmd_empty,
p0_cmd_full => c3_p0_cmd_full,
p0_wr_clk => c3_clk0,
p0_wr_en => c3_p0_wr_en,
p0_wr_mask => c3_p0_wr_mask,
p0_wr_data => c3_p0_wr_data,
p0_wr_full => c3_p0_wr_full,
p0_wr_empty => c3_p0_wr_empty,
p0_wr_count => c3_p0_wr_count,
p0_wr_underrun => c3_p0_wr_underrun,
p0_wr_error => c3_p0_wr_error,
p0_rd_clk => c3_clk0,
p0_rd_en => c3_p0_rd_en,
p0_rd_data => c3_p0_rd_data,
p0_rd_full => c3_p0_rd_full,
p0_rd_empty => c3_p0_rd_empty,
p0_rd_count => c3_p0_rd_count,
p0_rd_overflow => c3_p0_rd_overflow,
p0_rd_error => c3_p0_rd_error,
p1_cmd_clk => c3_clk0,
p1_cmd_en => c3_p1_cmd_en,
p1_cmd_instr => c3_p1_cmd_instr,
p1_cmd_bl => c3_p1_cmd_bl,
p1_cmd_byte_addr => c3_p1_cmd_byte_addr,
p1_cmd_empty => c3_p1_cmd_empty,
p1_cmd_full => c3_p1_cmd_full,
p1_wr_clk => c3_clk0,
p1_wr_en => c3_p1_wr_en,
p1_wr_mask => c3_p1_wr_mask,
p1_wr_data => c3_p1_wr_data,
p1_wr_full => c3_p1_wr_full,
p1_wr_empty => c3_p1_wr_empty,
p1_wr_count => c3_p1_wr_count,
p1_wr_underrun => c3_p1_wr_underrun,
p1_wr_error => c3_p1_wr_error,
p1_rd_clk => c3_clk0,
p1_rd_en => c3_p1_rd_en,
p1_rd_data => c3_p1_rd_data,
p1_rd_full => c3_p1_rd_full,
p1_rd_empty => c3_p1_rd_empty,
p1_rd_count => c3_p1_rd_count,
p1_rd_overflow => c3_p1_rd_overflow,
p1_rd_error => c3_p1_rd_error,
selfrefresh_enter => c3_selfrefresh_enter,
selfrefresh_mode => c3_selfrefresh_mode
);
memc3_tb_top_inst : memc3_tb_top
generic map
(
C_SIMULATION => C3_SIMULATION,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_SMALL_DEVICE => C3_SMALL_DEVICE,
C_p0_BEGIN_ADDRESS => C3_p0_BEGIN_ADDRESS,
C_p0_DATA_MODE => C3_p0_DATA_MODE,
C_p0_END_ADDRESS => C3_p0_END_ADDRESS,
C_p0_PRBS_EADDR_MASK_POS => C3_p0_PRBS_EADDR_MASK_POS,
C_p0_PRBS_SADDR_MASK_POS => C3_p0_PRBS_SADDR_MASK_POS,
C_p1_BEGIN_ADDRESS => C3_p1_BEGIN_ADDRESS,
C_p1_DATA_MODE => C3_p1_DATA_MODE,
C_p1_END_ADDRESS => C3_p1_END_ADDRESS,
C_p1_PRBS_EADDR_MASK_POS => C3_p1_PRBS_EADDR_MASK_POS,
C_p1_PRBS_SADDR_MASK_POS => C3_p1_PRBS_SADDR_MASK_POS
)
port map
(
error => c3_error,
calib_done => c3_calib_done,
clk0 => c3_clk0,
rst0 => c3_rst0,
cmp_error => c3_cmp_error,
cmp_data_valid => c3_cmp_data_valid,
vio_modify_enable => c3_vio_modify_enable,
error_status => c3_error_status,
vio_data_mode_value => c3_vio_data_mode_value,
vio_addr_mode_value => c3_vio_addr_mode_value,
cmp_data => c3_cmp_data,
p0_mcb_cmd_en_o => c3_p0_cmd_en,
p0_mcb_cmd_instr_o => c3_p0_cmd_instr,
p0_mcb_cmd_bl_o => c3_p0_cmd_bl,
p0_mcb_cmd_addr_o => c3_p0_cmd_byte_addr,
p0_mcb_cmd_full_i => c3_p0_cmd_full,
p0_mcb_wr_en_o => c3_p0_wr_en,
p0_mcb_wr_mask_o => c3_p0_wr_mask,
p0_mcb_wr_data_o => c3_p0_wr_data,
p0_mcb_wr_full_i => c3_p0_wr_full,
p0_mcb_wr_fifo_counts => c3_p0_wr_count,
p0_mcb_rd_en_o => c3_p0_rd_en,
p0_mcb_rd_data_i => c3_p0_rd_data,
p0_mcb_rd_empty_i => c3_p0_rd_empty,
p0_mcb_rd_fifo_counts => c3_p0_rd_count,
p1_mcb_cmd_en_o => c3_p1_cmd_en,
p1_mcb_cmd_instr_o => c3_p1_cmd_instr,
p1_mcb_cmd_bl_o => c3_p1_cmd_bl,
p1_mcb_cmd_addr_o => c3_p1_cmd_byte_addr,
p1_mcb_cmd_full_i => c3_p1_cmd_full,
p1_mcb_wr_en_o => c3_p1_wr_en,
p1_mcb_wr_mask_o => c3_p1_wr_mask,
p1_mcb_wr_data_o => c3_p1_wr_data,
p1_mcb_wr_full_i => c3_p1_wr_full,
p1_mcb_wr_fifo_counts => c3_p1_wr_count,
p1_mcb_rd_en_o => c3_p1_rd_en,
p1_mcb_rd_data_i => c3_p1_rd_data,
p1_mcb_rd_empty_i => c3_p1_rd_empty,
p1_mcb_rd_fifo_counts => c3_p1_rd_count
);
end arc;
| gpl-3.0 | 27f96700c0894ae929c7a75ac249ce14 | 0.452821 | 3.401289 | false | false | false | false |
Yarr/Yarr-fw | rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/sim/rd_data_gen.vhd | 20 | 16,459 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: rd_data_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module has all the timing control for generating "compare data"
-- to compare the read data from memory.
-- Reference:
-- Revision History: 2010/01/09 parameter MEM_BURST_LEN is missing in v6_data_gen instance module.
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity rd_data_gen is
generic (
FAMILY : string := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic; --
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0); -- "00" = bram;
rd_mdata_en : in std_logic;
cmd_rdy_o : out std_logic; -- ready to receive command. It should assert when data_port is ready at the // beginning and will be deasserted once see the cmd_valid_i is asserted.
-- And then it should reasserted when
-- it is generating the last_word.
cmd_valid_i : in std_logic; -- when both cmd_valid_i and cmd_rdy_o is high, the command is valid.
last_word_o : out std_logic;
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- generated address used to determine data pattern.
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- generated address used to determine data pattern.
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0); -- generated burst length for control the burst data
user_bl_cnt_is_1_o : out std_logic;
data_rdy_i : in std_logic; -- connect from mcb_wr_full when used as wr_data_gen in sp6
-- connect from mcb_rd_empty when used as rd_data_gen in sp6
-- connect from rd_data_valid in v6
-- When both data_rdy and data_valid is asserted, the ouput data is valid.
data_valid_o : out std_logic; -- connect to wr_en or rd_en and is asserted whenever the
-- pattern is available.
data_o : out std_logic_vector(DWIDTH - 1 downto 0) -- generated data pattern
);
end entity rd_data_gen;
ARCHITECTURE trans OF rd_data_gen IS
COMPONENT sp6_data_gen IS
GENERIC (
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS";
NUM_DQ_PINS : INTEGER := 8;
COLUMN_WIDTH : INTEGER := 10
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
cmd_startA : IN STD_LOGIC;
cmd_startB : IN STD_LOGIC;
cmd_startC : IN STD_LOGIC;
cmd_startD : IN STD_LOGIC;
cmd_startE : IN STD_LOGIC;
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
user_burst_cnt : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
fifo_rdy_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0)
);
END COMPONENT;
COMPONENT v6_data_gen IS
GENERIC (
ADDR_WIDTH : INTEGER := 32;
MEM_BURST_LEN : integer := 8;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_ALL";
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3;
COLUMN_WIDTH : INTEGER := 10
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
cmd_startA : IN STD_LOGIC;
cmd_startB : IN STD_LOGIC;
cmd_startC : IN STD_LOGIC;
cmd_startD : IN STD_LOGIC;
cmd_startE : IN STD_LOGIC;
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
user_burst_cnt : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
fifo_rdy_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(NUM_DQ_PINS*4 - 1 DOWNTO 0)
);
END COMPONENT;
SIGNAL prbs_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL cmd_start : STD_LOGIC;
SIGNAL adata : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL hdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL ndata : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL w1data : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL v6_w1data : STD_LOGIC_VECTOR(NUM_DQ_PINS * 4 - 1 DOWNTO 0);
signal w0data : std_logic_vector(31 downto 0);
signal data : std_logic_vector(DWIDTH - 1 downto 0);
signal cmd_rdy : std_logic;
signal data_valid : std_logic;
signal user_burst_cnt : std_logic_vector(6 downto 0);
signal data_rdy_r1 : std_logic;
signal data_rdy_r2 : std_logic;
signal next_count_is_one : std_logic;
signal cmd_valid_r1 : std_logic;
signal w3data : std_logic_vector(31 downto 0);
signal data_port_fifo_rdy : std_logic;
--assign cmd_start = cmd_valid_i & cmd_rdy ;
signal user_bl_cnt_is_1 : std_logic;
signal cmd_start_b : std_logic;
-- need to wait for extra cycle for data coming out from rd_post_fifo in V6 interface
-- need to wait for extra cycle for data coming out from rd_post_fifo in V6 interface
-- counter to count user burst length
signal u_bcount_2 : std_logic;
-- Declare intermediate signals for referenced outputs
signal last_word_o_xhdl1 : std_logic;
signal data_o_xhdl0 : std_logic_vector(DWIDTH - 1 downto 0);
begin
-- Drive referenced outputs
last_word_o <= last_word_o_xhdl1;
data_port_fifo_rdy <= data_rdy_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
data_rdy_r1 <= data_rdy_i;
data_rdy_r2 <= data_rdy_r1;
cmd_valid_r1 <= cmd_valid_i;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (user_burst_cnt = "0000010" and data_rdy_i = '1') then
next_count_is_one <= '1';
else
next_count_is_one <= '0';
end if;
end if;
end process;
user_bl_cnt_is_1_o <= user_bl_cnt_is_1;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((user_burst_cnt = "0000010" and data_port_fifo_rdy = '1' and FAMILY = "SPARTAN6") or
(user_burst_cnt = "0000010" and data_port_fifo_rdy = '1' and FAMILY = "VIRTEX6") ) then
user_bl_cnt_is_1 <= '1';
else
user_bl_cnt_is_1 <= '0';
end if;
end if;
end process;
process (cmd_valid_i, cmd_valid_r1, cmd_rdy, user_bl_cnt_is_1, rd_mdata_en)
begin
if (FAMILY = "SPARTAN6") then
cmd_start <= cmd_valid_i and cmd_rdy;
cmd_start_b <= cmd_valid_i and cmd_rdy;
else
if (MEM_BURST_LEN = 4) then
cmd_start <= rd_mdata_en;
else
cmd_start <= (not(cmd_valid_r1) and cmd_valid_i) or user_bl_cnt_is_1;
cmd_start_b <= (not(cmd_valid_r1) and cmd_valid_i) or user_bl_cnt_is_1;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
user_burst_cnt <= "0000000";
elsif (cmd_start = '1') then
if (bl_i = "000000") then
user_burst_cnt <= "1000000" ;
else
user_burst_cnt <= ('0' & bl_i) ;
end if;
elsif (data_port_fifo_rdy = '1') then
if (user_burst_cnt /= "0000000") then
user_burst_cnt <= user_burst_cnt - "0000001";
else
user_burst_cnt <= "0000000";
end if;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((user_burst_cnt = "0000010" and data_rdy_i = '1') or (cmd_start = '1' and bl_i = "000001")) then
u_bcount_2 <= '1';
elsif (last_word_o_xhdl1 = '1') then
u_bcount_2 <= '0';
end if;
end if;
end process;
last_word_o_xhdl1 <= u_bcount_2 and data_rdy_i;
-- cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i
-- is assert and reassert during the last data
--data_valid_o logic
cmd_rdy_o <= cmd_rdy;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdy <= '1';
elsif (cmd_start = '1') then
cmd_rdy <= '0';
elsif (data_port_fifo_rdy = '1' and user_burst_cnt = "0000001") then
cmd_rdy <= '1';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
data_valid <= '0';
elsif (user_burst_cnt = "0000001" and data_port_fifo_rdy = '1') then
data_valid <= '0';
elsif ((user_burst_cnt >= "0000001") or cmd_start = '1') then
data_valid <= '1';
end if;
end if;
end process;
process (data_valid, data_port_fifo_rdy)
begin
if (FAMILY = "SPARTAN6") then
data_valid_o <= data_valid;
else
data_valid_o <= data_port_fifo_rdy;
end if;
end process;
xhdl2 : if (FAMILY = "SPARTAN6") generate
sp6_data_gen_inst : sp6_data_gen
generic map (
ADDR_WIDTH => 32,
BL_WIDTH => BL_WIDTH,
DWIDTH => DWIDTH,
DATA_PATTERN => DATA_PATTERN,
NUM_DQ_PINS => NUM_DQ_PINS,
COLUMN_WIDTH => COLUMN_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(1),
data_rdy_i => data_rdy_i,
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_startA => cmd_start,
cmd_startB => cmd_start,
cmd_startC => cmd_start,
cmd_startD => cmd_start,
cmd_startE => cmd_start,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
user_burst_cnt => user_burst_cnt,
fifo_rdy_i => data_port_fifo_rdy,
data_o => data_o
);
end generate;
xhdl3 : if (FAMILY = "VIRTEX6") generate
v6_data_gen_inst : v6_data_gen
generic map (
ADDR_WIDTH => 32,
BL_WIDTH => BL_WIDTH,
MEM_BURST_LEN => MEM_BURST_LEN,
DWIDTH => DWIDTH,
DATA_PATTERN => DATA_PATTERN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
COLUMN_WIDTH => COLUMN_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(1),
data_rdy_i => data_rdy_i,
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_startA => cmd_start,
cmd_startB => cmd_start,
cmd_startC => cmd_start,
cmd_startD => cmd_start,
cmd_startE => cmd_start,
fixed_data_i => fixed_data_i,
m_addr_i => addr_i, --(m_addr_i ),
addr_i => addr_i,
user_burst_cnt => user_burst_cnt,
fifo_rdy_i => data_port_fifo_rdy,
data_o => data_o
);
end generate;
end architecture trans;
| gpl-3.0 | 23407cbf24985e93135067a043c43484 | 0.511817 | 3.784548 | false | false | false | false |
NicoLedwith/Dr.AluOpysel | RAT_MCU/VGAdrive.vhd | 3 | 3,620 | --
-- Sends the given RGB data to a VGA interface.
--
-- Original author: unknown
--
-- Peter Heatwole, Aaron Barton
-- CPE233, Winter 2012, CalPoly
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity VGAdrive is
port( clock : in std_logic; -- 25.175 Mhz clock
red, green : in std_logic_vector(2 downto 0);
blue : in std_logic_vector(1 downto 0);
row, column : out std_logic_vector(9 downto 0); -- for current pixel
Rout, Gout : out std_logic_vector(2 downto 0);
Bout : out std_logic_vector(1 downto 0);
H, V : out std_logic); -- VGA drive signals
-- The signals Rout, Gout, Bout, H and V are output to the monitor.
-- The row and column outputs are used to know when to assert red,
-- green and blue to color the current pixel. For VGA, the column
-- values that are valid are from 0 to 639, all other values should
-- be ignored. The row values that are valid are from 0 to 479 and
-- again, all other values are ignored. To turn on a pixel on the
-- VGA monitor, some combination of red, green and blue should be
-- asserted before the rising edge of the clock. Objects which are
-- displayed on the monitor, assert their combination of red, green and
-- blue when they detect the row and column values are within their
-- range. For multiple objects sharing a screen, they must be combined
-- using logic to create single red, green, and blue signals.
end VGAdrive;
architecture Behavioral of VGAdrive is
subtype counter is std_logic_vector(9 downto 0);
constant B : natural := 93; -- horizontal blank: 3.77 us
constant C : natural := 45; -- front guard: 1.89 us
constant D : natural := 640; -- horizontal columns: 25.17 us
constant E : natural := 22; -- rear guard: 0.94 us
constant A : natural := B + C + D + E; -- one horizontal sync cycle: 31.77 us
constant P : natural := 2; -- vertical blank: 64 us
constant Q : natural := 32; -- front guard: 1.02 ms
constant R : natural := 480; -- vertical rows: 15.25 ms
constant S : natural := 11; -- rear guard: 0.35 ms
constant O : natural := P + Q + R + S; -- one vertical sync cycle: 16.6 ms
begin
-- Rout <= red;
-- Gout <= green;
-- Bout <= blue;
process
variable vertical, horizontal : counter; -- define counters
begin
wait until clock = '1';
-- increment counters
if horizontal < A - 1 then
horizontal := horizontal + 1;
else
horizontal := (others => '0');
if vertical < O - 1 then -- less than oh
vertical := vertical + 1;
else
vertical := (others => '0'); -- is set to zero
end if;
end if;
-- define H pulse
if horizontal >= (D + E) and horizontal < (D + E + B) then
H <= '0';
else
H <= '1';
end if;
-- define V pulse
if vertical >= (R + S) and vertical < (R + S + P) then
V <= '0';
else
V <= '1';
end if;
-- mapping of the variable to the signals
-- negative signs are because the conversion bits are reversed
if vertical <= 479 and horizontal <= 639 then
Rout <= red;
Gout <= green;
Bout <= blue;
else
Rout <= "000";
Gout <= "000";
Bout <= "00";
end if;
row <= vertical;
column <= horizontal;
end process;
end Behavioral;
| mit | 0bec8fec3ad8889769c4e11a996a4fb6 | 0.577901 | 3.879957 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/instantiation/rule_034_test_input.vhd | 1 | 699 |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST2 : component INST2
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST3 : entity fifo_dsn.INST3(rtl)
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
end architecture ARCH;
| gpl-3.0 | ff3d477ce0b287fa8306b9d7e29ff93b | 0.447783 | 2.688462 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/concurrent/rule_400_test_input.vhd | 1 | 395 |
architecture rtl of fifo is begin
s_foo <= (
item => 12,
another_item => 34
);
s_foo <= (
item => 12,
another_item => 34
);
s_foo <= ( item1 => 12,
item2=> f(a, b ,c),
item3 => 36
);
s_foo <= (a and
b and
c);
end architecture rtl;
| gpl-3.0 | e3bd3fdaad9c553a387c01bb72c866a2 | 0.334177 | 3.95 | false | false | false | false |
Nibble-Knowledge/peripheral-ethernet | vhdl-serial/ram.vhd | 1 | 1,920 | -------------------------------------------------------
-- Design Name : ram_sp_ar_aw
-- File Name : ram_sp_ar_aw.vhd
-- Function : Asynchronous read write RAM
-- Coder : Deepak Kumar Tala (Verilog)
-- Translator : Alexander H Pham (VHDL)
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ram_sp_ar_aw is
generic (
DATA_WIDTH :integer := 8;
ADDR_WIDTH :integer := 15
);
port (
address :in std_logic_vector (ADDR_WIDTH-1 downto 0); -- address Input
data :inout std_logic_vector (DATA_WIDTH-1 downto 0); -- data bi-directional
cs :in std_logic; -- Chip Select
we :in std_logic; -- Write Enable/Read Enable
oe :in std_logic -- Output Enable
);
end entity;
architecture rtl of ram_sp_ar_aw is
----------------Internal variables----------------
constant RAM_DEPTH :integer := 2**ADDR_WIDTH;
signal data_out :std_logic_vector (DATA_WIDTH-1 downto 0);
type RAM is array (integer range <>)of std_logic_vector (DATA_WIDTH-1 downto 0);
signal mem : RAM (0 to RAM_DEPTH-1);
begin
----------------Code Starts Here------------------
-- Tri-State Buffer control
data <= data_out when (cs = '1' and oe = '1' and we = '0') else (others=>'Z');
-- Memory Write Block
MEM_WRITE:
process (address, data, cs, we) begin
if (cs = '1' and we = '1') then
mem(conv_integer(address)) <= data;
end if;
end process;
-- Memory Read Block
MEM_READ:
process (address, cs, we, oe, mem) begin
if (cs = '1' and we = '0' and oe = '1') then
data_out <= mem(conv_integer(address));
end if;
end process;
end architecture;
| unlicense | acd71b7455d496fde5361f11f610a82e | 0.503125 | 3.894523 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/styles/jcl/graphicsaccelerator/Bresenhamer.fixed.vhd | 1 | 9,594 | library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity BRESENHAMER is
port (
WRITEENABLE : out std_logic;
X : out std_logic_vector(9 downto 0);
Y : out std_logic_vector(8 downto 0);
X1 : in std_logic_vector(9 downto 0);
Y1 : in std_logic_vector(8 downto 0);
X2 : in std_logic_vector(9 downto 0);
Y2 : in std_logic_vector(8 downto 0);
SS : out std_logic_vector(3 downto 0);
CLK : in std_logic;
STARTDRAW : in std_logic;
DBG : out std_logic_vector(11 downto 0);
RESET : in std_logic
);
end entity BRESENHAMER;
architecture BEHAVIORAL of BRESENHAMER is
signal myx1, myx2 : std_logic_vector(11 downto 0);
signal myy1, myy2 : std_logic_vector(11 downto 0);
signal p : std_logic_vector(11 downto 0);
signal p0_1 : std_logic_vector(11 downto 0);
signal p0_2 : std_logic_vector(11 downto 0);
signal p0_3 : std_logic_vector(11 downto 0);
signal p0_4 : std_logic_vector(11 downto 0);
signal p0_5 : std_logic_vector(11 downto 0);
signal p0_6 : std_logic_vector(11 downto 0);
signal p0_7 : std_logic_vector(11 downto 0);
signal p0_8 : std_logic_vector(11 downto 0);
signal p_1 : std_logic_vector(11 downto 0);
signal p_2 : std_logic_vector(11 downto 0);
signal p_3 : std_logic_vector(11 downto 0);
signal p_4 : std_logic_vector(11 downto 0);
signal p_5 : std_logic_vector(11 downto 0);
signal p_6 : std_logic_vector(11 downto 0);
signal p_7 : std_logic_vector(11 downto 0);
signal p_8 : std_logic_vector(11 downto 0);
signal ndx, ndy : std_logic_vector(11 downto 0);
signal dx : std_logic_vector(11 downto 0);
signal dy : std_logic_vector(11 downto 0);
signal t_2dx : std_logic_vector(11 downto 0);
signal t_2dy : std_logic_vector(11 downto 0);
signal neg_dx : std_logic_vector(11 downto 0);
signal neg_dy : std_logic_vector(11 downto 0);
signal t_2neg_dx : std_logic_vector(11 downto 0);
signal t_2neg_dy : std_logic_vector(11 downto 0);
signal dx_minus_dy : std_logic_vector(11 downto 0);
signal minus_dx_minus_dy : std_logic_vector(11 downto 0);
signal minus_dx_plus_dy : std_logic_vector(11 downto 0);
signal dx_plus_dy : std_logic_vector(11 downto 0);
signal state : std_logic_vector(3 downto 0) := "0000";
signal condx1x2, condy1y2 : std_logic;
signal ccounter : std_logic_vector(18 downto 0) := "0000000000000000000";
constant idle : std_logic_vector(3 downto 0) := "0000";
constant init : std_logic_vector(3 downto 0) := "0001";
constant case1 : std_logic_vector(3 downto 0) := "0010";
constant case2 : std_logic_vector(3 downto 0) := "0011";
constant case3 : std_logic_vector(3 downto 0) := "0100";
constant case4 : std_logic_vector(3 downto 0) := "0101";
constant case5 : std_logic_vector(3 downto 0) := "0110";
constant case6 : std_logic_vector(3 downto 0) := "0111";
constant case7 : std_logic_vector(3 downto 0) := "1000";
constant case8 : std_logic_vector(3 downto 0) := "1001";
constant clear : std_logic_vector(3 downto 0) := "1010";
begin
ndx <= ("00" & X2) - ("00" & X1);
ndy <= ("000" & Y2) - ("000" & Y1);
neg_dx <= 0 - dx;
neg_dy <= 0 - dy;
DBG <= p;
dx_minus_dy <= dx + neg_dy;
minus_dx_minus_dy <= neg_dx + neg_dy;
minus_dx_plus_dy <= neg_dx + dy;
dx_plus_dy <= dx + dy;
t_2dy <= dy(10 downto 0) & '0';
t_2dx <= dx(10 downto 0) & '0';
t_2neg_dy <= neg_dy(10 downto 0) & '0';
t_2neg_dx <= neg_dx(10 downto 0) & '0';
p0_1 <= t_2dy + neg_dx;
p0_2 <= t_2dx + neg_dy;
p0_3 <= t_2neg_dx + dy;
p0_4 <= t_2dy + neg_dx;
p0_5 <= t_2neg_dy + dx;
p0_6 <= t_2neg_dx + dy;
p0_7 <= t_2dx + neg_dy;
p0_8 <= t_2neg_dy + dx;
p_1 <= p + t_2dy when p(11)='1' else
p + t_2dy + t_2neg_dx;
p_2 <= p + t_2dx when p(11)='1' else
p + t_2dx + t_2neg_dy;
p_3 <= p + t_2neg_dx when p(11)='1' else
p + t_2neg_dx + t_2neg_dy;
p_4 <= p + t_2dy when p(11)='1' else
p + t_2dy + t_2dx;
p_5 <= p + t_2neg_dy when p(11)='1' else
p + t_2neg_dy + t_2dx;
p_6 <= p + t_2neg_dx when p(11)='1' else
p + t_2neg_dx + t_2dy;
p_7 <= p + t_2dx when p(11)='1' else
p + t_2dx + t_2dy;
p_8 <= p + t_2neg_dy when p(11)='1' else
p + t_2neg_dy + t_2neg_dx;
X <= ccounter(9 downto 0) when state = clear else
myx1(9 downto 0);
Y <= ccounter(18 downto 10) when state = clear else
myy1(8 downto 0);
SS <= state;
WRITEENABLE <= '0' when state = idle or state = init else
'1';
process (CLK) is
begin
if (rising_edge(CLK)) then
if (state = idle) then
if (RESET = '1') then
state <= clear;
ccounter <= (others => '0');
elsif (STARTDRAW = '1') then
myx1(9 downto 0) <= X1;
myx1(11 downto 10) <= "00";
myy1(8 downto 0) <= Y1;
myy1(11 downto 9) <= "000";
myx2(9 downto 0) <= X2;
myx2(11 downto 10) <= "00";
myy2(8 downto 0) <= Y2;
myy2(11 downto 9) <= "000";
dx <= ndx;
dy <= ndy;
state <= init;
end if;
elsif (state = init) then
if (dx(11) = '0' and dy(11) = '0' and dx_minus_dy(11) = '0') then
state <= case1;
p <= p0_1;
elsif (dx(11) = '0' and dy(11) = '0' and dx_minus_dy(11) = '1') then
state <= case2;
p <= p0_2;
elsif (dx(11) = '1' and dy(11) = '0' and minus_dx_minus_dy(11) = '1') then
state <= case3;
p <= p0_3;
elsif (dx(11) = '1' and dy(11) = '0' and minus_dx_minus_dy(11) = '0') then
state <= case4;
p <= p0_4;
elsif (dx(11) = '1' and dy(11) = '1' and minus_dx_plus_dy(11) = '0') then
state <= case5;
p <= p0_5;
elsif (dx(11) = '1' and dy(11) = '1' and minus_dx_plus_dy(11) = '1') then
state <= case6;
p <= p0_6;
elsif (dx(11) = '0' and dy(11) = '1' and dx_plus_dy(11) = '1') then
state <= case7;
p <= p0_7;
else
state <= case8;
p <= p0_8;
end if;
elsif (state = case1) then
if (myx1 = myx2) then
state <= idle;
else
myx1 <= myx1 + 1;
p <= p_1;
if (p(11) = '0') then
myy1 <= myy1 + 1;
end if;
end if;
elsif (state = case2) then
if (myy1 = myy2) then
state <= idle;
else
myy1 <= myy1 + 1;
p <= p_2;
if (p(11) = '0') then
myx1 <= myx1 + 1;
end if;
end if;
elsif (state = case3) then
if (myy1 = myy2) then
state <= idle;
else
myy1 <= myy1 + 1;
p <= p_3;
if (p(11) = '0') then
myx1 <= myx1 - 1;
end if;
end if;
elsif (state = case4) then
if (myx1 = myx2) then
state <= idle;
else
myx1 <= myx1 - 1;
p <= p_4;
if (p(11) = '0') then
myy1 <= myy1 + 1;
end if;
end if;
elsif (state = case5) then
if (myx1 = myx2) then
state <= idle;
else
myx1 <= myx1 - 1;
p <= p_5;
if (p(11) = '0') then
myy1 <= myy1 - 1;
end if;
end if;
elsif (state = case6) then
if (myy1 = myy2) then
state <= idle;
else
myy1 <= myy1 - 1;
p <= p_6;
if (p(11) = '0') then
myx1 <= myx1 - 1;
end if;
end if;
elsif (state = case7) then
if (myy1 = myy2) then
state <= idle;
else
myy1 <= myy1 - 1;
p <= p_7;
if (p(11) = '0') then
myx1 <= myx1 + 1;
end if;
end if;
elsif (state = case8) then
if (myx1 = myx2) then
state <= idle;
else
myx1 <= myx1 + 1;
p <= p_8;
if (p(11) = '0') then
myy1 <= myy1 - 1;
end if;
end if;
elsif (state = clear) then
ccounter <= ccounter + 1;
if (ccounter = "1111111111111111111") then
state <= idle;
end if;
end if;
end if;
end process;
end architecture BEHAVIORAL;
| gpl-3.0 | 4a30630071478c77fb38a99c051b30eb | 0.442464 | 3.15696 | false | false | false | false |
Yarr/Yarr-fw | rtl/spartan6/rx-core/data_alignment.vhd | 3 | 4,097 | -- word alignment
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity data_alignment is
port
(
clk : in std_logic := '0';
reset : in std_logic := '0';
din : in std_logic_vector(1 downto 0) := "00";
din_valid : in std_logic_vector(1 downto 0) := "00";
dout : out std_logic_vector(9 downto 0) := (others => '0');
dout_valid : out std_logic := '0';
dout_sync : out std_logic := '0'
);
end data_alignment;
architecture Behavioral of data_alignment is
-- FE-I4 Encoded Komma Words used for Alignment of the Decoder
constant idle_word : std_logic_vector(9 downto 0) := "0011111001";
constant sof_word : std_logic_vector(9 downto 0) := "0011111000";
constant eof_word : std_logic_vector(9 downto 0) := "0011111010";
-- Count of Bits before a new sync word is necessary (currently arbitrary)
constant fei4syncPeriod: integer := 160000000;
signal data_sr : std_logic_vector(10 downto 0) := (others => '0');
signal dcnt : integer range 0 to 11 := 0;
signal scnt : integer range 0 to fei4syncPeriod := 0;
signal sync : std_logic := '0';
signal sync_word : std_logic_vector(1 downto 0) := (others => '0');
signal sync_holdoff : std_logic := '0';
begin
-- search for sync words
process (reset, data_sr) begin
if reset = '1' then
sync_word <= "00";
else
if sync_holdoff = '0' then
if (data_sr(9 downto 0) = idle_word) or (data_sr(9 downto 0) = not idle_word) or
(data_sr(9 downto 0) = sof_word) or (data_sr(9 downto 0) = not sof_word) or
(data_sr(9 downto 0) = eof_word) or (data_sr(9 downto 0) = not eof_word) then
sync_word <= "01";
elsif (data_sr(10 downto 1) = idle_word) or (data_sr(10 downto 1) = not idle_word) or
(data_sr(10 downto 1) = sof_word) or (data_sr(10 downto 1) = not sof_word) or
(data_sr(10 downto 1) = eof_word) or (data_sr(10 downto 1) = not eof_word) then
sync_word <= "10";
else
sync_word <= "00";
end if;
else
sync_word <= "00";
end if;
end if;
end process;
-- data alignment
process begin
wait until rising_edge(clk);
if reset = '1' then
dout <= (others => '0');
dout_valid <= '0';
sync <= '0';
data_sr <= (others => '0');
dcnt <= 0;
scnt <= 0;
else
-- clear sync flag
if scnt = fei4syncPeriod then
sync <= '0';
scnt <= 0;
else
scnt <= scnt + 1;
end if;
-- shift in new data
if din_valid = "01" then
data_sr <= data_sr(9 downto 0) & din(0);
if sync_word = "01" then
sync <= '1';
scnt <= 1;
dcnt <= 1;
sync_holdoff <= '1';
elsif sync_word = "10" then
sync <= '1';
scnt <= 2;
dcnt <= 2;
sync_holdoff <= '1';
else
dcnt <= dcnt + 1;
end if;
if dcnt = 10 then
dout <= data_sr(9 downto 0);
dout_valid <= '1';
sync_holdoff <= '0';
dcnt <= 1;
elsif dcnt = 11 then
dout <= data_sr(10 downto 1);
dout_valid <= '1';
sync_holdoff <= '0';
dcnt <= 2;
else
dout_valid <= '0';
end if;
elsif din_valid = "11" then
data_sr <= data_sr(8 downto 0) & din(0) & din(1);
if sync_word = "01" then
sync <= '1';
scnt <= 2;
dcnt <= 2;
elsif sync_word = "10" then
sync <= '1';
scnt <= 3;
dcnt <= 3;
else
dcnt <= dcnt + 2;
end if;
if dcnt = 10 then
dout <= data_sr(9 downto 0);
dout_valid <= '1' and sync;
sync_holdoff <= '0';
dcnt <= 2;
elsif dcnt = 11 then
dout <= data_sr(10 downto 1);
dout_valid <= '1' and sync;
sync_holdoff <= '0';
dcnt <= 3;
else
dout_valid <= '0';
end if;
else
if sync_word = "01" then
sync <= '1';
scnt <= 0;
dcnt <= 0;
elsif sync_word = "10" then
sync <= '1';
scnt <= 1;
dcnt <= 1;
end if;
if dcnt = 10 then
dout <= data_sr(9 downto 0);
dout_valid <= '1' and sync;
sync_holdoff <= '0';
dcnt <= 0;
elsif dcnt = 11 then
dout <= data_sr(10 downto 1);
dout_valid <= '1' and sync;
sync_holdoff <= '0';
dcnt <= 1;
else
dout_valid <= '0';
end if;
end if;
end if;
end process;
dout_sync <= sync;
end Behavioral;
| gpl-3.0 | 50d5fbb63b8ec9403616c70b7f4fe91c | 0.562607 | 2.755212 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/constant/rule_016_test_input_positional.fixed.vhd | 1 | 842 |
architecture rtl of fifo is
constant GBE_RX_AVST_NULL : t_avst_packet(data(7 downto 0), empty(0 downto 0), error(5 downto 0)) :=
(
x"00",
'0',
'0',
'0',
"-",
"000000"
);
constant GBE_RX_AVST_NULL : t_avst_packet(data(7 downto 0), empty(0 downto 0), error(5 downto 0)) :=
(
x"00", '0', '0',
'0', "-",
"000000"
);
-- Verify others are still handled
constant cons2 : t_type :=
(
(others => (valid => '0', data => (others => '0'))), (others => (1 => '0', (others => '0')))
);
-- Verify assignments are still handled
constant cons1 : t_type :=
(
1 => func1(std_logic_vector(G_GEN), G_GEN2),
2 => func1(std_logic_vector(G_GEN3), G_GEN4)
);
constant AVMM_MASTER_NULL : t_avmm_master :=
(
(others => '0'), (others => '0'), '0', '0'
);
begin
end architecture rtl;
| gpl-3.0 | c9d828ca1d11bb2598be46375e4fad29 | 0.535629 | 2.806667 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/conditional_expressions/rule_500_test_input.fixed_upper.vhd | 1 | 400 |
architecture rtl of fifo is
begin
process
begin
var1 := '0' WHEN rd_en = '1' else '1';
var2 := '0' WHEN rd_en = '1' else '1';
wr_en_a <= force '0' WHEN rd_en = '1' else '1';
wr_en_b <= force '0' WHEN rd_en = '1' else '1';
end process;
concurrent_wr_en_a <= '0' WHEN rd_en = '1' else '1';
concurrent_wr_en_b <= '0' when rd_en = '1' else '1';
end architecture rtl;
| gpl-3.0 | d478e8fe056ee067dc25e5314c4c3bc6 | 0.54 | 2.564103 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/variable_assignment/rule_401_test_input.vhd | 1 | 384 |
architecture rtl of fifo is
begin
process begin
wr_data :=
(
(name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"),
(name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00")
);
end process;
end architecture rtl;
| gpl-3.0 | e02ee137c1d491f03d5317777b9381eb | 0.429688 | 3.282051 | false | false | false | false |
Nibble-Knowledge/peripheral-ethernet | vhdl-serial/pc2periph.vhd | 1 | 4,458 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:14:34 02/22/2016
-- Design Name:
-- Module Name: pc2periph - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity pc2periph is
Port ( clk_uart : in STD_LOGIC; --Clock set to the baud rate
reset : in STD_LOGIC;
rs232_td : in STD_LOGIC; --Data transmitted from PC
--rs232_rts : in STD_LOGIC; --Request from PC to transmit data
mem_inuse : in STD_LOGIC;
rs232_cts : out STD_LOGIC; --Response to PC that the peripheral is ready to accept data
ram_addr : out STD_LOGIC_VECTOR (14 downto 0);
ram_data : out STD_LOGIC_VECTOR (7 downto 0));
end pc2periph;
architecture Behavioral of pc2periph is
--signal mem_captured : std_logic; --Memory is exclusively used by this component and no other
signal mem_addr : integer;
signal mem_increment : std_logic; --We'd like to increment the address in START only when we've read a byte
signal data_buf : std_logic_vector(ram_data'range);
signal data_buf_pos : integer;
--FSM
type PERIPHSTATE is (START, LISTEN, STOPANDWRITE);
signal CurrState : PERIPHSTATE;
begin
process(clk_uart, reset)
begin
if reset = '1' then
CurrState <= START;--WAIT4RTS;
ram_data <= (others => '0');
--rs232_cts <= '0'; --mem_captured <= '0';
mem_addr <= 0;
mem_increment <= '0';
data_buf <= (others => '0');
elsif rising_edge(clk_uart) then
--if rs232_rts = '1' then
case CurrState is --begin FSM
--when WAIT4RTS => --Waiting for PC to send an RTS
--When it does, ensure that memory is not currently in use
--If that's the case, await the start signal
-- if mem_inuse = '0' then --and mem_inuse = '0' then
-- CurrState <= START;
-- end if;
when START => --await the start signal, i.e. transition from high to low
--YES, YOU HEARD THAT RIGHT! HIGH TO LOW! Why? Everything is going through a CMOS circuit, so signals get inverted
--BUT! Since the bits themselves are inverted, the CMOS circuit puts them correctly! Strange, innit?
--So when transition is detected, go to the listening state and buffer the signals
if rs232_td = '0' then
CurrState <= LISTEN;
data_buf_pos <= ram_data'length - 1;
rs232_cts <= '1';
else
rs232_cts <= '0';
--If RTS is lost, wait for it to come back
--elsif rs232_rts = '0' then
-- CurrState <= WAIT4RTS;
end if;
if mem_increment = '1' then
mem_addr <= mem_addr + 1;
mem_increment <= '0';
end if;
when LISTEN => --Receive bits
--In the event that RTS is lost, decrement the address and wait for RTS to come back
--if rs232_rts = '0' then
-- CurrState <= WAIT4RTS;
-- mem_addr <= mem_addr - 1;
--Otherwise, buffer the incoming data
--else
data_buf <= rs232_td & data_buf(data_buf'length-1 downto 1);
--If this is the last bit received, go to the next state
--Otherwise, decrement the bit counter
if data_buf_pos = 0 then
CurrState <= STOPANDWRITE;
else
data_buf_pos <= data_buf_pos - 1;
end if;
--end if;
when STOPANDWRITE => --hope that the signals were not screwed up in any way and write it to RAM
ram_data <= data_buf;
CurrState <= START;
mem_increment <= '1';
end case;
--else
--Release control of the memory (and turn off CTS)
-- mem_captured <= '0';
--end if;
end if;
end process;
--If memory is captured, that means we can signal the PC that we're ready to accept data
--rs232_cts <= mem_captured;
--Do not write directly to these outputs
ram_addr <= std_logic_vector(to_unsigned(mem_addr, ram_addr'length));
end Behavioral;
| unlicense | 1031ee22aace97c763eda4e25936ac20 | 0.602064 | 3.490995 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_scc.vhd | 1 | 48,409 | -------------------------------------------------------------------------------
-- axi_datamover_scc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_scc.vhd
--
-- Description:
-- This file implements the DataMover Lite Master Simple Command Calculator (SCC).
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_datamover_scc.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
--
-- History:
-- DET 04/19/2011 Initial Version for EDK 13.3
--
--
-- PVK 9/16/2011
-- ~~~~~
-- -- Removed unused signals from the sensitivity list and added missing
-- signals to sensitivity list in SCC_SM_COMB process.
-- ^^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_scc is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 64 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 2 to 64 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_MICRO_DMA : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4
-- Sets the width of the Tag field in the input command
);
port (
-- Clock and Reset inputs -------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------
-- Command Input Interface ---------------------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface ----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_sof : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
--
calc_error : Out std_logic --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
);
end entity axi_datamover_scc;
architecture implementation of axi_datamover_scc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_slice_width
--
-- Function Description:
-- Calculates the bits to rip from the Command BTT field to calculate
-- the LEN value output to the AXI Address Channel.
--
-------------------------------------------------------------------
function funct_get_slice_width (max_burst_len : integer) return integer is
Variable temp_slice_width : Integer := 0;
begin
case max_burst_len is
when 64 =>
temp_slice_width := 7;
when 32 =>
temp_slice_width := 6;
when 16 =>
temp_slice_width := 5;
when 8 =>
temp_slice_width := 4;
when 4 =>
temp_slice_width := 3;
when others => -- assume 16 dbeats is max LEN
temp_slice_width := 2;
end case;
Return (temp_slice_width);
end function funct_get_slice_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_btt_ls_unused (transfer_width : integer) return integer is
Variable temp_btt_ls_unused : Integer := 0; -- 8-bit stream
begin
case transfer_width is
when 64 =>
temp_btt_ls_unused := 3;
when 32 =>
temp_btt_ls_unused := 2;
when 16 =>
temp_btt_ls_unused := 1;
when others => -- assume 8-bit transfers
temp_btt_ls_unused := 0;
end case;
Return (temp_btt_ls_unused);
end function funct_get_btt_ls_unused;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
Constant AXI_BURST_FIXED : std_logic_vector(1 downto 0) := "00";
Constant AXI_BURST_INCR : std_logic_vector(1 downto 0) := "01";
Constant AXI_BURST_WRAP : std_logic_vector(1 downto 0) := "10";
Constant AXI_BURST_RESVD : std_logic_vector(1 downto 0) := "11";
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Constant BTT_SLICE_SIZE : integer := funct_get_slice_width(C_MAX_BURST_LEN);
Constant MAX_BURST_LEN_US : unsigned(BTT_SLICE_SIZE-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BTT_SLICE_SIZE);
Constant BTT_LS_UNUSED_WIDTH : integer := funct_get_btt_ls_unused(C_STREAM_DWIDTH);
Constant CMD_BTT_WIDTH : integer := BTT_SLICE_SIZE+BTT_LS_UNUSED_WIDTH;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_ZEROS : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
Constant BTT_SLICE_ONE : unsigned(BTT_SLICE_SIZE-1 downto 0) := TO_UNSIGNED(1, BTT_SLICE_SIZE);
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8; -- Number of bytes in the Stream
Constant LEN_WIDTH : integer := 8;
-- Type Declarations --------------------------------------------
type SCC_SM_STATE_TYPE is (
INIT,
POP_RECOVER,
GET_NXT_CMD,
CHK_AND_CALC,
PUSH_TO_AXI,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
signal sm_scc_state : SCC_SM_STATE_TYPE := INIT;
signal sm_scc_state_ns : SCC_SM_STATE_TYPE := INIT;
signal sm_pop_input_cmd : std_logic := '0';
signal sm_pop_input_cmd_ns : std_logic := '0';
signal sm_set_push2axi : std_logic := '0';
signal sm_set_push2axi_ns : std_logic := '0';
signal sm_set_error : std_logic := '0';
signal sm_set_error_ns : std_logic := '0';
Signal sm_scc_sm_ready : std_logic := '0';
Signal sm_scc_sm_ready_ns : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
signal sig_addr_data_rdy_pending : std_logic := '0';
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_load_input_cmd : std_logic := '0';
signal sig_cmd_reg_empty : std_logic := '0';
signal sig_cmd_reg_full : std_logic := '0';
signal sig_cmd_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_reg : std_logic := '0';
signal sig_cmd_burst_reg : std_logic_vector (1 downto 0) := "00";
signal sig_cmd_tag_reg : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_data_rdy4cmd : std_logic := '0';
signal sig_btt_raw : std_logic := '0';
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_is_zero_reg : std_logic := '0';
signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_strt_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_next_end_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_input_eof_reg : std_logic;
begin --(architecture implementation)
-- Assign calculation error output
calc_error <= sm_set_error;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= sig_cmd_reg_empty and sm_scc_sm_ready;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_next_tag ;
mstr2addr_addr <= sig_next_addr ;
mstr2addr_len <= sig_next_len ;
mstr2addr_size <= sig_next_size ;
mstr2addr_burst <= sig_cmd_burst_reg;
mstr2addr_cache <= sig_next_cache;
mstr2addr_user <= sig_next_user;
mstr2addr_cmd_valid <= sig_cmd2addr_valid;
mstr2addr_calc_error <= sm_set_error ;
mstr2addr_cmd_cmplt <= '1' ; -- Lite mode is always 1
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_next_tag ;
mstr2data_saddr_lsb <= sig_cmd_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_next_len ;
mstr2data_strt_strb <= sig_next_strt_strb;
mstr2data_last_strb <= sig_next_end_strb;
mstr2data_sof <= '1'; -- Lite mode is always 1 cmd
mstr2data_eof <= sig_input_eof_reg; -- Lite mode is always 1 cmd
mstr2data_cmd_cmplt <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_valid <= sig_cmd2data_valid;
mstr2data_calc_error <= sm_set_error;
-- Internal logic ------------------------------
sig_addr_data_rdy_pending <= sig_cmd2addr_valid or
sig_cmd2data_valid;
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
sig_load_input_cmd <= cmd2mstr_cmd_valid and
sig_cmd_reg_empty and
sm_scc_sm_ready;
sig_next_tag <= sig_cmd_tag_reg;
sig_next_addr <= sig_cmd_addr_reg;
sig_addr_data_rdy4cmd <= addr2mstr_cmd_ready and data2mstr_cmd_ready;
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_NO_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH = 0) generate
-- signals
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto 0));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value,
-- otheriwse subtract 1 from the BTT ripped value
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1;
end generate GEN_NO_RESIDUE_BITS;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_HAS_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_HAS_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH > 0) generate
-- signals
signal sig_btt_len_residue : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto BTT_LS_UNUSED_WIDTH));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
sig_btt_len_residue <= UNSIGNED(sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0));
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value
-- However if residue bits are zeroes then subtract
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1
when (sig_btt_len_residue = BTT_RESIDUE_ZEROS)
Else sig_len_btt_slice;
end generate GEN_HAS_RESIDUE_BITS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_CMD
--
-- Process Description:
-- Implements the input command holding registers
--
-------------------------------------------------------------
REG_INPUT_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sm_pop_input_cmd = '1') then
sig_cmd_btt_reg <= (others => '0');
sig_cmd_type_reg <= '0';
sig_cmd_addr_reg <= (others => '0');
sig_cmd_tag_reg <= (others => '0');
sig_btt_is_zero_reg <= '0';
sig_cmd_reg_empty <= '1';
sig_cmd_reg_full <= '0';
sig_input_eof_reg <= '0';
sig_cmd_burst_reg <= "00";
elsif (sig_load_input_cmd = '1') then
sig_cmd_btt_reg <= sig_cmd_btt_slice;
sig_cmd_type_reg <= cmd2mstr_command(CMD_TYPE_INDEX);
sig_cmd_addr_reg <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_reg <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_btt_is_zero_reg <= sig_btt_is_zero;
sig_cmd_reg_empty <= '0';
sig_cmd_reg_full <= '1';
sig_cmd_burst_reg <= sig_next_burst;
if (C_MICRO_DMA = 1) then
sig_input_eof_reg <= cmd2mstr_command(CMD_EOF_INDEX);
else
sig_input_eof_reg <= '1';
end if;
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_CMD;
-- Only Incrementing Burst type supported (per Interface_X guidelines)
sig_next_burst <= AXI_BURST_INCR when (cmd2mstr_command(CMD_TYPE_INDEX) = '1') else
AXI_BURST_FIXED;
sig_next_user <= cache2mstr_command (7 downto 4);
sig_next_cache <= cache2mstr_command (3 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_64
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 64-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_64 : if (C_STREAM_DWIDTH = 64) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_8BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 3;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0');
-- note 1 extra bit implied
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_8bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 64 bits wide and 8 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_8bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "0001" =>
sig_last_strb <= "00000001";
when "0010" =>
sig_last_strb <= "00000011";
when "0011" =>
sig_last_strb <= "00000111";
when "0100" =>
sig_last_strb <= "00001111";
when "0101" =>
sig_last_strb <= "00011111";
when "0110" =>
sig_last_strb <= "00111111";
when "0111" =>
sig_last_strb <= "01111111";
when others =>
sig_last_strb <= "11111111";
end case;
end process IMP_LAST_STRB_8bit;
end generate GEN_LEN_SDWIDTH_64;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_32
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 32-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_32 : if (C_STREAM_DWIDTH = 32) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_4BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 2;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_4bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 32 bits wide and 4 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_4bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "001" =>
sig_last_strb <= "0001";
when "010" =>
sig_last_strb <= "0011";
when "011" =>
sig_last_strb <= "0111";
when others =>
sig_last_strb <= "1111";
end case;
end process IMP_LAST_STRB_4bit;
end generate GEN_LEN_SDWIDTH_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_16
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 16-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_16 : if (C_STREAM_DWIDTH = 16) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_2BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 1;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_2bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 16 bits wide and 2 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_2bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "01" =>
sig_last_strb <= "01";
when others =>
sig_last_strb <= "11";
end case;
end process IMP_LAST_STRB_2bit;
end generate GEN_LEN_SDWIDTH_16;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_8
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 8-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_8 : if (C_STREAM_DWIDTH = 8) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_1BYTE;
begin
-- Assign the Address Channel Controller Qualifiers
sig_next_size <= AXI_SIZE2USE;
-- Assign the Data Channel Controller Qualifiers
sig_next_strt_strb <= (others => '1');
sig_next_end_strb <= (others => '1');
end generate GEN_LEN_SDWIDTH_8;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Ready control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sm_set_push2axi_ns = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Ready control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sm_set_push2axi_ns = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: SCC_SM_COMB
--
-- Process Description:
-- Implements combinational portion of state machine
--
-------------------------------------------------------------
SCC_SM_COMB : process (sm_scc_state,
cmd2mstr_cmd_valid,
sig_addr_data_rdy_pending,
sig_cmd_reg_full,
sig_btt_is_zero_reg
)
begin
-- Set default State machine outputs
sm_pop_input_cmd_ns <= '0';
sm_set_push2axi_ns <= '0';
sm_scc_state_ns <= sm_scc_state;
sm_set_error_ns <= '0';
sm_scc_sm_ready_ns <= '1';
case sm_scc_state is
----------------------------------------------------
when INIT =>
-- if (sig_addr_data_rdy4cmd = '1') then
if (cmd2mstr_cmd_valid = '1') then -- wait for first cmd valid after reset
sm_scc_state_ns <= GET_NXT_CMD; -- jump to get command
else
sm_scc_sm_ready_ns <= '0';
sm_scc_state_ns <= INIT; -- Stay in Init
End if;
----------------------------------------------------
when POP_RECOVER =>
sm_scc_state_ns <= GET_NXT_CMD; -- jump to next state
----------------------------------------------------
when GET_NXT_CMD =>
if (sig_cmd_reg_full = '1') then
sm_scc_state_ns <= CHK_AND_CALC; -- jump to next state
else
sm_scc_state_ns <= GET_NXT_CMD; -- stay in this state
end if;
----------------------------------------------------
when CHK_AND_CALC =>
sm_set_push2axi_ns <= '1'; -- Push the command to ADDR and DATA
if (sig_btt_is_zero_reg = '1') then
sm_scc_state_ns <= ERROR_TRAP; -- jump to error trap
sm_set_error_ns <= '1'; -- Set internal error flag
else
sm_scc_state_ns <= PUSH_TO_AXI;
end if;
----------------------------------------------------
when PUSH_TO_AXI =>
if (sig_addr_data_rdy_pending = '1') then
sm_scc_state_ns <= PUSH_TO_AXI; -- stay in this state
-- until both Addr and Data have taken commands
else
sm_pop_input_cmd_ns <= '1';
sm_scc_state_ns <= POP_RECOVER; -- jump back to fetch new cmd input
end if;
----------------------------------------------------
when ERROR_TRAP =>
sm_scc_state_ns <= ERROR_TRAP; -- stay in this state
sm_set_error_ns <= '1';
----------------------------------------------------
when others =>
sm_scc_state_ns <= INIT; -- error so always jump to init state
end case;
end process SCC_SM_COMB;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SCC_SM_REG
--
-- Process Description:
-- Implements registered portion of state machine
--
-------------------------------------------------------------
SCC_SM_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sm_scc_state <= INIT;
sm_pop_input_cmd <= '0' ;
sm_set_push2axi <= '0' ;
sm_set_error <= '0' ;
sm_scc_sm_ready <= '0' ;
else
sm_scc_state <= sm_scc_state_ns ;
sm_pop_input_cmd <= sm_pop_input_cmd_ns ;
sm_set_push2axi <= sm_set_push2axi_ns ;
sm_set_error <= sm_set_error_ns ;
sm_scc_sm_ready <= sm_scc_sm_ready_ns ;
end if;
end if;
end process SCC_SM_REG;
end implementation;
| bsd-2-clause | 67312e03de68267332d38cd454ad1925 | 0.426677 | 4.819693 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_sg_v4_1/hdl/src/vhdl/axi_sg_datamover.vhd | 1 | 51,672 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg.vhd
--
-- Description:
-- Top level VHDL wrapper for the AXI DataMover
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_mm2s_basic_wrap;
use axi_sg_v4_1.axi_sg_s2mm_basic_wrap;
-------------------------------------------------------------------------------
entity axi_sg_datamover is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_M_AXI_MM2S_ARID : Integer range 0 to 255 := 0;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_M_AXI_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_MM2S_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_M_AXIS_MM2S_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 16 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_MM2S_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_S2MM : Integer range 0 to 4 := 2;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Basic S2MM functionality
C_M_AXI_S2MM_AWID : Integer range 0 to 255 := 1;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_M_AXI_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_S2MM_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S_AXIS_S2MM_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 16 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the S2MM Command Interface
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if support for indeterminate packet lengths
-- are to be received on the input Stream interface
-- 0 = Omit support (User MUST transfer the exact number of
-- bytes on the Stream interface as specified in the BTT
-- field of the Corresponding DataMover Command)
-- 1 = Include support for indeterminate packet lengths
-- This causes FIFOs to be added and "Store and Forward"
-- behavior of the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_S2MM_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- S2MM (Write) Store and Forward function
-- 0 = Omit S2MM Store and Forward
-- 1 = Include S2MM Store and Forward
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 1;
C_ENABLE_EXTRA_FIELD : integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock input ----------------------------------
m_axi_mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
m_axi_mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
sg_ctl : in std_logic_vector (7 downto 0) ;
-- MM2S Halt request input control --------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------
-- Error discrete output -------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O ---------
m_axis_mm2s_cmdsts_aclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
s_axis_mm2s_cmd_tvalid : in std_logic; --
s_axis_mm2s_cmd_tready : out std_logic; --
s_axis_mm2s_cmd_tdata : in std_logic_vector(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_MM2S_ADDR_WIDTH+40)-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) ------------------------
m_axis_mm2s_sts_tvalid : out std_logic; --
m_axis_mm2s_sts_tready : in std_logic; --
m_axis_mm2s_sts_tdata : out std_logic_vector(7 downto 0); --
m_axis_mm2s_sts_tkeep : out std_logic_vector(0 downto 0); --
m_axis_mm2s_sts_tlast : out std_logic; --
--------------------------------------------------------------------
-- Address Posting contols -----------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
--------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------------------
m_axi_mm2s_arid : out std_logic_vector(C_M_AXI_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_mm2s_alock : out std_logic_vector(2 downto 0); --
-- m_axi_mm2s_acache : out std_logic_vector(4 downto 0); --
-- m_axi_mm2s_aqos : out std_logic_vector(3 downto 0); --
-- m_axi_mm2s_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------------
m_axi_mm2s_rdata : In std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0); --
m_axi_mm2s_rresp : In std_logic_vector(1 downto 0); --
m_axi_mm2s_rlast : In std_logic; --
m_axi_mm2s_rvalid : In std_logic; --
m_axi_mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -------------------------------------------------------
m_axis_mm2s_tdata : Out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_tkeep : Out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tlast : Out std_logic; --
m_axis_mm2s_tvalid : Out std_logic; --
m_axis_mm2s_tready : In std_logic; --
----------------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) ; --
-------------------------------------------------------------------------------
-- S2MM Primary Clock input ---------------------------------
m_axi_s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
m_axi_s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------
-- S2MM Halt request input control ------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
-----------------------------------------------------
-- S2MM Error discrete output ------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O -----------------
m_axis_s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) --------------------------------------------------
s_axis_s2mm_cmd_tvalid : in std_logic; --
s_axis_s2mm_cmd_tready : out std_logic; --
s_axis_s2mm_cmd_tdata : in std_logic_vector(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_S2MM_ADDR_WIDTH+40)-1 downto 0); --
-----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------------------------------------------------
m_axis_s2mm_sts_tvalid : out std_logic; --
m_axis_s2mm_sts_tready : in std_logic; --
m_axis_s2mm_sts_tdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
m_axis_s2mm_sts_tkeep : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
m_axis_s2mm_sts_tlast : out std_logic; --
-------------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O ----------------------------------------------------
m_axi_s2mm_awid : out std_logic_vector(C_M_AXI_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-------------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_s2mm__awlock : out std_logic_vector(2 downto 0); --
-- m_axi_s2mm__awcache : out std_logic_vector(4 downto 0); --
-- m_axi_s2mm__awqos : out std_logic_vector(3 downto 0); --
-- m_axi_s2mm__awregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O --------------------------------------------------
m_axi_s2mm_wdata : Out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); --
m_axi_s2mm_wstrb : Out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); --
m_axi_s2mm_wlast : Out std_logic; --
m_axi_s2mm_wvalid : Out std_logic; --
m_axi_s2mm_wready : In std_logic; --
-------------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -------------------------
m_axi_s2mm_bresp : In std_logic_vector(1 downto 0); --
m_axi_s2mm_bvalid : In std_logic; --
m_axi_s2mm_bready : Out std_logic; --
----------------------------------------------------------------------
-- S2MM AXI Slave Stream Channel I/O -------------------------------------------------------
s_axis_s2mm_tdata : In std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0); --
s_axis_s2mm_tkeep : In std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0); --
s_axis_s2mm_tlast : In std_logic; --
s_axis_s2mm_tvalid : In std_logic; --
s_axis_s2mm_tready : Out std_logic; --
---------------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
------------------------------------------------------------------------
);
end entity axi_sg_datamover;
architecture implementation of axi_sg_datamover is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_brst_len
--
-- Function Description:
-- This function is used to limit the parameterized max burst
-- databeats when the tranfer data width is 256 bits or greater.
-- This is required to keep from crossing the 4K byte xfer
-- boundary required by AXI. This process is further complicated
-- by the inclusion/omission of upsizers or downsizers in the
-- data path.
--
-------------------------------------------------------------------
function funct_clip_brst_len (param_burst_beats : integer;
mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
constant FCONST_SIZERS_ENABLED : boolean := (down_up_sizers_enabled > 0);
Variable fvar_max_burst_dbeats : Integer;
begin
-- coverage off
if (FCONST_SIZERS_ENABLED) then -- use MMap dwidth for calc
If (mmap_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (mmap_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (mmap_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit mmap width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
End if;
else -- use stream dwidth for calc
If (stream_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (stream_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (stream_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit stream width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
-- coverage on
End if;
end if;
Return (fvar_max_burst_dbeats);
end function funct_clip_brst_len;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_depth_16
--
-- Function Description:
-- This function is used to fix the Command and Status FIFO depths to
-- 16 entries when Async clocking mode is enabled. This is required
-- due to the way the async_fifo_fg.vhd design in proc_common is
-- implemented.
-------------------------------------------------------------------
function funct_fix_depth_16 (async_clocking_mode : integer;
requested_depth : integer) return integer is
Variable fvar_depth_2_use : Integer;
begin
-- coverage off
If (async_clocking_mode = 1) Then -- async mode so fix at 16
fvar_depth_2_use := 16;
Elsif (requested_depth > 16) Then -- limit at 16
fvar_depth_2_use := 16;
-- coverage on
Else -- use requested depth
fvar_depth_2_use := requested_depth;
End if;
Return (fvar_depth_2_use);
end function funct_fix_depth_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_min_btt_width
--
-- Function Description:
-- This function calculates the minimum required value
-- for the used width of the command BTT field.
--
-------------------------------------------------------------------
function funct_get_min_btt_width (max_burst_beats : integer;
bytes_per_beat : integer ) return integer is
Variable var_min_btt_needed : Integer;
Variable var_max_bytes_per_burst : Integer;
begin
var_max_bytes_per_burst := max_burst_beats*bytes_per_beat;
-- coverage off
if (var_max_bytes_per_burst <= 16) then
var_min_btt_needed := 5;
elsif (var_max_bytes_per_burst <= 32) then
var_min_btt_needed := 6;
-- coverage on
elsif (var_max_bytes_per_burst <= 64) then
var_min_btt_needed := 7;
-- coverage off
elsif (var_max_bytes_per_burst <= 128) then
var_min_btt_needed := 8;
elsif (var_max_bytes_per_burst <= 256) then
var_min_btt_needed := 9;
elsif (var_max_bytes_per_burst <= 512) then
var_min_btt_needed := 10;
elsif (var_max_bytes_per_burst <= 1024) then
var_min_btt_needed := 11;
elsif (var_max_bytes_per_burst <= 2048) then
var_min_btt_needed := 12;
elsif (var_max_bytes_per_burst <= 4096) then
var_min_btt_needed := 13;
else -- 8K byte range
var_min_btt_needed := 14;
end if;
-- coverage on
Return (var_min_btt_needed);
end function funct_get_min_btt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_xfer_bytes_per_dbeat
--
-- Function Description:
-- Calculates the nuber of bytes that will transfered per databeat
-- on the AXI4 MMap Bus.
--
-------------------------------------------------------------------
function funct_get_xfer_bytes_per_dbeat (mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
Variable temp_bytes_per_dbeat : Integer := 4;
begin
-- coverage off
if (down_up_sizers_enabled > 0) then -- down/up sizers are in use, use full mmap dwidth
temp_bytes_per_dbeat := mmap_transfer_bit_width/8;
-- coverage on
else -- No down/up sizers so use Stream data width
temp_bytes_per_dbeat := stream_transfer_bit_width/8;
end if;
Return (temp_bytes_per_dbeat);
end function funct_get_xfer_bytes_per_dbeat;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_btt_used
--
-- Function Description:
-- THis function makes sure the BTT width used is at least the
-- minimum needed.
--
-------------------------------------------------------------------
function funct_fix_btt_used (requested_btt_width : integer;
min_btt_width : integer) return integer is
Variable var_corrected_btt_width : Integer;
begin
-- coverage off
If (requested_btt_width < min_btt_width) Then
var_corrected_btt_width := min_btt_width;
-- coverage on
else
var_corrected_btt_width := requested_btt_width;
End if;
Return (var_corrected_btt_width);
end function funct_fix_btt_used;
-------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------
Constant MM2S_TAG_WIDTH : integer := 4;
Constant S2MM_TAG_WIDTH : integer := 4;
Constant MM2S_DOWNSIZER_ENABLED : integer := C_MM2S_INCLUDE_SF;
Constant S2MM_UPSIZER_ENABLED : integer := C_S2MM_INCLUDE_SF + C_S2MM_SUPPORT_INDET_BTT;
Constant MM2S_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_MM2S_BURST_SIZE,
C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant S2MM_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_S2MM_BURST_SIZE,
C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant MM2S_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_MM2S_STSCMD_IS_ASYNC,
C_MM2S_STSCMD_FIFO_DEPTH);
Constant S2MM_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_S2MM_STSCMD_IS_ASYNC,
C_S2MM_STSCMD_FIFO_DEPTH);
Constant MM2S_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant MM2S_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(MM2S_MAX_BURST_BEATS,
MM2S_BYTES_PER_BEAT);
Constant MM2S_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_MM2S_BTT_USED,
MM2S_MIN_BTT_NEEDED);
Constant S2MM_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant S2MM_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(S2MM_MAX_BURST_BEATS,
S2MM_BYTES_PER_BEAT);
Constant S2MM_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_S2MM_BTT_USED,
S2MM_MIN_BTT_NEEDED);
-- Signals
signal sig_mm2s_tstrb : std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mm2s_sts_tstrb : std_logic_vector(0 downto 0) := (others => '0');
signal sig_s2mm_tstrb : std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_s2mm_sts_tstrb : std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0) := (others => '0');
begin --(architecture implementation)
-------------------------------------------------------------
-- Conversion to tkeep for external stream connnections
-------------------------------------------------------------
-- MM2S Stream Output
m_axis_mm2s_tkeep <= sig_mm2s_tstrb ;
-- MM2S Status Stream Output
m_axis_mm2s_sts_tkeep <= sig_mm2s_sts_tstrb ;
-- S2MM Stream Input
sig_s2mm_tstrb <= s_axis_s2mm_tkeep ;
-- S2MM Status Stream Output
m_axis_s2mm_sts_tkeep <= sig_s2mm_sts_tstrb ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_BASIC
--
-- If Generate Description:
-- Instantiate the MM2S Basic Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_BASIC : if (C_INCLUDE_MM2S = 2) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_BASIC_WRAPPER
--
-- Description:
-- Read Basic Wrapper Instance
--
------------------------------------------------------------
I_MM2S_BASIC_WRAPPER : entity axi_sg_v4_1.axi_sg_mm2s_basic_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
sg_ctl => sg_ctl ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_BASIC;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_BASIC
--
-- If Generate Description:
-- Instantiate the S2MM Basic Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_BASIC : if (C_INCLUDE_S2MM = 2) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_BASIC_WRAPPER
--
-- Description:
-- Write Basic Wrapper Instance
--
------------------------------------------------------------
I_S2MM_BASIC_WRAPPER : entity axi_sg_v4_1.axi_sg_s2mm_basic_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
sg_ctl => sg_ctl ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_BASIC;
end implementation;
| bsd-2-clause | 2aec1b1709cabe00e54421e7044ab2fe | 0.408055 | 4.603706 | false | false | false | false |
Logistic1994/CPU | module_IR.vhd | 1 | 2,039 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:37:33 05/14/2015
-- Design Name:
-- Module Name: module_IR - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity module_IR is
port (
clk_IR: in std_logic;
nreset: in std_logic;
LD_IR1, LD_IR2, LD_IR3: in std_logic; -- ¿ØÖÆÐźÅ
nARen: in std_logic; -- ramµØÖ·¿ØÖÆÐźÅ
datai: in std_logic_vector(7 downto 0);
IR: out std_logic_vector(7 downto 0); -- IRÖ¸Áî±àÂë
PC: out std_logic_vector(11 downto 0); -- PCеØÖ·
ARo: out std_logic_vector(6 downto 0); -- RAM¶ÁдµØÖ·
ao: out std_logic;
RS, RD: out std_logic); -- Ô´¼Ä´æÆ÷ºÍÄ¿µÄ¼Ä´æÆ÷
end module_IR;
architecture Behavioral of module_IR is
signal thePC2AR: std_logic_vector(6 downto 0);
begin
process(nreset, clk_IR)
begin
if nreset = '0' then
thePC2AR <= (others => '0');
elsif rising_edge(clk_IR) then
if LD_IR1 = '1' then
IR <= datai;
RS <= datai(0);
RD <= datai(1);
ARo <= (others => 'Z');
ao <= '0';
elsif LD_IR2 = '1' then
PC(11 downto 8) <= datai(3 downto 0);
ARo <= (others => 'Z');
ao <= '0';
elsif LD_IR3 = '1' then
PC(7 downto 0) <= datai(7 downto 0);
thePC2AR <= datai(6 downto 0);
ARo <= (others => 'Z');
ao <= '0';
elsif nARen = '0' then
ARo <= thePC2AR;
ao <= '1';
else
ARo <= (others => 'Z');
ao <= '0';
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | 0a4bd22e7f291c84e9daf221b69cff20 | 0.562531 | 2.908702 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/sequential/rule_401_test_input.vhd | 1 | 1,812 |
architecture rtl of fifo is
begin
process begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1100" else
my_sig4 when input = "0010" else
'0';
my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when a = "0000" and func1(345) or
b = "1000" and func2(567) and
c = "00" else
sig1 when a = "1000" and func2(560) and
b = "0010" else
'0';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
-- Testing no code after assignment
my_signal <=
'1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
my_signal <=
(others => '0') when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
end process;
end architecture rtl;
| gpl-3.0 | 4600f989e1e9873f9ca630d93d3482f6 | 0.510486 | 3.330882 | false | false | false | false |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/cascaded_integrator_comb/cic_compiler_v4_0/hdl/cic_compiler_v4_0_hdl_comps.vhd | 1 | 17,132 | `protect begin_protected
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| mit | 19f9cdde6bfc7e0352e4fe374cdeaa86 | 0.938361 | 1.875219 | false | false | false | false |
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`protect end_protected
| mit | 635ab01a9297cceb2a735a1c5388f346 | 0.938123 | 1.872271 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/ramfifo/wr_logic_pkt_fifo.vhd | 2 | 31,831 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 21824)
`protect data_block
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85P3T65K1YS6uD2QRJRyOi7SwMFGxbMORnBQWpU+oEsuIpR8x4RFZ08FSfmrt+Xkik2vgYzztZG/
vbDas5JiGOqaucSvmlYwAY0GNcTzFxcK3FMYxkGMFkWvJCoQW15VtMIcqeytMjFJG4spKk9FyAKC
wZc6V6w0N16T29FUXHgSWJDBeavJgmRt/PTHtnW+VlHU23wdjypsC/9durWuhooyb3eP9GjP0mRG
dE7nRtHYmDZDwU67AUbs+m0E+CJ889GLGuULehMQercSyJKWFL7kA6FXLt3o+Ov5T77JdIwkajnr
T6KFhSq2GmfZuoAuKNlMoWnI2fN6EJVhPL0xbzdHHEa3bwYBN6YmNYZrMgkRkzKaz71y3Vj5yp+e
mBREN2olFJBCn8eXLCDJl9dAWTduPCJI0JCI+1COAIXQNDH1Ma/sLi4PBFwGOi5UR1tnwFDolyEH
lUfaM7atiEgTW5sYszS3M7XY+2ZunixNczOAoECzTZYes77QhI16s4obtXfyDDVbf9Y=
`protect end_protected
| bsd-2-clause | 181b9ebf3a280bda6dc02317e6806717 | 0.945462 | 1.847954 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/case/rule_019_test_input.fixed.vhd | 1 | 596 |
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_1;
PROC_2 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1=>
a <= b;
b <= c;
c <= d;
end CASE;
end process PROC_2;
PROC_2 : process (a, b, c) is
begin
-- Some Comment
case boolean_1 is
when STATE_1=>
a <= b;
b <= c;
c <= d;
end CASE;
end process PROC_2;
end architecture ARCH;
| gpl-3.0 | e86ffea51fb6f56230f07764ddfb4d77 | 0.474832 | 3.274725 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/generic/rule_014_test_input.fixed.vhd | 1 | 330 |
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
end entity FIFO;
-- Violation below
entity FIFO is
generic(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32
);
port(
i_port1 : in std_logic;
i_port2 : in std_logic
);
end entity FIFO;
| gpl-3.0 | 4371e458585bcd589f0e167089fb1dcd | 0.575758 | 3.173077 | false | false | false | false |
NicoLedwith/Dr.AluOpysel | RAT_MCU/VGA_Stuff/vga_clk_div.vhd | 1 | 805 | --
-- Declares a clock divider to synchronize the VGA scanlines
--
-- Original author: unknown
--
-- Peter Heatwole, Aaron Barton
-- CPE233, Winter 2012, CalPoly
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity vga_clk_div is
port(clk : in std_logic;
clkout : out std_logic);
end vga_clk_div;
architecture Behavioral of vga_clk_div is
signal tmp_clkf : std_logic;
begin
my_div_fast: process (clk,tmp_clkf)
variable div_cnt : integer := 0;
begin
if (rising_edge(clk)) then
if (div_cnt = 0) then
tmp_clkf <= not tmp_clkf;
div_cnt := 0;
else
div_cnt := div_cnt + 1;
end if;
end if;
clkout <= tmp_clkf;
end process my_div_fast;
end Behavioral;
| mit | d770ff1fcc652970c812ba38373945a8 | 0.565217 | 3.396624 | false | false | false | false |
rjarzmik/mips_processor | MEM/Memory_access.vhd | 1 | 15,056 | -------------------------------------------------------------------------------
-- Title : Memory access stage
-- Project :
-------------------------------------------------------------------------------
-- File : memory_access.vhd
-- Author : Simon Desfarges
-- Company :
-- Created : 2016-11-24
-- Last update: 2017-01-04
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-- This is the memory access pipeline stage.
-- Depending on operation to do (load/store), does the corresponding memory
-- access (ie write or read the L1 cache). This module outputs the read memory
-- data to store in the register. It outputs a 'stall' signal for earlier
-- stages in case of memory latency > 1 clock cycle.
--
-- Concerning Stores, the latency is minimum 2 cycles: 1 to set @, data, we and
-- 1 to get the write acknoledgement. In my opinion, this part should be done
-- in WB stage, because 'store' is a kind of 'commit'. This instruction is not
-- really killable at this stage as a store is atomic and lasts more than 1
-- cycle. In a first approach, this stage should not need kill (may need it
-- when exception occurs).
-- Another optimization which can reduce the latency is to reverse the "WR ACK"
-- logic: instead of ACK the write, use a 'MEM BUSY' signal. It jumps to '1' if
-- the memory cache is busy (ie cache miss). If the cache is not busy, the
-- write en transaction is registered (need to maintain the data to write for
-- only one cycle). The 'need_stall' signal is set to 1 if we have a store
-- instruction AND the cache is not busy. The miss is hidden by others
-- instructions.
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-11-24 1.0 simon Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.cpu_defs.all;
use work.instruction_defs.all;
-------------------------------------------------------------------------------
entity Memory_access is
generic (
ADDR_WIDTH : integer := 32;
DATA_WIDTH : integer := 32
);
port (
clk : in std_logic; -- input clk
rst : in std_logic; -- input async reset
stall_req : in std_logic;
kill_req : in std_logic;
o_exception : out std_logic; -- An exception happened in the module. The
-- only 'supported' exception is when a store
-- is killed.
i_reg1 : in register_port_type; -- Memory address to access
i_reg2 : in register_port_type; -- not used, to be fwded
i_mem_op : in memory_op_type;
i_mem_data : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- Data to
-- store in memory
-- Carry-over signals
i_is_jump : in std_logic; -- not used, to be fwded
i_jump_target : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- not used, to be fwded
i_instr_tag : in instr_tag_t;
o_reg1 : out register_port_type;
o_reg2 : out register_port_type;
o_jump_target : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
o_is_jump : out std_logic;
o_m0_instr_tag : out instr_tag_t;
o_m1_instr_tag : out instr_tag_t;
o_m2_instr_tag : out instr_tag_t;
-- Control hazard outputs. Needed to check RAW hazards
o_stage1_reg1 : out register_port_type;
o_stage1_reg2 : out register_port_type;
o_stage2_reg1 : out register_port_type;
o_stage2_reg2 : out register_port_type;
-- Memory interface
i_mem_rd_valid : in std_logic;
i_mem_rd_data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
o_mem_wr_en : out std_logic;
o_mem_word_width : out std_logic; -- Actual width of the word to be
-- written. 1 -> 32 bits, 0 -> 8 bits (LSB)
i_mem_wr_ack : in std_logic;
o_mem_addr : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
o_mem_wr_data : out std_logic_vector(DATA_WIDTH - 1 downto 0);
o_need_stall : out std_logic;
-- debug signals
i_dbg_mem_pc : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
o_dbg_mem0_pc : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
o_dbg_mem1_pc : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
o_dbg_mem2_pc : out std_logic_vector(ADDR_WIDTH - 1 downto 0)
);
end entity Memory_access;
architecture rtl of Memory_access is
-- This first version has a minimal latency of 3 clk: 1 clk to put input @ to
-- memory bus @, 1 clk to retrieve corresponding data from memory and a last
-- one to register it on the output. The
-- o_need_stall signal is not registered because we need to stall the earlier
-- stages with no delay if memory access has a latency > 1 clk.
signal r1_reg1 : register_port_type;
signal r1_reg2 : register_port_type;
signal r1_mem_op : memory_op_type;
signal r1_is_jump : std_logic;
signal r1_jump_target : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal r1_instr_tag : instr_tag_t;
signal r2_reg1 : register_port_type;
signal r2_reg2 : register_port_type;
signal r2_mem_op : memory_op_type;
signal r2_is_jump : std_logic;
signal r2_jump_target : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal r2_instr_tag : instr_tag_t;
signal r1_dbg_mem_pc : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal r2_dbg_mem_pc : std_logic_vector(ADDR_WIDTH - 1 downto 0);
-- Memory interface internal use.
signal s_mem_wr_en : std_logic;
signal s_mem_word_width : std_logic;
signal s_mem_addr : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal s_mem_wr_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal s_need_stall : std_logic;
signal s_mem_op_load : std_logic;
signal s_mem_op_store : std_logic;
begin -- architecture rtl
-- Output internal registers for the control hazard module.
o_stage1_reg1 <= r1_reg1;
o_stage1_reg2 <= r1_reg2;
o_stage2_reg1 <= r2_reg1;
o_stage2_reg2 <= r2_reg2;
o_mem_wr_en <= s_mem_wr_en;
o_mem_word_width <= s_mem_word_width;
o_mem_addr <= s_mem_addr;
o_mem_wr_data <= s_mem_wr_data;
o_need_stall <= s_need_stall;
-- stall if there is a read mem access taking longer than 1 clk or a wr
-- access and data not ACKed.
s_need_stall <= (not rst)
and (
(s_mem_op_load and not i_mem_rd_valid)
or (s_mem_op_store and not i_mem_wr_ack)
);
with r1_mem_op select
s_mem_op_load <=
'0' when none | storew | store8,
'1' when others;
with r1_mem_op select
s_mem_op_store <=
'1' when storew | store8,
'0' when others;
-- purpose: because of memory latency we need to register inpout
-- signal to easily retrieve them for output.
-- type : sequential
-- inputs : clk, rst
-- outputs:
internal_regs : process (clk, rst) is
begin -- process internal regs
if rst = '1' then -- asynchronous reset (active high)
r1_mem_op <= none;
r1_jump_target <= (others => '0');
r1_is_jump <= '0';
r1_reg1.we <= '0';
r1_reg1.idx <= 0;
r1_reg1.data <= (others => '0');
r1_reg2.we <= '0';
r1_reg2.idx <= 0;
r1_reg2.data <= (others => '0');
r1_instr_tag <= INSTR_TAG_NONE;
r1_dbg_mem_pc <= (others => 'X');
r2_mem_op <= none;
r2_jump_target <= (others => '0');
r2_is_jump <= '0';
r2_reg1.we <= '0';
r2_reg1.idx <= 0;
r2_reg1.data <= (others => '0');
r2_reg2.we <= '0';
r2_reg2.idx <= 0;
r2_reg2.data <= (others => '0');
r2_instr_tag <= INSTR_TAG_NONE;
r2_dbg_mem_pc <= (others => 'X');
elsif rising_edge(clk) then -- rising clock edge
if kill_req = '1' then
r1_mem_op <= none;
r1_jump_target <= (others => '0');
r1_is_jump <= '0';
r1_reg1.we <= '0';
r1_reg1.idx <= 0;
r1_reg1.data <= (others => '0');
r1_reg2.we <= '0';
r1_reg2.idx <= 0;
r1_reg2.data <= (others => '0');
r1_instr_tag <= INSTR_TAG_NONE;
r1_dbg_mem_pc <= (others => 'X');
r2_mem_op <= none;
r2_jump_target <= (others => '0');
r2_is_jump <= '0';
r2_reg1.we <= '0';
r2_reg1.idx <= 0;
r2_reg1.data <= (others => '0');
r2_reg2.we <= '0';
r2_reg2.idx <= 0;
r2_reg2.data <= (others => '0');
r2_instr_tag <= INSTR_TAG_NONE;
r2_dbg_mem_pc <= (others => 'X');
elsif stall_req = '0' then
if s_need_stall = '0' then
r1_reg1.we <= i_reg1.we;
r1_reg1.idx <= i_reg1.idx;
r1_reg1.data <= i_reg1.data;
r1_reg2.we <= i_reg2.we;
r1_reg2.idx <= i_reg2.idx;
r1_reg2.data <= i_reg2.data;
r1_mem_op <= i_mem_op;
r1_is_jump <= i_is_jump;
r1_jump_target <= i_jump_target;
r1_instr_tag <= i_instr_tag;
r1_dbg_mem_pc <= i_dbg_mem_pc;
r2_reg1.we <= r1_reg1.we;
r2_reg1.idx <= r1_reg1.idx;
r2_reg1.data <= r1_reg1.data;
r2_reg2.we <= r1_reg2.we;
r2_reg2.idx <= r1_reg2.idx;
r2_reg2.data <= r1_reg2.data;
r2_mem_op <= r1_mem_op;
r2_is_jump <= r1_is_jump;
r2_jump_target <= r1_jump_target;
r2_instr_tag <= r1_instr_tag;
r2_dbg_mem_pc <= r1_dbg_mem_pc;
end if;
end if;
end if;
end process internal_regs;
-- purpose: According to memory_operation, do the right memory access
-- type : sequential
-- inputs : clk, rst
-- outputs:
process (clk, rst) is
begin -- process
if rst = '1' then -- asynchronous reset (active high)
s_mem_wr_en <= '0';
s_mem_word_width <= '0';
s_mem_addr <= (others => '0');
s_mem_wr_data <= (others => '0');
elsif rising_edge(clk) then -- rising clock edge
if kill_req = '1' then
s_mem_wr_en <= '0';
elsif stall_req = '0' then
if s_need_stall = '0' then
case i_mem_op is
when loadw =>
s_mem_addr <= i_reg1.data;
s_mem_wr_en <= '0';
when load8 =>
s_mem_addr <= i_reg1.data;
s_mem_wr_en <= '0';
when load8_signextend32 =>
s_mem_addr <= i_reg1.data;
s_mem_wr_en <= '0';
when storew =>
s_mem_addr <= i_reg1.data;
s_mem_wr_data <= i_mem_data;
s_mem_wr_en <= '1';
s_mem_word_width <= '1';
when store8 =>
s_mem_addr <= i_reg1.data;
s_mem_wr_data(DATA_WIDTH - 1 downto 8) <= (others => '0');
s_mem_wr_data(7 downto 0) <= i_mem_data(7 downto 0);
s_mem_wr_en <= '1';
s_mem_word_width <= '0';
when others =>
s_mem_wr_en <= '0';
end case;
end if;
end if;
end if;
end process;
-- purpose: Outputs Mem datas in registers. Masks/sign extend datas.
-- type : sequential
-- inputs : clk, rst
-- outputs:
process (clk, rst) is
begin
if rst = '1' then
o_reg1.idx <= 0;
o_reg1.we <= '0';
o_reg1.data <= (others => '0');
o_reg2.idx <= 0;
o_reg2.we <= '0';
o_reg2.data <= (others => '0');
o_jump_target <= (others => '0');
o_is_jump <= '0';
o_exception <= '0';
elsif rising_edge(clk) then
o_exception <= '0';
if kill_req = '1' then -- outputs a NOP
o_reg1.we <= '0';
o_reg2.we <= '0';
o_is_jump <= '0';
if (r2_mem_op = store8
or r2_mem_op = storew) then -- For now a store cannot be killed.
-- (because it is hard to roll-back the
-- memory transaction).
o_exception <= '1';
end if;
elsif stall_req = '0' then
o_reg1.idx <= r2_reg1.idx;
if i_mem_rd_valid = '1'
and (r2_mem_op = load8_signextend32
or r2_mem_op = load8
or r2_mem_op = loadw)
then
o_reg1.we <= '1';
else
o_reg1.we <= r2_reg1.we;
end if;
if i_mem_rd_valid = '1' then
case r2_mem_op is
when loadw =>
o_reg1.data <= i_mem_rd_data;
when load8 =>
o_reg1.data (DATA_WIDTH - 1 downto 8) <= (others => '0');
o_reg1.data (7 downto 0) <= i_mem_rd_data (7 downto 0);
when load8_signextend32 =>
o_reg1.data (DATA_WIDTH - 1 downto 8) <= (others => i_mem_rd_data(7));
o_reg1.data (7 downto 0) <= i_mem_rd_data (7 downto 0);
when others =>
o_reg1.data <= r2_reg1.data;
end case;
else
o_reg1.data <= r2_reg1.data;
end if;
o_reg2 <= r2_reg2;
o_jump_target <= r2_jump_target;
o_is_jump <= r2_is_jump;
end if;
end if;
end process;
instr_tags : process(clk, rst, kill_req, stall_req, r1_instr_tag,
r2_instr_tag)
begin
if rst = '1' then
o_m0_instr_tag <= INSTR_TAG_NONE;
o_m1_instr_tag <= INSTR_TAG_NONE;
o_m2_instr_tag <= INSTR_TAG_NONE;
elsif rising_edge(clk) then
if kill_req = '1' then
o_m0_instr_tag <= INSTR_TAG_NONE;
o_m1_instr_tag <= INSTR_TAG_NONE;
o_m2_instr_tag <= INSTR_TAG_NONE;
elsif stall_req = '1' or s_need_stall = '1' then
else
o_m2_instr_tag <= r2_instr_tag;
end if;
end if;
o_m0_instr_tag <= r1_instr_tag;
o_m1_instr_tag <= r2_instr_tag;
end process instr_tags;
debug : process (clk, rst, r1_dbg_mem_pc, r2_dbg_mem_pc) is
begin -- process debug
if rst = '1' then -- asynchronous reset (active low)
o_dbg_mem0_pc <= (others => 'X');
o_dbg_mem1_pc <= (others => 'X');
o_dbg_mem2_pc <= (others => 'X');
elsif rising_edge(clk) then -- rising clock edge
if kill_req = '1' then
o_dbg_mem0_pc <= (others => 'X');
o_dbg_mem1_pc <= (others => 'X');
o_dbg_mem2_pc <= (others => 'X');
elsif stall_req = '1' or s_need_stall = '1' then
else
o_dbg_mem2_pc <= r2_dbg_mem_pc;
end if;
end if;
o_dbg_mem0_pc <= r1_dbg_mem_pc;
o_dbg_mem1_pc <= r2_dbg_mem_pc;
end process debug;
end architecture rtl;
| gpl-3.0 | d91434d55666cb23b21713d3f84917eb | 0.512553 | 3.146499 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/styles/jcl/c16/Board_cpu.fixed.vhd | 1 | 4,459 | --
-- This is the top level VHDL file.
--
-- It iobufs for bidirational signals (towards an optional
-- external fast SRAM.
--
-- Pins fit the AVNET Virtex-E Evaluation board
--
-- For other boards, change pin assignments in this file.
--
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.cpu_pack.all;
library UNISIM;
use unisim.vcomponents.all;
entity BOARD_CPU is
port (
CLK40 : in std_logic;
SWITCH : in std_logic_vector(9 downto 0);
SER_IN : in std_logic;
SER_OUT : out std_logic;
TEMP_SPO : in std_logic;
TEMP_SPI : out std_logic;
CLK_OUT : out std_logic;
LED : out std_logic_vector(7 downto 0);
ENABLE_N : out std_logic;
DEACTIVATE_N : out std_logic;
TEMP_CE : out std_logic;
TEMP_SCLK : out std_logic;
SEG1 : out std_logic_vector(7 downto 0);
SEG2 : out std_logic_vector(7 downto 0);
XM_ADR : out std_logic_vector(14 downto 0);
XM_CE_N : out std_logic;
XM_OE_N : out std_logic;
XM_WE_N : inout std_logic;
XM_DIO : inout std_logic_vector(7 downto 0)
);
end entity BOARD_CPU;
architecture BEHAVIORAL of BOARD_CPU is
component CPU is
port (
CLK_I : in std_logic;
SWITCH : in std_logic_vector(9 downto 0);
SER_IN : in std_logic;
SER_OUT : out std_logic;
TEMP_SPO : in std_logic;
TEMP_SPI : out std_logic;
TEMP_CE : out std_logic;
TEMP_SCLK : out std_logic;
SEG1 : out std_logic_vector(7 downto 0);
SEG2 : out std_logic_vector( 7 downto 0);
LED : out std_logic_vector( 7 downto 0);
XM_ADR : out std_logic_vector(15 downto 0);
XM_RDAT : in std_logic_vector( 7 downto 0);
XM_WDAT : out std_logic_vector( 7 downto 0);
XM_WE : out std_logic;
XM_CE : out std_logic
);
end component;
signal xm_wdat : std_logic_vector( 7 downto 0);
signal xm_rdat : std_logic_vector( 7 downto 0);
signal mem_t : std_logic;
signal xm_we : std_logic;
signal we_n : std_logic;
signal del_we_n : std_logic;
signal xm_ce : std_logic;
signal lclk : std_logic;
begin
CP : CPU
port map (
CLK_I => CLK40,
SWITCH => SWITCH,
SER_IN => SER_IN,
SER_OUT => SER_OUT,
TEMP_SPO => TEMP_SPO,
TEMP_SPI => TEMP_SPI,
XM_ADR(14 downto 0) => XM_ADR,
XM_ADR(15) => open,
XM_RDAT => xm_rdat,
XM_WDAT => xm_wdat,
XM_WE => xm_we,
XM_CE => xm_ce,
TEMP_CE => TEMP_CE,
TEMP_SCLK => TEMP_SCLK,
SEG1 => SEG1,
SEG2 => SEG2,
LED => LED
);
ENABLE_N <= '0';
DEACTIVATE_N <= '1';
CLK_OUT <= lclk;
mem_t <= del_we_n; -- active low
we_n <= not xm_we;
XM_OE_N <= xm_we;
XM_CE_N <= not xm_ce;
P147 : IOBUF
port map (
I => xm_wdat(7),
O => xm_rdat(7),
T => mem_t,
IO => XM_DIO(7)
);
P144 : IOBUF
port map (
I => xm_wdat(0),
O => xm_rdat(0),
T => mem_t,
IO => XM_DIO(0)
);
P142 : IOBUF
port map (
I => xm_wdat(6),
O => xm_rdat(6),
T => mem_t,
IO => XM_DIO(6)
);
P141 : IOBUF
port map (
I => xm_wdat(1),
O => xm_rdat(1),
T => mem_t,
IO => XM_DIO(1)
);
P140 : IOBUF
port map (
I => xm_wdat(5),
O => xm_rdat(5),
T => mem_t,
IO => XM_DIO(5)
);
P139 : IOBUF
port map (
I => xm_wdat(2),
O => xm_rdat(2),
T => mem_t,
IO => XM_DIO(2)
);
P133 : IOBUF
port map (
I => xm_wdat(4),
O => xm_rdat(4),
T => mem_t,
IO => XM_DIO(4)
);
P131 : IOBUF
port map (
I => xm_wdat(3),
O => xm_rdat(3),
T => mem_t,
IO => XM_DIO(3)
);
P63 : IOBUF
port map (
I => we_n,
O => del_we_n,
T => '0',
IO => XM_WE_N
);
process (CLK40) is
begin
if (rising_edge(CLK40)) then
lclk <= not lclk;
end if;
end process;
end architecture BEHAVIORAL;
| gpl-3.0 | c2572194c23e3e51750cbbcd400bfbf9 | 0.469163 | 2.951026 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/generic/rule_010_test_input.fixed_move_left.vhd | 1 | 441 |
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32) -- Comment
;
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
-- Violation below
entity FIFO is
GENERIC(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32); -- Comment should stay
PORT (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1');
end entity FIFO;
| gpl-3.0 | 519369657c7ac29f0734acf24a45490a | 0.575964 | 3.15 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/vhdlFile/exit_statement/classification_test_input.vhd | 1 | 384 |
architecture RTL of ENTITY_NAME is
begin
process
begin
EXIT_LABEL : exit loop_label when a(23 downto 5) = 20;
exit loop_label when a(23 downto 5) = 20;
EXIT_LABEL : exit when a(23 downto 5) = 20;
exit when a(23 downto 5) = 20;
EXIT_LABEL : exit loop_label;
exit loop_label;
exit;
exit when a <= b;
end process;
end architecture RTL;
| gpl-3.0 | f1c838b771babf62f3ce579f6b1642ab | 0.622396 | 3.368421 | false | false | false | false |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/xbip_utils_v3_0/hdl/xcc_utils_v3_0.vhd | 3 | 7,255 | `protect begin_protected
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`protect end_protected
| mit | b5df04fa47f3b0f3f5043f463429cbe1 | 0.911509 | 1.952368 | false | false | false | false |
wklimann/PCM3168 | PCM3168/I2S_OUT.vhd | 1 | 3,429 | ---------------------------------------------------------------------------------
-- Engineer: Klimann Wendelin
--
-- Create Date: 08:36:20 11/Okt/2013
-- Design Name: i2s_out
--
-- Description:
--
-- This module provides a bridge between an I2S serial device (audio ADC, S/PDIF
-- Decoded data) and a parallel device (microcontroller, IP block).
--
-- It's coded as a generic VHDL entity, so developer can choose the proper signal
-- width (8/16/24/32 bit)
--
-- Input takes:
-- -I2S Bit Clock
-- -I2S LR Clock (Left/Right channel indication)
-- -DATA_L / DATA_R parallel inputs
--
-- Output provides:
-- -I2S Data
-- -DATA_RDY output ready signals.
--
--
-- The data from the parallel inputs is shifted to the I2S data output
--
--------------------------------------------------------------------------------
-- I2S Waveform summary
--
-- BIT_CK __ __ __ __ __ __ __ __ __
-- | 1|__| 2|_| 3|__| 4|__| 5|__... ... |32|__| 1|__| 2|__| 3| ...
--
-- LR_CK ... ... ___________________
-- ____________L_Channel_Data______________| R Channel Data ...
--
-- DATA x< 00 ><D24><D22><D21><D20> ... ... < 00 ><D24><D23> ...
--
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity i2s_out is
-- width: How many bits (from MSB) are gathered from the serial I2S input
generic(width : integer := 24);
port(
-- I2S ports
LR_CLK : in std_logic; --Left/Right indicator clock
BIT_CLK : in std_logic; --Bit clock
DOUT : out std_logic; --Data Output
-- Control ports
RESET : in std_logic; --Asynchronous Reset (Active Low)
-- Parallel ports
-- use (width-1 downto 0); for big endian fotmat
-- or (0 to width-1) for little endian
DATA_L : in std_logic_vector(0 to width-1);
DATA_R : in std_logic_vector(0 to width-1);
-- Output status ports
DATA_RDY_L : out std_logic; --Falling edge means data is ready
DATA_RDY_R : out std_logic --Falling edge means data is ready
);
end i2s_out;
architecture rtl of i2s_out is
--signals
signal counter : integer range 0 to width;
signal s_current_lr : std_logic;
begin
-- serial to parallel interface
i2s_out: process(RESET, BIT_CLK, LR_CLK, DATA_L, DATA_R)
begin
if(RESET = '0') then
counter <= 0;
s_current_lr <= '0';
DATA_RDY_L <= '0';
DATA_RDY_R <= '0';
DOUT <= '0';
elsif(BIT_CLK'event and BIT_CLK = '0') then
if(s_current_lr = LR_CLK) then
if(s_current_lr = '1') then
DOUT <= DATA_R(counter);
else
DOUT <= DATA_L(counter);
end if;
if (counter < width-1) then
counter <= counter + 1;
else
-- if there is a failure in the clk signals rate -> send 0 to DOUT
DOUT <= '0';
end if;
-- reset the DATA_RDY_x signals
DATA_RDY_L <= '0';
DATA_RDY_R <= '0';
-- if there is a change in the LR_CLK signal enter the else branch
else
if(s_current_lr = '1') then
DOUT <= DATA_R(counter);
DATA_RDY_R <= '1';
else
DOUT <= DATA_L(counter);
DATA_RDY_L <= '1';
end if;
counter <= 0;
s_current_lr <= LR_CLK;
end if; -- (s_current_lr = LR_CLK)
end if; -- reset / rising_edge
end process i2s_out;
end rtl;
| gpl-2.0 | 97852d7cf734c938d1171b2a3f6adea4 | 0.507145 | 3.163284 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_bram_ctrl_0_bram_0/daala_zynq_axi_bram_ctrl_0_bram_0/simulation/random.vhd | 1 | 4,108 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v8_0 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
| bsd-2-clause | 52a7c4baee733bdeebe7aa57bf26dff8 | 0.59445 | 4.711009 | false | false | false | false |
Yarr/Yarr-fw | rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/sim/wr_data_gen.vhd | 20 | 18,946 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: wr_data_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose:
-- Reference:
-- Revision History:
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity wr_data_gen is
generic (
TCQ : TIME := 100 ps;
FAMILY : string := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MEM_BURST_LEN : integer := 8;
MODE : string := "WR"; --"WR", "RD"
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic; --
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0); -- "00" = bram;
cmd_rdy_o : out std_logic; -- ready to receive command. It should assert when data_port is ready at the // beginning and will be deasserted once see the cmd_valid_i is asserted.
-- And then it should reasserted when
-- it is generating the last_word.
cmd_valid_i : in std_logic; -- when both cmd_valid_i and cmd_rdy_o is high, the command is valid.
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
last_word_o : out std_logic;
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- generated address used to determine data pattern.
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0); -- generated burst length for control the burst data
data_rdy_i : in std_logic; -- connect from mcb_wr_full when used as wr_data_gen
-- connect from mcb_rd_empty when used as rd_data_gen
-- When both data_rdy and data_valid is asserted, the ouput data is valid.
data_valid_o : out std_logic; -- connect to wr_en or rd_en and is asserted whenever the
-- pattern is available.
data_o : out std_logic_vector(DWIDTH - 1 downto 0); -- generated data pattern
data_wr_end_o : out std_logic
);
end entity wr_data_gen;
architecture trans of wr_data_gen is
COMPONENT sp6_data_gen IS
GENERIC (
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS";
NUM_DQ_PINS : INTEGER := 8;
COLUMN_WIDTH : INTEGER := 10
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
cmd_startA : IN STD_LOGIC;
cmd_startB : IN STD_LOGIC;
cmd_startC : IN STD_LOGIC;
cmd_startD : IN STD_LOGIC;
cmd_startE : IN STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH - 1 downto 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
user_burst_cnt : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
fifo_rdy_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0)
);
END COMPONENT;
COMPONENT v6_data_gen IS
GENERIC (
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
MEM_BURST_LEN : integer := 8;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS";
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3;
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
cmd_startA : IN STD_LOGIC;
cmd_startB : IN STD_LOGIC;
cmd_startC : IN STD_LOGIC;
cmd_startD : IN STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH - 1 downto 0);
cmd_startE : IN STD_LOGIC;
m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
user_burst_cnt : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
fifo_rdy_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(NUM_DQ_PINS*4 - 1 DOWNTO 0)
);
END COMPONENT;
signal data : std_logic_vector(DWIDTH - 1 downto 0);
signal cmd_rdy : std_logic;
signal cmd_rdyB : std_logic;
signal cmd_rdyC : std_logic;
signal cmd_rdyD : std_logic;
signal cmd_rdyE : std_logic;
signal cmd_rdyF : std_logic;
signal cmd_start : std_logic;
signal cmd_startB : std_logic;
signal cmd_startC : std_logic;
signal cmd_startD : std_logic;
signal cmd_startE : std_logic;
signal cmd_startF : std_logic;
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal user_burst_cnt : std_logic_vector(6 downto 0);
signal walk_cnt : std_logic_vector(2 downto 0);
signal fifo_not_full : std_logic;
signal i : integer;
signal j : integer;
signal w3data : std_logic_vector(31 downto 0);
-- counter to count user burst length
-- bl_i;
signal u_bcount_2 : std_logic;
signal last_word_t : std_logic;
-- Declare intermediate signals for referenced outputs
signal last_word_o_xhdl1 : std_logic;
signal data_o_xhdl0 : std_logic_vector(DWIDTH - 1 downto 0);
signal tpt_hdata_xhdl2 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
begin
-- Drive referenced outputs
last_word_o <= last_word_o_xhdl1;
data_o <= data_o_xhdl0;
fifo_not_full <= data_rdy_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (((user_burst_cnt = "0000010") or (((cmd_start = '1') and (bl_i = "000001")) and FAMILY = "VIRTEX6")) and (fifo_not_full = '1')) then
data_wr_end_o <= '1';
else
data_wr_end_o <= '0';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmd_start <= cmd_validC_i and cmd_rdyC;
cmd_startB <= cmd_valid_i and cmd_rdyB;
cmd_startC <= cmd_validB_i and cmd_rdyC;
cmd_startD <= cmd_validB_i and cmd_rdyD;
cmd_startE <= cmd_validB_i and cmd_rdyE;
cmd_startF <= cmd_validB_i and cmd_rdyF;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
user_burst_cnt <= "0000000" ;
elsif (cmd_start = '1') then
if (FAMILY = "SPARTAN6") then
if (bl_i = "000000") then
user_burst_cnt <= "1000000" ;
else
user_burst_cnt <= ('0' & bl_i) ;
end if;
else
user_burst_cnt <= ('0' & bl_i) ;
end if;
elsif (fifo_not_full = '1') then
if (user_burst_cnt /= "0000000") then
user_burst_cnt <= user_burst_cnt - "0000001" ;
else
user_burst_cnt <= "0000000" ;
end if;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((user_burst_cnt = "0000010" and fifo_not_full = '1') or (cmd_startC = '1' and bl_i = "000001")) then
u_bcount_2 <= '1' ;
elsif (last_word_o_xhdl1 = '1') then
u_bcount_2 <= '0' ;
end if;
end if;
end process;
last_word_o_xhdl1 <= u_bcount_2 and fifo_not_full;
-- cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i
-- is assert and reassert during the last data
cmd_rdy_o <= cmd_rdy and fifo_not_full;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdy <= '1' ;
elsif (cmd_start = '1') then
if (bl_i = "000001") then
cmd_rdy <= '1' ;
else
cmd_rdy <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdy <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyB <= '1' ;
elsif (cmd_startB = '1') then
if (bl_i = "000001") then
cmd_rdyB <= '1' ;
else
cmd_rdyB <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyB <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyC <= '1' ;
elsif (cmd_startC = '1') then
if (bl_i = "000001") then
cmd_rdyC <= '1' ;
else
cmd_rdyC <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyC <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyD <= '1' ;
elsif (cmd_startD = '1') then
if (bl_i = "000001") then
cmd_rdyD <= '1' ;
else
cmd_rdyD <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyD <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyE <= '1' ;
elsif (cmd_startE = '1') then
if (bl_i = "000001") then
cmd_rdyE <= '1' ;
else
cmd_rdyE <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyE <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyF <= '1' ;
elsif (cmd_startF = '1') then
if (bl_i = "000001") then
cmd_rdyF <= '1' ;
else
cmd_rdyF <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyF <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(1)) = '1') then
data_valid <= '0' ;
elsif (cmd_start = '1') then
data_valid <= '1' ;
elsif (fifo_not_full = '1' and user_burst_cnt <= "0000001") then
data_valid <= '0' ;
end if;
end if;
end process;
data_valid_o <= data_valid and fifo_not_full;
s6_wdgen : if (FAMILY = "SPARTAN6") generate
sp6_data_gen_inst : sp6_data_gen
generic map (
ADDR_WIDTH => 32,
BL_WIDTH => BL_WIDTH,
DWIDTH => DWIDTH,
DATA_PATTERN => DATA_PATTERN,
NUM_DQ_PINS => NUM_DQ_PINS,
COLUMN_WIDTH => COLUMN_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(1),
data_rdy_i => data_rdy_i,
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_startA => cmd_start,
cmd_startB => cmd_startB,
cmd_startC => cmd_startC,
cmd_startD => cmd_startD,
cmd_startE => cmd_startE,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
user_burst_cnt => user_burst_cnt,
fifo_rdy_i => fifo_not_full,
data_o => data_o_xhdl0
);
end generate;
v6_wdgen : if (FAMILY = "VIRTEX6") generate
v6_data_gen_inst : v6_data_gen
generic map (
ADDR_WIDTH => 32,
BL_WIDTH => BL_WIDTH,
DWIDTH => DWIDTH,
MEM_BURST_LEN => MEM_BURST_LEN,
DATA_PATTERN => DATA_PATTERN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
COLUMN_WIDTH => COLUMN_WIDTH,
EYE_TEST => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(1),
data_rdy_i => data_rdy_i,
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_starta => cmd_start,
cmd_startb => cmd_startB,
cmd_startc => cmd_startC,
cmd_startd => cmd_startD,
cmd_starte => cmd_startE,
fixed_data_i => fixed_data_i,
m_addr_i => addr_i, --m_addr_i,
addr_i => addr_i,
user_burst_cnt => user_burst_cnt,
fifo_rdy_i => fifo_not_full,
data_o => data_o_xhdl0
);
end generate;
end architecture trans;
| gpl-3.0 | 59570da02fde5592cce147b49078ed90 | 0.46205 | 3.930705 | false | false | false | false |
Jorge9314/ElectronicaDigital | Impresora2D/rs232_tb.vhd | 1 | 4,331 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY rs232_tb IS
END rs232_tb;
ARCHITECTURE behavior OF rs232_tb IS
COMPONENT RS232
PORT(
clk : IN std_logic;
Entrada_8bits : IN std_logic_vector(7 downto 0);
Activador_Envio_Mensaje : IN std_logic;
Salida_1bit : OUT std_logic;
Entrada_1bit : IN std_logic;
Mensaje_8bits : OUT std_logic_vector(7 downto 0);
Activador_Entrega_Mensaje : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal Entrada_8bits : std_logic_vector(7 downto 0) := (others => '0');
signal Activador_Envio_Mensaje : std_logic := '0';
signal Entrada_1bit : std_logic := '0';
--Outputs
signal Salida_1bit : std_logic;
signal Mensaje_8bits : std_logic_vector(7 downto 0);
signal Activador_Entrega_Mensaje : std_logic;
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RS232 PORT MAP (
clk => clk,
Entrada_8bits => Entrada_8bits,
Activador_Envio_Mensaje => Activador_Envio_Mensaje,
Salida_1bit => Salida_1bit,
Entrada_1bit => Entrada_1bit,
Mensaje_8bits => Mensaje_8bits,
Activador_Entrega_Mensaje => Activador_Entrega_Mensaje
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-------------------------------------------------------------
-- Recibo un 11111111 con paridad 0
-------------------------------------------------------------
-- IDLE --
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
-- BIT DE INICIO --
Recibo <= '0';
wait for 0.10416 ms;
-- 8 BITS DE INFORMACION --
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
-- BIT DE PARIDAD --
Recibo <= '0';
wait for 0.10416 ms;
-- BIT DE PARADA --
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
-------------------------------------------------------------
-- Recibo un 01111110 con paridad 1 MALO!!!!!!
-------------------------------------------------------------
-- IDLE --
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
-- BIT DE INICIO --
Recibo <= '0';
wait for 0.10416 ms;
-- 8 BITS DE INFORMACION --
Recibo <= '0';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '0';
wait for 0.10416 ms;
-- BIT DE PARIDAD --
Recibo <= '1';
wait for 0.10416 ms;
-- BIT DE PARADA --
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
-------------------------------------------------------------
-- Recibo un 10110110 con paridad 1
-------------------------------------------------------------
-- IDLE --
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
-- BIT DE INICIO --
Recibo <= '0';
wait for 0.10416 ms;
-- 8 BITS DE INFORMACION --
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '0';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '0';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '0';
wait for 0.10416 ms;
-- BIT DE PARIDAD --
Recibo <= '1';
wait for 0.10416 ms;
-- BIT DE PARADA --
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
wait;
end process;
END; | gpl-3.0 | 910f3066055e8f7228d394b704b1baa6 | 0.49873 | 3.249062 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/styles/indent_only/graphicsaccelerator/Pointer.vhd | 1 | 1,626 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity Pointer is
Generic (initX : STD_LOGIC_VECTOR (9 downto 0);
initY : STD_LOGIC_VECTOR (8 downto 0));
Port ( MoveUp : in STD_LOGIC;
MoveDown : in STD_LOGIC;
MoveLeft : in STD_LOGIC;
MoveRight : in STD_LOGIC;
Move : in STD_LOGIC;
Clk : in STD_LOGIC;
Here : out STD_LOGIC;
X : out STD_LOGIC_VECTOR (9 downto 0);
Y : out STD_LOGIC_VECTOR (8 downto 0);
syncX : in STD_LOGIC_VECTOR (9 downto 0);
syncY : in STD_LOGIC_VECTOR (8 downto 0));
end Pointer;
architecture Behavioral of Pointer is
signal rX : STD_LOGIC_VECTOR (9 downto 0) := initX;
signal rY : STD_LOGIC_VECTOR (8 downto 0) := initY;
begin
Here <= '1' when syncX(9 downto 3)=rX(9 downto 3) and
syncY(8 downto 3)=rY(8 downto 3) else '0';
X <= rX;
Y <= rY;
process (Clk) begin
if (rising_edge(Clk)) then
if (Move = '1') then
if (MoveLeft = '1' and MoveRight = '0') then
if not (rX = "0000000000") then
rX <= rX - 1;
end if;
elsif (MoveLeft = '0' and MoveRight = '1') then
if not (rX = "1001111111") then
rX <= rX + 1;
end if;
end if;
if (MoveUp = '1' and MoveDown = '0') then
if not (rY = "000000000") then
rY <= rY - 1;
end if;
elsif (MoveUp = '0' and MoveDown = '1') then
if not (rY = "111011111") then
rY <= rY + 1;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | be6418322a73907db8b350ec8115616a | 0.54797 | 3.169591 | false | false | false | false |
kjellhar/axi_mmc | sim/basic_cmd_test/basic_cmd_test.vhd | 1 | 7,275 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/29/2014 09:07:43 PM
-- Design Name:
-- Module Name: basic_cmd_test - testbench
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity basic_cmd_test is
-- Port ( );
end basic_cmd_test;
architecture testbench of basic_cmd_test is
constant clk100M_per : time := 10 ns;
component mmc_core_top is
Port ( clk : in std_logic;
reset : in std_logic;
irq : out std_logic;
execute : in std_logic;
busy : out std_logic;
status_reg_o : out std_logic_vector (31 downto 0);
config_reg_i : in std_logic_vector (31 downto 0);
config_reg_o : out std_logic_vector (31 downto 0);
config_reg_wr : in std_logic;
operation_reg_i : in std_logic_vector (31 downto 0);
operation_reg_o : out std_logic_vector (31 downto 0);
operation_reg_wr : in std_logic;
cmd_arg_reg_i : in std_logic_vector (31 downto 0);
cmd_arg_reg_o : out std_logic_vector (31 downto 0);
cmd_arg_reg_wr : in std_logic;
respons_fifo_o : out std_logic_vector (31 downto 0);
respons_fifo_pull : in std_logic;
respons_fifo_empty : out std_logic;
rdata_fifo_o : out std_logic_vector (31 downto 0 );
rdata_fifo_pull : in std_logic;
rdata_fifo_empty : out std_logic;
-- MCC signals
mmc_clk_o : out std_logic;
mmc_rst_o : out std_logic;
mmc_cmd_i : in std_logic;
mmc_cmd_o : out std_logic;
mmc_dat_i : in std_logic_vector (7 downto 0);
mmc_dat_o : out std_logic_vector (7 downto 0);
-- Auxillary MMC signals
mmc_cpresent_i : in std_logic;
mmc_pwr_en_o : out std_logic;
-- MMC pin control signals
mmc_cmd_dir : out std_logic;
mmc_dat_dir : out std_logic
);
end component;
signal test_en : std_logic := '1';
signal clk100M : std_logic := '0';
signal reset : std_logic := '1';
signal execute : std_logic := '0';
signal status_reg_o : std_logic_vector (31 downto 0);
signal config_reg_o : std_logic_vector (31 downto 0);
signal config_reg_i : std_logic_vector (31 downto 0) := (others => '0');
signal config_reg_wr : std_logic := '0';
signal operation_reg_o : std_logic_vector (31 downto 0);
signal operation_reg_i : std_logic_vector (31 downto 0) := (others => '0');
signal operation_reg_wr : std_logic := '0';
signal cmd_arg_reg_o : std_logic_vector (31 downto 0);
signal cmd_arg_reg_i : std_logic_vector (31 downto 0) := (others => '0');
signal cmd_arg_reg_wr : std_logic := '0';
signal mmc_clk_o : std_logic;
signal mmc_cmd_o : std_logic;
signal mmc_cmd_dir : std_logic;
signal response : std_logic_vector (135 downto 0) := (others => '1');
begin
-- DUT instantiation
u_dut : mmc_core_top
Port map (
clk => clk100M,
reset => reset,
--irq => ,
execute => execute,
--busy => ,
status_reg_o => status_reg_o,
config_reg_i => config_reg_i,
config_reg_o => config_reg_o,
config_reg_wr => config_reg_wr,
operation_reg_i => operation_reg_i,
operation_reg_o => operation_reg_o,
operation_reg_wr => operation_reg_wr,
cmd_arg_reg_i => cmd_arg_reg_i,
cmd_arg_reg_o => cmd_arg_reg_o,
cmd_arg_reg_wr => cmd_arg_reg_wr,
--respons_fifo_o => ,
respons_fifo_pull => '0',
--respons_fifo_empty => ,
--rdata_fifo_o => ,
rdata_fifo_pull => '0',
--rdata_fifo_empty => ,
-- MCC signals
mmc_clk_o => mmc_clk_o,
--mmc_rst_o => ,
mmc_cmd_i => response(135),
mmc_cmd_o => mmc_cmd_o,
mmc_dat_i => "00000000",
--mmc_dat_o => ,
-- Auxillary MMC signals
mmc_cpresent_i => '1',
--mmc_pwr_en_o => ,
-- MMC pin control signals
mmc_cmd_dir => mmc_cmd_dir
--mmc_dat_dir =>
);
-- Clock generator
process
begin
if test_en='1' then
clk100M <= '1', '0' after clk100M_per/2;
wait for clk100M_per;
else
wait;
end if;
end process;
-- Testbench stimuli
process
begin
test_en <= '1';
reset <= '1';
wait for 100 ns;
reset <= '0';
wait for 10*clk100M_per;
wait until rising_edge(clk100M);
config_reg_i <= X"02" & X"000201";
wait until rising_edge(clk100M);
config_reg_wr <= '1';
wait until rising_edge(clk100M);
config_reg_wr <= '0';
config_reg_i <= (others => '0');
operation_reg_i <= X"00" & '0' & "1010011" & "000" & "0000" & "011" & "010011";
wait until rising_edge(clk100M);
operation_reg_wr <= '1';
wait until rising_edge(clk100M);
operation_reg_wr <= '0';
operation_reg_i <= (others => '0');
cmd_arg_reg_i <= X"01234567";
wait until rising_edge(clk100M);
cmd_arg_reg_wr <= '1';
wait until rising_edge(clk100M);
cmd_arg_reg_wr <= '0';
cmd_arg_reg_i <= (others => '0');
wait for 10*clk100M_per;
wait until rising_edge(clk100M);
execute <= '1';
wait until rising_edge(clk100M);
execute <= '0';
wait until falling_edge(mmc_cmd_o);
for i in 0 to 47 loop
wait until rising_edge(mmc_clk_o);
end loop;
wait until rising_edge(mmc_clk_o);
wait until rising_edge(mmc_clk_o);
wait until rising_edge(mmc_clk_o);
response <= X"73C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C1";
for i in 0 to 135 loop
wait until rising_edge(mmc_clk_o);
response <= response (134 downto 0) & '1';
end loop;
wait for 200 ns;
test_en <= '0';
wait;
end process;
end testbench;
| mit | b0508131f02d8fd1d00e0bd72334e223 | 0.486735 | 3.721228 | false | true | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/if_statement/rule_025_test_input.vhd | 1 | 566 |
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
IF a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
IF x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
end process;
end architecture RTL;
| gpl-3.0 | 6f531c14af2d222f397ec506b02414ba | 0.379859 | 3.19774 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/axi_lite.vhd | 1 | 95,492 | -------------------------------------------------------------------------------
-- axi_lite.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: axi_lite.vhd
--
-- Description: This file is the top level module for the AXI-Lite
-- instantiation of the BRAM controller interface.
--
-- Responsible for shared address pipelining between the
-- write address (AW) and read address (AR) channels.
-- Controls (seperately) the data flows for the write data
-- (W), write response (B), and read data (R) channels.
--
-- Creates a shared port to BRAM (for all read and write
-- transactions) or dual BRAM port utilization based on a
-- generic parameter setting.
--
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- ecc_gen.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/1/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Remove library version # dependency. Replace with work library.
-- ^^^^^^
-- JLJ 2/22/2011 v1.03a
-- ~~~~~~
-- Update BRAM address mapping to lite_ecc_reg module. Corrected
-- signal size for XST detected unused bits in vector.
-- Plus minor code cleanup.
--
-- Add top level parameter, C_ECC_TYPE for Hsiao ECC algorithm.
-- ^^^^^^
-- JLJ 2/23/2011 v1.03a
-- ~~~~~~
-- Add Hsiao ECC algorithm logic (similar to full_axi module HDL).
-- ^^^^^^
-- JLJ 2/24/2011 v1.03a
-- ~~~~~~
-- Move REG_RDATA register process out from C_ECC_TYPE generate block
-- to C_ECC generate block.
-- ^^^^^^
-- JLJ 3/22/2011 v1.03a
-- ~~~~~~
-- Add LUT level with reset signal to combinatorial outputs, AWREADY
-- and WREADY. This will ensure that the output remains LOW during reset,
-- regardless of AWVALID or WVALID input signals.
-- ^^^^^^
-- JLJ 3/28/2011 v1.03a
-- ~~~~~~
-- Remove combinatorial output paths on AWREADY and WREADY.
-- Combine AWREADY and WREADY registers.
-- Remove combinatorial output path on ARREADY. Can pre-assert ARREADY
-- (but only for non ECC configurations).
-- Create 3-bit counter for BVALID response, seperate from AW/W channels.
--
-- Delay assertion of WREADY in ECC configurations to minimize register
-- resource utilization.
-- No pre-assertion of ARREADY in ECC configurations (due to write latency
-- with ECC enabled).
--
-- ^^^^^^
-- JLJ 3/30/2011 v1.03a
-- ~~~~~~
-- Update Sl_CE and Sl_UE flag assertions to a single clock cycle.
-- Clean up comments.
-- ^^^^^^
-- JLJ 4/19/2011 v1.03a
-- ~~~~~~
-- Update BVALID assertion when ECC is enabled to match the implementation
-- when C_ECC = 0. Optimize back to back write performance when C_ECC = 1.
-- ^^^^^^
-- JLJ 4/22/2011 v1.03a
-- ~~~~~~
-- Modify FaultInjectClr signal assertion. With BVALID counter, delay
-- when fault inject register gets cleared.
-- ^^^^^^
-- JLJ 4/22/2011 v1.03a
-- ~~~~~~
-- Code clean up.
-- ^^^^^^
-- JLJ 5/6/2011 v1.03a
-- ~~~~~~
-- Remove usage of C_FAMILY.
-- Hard code C_USE_LUT6 constant.
-- ^^^^^^
-- JLJ 7/7/2011 v1.03a
-- ~~~~~~
-- Fix DV regression failure with reset.
-- Hold off BRAM enable output with active reset signal.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.lite_ecc_reg;
use work.parity;
use work.checkbit_handler;
use work.correct_one_bit;
use work.ecc_gen;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity axi_lite is
generic (
C_S_AXI_PROTOCOL : string := "AXI4LITE";
-- Set to AXI4LITE to optimize out burst transaction support
C_S_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_SINGLE_PORT_BRAM : integer := 1;
-- Enable single port usage of BRAM
-- C_FAMILY : string := "virtex6";
-- Specify the target architecture type
-- AXI-Lite Register Parameters
C_S_AXI_CTRL_ADDR_WIDTH : integer := 32;
-- Width of AXI-Lite address bus (in bits)
C_S_AXI_CTRL_DATA_WIDTH : integer := 32;
-- Width of AXI-Lite data bus (in bits)
-- ECC Parameters
C_ECC : integer := 0;
-- Enables or disables ECC functionality
C_ECC_TYPE : integer := 0; -- v1.03a
-- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code
C_ECC_WIDTH : integer := 8;
-- Width of ECC data vector
C_FAULT_INJECT : integer := 0;
-- Enable fault injection registers
C_ECC_ONOFF_RESET_VALUE : integer := 1;
-- By default, ECC checking is on (can disable ECC @ reset by setting this to 0)
-- Hard coded parameters at top level.
-- Note: Kept in design for future enhancement.
C_ENABLE_AXI_CTRL_REG_IF : integer := 0;
-- By default the ECC AXI-Lite register interface is enabled
C_CE_FAILING_REGISTERS : integer := 0;
-- Enable CE (correctable error) failing registers
C_UE_FAILING_REGISTERS : integer := 0;
-- Enable UE (uncorrectable error) failing registers
C_ECC_STATUS_REGISTERS : integer := 0;
-- Enable ECC status registers
C_ECC_ONOFF_REGISTER : integer := 0;
-- Enable ECC on/off control register
C_CE_COUNTER_WIDTH : integer := 0
-- Selects CE counter width/threshold to assert ECC_Interrupt
);
port (
-- AXI Interface Signals
-- AXI Clock and Reset
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
ECC_Interrupt : out std_logic := '0';
ECC_UE : out std_logic := '0';
-- *** AXI Write Address Channel Signals (AW) ***
AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
AXI_AWVALID : in std_logic;
AXI_AWREADY : out std_logic;
-- Unused AW AXI-Lite Signals
-- AXI_AWID : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0);
-- AXI_AWLEN : in std_logic_vector(7 downto 0);
-- AXI_AWSIZE : in std_logic_vector(2 downto 0);
-- AXI_AWBURST : in std_logic_vector(1 downto 0);
-- AXI_AWLOCK : in std_logic; -- Currently unused
-- AXI_AWCACHE : in std_logic_vector(3 downto 0); -- Currently unused
-- AXI_AWPROT : in std_logic_vector(2 downto 0); -- Currently unused
-- *** AXI Write Data Channel Signals (W) ***
AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
AXI_WSTRB : in std_logic_vector(C_S_AXI_DATA_WIDTH/8-1 downto 0);
AXI_WVALID : in std_logic;
AXI_WREADY : out std_logic;
-- Unused W AXI-Lite Signals
-- AXI_WLAST : in std_logic;
-- *** AXI Write Data Response Channel Signals (B) ***
AXI_BRESP : out std_logic_vector(1 downto 0);
AXI_BVALID : out std_logic;
AXI_BREADY : in std_logic;
-- Unused B AXI-Lite Signals
-- AXI_BID : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0);
-- *** AXI Read Address Channel Signals (AR) ***
AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
AXI_ARVALID : in std_logic;
AXI_ARREADY : out std_logic;
-- *** AXI Read Data Channel Signals (R) ***
AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
AXI_RRESP : out std_logic_vector(1 downto 0);
AXI_RLAST : out std_logic;
AXI_RVALID : out std_logic;
AXI_RREADY : in std_logic;
-- *** AXI-Lite ECC Register Interface Signals ***
-- AXI-Lite Clock and Reset
-- Note: AXI-Lite Control IF and AXI IF share the same clock.
-- S_AXI_CTRL_AClk : in std_logic;
-- S_AXI_CTRL_AResetn : in std_logic;
-- AXI-Lite Write Address Channel Signals (AW)
AXI_CTRL_AWVALID : in std_logic;
AXI_CTRL_AWREADY : out std_logic;
AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
-- AXI-Lite Write Data Channel Signals (W)
AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
AXI_CTRL_WVALID : in std_logic;
AXI_CTRL_WREADY : out std_logic;
-- AXI-Lite Write Data Response Channel Signals (B)
AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
AXI_CTRL_BVALID : out std_logic;
AXI_CTRL_BREADY : in std_logic;
-- AXI-Lite Read Address Channel Signals (AR)
AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
AXI_CTRL_ARVALID : in std_logic;
AXI_CTRL_ARREADY : out std_logic;
-- AXI-Lite Read Data Channel Signals (R)
AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
AXI_CTRL_RVALID : out std_logic;
AXI_CTRL_RREADY : in std_logic;
-- *** BRAM Port A Interface Signals ***
-- Note: Clock handled at top level (axi_bram_ctrl module)
BRAM_En_A : out std_logic;
BRAM_WE_A : out std_logic_vector (C_S_AXI_DATA_WIDTH/8+(C_ECC_WIDTH+7)/8-1 downto 0);
BRAM_Addr_A : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
BRAM_WrData_A : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); -- @ port level = 8-bits wide ECC
BRAM_RdData_A : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); -- @ port level = 8-bits wide ECC
-- Note: Remove BRAM_RdData_A port (unused in dual port mode)
-- Platgen will keep port open on BRAM block
-- *** BRAM Port B Interface Signals ***
-- Note: Clock handled at top level (axi_bram_ctrl module)
BRAM_En_B : out std_logic;
BRAM_WE_B : out std_logic_vector (C_S_AXI_DATA_WIDTH/8+(C_ECC_WIDTH+7)/8-1 downto 0);
BRAM_Addr_B : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
BRAM_WrData_B : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); -- @ port level = 8-bits wide ECC
BRAM_RdData_B : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) -- @ port level = 8-bits wide ECC
);
end entity axi_lite;
-------------------------------------------------------------------------------
architecture implementation of axi_lite is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- All functions defined in axi_bram_ctrl_funcs package.
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant C_RESET_ACTIVE : std_logic := '0';
constant RESP_OKAY : std_logic_vector (1 downto 0) := "00"; -- Normal access OK response
constant RESP_SLVERR : std_logic_vector (1 downto 0) := "10"; -- Slave error
-- For future implementation.
-- constant RESP_EXOKAY : std_logic_vector (1 downto 0) := "01"; -- Exclusive access OK response
-- constant RESP_DECERR : std_logic_vector (1 downto 0) := "11"; -- Decode error
-- Modify C_BRAM_ADDR_SIZE to be adjusted for BRAM data width
-- When BRAM data width = 32 bits, BRAM_Addr (1:0) = "00"
-- When BRAM data width = 64 bits, BRAM_Addr (2:0) = "000"
-- When BRAM data width = 128 bits, BRAM_Addr (3:0) = "0000"
-- When BRAM data width = 256 bits, BRAM_Addr (4:0) = "00000"
constant C_BRAM_ADDR_ADJUST_FACTOR : integer := log2 (C_S_AXI_DATA_WIDTH/8);
constant C_BRAM_ADDR_ADJUST : integer := C_S_AXI_ADDR_WIDTH - C_BRAM_ADDR_ADJUST_FACTOR;
constant C_AXI_DATA_WIDTH_BYTES : integer := C_S_AXI_DATA_WIDTH/8;
-- Internal data width based on C_S_AXI_DATA_WIDTH.
constant C_INT_ECC_WIDTH : integer := Int_ECC_Size (C_S_AXI_DATA_WIDTH);
-- constant C_USE_LUT6 : boolean := Family_To_LUT_Size (String_To_Family (C_FAMILY,false)) = 6;
-- Remove usage of C_FAMILY.
-- All architectures supporting AXI will support a LUT6.
-- Hard code this internal constant used in ECC algorithm.
-- constant C_USE_LUT6 : boolean := Family_To_LUT_Size (String_To_Family (C_FAMILY,false)) = 6;
constant C_USE_LUT6 : boolean := TRUE;
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal axi_aresetn_d1 : std_logic := '0';
signal axi_aresetn_re : std_logic := '0';
-------------------------------------------------------------------------------
-- AXI Write & Read Address Channel Signals
-------------------------------------------------------------------------------
-- State machine type declarations
type LITE_SM_TYPE is ( IDLE,
SNG_WR_DATA,
RD_DATA,
RMW_RD_DATA,
RMW_MOD_DATA,
RMW_WR_DATA
);
signal lite_sm_cs, lite_sm_ns : LITE_SM_TYPE;
signal axi_arready_cmb : std_logic := '0';
signal axi_arready_reg : std_logic := '0';
signal axi_arready_int : std_logic := '0';
-------------------------------------------------------------------------------
-- AXI Write Data Channel Signals
-------------------------------------------------------------------------------
signal axi_wready_cmb : std_logic := '0';
signal axi_wready_int : std_logic := '0';
-------------------------------------------------------------------------------
-- AXI Write Response Channel Signals
-------------------------------------------------------------------------------
signal axi_bresp_int : std_logic_vector (1 downto 0) := (others => '0');
signal axi_bvalid_int : std_logic := '0';
signal bvalid_cnt_inc : std_logic := '0';
signal bvalid_cnt_inc_d1 : std_logic := '0';
signal bvalid_cnt_dec : std_logic := '0';
signal bvalid_cnt : std_logic_vector (2 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- AXI Read Data Channel Signals
-------------------------------------------------------------------------------
signal axi_rresp_int : std_logic_vector (1 downto 0) := (others => '0');
signal axi_rvalid_set : std_logic := '0';
signal axi_rvalid_set_r : std_logic := '0';
signal axi_rvalid_int : std_logic := '0';
signal axi_rlast_set : std_logic := '0';
signal axi_rlast_set_r : std_logic := '0';
signal axi_rlast_int : std_logic := '0';
signal axi_rdata_int : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi_rdata_int_corr : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Internal BRAM Signals
-------------------------------------------------------------------------------
signal bram_we_a_int : std_logic_vector (C_S_AXI_DATA_WIDTH/8+(C_ECC_WIDTH+7)/8-1 downto 0) := (others => '0');
signal bram_en_a_cmb : std_logic := '0';
signal bram_en_b_cmb : std_logic := '0';
signal bram_en_a_int : std_logic := '0';
signal bram_en_b_int : std_logic := '0';
signal bram_addr_a_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
signal bram_addr_a_int_q : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
signal bram_addr_b_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
signal BRAM_Addr_A_i : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal BRAM_Addr_B_i : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal bram_wrdata_a_int : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0'); -- Port level signal, 8-bits ECC
-------------------------------------------------------------------------------
-- Internal ECC Signals
-------------------------------------------------------------------------------
signal FaultInjectClr : std_logic := '0'; -- Clear for Fault Inject Registers
signal CE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers
signal UE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers
signal CE_CounterReg_Inc : std_logic := '0'; -- Increment CE Counter Register
signal Sl_CE : std_logic := '0'; -- Correctable Error Flag
signal Sl_UE : std_logic := '0'; -- Uncorrectable Error Flag
signal Sl_CE_i : std_logic := '0';
signal Sl_UE_i : std_logic := '0';
signal FaultInjectData : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal FaultInjectECC : std_logic_vector (C_INT_ECC_WIDTH-1 downto 0) := (others => '0'); -- Specific to BRAM data width
signal CorrectedRdData : std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1) := (others => '0');
signal UnCorrectedRdData : std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1) := (others => '0');
signal CE_Q : std_logic := '0';
signal UE_Q : std_logic := '0';
signal Enable_ECC : std_logic := '0';
signal RdModifyWr_Read : std_logic := '0'; -- Read cycle in read modify write sequence
signal RdModifyWr_Check : std_logic := '0'; -- Read cycle in read modify write sequence
signal RdModifyWr_Modify : std_logic := '0'; -- Modify cycle in read modify write sequence
signal RdModifyWr_Write : std_logic := '0'; -- Write cycle in read modify write sequence
signal WrData : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal WrData_cmb : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal Active_Wr : std_logic := '0';
signal BRAM_Addr_En : std_logic := '0';
signal Syndrome : std_logic_vector(0 to C_INT_ECC_WIDTH-1); -- Specific to BRAM data width
signal Syndrome_4 : std_logic_vector (0 to 1) := (others => '0'); -- Specific to 32-bit ECC
signal Syndrome_6 : std_logic_vector (0 to 5) := (others => '0'); -- Specific to 32-bit ECC
signal syndrome_reg : std_logic_vector(0 to C_INT_ECC_WIDTH-1); -- Specific to BRAM data width
signal syndrome_4_reg : std_logic_vector (0 to 1) := (others => '0'); -- Specific for 32-bit ECC
signal syndrome_6_reg : std_logic_vector (0 to 5) := (others => '0'); -- Specific for 32-bit ECC
signal syndrome_reg_i : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- *** AXI-Lite ECC Register Output Signals ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_NO_REGS
-- Purpose: Generate default values if ECC registers are disabled (or when
-- ECC is disabled).
-- Include both AXI-Lite default signal values & internal
-- core signal values.
---------------------------------------------------------------------------
-- For future implementation.
-- GEN_NO_REGS: if (C_ECC = 1 and C_ENABLE_AXI_CTRL_REG_IF = 0) or (C_ECC = 0) generate
GEN_NO_REGS: if (C_ECC = 0) generate
begin
AXI_CTRL_AWREADY <= '0';
AXI_CTRL_WREADY <= '0';
AXI_CTRL_BRESP <= (others => '0');
AXI_CTRL_BVALID <= '0';
AXI_CTRL_ARREADY <= '0';
AXI_CTRL_RDATA <= (others => '0');
AXI_CTRL_RRESP <= (others => '0');
AXI_CTRL_RVALID <= '0';
-- No fault injection
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
-- Interrupt only enabled when ECC status/interrupt registers enabled
ECC_Interrupt <= '0';
ECC_UE <= '0';
BRAM_Addr_En <= '0';
-----------------------------------------------------------------------
-- Generate: GEN_DIS_ECC
-- Purpose: Disable ECC in read path when ECC is disabled in core.
-----------------------------------------------------------------------
GEN_DIS_ECC: if C_ECC = 0 generate
Enable_ECC <= '0';
end generate GEN_DIS_ECC;
-- For future implementation.
--
-- -----------------------------------------------------------------------
-- -- Generate: GEN_EN_ECC
-- -- Purpose: Enable ECC when C_ECC = 1 and no ECC registers are available.
-- -- ECC on/off control register is not accessible (so ECC is always
-- -- enabled in this configuraiton).
-- -----------------------------------------------------------------------
-- GEN_EN_ECC: if (C_ECC = 1 and C_ENABLE_AXI_CTRL_REG_IF = 0) generate
-- Enable_ECC <= '1'; -- ECC ON/OFF register can not be enabled (as no ECC
-- -- ECC registers are available. Therefore, ECC
-- -- is always enabled.
-- end generate GEN_EN_ECC;
end generate GEN_NO_REGS;
---------------------------------------------------------------------------
-- Generate: GEN_REGS
-- Purpose: Generate ECC register module when ECC is enabled and
-- ECC registers are enabled.
---------------------------------------------------------------------------
-- For future implementation.
-- GEN_REGS: if (C_ECC = 1 and C_ENABLE_AXI_CTRL_REG_IF = 1) generate
GEN_REGS: if (C_ECC = 1) generate
begin
---------------------------------------------------------------------------
-- Instance: I_LITE_ECC_REG
-- Description: This module is for the AXI-Lite ECC registers.
--
-- Responsible for all AXI-Lite communication to the
-- ECC register bank. Provides user interface signals
-- to rest of AXI BRAM controller IP core for ECC functionality
-- and control.
-- Manages AXI-Lite write address (AW) and read address (AR),
-- write data (W), write response (B), and read data (R) channels.
---------------------------------------------------------------------------
I_LITE_ECC_REG : entity work.lite_ecc_reg
generic map (
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH ,
C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH ,
C_ECC_WIDTH => C_INT_ECC_WIDTH , -- ECC width specific to data width
C_FAULT_INJECT => C_FAULT_INJECT ,
C_CE_FAILING_REGISTERS => C_CE_FAILING_REGISTERS ,
C_UE_FAILING_REGISTERS => C_UE_FAILING_REGISTERS ,
C_ECC_STATUS_REGISTERS => C_ECC_STATUS_REGISTERS ,
C_ECC_ONOFF_REGISTER => C_ECC_ONOFF_REGISTER ,
C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE ,
C_CE_COUNTER_WIDTH => C_CE_COUNTER_WIDTH
)
port map (
S_AXI_AClk => S_AXI_AClk , -- AXI clock
S_AXI_AResetn => S_AXI_AResetn ,
-- Note: AXI-Lite Control IF and AXI IF share the same clock.
-- S_AXI_CTRL_AClk => S_AXI_CTRL_AClk , -- AXI-Lite clock
-- S_AXI_CTRL_AResetn => S_AXI_CTRL_AResetn ,
Interrupt => ECC_Interrupt ,
ECC_UE => ECC_UE ,
AXI_CTRL_AWVALID => AXI_CTRL_AWVALID ,
AXI_CTRL_AWREADY => AXI_CTRL_AWREADY ,
AXI_CTRL_AWADDR => AXI_CTRL_AWADDR ,
AXI_CTRL_WDATA => AXI_CTRL_WDATA ,
AXI_CTRL_WVALID => AXI_CTRL_WVALID ,
AXI_CTRL_WREADY => AXI_CTRL_WREADY ,
AXI_CTRL_BRESP => AXI_CTRL_BRESP ,
AXI_CTRL_BVALID => AXI_CTRL_BVALID ,
AXI_CTRL_BREADY => AXI_CTRL_BREADY ,
AXI_CTRL_ARADDR => AXI_CTRL_ARADDR ,
AXI_CTRL_ARVALID => AXI_CTRL_ARVALID ,
AXI_CTRL_ARREADY => AXI_CTRL_ARREADY ,
AXI_CTRL_RDATA => AXI_CTRL_RDATA ,
AXI_CTRL_RRESP => AXI_CTRL_RRESP ,
AXI_CTRL_RVALID => AXI_CTRL_RVALID ,
AXI_CTRL_RREADY => AXI_CTRL_RREADY ,
Enable_ECC => Enable_ECC ,
FaultInjectClr => FaultInjectClr ,
CE_Failing_We => CE_Failing_We ,
CE_CounterReg_Inc => CE_Failing_We ,
Sl_CE => Sl_CE ,
Sl_UE => Sl_UE ,
BRAM_Addr_A => BRAM_Addr_A_i (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) , -- v1.03a
BRAM_Addr_B => BRAM_Addr_B_i (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) , -- v1.03a
BRAM_Addr_En => BRAM_Addr_En ,
Active_Wr => Active_Wr ,
FaultInjectData => FaultInjectData ,
FaultInjectECC => FaultInjectECC
);
FaultInjectClr <= '1' when (bvalid_cnt_inc_d1 = '1') else '0';
CE_Failing_We <= '1' when Enable_ECC = '1' and CE_Q = '1' else '0';
Active_Wr <= '1' when (RdModifyWr_Read = '1' or RdModifyWr_Check = '1' or RdModifyWr_Modify = '1' or RdModifyWr_Write = '1') else '0';
-----------------------------------------------------------------------
-- Add register delay on BVALID counter increment
-- Used to clear fault inject register.
REG_BVALID_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
bvalid_cnt_inc_d1 <= '0';
else
bvalid_cnt_inc_d1 <= bvalid_cnt_inc;
end if;
end if;
end process REG_BVALID_CNT;
-----------------------------------------------------------------------
end generate GEN_REGS;
---------------------------------------------------------------------------
-- *** AXI Output Signals ***
---------------------------------------------------------------------------
-- AXI Write Address Channel Output Signals
-- AXI_AWREADY <= axi_awready_cmb;
-- AXI_AWREADY <= '0' when (S_AXI_AResetn = '0') else axi_awready_cmb; -- v1.03a
AXI_AWREADY <= axi_wready_int; -- v1.03a
-- AXI Write Data Channel Output Signals
-- AXI_WREADY <= axi_wready_cmb;
-- AXI_WREADY <= '0' when (S_AXI_AResetn = '0') else axi_wready_cmb; -- v1.03a
AXI_WREADY <= axi_wready_int; -- v1.03a
-- AXI Write Response Channel Output Signals
AXI_BRESP <= axi_bresp_int;
AXI_BVALID <= axi_bvalid_int;
-- AXI Read Address Channel Output Signals
-- AXI_ARREADY <= axi_arready_cmb; -- v1.03a
AXI_ARREADY <= axi_arready_int; -- v1.03a
-- AXI Read Data Channel Output Signals
-- AXI_RRESP <= axi_rresp_int;
AXI_RRESP <= RESP_SLVERR when (C_ECC = 1 and Sl_UE_i = '1') else axi_rresp_int;
-- AXI_RDATA <= axi_rdata_int;
-- Move assignment of RDATA to generate statements based on C_ECC.
AXI_RVALID <= axi_rvalid_int;
AXI_RLAST <= axi_rlast_int;
----------------------------------------------------------------------------
-- Need to detect end of reset cycle to assert AWREADY on AXI bus
REG_ARESETN: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
axi_aresetn_d1 <= S_AXI_AResetn;
end if;
end process REG_ARESETN;
-- Create combinatorial RE detect of S_AXI_AResetn
axi_aresetn_re <= '1' when (S_AXI_AResetn = '1' and axi_aresetn_d1 = '0') else '0';
----------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** AXI Write Address Channel Interface ***
---------------------------------------------------------------------------
-- Notes:
-- No address pipelining for AXI-Lite.
-- PDR feedback.
-- Remove address register stage to BRAM.
-- Rely on registers in AXI Interconnect.
---------------------------------------------------------------------------
-- Generate: GEN_ADDR
-- Purpose: Generate all valid bits in the address(es) to BRAM.
-- If dual port, generate Port B address signal.
---------------------------------------------------------------------------
GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate
begin
---------------------------------------------------------------------------
-- Generate: GEN_ADDR_SNG_PORT
-- Purpose: Generate BRAM address when a single port to BRAM.
-- Mux read and write addresses from AXI AW and AR channels.
---------------------------------------------------------------------------
GEN_ADDR_SNG_PORT: if (C_SINGLE_PORT_BRAM = 1) generate
begin
-- Read takes priority over AWADDR
-- bram_addr_a_int (i) <= AXI_ARADDR (i) when (AXI_ARVALID = '1') else AXI_AWADDR (i);
-- ISE should optimize away this mux when connected to the AXI Interconnect
-- as the AXI Interconnect duplicates the write or read address on both channels.
-- v1.03a
-- ARVALID may get asserted while handling ECC read-modify-write.
-- With the delay in assertion of AWREADY/WREADY, must add some logic to the
-- control on this mux select.
bram_addr_a_int (i) <= AXI_ARADDR (i) when ((AXI_ARVALID = '1' and
(lite_sm_cs = IDLE or lite_sm_cs = SNG_WR_DATA)) or
(lite_sm_cs = RD_DATA))
else AXI_AWADDR (i);
end generate GEN_ADDR_SNG_PORT;
---------------------------------------------------------------------------
-- Generate: GEN_ADDR_DUAL_PORT
-- Purpose: Generate BRAM address when a single port to BRAM.
-- Mux read and write addresses from AXI AW and AR channels.
---------------------------------------------------------------------------
GEN_ADDR_DUAL_PORT: if (C_SINGLE_PORT_BRAM = 0) generate
begin
bram_addr_a_int (i) <= AXI_AWADDR (i);
bram_addr_b_int (i) <= AXI_ARADDR (i);
end generate GEN_ADDR_DUAL_PORT;
end generate GEN_ADDR;
---------------------------------------------------------------------------
-- *** AXI Read Address Channel Interface ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_ARREADY
-- Purpose: Only pre-assert ARREADY for non ECC designs.
-- With ECC, a write requires a read-modify-write and
-- will miss the address associated with the ARVALID
-- (due to the # of clock cycles).
---------------------------------------------------------------------------
GEN_ARREADY: if (C_ECC = 0) generate
begin
REG_ARREADY: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
-- ARREADY is asserted until we detect the ARVALID.
-- Check for back-to-back ARREADY assertions (add axi_arready_int).
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(AXI_ARVALID = '1' and axi_arready_int = '1') then
axi_arready_int <= '0';
-- Then ARREADY is asserted again when the read operation completes.
elsif (axi_aresetn_re = '1') or
(axi_rlast_int = '1' and AXI_RREADY = '1') then
axi_arready_int <= '1';
else
axi_arready_int <= axi_arready_int;
end if;
end if;
end process REG_ARREADY;
end generate GEN_ARREADY;
---------------------------------------------------------------------------
-- Generate: GEN_ARREADY_ECC
-- Purpose: Generate ARREADY from SM logic. ARREADY is not pre-asserted
-- as in the non ECC configuration.
---------------------------------------------------------------------------
GEN_ARREADY_ECC: if (C_ECC = 1) generate
begin
axi_arready_int <= axi_arready_reg;
end generate GEN_ARREADY_ECC;
---------------------------------------------------------------------------
-- *** AXI Write Data Channel Interface ***
---------------------------------------------------------------------------
-- No AXI_WLAST
---------------------------------------------------------------------------
-- Generate: GEN_WRDATA
-- Purpose: Generate BRAM port A write data. For AXI-Lite, pass
-- through from AXI bus. If ECC is enabled, merge with fault
-- inject vector.
-- Write data bits are in lower order bit lanes.
-- (31:0) or (63:0)
---------------------------------------------------------------------------
GEN_WRDATA: for i in C_S_AXI_DATA_WIDTH-1 downto 0 generate
begin
---------------------------------------------------------------------------
-- Generate: GEN_NO_ECC
-- Purpose: Generate output write data when ECC is disabled.
-- Remove write data path register to BRAM
---------------------------------------------------------------------------
GEN_NO_ECC : if C_ECC = 0 generate
begin
bram_wrdata_a_int (i) <= AXI_WDATA (i);
end generate GEN_NO_ECC;
---------------------------------------------------------------------------
-- Generate: GEN_W_ECC
-- Purpose: Generate output write data when ECC is enable
-- (use fault vector).
-- (N:0)
---------------------------------------------------------------------------
GEN_W_ECC : if C_ECC = 1 generate
begin
bram_wrdata_a_int (i) <= WrData (i) xor FaultInjectData (i);
end generate GEN_W_ECC;
end generate GEN_WRDATA;
---------------------------------------------------------------------------
-- *** AXI Write Response Channel Interface ***
---------------------------------------------------------------------------
-- No BID support (wrap around in Interconnect)
-- In AXI-Lite, no WLAST assertion
-- Drive constant value out on BRESP
-- axi_bresp_int <= RESP_OKAY;
axi_bresp_int <= RESP_SLVERR when (C_ECC = 1 and UE_Q = '1') else RESP_OKAY;
---------------------------------------------------------------------------
-- Implement BVALID with counter regardless of IP configuration.
--
-- BVALID counter to track the # of required BVALID/BREADY handshakes
-- needed to occur on the AXI interface. Based on early and seperate
-- AWVALID/AWREADY and WVALID/WREADY handshake exchanges.
REG_BVALID_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
bvalid_cnt <= (others => '0');
-- Ensure we only increment counter wyhen BREADY is not asserted
elsif (bvalid_cnt_inc = '1') and (bvalid_cnt_dec = '0') then
bvalid_cnt <= std_logic_vector (unsigned (bvalid_cnt (2 downto 0)) + 1);
-- Ensure that we only decrement when SM is not incrementing
elsif (bvalid_cnt_dec = '1') and (bvalid_cnt_inc = '0') then
bvalid_cnt <= std_logic_vector (unsigned (bvalid_cnt (2 downto 0)) - 1);
else
bvalid_cnt <= bvalid_cnt;
end if;
end if;
end process REG_BVALID_CNT;
bvalid_cnt_dec <= '1' when (AXI_BREADY = '1' and axi_bvalid_int = '1' and bvalid_cnt /= "000") else '0';
-- Replace BVALID output register
-- Assert BVALID as long as BVALID counter /= zero
REG_BVALID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(bvalid_cnt = "001" and bvalid_cnt_dec = '1') then
axi_bvalid_int <= '0';
elsif (bvalid_cnt /= "000") then
axi_bvalid_int <= '1';
else
axi_bvalid_int <= '0';
end if;
end if;
end process REG_BVALID;
---------------------------------------------------------------------------
-- *** AXI Read Data Channel Interface ***
---------------------------------------------------------------------------
-- For reductions on AXI-Lite, drive constant value on RESP
axi_rresp_int <= RESP_OKAY;
---------------------------------------------------------------------------
-- Generate: GEN_R
-- Purpose: Generate AXI R channel outputs when ECC is disabled.
-- No register delay on AXI_RVALID and AXI_RLAST.
---------------------------------------------------------------------------
GEN_R: if C_ECC = 0 generate
begin
---------------------------------------------------------------------------
-- AXI_RVALID Output Register
--
-- Set AXI_RVALID when read data SM indicates.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
---------------------------------------------------------------------------
REG_RVALID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1') then
-- Code coverage is hitting this condition and axi_rvalid_int is ALWAYS = '1'
-- May be able to remove from this if clause (and simplify logic)
axi_rvalid_int <= '0';
elsif (axi_rvalid_set = '1') then
axi_rvalid_int <= '1';
else
axi_rvalid_int <= axi_rvalid_int;
end if;
end if;
end process REG_RVALID;
---------------------------------------------------------------------------
-- AXI_RLAST Output Register
--
-- Set AXI_RLAST when read data SM indicates.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
---------------------------------------------------------------------------
REG_RLAST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1') then
-- Code coverage is hitting this condition and axi_rvalid_int is ALWAYS = '1'
-- May be able to remove from this if clause (and simplify logic)
axi_rlast_int <= '0';
elsif (axi_rlast_set = '1') then
axi_rlast_int <= '1';
else
axi_rlast_int <= axi_rlast_int;
end if;
end if;
end process REG_RLAST;
end generate GEN_R;
---------------------------------------------------------------------------
-- Generate: GEN_R_ECC
-- Purpose: Generate AXI R channel outputs when ECC is enabled.
-- Must use registered delayed control signals for RLAST
-- and RVALID to align with register inclusion for corrected
-- read data in ECC logic.
---------------------------------------------------------------------------
GEN_R_ECC: if C_ECC = 1 generate
begin
---------------------------------------------------------------------------
-- AXI_RVALID Output Register
--
-- Set AXI_RVALID when read data SM indicates.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
---------------------------------------------------------------------------
REG_RVALID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1') then
-- Code coverage is hitting this condition and axi_rvalid_int is ALWAYS = '1'
-- May be able to remove from this if clause (and simplify logic)
axi_rvalid_int <= '0';
elsif (axi_rvalid_set_r = '1') then
axi_rvalid_int <= '1';
else
axi_rvalid_int <= axi_rvalid_int;
end if;
end if;
end process REG_RVALID;
---------------------------------------------------------------------------
-- AXI_RLAST Output Register
--
-- Set AXI_RLAST when read data SM indicates.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
---------------------------------------------------------------------------
REG_RLAST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1') then
-- Code coverage is hitting this condition and axi_rvalid_int is ALWAYS = '1'
-- May be able to remove from this if clause (and simplify logic)
axi_rlast_int <= '0';
elsif (axi_rlast_set_r = '1') then
axi_rlast_int <= '1';
else
axi_rlast_int <= axi_rlast_int;
end if;
end if;
end process REG_RLAST;
end generate GEN_R_ECC;
---------------------------------------------------------------------------
--
-- Generate AXI bus read data. No register. Pass through
-- read data from BRAM. Determine source on single port
-- vs. dual port configuration.
--
---------------------------------------------------------------------------
-----------------------------------------------------------------------
-- Generate: RDATA_NO_ECC
-- Purpose: Define port A/B from BRAM on AXI_RDATA when ECC disabled.
-----------------------------------------------------------------------
RDATA_NO_ECC: if (C_ECC = 0) generate
begin
AXI_RDATA <= axi_rdata_int;
-----------------------------------------------------------------------
-- Generate: GEN_RDATA_SNG_PORT
-- Purpose: Source of read data: Port A in single port configuration.
-----------------------------------------------------------------------
GEN_RDATA_SNG_PORT: if (C_SINGLE_PORT_BRAM = 1) generate
begin
axi_rdata_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= BRAM_RdData_A(C_S_AXI_DATA_WIDTH-1 downto 0);
end generate GEN_RDATA_SNG_PORT;
-----------------------------------------------------------------------
-- Generate: GEN_RDATA_DUAL_PORT
-- Purpose: Source of read data: Port B in dual port configuration.
-----------------------------------------------------------------------
GEN_RDATA_DUAL_PORT: if (C_SINGLE_PORT_BRAM = 0) generate
begin
axi_rdata_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= BRAM_RdData_B (C_S_AXI_DATA_WIDTH-1 downto 0);
end generate GEN_RDATA_DUAL_PORT;
end generate RDATA_NO_ECC;
-----------------------------------------------------------------------
-- Generate: RDATA_W_ECC
-- Purpose: Connect AXI_RDATA from ECC module when ECC enabled.
-----------------------------------------------------------------------
RDATA_W_ECC: if (C_ECC = 1) generate
subtype syndrome_bits is std_logic_vector (0 to 6);
type correct_data_table_type is array (natural range 0 to 31) of syndrome_bits;
constant correct_data_table : correct_data_table_type := (
0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001",
4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001",
8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101",
12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101",
16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101",
20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101",
24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011",
28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011"
);
begin
-- Logic common to either type of ECC encoding/decoding
-- Renove bit reversal on AXI_RDATA output.
AXI_RDATA <= axi_rdata_int when (Enable_ECC = '0' or Sl_UE_i = '1') else axi_rdata_int_corr;
CorrectedRdData (0 to C_S_AXI_DATA_WIDTH-1) <= axi_rdata_int_corr (C_S_AXI_DATA_WIDTH-1 downto 0);
-- Remove GEN_RDATA that was doing bit reversal.
-- Read back data is registered prior to any single bit error correction.
REG_RDATA: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rdata_int <= (others => '0');
else
axi_rdata_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= UnCorrectedRdData (0 to C_S_AXI_DATA_WIDTH-1);
end if;
end if;
end process REG_RDATA;
---------------------------------------------------------------------------
-- Generate: RDATA_W_HAMMING
-- Purpose: Add generate statement for Hamming Code ECC algorithm
-- specific logic.
---------------------------------------------------------------------------
RDATA_W_HAMMING: if C_ECC_TYPE = 0 generate
begin
-- Move correct_one_bit logic to output side of AXI_RDATA output register.
-- Improves timing by balancing logic on both sides of pipeline stage.
-- Utilizing registers in AXI interconnect makes this feasible.
---------------------------------------------------------------------------
-- Register ECC syndrome value to correct any single bit errors
-- post-register on AXI read data.
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
syndrome_reg <= Syndrome;
syndrome_4_reg <= Syndrome_4;
syndrome_6_reg <= Syndrome_6;
end if;
end process REG_SYNDROME;
---------------------------------------------------------------------------
-- Do last XOR on select syndrome bits outside of checkbit_handler (to match rd_chnl
-- w/ balanced pipeline stage) before correct_one_bit module.
syndrome_reg_i (0 to 3) <= syndrome_reg (0 to 3);
PARITY_CHK4: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2)
port map (
InA => syndrome_4_reg (0 to 1), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_reg_i (4) ); -- [out std_logic]
syndrome_reg_i (5) <= syndrome_reg (5);
PARITY_CHK6: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => syndrome_6_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_reg_i (6) ); -- [out std_logic]
---------------------------------------------------------------------------
-- Generate: GEN_CORR_32
-- Purpose: Generate corrected read data based on syndrome value.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
GEN_CORR_32: for i in 0 to C_S_AXI_DATA_WIDTH-1 generate
begin
---------------------------------------------------------------------------
-- Instance: CORR_ONE_BIT_32
-- Description: Generate ECC bits for checking data read from BRAM.
---------------------------------------------------------------------------
CORR_ONE_BIT_32: entity work.correct_one_bit
generic map (
C_USE_LUT6 => C_USE_LUT6,
Correct_Value => correct_data_table (i))
port map (
DIn => axi_rdata_int (i),
Syndrome => syndrome_reg_i,
DCorr => axi_rdata_int_corr (i));
end generate GEN_CORR_32;
end generate RDATA_W_HAMMING;
-- Hsiao ECC done in seperate generate statement (GEN_HSIAO_ECC)
end generate RDATA_W_ECC;
---------------------------------------------------------------------------
-- Main AXI-Lite State Machine
--
-- Description: Central processing unit for AXI-Lite write and read address
-- channel interface handling and handshaking.
-- Handles all arbitration between write and read channels
-- to utilize single port to BRAM
--
-- Outputs: axi_wready_int Registered
-- axi_arready_reg Registered (used in ECC configurations)
-- bvalid_cnt_inc Combinatorial
-- axi_rvalid_set Combinatorial
-- axi_rlast_set Combinatorial
-- bram_en_a_cmb Combinatorial
-- bram_en_b_cmb Combinatorial
-- bram_we_a_int Combinatorial
--
--
-- LITE_SM_CMB_PROCESS: Combinational process to determine next state.
-- LITE_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
LITE_SM_CMB_PROCESS: process ( AXI_AWVALID,
AXI_WVALID,
AXI_WSTRB,
AXI_ARVALID,
AXI_RREADY,
bvalid_cnt,
axi_rvalid_int,
lite_sm_cs )
begin
-- assign default values for state machine outputs
lite_sm_ns <= lite_sm_cs;
axi_wready_cmb <= '0';
axi_arready_cmb <= '0';
bvalid_cnt_inc <= '0';
axi_rvalid_set <= '0';
axi_rlast_set <= '0';
bram_en_a_cmb <= '0';
bram_en_b_cmb <= '0';
bram_we_a_int <= (others => '0');
case lite_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- AXI Interconnect will only issue AWVALID OR ARVALID
-- at a time. In the case when the core is attached
-- to another AXI master IP, arbitrate between read
-- and write operation. Read operation will always win.
if (AXI_ARVALID = '1') then
lite_sm_ns <= RD_DATA;
-- Initiate BRAM read transfer
-- For single port BRAM, use Port A
-- For dual port BRAM, use Port B
if (C_SINGLE_PORT_BRAM = 1) then
bram_en_a_cmb <= '1';
else
bram_en_b_cmb <= '1';
end if;
bram_we_a_int <= (others => '0');
-- RVALID to be asserted in next clock cycle
-- Only 1 clock cycle latency on reading data from BRAM
axi_rvalid_set <= '1';
-- Due to single data beat with AXI-Lite
-- Assert RLAST on AXI
axi_rlast_set <= '1';
-- Only in ECC configurations
-- Must assert ARREADY here (no pre-assertion)
if (C_ECC = 1) then
axi_arready_cmb <= '1';
end if;
-- Write operations are lower priority than reads
-- when an AXI master asserted both operations simultaneously.
elsif (AXI_AWVALID = '1') and (AXI_WVALID = '1') and
(bvalid_cnt /= "111") then
-- Initiate BRAM write transfer
bram_en_a_cmb <= '1';
-- Always perform a read-modify-write sequence with ECC is enabled.
if (C_ECC = 1) then
lite_sm_ns <= RMW_RD_DATA;
-- Disable Port A write enables
bram_we_a_int <= (others => '0');
else
-- Non ECC operation or an ECC full 32-bit word write
-- Assert acknowledge of data & address on AXI.
-- Wait to assert AWREADY and WREADY in ECC designs.
axi_wready_cmb <= '1';
-- Increment counter to track # of required BVALID responses.
bvalid_cnt_inc <= '1';
lite_sm_ns <= SNG_WR_DATA;
bram_we_a_int <= AXI_WSTRB;
end if;
end if;
------------------------- SNG_WR_DATA State -------------------------
when SNG_WR_DATA =>
-- With early assertion of ARREADY, the SM
-- must be able to accept a read address at any clock cycle.
-- Check here for active ARVALID and directly handle read
-- and do not proceed back to IDLE (no empty clock cycle in which
-- read address may be missed).
if (AXI_ARVALID = '1') and (C_ECC = 0) then
lite_sm_ns <= RD_DATA;
-- Initiate BRAM read transfer
-- For single port BRAM, use Port A
-- For dual port BRAM, use Port B
if (C_SINGLE_PORT_BRAM = 1) then
bram_en_a_cmb <= '1';
else
bram_en_b_cmb <= '1';
end if;
bram_we_a_int <= (others => '0');
-- RVALID to be asserted in next clock cycle
-- Only 1 clock cycle latency on reading data from BRAM
axi_rvalid_set <= '1';
-- Due to single data beat with AXI-Lite
-- Assert RLAST on AXI
axi_rlast_set <= '1';
-- Only in ECC configurations
-- Must assert ARREADY here (no pre-assertion)
-- Pre-assertion of ARREADY is only for non ECC configurations.
if (C_ECC = 1) then
axi_arready_cmb <= '1';
end if;
else
lite_sm_ns <= IDLE;
end if;
---------------------------- RD_DATA State ---------------------------
when RD_DATA =>
-- Data is presented to AXI bus
-- Wait for acknowledgment to process any next transfers
-- RVALID may not be asserted as we transition into this state.
if (AXI_RREADY = '1') and (axi_rvalid_int = '1') then
lite_sm_ns <= IDLE;
end if;
------------------------- RMW_RD_DATA State -------------------------
when RMW_RD_DATA =>
lite_sm_ns <= RMW_MOD_DATA;
------------------------- RMW_MOD_DATA State -------------------------
when RMW_MOD_DATA =>
lite_sm_ns <= RMW_WR_DATA;
-- Hold off on assertion of WREADY and AWREADY until
-- here, so no pipeline registers necessary.
-- Assert acknowledge of data & address on AXI
axi_wready_cmb <= '1';
-- Increment counter to track # of required BVALID responses.
-- Able to assert this signal early, then BVALID counter
-- will get incremented in the next clock cycle when WREADY
-- is asserted.
bvalid_cnt_inc <= '1';
------------------------- RMW_WR_DATA State -------------------------
when RMW_WR_DATA =>
-- Initiate BRAM write transfer
bram_en_a_cmb <= '1';
-- Enable all WEs to BRAM
bram_we_a_int <= (others => '1');
-- Complete write operation
lite_sm_ns <= IDLE;
--coverage off
------------------------------ Default ----------------------------
when others =>
lite_sm_ns <= IDLE;
--coverage on
end case;
end process LITE_SM_CMB_PROCESS;
---------------------------------------------------------------------------
LITE_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
lite_sm_cs <= IDLE;
axi_wready_int <= '0';
axi_arready_reg <= '0';
axi_rvalid_set_r <= '0';
axi_rlast_set_r <= '0';
else
lite_sm_cs <= lite_sm_ns;
axi_wready_int <= axi_wready_cmb;
axi_arready_reg <= axi_arready_cmb;
axi_rvalid_set_r <= axi_rvalid_set;
axi_rlast_set_r <= axi_rlast_set;
end if;
end if;
end process LITE_SM_REG_PROCESS;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** ECC Logic ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_ECC
-- Purpose: Generate BRAM ECC write data and check ECC on read operations.
-- Create signals to update ECC registers (lite_ecc_reg module interface).
--
---------------------------------------------------------------------------
GEN_ECC: if C_ECC = 1 generate
constant null7 : std_logic_vector(0 to 6) := "0000000"; -- Specific to 32-bit data width (AXI-Lite)
signal WrECC : std_logic_vector (C_INT_ECC_WIDTH-1 downto 0); -- Specific to BRAM data width
signal WrECC_i : std_logic_vector (C_ECC_WIDTH-1 downto 0) := (others => '0');
signal wrdata_i : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0);
signal AXI_WDATA_Q : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0);
signal AXI_WSTRB_Q : std_logic_vector ((C_S_AXI_DATA_WIDTH/8 - 1) downto 0);
signal bram_din_a_i : std_logic_vector (0 to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1) := (others => '0'); -- Set for port data width
signal bram_rddata_in : std_logic_vector (C_S_AXI_DATA_WIDTH+C_INT_ECC_WIDTH-1 downto 0) := (others => '0');
subtype syndrome_bits is std_logic_vector (0 to 6);
type correct_data_table_type is array (natural range 0 to 31) of syndrome_bits;
constant correct_data_table : correct_data_table_type := (
0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001",
4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001",
8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101",
12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101",
16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101",
20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101",
24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011",
28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011"
);
type bool_array is array (natural range 0 to 6) of boolean;
constant inverted_bit : bool_array := (false,false,true,false,true,false,false);
begin
-- Read on Port A
-- or any operation on Port B (it will be read only).
BRAM_Addr_En <= '1' when (bram_en_a_int = '1' and bram_we_a_int = "00000") or
(bram_en_b_int = '1')
else '0';
-- BRAM_WE generated from SM
-- Remember byte write enables one clock cycle to properly mux bytes to write,
-- with read data in read/modify write operation
-- Write in Read/Write always 1 cycle after Read
REG_RMW_SIGS : process (S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
-- Add reset values
if (S_AXI_AResetn = C_RESET_ACTIVE) then
RdModifyWr_Check <= '0';
RdModifyWr_Modify <= '0';
RdModifyWr_Write <= '0';
else
RdModifyWr_Check <= RdModifyWr_Read;
RdModifyWr_Modify <= RdModifyWr_Check;
RdModifyWr_Write <= RdModifyWr_Modify;
end if;
end if;
end process REG_RMW_SIGS;
-- v1.03a
-- Delay assertion of WREADY to minimize registers in core.
-- Use SM transition to RMW "read" to assert this signal.
RdModifyWr_Read <= '1' when (lite_sm_ns = RMW_RD_DATA) else '0';
-- Remember write data one cycle to be available after read has been completed in a
-- read/modify write operation
STORE_WRITE_DBUS : process (S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
AXI_WDATA_Q <= (others => '0');
AXI_WSTRB_Q <= (others => '0');
-- v1.03a
-- With the delay assertion of WREADY, use WVALID
-- to register in WDATA and WSTRB signals.
elsif (AXI_WVALID = '1') then
AXI_WDATA_Q <= AXI_WDATA;
AXI_WSTRB_Q <= AXI_WSTRB;
end if;
end if;
end process STORE_WRITE_DBUS;
wrdata_i <= AXI_WDATA_Q when RdModifyWr_Modify = '1' else AXI_WDATA;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_WRDATA_CMB
-- Purpose: Replace manual signal assignment for WrData_cmb with
-- generate funtion.
--
-- Ensure correct byte swapping occurs with
-- CorrectedRdData (0 to C_S_AXI_DATA_WIDTH-1) assignment
-- to WrData_cmb (C_S_AXI_DATA_WIDTH-1 downto 0).
--
-- AXI_WSTRB_Q (C_S_AXI_DATA_WIDTH_BYTES-1 downto 0) matches
-- to WrData_cmb (C_S_AXI_DATA_WIDTH-1 downto 0).
--
------------------------------------------------------------------------
GEN_WRDATA_CMB: for i in C_AXI_DATA_WIDTH_BYTES-1 downto 0 generate
begin
WrData_cmb ( (((i+1)*8)-1) downto i*8 ) <= wrdata_i ((((i+1)*8)-1) downto i*8) when
(RdModifyWr_Modify = '1' and AXI_WSTRB_Q(i) = '1')
else CorrectedRdData ( (C_S_AXI_DATA_WIDTH - ((i+1)*8)) to
(C_S_AXI_DATA_WIDTH - (i*8) - 1) );
end generate GEN_WRDATA_CMB;
REG_WRDATA : process (S_AXI_AClk) is
begin
-- Remove reset value to minimize resources & improve timing
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
WrData <= WrData_cmb;
end if;
end process REG_WRDATA;
------------------------------------------------------------------------
-- New assignment of ECC bits to BRAM write data outside generate
-- blocks. Same signal assignment regardless of ECC type.
bram_wrdata_a_int (C_S_AXI_DATA_WIDTH + C_ECC_WIDTH - 1) <= '0';
bram_wrdata_a_int ((C_S_AXI_DATA_WIDTH + C_INT_ECC_WIDTH - 1) downto C_S_AXI_DATA_WIDTH)
<= WrECC xor FaultInjectECC;
------------------------------------------------------------------------
-- No need to use RdModifyWr_Write in the data path.
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HAMMING_ECC
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
------------------------------------------------------------------------
GEN_HAMMING_ECC: if C_ECC_TYPE = 0 generate
begin
---------------------------------------------------------------------------
-- Instance: CHK_HANDLER_WR_32
-- Description: Generate ECC bits for writing into BRAM.
-- WrData (N:0)
---------------------------------------------------------------------------
CHK_HANDLER_WR_32: entity work.checkbit_handler
generic map (
C_ENCODE => true, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
DataIn => WrData, -- [in std_logic_vector(0 to 31)]
CheckIn => null7, -- [in std_logic_vector(0 to 6)]
CheckOut => WrECC, -- [out std_logic_vector(0 to 6)]
Syndrome_4 => open, -- [out std_logic_vector(0 to 1)]
Syndrome_6 => open, -- [out std_logic_vector(0 to 5)]
Syndrome => open, -- [out std_logic_vector(0 to 6)]
Enable_ECC => '1', -- [in std_logic]
Syndrome_Chk => null7, -- [in std_logic_vector(0 to 6)]
UE_Q => '0', -- [in std_logic]
CE_Q => '0', -- [in std_logic]
UE => open, -- [out std_logic]
CE => open ); -- [out std_logic]
---------------------------------------------------------------------------
-- Instance: CHK_HANDLER_RD_32
-- Description: Generate ECC bits for checking data read from BRAM.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
CHK_HANDLER_RD_32: entity work.checkbit_handler
generic map (
C_ENCODE => false, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
-- DataIn (8:39)
-- CheckIn (1:7)
-- Bit swapping done at port level on checkbit_handler (31:0) & (6:0)
DataIn => bram_din_a_i (C_INT_ECC_WIDTH+1 to C_INT_ECC_WIDTH+C_S_AXI_DATA_WIDTH), -- [in std_logic_vector(8 to 39)]
CheckIn => bram_din_a_i (1 to C_INT_ECC_WIDTH), -- [in std_logic_vector(1 to 7)]
CheckOut => open, -- [out std_logic_vector(0 to 6)]
Syndrome => Syndrome, -- [out std_logic_vector(0 to 6)]
Syndrome_4 => Syndrome_4, -- [out std_logic_vector(0 to 1)]
Syndrome_6 => Syndrome_6, -- [out std_logic_vector(0 to 5)]
Syndrome_Chk => syndrome_reg_i, -- [in std_logic_vector(0 to 6)]
Enable_ECC => Enable_ECC, -- [in std_logic]
UE_Q => UE_Q, -- [in std_logic]
CE_Q => CE_Q, -- [in std_logic]
UE => Sl_UE_i, -- [out std_logic]
CE => Sl_CE_i ); -- [out std_logic]
-- GEN_CORR_32 generate & correct_one_bit instantiation moved to generate
-- of AXI RDATA output register logic to use registered syndrome value.
end generate GEN_HAMMING_ECC;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HSIAO_ECC
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
-- Derived from MIG v3.7 Hsiao HDL.
------------------------------------------------------------------------
GEN_HSIAO_ECC: if C_ECC_TYPE = 1 generate
constant CODE_WIDTH : integer := C_S_AXI_DATA_WIDTH + C_INT_ECC_WIDTH;
constant ECC_WIDTH : integer := C_INT_ECC_WIDTH;
type type_int0 is array (C_S_AXI_DATA_WIDTH - 1 downto 0) of std_logic_vector (ECC_WIDTH - 1 downto 0);
signal syndrome_ns : std_logic_vector(ECC_WIDTH - 1 downto 0);
signal syndrome_r : std_logic_vector(ECC_WIDTH - 1 downto 0);
signal ecc_rddata_r : std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0);
signal h_matrix : type_int0;
signal h_rows : std_logic_vector (CODE_WIDTH * ECC_WIDTH - 1 downto 0);
signal flip_bits : std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0);
begin
---------------------- Hsiao ECC Write Logic ----------------------
-- Instantiate ecc_gen module, generated from MIG
ECC_GEN_HSIAO: entity work.ecc_gen
generic map (
code_width => CODE_WIDTH,
ecc_width => ECC_WIDTH,
data_width => C_S_AXI_DATA_WIDTH
)
port map (
-- Output
h_rows => h_rows (CODE_WIDTH * ECC_WIDTH - 1 downto 0)
);
-- Merge muxed rd/write data to gen
HSIAO_ECC: process (h_rows, WrData)
constant DQ_WIDTH : integer := CODE_WIDTH;
variable ecc_wrdata_tmp : std_logic_vector(DQ_WIDTH-1 downto C_S_AXI_DATA_WIDTH);
begin
-- Loop to generate all ECC bits
for k in 0 to ECC_WIDTH - 1 loop
ecc_wrdata_tmp (CODE_WIDTH - k - 1) := REDUCTION_XOR ( (WrData (C_S_AXI_DATA_WIDTH - 1 downto 0)
and h_rows (k * CODE_WIDTH + C_S_AXI_DATA_WIDTH - 1 downto k * CODE_WIDTH)));
end loop;
WrECC (C_INT_ECC_WIDTH-1 downto 0) <= ecc_wrdata_tmp (DQ_WIDTH-1 downto C_S_AXI_DATA_WIDTH);
end process HSIAO_ECC;
---------------------- Hsiao ECC Read Logic -----------------------
GEN_RD_ECC: for m in 0 to ECC_WIDTH - 1 generate
begin
syndrome_ns (m) <= REDUCTION_XOR ( bram_rddata_in (CODE_WIDTH-1 downto 0)
and h_rows ((m*CODE_WIDTH)+CODE_WIDTH-1 downto (m*CODE_WIDTH)));
end generate GEN_RD_ECC;
-- Insert register stage for syndrome
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
syndrome_r <= syndrome_ns;
-- Replicate BRAM read back data register for Hamming ECC
ecc_rddata_r <= bram_rddata_in (C_S_AXI_DATA_WIDTH-1 downto 0);
end if;
end process REG_SYNDROME;
-- Reconstruct H-matrix
H_COL: for n in 0 to C_S_AXI_DATA_WIDTH - 1 generate
begin
H_BIT: for p in 0 to ECC_WIDTH - 1 generate
begin
h_matrix (n)(p) <= h_rows (p * CODE_WIDTH + n);
end generate H_BIT;
end generate H_COL;
GEN_FLIP_BIT: for r in 0 to C_S_AXI_DATA_WIDTH - 1 generate
begin
flip_bits (r) <= BOOLEAN_TO_STD_LOGIC (h_matrix (r) = syndrome_r);
end generate GEN_FLIP_BIT;
axi_rdata_int_corr (C_S_AXI_DATA_WIDTH-1 downto 0) <= ecc_rddata_r (C_S_AXI_DATA_WIDTH-1 downto 0) xor
flip_bits (C_S_AXI_DATA_WIDTH-1 downto 0);
Sl_CE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0)));
Sl_UE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and not (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0)));
end generate GEN_HSIAO_ECC;
-- Capture correctable/uncorrectable error from BRAM read.
-- Either during RMW of write operation or during BRAM read.
CORR_REG: process(S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if RdModifyWr_Modify = '1' or
((Enable_ECC = '1') and
(axi_rvalid_int = '1' and AXI_RREADY = '1')) then -- Capture error signals
CE_Q <= Sl_CE_i;
UE_Q <= Sl_UE_i;
else
CE_Q <= '0';
UE_Q <= '0';
end if;
end if;
end process CORR_REG;
-- Register CE and UE flags to register block.
Sl_CE <= CE_Q;
Sl_UE <= UE_Q;
---------------------------------------------------------------------------
-- Generate: GEN_DIN_A
-- Purpose: Generate BRAM read data vector assignment to always be from Port A
-- in a single port BRAM configuration.
-- Map BRAM_RdData_A (N:0) to bram_din_a_i (0:N)
-- Including read back ECC bits.
---------------------------------------------------------------------------
GEN_DIN_A: if C_SINGLE_PORT_BRAM = 1 generate
begin
---------------------------------------------------------------------------
-- Generate: GEN_DIN_A_HAMMING
-- Purpose: Standard input for Hamming ECC code generation.
-- MSB '0' is removed in port mapping to checkbit_handler module.
---------------------------------------------------------------------------
GEN_DIN_A_HAMMING: if C_ECC_TYPE = 1 generate
begin
bram_din_a_i (0 to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1) <= BRAM_RdData_A (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0);
end generate GEN_DIN_A_HAMMING;
---------------------------------------------------------------------------
-- Generate: GEN_DIN_A_HSIAO
-- Purpose: For Hsiao ECC implementation configurations.
-- Remove MSB '0' on 32-bit implementation with fixed
-- '0' in (8-bit wide) ECC data bits (only need 7-bits in h-matrix).
---------------------------------------------------------------------------
GEN_DIN_A_HSIAO: if C_ECC_TYPE = 1 generate
begin
bram_rddata_in <= BRAM_RdData_A (C_S_AXI_DATA_WIDTH+C_INT_ECC_WIDTH-1 downto 0);
end generate GEN_DIN_A_HSIAO;
end generate GEN_DIN_A;
---------------------------------------------------------------------------
-- Generate: GEN_DIN_B
-- Purpose: Generate BRAM read data vector assignment in a dual port
-- configuration to be either from Port B, or from Port A in a
-- read-modify-write sequence.
-- Map BRAM_RdData_A/B (N:0) to bram_din_a_i (0:N)
-- Including read back ECC bits.
---------------------------------------------------------------------------
GEN_DIN_B: if C_SINGLE_PORT_BRAM = 0 generate
begin
---------------------------------------------------------------------------
-- Generate: GEN_DIN_B_HAMMING
-- Purpose: Standard input for Hamming ECC code generation.
-- MSB '0' is removed in port mapping to checkbit_handler module.
---------------------------------------------------------------------------
GEN_DIN_B_HAMMING: if C_ECC_TYPE = 1 generate
begin
bram_din_a_i (0 to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1) <= BRAM_RdData_A (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0)
when (RdModifyWr_Check = '1')
else BRAM_RdData_B (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0);
end generate GEN_DIN_B_HAMMING;
---------------------------------------------------------------------------
-- Generate: GEN_DIN_B_HSIAO
-- Purpose: For Hsiao ECC implementation configurations.
-- Remove MSB '0' on 32-bit implementation with fixed
-- '0' in (8-bit wide) ECC data bits (only need 7-bits in h-matrix).
---------------------------------------------------------------------------
GEN_DIN_B_HSIAO: if C_ECC_TYPE = 1 generate
begin
bram_rddata_in <= BRAM_RdData_A (C_S_AXI_DATA_WIDTH+C_INT_ECC_WIDTH-1 downto 0)
when (RdModifyWr_Check = '1')
else BRAM_RdData_B (C_S_AXI_DATA_WIDTH+C_INT_ECC_WIDTH-1 downto 0);
end generate GEN_DIN_B_HSIAO;
end generate GEN_DIN_B;
-- Map data vector from BRAM to use in correct_one_bit module with
-- register syndrome (post AXI RDATA register).
UnCorrectedRdData (0 to C_S_AXI_DATA_WIDTH-1) <= bram_din_a_i (C_ECC_WIDTH to C_ECC_WIDTH+C_S_AXI_DATA_WIDTH-1);
end generate GEN_ECC;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** BRAM Interface Signals ***
---------------------------------------------------------------------------
-- With AXI-LITE no narrow operations are allowed.
-- AXI_WSTRB is ignored and all byte lanes are written.
bram_en_a_int <= bram_en_a_cmb;
-- BRAM_En_A <= bram_en_a_int;
-- DV regression failure with reset
-- 7/7/11
BRAM_En_A <= '0' when (S_AXI_AResetn = C_RESET_ACTIVE) else bram_en_a_int;
-----------------------------------------------------------------------
-- Generate: GEN_BRAM_EN_DUAL_PORT
-- Purpose: Only generate Port B BRAM enable signal when
-- configured for dual port BRAM.
-----------------------------------------------------------------------
GEN_BRAM_EN_DUAL_PORT: if (C_SINGLE_PORT_BRAM = 0) generate
begin
bram_en_b_int <= bram_en_b_cmb;
BRAM_En_B <= bram_en_b_int;
end generate GEN_BRAM_EN_DUAL_PORT;
-----------------------------------------------------------------------
-- Generate: GEN_BRAM_EN_SNG_PORT
-- Purpose: Drive default for unused BRAM Port B in single
-- port BRAM configuration.
-----------------------------------------------------------------------
GEN_BRAM_EN_SNG_PORT: if (C_SINGLE_PORT_BRAM = 1) generate
begin
BRAM_En_B <= '0';
end generate GEN_BRAM_EN_SNG_PORT;
---------------------------------------------------------------------------
-- Generate: GEN_BRAM_WE
-- Purpose: BRAM WE generate process
-- One WE per 8-bits of BRAM data.
---------------------------------------------------------------------------
GEN_BRAM_WE: for i in (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH)/8-1 downto 0 generate
begin
BRAM_WE_A (i) <= bram_we_a_int (i);
end generate GEN_BRAM_WE;
---------------------------------------------------------------------------
BRAM_Addr_A <= BRAM_Addr_A_i;
BRAM_Addr_B <= BRAM_Addr_B_i;
---------------------------------------------------------------------------
-- Generate: GEN_L_BRAM_ADDR
-- Purpose: Generate zeros on lower order address bits adjustable
-- based on BRAM data width.
---------------------------------------------------------------------------
GEN_L_BRAM_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate
begin
BRAM_Addr_A_i (i) <= '0';
BRAM_Addr_B_i (i) <= '0';
end generate GEN_L_BRAM_ADDR;
---------------------------------------------------------------------------
-- Generate: GEN_BRAM_ADDR
-- Purpose: Assign BRAM address output from address counter.
---------------------------------------------------------------------------
GEN_U_BRAM_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate
begin
BRAM_Addr_A_i (i) <= bram_addr_a_int (i);
-----------------------------------------------------------------------
-- Generate: GEN_BRAM_ADDR_DUAL_PORT
-- Purpose: Only generate Port B BRAM address when
-- configured for dual port BRAM.
-----------------------------------------------------------------------
GEN_BRAM_ADDR_DUAL_PORT: if (C_SINGLE_PORT_BRAM = 0) generate
begin
BRAM_Addr_B_i (i) <= bram_addr_b_int (i);
end generate GEN_BRAM_ADDR_DUAL_PORT;
-----------------------------------------------------------------------
-- Generate: GEN_BRAM_ADDR_SNG_PORT
-- Purpose: Drive default for unused BRAM Port B in single
-- port BRAM configuration.
-----------------------------------------------------------------------
GEN_BRAM_ADDR_SNG_PORT: if (C_SINGLE_PORT_BRAM = 1) generate
begin
BRAM_Addr_B_i (i) <= '0';
end generate GEN_BRAM_ADDR_SNG_PORT;
end generate GEN_U_BRAM_ADDR;
---------------------------------------------------------------------------
-- Generate: GEN_BRAM_WRDATA
-- Purpose: Generate BRAM Write Data for Port A.
---------------------------------------------------------------------------
-- When C_ECC = 0, C_ECC_WIDTH = 0 (at top level HDL)
GEN_BRAM_WRDATA: for i in (C_S_AXI_DATA_WIDTH + C_ECC_WIDTH - 1) downto 0 generate
begin
BRAM_WrData_A (i) <= bram_wrdata_a_int (i);
end generate GEN_BRAM_WRDATA;
BRAM_WrData_B <= (others => '0');
BRAM_WE_B <= (others => '0');
---------------------------------------------------------------------------
end architecture implementation;
| bsd-2-clause | 8ae83ca9c3668f6378a12934381e03b8 | 0.427366 | 4.633959 | false | false | false | false |
Yarr/Yarr-fw | rtl/spartan6/gn4124-core/l2p_arbiter.vhd | 2 | 7,870 | -------------------------------------------------------------------------------
-- --
-- CERN BE-CO-HT GN4124 core for PCIe FMC carrier --
-- http://www.ohwr.org/projects/gn4124-core --
-------------------------------------------------------------------------------
--
-- unit name: GN4124 core arbiter (arbiter.vhd)
--
-- authors: Simon Deprez ([email protected])
-- Matthieu Cattin ([email protected])
--
-- date: 12-08-2010
--
-- version: 0.1
--
-- description: Arbitrates PCIe accesses between Wishbone master,
-- L2P DMA master and P2L DMA master
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- last changes: 23-09-2010 (mcattin) Add FF on data path and
-- change valid request logic
-- 26.02.2014 (theim) Changed priority order (swapped LDM <-> PDM)
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
use work.common_pkg.all;
entity l2p_arbiter is
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- From Wishbone master (wbm) to arbiter (arb)
wbm_arb_valid_i : in std_logic;
wbm_arb_dframe_i : in std_logic;
wbm_arb_data_i : in std_logic_vector(31 downto 0);
wbm_arb_req_i : in std_logic;
arb_wbm_gnt_o : out std_logic;
---------------------------------------------------------
-- From P2L DMA master (pdm) to arbiter (arb)
pdm_arb_valid_i : in std_logic;
pdm_arb_dframe_i : in std_logic;
pdm_arb_data_i : in std_logic_vector(31 downto 0);
pdm_arb_req_i : in std_logic;
arb_pdm_gnt_o : out std_logic;
---------------------------------------------------------
-- From L2P DMA master (ldm) to arbiter (arb)
ldm_arb_valid_i : in std_logic;
ldm_arb_dframe_i : in std_logic;
ldm_arb_data_i : in std_logic_vector(31 downto 0);
ldm_arb_req_i : in std_logic;
arb_ldm_gnt_o : out std_logic;
---------------------------------------------------------
-- From arbiter (arb) to serializer (ser)
arb_ser_valid_o : out std_logic;
arb_ser_dframe_o : out std_logic;
arb_ser_data_o : out std_logic_vector(31 downto 0)
);
end l2p_arbiter;
architecture rtl of l2p_arbiter is
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal wbm_arb_req_valid : std_logic;
signal pdm_arb_req_valid : std_logic;
signal ldm_arb_req_valid : std_logic;
signal arb_wbm_gnt : std_logic;
signal arb_pdm_gnt : std_logic;
signal arb_ldm_gnt : std_logic;
signal eop : std_logic; -- End of packet
signal arb_ser_valid_t : std_logic;
signal arb_ser_dframe_t : std_logic;
signal arb_ser_data_t : std_logic_vector(31 downto 0);
begin
-- A request is valid only if the access not already granted to another source
wbm_arb_req_valid <= wbm_arb_req_i and (not(arb_pdm_gnt) and not(arb_ldm_gnt));
pdm_arb_req_valid <= pdm_arb_req_i and (not(arb_wbm_gnt) and not(arb_ldm_gnt));
ldm_arb_req_valid <= ldm_arb_req_i and (not(arb_wbm_gnt) and not(arb_pdm_gnt));
-- Detect end of packet to delimit the arbitration phase
-- eop <= ((arb_wbm_gnt and not(wbm_arb_dframe_i) and wbm_arb_valid_i) or
-- (arb_pdm_gnt and not(pdm_arb_dframe_i) and pdm_arb_valid_i) or
-- (arb_ldm_gnt and not(ldm_arb_dframe_i) and ldm_arb_valid_i));
process (clk_i, rst_n_i)
begin
if (rst_n_i = c_RST_ACTIVE) then
eop <= '0';
elsif rising_edge(clk_i) then
if ((arb_wbm_gnt = '1' and wbm_arb_dframe_i = '0' and wbm_arb_valid_i = '1') or
(arb_pdm_gnt = '1' and pdm_arb_dframe_i = '0' and pdm_arb_valid_i = '1') or
(arb_ldm_gnt = '1' and ldm_arb_dframe_i = '0' and ldm_arb_valid_i = '1')) then
eop <= '1';
else
eop <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Arbitration is started when a valid request is present and ends when the
-- EOP condition is detected
--
-- Strict priority arbitration scheme
-- Highest : WBM request
-- : LDM request
-- Lowest : PDM request
-----------------------------------------------------------------------------
process (clk_i, rst_n_i)
begin
if(rst_n_i = c_RST_ACTIVE) then
arb_wbm_gnt <= '0';
arb_pdm_gnt <= '0';
arb_ldm_gnt <= '0';
elsif rising_edge(clk_i) then
--if (arb_req_valid = '1') then
if (eop = '1') then
arb_wbm_gnt <= '0';
arb_pdm_gnt <= '0';
arb_ldm_gnt <= '0';
elsif (wbm_arb_req_valid = '1') then
arb_wbm_gnt <= '1';
arb_pdm_gnt <= '0';
arb_ldm_gnt <= '0';
elsif (ldm_arb_req_valid = '1') then
arb_wbm_gnt <= '0';
arb_pdm_gnt <= '0';
arb_ldm_gnt <= '1';
elsif (pdm_arb_req_valid = '1') then
arb_wbm_gnt <= '0';
arb_pdm_gnt <= '1';
arb_ldm_gnt <= '0';
end if;
end if;
end process;
process (clk_i, rst_n_i)
begin
if rst_n_i = '0' then
arb_ser_valid_t <= '0';
arb_ser_dframe_t <= '0';
arb_ser_data_t <= (others => '0');
elsif rising_edge(clk_i) then
if arb_wbm_gnt = '1' then
arb_ser_valid_t <= wbm_arb_valid_i;
arb_ser_dframe_t <= wbm_arb_dframe_i;
arb_ser_data_t <= wbm_arb_data_i;
elsif arb_pdm_gnt = '1' then
arb_ser_valid_t <= pdm_arb_valid_i;
arb_ser_dframe_t <= pdm_arb_dframe_i;
arb_ser_data_t <= pdm_arb_data_i;
elsif arb_ldm_gnt = '1' then
arb_ser_valid_t <= ldm_arb_valid_i;
arb_ser_dframe_t <= ldm_arb_dframe_i;
arb_ser_data_t <= ldm_arb_data_i;
else
arb_ser_valid_t <= '0';
arb_ser_dframe_t <= '0';
arb_ser_data_t <= (others => '0');
end if;
end if;
end process;
process (clk_i, rst_n_i)
begin
if rst_n_i = '0' then
arb_ser_valid_o <= '0';
arb_ser_dframe_o <= '0';
arb_ser_data_o <= (others => '0');
elsif rising_edge(clk_i) then
arb_ser_valid_o <= arb_ser_valid_t;
arb_ser_dframe_o <= arb_ser_dframe_t;
arb_ser_data_o <= arb_ser_data_t;
end if;
end process;
arb_wbm_gnt_o <= arb_wbm_gnt;
arb_pdm_gnt_o <= arb_pdm_gnt;
arb_ldm_gnt_o <= arb_ldm_gnt;
end rtl;
| gpl-3.0 | a59c48ff08aea825a594795b10fda6ac | 0.491105 | 3.479222 | false | false | false | false |
siavooshpayandehazad/TTU_CPU_Project | pico_CPU/package.vhd | 1 | 4,350 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pico_cpu is
constant CPU_Bitwidth : integer := 32;
constant CPU_Instwidth : integer := 6 + CPU_Bitwidth;
constant InstMem_depth : integer := 1024;
constant DataMem_depth : integer := 1024;
constant clock_period : time := 1 ns;
component ALU is
generic (BitWidth: integer);
port ( A: in std_logic_vector (BitWidth-1 downto 0);
B: in std_logic_vector (BitWidth-1 downto 0);
Command: in std_logic_vector (3 downto 0);
Cflag_in: in std_logic;
Cflag_out: out std_logic;
Result: out std_logic_vector (BitWidth-1 downto 0)
);
end component;
component RegisterFile is
generic (BitWidth: integer);
port ( clk : in std_logic;
rst: in std_logic;
Data_in_mem: in std_logic_vector (BitWidth-1 downto 0);
Data_in_CU: in std_logic_vector (BitWidth-1 downto 0);
Data_in_ACC: in std_logic_vector (BitWidth-1 downto 0);
Data_in_sel: in std_logic_vector (1 downto 0);
Register_in_sel: in std_logic_vector (7 downto 0);
Register_out_sel: in std_logic_vector (2 downto 0);
Data_out: out std_logic_vector (BitWidth-1 downto 0)
);
end component;
component PicoCPU is
port(
rst: in std_logic;
clk: in std_logic;
FlagOut: out std_logic_vector ( 3 downto 0);
output: out std_logic_vector ( CPU_Bitwidth-1 downto 0)
);
end component;
component ControlUnit is
generic (BitWidth: integer;
InstructionWidth:integer);
port(
rst: in std_logic;
clk: in std_logic;
Instr_In: in std_logic_vector (InstructionWidth-1 downto 0);
Instr_Add: out std_logic_vector (BitWidth-1 downto 0);
MemRdAddress: out std_logic_vector (BitWidth-1 downto 0);
MemWrtAddress: out std_logic_vector (BitWidth-1 downto 0);
Mem_RW: out std_logic;
DPU_Flags: in std_logic_vector (3 downto 0);
DataToDPU: out std_logic_vector (BitWidth-1 downto 0);
CommandToDPU: out std_logic_vector (10 downto 0);
Reg_in_sel: out std_logic_vector (7 downto 0);
Reg_out_sel: out std_logic_vector (2 downto 0);
DataFromDPU: in std_logic_vector (BitWidth-1 downto 0)
);
end component;
----------------------------------------
component InstMem is
generic (BitWidth : integer;
InstructionWidth:integer);
port ( address : in std_logic_vector(BitWidth-1 downto 0);
data : out std_logic_vector(InstructionWidth-1 downto 0) );
end component;
----------------------------------------
component DPU is
generic (BitWidth: integer);
port ( Data_in_mem: in std_logic_vector (BitWidth-1 downto 0);
Data_in: in std_logic_vector (BitWidth-1 downto 0);
clk: in std_logic;
Command: in std_logic_vector (10 downto 0);
Reg_in_sel: in std_logic_vector (7 downto 0);
Reg_out_sel: in std_logic_vector (2 downto 0);
rst: in std_logic;
DPU_Flags: out std_logic_vector (3 downto 0);
Result: out std_logic_vector (BitWidth-1 downto 0)
);
end component;
----------------------------------------
component Mem is
generic (BitWidth: integer);
port ( RdAddress: in std_logic_vector (BitWidth-1 downto 0);
Data_in: in std_logic_vector (BitWidth-1 downto 0);
WrtAddress: in std_logic_vector (BitWidth-1 downto 0);
clk: in std_logic;
RW: in std_logic;
rst: in std_logic;
Data_Out: out std_logic_vector (BitWidth-1 downto 0)
);
end component;
component Adder_Sub is
generic (BitWidth: integer);
port (
A: in std_logic_vector (BitWidth-1 downto 0);
B: in std_logic_vector (BitWidth-1 downto 0);
Add_Sub: in std_logic;
result: out std_logic_vector (BitWidth-1 downto 0);
Cout: out std_logic
);
end component;
component FullAdderSub is
Port ( C_in : in STD_LOGIC;
A : in STD_LOGIC;
B : in STD_LOGIC;
Add_Sub: in STD_LOGIC;
C_out : out STD_LOGIC;
Sum : out STD_LOGIC);
end component;
end; --package body
| gpl-2.0 | f0ad5066ca104ff5f6caee4e82a98490 | 0.581839 | 3.740327 | false | false | false | false |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/cascaded_integrator_comb/cic_compiler_v4_0/hdl/emb_calc.vhd | 1 | 83,900 | `protect begin_protected
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`protect end_protected
| mit | 7cea79677722ec4e62eda24f4e2cfff6 | 0.951228 | 1.813897 | false | false | false | false |
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`protect end_protected
| mit | 8643edb29ca2f72509a2f953210c79ae | 0.938827 | 1.870459 | false | false | false | false |
lvd2/zxevo | fpga/sdload/trunk/sim_models/T80_Pack.vhd | 5 | 8,597 | -- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T80_Pack is
component T80
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic;
ResetPC : in std_logic_vector(15 downto 0);
ResetSP : in std_logic_vector(15 downto 0)
);
end component;
component T80_Reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end component;
component T80_MCode
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic
);
end component;
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
end;
| gpl-3.0 | e35b8a93f308ca8f1fb7a5f421fed696 | 0.528905 | 3.427831 | false | false | false | false |
Yarr/Yarr-fw | rtl/kintex7/rx-core/fei4_rx_channel.vhd | 1 | 6,295 | -- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: RX channel
-- # FE-I4 Style Rx Channel; Sync, Align & Decode
-- ####################################
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library decode_8b10b;
entity fei4_rx_channel is
port (
-- Sys connect
rst_n_i : in std_logic;
clk_160_i : in std_logic;
clk_640_i : in std_logic;
enable_i : in std_logic;
-- Input
rx_data_i : in std_logic;
trig_tag_i : in std_logic_vector(31 downto 0);
-- Output
rx_data_o : out std_logic_vector(25 downto 0);
rx_valid_o : out std_logic;
rx_stat_o : out std_logic_vector(7 downto 0);
rx_data_raw_o : out std_logic_vector(7 downto 0)
);
end fei4_rx_channel;
architecture behavioral of fei4_rx_channel is
component cdr_serdes
port (
-- clocks
clk160 : in std_logic;
clk640 : in std_logic;
-- reset
reset : in std_logic;
-- data input
din : in std_logic;
slip : in std_logic;
-- data output
data_value : out std_logic_vector(1 downto 0);
data_valid : out std_logic_vector(1 downto 0);
data_lock : out std_logic
);
end component;
component data_alignment
port
(
clk : in std_logic;
reset : in std_logic;
din : in std_logic_vector(1 downto 0);
din_valid : in std_logic_vector(1 downto 0);
dout : out std_logic_vector(9 downto 0);
dout_valid : out std_logic;
dout_sync : out std_logic
);
end component;
component decode_8b10b_wrapper
port(
CLK : IN std_logic;
DIN : IN std_logic_vector(9 downto 0);
CE : IN std_logic;
SINIT : IN std_logic;
DOUT : OUT std_logic_vector(7 downto 0);
KOUT : OUT std_logic;
CODE_ERR : OUT std_logic;
DISP_ERR : OUT std_logic;
ND : OUT std_logic
);
end component;
constant c_SOF : std_logic_vector(7 downto 0) := x"fc";
constant c_EOF : std_logic_vector(7 downto 0) := x"bc";
constant c_IDLE : std_logic_vector(7 downto 0) := x"3c";
signal data_raw_value : std_logic_vector(1 downto 0);
signal data_raw_valid : std_logic_vector(1 downto 0);
signal data_raw_lock : std_logic;
signal data_enc_value : std_logic_vector(9 downto 0);
signal data_enc_valid : std_logic;
signal data_enc_sync : std_logic;
signal data_enc_value_rev : std_logic_vector(9 downto 0);
signal data_enc_valid_rev : std_logic;
signal data_enc_valid_rev_d : std_logic;
signal data_dec_value : std_logic_vector(7 downto 0);
signal data_dec_valid : std_logic;
signal data_dec_kchar : std_logic;
signal data_dec_decerr : std_logic;
signal data_dec_disperr : std_logic;
signal data_fram_cnt : unsigned(1 downto 0);
signal data_frame_flag : std_logic;
signal data_frame_value : std_logic_vector(25 downto 0);
signal data_frame_valid : std_logic;
signal status : std_logic_vector(7 downto 0);
begin
-- Status Output
rx_stat_o <= status;
status(0) <= data_raw_lock;
status(1) <= data_enc_sync;
status(2) <= data_dec_decerr;
status(3) <= data_dec_disperr;
status(5 downto 4) <= data_raw_value;
status(7 downto 6) <= data_raw_valid;
rx_data_raw_o <= data_dec_value;
-- Frame collector
rx_data_o <= data_frame_value;
rx_valid_o <= data_frame_valid and data_raw_lock and data_enc_sync and enable_i;
framing_proc : process(clk_160_i, rst_n_i)
begin
if (rst_n_i = '0') then
data_fram_cnt <= (others => '0');
data_frame_flag <= '0';
data_frame_value <= (others => '0');
data_frame_valid <= '0';
elsif rising_edge(clk_160_i) then
-- Count bytes
if (data_frame_flag = '1' and data_dec_valid = '1' and data_fram_cnt = 2) then
data_fram_cnt <= (others => '0');
data_frame_valid <= '1';
elsif (data_frame_flag = '1' and data_dec_valid = '1' and data_fram_cnt < 2) then
data_fram_cnt <= data_fram_cnt + 1;
data_frame_valid <= '0';
elsif (data_frame_flag = '0') then
data_fram_cnt <= (others => '0');
data_frame_valid <= '0';
else
data_frame_valid <= '0';
end if;
-- Mark Start and End of Frame
if (data_dec_valid = '1' and data_dec_kchar = '1' and data_dec_value = c_SOF and data_enc_sync = '1') then
data_frame_flag <= '1';
data_frame_value(25 downto 24) <= "01"; -- tag code
data_frame_value(23 downto 0) <= trig_tag_i(23 downto 0);
data_frame_valid <= '1';
elsif (data_dec_valid = '1' and data_dec_kchar = '1' and (data_dec_value = c_EOF or data_dec_value = c_IDLE)) then
data_frame_flag <= '0';
end if;
-- Build Frame
if (data_frame_flag = '1' and data_dec_valid = '1' and data_dec_kchar = '0' ) then
data_frame_value(25 downto 24) <= "00"; -- no special code
data_frame_value(23 downto 16) <= data_frame_value(15 downto 8);
data_frame_value(15 downto 8) <= data_frame_value(7 downto 0);
data_frame_value(7 downto 0) <= data_dec_value;
end if;
end if;
end process framing_proc;
-- Reverse bit order to make it standard
reverse_proc : process (clk_160_i, rst_n_i)
begin
if (rst_n_i = '0') then
data_enc_value_rev <= (others => '0');
data_enc_valid_rev <= '0';
data_enc_valid_rev_d <= '0';
data_dec_valid <= '0';
elsif rising_edge(clk_160_i) then
for I in 0 to 9 loop
data_enc_value_rev(I) <= data_enc_value(9-I);
end loop;
data_enc_valid_rev <= data_enc_valid;
data_enc_valid_rev_d <= data_enc_valid_rev;
data_dec_valid <= data_enc_valid_rev_d;
end if;
end process reverse_proc;
cmp_cdr_serdes : cdr_serdes port map (
clk160 => clk_160_i,
clk640 => clk_640_i,
reset => not rst_n_i,
din => rx_data_i,
slip => '0',
data_value => data_raw_value,
data_valid => data_raw_valid,
data_lock => data_raw_lock
);
cmp_data_align : data_alignment port map (
clk => clk_160_i,
reset => not rst_n_i,
din => data_raw_value,
din_valid => data_raw_valid,
dout => data_enc_value,
dout_valid => data_enc_valid,
dout_sync => data_enc_sync
);
cmp_decoder: decode_8b10b_wrapper PORT MAP(
CLK => clk_160_i,
DIN => data_enc_value_rev,
CE => data_enc_valid_rev,
SINIT => '0',
DOUT => data_dec_value,
KOUT => data_dec_kchar,
CODE_ERR => data_dec_decErr,
DISP_ERR => data_dec_dispErr,
ND => open
);
end behavioral;
| gpl-3.0 | 5a30149ec326db7fd61c69a53d8f6a5d | 0.616203 | 2.721574 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_dma_v7_1/hdl/src/vhdl/axi_dma_cmd_split.vhd | 1 | 22,455 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
entity axi_dma_cmd_split is
generic (
C_ADDR_WIDTH : integer range 32 to 64 := 32;
C_DM_STATUS_WIDTH : integer range 8 to 32 := 8;
C_INCLUDE_S2MM : integer range 0 to 1 := 0
);
port (
clock : in std_logic;
sgresetn : in std_logic;
clock_sec : in std_logic;
aresetn : in std_logic;
-- command coming from _MNGR
s_axis_cmd_tvalid : in std_logic;
s_axis_cmd_tready : out std_logic;
s_axis_cmd_tdata : in std_logic_vector ((2*C_ADDR_WIDTH+CMD_BASE_WIDTH+46)-1 downto 0);
-- split command to DM
s_axis_cmd_tvalid_s : out std_logic;
s_axis_cmd_tready_s : in std_logic;
s_axis_cmd_tdata_s : out std_logic_vector ((C_ADDR_WIDTH+CMD_BASE_WIDTH+8)-1 downto 0);
-- Tvalid from Datamover
tvalid_from_datamover : in std_logic;
status_in : in std_logic_vector (C_DM_STATUS_WIDTH-1 downto 0);
tvalid_unsplit : out std_logic;
status_out : out std_logic_vector (C_DM_STATUS_WIDTH-1 downto 0);
-- Tlast of stream data from Datamover
tlast_stream_data : in std_logic;
tready_stream_data : in std_logic;
tlast_unsplit : out std_logic;
tlast_unsplit_user : out std_logic
);
end entity axi_dma_cmd_split;
architecture implementation of axi_dma_cmd_split is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
type SPLIT_MM2S_STATE_TYPE is (
IDLE,
SEND,
SPLIT
);
signal mm2s_cs : SPLIT_MM2S_STATE_TYPE;
signal mm2s_ns : SPLIT_MM2S_STATE_TYPE;
signal mm2s_cmd : std_logic_vector (2*C_ADDR_WIDTH+CMD_BASE_WIDTH+46-1 downto 0);
signal command_ns : std_logic_vector (2*C_ADDR_WIDTH+CMD_BASE_WIDTH-1 downto 0);
signal command : std_logic_vector (2*C_ADDR_WIDTH+CMD_BASE_WIDTH-1 downto 0);
signal cache_info : std_logic_vector (31 downto 0);
signal vsize_data : std_logic_vector (22 downto 0);
signal vsize_data_int : std_logic_vector (22 downto 0);
signal vsize : std_logic_vector (22 downto 0);
signal counter : std_logic_vector (22 downto 0);
signal counter_tlast : std_logic_vector (22 downto 0);
signal split_cmd : std_logic_vector (31 downto 0);
signal stride_data : std_logic_vector (22 downto 0);
signal vsize_over : std_logic;
signal cmd_proc_cdc_from : std_logic;
signal cmd_proc_cdc_to : std_logic;
signal cmd_proc_cdc : std_logic;
signal cmd_proc_ns : std_logic;
ATTRIBUTE async_reg : STRING;
-- ATTRIBUTE async_reg OF cmd_proc_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF cmd_proc_cdc : SIGNAL IS "true";
signal cmd_out : std_logic;
signal cmd_out_ns : std_logic;
signal split_out : std_logic;
signal split_out_ns : std_logic;
signal command_valid : std_logic;
signal command_valid_ns : std_logic;
signal command_ready : std_logic;
signal reset_lock : std_logic;
signal reset_lock_tlast : std_logic;
signal tvalid_unsplit_int : std_logic;
signal tlast_stream_data_int : std_logic;
signal ready_for_next_cmd : std_logic;
signal ready_for_next_cmd_tlast : std_logic;
signal ready_for_next_cmd_tlast_cdc_from : std_logic;
signal ready_for_next_cmd_tlast_cdc_to : std_logic;
signal ready_for_next_cmd_tlast_cdc : std_logic;
-- ATTRIBUTE async_reg OF ready_for_next_cmd_tlast_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF ready_for_next_cmd_tlast_cdc : SIGNAL IS "true";
signal tmp1, tmp2, tmp3, tmp4 : std_logic;
signal tlast_int : std_logic;
signal eof_bit : std_logic;
signal eof_bit_cdc_from : std_logic;
signal eof_bit_cdc_to : std_logic;
signal eof_bit_cdc : std_logic;
signal eof_set : std_logic;
signal over_ns, over : std_logic;
signal cmd_in : std_logic;
signal status_out_int : std_logic_vector (C_DM_STATUS_WIDTH-1 downto 0);
begin
s_axis_cmd_tvalid_s <= command_valid;
command_ready <= s_axis_cmd_tready_s;
s_axis_cmd_tdata_s <= command (103 downto 96) & command (71 downto 0);
REGISTER_STATE_MM2S : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
mm2s_cs <= IDLE;
cmd_proc_cdc_from <= '0';
cmd_out <= '0';
command <= (others => '0');
command_valid <= '0';
split_out <= '0';
over <= '0';
else
mm2s_cs <= mm2s_ns;
cmd_proc_cdc_from <= cmd_proc_ns;
cmd_out <= cmd_out_ns;
command <= command_ns;
command_valid <= command_valid_ns;
split_out <= split_out_ns;
over <= over_ns;
end if;
end if;
end process REGISTER_STATE_MM2S;
-- grab the MM2S command coming from MM2S_mngr
REGISTER_MM2S_CMD : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
mm2s_cmd <= (others => '0');
s_axis_cmd_tready <= '0';
cache_info <= (others => '0');
vsize_data <= (others => '0');
vsize_data_int <= (others => '0');
stride_data <= (others => '0');
eof_bit_cdc_from <= '0';
cmd_in <= '0';
elsif (s_axis_cmd_tvalid = '1' and ready_for_next_cmd = '1' and cmd_proc_cdc_from = '0' and ready_for_next_cmd_tlast_cdc = '1') then -- when there is no processing being done, means it is ready to accept
mm2s_cmd <= s_axis_cmd_tdata;
s_axis_cmd_tready <= '1';
cache_info <= s_axis_cmd_tdata (149 downto 118);
vsize_data <= s_axis_cmd_tdata (117 downto 95);
vsize_data_int <= s_axis_cmd_tdata (117 downto 95) - '1';
stride_data <= s_axis_cmd_tdata (94 downto 72);
eof_bit_cdc_from <= s_axis_cmd_tdata (30);
cmd_in <= '1';
else
mm2s_cmd <= mm2s_cmd; --split_cmd;
vsize_data <= vsize_data;
vsize_data_int <= vsize_data_int;
stride_data <= stride_data;
cache_info <= cache_info;
s_axis_cmd_tready <= '0';
eof_bit_cdc_from <= eof_bit_cdc_from;
cmd_in <= '0';
end if;
end if;
end process REGISTER_MM2S_CMD;
REGISTER_DECR_VSIZE : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
vsize <= "00000000000000000000000";
elsif (command_valid = '1' and command_ready = '1' and (vsize < vsize_data_int)) then -- sending a cmd out to DM
vsize <= vsize + '1';
elsif (cmd_proc_cdc_from = '0') then -- idle or when all cmd are sent to DM
vsize <= "00000000000000000000000";
else
vsize <= vsize;
end if;
end if;
end process REGISTER_DECR_VSIZE;
vsize_over <= '1' when (vsize = vsize_data_int) else '0';
-- eof_set <= eof_bit when (vsize = vsize_data_int) else '0';
REGISTER_SPLIT : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
split_cmd <= (others => '0');
elsif (s_axis_cmd_tvalid = '1' and cmd_proc_cdc_from = '0' and ready_for_next_cmd = '1' and ready_for_next_cmd_tlast_cdc = '1') then
split_cmd <= s_axis_cmd_tdata (63 downto 32); -- capture the ba when a new cmd arrives
elsif (split_out = '1') then -- add stride to previous ba
split_cmd <= split_cmd + stride_data;
else
split_cmd <= split_cmd;
end if;
end if;
end process REGISTER_SPLIT;
MM2S_MACHINE : process(mm2s_cs,
s_axis_cmd_tvalid,
cmd_proc_cdc_from,
vsize_over, command_ready,
cache_info, mm2s_cmd,
split_cmd, eof_set,
cmd_in, command
)
begin
over_ns <= '0';
cmd_proc_ns <= '0'; -- ready to receive new command
split_out_ns <= '0';
command_valid_ns <= '0';
mm2s_ns <= mm2s_cs;
-- Default signal assignment
case mm2s_cs is
-------------------------------------------------------------------
when IDLE =>
command_ns <= cache_info & mm2s_cmd (72 downto 65) & split_cmd & mm2s_cmd (31) & eof_set & mm2s_cmd (29 downto 0); -- buf length remains the same
-- command_ns <= cache_info & mm2s_cmd (72 downto 65) & split_cmd & mm2s_cmd (31 downto 0); -- buf length remains the same
if (cmd_in = '1' and cmd_proc_cdc_from = '0') then
cmd_proc_ns <= '1'; -- new command has come in and i need to start processing
mm2s_ns <= SEND;
over_ns <= '0';
split_out_ns <= '1';
command_valid_ns <= '1';
else
mm2s_ns <= IDLE;
over_ns <= '0';
cmd_proc_ns <= '0'; -- ready to receive new command
split_out_ns <= '0';
command_valid_ns <= '0';
end if;
-------------------------------------------------------------------
when SEND =>
cmd_out_ns <= '1';
command_ns <= command;
if (vsize_over = '1' and command_ready = '1') then
mm2s_ns <= IDLE;
cmd_proc_ns <= '1';
command_valid_ns <= '0';
split_out_ns <= '0';
over_ns <= '1';
elsif (command_ready = '0') then --(command_valid = '1' and command_ready = '0') then
mm2s_ns <= SEND;
command_valid_ns <= '1';
cmd_proc_ns <= '1';
split_out_ns <= '0';
over_ns <= '0';
else
mm2s_ns <= SPLIT;
command_valid_ns <= '0';
cmd_proc_ns <= '1';
over_ns <= '0';
split_out_ns <= '0';
end if;
-------------------------------------------------------------------
when SPLIT =>
cmd_proc_ns <= '1';
mm2s_ns <= SEND;
command_ns <= cache_info & mm2s_cmd (72 downto 65) & split_cmd & mm2s_cmd (31) & eof_set & mm2s_cmd (29 downto 0); -- buf length remains the same
-- command_ns <= cache_info & mm2s_cmd (72 downto 65) & split_cmd & mm2s_cmd (31 downto 0); -- buf length remains the same
cmd_out_ns <= '0';
split_out_ns <= '1';
command_valid_ns <= '1';
-------------------------------------------------------------------
-- coverage off
when others =>
mm2s_ns <= IDLE;
-- coverage on
end case;
end process MM2S_MACHINE;
SWALLOW_TVALID : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
counter <= (others => '0');
-- tvalid_unsplit_int <= '0';
reset_lock <= '1';
ready_for_next_cmd <= '0';
elsif (vsize_data_int = "00000000000000000000000") then
-- tvalid_unsplit_int <= '0';
ready_for_next_cmd <= '1';
reset_lock <= '0';
elsif ((tvalid_from_datamover = '1') and (counter < vsize_data_int)) then
counter <= counter + '1';
-- tvalid_unsplit_int <= '0';
ready_for_next_cmd <= '0';
reset_lock <= '0';
elsif ((counter = vsize_data_int) and (reset_lock = '0') and (tvalid_from_datamover = '1')) then
counter <= (others => '0');
-- tvalid_unsplit_int <= '1';
ready_for_next_cmd <= '1';
else
counter <= counter;
-- tvalid_unsplit_int <= '0';
if (cmd_proc_cdc_from = '1') then
ready_for_next_cmd <= '0';
else
ready_for_next_cmd <= ready_for_next_cmd;
end if;
end if;
end if;
end process SWALLOW_TVALID;
tvalid_unsplit_int <= tvalid_from_datamover when (counter = vsize_data_int) else '0'; --tvalid_unsplit_int;
SWALLOW_TDATA : process(clock)
begin
if(clock'EVENT and clock = '1')then
if (sgresetn = '0' or cmd_in = '1') then
tvalid_unsplit <= '0';
status_out_int <= (others => '0');
else
tvalid_unsplit <= tvalid_unsplit_int;
if (tvalid_from_datamover = '1') then
status_out_int (C_DM_STATUS_WIDTH-2 downto 0) <= status_in (C_DM_STATUS_WIDTH-2 downto 0) or status_out_int (C_DM_STATUS_WIDTH-2 downto 0);
else
status_out_int <= status_out_int;
end if;
if (tvalid_unsplit_int = '1') then
status_out_int (C_DM_STATUS_WIDTH-1) <= status_in (C_DM_STATUS_WIDTH-1);
end if;
end if;
end if;
end process SWALLOW_TDATA;
status_out <= status_out_int;
SWALLOW_TLAST_GEN : if C_INCLUDE_S2MM = 0 generate
begin
eof_set <= '1'; --eof_bit when (vsize = vsize_data_int) else '0';
CDC_CMD_PROC1 : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => cmd_proc_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => clock_sec,
scndry_resetn => '0',
scndry_out => cmd_proc_cdc,
scndry_vect_out => open
);
CDC_CMD_PROC2 : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => eof_bit_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => clock_sec,
scndry_resetn => '0',
scndry_out => eof_bit_cdc,
scndry_vect_out => open
);
CDC_CMD_PROC : process (clock_sec)
begin
if (clock_sec'EVENT and clock_sec = '1') then
if (aresetn = '0') then
-- cmd_proc_cdc_to <= '0';
-- cmd_proc_cdc <= '0';
-- eof_bit_cdc_to <= '0';
-- eof_bit_cdc <= '0';
ready_for_next_cmd_tlast_cdc_from <= '0';
else
-- cmd_proc_cdc_to <= cmd_proc_cdc_from;
-- cmd_proc_cdc <= cmd_proc_cdc_to;
-- eof_bit_cdc_to <= eof_bit_cdc_from;
-- eof_bit_cdc <= eof_bit_cdc_to;
ready_for_next_cmd_tlast_cdc_from <= ready_for_next_cmd_tlast;
end if;
end if;
end process CDC_CMD_PROC;
CDC_CMDTLAST_PROC : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => ready_for_next_cmd_tlast_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => clock,
scndry_resetn => '0',
scndry_out => ready_for_next_cmd_tlast_cdc,
scndry_vect_out => open
);
--CDC_CMDTLAST_PROC : process (clock)
-- begin
-- if (clock'EVENT and clock = '1') then
-- if (sgresetn = '0') then
-- ready_for_next_cmd_tlast_cdc_to <= '0';
-- ready_for_next_cmd_tlast_cdc <= '0';
-- else
-- ready_for_next_cmd_tlast_cdc_to <= ready_for_next_cmd_tlast_cdc_from;
-- ready_for_next_cmd_tlast_cdc <= ready_for_next_cmd_tlast_cdc_to;
-- end if;
-- end if;
--end process CDC_CMDTLAST_PROC;
SWALLOW_TLAST : process(clock_sec)
begin
if(clock_sec'EVENT and clock_sec = '1')then
if(aresetn = '0')then
counter_tlast <= (others => '0');
tlast_stream_data_int <= '0';
reset_lock_tlast <= '1';
ready_for_next_cmd_tlast <= '1';
elsif ((tlast_stream_data = '1' and tready_stream_data = '1') and vsize_data_int = "00000000000000000000000") then
tlast_stream_data_int <= '0';
ready_for_next_cmd_tlast <= '1';
reset_lock_tlast <= '0';
elsif ((tlast_stream_data = '1' and tready_stream_data = '1') and (counter_tlast < vsize_data_int)) then
counter_tlast <= counter_tlast + '1';
tlast_stream_data_int <= '0';
ready_for_next_cmd_tlast <= '0';
reset_lock_tlast <= '0';
elsif ((counter_tlast = vsize_data_int) and (reset_lock_tlast = '0') and (tlast_stream_data = '1' and tready_stream_data = '1')) then
counter_tlast <= (others => '0');
tlast_stream_data_int <= '1';
ready_for_next_cmd_tlast <= '1';
else
counter_tlast <= counter_tlast;
tlast_stream_data_int <= '0';
if (cmd_proc_cdc = '1') then
ready_for_next_cmd_tlast <= '0';
else
ready_for_next_cmd_tlast <= ready_for_next_cmd_tlast;
end if;
end if;
end if;
end process SWALLOW_TLAST;
tlast_unsplit <= tlast_stream_data when (counter_tlast = vsize_data_int and eof_bit_cdc = '1') else '0';
tlast_unsplit_user <= tlast_stream_data when (counter_tlast = vsize_data_int) else '0';
-- tlast_unsplit <= tlast_stream_data; -- when (counter_tlast = vsize_data_int) else '0';
end generate SWALLOW_TLAST_GEN;
SWALLOW_TLAST_GEN_S2MM : if C_INCLUDE_S2MM = 1 generate
begin
eof_set <= eof_bit_cdc_from;
ready_for_next_cmd_tlast_cdc <= '1';
end generate SWALLOW_TLAST_GEN_S2MM;
end implementation;
| bsd-2-clause | f2bf28cefecb57f0eda7939de7083c34 | 0.502472 | 3.775219 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/ramfifo/memory.vhd | 2 | 114,679 | `protect begin_protected
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 83152)
`protect data_block
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`protect end_protected
| bsd-2-clause | 9b856cac2275c3564dffde2d9006a724 | 0.953113 | 1.816467 | false | false | false | false |
Yarr/Yarr-fw | rtl/common/wb_traffic_gen.vhd | 1 | 2,034 | ----------------------------------------------------------------------------------
-- Company: LBNL
-- Engineer: Arnaud Sautaux
-- E-Mail: [email protected]
--
-- Project: YARR
-- Module: Traffic generator
-- Description: Master generating traffic
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity wb_traffic_gen is
generic (
ADDR_WIDTH : integer := 32;
DATA_WIDTH : integer := 64;
WRITE : std_logic := '1';
COUNTER_START : integer := 0
);
port (
-- SYS CON
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
-- Wishbone Master out
wb_adr_o : out std_logic_vector(ADDR_WIDTH-1 downto 0);
wb_dat_o : out std_logic_vector(DATA_WIDTH-1 downto 0);
wb_we_o : out std_logic;
wb_stb_o : out std_logic;
wb_cyc_o : out std_logic;
-- Wishbone Master in
--wb_dat_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
--wb_ack_i : in std_logic;
wb_stall_i : in std_logic
);
end wb_traffic_gen;
architecture Behavioral of wb_traffic_gen is
signal counter : std_logic_vector(DATA_WIDTH-1 downto 0);
begin
traffic_p: process (clk, rst)
begin
if (rst ='1') then
counter <= conv_std_logic_vector(COUNTER_START,DATA_WIDTH);
wb_adr_o <= conv_std_logic_vector(COUNTER_START,ADDR_WIDTH);
wb_dat_o <= conv_std_logic_vector(COUNTER_START,DATA_WIDTH);
wb_we_o <= '0';
wb_stb_o <= '0';
wb_cyc_o <= '0';
elsif (clk'event and clk = '1') then
if wb_stall_i = '0' and en = '1' then
counter <= counter + 1;
wb_adr_o <= counter(ADDR_WIDTH-1 downto 0);
wb_dat_o <= counter;
wb_we_o <= WRITE;
wb_stb_o <= '1';
wb_cyc_o <= '1';
else
counter <= counter;
wb_adr_o <= (others => '0');
wb_dat_o <= (others => '0');
wb_we_o <= '0';
wb_stb_o <= '0';
wb_cyc_o <= '0';
end if;
end if;
end process traffic_p;
end Behavioral;
| gpl-3.0 | b7eb085fdba488f39449861b8b77ecb1 | 0.544248 | 2.767347 | false | false | false | false |
Yarr/Yarr-fw | rtl/spartan6/gn4124-core/spartan6/l2p_ser.vhd | 2 | 8,734 | --------------------------------------------------------------------------------
-- --
-- CERN BE-CO-HT GN4124 core for PCIe FMC carrier --
-- http://www.ohwr.org/projects/gn4124-core --
--------------------------------------------------------------------------------
--
-- unit name: L2P serializer (l2p_ser_s6.vhd)
--
-- authors: Simon Deprez ([email protected])
-- Matthieu Cattin ([email protected])
--
-- date: 31-08-2010
--
-- version: 1.0
--
-- description: Generates the DDR L2P bus from SDR that is synchronous to the
-- core clock. Spartan6 FPGAs version.
--
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: 23-09-2010 (mcattin) Always active high reset for FFs.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity l2p_ser is
port
(
---------------------------------------------------------
-- Reset and clock
rst_n_i : in std_logic;
sys_clk_i : in std_logic;
io_clk_i : in std_logic;
serdes_strobe_i : in std_logic;
---------------------------------------------------------
-- L2P SDR inputs
l2p_valid_i : in std_logic;
l2p_dframe_i : in std_logic;
l2p_data_i : in std_logic_vector(31 downto 0);
---------------------------------------------------------
-- L2P DDR outputs
l2p_clk_p_o : out std_logic;
l2p_clk_n_o : out std_logic;
l2p_valid_o : out std_logic;
l2p_dframe_o : out std_logic;
l2p_data_o : out std_logic_vector(15 downto 0)
);
end l2p_ser;
architecture rtl of l2p_ser is
-----------------------------------------------------------------------------
-- Components declaration
-----------------------------------------------------------------------------
component serdes_n_to_1_s2_se
generic (
S : integer := 2; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
txioclk : in std_logic; -- IO Clock network
txserdesstrobe : in std_logic; -- Parallel data capture strobe
reset : in std_logic; -- Reset
gclk : in std_logic; -- Global clock
datain : in std_logic_vector((D*S)-1 downto 0); -- Data for output
dataout : out std_logic_vector(D-1 downto 0)) ; -- output
end component serdes_n_to_1_s2_se;
component serdes_n_to_1_s2_diff
generic (
S : integer := 2; -- Parameter to set the serdes factor 1..8
D : integer := 1) ; -- Set the number of inputs and outputs
port (
txioclk : in std_logic; -- IO Clock network
txserdesstrobe : in std_logic; -- Parallel data capture strobe
reset : in std_logic; -- Reset
gclk : in std_logic; -- Global clock
datain : in std_logic_vector((D*S)-1 downto 0); -- Data for output
dataout_p : out std_logic_vector(D-1 downto 0); -- output
dataout_n : out std_logic_vector(D-1 downto 0)) ; -- output
end component serdes_n_to_1_s2_diff;
-----------------------------------------------------------------------------
-- Comnstants declaration
-----------------------------------------------------------------------------
constant S : integer := 2; -- Set the serdes factor to 2
constant D : integer := 16; -- Set the number of outputs
constant c_TX_CLK : std_logic_vector(1 downto 0) := "01";
-----------------------------------------------------------------------------
-- Signals declaration
-----------------------------------------------------------------------------
-- Serdes reset
signal rst : std_logic;
-- SDR signals
signal l2p_dframe_t : std_logic_vector(1 downto 0);
signal l2p_valid_t : std_logic_vector(1 downto 0);
signal l2p_dframe_v : std_logic_vector(0 downto 0);
signal l2p_valid_v : std_logic_vector(0 downto 0);
signal l2p_clk_p_v : std_logic_vector(0 downto 0);
signal l2p_clk_n_v : std_logic_vector(0 downto 0);
begin
------------------------------------------------------------------------------
-- Active high reset for DDR FF
------------------------------------------------------------------------------
gen_fifo_rst_n : if c_RST_ACTIVE = '0' generate
rst <= not(rst_n_i);
end generate;
gen_fifo_rst : if c_RST_ACTIVE = '1' generate
rst <= rst_n_i;
end generate;
------------------------------------------------------------------------------
-- Instantiate serialiser to generate forwarded clock
------------------------------------------------------------------------------
cmp_clk_out : serdes_n_to_1_s2_diff
generic map(
S => S,
D => 1)
port map (
txioclk => io_clk_i,
txserdesstrobe => serdes_strobe_i,
gclk => sys_clk_i,
reset => rst,
datain => c_TX_CLK, -- Transmit a constant to make the clock
dataout_p => l2p_clk_p_v,
dataout_n => l2p_clk_n_v);
-- Type conversion, std_logic_vector to std_logic
l2p_clk_p_o <= l2p_clk_p_v(0);
l2p_clk_n_o <= l2p_clk_n_v(0);
------------------------------------------------------------------------------
-- Instantiate serialisers for output data lines
------------------------------------------------------------------------------
cmp_data_out : serdes_n_to_1_s2_se
generic map(
S => S,
D => D)
port map (
txioclk => io_clk_i,
txserdesstrobe => serdes_strobe_i,
gclk => sys_clk_i,
reset => rst,
datain => l2p_data_i,
dataout => l2p_data_o);
------------------------------------------------------------------------------
-- Instantiate serialisers for dframe
------------------------------------------------------------------------------
cmp_dframe_out : serdes_n_to_1_s2_se
generic map(
S => S,
D => 1)
port map (
txioclk => io_clk_i,
txserdesstrobe => serdes_strobe_i,
gclk => sys_clk_i,
reset => rst,
datain => l2p_dframe_t,
dataout => l2p_dframe_v);
-- Serialize two times the same value
l2p_dframe_t <= l2p_dframe_i & l2p_dframe_i;
-- Type conversion, std_logic_vector to std_logic
l2p_dframe_o <= l2p_dframe_v(0);
------------------------------------------------------------------------------
-- Instantiate serialisers for valid
------------------------------------------------------------------------------
cmp_valid_out : serdes_n_to_1_s2_se
generic map(
S => S,
D => 1)
port map (
txioclk => io_clk_i,
txserdesstrobe => serdes_strobe_i,
gclk => sys_clk_i,
reset => rst,
datain => l2p_valid_t,
dataout => l2p_valid_v);
-- Serialize two times the same value
l2p_valid_t <= l2p_valid_i & l2p_valid_i;
-- Type conversion, std_logic_vector to std_logic
l2p_valid_o <= l2p_valid_v(0);
end rtl;
| gpl-3.0 | b22fdd9af873554626d5fa21cf369058 | 0.425006 | 4.39336 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/case/rule_011_test_input.vhd | 1 | 489 |
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 | STATE_2 |
STATE_3 | STATE_4 |
STATE_5 | STATE_6 =>
a <= b;
when STATE_2 =>
b <= c;
-- This should fail
when STATE_1 | STATE_2 |
| STATE_3 | STATE_4 |
| STATE_5
| STATE_6
| STATE_7 =>
a <= b;
end case;
end process PROC_1;
end architecture ARCH;
| gpl-3.0 | de06478e40f53aa371be98aeeeedcbec | 0.458078 | 3.517986 | false | false | false | false |
Yarr/Yarr-fw | ip-cores/spartan6/rx_channel_fifo.vhd | 2 | 10,230 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file rx_channel_fifo.vhd when simulating
-- the core, rx_channel_fifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY rx_channel_fifo IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END rx_channel_fifo;
ARCHITECTURE rx_channel_fifo_a OF rx_channel_fifo IS
-- synthesis translate_off
COMPONENT wrapped_rx_channel_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_rx_channel_fifo USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 6,
c_default_value => "BlankString",
c_din_width => 32,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 32,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "512x36",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 63,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 62,
c_prog_full_type => 0,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 6,
c_rd_depth => 64,
c_rd_freq => 1,
c_rd_pntr_width => 6,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 6,
c_wr_depth => 64,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 6,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_rx_channel_fifo
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty
);
-- synthesis translate_on
END rx_channel_fifo_a;
| gpl-3.0 | 4d38ea4e0a6657ad602d4459f51b155e | 0.537243 | 3.330078 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/ramfifo/wr_handshaking_flags.vhd | 2 | 12,552 | `protect begin_protected
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`protect end_protected
| bsd-2-clause | fd2d4bdb7cf4ff6b289e4da98ece0101 | 0.929812 | 1.888939 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/conditional_waveforms/rule_501_test_input.vhd | 2 | 400 |
architecture rtl of fifo is
begin
process
begin
var1 := '0' when rd_en = '1' ELSE '1';
var2 := '0' when rd_en = '1' else '1';
wr_en_a <= force '0' when rd_en = '1' ELSE '1';
wr_en_b <= force '0' when rd_en = '1' else '1';
end process;
concurrent_wr_en_a <= '0' when rd_en = '1' ELSE '1';
concurrent_wr_en_b <= '0' when rd_en = '1' else '1';
end architecture rtl;
| gpl-3.0 | fce38854e6d1ec2fd5d5dd313c3595c3 | 0.54 | 2.564103 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/builtin/builtin_extdepth.vhd | 2 | 80,613 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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KarlxC4ULg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 57936)
`protect data_block
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| bsd-2-clause | 65e137e71228fc161a4399c1f893097c | 0.951956 | 1.81275 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_dma_v7_1/hdl/src/vhdl/axi_dma_s2mm_sts_mngr.vhd | 1 | 11,867 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_sts_mngr.vhd
-- Description: This entity mangages 'halt' and 'idle' status for the S2MM
-- channel
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_sts_mngr is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- system state --
s2mm_run_stop : in std_logic ; --
s2mm_ftch_idle : in std_logic ; --
s2mm_updt_idle : in std_logic ; --
s2mm_cmnd_idle : in std_logic ; --
s2mm_sts_idle : in std_logic ; --
--
-- stop and halt control/status --
s2mm_stop : in std_logic ; --
s2mm_halt_cmplt : in std_logic ; --
--
-- system control --
s2mm_all_idle : out std_logic ; --
s2mm_halted_clr : out std_logic ; --
s2mm_halted_set : out std_logic ; --
s2mm_idle_set : out std_logic ; --
s2mm_idle_clr : out std_logic --
);
end axi_dma_s2mm_sts_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_sts_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal all_is_idle : std_logic := '0';
signal all_is_idle_d1 : std_logic := '0';
signal all_is_idle_re : std_logic := '0';
signal all_is_idle_fe : std_logic := '0';
signal s2mm_datamover_idle : std_logic := '0';
signal s2mm_halt_cmpt_d1_cdc_tig : std_logic := '0';
signal s2mm_halt_cmpt_cdc_d2 : std_logic := '0';
signal s2mm_halt_cmpt_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s2mm_halt_cmpt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_halt_cmpt_cdc_d2 : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- all is idle when all is idle
all_is_idle <= s2mm_ftch_idle
and s2mm_updt_idle
and s2mm_cmnd_idle
and s2mm_sts_idle;
s2mm_all_idle <= all_is_idle;
-------------------------------------------------------------------------------
-- For data mover halting look at halt complete to determine when halt
-- is done and datamover has completly halted. If datamover not being
-- halted then can ignore flag thus simply flag as idle.
-------------------------------------------------------------------------------
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt_cmplt will remain asserted until detected in
-- reset module in secondary clock domain.
REG_TO_SECONDARY : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_halt_cmplt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s2mm_halt_cmpt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
---- if(m_axi_sg_aresetn = '0')then
---- s2mm_halt_cmpt_d1_cdc_tig <= '0';
---- s2mm_halt_cmpt_d2 <= '0';
---- else
-- s2mm_halt_cmpt_d1_cdc_tig <= s2mm_halt_cmplt;
-- s2mm_halt_cmpt_cdc_d2 <= s2mm_halt_cmpt_d1_cdc_tig;
---- end if;
-- end if;
-- end process REG_TO_SECONDARY;
s2mm_halt_cmpt_d2 <= s2mm_halt_cmpt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
s2mm_halt_cmpt_d2 <= s2mm_halt_cmplt;
end generate GEN_FOR_SYNC;
s2mm_datamover_idle <= '1' when (s2mm_stop = '1' and s2mm_halt_cmpt_d2 = '1')
or (s2mm_stop = '0')
else '0';
-------------------------------------------------------------------------------
-- Set halt bit if run/stop cleared and all processes are idle
-------------------------------------------------------------------------------
HALT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_halted_set <= '0';
elsif(s2mm_run_stop = '0' and all_is_idle = '1' and s2mm_datamover_idle = '1')then
s2mm_halted_set <= '1';
else
s2mm_halted_set <= '0';
end if;
end if;
end process HALT_PROCESS;
-------------------------------------------------------------------------------
-- Clear halt bit if run/stop is set and SG engine begins to fetch descriptors
-------------------------------------------------------------------------------
NOT_HALTED_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_halted_clr <= '0';
elsif(s2mm_run_stop = '1')then
s2mm_halted_clr <= '1';
else
s2mm_halted_clr <= '0';
end if;
end if;
end process NOT_HALTED_PROCESS;
-------------------------------------------------------------------------------
-- Register ALL is Idle to create rising and falling edges on idle flag
-------------------------------------------------------------------------------
IDLE_REG_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
all_is_idle_d1 <= '0';
else
all_is_idle_d1 <= all_is_idle;
end if;
end if;
end process IDLE_REG_PROCESS;
all_is_idle_re <= all_is_idle and not all_is_idle_d1;
all_is_idle_fe <= not all_is_idle and all_is_idle_d1;
-- Set or Clear IDLE bit in DMASR
s2mm_idle_set <= all_is_idle_re and s2mm_run_stop;
s2mm_idle_clr <= all_is_idle_fe;
end implementation;
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| bsd-2-clause | 8793038df1c19b5d5e61fb6f8bb16e25 | 0.949128 | 1.823085 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/vhdlFile/block_header/classification_test_input.vhd | 1 | 1,713 |
architecture RTL of BLOCK_EXAMPLE is
begin
-- correct block format
BLK : block is
generic (
A : std_logic;
B : integer;
E, F : positive
);
generic map (
A => B,
B => C,
E => X,
F => Z
);
port (
A : std_logic;
B : integer;
E, F : positive
);
port map (
A => B,
B => C,
E => X,
F => Z
);
begin
end block BLK;
-- correct block format
BLK : block is
generic map (
A => B,
B => C,
E => X,
F => Z
);
port (
A : std_logic;
B : integer;
E, F : positive
);
port map (
A => B,
B => C,
E => X,
F => Z
);
begin
end block BLK;
-- correct block format
BLK : block is
generic (
A : std_logic;
B : integer;
E, F : positive
);
port (
A : std_logic;
B : integer;
E, F : positive
);
port map (
A => B,
B => C,
E => X,
F => Z
);
begin
end block BLK;
-- correct block format
BLK : block is
generic (
A : std_logic;
B : integer;
E, F : positive
);
generic map (
A => B,
B => C,
E => X,
F => Z
);
port map (
A => B,
B => C,
E => X,
F => Z
);
begin
end block BLK;
-- correct block format
BLK : block is
generic (
A : std_logic;
B : integer;
E, F : positive
);
generic map (
A => B,
B => C,
E => X,
F => Z
);
port (
A : std_logic;
B : integer;
E, F : positive
);
begin
end block BLK;
end architecture RTL;
| gpl-3.0 | df7290661fabc6c27f30fddb906ecc62 | 0.388792 | 3.510246 | false | false | false | false |
siavooshpayandehazad/TTU_CPU_Project | pico_CPU_pipelined/DPU.vhd | 1 | 5,186 | library IEEE;
use IEEE.std_logic_1164.all;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_misc.all;
use IEEE.Numeric_Std.all;
use work.pico_cpu.all;
--DPU entity
entity DPU is
generic (BitWidth: integer);
port (
rst: in std_logic;
clk: in std_logic;
Data_in_mem: in std_logic_vector (BitWidth-1 downto 0);
Data_in_RegFile: in std_logic_vector (BitWidth-1 downto 0);
Data_in_control: in std_logic_vector (BitWidth-1 downto 0);
Command: in std_logic_vector (10 downto 0);
DPU_Flags: out std_logic_vector (3 downto 0);
DPU_Flags_FF: out std_logic_vector (3 downto 0);
Result_bypass: out std_logic_vector (BitWidth-1 downto 0);
Result: out std_logic_vector (BitWidth-1 downto 0)
);
end DPU;
--Architecture of the DPU
architecture RTL of DPU is
---------------------------------------------
-- Signals
---------------------------------------------
signal ACC_in,ACC_out: std_logic_vector (BitWidth-1 downto 0);
signal Mux_Out: std_logic_vector (BitWidth-1 downto 0):= (others=>'0');
---------------------------------------------
-- Flags
---------------------------------------------
signal EQ_Flag_out, EQ_Flag_in: std_logic := '0';
signal OV_Flag_out, OV_Flag_in: std_logic := '0';
signal Z_Flag_out, Z_Flag_in: std_logic := '0';
signal C_flag_in, C_flag_out, Cout:std_logic := '0';
signal OV_Flag_Value :std_logic := '0';
---------------------------------------------
-- Opcode Aliases
---------------------------------------------
alias Mux_Cont : std_logic_vector (1 downto 0) is Command (1 downto 0);
alias SetFlag : std_logic_vector (2 downto 0) is Command (8 downto 6);
alias ALUCommand : std_logic_vector (3 downto 0) is Command (5 downto 2);
begin
ALU_comp: ALU
generic map (BitWidth => BitWidth)
port map (ACC_out, Mux_Out, ALUCommand, C_flag_out, Cout, ACC_in);
---------------------------------------------
-- Registers and Flags
---------------------------------------------
process (clk,rst)
begin
if rst = '1' then
ACC_out<=(others =>'0');
OV_Flag_out <= '0';
Z_Flag_out <= '0';
EQ_Flag_out <= '0';
C_flag_out <= '0';
elsif clk'event and clk= '1' then
ACC_out <= ACC_in;
OV_Flag_out <= OV_Flag_in;
Z_Flag_out <= Z_Flag_in;
EQ_Flag_out <= EQ_Flag_in;
C_flag_out <= C_flag_in;
end if;
end process;
---------------------------------------------
-- ALU 2nd Input multiplexer
---------------------------------------------
process (Data_in_mem, Data_in_control, Data_in_RegFile, Mux_Cont)
begin
case Mux_Cont is
when "00" => Mux_Out <= Data_in_mem;
when "01" => Mux_Out <= Data_in_control;
when "10" => Mux_Out <= Data_in_RegFile;
when "11" => Mux_Out <= std_logic_vector(to_unsigned(1, BitWidth));
when others => Mux_Out <= std_logic_vector(to_unsigned(0, BitWidth));
end case;
end process;
OV_Flag_Value <= (ACC_in(BitWidth-1 ) and Mux_Out(BitWidth-1 ) and (not ACC_out(BitWidth-1 ))) or ((not ACC_in(BitWidth-1 )) and (not Mux_Out(BitWidth-1)) and ACC_out(BitWidth-1));
---------------------------------------------
-- Flag controls
---------------------------------------------
process(SetFlag, ALUCommand, ACC_in, OV_Flag_Value, Data_in_control, Cout, ACC_out, EQ_Flag_out,
Z_Flag_out, C_flag_out, OV_Flag_out)
begin
----------------------------------
if SetFlag = "011" then
EQ_Flag_in <= '0';
else
if ALUCommand /= "0010" then
if (ACC_out = Data_in_control) then
EQ_Flag_in <= '1';
else
EQ_Flag_in <= '0';
end if;
else
EQ_Flag_in <= EQ_Flag_out;
end if;
end if;
----------------------------------
if SetFlag = "001" then
Z_Flag_in <= '0';
else
if ALUCommand /= "0010" then
Z_Flag_in <= not (or_reduce(ACC_in));
else
Z_Flag_in <= Z_Flag_out;
end if;
end if;
----------------------------------
if SetFlag = "100" then
C_flag_in <= '0';
else
if ALUCommand /= "0010" and ALUCommand /= "1110" and ALUCommand /= "1111" then
C_flag_in <= Cout;
elsif ALUCommand = "1110" then --RRC
C_flag_in <= ACC_out(0);
elsif ALUCommand = "1111" then --RLC
C_flag_in <= ACC_out(BitWidth-1);
else
C_flag_in <= C_flag_out;
END IF;
end if;
----------------------------------
if SetFlag = "010" then
OV_Flag_in <= '0';
else
if (ALUCommand = "0000" or ALUCommand = "0001") then
OV_Flag_in <= OV_Flag_Value;
else
OV_Flag_in <= OV_Flag_out;
end if;
end if;
----------------------------------
end process;
Result_bypass <= ACC_in;
Result <= ACC_out;
DPU_Flags <= C_flag_in & EQ_Flag_in & Z_Flag_in & OV_Flag_in;
DPU_Flags_FF <= C_flag_out & EQ_Flag_out & Z_Flag_out & OV_Flag_out;
end RTL;
| gpl-2.0 | 51235e0727c909897bbae1026ab3965d | 0.476668 | 3.576552 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/ramfifo/rd_pe_sshft.vhd | 2 | 17,676 | `protect begin_protected
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| bsd-2-clause | 4e1d0f09f66e69c5626616bec9f703d3 | 0.938391 | 1.853607 | false | false | false | false |
Logistic1994/CPU | module_CLK.vhd | 1 | 1,957 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:22:45 05/10/2015
-- Design Name:
-- Module Name: MyClk - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity module_CLK is
port (
clk: in std_logic;
nreset: in std_logic;
clk1, nclk1: out std_logic;
clk2, nclk2: out std_logic;
w0, w1, w2, w3: out std_logic);
end module_CLK;
architecture Behavioral of module_CLK is
signal count1: integer range 0 to 3;
signal count2: integer range 0 to 3;
signal count3: std_logic;
begin
clk1 <= clk;
nclk1 <= not clk;
clk2 <= count3;
nclk2 <= not count3;
process(nreset, clk)
begin
if nreset = '0' then
count1 <= 0;
count2 <= 0;
count3 <= '0';
w0 <= '0';w1 <= '0';w2 <= '0';w3 <= '0';
elsif rising_edge(clk) then
count3 <= not count3;
if count1 = 0 then
if count2 = 0 then
w0 <= '1';w1 <= '0';w2 <= '0';w3 <= '0';
elsif count2 = 1 then
w0 <= '0';w1 <= '1';w2 <= '0';w3 <= '0';
elsif count2 = 2 then
w0 <= '0';w1 <= '0';w2 <= '1';w3 <= '0';
else
w0 <= '0';w1 <= '0';w2 <= '0';w3 <= '1';
end if;
if count2 = 3 then
count2 <= 0;
else
count2 <= count2 + 1;
end if;
end if;
if count1 = 1 then
count1 <= 0;
else
count1 <= count1 + 1;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | 4444db066a9c59ddc116e8b1e02d1093 | 0.541134 | 2.974164 | false | false | false | false |
kb3gtn/mojo_dactest | src/mojo_top.vhd | 1 | 14,375 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity mojo_top is
Port (
clk50m : in STD_LOGIC;
rst_n : in STD_LOGIC;
--cclk : in STD_LOGIC; -- spi/fpga programming clock (not used).
led : out STD_LOGIC_VECTOR (7 downto 0); -- board LEDs
-- spi interface shared with AVR and SPI flash chip (not used here)
--spi_mosi : in STD_LOGIC;
--spi_miso : out STD_LOGIC;
--spi_ss : in STD_LOGIC;
--spi_sck : in STD_LOGIC;
--spi_channel : in STD_LOGIC_VECTOR (3 downto 0); ( not used here)
-- avr rs232 interface (ttl levels) ( not used here )
-- avr_tx : in STD_LOGIC;
-- avr_rx : in STD_LOGIC;
-- avr_rx_busy : in STD_LOGIC
-- RS232
serial_tx : out STD_LOGIC; -- 3rd pin up from uC outside.
serial_rx : in STD_LOGIC; -- 4th pin up from uC outside.
-- Dac Interface
dac_reset : out STD_LOGIC;
dac_sleep : out STD_LOGIC;
dac_mode : out STD_LOGIC;
dac_cmode : out STD_LOGIC;
dac_clk_p : out STD_LOGIC;
dac_clk_n : out STD_LOGIC;
dac_DB : out signed( 11 downto 0 )
);
end mojo_top;
architecture Behavioral of mojo_top is
--#########################################################
--# Component Definitions
--#########################################################
component uart is
port (
i_clk : in std_logic; -- system clock
i_srst : in std_logic; -- synchronious reset, 1 - active
i_baud_div : in std_logic_vector(15 downto 0); -- clk divider to get to baud rate
-- uart interface
o_uart_tx : out std_logic; -- tx bit stream
i_uart_rx : in std_logic; -- uart rx bit stream input
-- fpga side
i_tx_send : in std_logic_vector(7 downto 0); -- data byte in
i_tx_send_we : in std_logic; -- write enable
o_tx_send_busy : out std_logic; -- tx is busy, writes are ignored.
o_rx_read : out std_logic_vector(7 downto 0); -- data byte out
o_rx_read_valid : out std_logic; -- read data valid this clock cycle
i_rx_read_rd : in std_logic -- read request, get next byte..
);
end component uart;
component uart_db_interface is
port (
i_clk : in std_logic; -- input system clock
i_srst : in std_logic; -- sync reset to system clock
-- uart interface
i_rx_data : in std_logic_vector( 7 downto 0); -- data from uart
i_rx_data_valid : in std_logic; -- valid data from uart
o_rx_read_ack : out std_logic; -- tell uart we have read byte.
o_tx_send : out std_logic_vector( 7 downto 0); -- tx_send data
o_tx_send_wstrb : out std_logic; -- write data strobe
i_tx_send_busy : in std_logic; -- uart is busy tx, don't write anything.. (stall)
-- databus master interface
o_db_cmd_wstrb : out std_logic; -- write command strobe
o_db_cmd_out : out std_logic_vector( 7 downto 0); -- cmd to databus master
o_db_cmd_data_out : out std_logic_vector( 7 downto 0); -- write data to databus master
i_db_cmd_data_in : in std_logic_vector( 7 downto 0); -- read data from databus master
i_db_cmd_rdy : in std_logic -- db is ready to process a cmd / previous cmd is complete.
);
end component;
component databus_master is
generic (
slave_latency_max : integer := 3 -- latency from read/write strb to when the
-- operation is complete in number of i_clk cycles.
-- 3 would give a slave 3 clock cycles to perform
-- the needed operation.
);
port (
-- clock and resets
i_clk : in std_logic; -- input system clock
i_srst : in std_logic; -- sync reset to system clock
-- db master cmd interface
i_db_cmd_in : in std_logic_vector( 7 downto 0); -- input cmd byte
i_db_cmd_wstrb : in std_logic; -- write strobe for cmd byte
o_db_cmd_rdy : out std_logic; -- '1' rdy to process next cmd, '0' busy
i_db_cmd_data_in : in std_logic_vector( 7 downto 0); -- input byte if cmd is a write (with wstrb)
o_db_cmd_data_out : out std_logic_vector( 7 downto 0); -- output byte if cmd was a read
-- data bus interface
o_db_addr : out std_logic_vector( 6 downto 0); -- 6 -> 0 bit address bus (7 bits)
o_db_write_data : out std_logic_vector( 7 downto 0); -- write data
i_db_read_data : in std_logic_vector( 7 downto 0); -- read data
o_db_read_strb : out std_logic; -- db_read_strobe
o_db_write_strb : out std_logic -- db_write_strobe
);
end component;
component dac_test is
port (
i_clk : in std_logic;
i_rst : in std_logic;
------------------------------------------
o_dac_cmode : out std_logic;
o_dac_mode : out std_logic;
o_dac_reset : out std_logic;
o_dac_sleep : out std_logic;
o_dac_clk : out std_logic;
o_dac_db : out signed(11 downto 0);
------------------------------------------
i_nco_ftw : in unsigned(31 downto 0)
);
end component dac_test;
--###########################################################
--# Signal Definitions
--###########################################################
-- uart signals
signal baud_div : std_logic_vector( 15 downto 0);
signal tx_byte : std_logic_vector( 7 downto 0);
signal tx_byte_we : std_logic;
signal tx_byte_busy : std_logic;
signal rx_byte : std_logic_vector( 7 downto 0);
signal rx_byte_valid : std_logic;
signal rx_byte_rd : std_logic;
-- data bus master signals
signal db_cmd : std_logic_vector( 7 downto 0 );
signal db_cmd_wstrb : std_logic;
signal db_cmd_rdy : std_logic;
signal db_cmd_wr_data : std_logic_vector( 7 downto 0 );
signal db_cmd_rd_data : std_logic_vector( 7 downto 0 );
-- data bus interface to slaves
signal db_addr : std_logic_vector(6 downto 0);
signal db_wr_data : std_logic_vector(7 downto 0);
signal db_rd_data : std_logic_vector(7 downto 0);
signal db_wr_strb : std_logic;
signal db_rd_strb : std_logic;
-- output register for driving the LEDs
signal led_reg : std_logic_vector(7 downto 0);
-- nco registers
signal nco_reg0 : unsigned( 7 downto 0 );
signal nco_reg1 : unsigned( 7 downto 0 );
signal nco_reg2 : unsigned( 7 downto 0 );
signal nco_reg3 : unsigned( 7 downto 0 );
signal nco_update_state : std_logic_vector( 3 downto 0 );
signal nco_ftw : unsigned( 31 downto 0 );
signal dac_clk : std_logic;
signal dac_sample : signed(11 downto 0);
-- sync reset signal to 50 MHz clk
signal srst : std_logic;
begin
led <= led_reg;
-- led <= rx_byte;
baud_div <= x"01B2"; -- 115200
uart_1 : uart
port map (
i_clk => clk50m,
i_srst => srst,
i_baud_div => baud_div,
-- uart interface
o_uart_tx => serial_tx,
i_uart_rx => serial_rx,
-- fpga side
i_tx_send => tx_byte,
i_tx_send_we => tx_byte_we,
o_tx_send_busy => tx_byte_busy,
o_rx_read => rx_byte,
o_rx_read_valid => rx_byte_valid,
i_rx_read_rd => rx_byte_rd
);
udbi_1 : uart_db_interface
port map (
i_clk => clk50m,
i_srst => srst,
-- uart interface
i_rx_data => rx_byte,
i_rx_data_valid => rx_byte_valid,
o_rx_read_ack => rx_byte_rd,
o_tx_send => tx_byte,
o_tx_send_wstrb => tx_byte_we,
i_tx_send_busy => tx_byte_busy,
-- databus master interface
o_db_cmd_wstrb => db_cmd_wstrb,
o_db_cmd_out => db_cmd,
o_db_cmd_data_out => db_cmd_wr_data,
i_db_cmd_data_in => db_cmd_rd_data,
i_db_cmd_rdy => db_cmd_rdy
);
db_master_1 : databus_master
generic map (
slave_latency_max => 3 -- latency from read/write strb to when the
-- operation is complete in number of i_clk cycles.
-- 3 would give a slave 3 clock cycles to perform
-- the needed operation.
)
port map (
-- clock and resets
i_clk => clk50m,
i_srst => srst,
-- db master cmd interface
i_db_cmd_in => db_cmd,
i_db_cmd_wstrb => db_cmd_wstrb,
o_db_cmd_rdy => db_cmd_rdy,
i_db_cmd_data_in => db_cmd_wr_data,
o_db_cmd_data_out => db_cmd_rd_data,
-- data bus interface
o_db_addr => db_addr,
o_db_write_data => db_wr_data,
i_db_read_data => db_rd_data,
o_db_read_strb => db_rd_strb,
o_db_write_strb => db_wr_strb
);
-- generate synchronious reset signal for
-- synchronious blocks
rst_sync : process( clk50m )
begin
if ( rising_edge(clk50m) ) then
if ( rst_n = '0' ) then
-- reset active
srst <= '1';
-- for now, just hardcode the nco rate at startup
-- 0x1AE ~= 10 Hz rate.. (10.0117176818 Hz)
-- freq = (nco_ftw / 2^31-1)*50e6
-- nco_ftw = ( Freq / 50e6 ) * (2^31-1)
-- nco_ftw <= x"000001AE";
else
srst <= '0';
end if;
end if;
end process;
-- simple data bus slave to control LEDs on address 3
led_ctrl : process( clk50m )
begin
if ( rising_edge( clk50m ) ) then
if ( srst = '1' ) then
led_reg <= (others=>'0');
else
if ( db_wr_strb = '1' ) then
-- if address 0x03
if ( db_addr = "0000011" ) then
led_reg <= db_wr_data;
end if;
end if;
if ( db_rd_strb = '1' ) then
if ( db_addr = "0000011" ) then
db_rd_data <= led_reg;
end if;
else
db_rd_data <= (others=>'Z');
end if;
end if;
end if;
end process;
-- memory map register for DAC, write only registers.
-- have to write to all 4 to update the nco_ftw. order dosn't mater.
DAC_REGS : process( clk50m )
begin
if ( rising_edge(clk50m) ) then
if ( srst = '1' ) then
nco_ftw <= x"051eb852"; -- ~ 1 MHz cycle rate..
else
if ( db_wr_strb = '1' ) then
if ( db_addr = "0000100" ) then -- addr 4
nco_reg0 <= unsigned(db_wr_data);
nco_update_state(0) <= '1';
end if;
if ( db_addr = "0000101" ) then -- addr 5
nco_reg1 <= unsigned(db_wr_data);
nco_update_state(1) <= '1';
end if;
if ( db_addr = "0000110" ) then -- addr 6
nco_reg2 <= unsigned(db_wr_data);
nco_update_state(2) <= '1';
end if;
if ( db_addr = "0000111" ) then -- addr 7
nco_reg3 <= unsigned(db_wr_data);
nco_update_state(3) <= '1';
end if;
if ( nco_update_state <= "1111" ) then
nco_update_state <= (others=>'0');
nco_ftw <= nco_reg0 & nco_reg1 & nco_reg2 & nco_reg3;
end if;
end if;
end if;
end if;
end process;
-- single ended to differental IO driver block.. (Xilinx)
OBUFDS_inst : OBUFDS
generic map (
IOSTANDARD => "DEFAULT"
)
port map (
O => dac_clk_p, -- P clk pin
OB => dac_clk_n, -- N clk pin
I => dac_clk -- input clock
);
u_dac_test : dac_test
port map (
i_clk => clk50m,
i_rst => srst,
------------------------------------------
o_dac_cmode => dac_cmode,
o_dac_mode => dac_mode,
o_dac_reset => dac_reset,
o_dac_sleep => dac_sleep,
o_dac_clk => dac_clk,
o_dac_db => dac_sample,
------------------------------------------
i_nco_ftw => nco_ftw
);
dac_sample_latch : process( dac_clk )
begin
if ( rising_edge(dac_clk) ) then
dac_DB <= dac_sample;
end if;
end process;
end architecture;
| apache-2.0 | 23cd7cb44e2d235fd3e911a42f525164 | 0.442365 | 3.911565 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_skid_buf.vhd | 1 | 18,843 | -------------------------------------------------------------------------------
-- axi_datamover_skid_buf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_skid_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_datamover_skid_buf.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
--
-- History:
-- DET 04/19/2011 Initial Version for EDK 13.3
--
-- DET 6/20/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Added 512 and 1024 data width support
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_skid_buf is
generic (
C_WDATA_WIDTH : INTEGER := 32
-- Width of the Stream Data bus (in bits)
);
port (
-- Clock and Reset Inputs ---------------------------------------------
aclk : In std_logic ; --
arst : In std_logic ; --
-----------------------------------------------------------------------
-- Shutdown control (assert for 1 clk pulse) --------------------------
--
skid_stop : In std_logic ; --
-----------------------------------------------------------------------
-- Slave Side (Stream Data Input) -------------------------------------
s_valid : In std_logic ; --
s_ready : Out std_logic ; --
s_data : In std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
s_strb : In std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
s_last : In std_logic ; --
-----------------------------------------------------------------------
-- Master Side (Stream Data Output ------------------------------------
m_valid : Out std_logic ; --
m_ready : In std_logic ; --
m_data : Out std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
m_strb : Out std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
m_last : Out std_logic --
-----------------------------------------------------------------------
);
end entity axi_datamover_skid_buf;
architecture implementation of axi_datamover_skid_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_stop_request : std_logic := '0';
signal sig_stopped : std_logic := '0';
signal sig_sready_stop : std_logic := '0';
signal sig_sready_early_stop : std_logic := '0';
signal sig_sready_stop_set : std_logic := '0';
signal sig_sready_stop_reg : std_logic := '0';
signal sig_mvalid_stop_reg : std_logic := '0';
signal sig_mvalid_stop : std_logic := '0';
signal sig_mvalid_early_stop : std_logic := '0';
signal sig_mvalid_stop_set : std_logic := '0';
signal sig_slast_with_stop : std_logic := '0';
signal sig_sstrb_stop_mask : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_sstrb_with_stop : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
m_valid <= sig_m_valid_out;
s_ready <= sig_s_ready_out;
m_strb <= sig_strb_reg_out;
m_last <= sig_last_reg_out;
m_data <= sig_data_reg_out;
-- Special shutdown logic version od Slast.
-- A halt request forces a tlast through the skig buffer
sig_slast_with_stop <= s_last or sig_stop_request;
sig_sstrb_with_stop <= s_strb or sig_sstrb_stop_mask;
-- Assign the special s_ready FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= m_ready or not(sig_m_valid_dup);
-- Generate the skid input register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else s_data;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_sstrb_with_stop;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_slast_with_stop;
-- m_valid combinational logic
sig_m_valid_comb <= s_valid or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(m_ready)));
-- s_ready combinational logic
sig_s_ready_comb <= m_ready or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(s_valid)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers s_ready handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_sready_stop = '1' or
sig_sready_early_stop = '1') then -- Special stop condition
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers m_valid handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1' or -- Fix from AXI DMA
sig_mvalid_stop = '1' or
sig_mvalid_stop_set = '1') then -- Special stop condition
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
SKID_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_data_skid_reg <= (others => '0');
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_data_skid_reg <= s_data;
sig_strb_skid_reg <= sig_sstrb_with_stop;
sig_last_skid_reg <= sig_slast_with_stop;
else
null; -- hold current state
end if;
end if;
end process SKID_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_mvalid_stop_reg = '1') then
sig_data_reg_out <= (others => '0');
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_REG;
-------- Special Stop Logic --------------------------------------
sig_sready_stop <= sig_sready_stop_reg;
sig_sready_early_stop <= skid_stop; -- deassert S_READY immediately
sig_sready_stop_set <= sig_sready_early_stop;
sig_mvalid_stop <= sig_mvalid_stop_reg;
sig_mvalid_early_stop <= sig_m_valid_dup and
m_ready and
skid_stop;
sig_mvalid_stop_set <= sig_mvalid_early_stop or
(sig_stop_request and
not(sig_m_valid_dup)) or
(sig_m_valid_dup and
m_ready and
sig_stop_request);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STOP_REQ_FLOP
--
-- Process Description:
-- This process implements the Stop request flop. It is a
-- sample and hold register that can only be cleared by reset.
--
-------------------------------------------------------------
IMP_STOP_REQ_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_stop_request <= '0';
sig_sstrb_stop_mask <= (others => '0');
elsif (skid_stop = '1') then
sig_stop_request <= '1';
sig_sstrb_stop_mask <= (others => '1');
else
null; -- hold current state
end if;
end if;
end process IMP_STOP_REQ_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_SREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the s_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_SREADY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_sready_stop_reg <= '0';
elsif (sig_sready_stop_set = '1') then
sig_sready_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_SREADY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_MVALID_FLOP
--
-- Process Description:
-- This process implements the flag to clear the m_valid
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_MVALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_mvalid_stop_reg <= '0';
elsif (sig_mvalid_stop_set = '1') then
sig_mvalid_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_MVALID_FLOP;
end implementation;
| bsd-2-clause | a038587759eb16f6cc2e9c42886e5819 | 0.456084 | 4.49499 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_dma_v7_1/hdl/src/vhdl/axi_dma_mm2s_mngr.vhd | 1 | 49,915 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_mngr.vhd
-- Description: This entity is the top level entity for the AXI DMA MM2S
-- manager.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_mngr is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
-----------------------------------------------------------------------
-- Memory Map to Stream (MM2S) Parameters
-----------------------------------------------------------------------
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary Clock and Reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
soft_reset : in std_logic ; --
--
-- MM2S Control and Status --
mm2s_run_stop : in std_logic ; --
mm2s_keyhole : in std_logic ;
mm2s_halted : in std_logic ; --
mm2s_ftch_idle : in std_logic ; --
mm2s_updt_idle : in std_logic ; --
mm2s_ftch_err_early : in std_logic ; --
mm2s_ftch_stale_desc : in std_logic ; --
mm2s_tailpntr_enble : in std_logic ; --
mm2s_halt : in std_logic ; --
mm2s_halt_cmplt : in std_logic ; --
mm2s_halted_clr : out std_logic ; --
mm2s_halted_set : out std_logic ; --
mm2s_idle_set : out std_logic ; --
mm2s_idle_clr : out std_logic ; --
mm2s_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
mm2s_new_curdesc_wren : out std_logic ; --
mm2s_stop : out std_logic ; --
mm2s_desc_flush : out std_logic ; --
cntrl_strm_stop : out std_logic ;
mm2s_all_idle : out std_logic ; --
--
mm2s_error : out std_logic ; --
s2mm_error : in std_logic ; --
-- Simple DMA Mode Signals
mm2s_sa : in std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
mm2s_length_wren : in std_logic ; --
mm2s_length : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
mm2s_smple_done : out std_logic ; --
mm2s_interr_set : out std_logic ; --
mm2s_slverr_set : out std_logic ; --
mm2s_decerr_set : out std_logic ; --
m_axis_mm2s_aclk : in std_logic;
mm2s_strm_tlast : in std_logic;
mm2s_strm_tready : in std_logic;
mm2s_axis_info : out std_logic_vector
(13 downto 0);
--
-- SG MM2S Descriptor Fetch AXI Stream In --
m_axis_mm2s_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_ftch_tvalid : in std_logic ; --
m_axis_mm2s_ftch_tready : out std_logic ; --
m_axis_mm2s_ftch_tlast : in std_logic ; --
m_axis_mm2s_ftch_tdata_new : in std_logic_vector --
(96 downto 0); --
m_axis_mm2s_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_mm2s_ftch_tvalid_new : in std_logic ; --
m_axis_ftch1_desc_available : in std_logic;
--
-- SG MM2S Descriptor Update AXI Stream Out --
s_axis_mm2s_updtptr_tdata : out std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis_mm2s_updtptr_tvalid : out std_logic ; --
s_axis_mm2s_updtptr_tready : in std_logic ; --
s_axis_mm2s_updtptr_tlast : out std_logic ; --
--
s_axis_mm2s_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_mm2s_updtsts_tvalid : out std_logic ; --
s_axis_mm2s_updtsts_tready : in std_logic ; --
s_axis_mm2s_updtsts_tlast : out std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_mm2s_cmd_tvalid : out std_logic ; --
s_axis_mm2s_cmd_tready : in std_logic ; --
s_axis_mm2s_cmd_tdata : out std_logic_vector --
((2*C_M_AXI_MM2S_ADDR_WIDTH+CMD_BASE_WIDTH+46)-1 downto 0);--
--
-- User Status Interface Ports (AXI Stream) --
m_axis_mm2s_sts_tvalid : in std_logic ; --
m_axis_mm2s_sts_tready : out std_logic ; --
m_axis_mm2s_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_mm2s_sts_tkeep : in std_logic_vector(0 downto 0) ; --
mm2s_err : in std_logic ; --
--
ftch_error : in std_logic ; --
updt_error : in std_logic ; --
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_dma_mm2s_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
attribute mark_debug : string;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Primary DataMover Command signals
signal mm2s_cmnd_wr : std_logic := '0';
signal mm2s_cmnd_data : std_logic_vector
((2*C_M_AXI_MM2S_ADDR_WIDTH+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal mm2s_cmnd_pending : std_logic := '0';
attribute mark_debug of mm2s_cmnd_data : signal is "true";
-- Primary DataMover Status signals
signal mm2s_done : std_logic := '0';
signal mm2s_stop_i : std_logic := '0';
signal mm2s_interr : std_logic := '0';
signal mm2s_slverr : std_logic := '0';
signal mm2s_decerr : std_logic := '0';
attribute mark_debug of mm2s_interr : signal is "true";
attribute mark_debug of mm2s_slverr : signal is "true";
attribute mark_debug of mm2s_decerr : signal is "true";
signal mm2s_tag : std_logic_vector(3 downto 0) := (others => '0');
signal dma_mm2s_error : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_d2 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
signal mm2s_error_i : std_logic := '0';
--signal cntrl_strm_stop : std_logic := '0';
signal mm2s_halted_set_i : std_logic := '0';
signal mm2s_sts_received_clr : std_logic := '0';
signal mm2s_sts_received : std_logic := '0';
signal mm2s_cmnd_idle : std_logic := '0';
signal mm2s_sts_idle : std_logic := '0';
-- Scatter Gather Interface signals
signal desc_fetch_req : std_logic := '0';
signal desc_fetch_done : std_logic := '0';
signal desc_fetch_done_del : std_logic := '0';
signal desc_update_req : std_logic := '0';
signal desc_update_done : std_logic := '0';
signal desc_available : std_logic := '0';
signal packet_in_progress : std_logic := '0';
signal mm2s_desc_baddress : std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength_v : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength_s : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_eof : std_logic := '0';
signal mm2s_desc_sof : std_logic := '0';
signal mm2s_desc_cmplt : std_logic := '0';
signal mm2s_desc_info : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_info_int : std_logic_vector(13 downto 0) := (others => '0');
signal mm2s_strm_tlast_int : std_logic;
signal rd_en_hold, rd_en_hold_int : std_logic;
-- Control Stream Fifo write signals
signal cntrlstrm_fifo_wren : std_logic := '0';
signal cntrlstrm_fifo_full : std_logic := '0';
signal cntrlstrm_fifo_din : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal info_fifo_full : std_logic;
signal info_fifo_empty : std_logic;
signal updt_pending : std_logic := '0';
signal mm2s_cmnd_wr_1 : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Include MM2S State Machine and support logic
-------------------------------------------------------------------------------
GEN_MM2S_DMA_CONTROL : if C_INCLUDE_MM2S = 1 generate
begin
-- Pass out to register module
mm2s_halted_set <= mm2s_halted_set_i;
-------------------------------------------------------------------------------
-- Graceful shut down logic
-------------------------------------------------------------------------------
-- Error from DataMover (DMAIntErr, DMADecErr, or DMASlvErr) or SG Update error
-- or SG Fetch error, or Stale Descriptor Error
mm2s_error_i <= dma_mm2s_error -- Primary data mover reports error
or updt_error -- SG Update engine reports error
or ftch_error -- SG Fetch engine reports error
or mm2s_ftch_err_early -- SG Fetch engine reports early error on mm2s
or mm2s_ftch_stale_desc; -- SG Fetch stale descriptor error
-- pass out to shut down s2mm
mm2s_error <= mm2s_error_i;
-- Clear run/stop and stop state machines due to errors or soft reset
-- Error based on datamover error report or sg update error or sg fetch error
-- SG update error and fetch error included because need to shut down, no way
-- to update descriptors on sg update error and on fetch error descriptor
-- data is corrupt therefor do not want to issue the xfer command to primary datamover
--CR#566306 status for both mm2s and s2mm datamover are masked during shutdown therefore
-- need to stop all processes regardless of the source of the error.
-- mm2s_stop_i <= mm2s_error -- Error
-- or soft_reset; -- Soft Reset issued
mm2s_stop_i <= mm2s_error_i -- Error on MM2S
or s2mm_error -- Error on S2MM
or soft_reset; -- Soft Reset issued
-- Reg stop out
REG_STOP_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop <= '0';
else
mm2s_stop <= mm2s_stop_i;
end if;
end if;
end process REG_STOP_OUT;
-- Generate DMA Controller For Scatter Gather Mode
GEN_SCATTER_GATHER_MODE : if C_INCLUDE_SG = 1 generate
begin
-- Not Used in SG Mode (Errors are imbedded in updated descriptor and
-- generate error after descriptor update is complete)
mm2s_interr_set <= '0';
mm2s_slverr_set <= '0';
mm2s_decerr_set <= '0';
mm2s_smple_done <= '0';
mm2s_cmnd_wr_1 <= m_axis_mm2s_ftch_tvalid_new;
---------------------------------------------------------------------------
-- MM2S Primary DMA Controller State Machine
---------------------------------------------------------------------------
I_MM2S_SM : entity axi_dma_v7_1.axi_dma_mm2s_sm
generic map(
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
mm2s_run_stop => mm2s_run_stop ,
mm2s_keyhole => mm2s_keyhole ,
mm2s_ftch_idle => mm2s_ftch_idle ,
mm2s_cmnd_idle => mm2s_cmnd_idle ,
mm2s_sts_idle => mm2s_sts_idle ,
mm2s_stop => mm2s_stop_i ,
mm2s_desc_flush => mm2s_desc_flush ,
-- MM2S Descriptor Fetch Request (from mm2s_sm)
desc_available => desc_available ,
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
desc_update_done => desc_update_done ,
updt_pending => updt_pending ,
packet_in_progress => packet_in_progress ,
-- DataMover Command
mm2s_cmnd_wr => open, --mm2s_cmnd_wr_1 ,
mm2s_cmnd_data => mm2s_cmnd_data ,
mm2s_cmnd_pending => mm2s_cmnd_pending ,
-- Descriptor Fields
mm2s_cache_info => mm2s_desc_info ,
mm2s_desc_baddress => mm2s_desc_baddress ,
mm2s_desc_blength => mm2s_desc_blength ,
mm2s_desc_blength_v => mm2s_desc_blength_v ,
mm2s_desc_blength_s => mm2s_desc_blength_s ,
mm2s_desc_eof => mm2s_desc_eof ,
mm2s_desc_sof => mm2s_desc_sof
);
---------------------------------------------------------------------------
-- MM2S Scatter Gather State Machine
---------------------------------------------------------------------------
I_MM2S_SG_IF : entity axi_dma_v7_1.axi_dma_mm2s_sg_if
generic map(
-------------------------------------------------------------------
-- Scatter Gather Parameters
-------------------------------------------------------------------
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA,
C_FAMILY => C_FAMILY
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- SG MM2S Descriptor Fetch AXI Stream In
m_axis_mm2s_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_mm2s_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_mm2s_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_mm2s_ftch_tlast => m_axis_mm2s_ftch_tlast ,
m_axis_mm2s_ftch_tdata_new => m_axis_mm2s_ftch_tdata_new ,
m_axis_mm2s_ftch_tdata_mcdma_new => m_axis_mm2s_ftch_tdata_mcdma_new ,
m_axis_mm2s_ftch_tvalid_new => m_axis_mm2s_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available ,
-- SG MM2S Descriptor Update AXI Stream Out
s_axis_mm2s_updtptr_tdata => s_axis_mm2s_updtptr_tdata ,
s_axis_mm2s_updtptr_tvalid => s_axis_mm2s_updtptr_tvalid ,
s_axis_mm2s_updtptr_tready => s_axis_mm2s_updtptr_tready ,
s_axis_mm2s_updtptr_tlast => s_axis_mm2s_updtptr_tlast ,
s_axis_mm2s_updtsts_tdata => s_axis_mm2s_updtsts_tdata ,
s_axis_mm2s_updtsts_tvalid => s_axis_mm2s_updtsts_tvalid ,
s_axis_mm2s_updtsts_tready => s_axis_mm2s_updtsts_tready ,
s_axis_mm2s_updtsts_tlast => s_axis_mm2s_updtsts_tlast ,
-- MM2S Descriptor Fetch Request (from mm2s_sm)
desc_available => desc_available ,
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
updt_pending => updt_pending ,
packet_in_progress => packet_in_progress ,
-- MM2S Descriptor Update Request
desc_update_done => desc_update_done ,
mm2s_ftch_stale_desc => mm2s_ftch_stale_desc ,
mm2s_sts_received_clr => mm2s_sts_received_clr ,
mm2s_sts_received => mm2s_sts_received ,
mm2s_desc_cmplt => mm2s_desc_cmplt ,
mm2s_done => mm2s_done ,
mm2s_interr => mm2s_interr ,
mm2s_slverr => mm2s_slverr ,
mm2s_decerr => mm2s_decerr ,
mm2s_tag => mm2s_tag ,
mm2s_halt => mm2s_halt , -- CR566306
-- Control Stream Output
cntrlstrm_fifo_wren => cntrlstrm_fifo_wren ,
cntrlstrm_fifo_full => cntrlstrm_fifo_full ,
cntrlstrm_fifo_din => cntrlstrm_fifo_din ,
-- MM2S Descriptor Field Output
mm2s_new_curdesc => mm2s_new_curdesc ,
mm2s_new_curdesc_wren => mm2s_new_curdesc_wren ,
mm2s_desc_baddress => mm2s_desc_baddress ,
mm2s_desc_blength => mm2s_desc_blength ,
mm2s_desc_blength_v => mm2s_desc_blength_v ,
mm2s_desc_blength_s => mm2s_desc_blength_s ,
mm2s_desc_info => mm2s_desc_info ,
mm2s_desc_eof => mm2s_desc_eof ,
mm2s_desc_sof => mm2s_desc_sof ,
mm2s_desc_app0 => mm2s_desc_app0 ,
mm2s_desc_app1 => mm2s_desc_app1 ,
mm2s_desc_app2 => mm2s_desc_app2 ,
mm2s_desc_app3 => mm2s_desc_app3 ,
mm2s_desc_app4 => mm2s_desc_app4
);
cntrlstrm_fifo_full <= '0';
end generate GEN_SCATTER_GATHER_MODE;
-- Generate DMA Controller for Simple DMA Mode
GEN_SIMPLE_DMA_MODE : if C_INCLUDE_SG = 0 generate
begin
-- Scatter Gather signals not used in Simple DMA Mode
m_axis_mm2s_ftch_tready <= '0';
s_axis_mm2s_updtptr_tdata <= (others => '0');
s_axis_mm2s_updtptr_tvalid <= '0';
s_axis_mm2s_updtptr_tlast <= '0';
s_axis_mm2s_updtsts_tdata <= (others => '0');
s_axis_mm2s_updtsts_tvalid <= '0';
s_axis_mm2s_updtsts_tlast <= '0';
desc_available <= '0';
desc_fetch_done <= '0';
packet_in_progress <= '0';
desc_update_done <= '0';
cntrlstrm_fifo_wren <= '0';
cntrlstrm_fifo_din <= (others => '0');
mm2s_new_curdesc <= (others => '0');
mm2s_new_curdesc_wren <= '0';
mm2s_desc_baddress <= (others => '0');
mm2s_desc_blength <= (others => '0');
mm2s_desc_blength_v <= (others => '0');
mm2s_desc_blength_s <= (others => '0');
mm2s_desc_eof <= '0';
mm2s_desc_sof <= '0';
mm2s_desc_cmplt <= '0';
mm2s_desc_app0 <= (others => '0');
mm2s_desc_app1 <= (others => '0');
mm2s_desc_app2 <= (others => '0');
mm2s_desc_app3 <= (others => '0');
mm2s_desc_app4 <= (others => '0');
desc_fetch_req <= '0';
-- Simple DMA State Machine
I_MM2S_SMPL_SM : entity axi_dma_v7_1.axi_dma_smple_sm
generic map(
C_M_AXI_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH,
C_MICRO_DMA => C_MICRO_DMA
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
run_stop => mm2s_run_stop ,
keyhole => mm2s_keyhole ,
stop => mm2s_stop_i ,
cmnd_idle => mm2s_cmnd_idle ,
sts_idle => mm2s_sts_idle ,
-- DataMover Status
sts_received => mm2s_sts_received ,
sts_received_clr => mm2s_sts_received_clr ,
-- DataMover Command
cmnd_wr => mm2s_cmnd_wr_1 ,
cmnd_data => mm2s_cmnd_data ,
cmnd_pending => mm2s_cmnd_pending ,
-- Trasnfer Qualifiers
xfer_length_wren => mm2s_length_wren ,
xfer_address => mm2s_sa ,
xfer_length => mm2s_length
);
-- Pass Done/Error Status out to DMASR
mm2s_interr_set <= mm2s_interr;
mm2s_slverr_set <= mm2s_slverr;
mm2s_decerr_set <= mm2s_decerr;
-- S2MM Simple DMA Transfer Done - used to assert IOC bit in DMASR.
-- Receive clear when not shutting down
mm2s_smple_done <= mm2s_sts_received_clr when mm2s_stop_i = '0'
-- Else halt set prior to halted being set
else mm2s_halted_set_i when mm2s_halted = '0'
else '0';
end generate GEN_SIMPLE_DMA_MODE;
-------------------------------------------------------------------------------
-- MM2S Primary DataMover command status interface
-------------------------------------------------------------------------------
I_MM2S_CMDSTS : entity axi_dma_v7_1.axi_dma_mm2s_cmdsts_if
generic map(
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL,
C_ENABLE_QUEUE => C_SG_INCLUDE_DESC_QUEUE
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Fetch command write interface from mm2s sm
mm2s_cmnd_wr => mm2s_cmnd_wr_1 ,
mm2s_cmnd_data => mm2s_cmnd_data ,
mm2s_cmnd_pending => mm2s_cmnd_pending ,
mm2s_sts_received_clr => mm2s_sts_received_clr ,
mm2s_sts_received => mm2s_sts_received ,
mm2s_tailpntr_enble => mm2s_tailpntr_enble ,
mm2s_desc_cmplt => mm2s_desc_cmplt ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep ,
-- MM2S Primary DataMover Status
mm2s_err => mm2s_err ,
mm2s_done => mm2s_done ,
mm2s_error => dma_mm2s_error ,
mm2s_interr => mm2s_interr ,
mm2s_slverr => mm2s_slverr ,
mm2s_decerr => mm2s_decerr ,
mm2s_tag => mm2s_tag
);
---------------------------------------------------------------------------
-- Halt / Idle Status Manager
---------------------------------------------------------------------------
I_MM2S_STS_MNGR : entity axi_dma_v7_1.axi_dma_mm2s_sts_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- dma control and sg engine status signals
mm2s_run_stop => mm2s_run_stop ,
mm2s_ftch_idle => mm2s_ftch_idle ,
mm2s_updt_idle => mm2s_updt_idle ,
mm2s_cmnd_idle => mm2s_cmnd_idle ,
mm2s_sts_idle => mm2s_sts_idle ,
-- stop and halt control/status
mm2s_stop => mm2s_stop_i ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
-- system state and control
mm2s_all_idle => mm2s_all_idle ,
mm2s_halted_clr => mm2s_halted_clr ,
mm2s_halted_set => mm2s_halted_set_i ,
mm2s_idle_set => mm2s_idle_set ,
mm2s_idle_clr => mm2s_idle_clr
);
-- MM2S Control Stream Included
GEN_CNTRL_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_INCLUDE_SG = 1 generate
begin
-- Register soft reset to create rising edge pulse to use for shut down.
-- soft_reset from DMACR does not clear until after all reset processes
-- are done. This causes stop to assert too long causing issue with
-- status stream skid buffer.
REG_SFT_RST : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
soft_reset_d1 <= '0';
soft_reset_d2 <= '0';
else
soft_reset_d1 <= soft_reset;
soft_reset_d2 <= soft_reset_d1;
end if;
end if;
end process REG_SFT_RST;
-- Rising edge soft reset pulse
soft_reset_re <= soft_reset_d1 and not soft_reset_d2;
-- Control Stream module stop requires rising edge of soft reset to
-- shut down due to DMACR.SoftReset does not deassert on internal hard reset
-- It clears after therefore do not want to issue another stop to cntrl strm
-- skid buffer.
cntrl_strm_stop <= mm2s_error_i -- Error
or soft_reset_re; -- Soft Reset issued
-- Control stream interface
-- I_MM2S_CNTRL_STREAM : entity axi_dma_v7_1.axi_dma_mm2s_cntrl_strm
-- generic map(
-- C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
-- C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH ,
-- C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH ,
-- C_FAMILY => C_FAMILY
-- )
-- port map(
-- -- Secondary clock / reset
-- m_axi_sg_aclk => m_axi_sg_aclk ,
-- m_axi_sg_aresetn => m_axi_sg_aresetn ,
--
-- -- Primary clock / reset
-- axi_prmry_aclk => axi_prmry_aclk ,
-- p_reset_n => p_reset_n ,
--
-- -- MM2S Error
-- mm2s_stop => cntrl_strm_stop ,
--
-- -- Control Stream input
---- cntrlstrm_fifo_wren => cntrlstrm_fifo_wren ,
-- cntrlstrm_fifo_full => cntrlstrm_fifo_full ,
-- cntrlstrm_fifo_din => cntrlstrm_fifo_din ,
--
-- -- Memory Map to Stream Control Stream Interface
-- m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
-- m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
-- m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
-- m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
-- m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
--
-- );
end generate GEN_CNTRL_STREAM;
-- MM2S Control Stream Excluded
GEN_NO_CNTRL_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_INCLUDE_SG = 0 generate
begin
soft_reset_d1 <= '0';
soft_reset_d2 <= '0';
soft_reset_re <= '0';
cntrl_strm_stop <= '0';
cntrlstrm_fifo_full <= '1';
end generate GEN_NO_CNTRL_STREAM;
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
end generate GEN_MM2S_DMA_CONTROL;
-------------------------------------------------------------------------------
-- Exclude MM2S State Machine and support logic
-------------------------------------------------------------------------------
GEN_NO_MM2S_DMA_CONTROL : if C_INCLUDE_MM2S = 0 generate
begin
m_axis_mm2s_ftch_tready <= '0';
s_axis_mm2s_updtptr_tdata <= (others =>'0');
s_axis_mm2s_updtptr_tvalid <= '0';
s_axis_mm2s_updtptr_tlast <= '0';
s_axis_mm2s_updtsts_tdata <= (others =>'0');
s_axis_mm2s_updtsts_tvalid <= '0';
s_axis_mm2s_updtsts_tlast <= '0';
mm2s_new_curdesc <= (others =>'0');
mm2s_new_curdesc_wren <= '0';
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others =>'0');
m_axis_mm2s_sts_tready <= '0';
mm2s_halted_clr <= '0';
mm2s_halted_set <= '0';
mm2s_idle_set <= '0';
mm2s_idle_clr <= '0';
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
mm2s_stop <= '0';
mm2s_desc_flush <= '0';
mm2s_all_idle <= '1';
mm2s_error <= '0'; -- CR#570587
mm2s_interr_set <= '0';
mm2s_slverr_set <= '0';
mm2s_decerr_set <= '0';
mm2s_smple_done <= '0';
cntrl_strm_stop <= '0';
end generate GEN_NO_MM2S_DMA_CONTROL;
TDEST_FIFO : if (C_ENABLE_MULTI_CHANNEL = 1) generate
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
desc_fetch_done_del <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
desc_fetch_done_del <= desc_fetch_done;
end if;
end if;
end process;
mm2s_desc_info_int <= mm2s_desc_info (19 downto 16) & mm2s_desc_info (12 downto 8) & mm2s_desc_info (4 downto 0);
-- mm2s_strm_tlast_int <= mm2s_strm_tlast and (not info_fifo_empty);
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (p_reset_n = '0') then
rd_en_hold <= '0';
rd_en_hold_int <= '0';
else
if (info_fifo_empty = '1' and mm2s_strm_tlast = '1' and mm2s_strm_tready = '1') then
rd_en_hold <= '1';
rd_en_hold_int <= '0';
elsif (info_fifo_empty = '0') then
rd_en_hold <= mm2s_strm_tlast and mm2s_strm_tready;
rd_en_hold_int <= rd_en_hold;
else
rd_en_hold <= rd_en_hold;
rd_en_hold_int <= rd_en_hold_int;
end if;
end if;
end if;
end process;
-- Following FIFO is used to store the Tuser, Tid and xCache info
I_INFO_FIFO : entity axi_dma_v7_1.axi_dma_afifo_autord
generic map(
C_DWIDTH => 14,
C_DEPTH => 31 ,
C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => 0,
C_USE_AUTORD => 0,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => m_axi_sg_aresetn ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => desc_fetch_done_del ,
AFIFO_Din => mm2s_desc_info_int ,
AFIFO_Rd_clk => m_axis_mm2s_aclk ,
AFIFO_Rd_en => rd_en_hold_int, --mm2s_strm_tlast_int ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => open ,
AFIFO_Dout => mm2s_axis_info ,
AFIFO_Full => info_fifo_full ,
AFIFO_Empty => info_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
end generate TDEST_FIFO;
NO_TDEST_FIFO : if (C_ENABLE_MULTI_CHANNEL = 0) generate
mm2s_axis_info <= (others => '0');
end generate NO_TDEST_FIFO;
end implementation;
| bsd-2-clause | 5042bf9a2237cb24c587790095cdc7fc | 0.404908 | 4.292287 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/procedure/rule_005_test_input.fixed.vhd | 1 | 968 |
architecture RTL of FIFO is
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
constant con1 : integer := 0;
variable var1 : integer := 12;
use ieee.std_logic_1164.all;
begin
end procedure proc_name;
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
constant con1 : integer := 0;
variable var1 : integer := 12;
use ieee.std_logic_1164.all;
begin
end procedure proc_name;
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
constant con1 : integer := 0;
variable var1 : integer := 12;
use ieee.std_logic_1164.all;
begin
end procedure proc_name;
begin
end architecture RTL;
| gpl-3.0 | cca0fa21dfcb539aa55b3607c83876df | 0.645661 | 3.532847 | false | false | false | false |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/cascaded_integrator_comb/cic_compiler_v4_0/hdl/counter.vhd | 1 | 25,043 | `protect begin_protected
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`protect end_protected
| mit | 626062bdd86acec648172bf75ae4ccec | 0.943657 | 1.841262 | false | false | false | false |
NicoLedwith/Dr.AluOpysel | RAT_MCU/StackPointer.vhd | 1 | 885 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity SP is
port ( RST,CLK,LD,INCR,DECR: in std_logic;
DATA_IN : in std_logic_vector (7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0));
end SP;
architecture my_count of SP is
signal s_cnt : std_logic_vector(7 downto 0);
begin
process (CLK, RST, LD, INCR, DECR)
begin
if (RST = '1') then
s_cnt <= "00000000"; -- asynchronous clear
elsif (rising_edge(CLK)) then
if (LD = '1') then
s_cnt <= DATA_IN; -- Load Condition
else
if (INCR = '1') then
s_cnt <= s_cnt + 1; -- increment
else
if (DECR = '1') then
s_cnt <= s_cnt - 1; -- Decrement
else
s_cnt <= S_cnt; -- Hold
end if;
end if;
end if;
end if;
end process;
DATA_OUT <= s_cnt;
end my_count; | mit | 3d3cb6e7e2fe01cf8e2a2214af48cc20 | 0.544633 | 2.940199 | false | false | false | false |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/fir_compiler_v7_1/hdl/fir_compiler_v7_1.vhd | 2 | 19,272 | `protect begin_protected
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| mit | d4c05eb500883d57d8111d63128a3162 | 0.939757 | 1.85379 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/styles/jcl/PIC.fixed.vhd | 1 | 11,696 | ----------------------------------------------------------------------------
---- Create Date: 00:12:45 10/23/2010
---- Design Name: pic
---- Project Name: PIC
---- Description:
---- A Programmable Interrupt Controller which can handle upto 8 ----
---- level triggered interrupts.The operating modes available are ----
---- polling fixed priority modes. ---- ----
----------------------------------------------------------------------------
---- ----
---- This file is a part of the pic project at ----
---- http://www.opencores.org/ ----
---- ----
---- Author(s): ----
---- Vipin Lal, [email protected] ----
---- ----
----------------------------------------------------------------------------
---- ----
---- Copyright (C) 2010 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PIC is
port (
CLK_I : in std_logic; -- Clock.
RST_I : in std_logic; -- Reset
IR : in unsigned(7 downto 0); -- Interrupt requests from peripherals.
DATABUS : inout unsigned(7 downto 0); -- Data bus between processor PIC.
INTR_O : out std_logic; -- Interrupt Request pin of processor.
INTA_I : in std_logic -- Interrupt ack.
);
end entity PIC;
architecture BEHAVIORAL of PIC is
type state_type is (
RESET_S, GET_COMMANDS, JUMP_INT_METHOD, START_POLLING, TX_INT_INFO_POLLING, ACK_ISR_DONE,
ACK_TXINFO_RXD, START_PRIORITY_CHECK, TX_INT_INFO_PRIORITY, ACK_TXINFO_RXD_PRIORITY, ACK_ISR_DONE_PT
);
signal next_s : state_type :=reset_s;
signal int_type : unsigned(1 downto 0):="01";
signal int_index, count_cmd : integer := 0;
type prior_table is array (0 to 7) of unsigned(2 downto 0);
signal pt : prior_table := (others => (others => '0'));
signal int_pt : unsigned(2 downto 0):="000";
signal flag, flag1 : std_logic := '0'; -- These flags are used for timing purposes.
begin
process (CLK_I, RST_I) is
begin
if (RST_I = '1') then
next_s <= reset_s;
elsif (rising_edge(CLK_I)) then
flag <= INTA_I;
case next_s is
when reset_s =>
-- initialze signals to zero.
flag <= '0';
flag1 <= '0';
int_type <= "00";
int_index <= 0;
count_cmd <= 0;
int_pt <= "000";
pt <= (others => (others => '0'));
if (RST_I = '0') then
next_s <= get_commands;
else
next_s <= reset_s;
end if;
DATABUS <= (others => 'Z');
when get_commands => -- Get commands and operating mode from the processor.
if (DATABUS(1 downto 0) = "01") then
int_type <= "01";
next_s <= jump_int_method;
elsif (DATABUS(1 downto 0) = "10" and count_cmd = 0) then
pt(0) <= DATABUS(7 downto 5);
pt(1) <= DATABUS(4 downto 2);
count_cmd <= count_cmd + 1;
next_s <= get_commands;
elsif (DATABUS(1 downto 0) = "10" and count_cmd = 1) then
pt(2) <= DATABUS(7 downto 5);
pt(3) <= DATABUS(4 downto 2);
count_cmd <= count_cmd + 1;
next_s <= get_commands;
elsif (DATABUS(1 downto 0) = "10" and count_cmd = 2) then
pt(4) <= DATABUS(7 downto 5);
pt(5) <= DATABUS(4 downto 2);
count_cmd <= count_cmd + 1;
next_s <= get_commands;
elsif (DATABUS(1 downto 0) = "10" and count_cmd = 3) then
pt(6) <= DATABUS(7 downto 5);
pt(7) <= DATABUS(4 downto 2);
count_cmd <= 0;
int_type <= "10";
next_s <= jump_int_method;
else
next_s <= get_commands;
end if;
when jump_int_method => -- Check which method is used to determine the interrupts.
flag <= '0';
flag1 <= '0';
int_index <= 0;
count_cmd <= 0;
int_pt <= "000";
if (int_type = "01") then
next_s <= start_polling; -- Polling method for checking the interrupts.
elsif (int_type = "10") then
next_s <= start_priority_check; -- Fixed priority scheme.
else
next_s <= reset_s; -- Error if no method is specified.
end if;
DATABUS <= (others => 'Z');
when start_polling => -- Check for interrupts(one by one) using polling method.
if (IR(int_index) = '1') then
INTR_O <= '1';
next_s <= tx_int_info_polling;
else
INTR_O <= '0';
end if;
if (int_index = 7) then
int_index <= 0;
else
int_index <= int_index + 1;
end if;
DATABUS <= (others => 'Z');
when tx_int_info_polling => -- Transmit interrupt information if an interrupt is found.
if (INTA_I = '0') then
INTR_O <= '0';
end if;
if (flag = '0') then
DATABUS <= "01011" & to_unsigned((int_index - 1), 3); -- MSB "01011" is for matching purpose.
flag1 <= '1';
else
flag1 <= '0';
end if;
if (flag1 = '1') then
next_s <= ack_txinfo_rxd;
if (INTA_I = '0') then
DATABUS <= (others => 'Z');
end if;
end if;
when ack_txinfo_rxd => -- ACK send by processor to tell PIC that interrupt info is received correctly.
if (INTA_I <= '0') then
next_s <= ack_ISR_done;
DATABUS <= (others => 'Z');
end if;
when ack_ISR_done => -- Wait for the ISR for the particular interrupt to get over.
if (INTA_I = '0' and DATABUS(7 downto 3) = "10100" and DATABUS(2 downto 0) = to_unsigned(int_index - 1, 3)) then
next_s <= start_polling;
else
next_s <= ack_ISR_done;
end if;
when start_priority_check => -- Fixed priority method for interrupt handling.
-- Interrupts are checked based on their priority.
if (IR(to_integer(pt(0))) = '1') then
int_pt <= pt(0);
INTR_O <= '1';
next_s <= tx_int_info_priority;
elsif (IR(to_integer(pt(1))) = '1') then
int_pt <= pt(1);
INTR_O <= '1';
next_s <= tx_int_info_priority;
elsif (IR(to_integer(pt(2))) = '1') then
int_pt <= pt(2);
INTR_O <= '1';
next_s <= tx_int_info_priority;
elsif (IR(to_integer(pt(3))) = '1') then
int_pt <= pt(3);
INTR_O <= '1';
next_s <= tx_int_info_priority;
elsif (IR(to_integer(pt(4))) = '1') then
int_pt <= pt(4);
INTR_O <= '1';
next_s <= tx_int_info_priority;
elsif (IR(to_integer(pt(5))) = '1') then
int_pt <= pt(5);
INTR_O <= '1';
next_s <= tx_int_info_priority;
elsif (IR(to_integer(pt(6))) = '1') then
int_pt <= pt(6);
INTR_O <= '1';
next_s <= tx_int_info_priority;
elsif (IR(to_integer(pt(7))) = '1') then
int_pt <= pt(7);
INTR_O <= '1';
next_s <= tx_int_info_priority;
else
next_s <= start_priority_check;
end if;
DATABUS <= (others => 'Z');
when tx_int_info_priority => -- Transmit interrupt information if an interrupt is found.
if (INTA_I = '0') then
INTR_O <= '0';
end if;
if (flag = '0') then
DATABUS <= "10011" & int_pt; -- MSB "10011" is for matching purpose.
flag1 <= '1';
else
flag1 <= '0';
end if;
if (flag1 = '1') then
next_s <= ack_txinfo_rxd_priority;
if (INTA_I = '0') then
DATABUS <= (others => 'Z');
end if;
end if;
when ack_txinfo_rxd_priority => -- ACK send by processor to tell PIC that interrupt info is received correctly.
if (INTA_I <= '0') then
next_s <= ack_ISR_done_pt;
DATABUS <= (others => 'Z');
end if;
when ack_ISR_done_pt => -- Wait for the ISR for the particular interrupt to get over.
if (INTA_I = '0' and DATABUS(7 downto 3) = "01100" and DATABUS(2 downto 0) = int_pt) then
next_s <= start_priority_check;
elsif (DATABUS(7 downto 3) /= "01100" or DATABUS(2 downto 0) /= int_pt) then
next_s <= reset_s; -- Error.
else
next_s <= ack_ISR_done_pt;
end if;
when others =>
DATABUS <= (others => 'Z');
end case;
end if;
end process;
end architecture BEHAVIORAL;
| gpl-3.0 | 9b5c8665baf459d3593bfb6452b8ee5d | 0.419289 | 4.328645 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/when/rule_001_test_input.vhd | 1 | 655 |
architecture ARCH of ENTITY is
begin
a <= sig1 when b = '1' else
sig2 when b = '0' else
sig3;
process
begin
d <= sig1 when b = '1' else--This is a comment
sig2 when c = '0' else -- This is a comment
sig3 when d = '1' else
sig4;
end process;
-- Violations below
a <= sig1 when b = '1'
else sig2 when b = '0'
else sig3;
process
begin
d <= sig1 when b = '1'--This is a comment
else sig2 when c = '0' -- This is a comment
else sig3 when d = '1'
else sig4;
end process;
a <= b when (c = '1')else d;
a <= b when (c = '1'else d;
end architecture ARCH;
| gpl-3.0 | bcfad37c0c69a5c01625943100bbcd7c | 0.535878 | 3.119048 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/blk_mem_gen_v8_0/blk_mem_gen_generic_cstr.vhd | 2 | 120,556 | `protect begin_protected
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gih6qm2NPrWy
`protect end_protected
| bsd-2-clause | 393270ce055b44c66f7722e066660376 | 0.953109 | 1.810558 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_bram_ctrl_0_bram_0/daala_zynq_axi_bram_ctrl_0_bram_0/simulation/bmg_stim_gen.vhd | 1 | 16,258 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v8_0 Core - Stimulus Generator For TDP
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For TDP
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_TDP IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_TDP;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_TDP IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLKA : IN STD_LOGIC;
CLKB : IN STD_LOGIC;
RSTA : IN STD_LOGIC;
RSTB : IN STD_LOGIC;
TB_RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
ENA : OUT STD_LOGIC :='0';
WEA : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0');
WEB : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0');
ADDRB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
DINB : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
ENB : OUT STD_LOGIC :='0';
CHECK_DATA: OUT STD_LOGIC_VECTOR(1 DOWNTO 0):=(OTHERS => '0')
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT BIT_ZERO : STD_LOGIC := '0';
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT ADDR_ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A : INTEGER:= DIVROUNDUP(64,64);
CONSTANT DATA_PART_CNT_B : INTEGER:= DIVROUNDUP(64,64);
SIGNAL WRITE_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB_INT : STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
SIGNAL MAX_COUNT : STD_LOGIC_VECTOR(10 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(1024,11);
SIGNAL DO_WRITE_A : STD_LOGIC := '0';
SIGNAL DO_READ_A : STD_LOGIC := '0';
SIGNAL DO_WRITE_B : STD_LOGIC := '0';
SIGNAL DO_READ_B : STD_LOGIC := '0';
SIGNAL COUNT_NO : STD_LOGIC_VECTOR (10 DOWNTO 0):=(OTHERS => '0');
SIGNAL DO_READ_RA : STD_LOGIC := '0';
SIGNAL DO_READ_RB : STD_LOGIC := '0';
SIGNAL DO_READ_REG_A: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL DO_READ_REG_B: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL WEA_VCC: STD_LOGIC_VECTOR(7 DOWNTO 0) :=(OTHERS => '1');
SIGNAL WEA_GND: STD_LOGIC_VECTOR(7 DOWNTO 0) :=(OTHERS => '0');
SIGNAL WEB_VCC: STD_LOGIC_VECTOR(7 DOWNTO 0) :=(OTHERS => '1');
SIGNAL WEB_GND: STD_LOGIC_VECTOR(7 DOWNTO 0) :=(OTHERS => '0');
SIGNAL COUNT : integer := 0;
SIGNAL COUNT_B : integer := 0;
CONSTANT WRITE_CNT_A : integer := 6;
CONSTANT READ_CNT_A : integer := 6;
CONSTANT WRITE_CNT_B : integer := 4;
CONSTANT READ_CNT_B : integer := 4;
signal porta_wr_rd : std_logic:='0';
signal portb_wr_rd : std_logic:='0';
signal porta_wr_rd_complete: std_logic:='0';
signal portb_wr_rd_complete: std_logic:='0';
signal incr_cnt : std_logic :='0';
signal incr_cnt_b : std_logic :='0';
SIGNAL PORTB_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTA_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTB_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R2 :STD_LOGIC :='0';
BEGIN
WRITE_ADDR_INT_A(31 DOWNTO 0) <= WRITE_ADDR_A(31 DOWNTO 0);
READ_ADDR_INT_A(31 DOWNTO 0) <= READ_ADDR_A(31 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE_A='1',WRITE_ADDR_INT_A,READ_ADDR_INT_A) ;
WRITE_ADDR_INT_B(31 DOWNTO 0) <= WRITE_ADDR_B(31 DOWNTO 0);
--To avoid collision during idle period, negating the read_addr of port A
READ_ADDR_INT_B(31 DOWNTO 0) <= IF_THEN_ELSE( (DO_WRITE_B='0' AND DO_READ_B='0'),ADDR_ZERO,READ_ADDR_B(31 DOWNTO 0));
ADDRB <= IF_THEN_ELSE(DO_WRITE_B='1',WRITE_ADDR_INT_B,READ_ADDR_INT_B) ;
DINA <= DINA_INT ;
DINB <= DINB_INT ;
CHECK_DATA(0) <= DO_READ_A;
CHECK_DATA(1) <= DO_READ_B;
RD_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 1024,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_READ_A,
LOAD => BIT_ZERO,
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_A
);
WR_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>1024 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE_A,
LOAD => BIT_ZERO,
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_A
);
RD_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 1024 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_READ_B,
LOAD => BIT_ZERO,
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_B
);
WR_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 1024 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_WRITE_B,
LOAD => BIT_ZERO,
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_B
);
WR_DATA_GEN_INST_A:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>64,
DOUT_WIDTH => 64,
DATA_PART_CNT => 1,
SEED => 2)
PORT MAP (
CLK =>CLKA,
RST => TB_RST,
EN => DO_WRITE_A,
DATA_OUT => DINA_INT
);
WR_DATA_GEN_INST_B:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>64,
DOUT_WIDTH =>64 ,
DATA_PART_CNT =>1,
SEED => 2)
PORT MAP (
CLK =>CLKB,
RST => TB_RST,
EN => DO_WRITE_B,
DATA_OUT => DINB_INT
);
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
ELSIF(PORTB_WR_RD_COMPLETE='1') THEN
LATCH_PORTB_WR_RD_COMPLETE <='1';
ELSIF(PORTA_WR_RD_HAPPENED='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD_L1 <='0';
PORTB_WR_RD_L2 <='0';
ELSE
PORTB_WR_RD_L1 <= LATCH_PORTB_WR_RD_COMPLETE;
PORTB_WR_RD_L2 <= PORTB_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_EN: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD <='1';
ELSE
PORTA_WR_RD <= PORTB_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD_R1 <='0';
PORTA_WR_RD_R2 <='0';
ELSE
PORTA_WR_RD_R1 <=PORTA_WR_RD;
PORTA_WR_RD_R2 <=PORTA_WR_RD_R1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_HAPPENED <= PORTA_WR_RD_R2;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
ELSIF(PORTA_WR_RD_COMPLETE='1') THEN
LATCH_PORTA_WR_RD_COMPLETE <='1';
ELSIF(PORTB_WR_RD_HAPPENED='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD_L1 <='0';
PORTA_WR_RD_L2 <='0';
ELSE
PORTA_WR_RD_L1 <= LATCH_PORTA_WR_RD_COMPLETE;
PORTA_WR_RD_L2 <= PORTA_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTB_EN: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD <='0';
ELSE
PORTB_WR_RD <= PORTA_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD_R1 <='0';
PORTB_WR_RD_R2 <='0';
ELSE
PORTB_WR_RD_R1 <=PORTB_WR_RD;
PORTB_WR_RD_R2 <=PORTB_WR_RD_R1;
END IF;
END IF;
END PROCESS;
---double registered of porta complete on portb clk
PORTB_WR_RD_HAPPENED <= PORTB_WR_RD_R2;
PORTA_WR_RD_COMPLETE <= '1' when count=(WRITE_CNT_A+READ_CNT_A) else '0';
start_counter: process(clka)
begin
if(rising_edge(clka)) then
if(TB_RST='1') then
incr_cnt <= '0';
elsif(porta_wr_rd ='1') then
incr_cnt <='1';
elsif(porta_wr_rd_complete='1') then
incr_cnt <='0';
end if;
end if;
end process;
COUNTER: process(clka)
begin
if(rising_edge(clka)) then
if(TB_RST='1') then
count <= 0;
elsif(incr_cnt='1') then
count<=count+1;
end if;
if(count=(WRITE_CNT_A+READ_CNT_A)) then
count<=0;
end if;
end if;
end process;
DO_WRITE_A<='1' when (count <WRITE_CNT_A and incr_cnt='1') else '0';
DO_READ_A <='1' when (count >WRITE_CNT_A and incr_cnt='1') else '0';
PORTB_WR_RD_COMPLETE <= '1' when count_b=(WRITE_CNT_B+READ_CNT_B) else '0';
startb_counter: process(clkb)
begin
if(rising_edge(clkb)) then
if(TB_RST='1') then
incr_cnt_b <= '0';
elsif(portb_wr_rd ='1') then
incr_cnt_b <='1';
elsif(portb_wr_rd_complete='1') then
incr_cnt_b <='0';
end if;
end if;
end process;
COUNTER_B: process(clkb)
begin
if(rising_edge(clkb)) then
if(TB_RST='1') then
count_b <= 0;
elsif(incr_cnt_b='1') then
count_b<=count_b+1;
end if;
if(count_b=WRITE_CNT_B+READ_CNT_B) then
count_b<=0;
end if;
end if;
end process;
DO_WRITE_B<='1' when (count_b <WRITE_CNT_B and incr_cnt_b='1') else '0';
DO_READ_B <='1' when (count_b >WRITE_CNT_B and incr_cnt_b='1') else '0';
BEGIN_SHIFT_REG_A: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_A(0),
CLK =>CLKA,
RST=>TB_RST,
D =>DO_READ_A
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_A(I),
CLK =>CLKA,
RST=>TB_RST,
D =>DO_READ_REG_A(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG_A;
BEGIN_SHIFT_REG_B: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_B(0),
CLK =>CLKB,
RST=>TB_RST,
D =>DO_READ_B
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_B(I),
CLK =>CLKB,
RST=>TB_RST,
D =>DO_READ_REG_B(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG_B;
REGCEA_PROCESS: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
DO_READ_RA <= '0';
ELSE
DO_READ_RA <= DO_READ_A;
END IF;
END IF;
END PROCESS;
REGCEB_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
DO_READ_RB <= '0';
ELSE
DO_READ_RB <= DO_READ_B;
END IF;
END IF;
END PROCESS;
---REGCEB SHOULD BE SET AT THE CORE OUTPUT REGISTER/EMBEEDED OUTPUT REGISTER
--- WHEN CORE OUTPUT REGISTER IS SET REGCE SHOUD BE SET TO '1' WHEN THE READ DATA IS AVAILABLE AT THE CORE OUTPUT REGISTER
--WHEN CORE OUTPUT REGISTER IS '0' AND OUTPUT_PRIMITIVE_REG ='1', REGCE SHOULD BE SET WHEN THE DATA IS AVAILABLE AT THE PRIMITIVE OUTPUT REGISTER.
-- HERE, TO GENERAILIZE REGCE IS ASSERTED
ENA <= DO_READ_A OR DO_WRITE_A ;
ENB <= DO_READ_B OR DO_WRITE_B ;
WEA <= IF_THEN_ELSE(DO_WRITE_A='1', WEA_VCC,WEA_GND) ;
WEB <= IF_THEN_ELSE(DO_WRITE_B='1', WEB_VCC,WEB_GND) ;
END ARCHITECTURE;
| bsd-2-clause | 104f07f6b6db399f337bd88f24e9483d | 0.575778 | 3.207972 | false | false | false | false |
rjarzmik/mips_processor | IF/Instruction_Provider.vhd | 1 | 7,533 | -------------------------------------------------------------------------------
-- Title : Instructions Provider
-- Project : Source files in two directories, custom library name, VHDL'87
-------------------------------------------------------------------------------
-- File : Instruction_Provider.vhd
-- Author : Robert Jarzmik <[email protected]>
-- Company :
-- Created : 2016-12-03
-- Last update: 2017-01-01
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-12-03 1.0 rj Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cpu_defs.all;
use work.cache_defs.all;
use work.instruction_defs.instr_tag_t;
-------------------------------------------------------------------------------
entity Instruction_Provider is
generic (
ADDR_WIDTH : integer;
DATA_WIDTH : integer
);
port (
clk : in std_logic;
rst : in std_logic;
-- control
--- kill_req = 1 implies that the instructions at i_next_pc and i_next_next_pc
--- should be killed, ie. o_valid sould be '0' for them.
kill_req : in std_logic;
--- stall_req = 1 implies nothing is latched
stall_req : in std_logic;
-- program counters
--- i_next_next_pc must get i_next_pc when o_do_step_pc is set
i_next_pc : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
i_next_pc_instr_tag : in instr_tag_t;
i_next_next_pc : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
i_next_next_pc_instr_tag : in instr_tag_t;
o_pc : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
o_instr_tag : out instr_tag_t;
o_data : out std_logic_vector(DATA_WIDTH - 1 downto 0);
o_valid : out std_logic;
o_do_step_pc : out std_logic;
-- L2 connections
o_creq : out cache_request_t;
i_cresp : in cache_response_t;
-- Debug signal
--- Current fetching address accessed in the instruction cache
o_dbg_fetching : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
o_dbg_fetching_itag : out instr_tag_t
);
end entity Instruction_Provider;
-------------------------------------------------------------------------------
architecture str of Instruction_Provider is
subtype addr_t is std_logic_vector(ADDR_WIDTH - 1 downto 0);
subtype data_t is std_logic_vector(DATA_WIDTH - 1 downto 0);
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal next_pc : addr_t;
signal after_pc : addr_t;
signal next_pc_itag : instr_tag_t;
signal after_pc_itag : instr_tag_t;
--- Cache query management
signal cache_query_addr : addr_t;
signal cache_query_itag : instr_tag_t;
signal cache_latched_pc : addr_t;
signal cache_latched_itag : instr_tag_t;
signal cache_response_data : data_t;
signal cache_response_valid : std_logic; -- true if data for
-- @cache_latched_pc is valid
signal cache_killer : boolean; -- true if the cache response should be killed
--- Cache outputs
signal out_pc : addr_t;
signal out_data : data_t;
signal out_valid : std_logic;
signal out_itag : instr_tag_t;
begin -- architecture str
l1c : entity work.Instruction_Cache(rtl)
generic map (
ADDR_WIDTH => ADDR_WIDTH,
DATA_WIDTH => DATA_WIDTH
)
port map (
clk => clk,
rst => rst,
-- cache query and response
addr => cache_query_addr,
data => cache_response_data,
data_valid => cache_response_valid,
-- signal carry over L2 connections
o_creq => o_creq,
i_cresp => i_cresp
);
--- PC handling
o_do_step_pc <= '1' when (cache_response_valid = '1' and stall_req = '0' and not cache_killer) or kill_req = '1' else '0';
next_pc <= i_next_pc;
after_pc <= i_next_next_pc;
next_pc_itag <= i_next_pc_instr_tag;
after_pc_itag <= i_next_next_pc_instr_tag;
--- Cache inputs
--- Cache is forced on next_pc on stall or kill, and makes only a "predictive"
--- after_pc fetch in the optimal workflow to sustain a cadence of 1 cycle.
cache_query_addr <= next_pc when
cache_response_valid = '0' or stall_req = '1' or cache_killer
else after_pc;
cache_query_itag <= next_pc_itag when
cache_response_valid = '0' or stall_req = '1' or cache_killer
else after_pc_itag;
cache_inputs : process(clk, rst)
begin
if rst = '1' then
cache_killer <= false;
elsif rising_edge(clk) then
--- If killing while cache_response_valid = '1', cache_query = i_next_next_pc.
--- In this case, when the future cache response should be killed.
if kill_req = '1' and cache_response_valid = '1' then
cache_killer <= true;
elsif kill_req = '1' and cache_response_valid = '0' then
--- If killing while cache_response_valid = '0', cache_query = i_next_pc.
--- In this case, when the future cache response should be killed, and
--- the next after it.
cache_killer <= true;
end if;
--- on next cache move forward, disarm the cache killer
if kill_req = '0' and cache_response_valid = '1' then
cache_killer <= false;
end if;
end if;
end process cache_inputs;
cache_outputs : process(clk, rst)
begin
if rst = '1' then
elsif rising_edge(clk) then
cache_latched_pc <= cache_query_addr;
cache_latched_itag <= cache_query_itag;
end if;
end process cache_outputs;
--- Outputs
outputs : process(clk, rst, kill_req)
begin
if rst = '1' then
elsif rising_edge(clk) then
if kill_req = '1' or cache_killer then
out_pc <= cache_latched_pc;
out_itag <= cache_latched_itag;
out_valid <= '0';
if cache_response_valid = '1' then
out_data <= cache_response_data;
else
out_data <= (others => 'X');
end if;
elsif stall_req = '1' then
elsif kill_req = '0' then
out_pc <= cache_latched_pc;
out_itag <= cache_latched_itag;
out_data <= cache_response_data;
out_valid <= cache_response_valid;
end if;
end if;
end process outputs;
--- Cache outputs
o_pc <= out_pc;
o_data <= out_data;
o_valid <= out_valid;
o_instr_tag <= out_itag;
--- Debug output
o_dbg_fetching <= cache_query_addr;
o_dbg_fetching_itag <= cache_query_itag;
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
end architecture str;
-------------------------------------------------------------------------------
| gpl-3.0 | 0e378c3a23e514639851fbfd5acdd8a9 | 0.502058 | 3.843367 | false | false | false | false |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/clk_wiz_1/clk_wiz_1_funcsim.vhdl | 1 | 8,108 | -- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.2 (win64) Build 932637 Wed Jun 11 13:33:10 MDT 2014
-- Date : Mon Dec 01 03:09:56 2014
-- Host : ECE-411-6 running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/coltmw/Documents/GitHub/ecen4024-microphone-array/microphone-array/microphone-array.srcs/sources_1/ip/clk_wiz_1/clk_wiz_1_funcsim.vhdl
-- Design : clk_wiz_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_wiz_1_clk_wiz_1_clk_wiz is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
reset : in STD_LOGIC;
locked : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of clk_wiz_1_clk_wiz_1_clk_wiz : entity is "clk_wiz_1_clk_wiz";
end clk_wiz_1_clk_wiz_1_clk_wiz;
architecture STRUCTURE of clk_wiz_1_clk_wiz_1_clk_wiz is
signal clk_in1_clk_wiz_1 : STD_LOGIC;
signal clk_out1_clk_wiz_1 : STD_LOGIC;
signal clkfbout_buf_clk_wiz_1 : STD_LOGIC;
signal clkfbout_clk_wiz_1 : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_clk_wiz_1,
O => clkfbout_buf_clk_wiz_1
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_clk_wiz_1
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_out1_clk_wiz_1,
O => clk_out1
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 36.375000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 36.375000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 4,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_clk_wiz_1,
CLKFBOUT => clkfbout_clk_wiz_1,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_in1_clk_wiz_1,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_out1_clk_wiz_1,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6) => '0',
DADDR(5) => '0',
DADDR(4) => '0',
DADDR(3) => '0',
DADDR(2) => '0',
DADDR(1) => '0',
DADDR(0) => '0',
DCLK => '0',
DEN => '0',
DI(15) => '0',
DI(14) => '0',
DI(13) => '0',
DI(12) => '0',
DI(11) => '0',
DI(10) => '0',
DI(9) => '0',
DI(8) => '0',
DI(7) => '0',
DI(6) => '0',
DI(5) => '0',
DI(4) => '0',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => '0',
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => locked,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_wiz_1 is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
reset : in STD_LOGIC;
locked : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of clk_wiz_1 : entity is true;
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of clk_wiz_1 : entity is "clk_wiz_1,clk_wiz_v5_1,{component_name=clk_wiz_1,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
end clk_wiz_1;
architecture STRUCTURE of clk_wiz_1 is
begin
inst: entity work.clk_wiz_1_clk_wiz_1_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1,
locked => locked,
reset => reset
);
end STRUCTURE;
| mit | 55c14ec3d385f41dd158f57b9d9c2fa3 | 0.624198 | 3.203477 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_mm2s_dre.vhd | 1 | 88,696 | -------------------------------------------------------------------------------
-- axi_datamover_mm2s_dre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_mm2s_dre.vhd
--
-- Description:
-- This VHDL design implements a 64 bit wide (8 byte lane) function that
-- realigns an arbitrarily aligned input data stream to an arbitrarily aligned
-- output data stream.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_datamover_mm2s_dre.vhd
-- |
-- |-- axi_datamover_dre_mux8_1_x_n.vhd
-- |-- axi_datamover_dre_mux4_1_x_n.vhd
-- |-- axi_datamover_dre_mux2_1_x_n.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
--
-- History:
-- DET 04/19/2011 Initial Version for EDK 13.3
--
-- DET 9/1/2011 Initial
-- ~~~~~~
-- - Per a Lint warning, added a range to the varables lvar_loop_count and
-- lvar_last_strb_hole_position.
-- ^^^^^^
--
-- PVK 9/16/2011
-- ~~~~~~~
-- - Removed else clause in some of the clocked process. This was reported
-- as synthesis warning in modelsim.
-- ^^^^^^^
--
---------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n;
use axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n;
use axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n;
-------------------------------------------------------------------------------
entity axi_datamover_mm2s_dre is
Generic (
C_DWIDTH : Integer := 64;
-- Sets the native data width of the DRE
C_ALIGN_WIDTH : Integer := 3
-- Sets the alignment port widths. The value should be
-- log2(C_DWIDTH)
);
port (
-- Clock and Reset inputs ---------------
dre_clk : In std_logic; --
dre_rst : In std_logic; --
----------------------------------------
-- Alignment Controls ------------------------------------------------
dre_new_align : In std_logic; --
dre_use_autodest : In std_logic; --
dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
dre_flush : In std_logic; --
----------------------------------------------------------------------
-- Input Stream Interface --------------------------------------------
dre_in_tstrb : In std_logic_vector((C_DWIDTH/8)-1 downto 0); --
dre_in_tdata : In std_logic_vector(C_DWIDTH-1 downto 0); --
dre_in_tlast : In std_logic; --
dre_in_tvalid : In std_logic; --
dre_in_tready : Out std_logic; --
----------------------------------------------------------------------
-- Output Stream Interface -------------------------------------------
dre_out_tstrb : Out std_logic_vector((C_DWIDTH/8)-1 downto 0); --
dre_out_tdata : Out std_logic_vector(C_DWIDTH-1 downto 0); --
dre_out_tlast : Out std_logic; --
dre_out_tvalid : Out std_logic; --
dre_out_tready : In std_logic --
----------------------------------------------------------------------
);
end entity axi_datamover_mm2s_dre;
architecture implementation of axi_datamover_mm2s_dre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the MSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_start_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_start : Integer := 0;
begin
bit_index_start := lane_index*lane_width;
return(bit_index_start);
end function get_start_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the LSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_end_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_end : Integer := 0;
begin
bit_index_end := (lane_index*lane_width) + (lane_width-1);
return(bit_index_end);
end function get_end_index;
-- Constants
Constant BYTE_WIDTH : integer := 8; -- bits
Constant DATA_WIDTH_BYTES : integer := C_DWIDTH/BYTE_WIDTH;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant NUM_BYTE_LANES : integer := C_DWIDTH/BYTE_WIDTH;
Constant ALIGN_VECT_WIDTH : integer := C_ALIGN_WIDTH;
Constant NO_STRB_SET_VALUE : integer := 0;
-- Types
type sig_byte_lane_type is array(DATA_WIDTH_BYTES-1 downto 0) of
std_logic_vector(SLICE_WIDTH-1 downto 0);
-- Signals
signal sig_input_data_reg : sig_byte_lane_type;
signal sig_delay_data_reg : sig_byte_lane_type;
signal sig_output_data_reg : sig_byte_lane_type;
signal sig_pass_mux_bus : sig_byte_lane_type;
signal sig_delay_mux_bus : sig_byte_lane_type;
signal sig_final_mux_bus : sig_byte_lane_type;
Signal sig_dre_strb_out_i : std_logic_vector(DATA_WIDTH_BYTES-1 downto 0) := (others => '0');
Signal sig_dre_data_out_i : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
Signal sig_dest_align_i : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_dre_flush_i : std_logic := '0';
Signal sig_pipeline_halt : std_logic := '0';
Signal sig_dre_tvalid_i : std_logic := '0';
Signal sig_input_accept : std_logic := '0';
Signal sig_tlast_enables : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_final_mux_has_tlast : std_logic := '0';
signal sig_tlast_out : std_logic := '0';
Signal sig_tlast_strobes : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
Signal sig_next_auto_dest : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_current_dest_align : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_last_written_strb : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
Signal sig_auto_flush : std_logic := '0';
Signal sig_flush_db1 : std_logic := '0';
Signal sig_flush_db2 : std_logic := '0';
signal sig_flush_db1_complete : std_logic := '0';
signal sig_flush_db2_complete : std_logic := '0';
signal sig_output_xfer : std_logic := '0';
signal sig_advance_pipe_data : std_logic := '0';
Signal sig_flush_reg : std_logic := '0';
Signal sig_input_flush_stall : std_logic := '0';
signal sig_enable_input_rdy : std_logic := '0';
signal sig_input_ready : std_logic := '0';
begin --(architecture implementation)
-- Misc assignments
--dre_in_tready <= sig_input_accept ;
dre_in_tready <= sig_input_ready ;
dre_out_tstrb <= sig_dre_strb_out_i ;
dre_out_tdata <= sig_dre_data_out_i ;
dre_out_tvalid <= sig_dre_tvalid_i ;
dre_out_tlast <= sig_tlast_out ;
sig_pipeline_halt <= sig_dre_tvalid_i and not(dre_out_tready);
sig_output_xfer <= sig_dre_tvalid_i and dre_out_tready;
sig_advance_pipe_data <= (dre_in_tvalid or
sig_dre_flush_i) and
not(sig_pipeline_halt) and
sig_enable_input_rdy;
sig_dre_flush_i <= sig_auto_flush ;
sig_input_accept <= dre_in_tvalid and
sig_input_ready;
sig_flush_db1_complete <= sig_flush_db1 and
not(sig_pipeline_halt);
sig_flush_db2_complete <= sig_flush_db2 and
not(sig_pipeline_halt);
sig_auto_flush <= sig_flush_db1 or sig_flush_db2;
sig_input_flush_stall <= sig_auto_flush; -- commanded flush needed for concatonation
sig_last_written_strb <= sig_dre_strb_out_i;
sig_input_ready <= sig_enable_input_rdy and
not(sig_pipeline_halt) and
not(sig_input_flush_stall) ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_FLOP
--
-- Process Description:
-- Just a flop for generating an input disable while reset
-- is in progress.
--
-------------------------------------------------------------
IMP_RESET_FLOP : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_enable_input_rdy <= '0';
else
sig_enable_input_rdy <= '1';
end if;
end if;
end process IMP_RESET_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_FLUSH_IN
--
-- Process Description:
-- Register for the flush signal
--
-------------------------------------------------------------
REG_FLUSH_IN : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or
sig_flush_db2 = '1') then
sig_flush_reg <= '0';
elsif (sig_input_accept = '1') then
sig_flush_reg <= dre_flush;
else
null; -- hold current state
end if;
end if;
end process REG_FLUSH_IN;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_FINAL_MUX_TLAST_OR
--
-- Process Description:
-- Look at all associated tlast bits in the Final Mux output
-- and detirmine if any are set.
--
--
-------------------------------------------------------------
DO_FINAL_MUX_TLAST_OR : process (sig_final_mux_bus)
Variable lvar_finalmux_or : std_logic_vector(NUM_BYTE_LANES-1 downto 0);
begin
lvar_finalmux_or(0) := sig_final_mux_bus(0)(SLICE_TLAST_INDEX);
for tlast_index in 1 to NUM_BYTE_LANES-1 loop
lvar_finalmux_or(tlast_index) :=
lvar_finalmux_or(tlast_index-1) or
sig_final_mux_bus(tlast_index)(SLICE_TLAST_INDEX);
end loop;
sig_final_mux_has_tlast <= lvar_finalmux_or(NUM_BYTE_LANES-1);
end process DO_FINAL_MUX_TLAST_OR;
------------------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_FLUSH_DB1
--
-- Process Description:
-- Creates the first sequential flag indicating that the DRE needs to flush out
-- current contents before allowing any new inputs. This is
-- triggered by the receipt of the TLAST.
--
-------------------------------------------------------------
GEN_FLUSH_DB1 : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
If (dre_rst = '1' or
sig_flush_db2_complete = '1') Then
sig_flush_db1 <= '0';
Elsif (sig_input_accept = '1') Then
sig_flush_db1 <= dre_flush or dre_in_tlast;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_FLUSH_DB1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_FLUSH_DB2
--
-- Process Description:
-- Creates a second sequential flag indicating that the DRE
-- is flushing out current contents. This is
-- triggered by the assertion of the first sequential flush
-- flag.
--
-------------------------------------------------------------
GEN_FLUSH_DB2 : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
If (dre_rst = '1' or
sig_flush_db2_complete = '1') Then
sig_flush_db2 <= '0';
elsif (sig_pipeline_halt = '0') then
sig_flush_db2 <= sig_flush_db1;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_FLUSH_DB2;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CALC_DEST_STRB_ALIGN
--
-- Process Description:
-- This process calculates the byte lane position of the
-- left-most STRB that is unasserted on the DRE output STRB bus.
-- The resulting value is used as the Destination Alignment
-- Vector for the DRE.
--
-------------------------------------------------------------
CALC_DEST_STRB_ALIGN : process (sig_last_written_strb)
Variable lvar_last_strb_hole_position : Integer range 0 to NUM_BYTE_LANES;
Variable lvar_strb_hole_detected : Boolean;
Variable lvar_first_strb_assert_found : Boolean;
Variable lvar_loop_count : integer range 0 to NUM_BYTE_LANES;
Begin
lvar_loop_count := NUM_BYTE_LANES;
lvar_last_strb_hole_position := 0;
lvar_strb_hole_detected := FALSE;
lvar_first_strb_assert_found := FALSE;
-- Search through the output STRB bus starting with the MSByte
while (lvar_loop_count > 0) loop
If (sig_last_written_strb(lvar_loop_count-1) = '0' and
lvar_first_strb_assert_found = FALSE) Then
lvar_strb_hole_detected := TRUE;
lvar_last_strb_hole_position := lvar_loop_count-1;
Elsif (sig_last_written_strb(lvar_loop_count-1) = '1') Then
lvar_first_strb_assert_found := true;
else
null; -- do nothing
End if;
lvar_loop_count := lvar_loop_count - 1;
End loop;
-- now assign the encoder output value to the bit position of the last Strobe encountered
If (lvar_strb_hole_detected) Then
sig_current_dest_align <= STD_LOGIC_VECTOR(TO_UNSIGNED(lvar_last_strb_hole_position, ALIGN_VECT_WIDTH));
else
sig_current_dest_align <= STD_LOGIC_VECTOR(TO_UNSIGNED(NO_STRB_SET_VALUE, ALIGN_VECT_WIDTH));
End if;
end process CALC_DEST_STRB_ALIGN;
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
-- For Generate
--
-- Label: FORMAT_OUTPUT_DATA_STRB
--
-- For Generate Description:
-- Connect the output Data and Strobe ports to the appropriate
-- bits in the sig_output_data_reg.
--
------------------------------------------------------------
FORMAT_OUTPUT_DATA_STRB : for byte_lane_index in 0 to NUM_BYTE_LANES-1 generate
begin
sig_dre_data_out_i(get_end_index(byte_lane_index, BYTE_WIDTH) downto
get_start_index(byte_lane_index, BYTE_WIDTH)) <=
sig_output_data_reg(byte_lane_index)(BYTE_WIDTH-1 downto 0);
sig_dre_strb_out_i(byte_lane_index) <=
sig_output_data_reg(byte_lane_index)(SLICE_WIDTH-2);
end generate FORMAT_OUTPUT_DATA_STRB;
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
---------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_INPUT_REG
--
-- For Generate Description:
--
-- Implements a programble number of input register slices.
--
--
------------------------------------------------------------
GEN_INPUT_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_INPUTREG_SLICE
--
-- Process Description:
-- Implement a single register slice for the Input Register.
--
-------------------------------------------------------------
DO_INPUTREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or
sig_flush_db1_complete = '1' or -- clear on reset or if
(dre_in_tvalid = '1' and
sig_pipeline_halt = '0' and -- the pipe is being advanced and
dre_in_tstrb(slice_index) = '0')) then -- no new valid data id being loaded
sig_input_data_reg(slice_index) <= ZEROED_SLICE;
elsif (dre_in_tstrb(slice_index) = '1' and
sig_input_accept = '1') then
sig_input_data_reg(slice_index) <= sig_tlast_enables(slice_index) &
dre_in_tstrb(slice_index) &
dre_in_tdata((slice_index*8)+7 downto slice_index*8);
else
null; -- don't change state
end if;
end if;
end process DO_INPUTREG_SLICE;
end generate GEN_INPUT_REG;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_DELAY_REG
--
-- For Generate Description:
--
-- Implements a programble number of output register slices
--
--
------------------------------------------------------------
GEN_DELAY_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DELAYREG_SLICE
--
-- Process Description:
-- Implement a single register slice
--
-------------------------------------------------------------
DO_DELAYREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or -- clear on reset or if
(sig_advance_pipe_data = '1' and -- the pipe is being advanced and
sig_delay_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '0')) then -- no new valid data id being loaded
sig_delay_data_reg(slice_index) <= ZEROED_SLICE;
elsif (sig_delay_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '1' and
sig_advance_pipe_data = '1') then
sig_delay_data_reg(slice_index) <= sig_delay_mux_bus(slice_index);
else
null; -- don't change state
end if;
end if;
end process DO_DELAYREG_SLICE;
end generate GEN_DELAY_REG;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_OUTPUT_REG
--
-- For Generate Description:
--
-- Implements a programble number of output register slices
--
--
------------------------------------------------------------
GEN_OUTPUT_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_OUTREG_SLICE
--
-- Process Description:
-- Implement a single register slice
--
-------------------------------------------------------------
DO_OUTREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or -- clear on reset or if
(sig_output_xfer = '1' and -- the output is being transfered and
sig_final_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '0')) then -- no new valid data id being loaded
sig_output_data_reg(slice_index) <= ZEROED_SLICE;
elsif (sig_final_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '1' and
sig_advance_pipe_data = '1') then
sig_output_data_reg(slice_index) <= sig_final_mux_bus(slice_index);
else
null; -- don't change state
end if;
end if;
end process DO_OUTREG_SLICE;
end generate GEN_OUTPUT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_TVALID
--
-- Process Description:
-- This sync process generates the Write request for the
-- destination interface.
--
-------------------------------------------------------------
GEN_TVALID : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_dre_tvalid_i <= '0';
elsif (sig_advance_pipe_data = '1') then
sig_dre_tvalid_i <= sig_final_mux_bus(NUM_BYTE_LANES-1)(SLICE_STROBE_INDEX) or -- MS Strobe is set or
sig_final_mux_has_tlast; -- the Last data beat of a packet
Elsif (dre_out_tready = '1' and -- a completed write but no
sig_dre_tvalid_i = '1') Then -- new input data so clear
-- until more input data shows up
sig_dre_tvalid_i <= '0';
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_TVALID;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_TLAST_OUT
--
-- Process Description:
-- This sync process generates the TLAST output for the
-- destination interface.
--
-------------------------------------------------------------
GEN_TLAST_OUT : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_tlast_out <= '0';
elsif (sig_advance_pipe_data = '1') then
sig_tlast_out <= sig_final_mux_has_tlast;
Elsif (dre_out_tready = '1' and -- a completed transfer
sig_dre_tvalid_i = '1') Then -- so clear tlast
sig_tlast_out <= '0';
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_TLAST_OUT;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_64
--
-- If Generate Description:
-- Support Logic and Mux Farm for 64-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_64 : if (C_DWIDTH = 64) generate
signal sig_cntl_state_64 : std_logic_vector(5 downto 0) := (others => '0');
Signal s_case_i_64 : Integer range 0 to 7 := 0;
Signal sig_shift_case_i : std_logic_vector(2 downto 0) := (others => '0');
Signal sig_shift_case_reg : std_logic_vector(2 downto 0) := (others => '0');
Signal sig_final_mux_sel : std_logic_vector(7 downto 0) := (others => '0');
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_8
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_8 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(7 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "00000000";
elsif (sig_tlast_strobes(7) = '1') then
sig_tlast_enables <= "10000000";
elsif (sig_tlast_strobes(6) = '1') then
sig_tlast_enables <= "01000000";
elsif (sig_tlast_strobes(5) = '1') then
sig_tlast_enables <= "00100000";
elsif (sig_tlast_strobes(4) = '1') then
sig_tlast_enables <= "00010000";
elsif (sig_tlast_strobes(3) = '1') then
sig_tlast_enables <= "00001000";
elsif (sig_tlast_strobes(2) = '1') then
sig_tlast_enables <= "00000100";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "00000010";
else
sig_tlast_enables <= "00000001";
end if;
end process FIND_MS_STRB_SET_8;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to sld_logic_vector
--sig_shift_case_i <= CONV_STD_LOGIC_VECTOR(s_case_i_64, 3);
sig_shift_case_i <= STD_LOGIC_VECTOR(TO_UNSIGNED(s_case_i_64, 3));
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_64
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_64 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_64)
-- signal sig_cntl_state_64 : std_logic_vector(5 downto 0);
-- Signal s_case_i_64 : Integer range 0 to 7;
begin
sig_cntl_state_64 <= dre_src_align & sig_dest_align_i;
case sig_cntl_state_64 is
when "000000" =>
s_case_i_64 <= 0;
when "000001" =>
s_case_i_64 <= 7;
when "000010" =>
s_case_i_64 <= 6;
when "000011" =>
s_case_i_64 <= 5;
when "000100" =>
s_case_i_64 <= 4;
when "000101" =>
s_case_i_64 <= 3;
when "000110" =>
s_case_i_64 <= 2;
when "000111" =>
s_case_i_64 <= 1;
when "001000" =>
s_case_i_64 <= 1;
when "001001" =>
s_case_i_64 <= 0;
when "001010" =>
s_case_i_64 <= 7;
when "001011" =>
s_case_i_64 <= 6;
when "001100" =>
s_case_i_64 <= 5;
when "001101" =>
s_case_i_64 <= 4;
when "001110" =>
s_case_i_64 <= 3;
when "001111" =>
s_case_i_64 <= 2;
when "010000" =>
s_case_i_64 <= 2;
when "010001" =>
s_case_i_64 <= 1;
when "010010" =>
s_case_i_64 <= 0;
when "010011" =>
s_case_i_64 <= 7;
when "010100" =>
s_case_i_64 <= 6;
when "010101" =>
s_case_i_64 <= 5;
when "010110" =>
s_case_i_64 <= 4;
when "010111" =>
s_case_i_64 <= 3;
when "011000" =>
s_case_i_64 <= 3;
when "011001" =>
s_case_i_64 <= 2;
when "011010" =>
s_case_i_64 <= 1;
when "011011" =>
s_case_i_64 <= 0;
when "011100" =>
s_case_i_64 <= 7;
when "011101" =>
s_case_i_64 <= 6;
when "011110" =>
s_case_i_64 <= 5;
when "011111" =>
s_case_i_64 <= 4;
when "100000" =>
s_case_i_64 <= 4;
when "100001" =>
s_case_i_64 <= 3;
when "100010" =>
s_case_i_64 <= 2;
when "100011" =>
s_case_i_64 <= 1;
when "100100" =>
s_case_i_64 <= 0;
when "100101" =>
s_case_i_64 <= 7;
when "100110" =>
s_case_i_64 <= 6;
when "100111" =>
s_case_i_64 <= 5;
when "101000" =>
s_case_i_64 <= 5;
when "101001" =>
s_case_i_64 <= 4;
when "101010" =>
s_case_i_64 <= 3;
when "101011" =>
s_case_i_64 <= 2;
when "101100" =>
s_case_i_64 <= 1;
when "101101" =>
s_case_i_64 <= 0;
when "101110" =>
s_case_i_64 <= 7;
when "101111" =>
s_case_i_64 <= 6;
when "110000" =>
s_case_i_64 <= 6;
when "110001" =>
s_case_i_64 <= 5;
when "110010" =>
s_case_i_64 <= 4;
when "110011" =>
s_case_i_64 <= 3;
when "110100" =>
s_case_i_64 <= 2;
when "110101" =>
s_case_i_64 <= 1;
when "110110" =>
s_case_i_64 <= 0;
when "110111" =>
s_case_i_64 <= 7;
when "111000" =>
s_case_i_64 <= 7;
when "111001" =>
s_case_i_64 <= 6;
when "111010" =>
s_case_i_64 <= 5;
when "111011" =>
s_case_i_64 <= 4;
when "111100" =>
s_case_i_64 <= 3;
when "111101" =>
s_case_i_64 <= 2;
when "111110" =>
s_case_i_64 <= 1;
when "111111" =>
s_case_i_64 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_64;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= (others => '0');
elsif (dre_new_align = '1' and
sig_input_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0) ,
I0 => sig_input_data_reg(1) ,
I1 => sig_input_data_reg(0) ,
Y => sig_pass_mux_bus(1)
);
-- Pass Mux Byte 2 (4-1 x8 Mux)
I_MUX4_1_PASS_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(2) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
Y => sig_pass_mux_bus(2)
);
-- Pass Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_PASS_B3 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(3) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
Y => sig_pass_mux_bus(3)
);
-- Pass Mux Byte 4 (8-1 x8 Mux)
I_MUX8_1_PASS_B4 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(4) ,
I1 => ZEROED_SLICE ,
I2 => ZEROED_SLICE ,
I3 => ZEROED_SLICE ,
I4 => sig_input_data_reg(0) ,
I5 => sig_input_data_reg(1) ,
I6 => sig_input_data_reg(2) ,
I7 => sig_input_data_reg(3) ,
Y => sig_pass_mux_bus(4)
);
-- Pass Mux Byte 5 (8-1 x8 Mux)
I_MUX8_1_PASS_B5 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(5) ,
I1 => ZEROED_SLICE ,
I2 => ZEROED_SLICE ,
I3 => sig_input_data_reg(0) ,
I4 => sig_input_data_reg(1) ,
I5 => sig_input_data_reg(2) ,
I6 => sig_input_data_reg(3) ,
I7 => sig_input_data_reg(4) ,
Y => sig_pass_mux_bus(5)
);
-- Pass Mux Byte 6 (8-1 x8 Mux)
I_MUX8_1_PASS_B6 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(6) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
I4 => sig_input_data_reg(2) ,
I5 => sig_input_data_reg(3) ,
I6 => sig_input_data_reg(4) ,
I7 => sig_input_data_reg(5) ,
Y => sig_pass_mux_bus(6)
);
-- Pass Mux Byte 7 (8-1 x8 Mux)
I_MUX8_1_PASS_B7 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(7) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
I4 => sig_input_data_reg(3) ,
I5 => sig_input_data_reg(4) ,
I6 => sig_input_data_reg(5) ,
I7 => sig_input_data_reg(6) ,
Y => sig_pass_mux_bus(7)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Byte 0 (8-1 x8 Mux)
I_MUX8_1_DLY_B0 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0) ,
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(1) ,
I2 => sig_input_data_reg(2) ,
I3 => sig_input_data_reg(3) ,
I4 => sig_input_data_reg(4) ,
I5 => sig_input_data_reg(5) ,
I6 => sig_input_data_reg(6) ,
I7 => sig_input_data_reg(7) ,
Y => sig_delay_mux_bus(0)
);
-- Delay Mux Byte 1 (8-1 x8 Mux)
I_MUX8_1_DLY_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(2) ,
I2 => sig_input_data_reg(3) ,
I3 => sig_input_data_reg(4) ,
I4 => sig_input_data_reg(5) ,
I5 => sig_input_data_reg(6) ,
I6 => sig_input_data_reg(7) ,
I7 => ZEROED_SLICE ,
Y => sig_delay_mux_bus(1)
);
-- Delay Mux Byte 2 (8-1 x8 Mux)
I_MUX8_1_DLY_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(3) ,
I2 => sig_input_data_reg(4) ,
I3 => sig_input_data_reg(5) ,
I4 => sig_input_data_reg(6) ,
I5 => sig_input_data_reg(7) ,
I6 => ZEROED_SLICE ,
I7 => ZEROED_SLICE ,
Y => sig_delay_mux_bus(2)
);
-- Delay Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_DLY_B3 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(7) ,
I1 => sig_input_data_reg(4) ,
I2 => sig_input_data_reg(5) ,
I3 => sig_input_data_reg(6) ,
Y => sig_delay_mux_bus(3)
);
-- Delay Mux Byte 4 (4-1 x8 Mux)
I_MUX4_1_DLY_B4 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(5) ,
I2 => sig_input_data_reg(6) ,
I3 => sig_input_data_reg(7) ,
Y => sig_delay_mux_bus(4)
);
-- Delay Mux Byte 5 (2-1 x8 Mux)
I_MUX2_1_DLY_B5 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH -- : Integer := 8
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(7),
I1 => sig_input_data_reg(6),
Y => sig_delay_mux_bus(5)
);
-- Delay Mux Byte 6 (Wire)
sig_delay_mux_bus(6) <= sig_input_data_reg(7);
-- Delay Mux Byte 7 (Zeroed)
sig_delay_mux_bus(7) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Byte 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(0) <= '0';
when "001" =>
sig_final_mux_sel(0) <= '1';
when "010" =>
sig_final_mux_sel(0) <= '1';
when "011" =>
sig_final_mux_sel(0) <= '1';
when "100" =>
sig_final_mux_sel(0) <= '1';
when "101" =>
sig_final_mux_sel(0) <= '1';
when "110" =>
sig_final_mux_sel(0) <= '1';
when "111" =>
sig_final_mux_sel(0) <= '1';
when others =>
sig_final_mux_sel(0) <= '0';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_input_data_reg(0),
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Byte 1 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B1_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 1 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B1_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(1) <= '0';
when "001" =>
sig_final_mux_sel(1) <= '1';
when "010" =>
sig_final_mux_sel(1) <= '1';
when "011" =>
sig_final_mux_sel(1) <= '1';
when "100" =>
sig_final_mux_sel(1) <= '1';
when "101" =>
sig_final_mux_sel(1) <= '1';
when "110" =>
sig_final_mux_sel(1) <= '1';
when "111" =>
sig_final_mux_sel(1) <= '0';
when others =>
sig_final_mux_sel(1) <= '0';
end case;
end process MUX2_1_FINAL_B1_CNTL;
I_MUX2_1_FINAL_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(1) ,
I0 => sig_pass_mux_bus(1) ,
I1 => sig_delay_data_reg(1),
Y => sig_final_mux_bus(1)
);
-- Final Mux Byte 2 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B2_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 2 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B2_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(2) <= '0';
when "001" =>
sig_final_mux_sel(2) <= '1';
when "010" =>
sig_final_mux_sel(2) <= '1';
when "011" =>
sig_final_mux_sel(2) <= '1';
when "100" =>
sig_final_mux_sel(2) <= '1';
when "101" =>
sig_final_mux_sel(2) <= '1';
when "110" =>
sig_final_mux_sel(2) <= '0';
when "111" =>
sig_final_mux_sel(2) <= '0';
when others =>
sig_final_mux_sel(2) <= '0';
end case;
end process MUX2_1_FINAL_B2_CNTL;
I_MUX2_1_FINAL_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(2) ,
I0 => sig_pass_mux_bus(2) ,
I1 => sig_delay_data_reg(2),
Y => sig_final_mux_bus(2)
);
-- Final Mux Byte 3 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B3_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 3 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B3_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(3) <= '0';
when "001" =>
sig_final_mux_sel(3) <= '1';
when "010" =>
sig_final_mux_sel(3) <= '1';
when "011" =>
sig_final_mux_sel(3) <= '1';
when "100" =>
sig_final_mux_sel(3) <= '1';
when "101" =>
sig_final_mux_sel(3) <= '0';
when "110" =>
sig_final_mux_sel(3) <= '0';
when "111" =>
sig_final_mux_sel(3) <= '0';
when others =>
sig_final_mux_sel(3) <= '0';
end case;
end process MUX2_1_FINAL_B3_CNTL;
I_MUX2_1_FINAL_B3 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(3) ,
I0 => sig_pass_mux_bus(3) ,
I1 => sig_delay_data_reg(3),
Y => sig_final_mux_bus(3)
);
-- Final Mux Byte 4 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B4_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 4 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B4_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(4) <= '0';
when "001" =>
sig_final_mux_sel(4) <= '1';
when "010" =>
sig_final_mux_sel(4) <= '1';
when "011" =>
sig_final_mux_sel(4) <= '1';
when "100" =>
sig_final_mux_sel(4) <= '0';
when "101" =>
sig_final_mux_sel(4) <= '0';
when "110" =>
sig_final_mux_sel(4) <= '0';
when "111" =>
sig_final_mux_sel(4) <= '0';
when others =>
sig_final_mux_sel(4) <= '0';
end case;
end process MUX2_1_FINAL_B4_CNTL;
I_MUX2_1_FINAL_B4 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(4) ,
I0 => sig_pass_mux_bus(4) ,
I1 => sig_delay_data_reg(4),
Y => sig_final_mux_bus(4)
);
-- Final Mux Byte 5 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B5_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 5 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B5_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(5) <= '0';
when "001" =>
sig_final_mux_sel(5) <= '1';
when "010" =>
sig_final_mux_sel(5) <= '1';
when "011" =>
sig_final_mux_sel(5) <= '0';
when "100" =>
sig_final_mux_sel(5) <= '0';
when "101" =>
sig_final_mux_sel(5) <= '0';
when "110" =>
sig_final_mux_sel(5) <= '0';
when "111" =>
sig_final_mux_sel(5) <= '0';
when others =>
sig_final_mux_sel(5) <= '0';
end case;
end process MUX2_1_FINAL_B5_CNTL;
I_MUX2_1_FINAL_B5 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(5) ,
I0 => sig_pass_mux_bus(5) ,
I1 => sig_delay_data_reg(5),
Y => sig_final_mux_bus(5)
);
-- Final Mux Byte 6 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B6_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 6 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B6_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(6) <= '0';
when "001" =>
sig_final_mux_sel(6) <= '1';
when "010" =>
sig_final_mux_sel(6) <= '0';
when "011" =>
sig_final_mux_sel(6) <= '0';
when "100" =>
sig_final_mux_sel(6) <= '0';
when "101" =>
sig_final_mux_sel(6) <= '0';
when "110" =>
sig_final_mux_sel(6) <= '0';
when "111" =>
sig_final_mux_sel(6) <= '0';
when others =>
sig_final_mux_sel(6) <= '0';
end case;
end process MUX2_1_FINAL_B6_CNTL;
I_MUX2_1_FINAL_B6 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(6) ,
I0 => sig_pass_mux_bus(6) ,
I1 => sig_delay_data_reg(6),
Y => sig_final_mux_bus(6)
);
-- Final Mux Byte 7 (wire)
sig_final_mux_sel(7) <= '0';
sig_final_mux_bus(7) <= sig_pass_mux_bus(7);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_64;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_32
--
-- If Generate Description:
-- Support Logic and Mux Farm for 32-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_32 : if (C_DWIDTH = 32) generate
signal sig_cntl_state_32 : std_logic_vector(3 downto 0);
Signal s_case_i_32 : Integer range 0 to 3;
Signal sig_shift_case_i : std_logic_vector(1 downto 0);
Signal sig_shift_case_reg : std_logic_vector(1 downto 0);
Signal sig_final_mux_sel : std_logic_vector(3 downto 0);
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_4
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_4 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(3 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "0000";
elsif (sig_tlast_strobes(3) = '1') then
sig_tlast_enables <= "1000";
elsif (sig_tlast_strobes(2) = '1') then
sig_tlast_enables <= "0100";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "0010";
else
sig_tlast_enables <= "0001";
end if;
end process FIND_MS_STRB_SET_4;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to sld_logic_vector
--sig_shift_case_i <= CONV_STD_LOGIC_VECTOR(s_case_i_32, 2);
sig_shift_case_i <= STD_LOGIC_VECTOR(TO_UNSIGNED(s_case_i_32, 2));
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_32
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_32 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_32)
begin
sig_cntl_state_32 <= dre_src_align(1 downto 0) & sig_dest_align_i(1 downto 0);
case sig_cntl_state_32 is
when "0000" =>
s_case_i_32 <= 0;
when "0001" =>
s_case_i_32 <= 3;
when "0010" =>
s_case_i_32 <= 2;
when "0011" =>
s_case_i_32 <= 1;
when "0100" =>
s_case_i_32 <= 1;
when "0101" =>
s_case_i_32 <= 0;
when "0110" =>
s_case_i_32 <= 3;
when "0111" =>
s_case_i_32 <= 2;
when "1000" =>
s_case_i_32 <= 2;
when "1001" =>
s_case_i_32 <= 1;
when "1010" =>
s_case_i_32 <= 0;
when "1011" =>
s_case_i_32 <= 3;
when "1100" =>
s_case_i_32 <= 3;
when "1101" =>
s_case_i_32 <= 2;
when "1110" =>
s_case_i_32 <= 1;
when "1111" =>
s_case_i_32 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_32;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= (others => '0');
elsif (dre_new_align = '1' and
sig_input_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(1),
I1 => sig_input_data_reg(0),
Y => sig_pass_mux_bus(1)
);
-- Pass Mux Byte 2 (4-1 x8 Mux)
I_MUX4_1_PASS_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(2) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
Y => sig_pass_mux_bus(2)
);
-- Pass Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_PASS_B3 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(3) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
Y => sig_pass_mux_bus(3)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Byte 0 (4-1 x8 Mux)
I_MUX4_1_DLY_B4 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(1) ,
I2 => sig_input_data_reg(2) ,
I3 => sig_input_data_reg(3) ,
Y => sig_delay_mux_bus(0)
);
-- Delay Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_DLY_B5 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(3),
I1 => sig_input_data_reg(2),
Y => sig_delay_mux_bus(1)
);
-- Delay Mux Byte 2 (Wire)
sig_delay_mux_bus(2) <= sig_input_data_reg(3);
-- Delay Mux Byte 3 (Zeroed)
sig_delay_mux_bus(3) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Slice 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(0) <= '0';
when "01" =>
sig_final_mux_sel(0) <= '1';
when "10" =>
sig_final_mux_sel(0) <= '1';
when "11" =>
sig_final_mux_sel(0) <= '1';
when others =>
sig_final_mux_sel(0) <= '0';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_pass_mux_bus(0) ,
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Slice 1 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B1_CNTL
--
-- Process Description:
-- This process generates the Select Control for slice 1 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B1_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(1) <= '0';
when "01" =>
sig_final_mux_sel(1) <= '1';
when "10" =>
sig_final_mux_sel(1) <= '1';
when "11" =>
sig_final_mux_sel(1) <= '0';
when others =>
sig_final_mux_sel(1) <= '0';
end case;
end process MUX2_1_FINAL_B1_CNTL;
I_MUX2_1_FINAL_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(1) ,
I0 => sig_pass_mux_bus(1) ,
I1 => sig_delay_data_reg(1),
Y => sig_final_mux_bus(1)
);
-- Final Mux Slice 2 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B2_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 2 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B2_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(2) <= '0';
when "01" =>
sig_final_mux_sel(2) <= '1';
when "10" =>
sig_final_mux_sel(2) <= '0';
when "11" =>
sig_final_mux_sel(2) <= '0';
when others =>
sig_final_mux_sel(2) <= '0';
end case;
end process MUX2_1_FINAL_B2_CNTL;
I_MUX2_1_FINAL_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(2) ,
I0 => sig_pass_mux_bus(2) ,
I1 => sig_delay_data_reg(2),
Y => sig_final_mux_bus(2)
);
-- Final Mux Slice 3 (wire)
sig_final_mux_sel(3) <= '0';
sig_final_mux_bus(3) <= sig_pass_mux_bus(3);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_32;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_16
--
-- If Generate Description:
-- Support Logic and Mux Farm for 16-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_16 : if (C_DWIDTH = 16) generate
signal sig_cntl_state_16 : std_logic_vector(1 downto 0);
Signal s_case_i_16 : Integer range 0 to 1;
Signal sig_shift_case_i : std_logic;
Signal sig_shift_case_reg : std_logic;
Signal sig_final_mux_sel : std_logic_vector(1 downto 0);
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_2
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_2 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(1 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "00";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "10";
else
sig_tlast_enables <= "01";
end if;
end process FIND_MS_STRB_SET_2;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to std_logic
sig_shift_case_i <= '1'
When s_case_i_16 = 1
Else '0';
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_16
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_16 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_16)
begin
sig_cntl_state_16 <= dre_src_align(0) & sig_dest_align_i(0);
case sig_cntl_state_16 is
when "00" =>
s_case_i_16 <= 0;
when "01" =>
s_case_i_16 <= 1;
when "10" =>
s_case_i_16 <= 1;
when "11" =>
s_case_i_16 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_16;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= '0';
elsif (dre_new_align = '1' and
sig_input_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg,
I0 => sig_input_data_reg(1),
I1 => sig_input_data_reg(0),
Y => sig_pass_mux_bus(1)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Slice 0 (Wire)
sig_delay_mux_bus(0) <= sig_input_data_reg(1);
-- Delay Mux Slice 1 (Zeroed)
sig_delay_mux_bus(1) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Slice 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when '0' =>
sig_final_mux_sel(0) <= '0';
when others =>
sig_final_mux_sel(0) <= '1';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_pass_mux_bus(0) ,
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Slice 1 (wire)
sig_final_mux_sel(1) <= '0';
sig_final_mux_bus(1) <= sig_pass_mux_bus(1);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_16;
end implementation;
| bsd-2-clause | 2303e225d21e726201cef250f7f88755 | 0.368844 | 4.596839 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/case/rule_017_test_input.fixed_upper.vhd | 1 | 589 |
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= b;
b <= c;
c <= d;
END case;
end process PROC_1;
PROC_2 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1=>
a <= b;
b <= c;
c <= d;
END case;
end process PROC_2;
PROC_3 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1=>
a <= b;
b <= c;
c <= d;
END case;
end process PROC_3;
end architecture ARCH;
| gpl-3.0 | f96804a75be89baa242f18e28e3057bc | 0.4618 | 3.308989 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/if_statement/rule_026_test_input.fixed_upper.vhd | 1 | 566 |
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
ELSIF c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
ELSIF x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' then
b <= '0';
ELSIF c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
ELSIF x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
end process;
end architecture RTL;
| gpl-3.0 | c1691c6c173ae69fc29db52cf8076a67 | 0.379859 | 3.19774 | false | false | false | false |
Yarr/Yarr-fw | ip-cores/spartan6/rx_bridge_fifo.vhd | 2 | 10,732 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file rx_bridge_fifo.vhd when simulating
-- the core, rx_bridge_fifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY rx_bridge_fifo IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC
);
END rx_bridge_fifo;
ARCHITECTURE rx_bridge_fifo_a OF rx_bridge_fifo IS
-- synthesis translate_off
COMPONENT wrapped_rx_bridge_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_rx_bridge_fifo USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 11,
c_default_value => "BlankString",
c_din_width => 32,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 32,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "2kx18",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 3,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 2047,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 2046,
c_prog_full_type => 3,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 11,
c_rd_depth => 2048,
c_rd_freq => 1,
c_rd_pntr_width => 11,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 11,
c_wr_depth => 2048,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 11,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_rx_bridge_fifo
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => prog_empty_thresh,
prog_full_thresh => prog_full_thresh,
dout => dout,
full => full,
empty => empty,
prog_full => prog_full,
prog_empty => prog_empty
);
-- synthesis translate_on
END rx_bridge_fifo_a;
| gpl-3.0 | 5426e16f8e123d0fd25dff1a81c2affc | 0.542862 | 3.324659 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/ramfifo/dmem.vhd | 2 | 12,333 | `protect begin_protected
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7392)
`protect data_block
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`protect end_protected
| bsd-2-clause | d96737ba840e13ed37b1ad25a8a4905c | 0.932052 | 1.883764 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_dma_v7_1/hdl/src/vhdl/axi_dma_reg_module.vhd | 1 | 86,248 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_reg_module.vhd
-- Description: This entity is AXI DMA Register Module Top Level
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_reg_module is
generic(
C_INCLUDE_MM2S : integer range 0 to 1 := 1 ;
C_INCLUDE_S2MM : integer range 0 to 1 := 1 ;
C_INCLUDE_SG : integer range 0 to 1 := 1 ;
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
C_AXI_LITE_IS_ASYNC : integer range 0 to 1 := 0 ;
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 32 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 32 := 32 ;
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ;
C_MICRO_DMA : integer range 0 to 1 := 0 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
);
port (
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
m_axi_sg_hrdresetn : in std_logic ; --
--
s_axi_lite_aclk : in std_logic ; --
axi_lite_reset_n : in std_logic ; --
--
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic ; --
s_axi_lite_awready : out std_logic ; --
s_axi_lite_awaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic ; --
s_axi_lite_arready : out std_logic ; --
s_axi_lite_araddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
--
-- MM2S Signals --
mm2s_stop : in std_logic ; --
mm2s_halted_clr : in std_logic ; --
mm2s_halted_set : in std_logic ; --
mm2s_idle_set : in std_logic ; --
mm2s_idle_clr : in std_logic ; --
mm2s_dma_interr_set : in std_logic ; --
mm2s_dma_slverr_set : in std_logic ; --
mm2s_dma_decerr_set : in std_logic ; --
mm2s_ioc_irq_set : in std_logic ; --
mm2s_dly_irq_set : in std_logic ; --
mm2s_irqdelay_status : in std_logic_vector(7 downto 0) ; --
mm2s_irqthresh_status : in std_logic_vector(7 downto 0) ; --
mm2s_ftch_interr_set : in std_logic ; --
mm2s_ftch_slverr_set : in std_logic ; --
mm2s_ftch_decerr_set : in std_logic ; --
mm2s_updt_interr_set : in std_logic ; --
mm2s_updt_slverr_set : in std_logic ; --
mm2s_updt_decerr_set : in std_logic ; --
mm2s_new_curdesc_wren : in std_logic ; --
mm2s_new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_dlyirq_dsble : out std_logic ; -- CR605888 --
mm2s_irqthresh_rstdsbl : out std_logic ; -- CR572013 --
mm2s_irqthresh_wren : out std_logic ; --
mm2s_irqdelay_wren : out std_logic ; --
mm2s_tailpntr_updated : out std_logic ; --
mm2s_dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
mm2s_dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
mm2s_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_taildesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_sa : out std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
mm2s_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
mm2s_length_wren : out std_logic ; --
--
-- S2MM Signals --
tdest_in : in std_logic_vector (6 downto 0) ;
same_tdest_in : in std_logic;
sg_ctl : out std_logic_vector (7 downto 0) ;
s2mm_sof : in std_logic ;
s2mm_eof : in std_logic ;
s2mm_stop : in std_logic ; --
s2mm_halted_clr : in std_logic ; --
s2mm_halted_set : in std_logic ; --
s2mm_idle_set : in std_logic ; --
s2mm_idle_clr : in std_logic ; --
s2mm_dma_interr_set : in std_logic ; --
s2mm_dma_slverr_set : in std_logic ; --
s2mm_dma_decerr_set : in std_logic ; --
s2mm_ioc_irq_set : in std_logic ; --
s2mm_dly_irq_set : in std_logic ; --
s2mm_irqdelay_status : in std_logic_vector(7 downto 0) ; --
s2mm_irqthresh_status : in std_logic_vector(7 downto 0) ; --
s2mm_ftch_interr_set : in std_logic ; --
s2mm_ftch_slverr_set : in std_logic ; --
s2mm_ftch_decerr_set : in std_logic ; --
s2mm_updt_interr_set : in std_logic ; --
s2mm_updt_slverr_set : in std_logic ; --
s2mm_updt_decerr_set : in std_logic ; --
s2mm_new_curdesc_wren : in std_logic ; --
s2mm_new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_tvalid : in std_logic;
s2mm_dlyirq_dsble : out std_logic ; -- CR605888 --
s2mm_irqthresh_rstdsbl : out std_logic ; -- CR572013 --
s2mm_irqthresh_wren : out std_logic ; --
s2mm_irqdelay_wren : out std_logic ; --
s2mm_tailpntr_updated : out std_logic ; --
s2mm_tvalid_latch : out std_logic ;
s2mm_tvalid_latch_del : out std_logic ;
s2mm_dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s2mm_dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s2mm_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_taildesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_da : out std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
s2mm_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_length_wren : out std_logic ; --
s2mm_bytes_rcvd : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_bytes_rcvd_wren : in std_logic ; --
--
soft_reset : out std_logic ; --
soft_reset_clr : in std_logic ; --
--
-- Fetch/Update error addresses --
ftch_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_introut : out std_logic ; --
s2mm_introut : out std_logic --
);
end axi_dma_reg_module;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_reg_module is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant LENGTH_PAD_WIDTH : integer := C_S_AXI_LITE_DATA_WIDTH - C_SG_LENGTH_WIDTH;
constant LENGTH_PAD : std_logic_vector(LENGTH_PAD_WIDTH-1 downto 0) := (others => '0');
constant ZERO_BYTES : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
constant NUM_REG_PER_S2MM_INT : integer := NUM_REG_PER_CHANNEL + (NUM_REG_PER_S2MM*C_ENABLE_MULTI_CHANNEL);
-- Specifies to axi_dma_register which block belongs to S2MM channel
-- so simple dma s2mm_da register offset can be correctly assigned
-- CR603034
--constant NOT_S2MM_CHANNEL : integer := 0;
--constant IS_S2MM_CHANNEL : integer := 1;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal axi2ip_wrce : std_logic_vector(23+(120*C_ENABLE_MULTI_CHANNEL) - 1 downto 0) := (others => '0');
signal axi2ip_wrdata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_rdce : std_logic_vector(23+(120*C_ENABLE_MULTI_CHANNEL) - 1 downto 0) := (others => '0');
signal axi2ip_rdaddr : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ip2axi_rddata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmacr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmasr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_sa_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_length_i : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_error_in : std_logic := '0';
signal mm2s_error_out : std_logic := '0';
signal s2mm_curdesc_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_curdesc_int2 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int2 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int3 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_dmacr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_dmasr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc1_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc1_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc1_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc1_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc2_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc2_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc2_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc2_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc3_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc3_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc3_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc3_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc4_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc4_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc4_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc4_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc5_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc5_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc5_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc5_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc6_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc6_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc6_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc6_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc7_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc7_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc7_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc7_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc8_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc8_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc8_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc8_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc9_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc9_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc9_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc9_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc10_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc10_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc10_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc10_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc11_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc11_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc11_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc11_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc12_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc12_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc12_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc12_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc13_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc13_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc13_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc13_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc14_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc14_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc14_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc14_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc15_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc15_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc15_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc15_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_lsb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_msb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_lsb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_msb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_da_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_length_i : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_error_in : std_logic := '0';
signal s2mm_error_out : std_logic := '0';
signal read_addr : std_logic_vector(9 downto 0) := (others => '0');
signal mm2s_introut_i_cdc_from : std_logic := '0';
signal mm2s_introut_d1_cdc_tig : std_logic := '0';
signal mm2s_introut_to : std_logic := '0';
signal s2mm_introut_i_cdc_from : std_logic := '0';
signal s2mm_introut_d1_cdc_tig : std_logic := '0';
signal s2mm_introut_to : std_logic := '0';
signal mm2s_sgctl : std_logic_vector (7 downto 0);
signal s2mm_sgctl : std_logic_vector (7 downto 0);
signal or_sgctl : std_logic_vector (7 downto 0);
signal open_window, wren : std_logic;
signal s2mm_tailpntr_updated_int : std_logic;
signal s2mm_tailpntr_updated_int1 : std_logic;
signal s2mm_tailpntr_updated_int2 : std_logic;
signal s2mm_tailpntr_updated_int3 : std_logic;
signal tvalid_int : std_logic;
signal tvalid_int1 : std_logic;
signal tvalid_int2 : std_logic;
signal new_tdest : std_logic;
signal tvalid_latch : std_logic;
signal tdest_changed : std_logic;
signal tdest_fix : std_logic_vector (4 downto 0);
signal same_tdest_int1 : std_logic;
signal same_tdest_int2 : std_logic;
signal same_tdest_int3 : std_logic;
signal same_tdest_arrived : std_logic;
--ATTRIBUTE async_reg OF mm2s_introut_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_introut_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF mm2s_introut_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_introut_to : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
or_sgctl <= mm2s_sgctl or s2mm_sgctl;
sg_ctl <= mm2s_sgctl or s2mm_sgctl;
mm2s_dmacr <= mm2s_dmacr_i; -- MM2S DMA Control Register
mm2s_dmasr <= mm2s_dmasr_i; -- MM2S DMA Status Register
mm2s_sa <= mm2s_sa_i; -- MM2S Source Address (Simple Only)
mm2s_length <= mm2s_length_i; -- MM2S Length (Simple Only)
s2mm_dmacr <= s2mm_dmacr_i; -- S2MM DMA Control Register
s2mm_dmasr <= s2mm_dmasr_i; -- S2MM DMA Status Register
s2mm_da <= s2mm_da_i; -- S2MM Destination Address (Simple Only)
s2mm_length <= s2mm_length_i; -- S2MM Length (Simple Only)
-- Soft reset set in mm2s DMACR or s2MM DMACR
soft_reset <= mm2s_dmacr_i(DMACR_RESET_BIT)
or s2mm_dmacr_i(DMACR_RESET_BIT);
-- CR572013 - added to match legacy SDMA operation
mm2s_irqthresh_rstdsbl <= not mm2s_dmacr_i(DMACR_DLY_IRQEN_BIT);
s2mm_irqthresh_rstdsbl <= not s2mm_dmacr_i(DMACR_DLY_IRQEN_BIT);
--GEN_S2MM_TDEST : if (C_NUM_S2MM_CHANNELS > 1) generate
GEN_S2MM_TDEST : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_S2MM = 1) generate
begin
PROC_WREN : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
s2mm_taildesc_int3 <= (others => '0');
s2mm_tailpntr_updated_int <= '0';
s2mm_tailpntr_updated_int2 <= '0';
s2mm_tailpntr_updated <= '0';
else -- (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
-- s2mm_tailpntr_updated_int <= new_tdest or same_tdest_arrived;
-- s2mm_tailpntr_updated_int2 <= s2mm_tailpntr_updated_int;
-- s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int2;
-- Commenting this code as it is causing SG to start early
s2mm_tailpntr_updated_int <= new_tdest or s2mm_tailpntr_updated_int1 or same_tdest_arrived;
s2mm_tailpntr_updated_int2 <= s2mm_tailpntr_updated_int;
s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int2;
end if;
end if;
end process PROC_WREN;
-- this is always '1' as MCH needs to have all desc reg programmed before hand
--s2mm_tailpntr_updated_int3_i <= s2mm_tailpntr_updated_int2_i and (not s2mm_tailpntr_updated_int_i); -- and tvalid_latch;
tdest_fix <= "11111";
new_tdest <= tvalid_int1 xor tvalid_int2;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
tvalid_int <= '0';
tvalid_int1 <= '0';
tvalid_int2 <= '0';
tvalid_latch <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
tvalid_int <= tdest_in (6); --s2mm_tvalid;
tvalid_int1 <= tvalid_int;
tvalid_int2 <= tvalid_int1;
s2mm_tvalid_latch_del <= tvalid_latch;
if (new_tdest = '1') then
tvalid_latch <= '0';
else
tvalid_latch <= '1';
end if;
end if;
end if;
end process;
-- will trigger tailptrupdtd and it will then get SG out of pause
same_tdest_arrived <= same_tdest_int2 xor same_tdest_int3;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
same_tdest_int1 <= '0';
same_tdest_int2 <= '0';
same_tdest_int3 <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
same_tdest_int1 <= same_tdest_in;
same_tdest_int2 <= same_tdest_int1;
same_tdest_int3 <= same_tdest_int2;
end if;
end if;
end process;
-- process (m_axi_sg_aclk)
-- begin
-- if (m_axi_sg_aresetn = '0') then
-- tvalid_int <= '0';
-- tvalid_int1 <= '0';
-- tvalid_latch <= '0';
-- tdest_in_int <= (others => '0');
-- elsif (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
-- tvalid_int <= s2mm_tvalid;
-- tvalid_int1 <= tvalid_int;
-- tdest_in_int <= tdest_in;
-- -- if (tvalid_int1 = '1' and (tdest_in_int /= tdest_in)) then
-- if (tvalid_int1 = '1' and tdest_in_int = "00000" and (tdest_in_int = tdest_in)) then
-- tvalid_latch <= '1';
-- elsif (tvalid_int1 = '1' and (tdest_in_int /= tdest_in)) then
-- tvalid_latch <= '0';
-- elsif (tvalid_int1 = '1' and (tdest_in_int = tdest_in)) then
-- tvalid_latch <= '1';
-- end if;
-- end if;
-- end process;
s2mm_tvalid_latch <= tvalid_latch;
PROC_TDEST_IN : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
s2mm_curdesc_int2 <= (others => '0');
s2mm_taildesc_int2 <= (others => '0');
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
s2mm_curdesc_int2 <= s2mm_curdesc_int;
s2mm_taildesc_int2 <= s2mm_taildesc_int;
end if;
end if;
end process PROC_TDEST_IN;
s2mm_curdesc <= s2mm_curdesc_int2;
s2mm_taildesc <= s2mm_taildesc_int2;
end generate GEN_S2MM_TDEST;
GEN_S2MM_NO_TDEST : if (C_ENABLE_MULTI_CHANNEL = 0) generate
--GEN_S2MM_NO_TDEST : if (C_NUM_S2MM_CHANNELS = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate
begin
s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int1;
s2mm_curdesc <= s2mm_curdesc_int;
s2mm_taildesc <= s2mm_taildesc_int;
s2mm_tvalid_latch <= '1';
s2mm_tvalid_latch_del <= '1';
end generate GEN_S2MM_NO_TDEST;
-- For 32 bit address map only lsb registers out
GEN_DESC_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
mm2s_curdesc <= mm2s_curdesc_lsb_i;
mm2s_taildesc <= mm2s_taildesc_lsb_i;
s2mm_curdesc_int <= s2mm_curdesc_lsb_muxed;
s2mm_taildesc_int <= s2mm_taildesc_lsb_muxed;
end generate GEN_DESC_ADDR_EQL32;
-- For 64 bit address map lsb and msb registers out
GEN_DESC_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
mm2s_curdesc <= mm2s_curdesc_msb_i & mm2s_curdesc_lsb_i;
mm2s_taildesc <= mm2s_taildesc_msb_i & mm2s_taildesc_lsb_i;
s2mm_curdesc_int <= s2mm_curdesc_msb_muxed & s2mm_curdesc_lsb_muxed;
s2mm_taildesc_int <= s2mm_taildesc_msb_muxed & s2mm_taildesc_lsb_muxed;
end generate GEN_DESC_ADDR_EQL64;
-------------------------------------------------------------------------------
-- Generate AXI Lite Inteface
-------------------------------------------------------------------------------
GEN_AXI_LITE_IF : if C_INCLUDE_MM2S = 1 or C_INCLUDE_S2MM = 1 generate
begin
AXI_LITE_IF_I : entity axi_dma_v7_1.axi_dma_lite_if
generic map(
C_NUM_CE => 23+(120*C_ENABLE_MULTI_CHANNEL) ,
C_AXI_LITE_IS_ASYNC => C_AXI_LITE_IS_ASYNC ,
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH
)
port map(
ip2axi_aclk => m_axi_sg_aclk ,
ip2axi_aresetn => m_axi_sg_hrdresetn ,
s_axi_lite_aclk => s_axi_lite_aclk ,
s_axi_lite_aresetn => axi_lite_reset_n ,
-- AXI Lite Write Address Channel
s_axi_lite_awvalid => s_axi_lite_awvalid ,
s_axi_lite_awready => s_axi_lite_awready ,
s_axi_lite_awaddr => s_axi_lite_awaddr ,
-- AXI Lite Write Data Channel
s_axi_lite_wvalid => s_axi_lite_wvalid ,
s_axi_lite_wready => s_axi_lite_wready ,
s_axi_lite_wdata => s_axi_lite_wdata ,
-- AXI Lite Write Response Channel
s_axi_lite_bresp => s_axi_lite_bresp ,
s_axi_lite_bvalid => s_axi_lite_bvalid ,
s_axi_lite_bready => s_axi_lite_bready ,
-- AXI Lite Read Address Channel
s_axi_lite_arvalid => s_axi_lite_arvalid ,
s_axi_lite_arready => s_axi_lite_arready ,
s_axi_lite_araddr => s_axi_lite_araddr ,
s_axi_lite_rvalid => s_axi_lite_rvalid ,
s_axi_lite_rready => s_axi_lite_rready ,
s_axi_lite_rdata => s_axi_lite_rdata ,
s_axi_lite_rresp => s_axi_lite_rresp ,
-- User IP Interface
axi2ip_wrce => axi2ip_wrce ,
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_rdce => open ,
axi2ip_rdaddr => axi2ip_rdaddr ,
ip2axi_rddata => ip2axi_rddata
);
end generate GEN_AXI_LITE_IF;
-------------------------------------------------------------------------------
-- No channels therefore do not generate an AXI Lite interface
-------------------------------------------------------------------------------
GEN_NO_AXI_LITE_IF : if C_INCLUDE_MM2S = 0 and C_INCLUDE_S2MM = 0 generate
begin
s_axi_lite_awready <= '0';
s_axi_lite_wready <= '0';
s_axi_lite_bresp <= (others => '0');
s_axi_lite_bvalid <= '0';
s_axi_lite_arready <= '0';
s_axi_lite_rvalid <= '0';
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rresp <= (others => '0');
end generate GEN_NO_AXI_LITE_IF;
-------------------------------------------------------------------------------
-- Generate MM2S Registers if included
-------------------------------------------------------------------------------
GEN_MM2S_REGISTERS : if C_INCLUDE_MM2S = 1 generate
begin
I_MM2S_DMA_REGISTER : entity axi_dma_v7_1.axi_dma_register
generic map (
C_NUM_REGISTERS => NUM_REG_PER_CHANNEL ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
-- C_NUM_S2MM_CHANNELS => 1 --C_S2MM_NUM_CHANNELS
--C_CHANNEL_IS_S2MM => NOT_S2MM_CHANNEL CR603034
)
port map(
-- Secondary Clock / Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- CPU Write Control (via AXI Lite)
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_wrce => axi2ip_wrce
(RESERVED_2C_INDEX
downto MM2S_DMACR_INDEX),
--(MM2S_LENGTH_INDEX
-- DMASR Register bit control/status
stop_dma => mm2s_stop ,
halted_clr => mm2s_halted_clr ,
halted_set => mm2s_halted_set ,
idle_set => mm2s_idle_set ,
idle_clr => mm2s_idle_clr ,
ioc_irq_set => mm2s_ioc_irq_set ,
dly_irq_set => mm2s_dly_irq_set ,
irqdelay_status => mm2s_irqdelay_status ,
irqthresh_status => mm2s_irqthresh_status ,
-- SG Error Control
ftch_interr_set => mm2s_ftch_interr_set ,
ftch_slverr_set => mm2s_ftch_slverr_set ,
ftch_decerr_set => mm2s_ftch_decerr_set ,
ftch_error_addr => ftch_error_addr ,
updt_interr_set => mm2s_updt_interr_set ,
updt_slverr_set => mm2s_updt_slverr_set ,
updt_decerr_set => mm2s_updt_decerr_set ,
updt_error_addr => updt_error_addr ,
dma_interr_set => mm2s_dma_interr_set ,
dma_slverr_set => mm2s_dma_slverr_set ,
dma_decerr_set => mm2s_dma_decerr_set ,
irqthresh_wren => mm2s_irqthresh_wren ,
irqdelay_wren => mm2s_irqdelay_wren ,
dlyirq_dsble => mm2s_dlyirq_dsble , -- CR605888
error_in => s2mm_error_out ,
error_out => mm2s_error_out ,
introut => mm2s_introut_i_cdc_from ,
soft_reset_in => s2mm_dmacr_i(DMACR_RESET_BIT),
soft_reset_clr => soft_reset_clr ,
-- CURDESC Update
update_curdesc => mm2s_new_curdesc_wren ,
new_curdesc => mm2s_new_curdesc ,
-- TAILDESC Update
tailpntr_updated => mm2s_tailpntr_updated ,
-- Channel Registers
sg_ctl => mm2s_sgctl ,
dmacr => mm2s_dmacr_i ,
dmasr => mm2s_dmasr_i ,
curdesc_lsb => mm2s_curdesc_lsb_i ,
curdesc_msb => mm2s_curdesc_msb_i ,
taildesc_lsb => mm2s_taildesc_lsb_i ,
taildesc_msb => mm2s_taildesc_msb_i ,
-- curdesc1_lsb => open ,
-- curdesc1_msb => open ,
-- taildesc1_lsb => open ,
-- taildesc1_msb => open ,
-- curdesc2_lsb => open ,
-- curdesc2_msb => open ,
-- taildesc2_lsb => open ,
-- taildesc2_msb => open ,
--
-- curdesc3_lsb => open ,
-- curdesc3_msb => open ,
-- taildesc3_lsb => open ,
-- taildesc3_msb => open ,
--
-- curdesc4_lsb => open ,
-- curdesc4_msb => open ,
-- taildesc4_lsb => open ,
-- taildesc4_msb => open ,
--
-- curdesc5_lsb => open ,
-- curdesc5_msb => open ,
-- taildesc5_lsb => open ,
-- taildesc5_msb => open ,
--
-- curdesc6_lsb => open ,
-- curdesc6_msb => open ,
-- taildesc6_lsb => open ,
-- taildesc6_msb => open ,
--
-- curdesc7_lsb => open ,
-- curdesc7_msb => open ,
-- taildesc7_lsb => open ,
-- taildesc7_msb => open ,
--
-- curdesc8_lsb => open ,
-- curdesc8_msb => open ,
-- taildesc8_lsb => open ,
-- taildesc8_msb => open ,
--
-- curdesc9_lsb => open ,
-- curdesc9_msb => open ,
-- taildesc9_lsb => open ,
-- taildesc9_msb => open ,
--
-- curdesc10_lsb => open ,
-- curdesc10_msb => open ,
-- taildesc10_lsb => open ,
-- taildesc10_msb => open ,
--
-- curdesc11_lsb => open ,
-- curdesc11_msb => open ,
-- taildesc11_lsb => open ,
-- taildesc11_msb => open ,
--
-- curdesc12_lsb => open ,
-- curdesc12_msb => open ,
-- taildesc12_lsb => open ,
-- taildesc12_msb => open ,
--
-- curdesc13_lsb => open ,
-- curdesc13_msb => open ,
-- taildesc13_lsb => open ,
-- taildesc13_msb => open ,
--
-- curdesc14_lsb => open ,
-- curdesc14_msb => open ,
-- taildesc14_lsb => open ,
-- taildesc14_msb => open ,
--
--
-- curdesc15_lsb => open ,
-- curdesc15_msb => open ,
-- taildesc15_lsb => open ,
-- taildesc15_msb => open ,
--
-- tdest_in => "00000" ,
buffer_address => mm2s_sa_i ,
buffer_length => mm2s_length_i ,
buffer_length_wren => mm2s_length_wren ,
bytes_received => ZERO_BYTES , -- Not used on transmit
bytes_received_wren => '0' -- Not used on transmit
);
-- If async clocks then cross interrupt out to AXI Lite clock domain
GEN_INTROUT_ASYNC : if C_AXI_LITE_IS_ASYNC = 1 generate
begin
PROC_REG_INTR2LITE : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_introut_i_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => mm2s_introut_to,
scndry_vect_out => open
);
-- PROC_REG_INTR2LITE : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- -- if(axi_lite_reset_n = '0')then
-- -- mm2s_introut_d1_cdc_tig <= '0';
-- -- mm2s_introut_to <= '0';
-- -- else
-- mm2s_introut_d1_cdc_tig <= mm2s_introut_i_cdc_from;
-- mm2s_introut_to <= mm2s_introut_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process PROC_REG_INTR2LITE;
mm2s_introut <= mm2s_introut_to;
end generate GEN_INTROUT_ASYNC;
-- If sync then simply pass out
GEN_INTROUT_SYNC : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
mm2s_introut <= mm2s_introut_i_cdc_from;
end generate GEN_INTROUT_SYNC;
end generate GEN_MM2S_REGISTERS;
-------------------------------------------------------------------------------
-- Tie MM2S Register outputs to zero if excluded
-------------------------------------------------------------------------------
GEN_NO_MM2S_REGISTERS : if C_INCLUDE_MM2S = 0 generate
begin
mm2s_dmacr_i <= (others => '0');
mm2s_dmasr_i <= (others => '0');
mm2s_curdesc_lsb_i <= (others => '0');
mm2s_curdesc_msb_i <= (others => '0');
mm2s_taildesc_lsb_i <= (others => '0');
mm2s_taildesc_msb_i <= (others => '0');
mm2s_tailpntr_updated <= '0';
mm2s_sa_i <= (others => '0');
mm2s_length_i <= (others => '0');
mm2s_length_wren <= '0';
mm2s_irqthresh_wren <= '0';
mm2s_irqdelay_wren <= '0';
mm2s_tailpntr_updated <= '0';
mm2s_introut <= '0';
mm2s_sgctl <= (others => '0');
mm2s_dlyirq_dsble <= '0';
end generate GEN_NO_MM2S_REGISTERS;
-------------------------------------------------------------------------------
-- Generate S2MM Registers if included
-------------------------------------------------------------------------------
GEN_S2MM_REGISTERS : if C_INCLUDE_S2MM = 1 generate
begin
I_S2MM_DMA_REGISTER : entity axi_dma_v7_1.axi_dma_register_s2mm
generic map (
C_NUM_REGISTERS => NUM_REG_PER_S2MM_INT, --NUM_REG_TOTAL, --NUM_REG_PER_CHANNEL ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
--C_CHANNEL_IS_S2MM => IS_S2MM_CHANNEL CR603034
)
port map(
-- Secondary Clock / Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- CPU Write Control (via AXI Lite)
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_wrce => axi2ip_wrce
((23+(120*C_ENABLE_MULTI_CHANNEL)-1)
downto RESERVED_2C_INDEX) ,
-- downto S2MM_DMACR_INDEX),
--S2MM_LENGTH_INDEX
-- DMASR Register bit control/status
stop_dma => s2mm_stop ,
halted_clr => s2mm_halted_clr ,
halted_set => s2mm_halted_set ,
idle_set => s2mm_idle_set ,
idle_clr => s2mm_idle_clr ,
ioc_irq_set => s2mm_ioc_irq_set ,
dly_irq_set => s2mm_dly_irq_set ,
irqdelay_status => s2mm_irqdelay_status ,
irqthresh_status => s2mm_irqthresh_status ,
-- SG Error Control
dma_interr_set => s2mm_dma_interr_set ,
dma_slverr_set => s2mm_dma_slverr_set ,
dma_decerr_set => s2mm_dma_decerr_set ,
ftch_interr_set => s2mm_ftch_interr_set ,
ftch_slverr_set => s2mm_ftch_slverr_set ,
ftch_decerr_set => s2mm_ftch_decerr_set ,
ftch_error_addr => ftch_error_addr ,
updt_interr_set => s2mm_updt_interr_set ,
updt_slverr_set => s2mm_updt_slverr_set ,
updt_decerr_set => s2mm_updt_decerr_set ,
updt_error_addr => updt_error_addr ,
irqthresh_wren => s2mm_irqthresh_wren ,
irqdelay_wren => s2mm_irqdelay_wren ,
dlyirq_dsble => s2mm_dlyirq_dsble , -- CR605888
error_in => mm2s_error_out ,
error_out => s2mm_error_out ,
introut => s2mm_introut_i_cdc_from ,
soft_reset_in => mm2s_dmacr_i(DMACR_RESET_BIT),
soft_reset_clr => soft_reset_clr ,
-- CURDESC Update
update_curdesc => s2mm_new_curdesc_wren ,
new_curdesc => s2mm_new_curdesc ,
-- TAILDESC Update
tailpntr_updated => s2mm_tailpntr_updated_int1 ,
-- Channel Registers
sg_ctl => s2mm_sgctl ,
dmacr => s2mm_dmacr_i ,
dmasr => s2mm_dmasr_i ,
curdesc_lsb => s2mm_curdesc_lsb_i ,
curdesc_msb => s2mm_curdesc_msb_i ,
taildesc_lsb => s2mm_taildesc_lsb_i ,
taildesc_msb => s2mm_taildesc_msb_i ,
curdesc1_lsb => s2mm_curdesc1_lsb_i ,
curdesc1_msb => s2mm_curdesc1_msb_i ,
taildesc1_lsb => s2mm_taildesc1_lsb_i ,
taildesc1_msb => s2mm_taildesc1_msb_i ,
curdesc2_lsb => s2mm_curdesc2_lsb_i ,
curdesc2_msb => s2mm_curdesc2_msb_i ,
taildesc2_lsb => s2mm_taildesc2_lsb_i ,
taildesc2_msb => s2mm_taildesc2_msb_i ,
curdesc3_lsb => s2mm_curdesc3_lsb_i ,
curdesc3_msb => s2mm_curdesc3_msb_i ,
taildesc3_lsb => s2mm_taildesc3_lsb_i ,
taildesc3_msb => s2mm_taildesc3_msb_i ,
curdesc4_lsb => s2mm_curdesc4_lsb_i ,
curdesc4_msb => s2mm_curdesc4_msb_i ,
taildesc4_lsb => s2mm_taildesc4_lsb_i ,
taildesc4_msb => s2mm_taildesc4_msb_i ,
curdesc5_lsb => s2mm_curdesc5_lsb_i ,
curdesc5_msb => s2mm_curdesc5_msb_i ,
taildesc5_lsb => s2mm_taildesc5_lsb_i ,
taildesc5_msb => s2mm_taildesc5_msb_i ,
curdesc6_lsb => s2mm_curdesc6_lsb_i ,
curdesc6_msb => s2mm_curdesc6_msb_i ,
taildesc6_lsb => s2mm_taildesc6_lsb_i ,
taildesc6_msb => s2mm_taildesc6_msb_i ,
curdesc7_lsb => s2mm_curdesc7_lsb_i ,
curdesc7_msb => s2mm_curdesc7_msb_i ,
taildesc7_lsb => s2mm_taildesc7_lsb_i ,
taildesc7_msb => s2mm_taildesc7_msb_i ,
curdesc8_lsb => s2mm_curdesc8_lsb_i ,
curdesc8_msb => s2mm_curdesc8_msb_i ,
taildesc8_lsb => s2mm_taildesc8_lsb_i ,
taildesc8_msb => s2mm_taildesc8_msb_i ,
curdesc9_lsb => s2mm_curdesc9_lsb_i ,
curdesc9_msb => s2mm_curdesc9_msb_i ,
taildesc9_lsb => s2mm_taildesc9_lsb_i ,
taildesc9_msb => s2mm_taildesc9_msb_i ,
curdesc10_lsb => s2mm_curdesc10_lsb_i ,
curdesc10_msb => s2mm_curdesc10_msb_i ,
taildesc10_lsb => s2mm_taildesc10_lsb_i ,
taildesc10_msb => s2mm_taildesc10_msb_i ,
curdesc11_lsb => s2mm_curdesc11_lsb_i ,
curdesc11_msb => s2mm_curdesc11_msb_i ,
taildesc11_lsb => s2mm_taildesc11_lsb_i ,
taildesc11_msb => s2mm_taildesc11_msb_i ,
curdesc12_lsb => s2mm_curdesc12_lsb_i ,
curdesc12_msb => s2mm_curdesc12_msb_i ,
taildesc12_lsb => s2mm_taildesc12_lsb_i ,
taildesc12_msb => s2mm_taildesc12_msb_i ,
curdesc13_lsb => s2mm_curdesc13_lsb_i ,
curdesc13_msb => s2mm_curdesc13_msb_i ,
taildesc13_lsb => s2mm_taildesc13_lsb_i ,
taildesc13_msb => s2mm_taildesc13_msb_i ,
curdesc14_lsb => s2mm_curdesc14_lsb_i ,
curdesc14_msb => s2mm_curdesc14_msb_i ,
taildesc14_lsb => s2mm_taildesc14_lsb_i ,
taildesc14_msb => s2mm_taildesc14_msb_i ,
curdesc15_lsb => s2mm_curdesc15_lsb_i ,
curdesc15_msb => s2mm_curdesc15_msb_i ,
taildesc15_lsb => s2mm_taildesc15_lsb_i ,
taildesc15_msb => s2mm_taildesc15_msb_i ,
tdest_in => tdest_in (5 downto 0) ,
buffer_address => s2mm_da_i ,
buffer_length => s2mm_length_i ,
buffer_length_wren => s2mm_length_wren ,
bytes_received => s2mm_bytes_rcvd ,
bytes_received_wren => s2mm_bytes_rcvd_wren
);
GEN_DESC_MUX_SINGLE_CH : if C_NUM_S2MM_CHANNELS = 1 generate
begin
s2mm_curdesc_lsb_muxed <= s2mm_curdesc_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc_msb_i;
end generate GEN_DESC_MUX_SINGLE_CH;
GEN_DESC_MUX : if C_NUM_S2MM_CHANNELS > 1 generate
begin
PROC_DESC_SEL : process (tdest_in, s2mm_curdesc_lsb_i,s2mm_curdesc_msb_i, s2mm_taildesc_lsb_i, s2mm_taildesc_msb_i,
s2mm_curdesc1_lsb_i,s2mm_curdesc1_msb_i, s2mm_taildesc1_lsb_i, s2mm_taildesc1_msb_i,
s2mm_curdesc2_lsb_i,s2mm_curdesc2_msb_i, s2mm_taildesc2_lsb_i, s2mm_taildesc2_msb_i,
s2mm_curdesc3_lsb_i,s2mm_curdesc3_msb_i, s2mm_taildesc3_lsb_i, s2mm_taildesc3_msb_i,
s2mm_curdesc4_lsb_i,s2mm_curdesc4_msb_i, s2mm_taildesc4_lsb_i, s2mm_taildesc4_msb_i,
s2mm_curdesc5_lsb_i,s2mm_curdesc5_msb_i, s2mm_taildesc5_lsb_i, s2mm_taildesc5_msb_i,
s2mm_curdesc6_lsb_i,s2mm_curdesc6_msb_i, s2mm_taildesc6_lsb_i, s2mm_taildesc6_msb_i,
s2mm_curdesc7_lsb_i,s2mm_curdesc7_msb_i, s2mm_taildesc7_lsb_i, s2mm_taildesc7_msb_i,
s2mm_curdesc8_lsb_i,s2mm_curdesc8_msb_i, s2mm_taildesc8_lsb_i, s2mm_taildesc8_msb_i,
s2mm_curdesc9_lsb_i,s2mm_curdesc9_msb_i, s2mm_taildesc9_lsb_i, s2mm_taildesc9_msb_i,
s2mm_curdesc10_lsb_i,s2mm_curdesc10_msb_i, s2mm_taildesc10_lsb_i, s2mm_taildesc10_msb_i,
s2mm_curdesc11_lsb_i,s2mm_curdesc11_msb_i, s2mm_taildesc11_lsb_i, s2mm_taildesc11_msb_i,
s2mm_curdesc12_lsb_i,s2mm_curdesc12_msb_i, s2mm_taildesc12_lsb_i, s2mm_taildesc12_msb_i,
s2mm_curdesc13_lsb_i,s2mm_curdesc13_msb_i, s2mm_taildesc13_lsb_i, s2mm_taildesc13_msb_i,
s2mm_curdesc14_lsb_i,s2mm_curdesc14_msb_i, s2mm_taildesc14_lsb_i, s2mm_taildesc14_msb_i,
s2mm_curdesc15_lsb_i,s2mm_curdesc15_msb_i, s2mm_taildesc15_lsb_i, s2mm_taildesc15_msb_i
)
begin
case tdest_in (3 downto 0) is
when "0000" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc_msb_i;
when "0001" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc1_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc1_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc1_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc1_msb_i;
when "0010" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc2_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc2_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc2_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc2_msb_i;
when "0011" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc3_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc3_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc3_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc3_msb_i;
when "0100" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc4_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc4_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc4_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc4_msb_i;
when "0101" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc5_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc5_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc5_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc5_msb_i;
when "0110" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc6_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc6_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc6_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc6_msb_i;
when "0111" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc7_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc7_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc7_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc7_msb_i;
when "1000" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc8_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc8_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc8_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc8_msb_i;
when "1001" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc9_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc9_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc9_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc9_msb_i;
when "1010" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc10_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc10_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc10_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc10_msb_i;
when "1011" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc11_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc11_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc11_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc11_msb_i;
when "1100" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc12_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc12_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc12_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc12_msb_i;
when "1101" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc13_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc13_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc13_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc13_msb_i;
when "1110" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc14_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc14_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc14_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc14_msb_i;
when "1111" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc15_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc15_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc15_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc15_msb_i;
when others =>
s2mm_curdesc_lsb_muxed <= (others => '0');
s2mm_curdesc_msb_muxed <= (others => '0');
s2mm_taildesc_lsb_muxed <= (others => '0');
s2mm_taildesc_msb_muxed <= (others => '0');
end case;
end process PROC_DESC_SEL;
end generate GEN_DESC_MUX;
-- If async clocks then cross interrupt out to AXI Lite clock domain
GEN_INTROUT_ASYNC : if C_AXI_LITE_IS_ASYNC = 1 generate
begin
-- Cross interrupt out to AXI Lite clock domain
PROC_REG_INTR2LITE : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_introut_i_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => s2mm_introut_to,
scndry_vect_out => open
);
-- PROC_REG_INTR2LITE : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(axi_lite_reset_n = '0')then
-- s2mm_introut_d1_cdc_tig <= '0';
-- s2mm_introut_to <= '0';
-- else
-- s2mm_introut_d1_cdc_tig <= s2mm_introut_i_cdc_from;
-- s2mm_introut_to <= s2mm_introut_d1_cdc_tig;
-- end if;
-- end if;
-- end process PROC_REG_INTR2LITE;
s2mm_introut <= s2mm_introut_to;
end generate GEN_INTROUT_ASYNC;
-- If sync then simply pass out
GEN_INTROUT_SYNC : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
s2mm_introut <= s2mm_introut_i_cdc_from;
end generate GEN_INTROUT_SYNC;
end generate GEN_S2MM_REGISTERS;
-------------------------------------------------------------------------------
-- Tie S2MM Register outputs to zero if excluded
-------------------------------------------------------------------------------
GEN_NO_S2MM_REGISTERS : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_dmacr_i <= (others => '0');
s2mm_dmasr_i <= (others => '0');
s2mm_curdesc_lsb_i <= (others => '0');
s2mm_curdesc_msb_i <= (others => '0');
s2mm_taildesc_lsb_i <= (others => '0');
s2mm_taildesc_msb_i <= (others => '0');
s2mm_da_i <= (others => '0');
s2mm_length_i <= (others => '0');
s2mm_length_wren <= '0';
s2mm_tailpntr_updated <= '0';
s2mm_introut <= '0';
s2mm_irqthresh_wren <= '0';
s2mm_irqdelay_wren <= '0';
s2mm_tailpntr_updated <= '0';
s2mm_dlyirq_dsble <= '0';
s2mm_tailpntr_updated_int1 <= '0';
s2mm_sgctl <= (others => '0');
end generate GEN_NO_S2MM_REGISTERS;
-------------------------------------------------------------------------------
-- AXI LITE READ MUX
-------------------------------------------------------------------------------
read_addr <= axi2ip_rdaddr(9 downto 0);
-- Generate read mux for Scatter Gather Mode
GEN_READ_MUX_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
mm2s_dmacr_i ,
mm2s_dmasr_i ,
mm2s_curdesc_lsb_i ,
mm2s_curdesc_msb_i ,
mm2s_taildesc_lsb_i ,
mm2s_taildesc_msb_i ,
s2mm_dmacr_i ,
s2mm_dmasr_i ,
s2mm_curdesc_lsb_i ,
s2mm_curdesc_msb_i ,
s2mm_taildesc_lsb_i ,
s2mm_taildesc_msb_i ,
s2mm_curdesc1_lsb_i ,
s2mm_curdesc1_msb_i ,
s2mm_taildesc1_lsb_i ,
s2mm_taildesc1_msb_i ,
s2mm_curdesc2_lsb_i ,
s2mm_curdesc2_msb_i ,
s2mm_taildesc2_lsb_i ,
s2mm_taildesc2_msb_i ,
s2mm_curdesc3_lsb_i ,
s2mm_curdesc3_msb_i ,
s2mm_taildesc3_lsb_i ,
s2mm_taildesc3_msb_i ,
s2mm_curdesc4_lsb_i ,
s2mm_curdesc4_msb_i ,
s2mm_taildesc4_lsb_i ,
s2mm_taildesc4_msb_i ,
s2mm_curdesc5_lsb_i ,
s2mm_curdesc5_msb_i ,
s2mm_taildesc5_lsb_i ,
s2mm_taildesc5_msb_i ,
s2mm_curdesc6_lsb_i ,
s2mm_curdesc6_msb_i ,
s2mm_taildesc6_lsb_i ,
s2mm_taildesc6_msb_i ,
s2mm_curdesc7_lsb_i ,
s2mm_curdesc7_msb_i ,
s2mm_taildesc7_lsb_i ,
s2mm_taildesc7_msb_i ,
s2mm_curdesc8_lsb_i ,
s2mm_curdesc8_msb_i ,
s2mm_taildesc8_lsb_i ,
s2mm_taildesc8_msb_i ,
s2mm_curdesc9_lsb_i ,
s2mm_curdesc9_msb_i ,
s2mm_taildesc9_lsb_i ,
s2mm_taildesc9_msb_i ,
s2mm_curdesc10_lsb_i ,
s2mm_curdesc10_msb_i ,
s2mm_taildesc10_lsb_i ,
s2mm_taildesc10_msb_i ,
s2mm_curdesc11_lsb_i ,
s2mm_curdesc11_msb_i ,
s2mm_taildesc11_lsb_i ,
s2mm_taildesc11_msb_i ,
s2mm_curdesc12_lsb_i ,
s2mm_curdesc12_msb_i ,
s2mm_taildesc12_lsb_i ,
s2mm_taildesc12_msb_i ,
s2mm_curdesc13_lsb_i ,
s2mm_curdesc13_msb_i ,
s2mm_taildesc13_lsb_i ,
s2mm_taildesc13_msb_i ,
s2mm_curdesc14_lsb_i ,
s2mm_curdesc14_msb_i ,
s2mm_taildesc14_lsb_i ,
s2mm_taildesc14_msb_i ,
s2mm_curdesc15_lsb_i ,
s2mm_curdesc15_msb_i ,
s2mm_taildesc15_lsb_i ,
s2mm_taildesc15_msb_i ,
or_sgctl
)
begin
case read_addr is
when MM2S_DMACR_OFFSET =>
ip2axi_rddata <= mm2s_dmacr_i;
when MM2S_DMASR_OFFSET =>
ip2axi_rddata <= mm2s_dmasr_i;
when MM2S_CURDESC_LSB_OFFSET =>
ip2axi_rddata <= mm2s_curdesc_lsb_i;
when MM2S_CURDESC_MSB_OFFSET =>
ip2axi_rddata <= mm2s_curdesc_msb_i;
when MM2S_TAILDESC_LSB_OFFSET =>
ip2axi_rddata <= mm2s_taildesc_lsb_i;
when MM2S_TAILDESC_MSB_OFFSET =>
ip2axi_rddata <= mm2s_taildesc_msb_i;
when SGCTL_OFFSET =>
ip2axi_rddata <= x"00000" & or_sgctl (7 downto 4) & "0000" & or_sgctl (3 downto 0);
when S2MM_DMACR_OFFSET =>
ip2axi_rddata <= s2mm_dmacr_i;
when S2MM_DMASR_OFFSET =>
ip2axi_rddata <= s2mm_dmasr_i;
when S2MM_CURDESC_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc_lsb_i;
when S2MM_CURDESC_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc_msb_i;
when S2MM_TAILDESC_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc_lsb_i;
when S2MM_TAILDESC_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc_msb_i;
when S2MM_CURDESC1_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc1_lsb_i;
when S2MM_CURDESC1_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc1_msb_i;
when S2MM_TAILDESC1_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc1_lsb_i;
when S2MM_TAILDESC1_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc1_msb_i;
when S2MM_CURDESC2_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc2_lsb_i;
when S2MM_CURDESC2_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc2_msb_i;
when S2MM_TAILDESC2_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc2_lsb_i;
when S2MM_TAILDESC2_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc2_msb_i;
when S2MM_CURDESC3_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc3_lsb_i;
when S2MM_CURDESC3_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc3_msb_i;
when S2MM_TAILDESC3_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc3_lsb_i;
when S2MM_TAILDESC3_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc3_msb_i;
when S2MM_CURDESC4_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc4_lsb_i;
when S2MM_CURDESC4_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc4_msb_i;
when S2MM_TAILDESC4_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc4_lsb_i;
when S2MM_TAILDESC4_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc4_msb_i;
when S2MM_CURDESC5_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc5_lsb_i;
when S2MM_CURDESC5_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc5_msb_i;
when S2MM_TAILDESC5_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc5_lsb_i;
when S2MM_TAILDESC5_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc5_msb_i;
when S2MM_CURDESC6_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc6_lsb_i;
when S2MM_CURDESC6_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc6_msb_i;
when S2MM_TAILDESC6_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc6_lsb_i;
when S2MM_TAILDESC6_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc6_msb_i;
when S2MM_CURDESC7_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc7_lsb_i;
when S2MM_CURDESC7_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc7_msb_i;
when S2MM_TAILDESC7_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc7_lsb_i;
when S2MM_TAILDESC7_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc7_msb_i;
when S2MM_CURDESC8_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc8_lsb_i;
when S2MM_CURDESC8_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc8_msb_i;
when S2MM_TAILDESC8_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc8_lsb_i;
when S2MM_TAILDESC8_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc8_msb_i;
when S2MM_CURDESC9_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc9_lsb_i;
when S2MM_CURDESC9_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc9_msb_i;
when S2MM_TAILDESC9_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc9_lsb_i;
when S2MM_TAILDESC9_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc9_msb_i;
when S2MM_CURDESC10_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc10_lsb_i;
when S2MM_CURDESC10_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc10_msb_i;
when S2MM_TAILDESC10_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc10_lsb_i;
when S2MM_TAILDESC10_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc10_msb_i;
when S2MM_CURDESC11_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc11_lsb_i;
when S2MM_CURDESC11_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc11_msb_i;
when S2MM_TAILDESC11_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc11_lsb_i;
when S2MM_TAILDESC11_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc11_msb_i;
when S2MM_CURDESC12_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc12_lsb_i;
when S2MM_CURDESC12_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc12_msb_i;
when S2MM_TAILDESC12_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc12_lsb_i;
when S2MM_TAILDESC12_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc12_msb_i;
when S2MM_CURDESC13_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc13_lsb_i;
when S2MM_CURDESC13_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc13_msb_i;
when S2MM_TAILDESC13_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc13_lsb_i;
when S2MM_TAILDESC13_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc13_msb_i;
when S2MM_CURDESC14_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc14_lsb_i;
when S2MM_CURDESC14_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc14_msb_i;
when S2MM_TAILDESC14_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc14_lsb_i;
when S2MM_TAILDESC14_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc14_msb_i;
when S2MM_CURDESC15_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc15_lsb_i;
when S2MM_CURDESC15_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc15_msb_i;
when S2MM_TAILDESC15_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc15_lsb_i;
when S2MM_TAILDESC15_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc15_msb_i;
-- coverage off
when others =>
ip2axi_rddata <= (others => '0');
-- coverage on
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_FOR_SG;
-- Generate read mux for Simple DMA Mode
GEN_READ_MUX_FOR_SMPL_DMA : if C_INCLUDE_SG = 0 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
mm2s_dmacr_i ,
mm2s_dmasr_i ,
mm2s_sa_i ,
mm2s_length_i ,
s2mm_dmacr_i ,
s2mm_dmasr_i ,
s2mm_da_i ,
s2mm_length_i
)
begin
case read_addr is
when MM2S_DMACR_OFFSET =>
ip2axi_rddata <= mm2s_dmacr_i;
when MM2S_DMASR_OFFSET =>
ip2axi_rddata <= mm2s_dmasr_i;
when MM2S_SA_OFFSET =>
ip2axi_rddata <= mm2s_sa_i;
when MM2S_LENGTH_OFFSET =>
ip2axi_rddata <= LENGTH_PAD & mm2s_length_i;
when S2MM_DMACR_OFFSET =>
ip2axi_rddata <= s2mm_dmacr_i;
when S2MM_DMASR_OFFSET =>
ip2axi_rddata <= s2mm_dmasr_i;
when S2MM_DA_OFFSET =>
ip2axi_rddata <= s2mm_da_i;
when S2MM_LENGTH_OFFSET =>
ip2axi_rddata <= LENGTH_PAD & s2mm_length_i;
when others =>
ip2axi_rddata <= (others => '0');
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_FOR_SMPL_DMA;
end implementation;
| bsd-2-clause | 0087dbf012ff1f2683d5467118037dc4 | 0.438016 | 3.716465 | false | false | false | false |
Yarr/Yarr-fw | rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/example_design/rtl/memc3_infrastructure.vhd | 6 | 12,267 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : memc3_infrastructure.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : Clock generation/distribution and reset synchronization
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity memc3_infrastructure is
generic
(
C_INCLK_PERIOD : integer := 2500;
C_RST_ACT_LOW : integer := 1;
C_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
C_CLKOUT0_DIVIDE : integer := 1;
C_CLKOUT1_DIVIDE : integer := 1;
C_CLKOUT2_DIVIDE : integer := 16;
C_CLKOUT3_DIVIDE : integer := 8;
C_CLKFBOUT_MULT : integer := 2;
C_DIVCLK_DIVIDE : integer := 1
);
port
(
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_i : in std_logic;
clk0 : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
mcb_drp_clk : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic
);
end entity;
architecture syn of memc3_infrastructure is
-- # of clock cycles to delay deassertion of reset. Needs to be a fairly
-- high number not so much for metastability protection, but to give time
-- for reset (i.e. stable clock cycles) to propagate through all state
-- machines and to all control signals (i.e. not all control signals have
-- resets, instead they rely on base state logic being reset, and the effect
-- of that reset propagating through the logic). Need this because we may not
-- be getting stable clock cycles while reset asserted (i.e. since reset
-- depends on PLL/DCM lock status)
constant RST_SYNC_NUM : integer := 25;
constant CLK_PERIOD_NS : real := (real(C_INCLK_PERIOD)) / 1000.0;
constant CLK_PERIOD_INT : integer := C_INCLK_PERIOD/1000;
signal clk_2x_0 : std_logic;
signal clk_2x_180 : std_logic;
signal clk0_bufg : std_logic;
signal clk0_bufg_in : std_logic;
signal mcb_drp_clk_bufg_in : std_logic;
signal clkfbout_clkfbin : std_logic;
signal rst_tmp : std_logic;
signal sys_clk_ibufg : std_logic;
signal sys_rst : std_logic;
signal rst0_sync_r : std_logic_vector(RST_SYNC_NUM-1 downto 0);
signal powerup_pll_locked : std_logic;
signal syn_clk0_powerup_pll_locked : std_logic;
signal locked : std_logic;
signal bufpll_mcb_locked : std_logic;
signal mcb_drp_clk_sig : std_logic;
attribute max_fanout : string;
attribute syn_maxfan : integer;
attribute KEEP : string;
attribute max_fanout of rst0_sync_r : signal is "10";
attribute syn_maxfan of rst0_sync_r : signal is 10;
attribute KEEP of sys_clk_ibufg : signal is "TRUE";
begin
sys_rst <= not(sys_rst_i) when (C_RST_ACT_LOW /= 0) else sys_rst_i;
clk0 <= clk0_bufg;
pll_lock <= bufpll_mcb_locked;
mcb_drp_clk <= mcb_drp_clk_sig;
diff_input_clk : if(C_INPUT_CLK_TYPE = "DIFFERENTIAL") generate
--***********************************************************************
-- Differential input clock input buffers
--***********************************************************************
u_ibufg_sys_clk : IBUFGDS
generic map (
DIFF_TERM => TRUE
)
port map (
I => sys_clk_p,
IB => sys_clk_n,
O => sys_clk_ibufg
);
end generate;
se_input_clk : if(C_INPUT_CLK_TYPE = "SINGLE_ENDED") generate
--***********************************************************************
-- SINGLE_ENDED input clock input buffers
--***********************************************************************
u_ibufg_sys_clk : IBUFG
port map (
I => sys_clk,
O => sys_clk_ibufg
);
end generate;
--***************************************************************************
-- Global clock generation and distribution
--***************************************************************************
u_pll_adv : PLL_ADV
generic map
(
BANDWIDTH => "OPTIMIZED",
CLKIN1_PERIOD => CLK_PERIOD_NS,
CLKIN2_PERIOD => CLK_PERIOD_NS,
CLKOUT0_DIVIDE => C_CLKOUT0_DIVIDE,
CLKOUT1_DIVIDE => C_CLKOUT1_DIVIDE,
CLKOUT2_DIVIDE => C_CLKOUT2_DIVIDE,
CLKOUT3_DIVIDE => C_CLKOUT3_DIVIDE,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
CLKOUT0_PHASE => 0.000,
CLKOUT1_PHASE => 180.000,
CLKOUT2_PHASE => 0.000,
CLKOUT3_PHASE => 0.000,
CLKOUT4_PHASE => 0.000,
CLKOUT5_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT5_DUTY_CYCLE => 0.500,
SIM_DEVICE => "SPARTAN6",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => C_DIVCLK_DIVIDE,
CLKFBOUT_MULT => C_CLKFBOUT_MULT,
CLKFBOUT_PHASE => 0.0,
REF_JITTER => 0.005000
)
port map
(
CLKFBIN => clkfbout_clkfbin,
CLKINSEL => '1',
CLKIN1 => sys_clk_ibufg,
CLKIN2 => '0',
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DWE => '0',
REL => '0',
RST => sys_rst,
CLKFBDCM => open,
CLKFBOUT => clkfbout_clkfbin,
CLKOUTDCM0 => open,
CLKOUTDCM1 => open,
CLKOUTDCM2 => open,
CLKOUTDCM3 => open,
CLKOUTDCM4 => open,
CLKOUTDCM5 => open,
CLKOUT0 => clk_2x_0,
CLKOUT1 => clk_2x_180,
CLKOUT2 => clk0_bufg_in,
CLKOUT3 => mcb_drp_clk_bufg_in,
CLKOUT4 => open,
CLKOUT5 => open,
DO => open,
DRDY => open,
LOCKED => locked
);
U_BUFG_CLK0 : BUFG
port map
(
O => clk0_bufg,
I => clk0_bufg_in
);
--U_BUFG_CLK1 : BUFG
-- port map (
-- O => mcb_drp_clk_sig,
-- I => mcb_drp_clk_bufg_in
-- );
U_BUFG_CLK1 : BUFGCE
port map (
O => mcb_drp_clk_sig,
I => mcb_drp_clk_bufg_in,
CE => locked
);
process (mcb_drp_clk_sig, sys_rst)
begin
if(sys_rst = '1') then
powerup_pll_locked <= '0';
elsif (mcb_drp_clk_sig'event and mcb_drp_clk_sig = '1') then
if (bufpll_mcb_locked = '1') then
powerup_pll_locked <= '1';
end if;
end if;
end process;
process (clk0_bufg, sys_rst)
begin
if(sys_rst = '1') then
syn_clk0_powerup_pll_locked <= '0';
elsif (clk0_bufg'event and clk0_bufg = '1') then
if (bufpll_mcb_locked = '1') then
syn_clk0_powerup_pll_locked <= '1';
end if;
end if;
end process;
--***************************************************************************
-- Reset synchronization
-- NOTES:
-- 1. shut down the whole operation if the PLL hasn't yet locked (and
-- by inference, this means that external sys_rst has been asserted -
-- PLL deasserts LOCKED as soon as sys_rst asserted)
-- 2. asynchronously assert reset. This was we can assert reset even if
-- there is no clock (needed for things like 3-stating output buffers).
-- reset deassertion is synchronous.
-- 3. asynchronous reset only look at pll_lock from PLL during power up. After
-- power up and pll_lock is asserted, the powerup_pll_locked will be asserted
-- forever until sys_rst is asserted again. PLL will lose lock when FPGA
-- enters suspend mode. We don't want reset to MCB get
-- asserted in the application that needs suspend feature.
--***************************************************************************
async_rst <= sys_rst or not(powerup_pll_locked);
-- async_rst <= rst_tmp;
rst_tmp <= sys_rst or not(syn_clk0_powerup_pll_locked);
-- rst_tmp <= sys_rst or not(powerup_pll_locked);
process (clk0_bufg, rst_tmp)
begin
if (rst_tmp = '1') then
rst0_sync_r <= (others => '1');
elsif (rising_edge(clk0_bufg)) then
rst0_sync_r <= rst0_sync_r(RST_SYNC_NUM-2 downto 0) & '0'; -- logical left shift by one (pads with 0)
end if;
end process;
rst0 <= rst0_sync_r(RST_SYNC_NUM-1);
BUFPLL_MCB_INST : BUFPLL_MCB
port map
( IOCLK0 => sysclk_2x,
IOCLK1 => sysclk_2x_180,
LOCKED => locked,
GCLK => mcb_drp_clk_sig,
SERDESSTROBE0 => pll_ce_0,
SERDESSTROBE1 => pll_ce_90,
PLLIN0 => clk_2x_0,
PLLIN1 => clk_2x_180,
LOCK => bufpll_mcb_locked
);
end architecture syn;
| gpl-3.0 | 6db9d408b8078138ebdc6e3abb766fcf | 0.531181 | 3.967335 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/proc_common_v4_0/hdl/src/vhdl/coregen_comp_defs.vhd | 2 | 52,359 | -------------------------------------------------------------------------------
-- $Id:$
-------------------------------------------------------------------------------
-- coregen_comp_defs - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: coregen_comp_defs.vhd
-- Version: initial
-- Description:
-- Component declarations for all black box netlists generated by
-- running COREGEN and FIFO Generator when XST elaborated the client core
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- coregen_comp_defs.vhd
-- |
-- |--- XilinxCoreLib.fifo_generator_v9_2
-- |--- XilinxCoreLib.fifo_generator_v9_3
-- |
-- |--- XilinxCoreLib.blk_mem_gen_v7_1
-- |--- XilinxCoreLib.blk_mem_gen_v7_3
--
-------------------------------------------------------------------------------
-- Author: DET
-- History:
-- DET 02/01/2008 Initial Version
--
-- DET 2/01/2008 for proc_common_v4_0
-- ~~~~~~
-- - Adapted coregen_comp_defs.vhd from proc_common_v2_00_a to create
-- this file.
-- - Changed instance of sync fifo to use new wrapper file that will adapt
-- to FIFO Generator primitive.
-- - Replaced "edk_generatecore" with "generatecore" utility call
-- - Removed the CAM component
-- ^^^^^^
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Added component for Fifo Generator version 4.3
-- - Added Block Memory Generator Component Version 2.7
-- ^^^^^^
--
-- MSH 2/26/2009 for EDK 11.1
-- ~~~~~~
-- - Added component for Fifo Generator version 5.1
-- - Added Block Memory Generator Component Version 3.1
-- ^^^^^^
--
-- DET 3/2/2009 for EDK 11.1
-- ~~~~~~
-- - Added new Parameters and ports for Fifo Generatore 5.1.
-- ^^^^^^
--
-- DET 3/30/2009 EDK 11.2
-- ~~~~~~
-- - Had to reorder parameter list of FIFO Generator 4.3 component to match
-- the corresponding Verilog model due to NCSIM positional order
-- dependancy of parameters in vhdl/verilog use case.
-- ^^^^^^
--
-- DET 4/8/2009 EDK 11.2
-- ~~~~~~
-- - Added blk_mem_gen_v3_2
-- ^^^^^^
--
-- DET 4/9/2009 EDK 11.2
-- ~~~~~~
-- - Added fifo_generator_v5_2
-- ^^^^^^
--
-- DET 2/9/2010 For EDK 12.1
-- ~~~~~~
-- - Added fifo_generator_v5_3
-- - Added blk_mem_gen_v3_3
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Added fifo_generator_v6_1
-- - Added blk_mem_gen_v4_1
-- ^^^^^^
--
-- DET 3/17/2010 Initial
-- ~~~~~~
-- -- Per CR554253
-- - Incorporated changes to comment out FLOP_DELAY parameter from the
-- blk_mem_gen_v4_1 component. This parameter is on the XilinxCoreLib
-- model for blk_mem_gen_v4_1 but is declared as a TIME type for the
-- vhdl version and an integer for the verilog.
-- ^^^^^^
--
-- DET 10/04/2010 EDK 13.1
-- ~~~~~~
-- - Added fifo_generator_v7_3
-- - Added blk_mem_gen_v5_2
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Replaced fifo_generator v7.3 with v8.1
-- - Added blk_mem_gen_v6_1
-- ^^^^^^
--
-- DET 12/17/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR587494
-- - Removed blk_mem_gen v6_1
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- - Update to use blk_mem_gen_v6_2
-- - Remove out of date components.
-- ^^^^^^
--
-- DET 3/3/2011 EDK 13.2
-- ~~~~~~
-- - Removed C_ELABORATION_DIR parameter from the component decalarion
-- ^^^^^^
--
-- DET 3/7/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR596052
-- - Added removed fifo generator and Blk Mem Gen components back into
-- coregen_comp_defs.
-- ^^^^^^
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
library fifo_generator_v11_0;
use fifo_generator_v11_0.all;
library blk_mem_gen_v8_0;
use blk_mem_gen_v8_0.all;
PACKAGE coregen_comp_defs IS
--------------------------------------------------------
-- Declare general attributes used in this file
-- for defining each component being used with
-- the generatecore utility
attribute box_type: string;
attribute GENERATOR_DEFAULT: string;
-------------------------------------------------------
-------------------------------------------------------------------------------------
-- Start FIFO Generator Component for fifo_generator_v11_0
-- The Component declaration for fifo_generator_v11_0 pulled from the
-- Coregen version of
-- file: fifo_generator_v11_0_comp.vhd.
--
-- This component is used for both dual clock (async) and synchronous fifos
-- implemented with BRAM or distributed RAM. Hard FIFO simulation support may not
-- be provided in FIFO Generator V10.0 so not supported here.
--
-- Note: AXI ports and parameters added for this version of FIFO Generator.
--
-------------------------------------------------------------------------------------
COMPONENT fifo_generator_v11_0
GENERIC (
-------------------------------------------------------------------------
-- Generic Declarations
-------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_COUNT_TYPE : integer := 0;
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := "";
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0;
C_FAMILY : string := "virtex6";
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_INT_CLK : integer := 0;
C_HAS_MEMINIT_FILE : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0;
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0;
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0;
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := "";
C_OPTIMIZATION_MODE : integer := 0;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PRIM_FIFO_TYPE : string := "4kx4";
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1;
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1;
C_MSGON_VAL : integer := 1;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_SYNCHRONIZER_STAGE : integer := 2;
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI4 Stream; 2: AXI4/AXI3
C_AXI_TYPE : integer := 0; -- 1: AXI4; 2: AXI4 Lite; 3: AXI3
C_HAS_AXI_WR_CHANNEL : integer := 0;
C_HAS_AXI_RD_CHANNEL : integer := 0;
C_HAS_SLAVE_CE : integer := 0;
C_HAS_MASTER_CE : integer := 0;
C_ADD_NGC_CONSTRAINT : integer := 0;
C_USE_COMMON_OVERFLOW : integer := 0;
C_USE_COMMON_UNDERFLOW : integer := 0;
C_USE_DEFAULT_SETTINGS : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH : integer := 4;
C_AXI_ADDR_WIDTH : integer := 32;
C_AXI_DATA_WIDTH : integer := 64;
C_AXI_LEN_WIDTH : integer := 8;
C_AXI_LOCK_WIDTH : integer := 2;
C_HAS_AXI_ID : integer := 0;
C_HAS_AXI_AWUSER : integer := 0;
C_HAS_AXI_WUSER : integer := 0;
C_HAS_AXI_BUSER : integer := 0;
C_HAS_AXI_ARUSER : integer := 0;
C_HAS_AXI_RUSER : integer := 0;
C_AXI_ARUSER_WIDTH : integer := 1;
C_AXI_AWUSER_WIDTH : integer := 1;
C_AXI_WUSER_WIDTH : integer := 1;
C_AXI_BUSER_WIDTH : integer := 1;
C_AXI_RUSER_WIDTH : integer := 1;
-- AXI Streaming
C_HAS_AXIS_TDATA : integer := 0;
C_HAS_AXIS_TID : integer := 0;
C_HAS_AXIS_TDEST : integer := 0;
C_HAS_AXIS_TUSER : integer := 0;
C_HAS_AXIS_TREADY : integer := 1;
C_HAS_AXIS_TLAST : integer := 0;
C_HAS_AXIS_TSTRB : integer := 0;
C_HAS_AXIS_TKEEP : integer := 0;
C_AXIS_TDATA_WIDTH : integer := 64;
C_AXIS_TID_WIDTH : integer := 8;
C_AXIS_TDEST_WIDTH : integer := 4;
C_AXIS_TUSER_WIDTH : integer := 4;
C_AXIS_TSTRB_WIDTH : integer := 4;
C_AXIS_TKEEP_WIDTH : integer := 4;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 5 = Common Clock Built-in FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH : integer := 1;
C_IMPLEMENTATION_TYPE_WDCH : integer := 1;
C_IMPLEMENTATION_TYPE_WRCH : integer := 1;
C_IMPLEMENTATION_TYPE_RACH : integer := 1;
C_IMPLEMENTATION_TYPE_RDCH : integer := 1;
C_IMPLEMENTATION_TYPE_AXIS : integer := 1;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Sync FIFO
-- 3 = Low Latency Async FIFO
C_APPLICATION_TYPE_WACH : integer := 0;
C_APPLICATION_TYPE_WDCH : integer := 0;
C_APPLICATION_TYPE_WRCH : integer := 0;
C_APPLICATION_TYPE_RACH : integer := 0;
C_APPLICATION_TYPE_RDCH : integer := 0;
C_APPLICATION_TYPE_AXIS : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH : integer := 0;
C_USE_ECC_WDCH : integer := 0;
C_USE_ECC_WRCH : integer := 0;
C_USE_ECC_RACH : integer := 0;
C_USE_ECC_RDCH : integer := 0;
C_USE_ECC_AXIS : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH : integer := 0;
C_ERROR_INJECTION_TYPE_RACH : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH : integer := 32;
C_DIN_WIDTH_WDCH : integer := 64;
C_DIN_WIDTH_WRCH : integer := 2;
C_DIN_WIDTH_RACH : integer := 32;
C_DIN_WIDTH_RDCH : integer := 64;
C_DIN_WIDTH_AXIS : integer := 1;
C_WR_DEPTH_WACH : integer := 16;
C_WR_DEPTH_WDCH : integer := 1024;
C_WR_DEPTH_WRCH : integer := 16;
C_WR_DEPTH_RACH : integer := 16;
C_WR_DEPTH_RDCH : integer := 1024;
C_WR_DEPTH_AXIS : integer := 1024;
C_WR_PNTR_WIDTH_WACH : integer := 4;
C_WR_PNTR_WIDTH_WDCH : integer := 10;
C_WR_PNTR_WIDTH_WRCH : integer := 4;
C_WR_PNTR_WIDTH_RACH : integer := 4;
C_WR_PNTR_WIDTH_RDCH : integer := 10;
C_WR_PNTR_WIDTH_AXIS : integer := 10;
C_HAS_DATA_COUNTS_WACH : integer := 0;
C_HAS_DATA_COUNTS_WDCH : integer := 0;
C_HAS_DATA_COUNTS_WRCH : integer := 0;
C_HAS_DATA_COUNTS_RACH : integer := 0;
C_HAS_DATA_COUNTS_RDCH : integer := 0;
C_HAS_DATA_COUNTS_AXIS : integer := 0;
C_HAS_PROG_FLAGS_WACH : integer := 0;
C_HAS_PROG_FLAGS_WDCH : integer := 0;
C_HAS_PROG_FLAGS_WRCH : integer := 0;
C_HAS_PROG_FLAGS_RACH : integer := 0;
C_HAS_PROG_FLAGS_RDCH : integer := 0;
C_HAS_PROG_FLAGS_AXIS : integer := 0;
-- 0: No Programmable FULL
-- 1: Single Programmable FULL Threshold Constant
-- 3: Single Programmable FULL Threshold Input Port
C_PROG_FULL_TYPE_WACH : integer := 5;
C_PROG_FULL_TYPE_WDCH : integer := 5;
C_PROG_FULL_TYPE_WRCH : integer := 5;
C_PROG_FULL_TYPE_RACH : integer := 5;
C_PROG_FULL_TYPE_RDCH : integer := 5;
C_PROG_FULL_TYPE_AXIS : integer := 5;
-- Single Programmable FULL Threshold Constant Assert Value
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer := 1023;
-- 0: No Programmable EMPTY
-- 1: Single Programmable EMPTY Threshold Constant
-- 3: Single Programmable EMPTY Threshold Input Port
C_PROG_EMPTY_TYPE_WACH : integer := 5;
C_PROG_EMPTY_TYPE_WDCH : integer := 5;
C_PROG_EMPTY_TYPE_WRCH : integer := 5;
C_PROG_EMPTY_TYPE_RACH : integer := 5;
C_PROG_EMPTY_TYPE_RDCH : integer := 5;
C_PROG_EMPTY_TYPE_AXIS : integer := 5;
-- Single Programmable EMPTY Threshold Constant Assert Value
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer := 1022;
C_REG_SLICE_MODE_WACH : integer := 0;
C_REG_SLICE_MODE_WDCH : integer := 0;
C_REG_SLICE_MODE_WRCH : integer := 0;
C_REG_SLICE_MODE_RACH : integer := 0;
C_REG_SLICE_MODE_RDCH : integer := 0;
C_REG_SLICE_MODE_AXIS : integer := 0
);
PORT(
------------------------------------------------------------------------------
-- Input and Output Declarations
------------------------------------------------------------------------------
-- Conventional FIFO Interface Signals
backup : in std_logic := '0';
backup_marker : in std_logic := '0';
clk : in std_logic := '0';
rst : in std_logic := '0';
srst : in std_logic := '0';
wr_clk : in std_logic := '0';
wr_rst : in std_logic := '0';
rd_clk : in std_logic := '0';
rd_rst : in std_logic := '0';
din : in std_logic_vector(C_DIN_WIDTH-1 downto 0) := (others => '0');
wr_en : in std_logic := '0';
rd_en : in std_logic := '0';
-- optional inputs
prog_empty_thresh : in std_logic_vector(C_RD_PNTR_WIDTH-1 downto 0) := (others => '0');
prog_empty_thresh_assert : in std_logic_vector(C_RD_PNTR_WIDTH-1 downto 0) := (others => '0');
prog_empty_thresh_negate : in std_logic_vector(C_RD_PNTR_WIDTH-1 downto 0) := (others => '0');
prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH-1 downto 0) := (others => '0');
prog_full_thresh_assert : in std_logic_vector(C_WR_PNTR_WIDTH-1 downto 0) := (others => '0');
prog_full_thresh_negate : in std_logic_vector(C_WR_PNTR_WIDTH-1 downto 0) := (others => '0');
int_clk : in std_logic := '0';
injectdbiterr : in std_logic := '0';
injectsbiterr : in std_logic := '0';
dout : out std_logic_vector(C_DOUT_WIDTH-1 downto 0) := (others => '0');
full : out std_logic := '0';
almost_full : out std_logic := '0';
wr_ack : out std_logic := '0';
overflow : out std_logic := '0';
empty : out std_logic := '1';
almost_empty : out std_logic := '1';
valid : out std_logic := '0';
underflow : out std_logic := '0';
data_count : out std_logic_vector(C_DATA_COUNT_WIDTH-1 downto 0) := (others => '0');
rd_data_count : out std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 downto 0) := (others => '0');
wr_data_count : out std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 downto 0) := (others => '0');
prog_full : out std_logic := '0';
prog_empty : out std_logic := '1';
sbiterr : out std_logic := '0';
dbiterr : out std_logic := '0';
-- axi global signal
m_aclk : in std_logic := '0';
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '1'; -- Active low reset, default value set to 1
m_aclk_en : in std_logic := '0';
s_aclk_en : in std_logic := '0';
-- axi full/lite slave write channel (write side)
s_axi_awid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(C_AXI_LEN_WIDTH-1 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(3-1 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(2-1 downto 0) := (others => '0');
s_axi_awlock : in std_logic_vector(C_AXI_LOCK_WIDTH-1 downto 0) := (others => '0');
s_axi_awcache : in std_logic_vector(4-1 downto 0) := (others => '0');
s_axi_awprot : in std_logic_vector(3-1 downto 0) := (others => '0');
s_axi_awqos : in std_logic_vector(4-1 downto 0) := (others => '0');
s_axi_awregion : in std_logic_vector(4-1 downto 0) := (others => '0');
s_axi_awuser : in std_logic_vector(C_AXI_AWUSER_WIDTH-1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic := '0';
s_axi_wid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
s_axi_wdata : in std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(C_AXI_DATA_WIDTH/8-1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wuser : in std_logic_vector(C_AXI_WUSER_WIDTH-1 downto 0) := (others => '0');
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic := '0';
s_axi_bid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
s_axi_bresp : out std_logic_vector(2-1 downto 0) := (others => '0');
s_axi_buser : out std_logic_vector(C_AXI_BUSER_WIDTH-1 downto 0) := (others => '0');
s_axi_bvalid : out std_logic := '0';
s_axi_bready : in std_logic := '0';
-- axi full/lite master write channel (read side)
m_axi_awid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
m_axi_awaddr : out std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
m_axi_awlen : out std_logic_vector(C_AXI_LEN_WIDTH-1 downto 0) := (others => '0');
m_axi_awsize : out std_logic_vector(3-1 downto 0) := (others => '0');
m_axi_awburst : out std_logic_vector(2-1 downto 0) := (others => '0');
m_axi_awlock : out std_logic_vector(C_AXI_LOCK_WIDTH-1 downto 0) := (others => '0');
m_axi_awcache : out std_logic_vector(4-1 downto 0) := (others => '0');
m_axi_awprot : out std_logic_vector(3-1 downto 0) := (others => '0');
m_axi_awqos : out std_logic_vector(4-1 downto 0) := (others => '0');
m_axi_awregion : out std_logic_vector(4-1 downto 0) := (others => '0');
m_axi_awuser : out std_logic_vector(C_AXI_AWUSER_WIDTH-1 downto 0) := (others => '0');
m_axi_awvalid : out std_logic := '0';
m_axi_awready : in std_logic := '0';
m_axi_wid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
m_axi_wdata : out std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
m_axi_wstrb : out std_logic_vector(C_AXI_DATA_WIDTH/8-1 downto 0) := (others => '0');
m_axi_wlast : out std_logic := '0';
m_axi_wuser : out std_logic_vector(C_AXI_WUSER_WIDTH-1 downto 0) := (others => '0');
m_axi_wvalid : out std_logic := '0';
m_axi_wready : in std_logic := '0';
m_axi_bid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
m_axi_bresp : in std_logic_vector(2-1 downto 0) := (others => '0');
m_axi_buser : in std_logic_vector(C_AXI_BUSER_WIDTH-1 downto 0) := (others => '0');
m_axi_bvalid : in std_logic := '0';
m_axi_bready : out std_logic := '0';
-- axi full/lite slave read channel (write side)
s_axi_arid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(C_AXI_LEN_WIDTH-1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(3-1 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(2-1 downto 0) := (others => '0');
s_axi_arlock : in std_logic_vector(C_AXI_LOCK_WIDTH-1 downto 0) := (others => '0');
s_axi_arcache : in std_logic_vector(4-1 downto 0) := (others => '0');
s_axi_arprot : in std_logic_vector(3-1 downto 0) := (others => '0');
s_axi_arqos : in std_logic_vector(4-1 downto 0) := (others => '0');
s_axi_arregion : in std_logic_vector(4-1 downto 0) := (others => '0');
s_axi_aruser : in std_logic_vector(C_AXI_ARUSER_WIDTH-1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic := '0';
s_axi_rid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
s_axi_rdata : out std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
s_axi_rresp : out std_logic_vector(2-1 downto 0) := (others => '0');
s_axi_rlast : out std_logic := '0';
s_axi_ruser : out std_logic_vector(C_AXI_RUSER_WIDTH-1 downto 0) := (others => '0');
s_axi_rvalid : out std_logic := '0';
s_axi_rready : in std_logic := '0';
-- axi full/lite master read channel (read side)
m_axi_arid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
m_axi_araddr : out std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
m_axi_arlen : out std_logic_vector(C_AXI_LEN_WIDTH-1 downto 0) := (others => '0');
m_axi_arsize : out std_logic_vector(3-1 downto 0) := (others => '0');
m_axi_arburst : out std_logic_vector(2-1 downto 0) := (others => '0');
m_axi_arlock : out std_logic_vector(C_AXI_LOCK_WIDTH-1 downto 0) := (others => '0');
m_axi_arcache : out std_logic_vector(4-1 downto 0) := (others => '0');
m_axi_arprot : out std_logic_vector(3-1 downto 0) := (others => '0');
m_axi_arqos : out std_logic_vector(4-1 downto 0) := (others => '0');
m_axi_arregion : out std_logic_vector(4-1 downto 0) := (others => '0');
m_axi_aruser : out std_logic_vector(C_AXI_ARUSER_WIDTH-1 downto 0) := (others => '0');
m_axi_arvalid : out std_logic := '0';
m_axi_arready : in std_logic := '0';
m_axi_rid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
m_axi_rdata : in std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
m_axi_rresp : in std_logic_vector(2-1 downto 0) := (others => '0');
m_axi_rlast : in std_logic := '0';
m_axi_ruser : in std_logic_vector(C_AXI_RUSER_WIDTH-1 downto 0) := (others => '0');
m_axi_rvalid : in std_logic := '0';
m_axi_rready : out std_logic := '0';
-- axi streaming slave signals (write side)
s_axis_tvalid : in std_logic := '0';
s_axis_tready : out std_logic := '0';
s_axis_tdata : in std_logic_vector(C_AXIS_TDATA_WIDTH-1 downto 0) := (others => '0');
s_axis_tstrb : in std_logic_vector(C_AXIS_TSTRB_WIDTH-1 downto 0) := (others => '0');
s_axis_tkeep : in std_logic_vector(C_AXIS_TKEEP_WIDTH-1 downto 0) := (others => '0');
s_axis_tlast : in std_logic := '0';
s_axis_tid : in std_logic_vector(C_AXIS_TID_WIDTH-1 downto 0) := (others => '0');
s_axis_tdest : in std_logic_vector(C_AXIS_TDEST_WIDTH-1 downto 0) := (others => '0');
s_axis_tuser : in std_logic_vector(C_AXIS_TUSER_WIDTH-1 downto 0) := (others => '0');
-- axi streaming master signals (read side)
m_axis_tvalid : out std_logic := '0';
m_axis_tready : in std_logic := '0';
m_axis_tdata : out std_logic_vector(C_AXIS_TDATA_WIDTH-1 downto 0) := (others => '0');
m_axis_tstrb : out std_logic_vector(C_AXIS_TSTRB_WIDTH-1 downto 0) := (others => '0');
m_axis_tkeep : out std_logic_vector(C_AXIS_TKEEP_WIDTH-1 downto 0) := (others => '0');
m_axis_tlast : out std_logic := '0';
m_axis_tid : out std_logic_vector(C_AXIS_TID_WIDTH-1 downto 0) := (others => '0');
m_axis_tdest : out std_logic_vector(C_AXIS_TDEST_WIDTH-1 downto 0) := (others => '0');
m_axis_tuser : out std_logic_vector(C_AXIS_TUSER_WIDTH-1 downto 0) := (others => '0');
-- axi full/lite write address channel signals
axi_aw_injectsbiterr : in std_logic := '0';
axi_aw_injectdbiterr : in std_logic := '0';
axi_aw_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 downto 0) := (others => '0');
axi_aw_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 downto 0) := (others => '0');
axi_aw_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WACH downto 0) := (others => '0');
axi_aw_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WACH downto 0) := (others => '0');
axi_aw_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WACH downto 0) := (others => '0');
axi_aw_sbiterr : out std_logic := '0';
axi_aw_dbiterr : out std_logic := '0';
axi_aw_overflow : out std_logic := '0';
axi_aw_underflow : out std_logic := '0';
axi_aw_prog_full : out std_logic := '0';
axi_aw_prog_empty : out std_logic := '1';
-- axi_aw_almost_full : out std_logic := '0';
-- axi_aw_almost_empty : out std_logic := '1';
-- axi full/lite write data channel signals
axi_w_injectsbiterr : in std_logic := '0';
axi_w_injectdbiterr : in std_logic := '0';
axi_w_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 downto 0) := (others => '0');
axi_w_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 downto 0) := (others => '0');
axi_w_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WDCH downto 0) := (others => '0');
axi_w_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WDCH downto 0) := (others => '0');
axi_w_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WDCH downto 0) := (others => '0');
axi_w_sbiterr : out std_logic := '0';
axi_w_dbiterr : out std_logic := '0';
axi_w_overflow : out std_logic := '0';
axi_w_underflow : out std_logic := '0';
axi_w_prog_full : out std_logic := '0';
axi_w_prog_empty : out std_logic := '1';
-- axi_w_almost_full : out std_logic := '0';
-- axi_w_almost_empty : out std_logic := '1';
-- axi full/lite write response channel signals
axi_b_injectsbiterr : in std_logic := '0';
axi_b_injectdbiterr : in std_logic := '0';
axi_b_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 downto 0) := (others => '0');
axi_b_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 downto 0) := (others => '0');
axi_b_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WRCH downto 0) := (others => '0');
axi_b_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WRCH downto 0) := (others => '0');
axi_b_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WRCH downto 0) := (others => '0');
axi_b_sbiterr : out std_logic := '0';
axi_b_dbiterr : out std_logic := '0';
axi_b_overflow : out std_logic := '0';
axi_b_underflow : out std_logic := '0';
axi_b_prog_full : out std_logic := '0';
axi_b_prog_empty : out std_logic := '1';
-- axi_b_almost_full : out std_logic := '0';
-- axi_b_almost_empty : out std_logic := '1';
-- axi full/lite read address channel signals
axi_ar_injectsbiterr : in std_logic := '0';
axi_ar_injectdbiterr : in std_logic := '0';
axi_ar_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 downto 0) := (others => '0');
axi_ar_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 downto 0) := (others => '0');
axi_ar_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RACH downto 0) := (others => '0');
axi_ar_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RACH downto 0) := (others => '0');
axi_ar_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RACH downto 0) := (others => '0');
axi_ar_sbiterr : out std_logic := '0';
axi_ar_dbiterr : out std_logic := '0';
axi_ar_overflow : out std_logic := '0';
axi_ar_underflow : out std_logic := '0';
axi_ar_prog_full : out std_logic := '0';
axi_ar_prog_empty : out std_logic := '1';
-- axi_ar_almost_full : out std_logic := '0';
-- axi_ar_almost_empty : out std_logic := '1';
-- axi full/lite read data channel signals
axi_r_injectsbiterr : in std_logic := '0';
axi_r_injectdbiterr : in std_logic := '0';
axi_r_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 downto 0) := (others => '0');
axi_r_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 downto 0) := (others => '0');
axi_r_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RDCH downto 0) := (others => '0');
axi_r_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RDCH downto 0) := (others => '0');
axi_r_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RDCH downto 0) := (others => '0');
axi_r_sbiterr : out std_logic := '0';
axi_r_dbiterr : out std_logic := '0';
axi_r_overflow : out std_logic := '0';
axi_r_underflow : out std_logic := '0';
axi_r_prog_full : out std_logic := '0';
axi_r_prog_empty : out std_logic := '1';
-- axi_r_almost_full : out std_logic := '0';
-- axi_r_almost_empty : out std_logic := '1';
-- axi streaming fifo related signals
axis_injectsbiterr : in std_logic := '0';
axis_injectdbiterr : in std_logic := '0';
axis_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 downto 0) := (others => '0');
axis_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 downto 0) := (others => '0');
axis_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_AXIS downto 0) := (others => '0');
axis_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_AXIS downto 0) := (others => '0');
axis_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_AXIS downto 0) := (others => '0');
axis_sbiterr : out std_logic := '0';
axis_dbiterr : out std_logic := '0';
axis_overflow : out std_logic := '0';
axis_underflow : out std_logic := '0';
axis_prog_full : out std_logic := '0';
axis_prog_empty : out std_logic := '1'
-- axis_almost_full : out std_logic := '0';
-- axis_almost_empty : out std_logic := '1'
);
END COMPONENT;
-- End FIFO Generator Component ---------------------------------------
-------------------------------------------------------------------------------------
-- Start Block Memory Generator Component for blk_mem_gen_v8_0
-- Component declaration for blk_mem_gen_v8_0 pulled from the
-- /proj/xbuilds/ids_14.4_P.49d.2.0/lin64/14.4/ISE_DS/ISE/vhdl/src/XilinxCoreLib
-- file: blk_mem_gen_v8_0.v
-- Verilog file used to match paramter order for NCSIM compatibility
-------------------------------------------------------------------------------------
component blk_mem_gen_v8_0 IS
GENERIC (
C_FAMILY : STRING := "virtex6";
C_XDEVICEFAMILY : STRING := "virtex6";
C_ELABORATION_DIR : STRING := "";
C_INTERFACE_TYPE : INTEGER := 0;
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_AXI_TYPE : INTEGER := 0;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC := '0';
DBITERR : OUT STD_LOGIC := '0';
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_AClk : IN STD_LOGIC := '0';
S_ARESETN : IN STD_LOGIC := '0';
-- AXI Full/Lite Slave Write (write side)
S_AXI_AWID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN STD_LOGIC := '0';
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST : IN STD_LOGIC := '0';
S_AXI_WVALID : IN STD_LOGIC := '0';
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC := '0';
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN STD_LOGIC := '0';
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC := '0';
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC := '0';
S_AXI_INJECTDBITERR : IN STD_LOGIC := '0';
S_AXI_SBITERR : OUT STD_LOGIC := '0';
S_AXI_DBITERR : OUT STD_LOGIC := '0';
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT; --blk_mem_gen_v8_0
-- The following tells XST that blk_mem_gen_v8_0 is a black box which
-- should be generated command given by the value of this attribute
-- Note the fully qualified SIM (JAVA class) name that forms the
-- basis of the core
-- ATTRIBUTE box_type OF blk_mem_gen_v8_0 : COMPONENT IS "black_box";
-- ATTRIBUTE generator_default OF blk_mem_gen_v8_0 : COMPONENT IS
-- "generatecore com.xilinx.ip.blk_mem_gen_v8_0.blk_mem_gen_v8_0 -a map_qvirtex_to=virtex map_qrvirtex_to=virtex map_virtexe_to=virtex map_qvirtex2_to=virtex2 map_qrvirtex2_to=virtex2 map_spartan2_to=virtex map_spartan2e_to=virtex map_virtex5_to=virtex4 map_spartan3a_to=spartan3e spartan3an_to=spartan3e spartan3adsp_to=spartan3e ";
-- End Block Memory Generator Component for v7_1 -------------------------------
END coregen_comp_defs;
| bsd-2-clause | 3f0eecfea6a966f87b92861fd692e802 | 0.459921 | 3.73273 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/styles/jcl/c16/BaudGen.fixed.vhd | 1 | 1,548 | library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
-- library UNISIM;
-- use UNISIM.VComponents.all;
entity BAUDGEN is
generic (
BG_CLOCK_FREQ : integer;
BG_BAUD_RATE : integer
);
port (
CLK_I : in std_logic;
RST_I : in std_logic;
CE_16 : out std_logic
);
end entity BAUDGEN;
architecture BEHAVIORAL of BAUDGEN is
-- divide bg_clock_freq and bg_baud_rate
-- by their common divisor...
--
function gcd (M, N: integer) return integer is
begin
if ((M mod N) = 0) then
return N;
else
return gcd(N, M mod N);
end if;
end;
constant common_div : integer := gcd(BG_CLOCK_FREQ, 16 * BG_BAUD_RATE);
constant clock_freq : integer := BG_CLOCK_FREQ / common_div;
constant baud_freq : integer := 16 * BG_BAUD_RATE / common_div;
constant limit : integer := clock_freq - baud_freq;
signal counter : integer range 0 to clock_freq - 1;
begin
process (CLK_I) is
begin
if (rising_edge(CLK_I)) then
CE_16 <= '0'; -- make CE_16 stay on for (at most) one cycle
if (RST_I = '1') then
counter <= 0;
elsif (counter >= limit) then
CE_16 <= '1';
counter <= counter - limit;
else
counter <= counter + baud_freq;
end if;
end if;
end process;
end architecture BEHAVIORAL;
| gpl-3.0 | 479eda30e59935d09f043606a17287b5 | 0.614341 | 3.424779 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/vhdlFile/interface_function_specification/classification_test_input.vhd | 1 | 3,230 |
-- Test generic clause
package PACK1 is
generic (
-- Test function
pure function funct1 parameter (
signal sig1, sig2 : in std_logic bus := 0;
constant con1, con2 : in std_logic := 0;
variable sig1, sig2 : in std_logic := 0;
sig1, sig2 : in std_logic bus := 0;
file fil1, fil2 : std_logic;
type typ1) return boolean is <>;
pure function funct1 parameter (
signal sig1, sig2 : in std_logic bus := 0;
constant con1, con2 : in std_logic := 0;
variable sig1, sig2 : in std_logic := 0;
sig1, sig2 : in std_logic bus := 0;
file fil1, fil2 : std_logic;
type typ1) return boolean is func1;
impure function funct1 parameter (
signal sig1, sig2 : in std_logic bus := 0;
constant con1, con2 : in std_logic := 0;
variable sig1, sig2 : in std_logic := 0;
sig1, sig2 : in std_logic bus := 0;
file fil1, fil2 : std_logic;
type typ1) return boolean is <>;
impure function funct1 parameter (
signal sig1, sig2 : in std_logic bus := 0;
constant con1, con2 : in std_logic := 0;
variable sig1, sig2 : in std_logic := 0;
sig1, sig2 : in std_logic bus := 0;
file fil1, fil2 : std_logic;
type typ1) return boolean is func1;
-- Remove Parameter
pure function funct1 (
signal sig1, sig2 : in std_logic bus := 0;
constant con1, con2 : in std_logic := 0;
variable sig1, sig2 : in std_logic := 0;
sig1, sig2 : in std_logic bus := 0;
file fil1, fil2 : std_logic;
type typ1) return boolean is <>;
pure function funct1 (
signal sig1, sig2 : in std_logic bus := 0;
constant con1, con2 : in std_logic := 0;
variable sig1, sig2 : in std_logic := 0;
sig1, sig2 : in std_logic bus := 0;
file fil1, fil2 : std_logic;
type typ1) return boolean is func1;
impure function funct1 (
signal sig1, sig2 : in std_logic bus := 0;
constant con1, con2 : in std_logic := 0;
variable sig1, sig2 : in std_logic := 0;
sig1, sig2 : in std_logic bus := 0;
file fil1, fil2 : std_logic;
type typ1) return boolean is <>;
impure function funct1 (
signal sig1, sig2 : in std_logic bus := 0;
constant con1, con2 : in std_logic := 0;
variable sig1, sig2 : in std_logic := 0;
sig1, sig2 : in std_logic bus := 0;
file fil1, fil2 : std_logic;
type typ1) return boolean is func1;
-- Remove formal_parameter_list
pure function funct1 return boolean is <>;
pure function funct1 return boolean is func1;
impure function funct1 return boolean is <>;
impure function funct1 return boolean is func1;
-- Remove interface_subprogram_default
pure function funct1 return boolean;
pure function funct1 return boolean;
impure function funct1 return boolean;
impure function funct1 return boolean;
-- Remove pure/impure
function funct1 return boolean;
function funct1 return boolean;
function funct1 return boolean;
function funct1 return boolean
);
end package PACK1;
| gpl-3.0 | 1f75f9fb0396b22eb0b968c1e7c3c01e | 0.594118 | 3.621076 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/ramfifo/wr_dc_as.vhd | 2 | 10,866 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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t18NVNr1Ig==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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aYoC/YqBmFOGnOKdEWY=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6304)
`protect data_block
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`protect end_protected
| bsd-2-clause | fe7e402a2f914bb2375c5846c1f74f35 | 0.926284 | 1.887769 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/generic_map/rule_008_test_input.vhd | 1 | 601 |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : INST1
generic map(
G_GEN_1 => 3,
4,
G_GEN_3 => 5
)
port map (w_port_1,
PORT_2 => w_port_2,
w_port_3
);
U_INST1 : INST1
generic map (
3,
G_GEN_2 => 4,
5
)
port map (PORT_1 => w_port_1,
w_port_2,
w_port_3
);
end architecture ARCH;
| gpl-3.0 | 603a590fca63b22cad7416d37d4eedbf | 0.445923 | 2.731818 | false | false | false | false |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/axi_utils_v2_0/hdl/glb_ifx_slave.vhd | 3 | 13,849 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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xDec5KibAw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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f9UO+0Hv/UkfRl3Nf+g=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8512)
`protect data_block
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aP7lZeED1N1rNpkz+QY5KfnPwMYz5eMvag6nuw/hO0qEcde7kXid1/XecTW1ii1HQBkHmlKEtaH6
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EM8FQtyF1CGXpLi3bHZL+QjmV1/1df3Mdqbixzlawwxtp4eZS3K9in2DYZ5/DJZpOt1vRf+5TpxX
6JmRQb0EgwQIXvfkyTOZqBanhw==
`protect end_protected
| mit | 43b7a425bd37159fcf5e9a6c6f80bef2 | 0.932775 | 1.887042 | false | false | false | false |
Yarr/Yarr-fw | ip-cores/spartan6/l2p_fifo.vhd | 2 | 10,707 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file l2p_fifo.vhd when simulating
-- the core, l2p_fifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY l2p_fifo IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END l2p_fifo;
ARCHITECTURE l2p_fifo_a OF l2p_fifo IS
-- synthesis translate_off
COMPONENT wrapped_l2p_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_l2p_fifo USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 10,
c_default_value => "BlankString",
c_din_width => 32,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "00C0FFEE",
c_dout_width => 32,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 1,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "1kx36",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 1023,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 1022,
c_prog_full_type => 4,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 10,
c_rd_depth => 1024,
c_rd_freq => 1,
c_rd_pntr_width => 10,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 10,
c_wr_depth => 1024,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 10,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_l2p_fifo
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_full_thresh_assert => prog_full_thresh_assert,
prog_full_thresh_negate => prog_full_thresh_negate,
dout => dout,
full => full,
empty => empty,
valid => valid,
prog_full => prog_full
);
-- synthesis translate_on
END l2p_fifo_a;
| gpl-3.0 | 0f10e89472b2dfa0deccb99961c52c80 | 0.542355 | 3.30565 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/whitespace/rule_006_test_input.vhd | 1 | 346 |
architecture RTL of FIFO is
signal sig1 : std_logic_vector(3 downto 0);
signal sig1 : std_logic_vector(3 downto 0 );
begin
a <= (b or ((c and d and e)));
a <= (b or ((c and d and e))
);
a <= (b or ((c and d and e))
);
a <= (b or ((c and d and e ) ) );
a <= (b or ' ');
a <= (b or ' ' );
end architecture RTL;
| gpl-3.0 | 4139ae0d6882542b0743c688e0867422 | 0.491329 | 2.768 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/vhdlFile/constant_declaration/classification_test_input.vhd | 1 | 407 |
architecture RTL of FIFO is
constant StartDay : WeekDay := Sat;
constant LogicalGND : Bit := '0';
constant BusWidth, QueueLength : Integer := 16;
constant CLKPeriod : Time := 15 ns;
constant MaxSimTime : Time := 200 * CLKPeriod;
constant EntryCode : NumericCodeType := (2,6,4,8,0,0,1,3);
constant DataBusReset: Std_Logic_Vector(7 downto 0) := "00000000";
begin
end architecture RTL;
| gpl-3.0 | 45adc879a79c544b4adcc869c08c0582 | 0.685504 | 3.449153 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/instantiation/rule_009_test_input.fixed_upper.vhd | 2 | 407 |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
end architecture ARCH;
| gpl-3.0 | 51e8cd7f2b7ceef17e204f02049a4e0e | 0.481572 | 2.787671 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/generic_map/rule_600_test_input.vhd | 1 | 492 |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
GEN_1_G => 3,
GEN_2_G => 4,
GEN_3_G => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : INST1
generic map (
GEN_1_W => 3,
GEN_2 => 4,
GEN_3_WR => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
end architecture ARCH;
| gpl-3.0 | 6be230f9d417f5c802219b03c8773d6b | 0.455285 | 2.779661 | false | false | false | false |
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