repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/ramfifo/compare.vhd | 2 | 11,879 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
B+0Be5dTZPosm+HMT3ybltSImC1RBEBJH7+AHBt/OSIbMBpaiMw+bADHmDe5+D/KcOJ9UHqwaDwv
WmT0fIYL2Q==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Q+xCHUZsDEIhGkN6Hx/OJRFdxTOU0FAu72kvd8+GE2u18J8cjwjtAIrp2ALXfnubOparrO7pFImp
K57aY9ojWnx4xcsYu76BATVOMPgfW9ZX95GUNmc87WciT7UMqiu+SCunN4Wb3fei1OjYkBw5DEkh
E4TNO0pDiWj54yKsULU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
iQVcAa0i6HIiiq/TMks2jBGO5OPQ+CwwGSMAzmjlFD7mcyHgbAuenwiPa7tzwxCqScwd6R0IvBzm
f/FdkE8fBI8CVEnnGaHXdlVnPE++z1rql28MYIsbw7qkmrKgPPIZmFDjXf/dXw4v9JDD5fnZQe5R
ya3KKTeEYyLwc8LRuttywXoEq649U+BrR2L0iuEazjzB/8J0xcmlaiPllj1RARBCK5XIAGjESdVB
mquCCTGtE6XvtMB1zyI76jIdY3jkbRLu+7LpFcJKmVASzSGtuN+qWgO/kgSxewa9+IRGFHod+EgZ
DzPciElpN5vcRoTp+D1QhA8QS9kx0n4s9SozqA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
wEEl4jl4fvrliiz5dm4J8NSopFgyJDycAVLwII/62Dk7puSWC6/G+RNGNHWKsEndY92FwrQNouTn
NkPPV3I7za75AlgNX+O9G3M1p31FU+Ujy4i7rBAg1M3ZEmRU6AmxZVrleX/lErOUyDutawEg0EzD
+fLrFoeiBlzOCN7EcL0=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ZuJl6Nw2yLUPUdKjxjbqDCn+awlJ/qai3scmm4nYD6TICLQmBUwS8ICXoU6eCMjMajaRZqXNIvvK
U/CG49305Gwo1+Rp4sIQBDVGKNxjczzoHzYZcgQuXM5pobuCUXJMf2dZTxTK0HQpDW/zgz3j5euE
owmt+T8k1E/7laSLO6HnsugXb8dLTiRpT67QAlRJuvH8Bde4+vz0n1jomq7yRuIgF/3GaXqzOK3t
f4P+6aTXt5PwGZSWg9l3a9JguY5fC/PoUzlqg9sWwJRMZNmP08iBOvwbGvCucGc1j9rLQaxEeS4X
DKDXrNYMBe4ox1IyZsvaaJQYCdgmZcAHzF0DcQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7056)
`protect data_block
CwNvxh33ShBivCTFruhNHSEVKUMP4l6l9es4MwS0aldpG+y/wqs6s7o+/99GZQ48Uk0Y21aKl9Yd
Bc/kmp8GmRPG10tH8euQL9SzHtV6rOiKEMfh5kP0PLTJ5yI4itqqcVogzuXb2XTZJ0eFNe4d792U
DM7nPvdVK+v4I8+DlocGayEO4oox0x19IgdeQZus7+u4PV8XNTjSMjpUeJ7/ra0cT85/U4H9POp9
OupRpJl3QK+aUhFXSAkl+KkaWYWpqAl8gC1Q2DrM7sjesO+FPinYtOZUy0HeHfx8f2gSdLmDkGQG
7pi/Vqdd2dfJrVis8/+Zb7l0nSSGYNS2MrURUro9ftjVuT2k8s+0VGZkkB3IEmiy4p9ndIHOXcxd
iC/JU1+e0tu0IEKqGEL3Huy781PkB/8IfgdCc7L4F2AK+Wl3nVi2eEr90MYalX9sRPoMrCk6iHF6
KLSXGtqLzbbLQd1W+oEAIWzPTEn7QjH65qtn397fYAGVgPHOZuNmP6GyzJwk5Copmz2jSshaDueL
0wTXb1wyCoyczOKrVu+LMKpGl9V/6IKVkzrloXiqqiUHtCa9ALZkaxcx8hsZdZL0niLCCI3V/pAd
gowsdjTx1FjagW58KLjlyN5bAg1FdZSeFfqsNs88rtzQA8gcNftcFTfG+uC/GpXYnvQ0PK98ISeN
8bu+pKT/8r3WHV2RF9g8bqQVIjMXFM+S83EeFcsmeq3CWXHvML2bh78NEtcjgNY5a7tI89s/qGWG
YWpuhi6J2Ey2ad/k/2w6pFUKsKWKat6y4t/oKw8ZXZ1sIewRywg8ABm2CAJW7Po3lY0DAmhTQB9m
F1r3fQ2gfNZmCLRnUansMsVTrG1ryWRU2esSCecYFS7qxZZt3VmwWR4VDijrXOsgE7w/Ae2u9Fdd
rECW0ROLaqW6RI/a/3l0LalhHMRJkykeAhaXW49nil4thfFj6swl5cNsXcwVA1zeBU/ekPJOiu7t
crzoBJVfsJHJx0Rd1cUMlsxz0b+lT4Rd1gh8Hme7TwXnRR8jgZQrt8qFP7H2TtpVmyg7VC0Tz4zn
/1KKy/E5EeB82xP4zG9g0ipcjsv5Mw4rFlxoHluqbr5i6g1t9zpFX9tf8pEkUkBFGEHgPzbu7MOD
LYYgaSgZJt6PPZxpJPK6Da1k4TqXXKzEC2VF7Femx5P4vQxCrUKBNJHh26kiZodn3N87e580WR14
NlkjWCyO87vpYVMX3LxFdN/k1V0Aw3VCYd73u52ecpXK2YUKVH6H8idmS3MrWXsUGtM0PZhL1347
LMTvsEx7PdyuW1rMuGHAiunR26nk0MGEbDVe+sAnuTWe0C0l05Q1EStDG6MP3zBK30KWcZMsyLIk
6rk/zS8/I6zHxEYBJ/pNdW05VxFzIBY5TLIrs6MSXhaw2MGrj9uy93XJcej4yItAEJsWvrnnyo2j
4CkqryOno1eTFR0INMmYEaKQ+UdFycX1SDZRgPx6UVV3AAijehzSRAx01kwPmuBbk5RX3/3cAUE4
S9StlmAUdktPzQWdUfrUFC7QfGrsOK7sSQ/5Mt+1U9vLIcmgkJGeZKbOofxD1M6Dy7hrCONflNZN
EnKw5QyuacBOiGhyE6f092q46IGIkAjH1x/9vPNNEY8OZ08bh5OtvghIBcUU0T48524hnu+h5gY0
q6TVmf9XClyPGK0Jmj0lgvZRhyWY4aC+MIMv+SG8IuGBKlemamJEEZuoJEo0lX5FZHbrudXILoHs
QMp/6D4xQxLGyaFFCDj5QrVXyK89noXmBZ7SHWOXFBtzQLkFxl56L0c+7VXGd4k5Odc4MZSmaN5k
e4rtctm0PrDB2uNHO1SU/AEI+XpysEUNl7Rlr8cwEE9ZwG+9PI6VgRJf4sQ5XmJb+5uXrumIw9p+
UvypTCcZ8f3UMXp06tPLw0LwMIR2mzmslCq72+QtTW5VHFhY5PrJcU6sjwEg//MYQ3DbTjasuCaC
1jPaDkOYbbBeq8i+bD+WV3abPczsUp3I1NgDIzDz57vidao0z1fG6aPr91hWecmqoCwO57atRe+A
wedJ8F+dOz9X6atUS8bPGv3vXmXnHKBfeBmBNEgDslZVmTY4ut3GvoBwkTe9ywE1q56X2sBwh6Tn
Em0OSATe5VS8FIx+jm92Kio4VFHKkQK4e+mepPbOls6+o9ecQVZShtgI/UwRfUC//dAAdRd8YVVA
hZB9+6/opVwqv1KtaF9h97o46y/A/eYrpOd1KmVz6ca7prT5pxBF32yToffsEYxAW3ccCxWeHqIX
6jU3emCq8BCzTUf0PI4mYWOWLZ7VmvVlsWjtt7qxAho/E9/lTz0u7TVvPVCrSmKx1GKausXLcXh8
u/AsYftnme9PE90/Tk3Qk+mfZxrDGqG2fqaQ/3GgvNx23ZP/ST4yCVzr44xe2TduNMjAfQZeBxQA
m+vzhbk9QI2yKDflO5xq2dNqySk4CcWTxDwRMOOPqTvHcffOBWhVkoCWoJfeKousgFDx5zItzZlt
VzvhVzh1j3DVle9XisrArA8a1kvTanM46khnTQMfBz0NdekG/suLIF8uuBzPtg/TdN43GHdpBTQd
C+LfXsDsIF+k/QAN9sJKD8BNhN6W9WxWLc6h5c6OTRZ9nRmTQCr5yVs1U0SSm1GAz9tK82buQ2Pl
cfYAa+JQDlb2MnH5q93nJPYREJhJ75+cvVclXqk65JfMRj1SynZjWt43a/yi8GKjaqZEx2D4CfCC
IutGwBRwLJ8mr/w7+L+hpQwyiw42t37E6+xLb0A5QjD+JgfjdOmH/Zl97tyZvfzEadNrL1lsuCtL
yFsvNmt8bKTJCakOkjMRZiCAeme9zwR1pQvSBHi69nUDVYnPd6A+7dy0zbOJKnr8LdNs3+1zDkzw
yugxl9du3C3WxR09K2VTqNptAN4mYIJ8g9SByBd982XPGT6YLQl4qfiefIcKNdgl0z5isEbZxYzt
oZL6wmn9gQebH468XoaKsdSuYRx6kcfQOs4cRBXTx7A89nig2gJwJi/xS2qRyoaxzQAzfXf91CZh
KRqbqg0UswKrVMzrxQnDNHr8MsUCUmFG8vZktkIlmSb3S6Z6X/AI6ln0Oy+GkrCYSFosl2YW6IrU
Ze+C1tVRzxZ+MHjhkIC6KBFvmAEl0zzr8fFq38DED1A4z8CHWSm//JCGVKqvxb0Gqnb2VEfE4kEV
HTEGBfMyJtVMPF5rgJpV/QkbjA5QYdfxTjYDJ2Vm30LsIwBibiJzU/4V0awOnmTvug9mzZd3jA5h
8PPiDxZSftgn2LyW7IycYUkrje55HDSAUuLNmQeLJioQOt0YnfJKjIMpEqylNjjJ9FcZaTMyc1fB
pD8v/HhETNToHvNpjJ2/TVi3p2iA0UbhY59asEOP+Dnjb1/wV8fdN6w1OHb9brsnWQAU1Oe1PuNp
vXcXBPSaHg+iW+OYQL+Y2euivfeANUeLh7NIKCU+G6KwTt6tt9U/KXcWG1x4wt/bBvBTKk3Rk7gN
bO8M4XfyzMrm6l0I7c+F9duNVgtr2mIJNigTxhKYQT0bdnPr2j8ZqpxYlll+07Al4Dyav0VYrtPw
PT6Xr7WkJKGvmrB8PaRtP7hlMZIz4Wz5BOAQafxXFysbZcxWh0MP8Xsq5yvNlBSexZOXSolGHrFY
joxdg7AKVgAxpoDYpYDQ/Y9OUiTBL7rbpN8xKy0/o3NzCqCqqVN40u64WaBQ/tOBfkgb17z/EMNR
Y8VxHst4k6JNnDhUGAyAQvp1VqbTu3OFUFiOdepnT4L/0Stddv7XqU4Cim7Oa7zHGBIPJn1ZvEai
gvF79l58NX2d3ylUzoDW2yjo9l5SFZGmAZ+OcXEQScR/tUu4YTdnMT5fLKlEnyuKww3eHQ4k6KB6
225qK1frIjsAV9iakdZlrPLfXcHhbiIi+hNfq0eyWQ4w98c5A/aiiAugsvuClw9XNtjtrsfoEvf/
0MUzYBv2/ockRsCvipq5AI0UuSQTBugzSE7zgwTUIuawPpv5Pygo6nYqBVmzFC1yOvxPVVAovmAN
Qa7tbzvQV5mQLJ3DNR8GTQ0JL9bZK+ZtPglML81EAUb5kKnNQnjMlefSzkGsMZLFaucssz4NRtwA
u7YdmoV0udOiRUVYWx2zCbF4HZkDegOhEtSE7EbhJni4IuqWmC/sfDSIIq1uGvUi2+YowZlGwJ1E
VYyyfeoTp/DE+aqO0z2vOPK9+I8mDKdM+GxVEJbxoge3VSg549XCXBcQG2MHxvp/+FXu3p8QIxlx
Jid9zKoQL2StMpZy2LEwzcT5BCKYq+rmxV2pNIzdx4CUIrXgj0Dq4wdbFTfhEJYnDE2bT+B+yL21
QUFVXB0w2TsC+rxNJN8AXjttFxUgR9LWeNFn8Fqfq8wejeK/KsxiZQx0irhhctMgI50JVnU3yjC4
J6VE/I+JZssK4+teA1cW/lLPDZTJpZKBPANySHRw3NV71dFA+qquqqTAAD4LGyx+M0RepzualzSm
T2ntMecTMk0wPcL7g5QyW5EgYOx3lGR9DXApQnFPS4Qg+T22vCKCPOygZpd0GLhn3cMerflQ4rg5
Hlkq5T52BmO0YfVHQ9gwvBeh/COSDnsWfyN9lkI7c2PHp8OuG8h0k/BXSjHPO4+NRUY1IZFyftZz
oE0qP/tk939Nb02dqUznmpJty4P0qKk5B2lKhKscms4L/v0y4wmN69GhXaRJAbizBGTOi1k4OhUE
Hp8zSAI5M7MXxjLZLXld10BCWyTku33/CrAir0UyYbdadUQz7vwp0A4UfFqccg+lvki2EZaWkVek
pG9a4XMhTvFcDj9hFitTGlFZJEfQm6EXKxEcTy365NLylmNJB/6pU77f9YQ4a060NBWwCXIO8yuJ
2CI1OJznxsfg2GwFFhaA6NUaUJx3luELNLMLDsmyguv2WmUp3dVfSPUsmBB8r61gPJ3qxFlfYzXS
CRMQJDClOBfo8JUAmcq8RupuGPgy/OhEzBJ8QW9X34Q/q4FnyJjulbjgiDl6E8QXH7gwjv80m5vN
Oaykf9guWVF52lPxoLWh9UKkXg6aGDOwG+DKvbQ3zyiurKOUq5wbwIrKYhWHI3QQ6FW/WAsELtpk
ONdyW6K7YRcA88eJ+g7P4RR7eBwbFz41QRsfodn/7G/DYLkhdqkAeETzIXt77/FFDJgj/NOZu3cl
phuk0nPfZaI9StlMIl4uZnYA92l14yMFg1g2Z1tenx2oXvYYqrf5tOLpQIGq5Jhd6bfW/S8o/+tQ
ZRQKI3P5LT8Gz23d4xqqlzsUKW6198/w4UG9PW9nI5HW71BqbCFT3tNsEwLismQG/sqyntIAHM00
AXPVhWTnn6T+kJHS5oQHse4F4Oen7hCjOzBUgw1Id3LYJJjN5ZqDg8MA/JQdusoh9t+5IqWYd3bu
NGgq9MT9gx0P7rIHPRoaAIqtvNzdg7g0BdX4m3IxH0kPmR+jjgXbrxA0F0cPfZaUH5ViBX/0buLH
Qczc4D69zUTXcYprtd52MVxfN/YHhCLVa6emLDenQ2Bxk4Gteftm9KG6ap6QdQ0/lFTdQTSst6Zm
oeumiPgQ7JKxe92JMhaaLnjoT6frCgf91ECHTkP9iWfBkkH5OCjUV9FKeXgKeeV6j3M9AVFi1ZJT
ESgCfeLiNudcKe2tzNaYcvPTaNR0+9rwwg3nrPUWHWtfvUM1eC70oNBLK/MLIEWTVLLQ+ZOnTIaW
kIR3xH9zNavnNHc9zxy73YDJ3CNvcZDPDZmxOfWheuePLorTU+P5BG7j6yzKC0yGMbr++LMFJHF/
ep9LiTUOS5Tux+R9qZgRDSEsnTGNag3kX3e49hK61pZprIpS9nwXtzpLvjP2joTKYUUZYiaV7PCu
FKtyZyRjLzvhyN8YZxquY5MbmEkHcZcy1Y+y1wnR0PHNZkfKdbC4r5xRCqQyVl5Yzizw8+nQQPKa
AT4mRkdwH0zMw3DckXMx1AQNvByFfKHHR1H45vCky6emxflxsoO3Ul2J7klwYyAN+tu3Mffj4q7L
py2nhAO2bKrw1qIaNIW6UMJI1Eab96g6sXlnqHrKHs+bYljtVN7BMMZFMjx58Ub7voSQUTEF/R+X
Z2qaGE1zs6DV2/ryEJtwjDtzYMKVeRjBROxxc4N4VWYUqXWACbGRdFYawre0o9rl+A0/ktQsfG9x
Ao55py+ctTf5a80t4nKnQTEvb+9mYMcTvz+Uf9t3mtrfViEw8ipHiutQYLvOf0NgE9lrw+3UHkbx
/2RW8bk5si3kDwKjVmTgqjwST0ZNNAQTrM1LIDYM/PDkTK9N1SW5D810MdS8vvROry5xaD/lDIrl
3Ou6RhNx010KNhi+dDudsHeaQDyobqz4/l1XFQSXIVyDdC1j8toY82Z4IpV84zmkvO3YrtjT+mep
SmQpe0F21W8yBSLubaxuPEqjKD7lRiLXTdtIXmtFKbiDHreB6ZzTu+W90G2oZKci05AibLC8O7L0
C26ntxIzD2lLNHKx+TPDIJXIcMA0pCb6tRIQJle0WuvmRrPq+AZodvF7rfefCaQFFexkYLVT4K6E
xU781NFpRenxd4SZuysh0PQ1G93H/xCKiEqi66/W3nTcUQZVCKQkGJ3bz3vlSdWkVJBue1K1TMOT
ppozr8Hkw494T+GQoMwWRgxr1iVFEBP4Lg3RzXyHPqh1GTzktH11kc3GmAZB88m76UCUbpYQEM+m
7cfrZNNYobQoVBAr2yWvS/E1R8iZ8JfU5iwdjxaiucxr5eWDQvdnjDk69QiNlfDqvqaPhpzD7tt7
D/2D5arcRCwZm2R4PKvSAHwHrnqlFRaRRrpesBtHKSTVsHOz48kN11B1qenuQgggzB83c+6+m4hW
kB7FyQ+zeGzsuAZdcLYdzMd4NvWavom51uVDKuwzS0Ewji/t6DUrGbIJSdL2Hi+14SG1VfQ1yz6+
0Anp3AV0rKf6gzygOZbFh7ehW+tBmmUHhcZ/tPcnu+5KjlQVkjYsWL0ykeEcS5zR+qCibEduKF/L
wtXcUOMoFZkgmIxqGWyQ8VcJbknzK6MQA03AWGpAakgGAKbZ+DHW5DCPgJ1IjPl8ukxN69WcLwcO
HxkD8T0X54hIVnPEDRXf9jIur2C3YWgPyrA2JsHbbfFJI3h1D3yfA+5uwp1NhDRPsqlUu3IA1KQA
Je8+OJo/Mhmu1zjB03yYqwbzjUSji5cZ0aeFOH25ZellGsto9MWbloRcyVyXDSVAN0y+7UYswYT9
aiwCjgyk7iUVREoeRd0Lz5OvNXFEXnf2ApL5oE/SR+1hRIJbSZzzNhNSXQ5AK3yt8F/YsRqvn4mA
/J3FIVgtuyi4bVwcbIVEaM0jniVoYuygQAgMRpvnZeRgq6fmvIWx1L/YDVOYGk4LeIKmbWWs3pBC
SiENdLfOlMnkhbli2QPbGTCJjPuCI7FSGnPrANuvO0rfu6+TZJzrUWRjs2fo+SxDKBr2L2fnHd0F
BtiwR6OoGIgCESytS0V05Kk8kIFPzMEyzXGEZad8PTgIPmsn6ZKUYr9THPu88fjKUiLnMuRQutTX
wVyfJ9up32cS9+wedzJiQK5HRKk4PtlCvQfOyJlZuRn7RCCv9l6MxKTW1Rz9AEW6fR9G8Mog5hGW
z4HpLPNXVwPPN8W3o6Z2K84rWjgYpN7qHNyLThku+2z4iIEaNpmZH4mAbIM5e7srdUKaq0BRj1dx
s2mymO4nxdskN7A+QdCdAFcrTookr8ohRciTJuamQ0Y81DFfe0LSyowLzO1BkTvMGnyMzw7Jpbc4
KPSfVyQse417s2r/J4hXxcGcsG15lVhD3aaGmGzTv1mcDGYr7H3r80IJwZoOeBfnBpePZowWoXZD
Z7iGjvgMmePMMGmUvfkE7/CpZSVh8wFjJmEGqvafr1riCAE3jApTIid3Dq7E/l47JVBFIlJkkXBR
V16Q4NwZhDpTfgGDtF1RcSSyIHMb0KDj5pMYgDsAfBRgK0sSWsd7Y6ZCdLOdfcxSZw5apUyr+ZoV
KsgsipORP5F9bXDYumiOP9uhl+zVVw8PB0+2DdvQPNRV3RPhSHPUoc82dIjgnjF6B18Yx7DN1BGV
1RVW2xtJKgk0fMu8sUk8q0EBmv3gutLvA5W8jSz1RCqqMHouA2qKj4zM1wae4+dFYRicWJSfFfy3
7yXBpzLl/NxC6zElGQOigzmOA7iptDzt19ThUBzV/yhCUGT4qU8SsyAsZ5mOpW7YPPbhFCm8JoSN
2WhEqCVJxpAV0UxZc5mnpHSz0nX+gaojOY2Q/ont2+5LoV1p0BZZHMLNxVrnZODsriMJ9Okj9JwS
yWe7wMQCQpS/MM7AqGSp6Ged8kFs0QdfFv6Oz8gw3SIT5sqCxrrCcz/J9p6abe/hhTnK3t5VNp/q
nDDXdiDF186q5jqBApWapPLfM+u9lfau+pBB89vD0Fj3b+eYaaaJNXc3ad/mx9rxN/nMCc6G+67w
108/4FzDKUtg/okDLCk+dqHO9tO5HsFg46jLLpW9iFeQmTVjksdRcNRciaO8EHE+CfynBrhQCM7P
WyaWHAc/PJLUSYexsEBp+Tp3Rg7C9RozH/MHhzkppyZZjYmI+CVOUvYawJV10XdTKwAqzZQZgiL9
1ak7gB/pqunkPjrrlnH2dk3yjDLrPdaCF3eIgpFgNhiausk6aMfXQZcV4AbHAKv/JEe6/Fu/judk
iqtIoVb7ubf8y5tkSnSk+1TrtA7a/F3YHbwBtMoCmO/Ru2/wc1UYkAoS45FpvmnM36Isgkwynnys
AdlllNvZVs/Z4a6reSv0g5g+xXxCobbSZEKF1tBG4U0CQJnUjLZ0dX6/lJkBHsYVktw8pIX4Ce26
ncuZR7JOkXFu9XI24S9fVQmaSJwo4nrGckqR6ojV1Os7tNWhSiAgyHRZAHQyBxmVTIT1gEsjm19f
2V8LKyE5tYYAVRj/CWuT/WVDFizBBxdIQ5IKGQ2tZBic8XZFD3q1ZxovdUpheP2Vt/b8Muc6Cjsi
Quy0kb+mlLHt0Z6xFTEgzIN8QKiI246m7Vx/rZ4EGZ42Fl4U74aFgKqODMFDvPxfqz21P+pvA8rx
Ets/MB1doBrYgPjUuBtNbEUUbVoVSko+ODVeiLUz73+eIOqreyNDJFx6TUobtO7wfJiVPPyKLIva
zHE5/br4Jn5YaXBhaLcQ5cntYxRFe+Rc6EwPX3uUIoCdlwBLdtXSyotegiGx77yPRyciX72Y6E7v
WgbD+6rEeI5+sTlqeSucoYpdvzQKfVUe+gfRJn2DHq079in8SIv/oqB4BqArjoWb0eLv5NAR46Wr
lZuXHc1D812ChjTEQtt/VwQcqHKskooD1C4rCVIPLSMXPHKu4BUklQUBsEudLmCpqGGOFLJsv0iZ
F4vqSEhtKwWn+hFUjnmDTRUsrqtdU7iCyn2RPH2s+F/BFDWQ1nhGoZ0vycEl
`protect end_protected
| bsd-2-clause | f92ddfabbd87d1e1d8fced6fa9ca0a86 | 0.928024 | 1.861912 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/generic_map/rule_001_test_input.fixed_lower.vhd | 1 | 598 |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : INST1
generic map (
G_GEN_1 => 1,
G_GEN_2 => 2,
G_GEN_3 => 3
);
U_INST1 : INST1
generic map (
G_GEN_1 => 1,
G_GEN_2 => 2,
G_GEN_3 => 3
);
U_INST1 : INST1
generic map (
G_GEN_1 => 1,
G_GEN_2 => 2,
G_GEN_3 => 3
);
end architecture ARCH;
| gpl-3.0 | 8ad6cdda7792e98ad5a80e0e9026584b | 0.438127 | 2.718182 | false | false | false | false |
Yarr/Yarr-fw | rtl/spartan6/rx-core/decode_8b10b/decode_8b10b_disp.vhd | 2 | 7,625 | ---------------------------------------------------------------------------
--
-- Module : decode_8b10b_disp.vhd
--
-- Version : 1.1
--
-- Last Update : 2008-10-31
--
-- Project : 8b/10b Decoder Reference Design
--
-- Description : Block memory-based Decoder disparity logic
--
-- Company : Xilinx, Inc.
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
--
-- History
--
-- Date Version Description
--
-- 10/31/2008 1.1 Initial release
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
library work;
USE work.decode_8b10b_pkg.ALL;
------------------------------------------------------------------------------
--Entity Declaration
------------------------------------------------------------------------------
ENTITY decode_8b10b_disp IS
GENERIC(
C_SINIT_DOUT : STRING := "00000000";
C_SINIT_RUN_DISP : INTEGER := 0;
C_HAS_DISP_IN : INTEGER := 0;
C_HAS_DISP_ERR : INTEGER := 0;
C_HAS_RUN_DISP : INTEGER := 0;
C_HAS_SYM_DISP : INTEGER := 0
);
PORT(
CE : IN STD_LOGIC := '0';
CLK : IN STD_LOGIC := '0';
SINIT : IN STD_LOGIC := '0';
SYM_DISP : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
DISP_IN : IN STD_LOGIC := '0';
RUN_DISP : OUT STD_LOGIC := '0';
DISP_ERR : OUT STD_LOGIC := '0';
USER_SYM_DISP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0')
);
END decode_8b10b_disp;
------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------
ARCHITECTURE xilinx OF decode_8b10b_disp IS
----------------------------------------------------------------------------
-- Signal Declarations
----------------------------------------------------------------------------
SIGNAL run_disp_q : STD_LOGIC := '0';
SIGNAL run_disp_d : STD_LOGIC := '0';
SIGNAL disp_in_q : STD_LOGIC := '0';
SIGNAL disp_err_i : STD_LOGIC := '0';
-------------------------------------------------------------------------------
-- Begin Architecture
-------------------------------------------------------------------------------
BEGIN
gmndi : IF (C_HAS_DISP_IN/=1 AND (C_HAS_RUN_DISP = 1 OR
C_HAS_SYM_DISP = 1 OR
C_HAS_DISP_ERR = 1)) GENERATE
-- store the current running disparity in run_disp_q as a mux selector for
-- the next code's run_disp and disp_err
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK='1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
run_disp_q <= bint_2_sl(C_SINIT_RUN_DISP) AFTER TFF;
ELSE
run_disp_q <= run_disp_d AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
-- mux the sym_disp bus and decode it into disp_err and run_disp
gde1 : IF (C_HAS_DISP_ERR = 1 OR C_HAS_SYM_DISP = 1) GENERATE
PROCESS (run_disp_q, SYM_DISP)
BEGIN
IF (run_disp_q = '1') THEN
disp_err_i <= SYM_DISP(3);
ELSE
disp_err_i <= SYM_DISP(1);
END IF;
END PROCESS;
END GENERATE gde1;
grd1 : IF (C_HAS_RUN_DISP = 1 OR C_HAS_SYM_DISP = 1 OR
C_HAS_DISP_ERR = 1) GENERATE
PROCESS (run_disp_q, SYM_DISP)
BEGIN
IF (run_disp_q = '1') THEN
run_disp_d <= SYM_DISP(2);
ELSE
run_disp_d <= SYM_DISP(0);
END IF;
END PROCESS;
END GENERATE grd1;
END GENERATE gmndi;
gmdi: IF (C_HAS_DISP_IN = 1 AND (C_HAS_RUN_DISP = 1 OR
C_HAS_SYM_DISP = 1 OR
C_HAS_DISP_ERR = 1)) GENERATE
-- use the current disp_in as a mux selector for the next code's run_disp
-- and disp_err
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK='1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
disp_in_q <= bint_2_sl(C_SINIT_RUN_DISP) AFTER TFF;
ELSE
disp_in_q <= DISP_IN AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
-- mux the sym_disp bus and decode it into disp_err and run_disp
gde2 : IF (C_HAS_DISP_ERR = 1 OR C_HAS_SYM_DISP = 1) GENERATE
PROCESS (disp_in_q, SYM_DISP)
BEGIN
IF (disp_in_q = '1') THEN
disp_err_i <= SYM_DISP(3);
ELSE
disp_err_i <= SYM_DISP(1);
END IF;
END PROCESS;
END GENERATE gde2;
grd2 : IF (C_HAS_RUN_DISP = 1 OR C_HAS_SYM_DISP = 1) GENERATE
PROCESS (disp_in_q, SYM_DISP)
BEGIN
IF (disp_in_q = '1') THEN
run_disp_d <= SYM_DISP(2);
ELSE
run_disp_d <= SYM_DISP(0);
END IF;
END PROCESS;
END GENERATE grd2;
END GENERATE gmdi;
-- map internal signals to outputs
DISP_ERR <= disp_err_i;
RUN_DISP <= run_disp_d;
USER_SYM_DISP(1) <= disp_err_i;
USER_SYM_DISP(0) <= run_disp_d;
END xilinx;
| gpl-3.0 | bd124bbf17aaa3940ded35a20299feff | 0.482754 | 4.166667 | false | false | false | false |
spzSource/MPFSM.RegFile.Sort | MPFSM_RegFile_Sort/MPFSM_RegFile_Sort_Design/src/RegFile.vhd | 1 | 2,707 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity REGFile is
generic(INITREG_T : std_logic_vector := "00000000";
ADDRESS_BIT_SIZE_T : integer := 2);
port(
init : in std_logic;
write_data_port : in std_logic_vector(INITREG_T'range);
write_address : in std_logic_vector(ADDRESS_BIT_SIZE_T - 1 downto 0);
read_data_port_1 : out std_logic_vector(INITREG_T'range);
read_data_port_2 : out std_logic_vector(INITREG_T'range);
read_address_1 : in std_logic_vector(ADDRESS_BIT_SIZE_T - 1 downto 0);
read_address_2 : in std_logic_vector(ADDRESS_BIT_SIZE_T - 1 downto 0);
write_enabled : in std_logic);
end REGFile;
architecture beh_regfile of REGFile is
component REGn is
generic(INITIAL : std_logic_vector := "00000000");
port(data_input : in std_logic_vector(INITIAL'range);
enabled : in std_logic;
init : in std_logic;
clk : in std_logic;
output_enabled : in std_logic;
data_output : out std_logic_vector(INITIAL'range));
end component;
signal write_enabled_flags : std_logic_vector(2 ** ADDRESS_BIT_SIZE_T - 1 downto 0);
signal read_enabled_flags : std_logic_vector(2 ** ADDRESS_BIT_SIZE_T - 1 downto 0);
signal read_data_1 : std_logic_vector(INITREG_T'range);
signal read_data_2 : std_logic_vector(INITREG_T'range);
begin
WRITE_ADDRESS_DECODER : process(write_address)
begin
for i in 0 to 2 ** ADDRESS_BIT_SIZE_T - 1 loop
if i = CONV_INTEGER(write_address) then
write_enabled_flags(i) <= '1';
else
write_enabled_flags(i) <= '0';
end if;
end loop;
end process;
READ_ADDRESS_DECODER : process(read_address_1, read_address_2)
begin
for i in 0 to 2 ** ADDRESS_BIT_SIZE_T - 1 loop
if i = CONV_INTEGER(read_address_1) or i = CONV_INTEGER(read_address_2) then
read_enabled_flags(i) <= '1';
else
read_enabled_flags(i) <= '0';
end if;
end loop;
end process;
REGi : for i in 2 ** ADDRESS_BIT_SIZE_T - 1 downto 0 generate
REGi : REGn generic map(INITIAL => INITREG_T)
port map(
write_data_port, -- data_input
write_enabled_flags(i), -- enabled
init, -- init
write_enabled, -- clk
read_enabled_flags(i), -- output_enabled
read_data_1 -- data_output
);
REG : REGn generic map(INITIAL => INITREG_T)
port map(
write_data_port,
write_enabled_flags(i),
init,
write_enabled,
read_enabled_flags(i),
read_data_2
);
end generate;
read_data_port_1 <= read_data_1;
read_data_port_2 <= read_data_2;
end beh_regfile; | mit | dff01dc95989655bc9b72bb29ab4473d | 0.61618 | 2.904506 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/instantiation/rule_028_test_input.fixed_lower.vhd | 1 | 823 |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : entity fifo_dsn.1clk_fifo
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : entity fifo_dsn.1clk_fifo
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : entity 1clk_fifo
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : entity 1clk_fifo
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
end architecture ARCH;
| gpl-3.0 | a0907be5a9fd34ee66fa5571e529fc77 | 0.484812 | 2.707237 | false | false | false | false |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/fir_compiler_v7_1/hdl/calc.vhd | 2 | 32,500 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
fMYhWOVUrX0VGEwVQ3NerKcEc1JmQh22m4uBM9Y4cl/MgDZ4V+o0BonAp95wgtMaqvpbJUxpiEeV
bEzOfQE3vg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
aD3zR6jRD/NfZQJygefshEqFgxxtPwfMxNgegE4QGrDgrxfvrdEyfxkGSMvFiszefrWw0fDD2NbK
gETTapVxuD9RJbvVfGtPfx5fkiXlOZpu+m4BZzSh+aCzdZofpkDqO9GWbyAVgkKIVKWPtc+1Whtd
L6AjxHD9MnmMR4lN+Yw=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
HJFTygU5tm19EZkAAw1bll+umYyCOO0Jf70Aq3f+tQVOwGoXLSiCK2bO5K/jybQRlzyyL4EPTGfr
Tx/USaK+qyFFmZcxJCk6llz5AiL2vVve4sU+Rgporn15MHmH0th3W/340dp28beRCVtqOWmB8wGj
5MQFp75hrFMNJS/yWjzRgXzOsBxtEiT+iaqVuxfjSkqQbWyfeCVcYC1mgsJ6QlHSEUsAnCJguWNN
mk7Fckf5P02eSZOg85w4PbCbf16zkMZkjBraAT6yVsImY5NY9gbiuJuIZOlURf//7QVlcEX+D9in
OlRKeYQruMEuBtHl+L8GuU+1zNkZ/VwWL1Ze3Q==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
VxZRtFdf272LJPXv3QauzWxelq9iJsRyOP1bET+dlzLzBnMhKo+mfFqprgnJS8dEHArKWGdbYiiq
aIbwew36hxBy1OyTK9pV1Ar336kRTqaNfQwKM1ly151IscWImXErTpzomNSbr3uWpQ6C51uS+ukp
j6TVtnusSTDBw0eRbGY=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
rGqQYUTOjnNyvO59cHbKCD22DRdNiewwDvzYPlia3RERxXgfs+Tvo01vnIvmkD0KQAfRpmFt/ddR
Rla4+7Qr7I6glHf7cpfNDMujsHInC8BOl39PDn1DkVFFI6/ddGDSwV65OzrgwAnOrLwIjmcM6qaZ
NT7CfEBeA/xANu1kfYkRZvB4o52lQMd524SCcKo3BCCNzuHh++Dxcns6hqKFQ/zpezVAyUDaUPLk
B+C45oTAb4gvkCqLVw2Fq/KU7RXLrHqH7E3NsKyD32pV+IF6gqJqlgwQcHMT+XoA3kZvTfppQzBK
Mhol24ibNzO9FerFdlhEcf5Rsb/6GG9kdHvrnQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 22320)
`protect data_block
oT7MR9BbY3ZXxsZpbZZsRNdFdd+yvleX7wEJsj/Xp2MTP5sXLDxHFp7IJSOgr6Z+hr9OoNOIs1mx
3qB2bQziaPOdxrRVsHVNu5eYxkqYbn6cYuuWq7hG/e2ylXYnHAAt4H5r7d5R4KamI+Vkxt63weg4
bST67ynxf69YnZZOCgVebV7Zmq6UhJZUFJL2qoN6Z6BA8RmXUPbo04TikGh5cej0CbaSijJoULpG
bRBD+vClBzki0KMBV1dPLWfTy9r5adejoFB6yMjJA2BCQjigKB1GIsSkU9dRAldwn+fi/cwqAo14
JVh6KUQgK+0I9NL/Ef9xbiv/m+4PK2tBjiaaNYhMWe19KS8r2T2iZlvO5cM4uYWRvKnldbglmQN8
HziM/K3OVRUT1b1lBZl+8gj9E2NXYyWlx5gNdS6KFdjRs0dLBb768pMilsqaQc2tJTrx4WEXPZBa
RJwvIlfudv16fa/3Q5S9VrzVH9QwjnWWt5U2zmFn4eA6xmIqiqB+9JktjshZGM7h+A916cBUPeix
OvgmFBQbFpUlNSrFCX0LGQgewLDn0fL770DlI0Hi6q+UjheNxxGx8+/5RxB7Yv+6bgCtsewyRk/Y
E2wJKO7WM1BeiAt/e66QSsEfkK4BF6ne+KnzcCmWo8/Tao72d8//tJU81uXjWavUzqi8q9eymz9d
ISM8HZNp9zwIIpxy6jaekwFwds+HUY48EQj0TjsGI5nuCjYemqfX9/R18giuhT45SHnPfNdCtP4b
VCjpJD70hWEQCrRw9hseMr5qnLbPe7GnjbZ0KmkBUyuvKcxqqMhjWjnG1s6ZR1QU+LjsBKbM1Qoa
AHjpx0XWGIpuv2lY0p0CcVmfKNDaykBZ1Rg5cSM/djNJfIeTCEV3qQbfEHYvmFkLKx8Zt1Nw6ox8
bVdiKyiwDjHl+Ye0hPwnXrF3itf2O6Cb4lDPggkWS4byckwoD4uXj7SuOUuX0dAq46quK02zfJsg
amq8RBwEQ0B7+3YEqjI7utHykkOxN1vPsfspiC3eL+xpJGqWQ0q0/B1Nz372AYJ7pQFI8HQGn/Bx
1AAVcPoh2Jt2oWwUr9GsLMxm4roj5hv+Mc9QD0Nln5SguEZfJ3KcNliGDlLFPJ9/uUB5Q+iN1Vwd
By0GaDaSZYQ+Kcu/v35htpX/AGiYIdGOhhRZPM36JtB10rwZaiUqRAeDkJWsUbFdYUXdyZzVi0ke
saxjoYbOwUepU1HI2l5FSXXmQx4BxkvnvGIPiD2mBQ6lQtwQdbO5P6ukqlgBKjqeGURVhbD+EMyd
GzIvraxjRkmyJ4zF0YZqCQ/1CjS2B96f0I0FJ32T1Gv4OInsntXU7p2BLIUCj1Rr48SnrLUFtrh4
KjeSBHDvKLo+l1kxW6IGPebY0P4Kyxpks1v4w3mzq74tYZ0iIaU0j/ltVGT2Kl4EP7MK7CqGxWLL
MXploRJgR7v699cwm6RaYKVHd6BvoKEkuINjfeoVvDFy2WL305X79E0EKnVVsITa4kvEYkDF7sae
I343V2YfTLIcTuXiR0AQ043uH5M0nBclgvzWdfmeP5Lqasnrdk5CXrXu/c5MkDtcJU5p/25dPsI/
clZb3OBERa4eSmVHriuzXD3OgTMv3LFvTpDXkbOKmjzs0mcsa30XzBTLTEMuX/MtoK6yrD3aIO5Z
KJ8JS1O21oHmOMcWNQMKrtMJH+x8pANTpT7i/RYCAW2n13f+Yxe7o7pLQRzAsAKNAa2ubh65OhS1
L9z1rfAMWN0GkzOykZWkbgq+uG63BFVReiDntQNXIW+S1IV+9XVRVTPPkU97jT4v04SD6L462UIl
R6naxELADABNOBiYBSdgo0LZrUr+XK/MKlUPcd34lqU///rrFIo86fGL/8MV+3kqqbWkzqX+7tfi
Ka0zPMA+D85oeiwk7E5NPAQWjbkIXESNuBpTrhvYKxjI7C4CQQZ7MU3zv/HKOCjcaCdq0rZBCkg/
J+zA9ShGi33ipcs6mOg0p8PWWcaHamo+jJYUhI2QAWRYNkp81qlItwvef6P8VpyCAnkwfUApA0En
6gLogYYTyZm7U21v/wekkskTkrVfyAik0X8T4dtYSgRLpvONmqYDHON1FdcZE20Rs5X1XYwwbKuv
08bKvPWEWW1cR7I8iFR7gA0Bt9lS4cPI59zc6FWzuF3b2Rriq9eNShFGaFr+wZRRo1O4po28vyt+
cOF/frMJWDTUfXI7hPrqwAZYb/RgPVMc1MWnDdnfDJfmTyBy1HZgw+MQQwzpTyXZH8q8x2BwRBJi
5GFvcZh4mdC3qFL1/bxQmWDoXtx0JY0NqXvEpTW2oSJ+Lcxgk9++l0YhC1SylVxraPgszPxg0uAF
A436OFnf1LQP0LTD6qh3/Thy95WEulsVZPqB2ipeLhYpKv9YvQAn5KtMkfyqL1UOkp1BFULEXARs
OHZYPSlMUBUU9X1eJGX+4VrVBFoP1BknyKa7LVi29djiMRnX/c+J8mGKBkMKag+FfntaiHEMgNPl
GT8s6U+Or/olmaONLcBvpFdehm6+m4TI+Ohl7TL/GFYEdL4rVbnlPLAJDvOWj6JFQ6edUPBX9rQF
dFBtNBEPbx8FQTUBoZDujqO+7A8AQXkPBrnJ/ZE2Fq8HkBFslbsfKzm6WWfb3aIUHRDchMcxJvcM
lYbN+nc3LKolkpkzBjEc6wjxmelbsaXVJ373IHlw8QED44FDs4hlmg8ndrqRxMdrc/jNdOE1wnTA
9h4bbD3X8/LWN6qrvisDdWovyTkCOmxIGOeoHbwAnwRev8lyJT+PtKToOD97S000p1e//9rlAby5
DfpWemDPIB/bEZQ47AbRsCQSziP4Y7WWw2vlWACLNP0C1tx3zgsFFOCj7qQnL/y6B7XqD7A8z1at
ADvTJe7yS9mPK2jKCcq6JYvxeZu+NETToMlHloSgQ0i50UlrbAiXhjKRu6nq6Ricn1cOELYzgwg9
UuZ5hgtS/0iLGH4hUfNtoTbBsO8o4ZgK1JF7KWu8bZojbq1HdnSieNDV4svr6Zi+IPo1nHxu1sAY
L9T4KffnO1ng1xMa19djZI2Lcz/EOTKoRleK32UQTbpd4Z002KRVCsvLCF8g9fvsTBBGawo6uPya
Zm+WAd0FBFfU9dRrhynIFabGppqH+WF6k+YgCiTcjeGQU+0Ex0AZCw0zoofrxaBgG1tWhFowWEtz
nWVjdoEZ21814PfGmOp6CNQ3M63rmlSWr2+wYbr7u/gQKRfzH8o8ocBJBpdyc9SBBySxay3ZdyAK
c4UQnVjP3DEDBcGyxbMAo2kT/NiOR17MUZo4B1HmcDS8h4i7VF4r4g/QgZlgxLDqYqsO5EjGim1d
sWEmmUwlEmBXx0R/NhqhlaxHq76uqxjIeAYC80d78ZW0QIWmfdSrI+lTWZszYJIQ0oVKZnSdSUDd
GVPSLI46kMvAVKorWTe5WLS5TK3P9aQxk3J2ewpov5uKgcAGiD7v27WhWCbL7+foUgcz5fEz+wpp
TAcAZtqFKs7Ltrd2BwZYtfRNCcJB5Ri60JSbGXS3uzkH8xLqHJcCcdCqoGLfg1f6tCzpjc9WSdnY
n1Alacr/s2cggkimk/qDO7B4tq72yT0ZD/itT93ydQtrWapYnbRKamNcGd+2a/vXPfSpD8QsquRf
bcqOf4g5UgKZjLfiIWK642NY/imnW+Nc0WES6r6BKmiuj4lq4ZdpXrBFfEYrsR19fT7UXi3IhhEm
4sHAoWsWvfnT7yH2t5FCJbZa4AkxngVHLGUtFiwkcMt/SE1lfwEEsswOCjrOJb7AjP2S+JI+yFC6
DdrBLmoYHTCUELmpMGIMR58S+v03g2D395ZNIN4E65YjjVIiomYWRcUK2GX9kI94mypIqr42i8K8
I0XGNzpzgc2eq03R5Teho5A0IDTGhthDC1iv/iAIWoO53Mci/0PG6V4NoXgG7+CCxV+EaMXbH5He
sX7Sl5NWAeVmPtFO61v+tYAIzxv3QQqHj9kjprrHwdCRUevskT1el+GpVlaaoZe6m8ITkHpOfM6u
XSyQc1O8n0RHo3Spcw1ArX8AaazGXit4AnzPblpAOwcArbNvYHnX6+6F5muaUXWvovQwFboJLRpP
kILPg+U8ECh+zaLGRaWXcd/b5tuC+ZtAYigjLmH/8xELXNwiMRJsMkw66TbiHVq41yV1U6ceTAeU
e2WwzvCrb7kjO9C1Aylmk9E8YOqXAThVIAd1Bdnxm6xWSVyuNK3NvIlV065y2VEpnOQba9NhfXxw
2gLnHQ3TBxSaTFytEJyyfpqaOEmFFLYJxNAgWbOz7yFIAG4edPvPpbPwwshoLXpqQr4kQLA2SrYj
w/KD761LgBqKeUY0N4Gm1NKoFcFhziFTH8bG52KgD/RGxTtJ4o5s9ZLZyULBuwYFt8tIhCAR36Xx
oJvVwFUzLnIlE+b1RqGarJ2M86TqlaHUH7BiT9lHg+U9+0NgNGyvvqIfCRQX1p4Dqfp7HJiSq14R
ZK5co7fyxyEOclGA9A26y6C48gY18bbjWbNerY2m4bBaV/BMIbPl0rwivGRbzTQwaXtkjej1bRgE
yjYyeZsn9ZUMvw2ivcYaIYDlauUAjYhtCFNlSPeLZyZaQ3WXKbUIFMLari7FclJujftWWWbZPfzF
2syxNfko66d5D4kMyX8XTNtiy5pcS2DLDW/jOaxR7Puk9mc12mrCPBKYkrpJSEkRS9aLrfGO1ZW/
odiI3Baor7pKL1q1itoYmYRUY4wbilbyaxp5wUyCyj6EiUEBE+8YsRDFZ6w1qOXfr6/wH+VSi+2C
cHrVvTSEni5aRfXleDAHhgpcmRy/TnvV0CMSl2qCLtzACF1WKBRLbebCmTunVcdbH6XZN+InmYLX
0/Plsyk7ch15Q9mm/sFVJqEYStC3nc44JvNT8HK7ntiMMDkxrDGEk3cCU5GjHH7zweyzHvwAH8LC
SGHQfzuIbcTPtJCHTl7QGnOfN4/OOQMLX74kEzh/0Sl2szllkNqK8wb8LY9H1xZmQUU7yyOUvO99
YvnhPmGqCAfAvHuLE19QrvBiqod7V1XfYZTXedzeEhqcWjwIWT8iuTBoL9evGr4dGavgmdtImUIF
u/dxhSDcAMD0r33+w2D7zThf7Zr7DvJ3/Kzs0TShGv/41h5oiIWrCQPOVP+Gqo52vZOVkZO0npTg
Qb7klCHpwUDsJTSDt//lrlvMr6XZ//33BV8JzjQIzVlY6jbjfJ6UYCMj7KFwxaNu8TvK30iq3zLc
SLjq7xugOZbwvMkb5h9gi4d4iA1pnY7VkV3QjnifK6cvABwHPiDj888QRnk0Z3UmH9FB29AddnS0
IeAE6b745/VzZzkptUHkubbB+VtTBMGT/QjPqoOphA5vhVNdFg0RPmbK3ShaeiSMWNqgB1EKlpDH
qzLa+jFU2/TORZc2Po1yvkxzGsedwgj8yZDKGAL3+bz5gxAvW6QRLc+x+BeIiNeTDjq46lJtzr06
ZyS2Ra27qvRtTxQUYygAxcdzwOs+PSURaF/X9AqOpLJZYY4bVv939T9NmWtBob5eSCxZdZsWbdPP
YmmnGuMLp5a0HEdpPAzy9fe03cX3VrLn7LPwcnfLhRVex9KNdk6KQ7lEjrApSIM6FIgQ2WRGszZW
GK06GeLvwzpb5NAKbLijZ4bVrnHJtpQBSrI7emMFL0GkLczm90jSufD/8ajTRETR3unBQNOucsOv
5jpss6HveG5nWiKegvZyfI11nu5g/XLaQsb1jAz1Wx92auEsH2wGOZBMMPEdVZMps3HlB3MqcFzn
nOeIJu3hCeIH9HhGcMm02qYkb+yU26N7zk5qbiottQoFFIhoT7eTDYQstJX5sPA+cytdheiWdPvw
w5mDtoQuHs0EOtkjtxz+sz5JpOlKwDgqLzr+sMteVt2ZViIjayYiOTV2iUKYIx9CMk2BwTsxRUxC
TIrtKkkeggaP1shE//CC3Q3V/bnyFlXLoYygM6nn+DdNZF0AySP2Uvwr7KXnyRU81qs0KvR/7bln
atnYkO4dOnlDRYO9SrZGtIo3gRXq0QSHQj1VVrXE/5EYbcfoFisuoFhIVKK1FPbZ1MwkVzfSAu0L
+NTmodzhYJ1xKLsPJUJV1aAJX6DTrgJV0e84mNZUSUFJ4Nw6glgfqLjjFdyrDXqMHPLUBAykL8ai
YrtRYZpVbw+6P+LEv3com0QSG/CRq3Pc9WhE5d0JY6jZnD/+P9kEm0HhsdQKZ9jV/8iWrd1f9J1L
EEBN5+s2w5s3M0vSxAznZy85RbnGIdiDOjBxE6yuBdS3J//BgiUNViEVAa2KmAS7UHuxwjHvTez6
WwP/gALTS3aN7uyf+uoRVAOBoLhdyDuqORfmOS9JENL7tQXwQ0GSFKL+sVRufAVh+YvloaH6T/Gl
rHfC4+a9UkLnJh5n5X7f0ngj3Hlo8jxrdOTqyA7VJnQsnIsoDMZ1UvqNJ1RERrHKs/FL5YFtwsCq
uRnNUgPq/6gg+A20J6TA9TYpkeT2p24LhuLuQe5OnzftiPqhVw0SOMWdSBRMDFTCM30W44ixr8oW
Wi+VjcKOPShlTRuYWS3n9VoFhwA4s4HI/jBX/MU5z8D6/aUL/hx0Q0iZxBawlFJ8zV6QQwTSbC9p
HnoK+RwuzcgszWGFlEeTKoqx3PrgeFBsdXVpWnpsRB6haT5qnme3mTY+nzDt/2aTn5/iOW/wVSI6
OkQ6mM+vqporZR0mpLnQ58xDqeAN+FdnvGt+46cxVB5m5Fr29SYg5JW5+ed1Sd4PlyTmwtPrKYDO
B7a34Zl6KS6r3CjWFZwhcmpb7fjXMtlL/SZ6l8CSCcYdseNXUcmgWf3F9ZGn1lnoTtgj2uuL4a4L
HRFzRl59MACollgplDAWCaUDHQ3NNxDTtxbgNlH1fxAnVcQxzfRPx/Z65IRJmePZVZoOYbOMkVMq
KiP/floXd/WYboX9b7Zxzp45bHE+AQtbMcUeMEpMFgrhsptEQsM739FwE3+UpQ76T5L4TsT2NqAB
E/C6MDoKgtV47afkQFya4jBJNQtaPxq6UEJGzkbdCribyDh65/2604D6njMzZ+FaKFkQreTVP655
VBqWD8ixlOymwb/kRQri5td+QKqFoougm4/hE+gst7DJp8vXaZNyRDLTheX/lPSNrt7/X6LX2+8i
/a9r1zoLcp+8Suz0KQw8nR7UBWJdquM04CJrxuSjcik5meK4qe3yPccHC8uwpqH6F53qcACLZd+3
oqma4znSwib+gGS6nAQEZ5lStb/T/WQK567nHnNccxAIovRz2IzL51bAB+0EKYxQ8igW+tkPCOLH
aw9KzO91/bycdAQFEIXJ6qzZlVPRKmNvij9ndPURK5LccLR7Szn2ejjwU6utUJvNUIxK+gzsRPl+
TQsPDIfzVJ5rNMyXg734FqiUv/Q6EUIOR7NY5VSOevzYccMkTnRCE5Z3LWtHwYTEfxxVlT+Sd/ta
2X4sNwiOPO/l51B2macwAhu7fun2THKJ72sqFmsZDux9jXNTXO3w+tXyAwK3Drp2oaknr6t8i3UJ
0sQXBS8qA/RDxUC49BIqPD3cmPGwNzpqxWkFKh+A3+4bcyWf/ZZXJC+xls0MndjTUxjXFan8ER5l
d6PhltewXw0+zrrp+M1q+u89craV5Qr6OljyJajMumvMkwDL986XVUIgg4SO3rh4MGpqj14wYWb3
y+cMPoEz+04cIKKhvX3D1w93lkAfvwVy0T1cij7B3dgeFDc9IB6Iuw/1tyVgwEeKp7Mw9N7t2byA
m0GB3bWoDieexZ1qeQtL04n+NQbQohndNWgmGusnjf7vmUjqe5Tl9pF95AmgqH+/ZSmEZhqiRvlB
cFo8cueyCQzVCMTwPrivLggEdrB+1X8I6vvsPb3vK5PMbnxtj4Jv9zoRlc76Gv7aakw7xF+0VCwK
VbKE2Wkm3P1oYur1+Ub900GjIdqWZ5/WOQYnV4IMWIys9/J+meqzWfIPstVBZJ1O5esPIcxAGyGQ
X73sH8eLdD1GwbsbFaJZUEWnjIeDuF0wzcsMxb65sRKb/OCgOSLF81gqkGHqXxi/4qE6aBTEkpjQ
DZpI+0MFcLhZQO1FY8X95tE6wyiUVPKWr6JlmmabZpvk+cApwdcW4situ0TV3foSZJh9rgU69Hbr
doUwmgAT43aAVoa6jEeMZShEOT+Jrqh98gT7LoBJhOiGgpCwH0IX2qGZDvu7dxjx5V5SkxLFUGHv
R+zvz5gLeIrg/vCZl8nHWcTfO49hat2b6d3T5tipP9phCvOD3TillnVnHWCNpxfXktPTcsaZ7p7S
htVOZ7V6Fc4NxJnGMnzFwz8huKl/6LhLokqOvQFi8Fn4jDsJgSlgxAAOUwOw7TwzZVOduZUm4rNb
1/6YgEVNY02sqPYaQi6a05L15eB5AtPCpFHtMrOZ7VOUNDVxaZMMeAKgOUh0wIRYQ0+TGRmcpTfw
Zlv6+SnLQIInwvziSpkRMbj3JJGpUriQbRKVDhlgq7qLY/DHTguO+u1xApIL5fKTEmDiHnZLKveq
Z1069NQibjfaU90gOxKtijEVFV5BeJfaYFuL854xJmfP1qHKYAJXlb+OoSlePogx1btgYgYZBSNp
H/R9QElevXJQXbHAlKjoXQPLS8TybFDGymgeRC6e8G7eiVE/omY8gaMGuwtOdiWQbzpZ4BHCKKv1
33DtydLvgFhQpYQn3y+gG1VfjBxttyHHdvaxy93r2NsXAjAZuCBO1nphXMQV8nRzvpFRhtuE8Qmf
LaioNEB2VmPilMEpnKi3kOhYgGO8kjufBHefDbkLQc8N2giAv0kTuqgOmDSuOb75MzUSP5iWZWkH
z14SjblpD9nF0iuUbQxa1iO4+6MsGkDnYW8l/q9moNKJaoj1aqiryR17R4kOmqHeIdWG4MivecKd
54JV00AvAG2BjT1ml+q9ZjJz98E6vVMFqFcC6RDDMGYylzwrJgY7Tc4gaCTQ3zfB/Tv2Eog8du4Y
ahTxCl86X2lDsc6sSm8cUl3dWVBlZt2eFuV2QiIIW+ewEQgAPW+CUcpObvyJH3Gs+USbD8Dg75v8
laLNc7/QA52iJ4EznKr+jX4GM2zoivWlRpj9inRUFcF+LSe5302Gi9wW/55fElQYJDtCuqSu9gj9
BuWFzfYBffucsrE1kxAGVGUnOJLTAwWTuJCEJNXbXXzj/HfmxHnwn32pcMREZvY2qrtv+mBBSSfv
tZxKPDxExPqZgsjKhH5KeRNn/s8lbTssDwRwYhZrbR/BmqZJfPYZm80A0QCtg7d9IgD7CORvhYTH
78DKh/XjRhoOfHqsN1vnqW3uC8ldFoTyYcrLeIh5qtB+CVzxlp+gLGCBUiXSu/Bd/rGHHFk8j1FO
jn4Cl09LtX2mxya6ajMTCZzkUxwXfFw6IryZT5a08JS7qiRjQi54/xzbde2HAw1SB029BF+TUjq2
Aqw2OmMy21oYEjPXxiguNRdYrtZ2JRsPiuJzixs6R3STgqmNmSiP5N2VL4xUhNzhk/hJrdhAbvW0
q16RgmknklT4o6daOUX6P1dVKBUOzgtXSc92CWwZ6FspjFV0DeNHHqP/zp87/PdRrhPNVbX7DrAu
Lu3Y7+ml7TEdiaRx76QLSz3oeIrg/KGeyiteBPccVR/pNK5nrcypzNgR2OqC6gNdm8mnQ8h/iqej
TZTTknQij9xE9yTYBhQ9LPYO5dI9nRmJMYaPA27PYjkECj+9guqVhQRw/+gLXvEgnPYhkFbP4eoM
sSFT8GghULWmMpJOt4JtYsB3tgzAoNC8PvE5af6Uorghwwn7BTIPgxiPkYf6PQ0CJJ1uIMoJen4C
HluU1rYr3fla4CbPLRS5wXxUWy9RyO8XofDHLAxQ6uWHwLApAYmCM66XkmlCQR3HeQPBMRGazvFY
d2DtAAYz/kyQ3E68mDFykT2bwVmtE32yOZUc8EMHnK036vw2fLMyHDGBQ54tKPs/5dyxCji/+dG+
4JfpYlr0XbDXbjKAdpaExr42FnJ0VviY3lJnQYoxSQa/m+p2gAVmWFKce+fomDMJeSAB1g6/aPDK
MGv+QAMV8hUTf5GM4grTp60ti2P4o2uzdUonAIrDpqdaMYNpA3MEIl6unQeavbcBPmNdeceQv6rB
65jHTTvDGp9Xhg2KJ9m4hLZAhnAhWI8GWtHJJ/15hCbbKi0jg2YkRjQtMvQBLSFt0J41+vobt1hB
a1hTeaQ7tM6CmXW8pkbuacp1jl28irusaS13Fn1SypAotzZ2mkT3smOp/xlv3zEAVrcO0t76RyBC
kImWStT4/ig3p/3OBH6Ywn8VrucORWE7MJixGKnAkVkqiQbdARMBNH+0kJP7c+uUYVX/mpdHVHMg
BncFpTQfmMP4bXXlcMk+np6+C/iIGZ52q+QSMYJyNrRWuP0KT/x7tOntIjZ+rJReBdiBCeK5BgOh
KWOSO3LssYef2L2N9pLHsvH68Xt7/bLe18CxFkBcuVcPQ5fubIjRnYqItT2JifnOj0H8aHoj8Jfs
uCViGffllUAvFOSSgwyr5/kpFOtsuN1ZF9559TasG7WhVKu6WSKOKImhvgQZDrT4zH1QBY8EO+k/
l1hOPexAyBxB+E3WxBIKqb0wcLmPv43H3triop10g7zYbTIcj8LYGHL+GHvLNR+1yvd5jtczluP3
XbqhuEp4JGqy1Ug6H3QvCR95wYKgI7kO8mPpDxzKqhjyHP1AX89In/ZnhfCSzNFpyKCHATY7E+/N
PydsObskeQF7ZjQp5u2k3NMaxQFeDWZsJ1usbvp0Bcr66kBPsWHrg3EQn9v35A++wztRfWCIe69K
bYp2j4tZ5y3jnZtfdccRxcZVsDLB70QF+PFn0QnDLaoHW3wLhyn20ofaE1Ab4FCOCUvCMSUoVJz0
iBy6o0ZbPriBLgI3W/LYbwiyq0AxzU4cLB6tXfFqt/0xnanexVqGJFKjLwKaTU7xDluJk0vBgJfZ
R5vtbaygaSWXefxKsJdttn6tNkjQ+YPWlhUv9MONOCtfusk11066AK2t/eC6JX2iwfvN+e2VT0e5
lHhcRp0x5sTj0Ma81vYEpMeRMRptQ5AT1U053e9w3Bqrnm6JbLsSBopC606/RSauIIkaaHfcLrt2
4WkJ9RAf1RrhIMDU42/S9+XhkGa8uayOCDRSGkjV0mDnZqf5dDh5Tj2FQuDrnR2Q00+jvH5YosNU
1n71DDCcdjP0X1gYA+aLR2Ugttgpm9FnGrW58nsfkLN08T3OSW0tSx3+JeoQ3EHG9KDh1vXuIHsW
gDRv/061i91H82jY3LT08tK+7Hz86mjPAtGTs3KJeEWEGy0TFdi8vNRlA4MJT+b9uyCgOhQOOllK
hsd+qHPQLsKDJWIUyV1ut/TJNVpTQEQBqnxm0YYXFqn2iG/DX2CdeClmcTW/AMcWaz3NxexmJj2A
ija+I1SZBRnHTTdTcWp+A11L7fJOfYJ8YCj5iP2qhO97b5AK6tjKDpnzegHYJ5R+P/ZmA/COVkqI
E3TZttu4cXhqOUlfW9KLKtDXHfgQDpy3yKgwD9wSS1VCOkiQZwiMTbJE1MmV7O4/sQETUH9iV1UX
EtJvQCgNZvZ01tFZjBia14p+UYg2oaOuwlEngRw/iBiZ2+q19SIQCE/VM3c02K8XDFfnrvQ2Hkcq
s8Bstzw1/ruiiQLnMdBa+LKAP+diX6SNqmwTvnsUhA98B0fiaw88J6+vNqCeWdtDfOeWeRbGIx9g
iGyhp0XPd9Kn9stSusWDR1HbrOCQD8+2SNyXfz4DO0Lqd7Xs7V+uoViN1CF0MIIwnfo+CSQpTfeX
qS0RTKEflotxLR31byHGkqxvfqnDbJcwpk/UBpLcfBCZxU3oP/e28t85ER37jiZcLmtYw+hMm8Pn
9tlbnL9UkeSYr6sp/ZnSJuNpT+/r4/OkVmAA693hB5KVRRukkIfXpLNV21gYKU1OxZ8ro/aLGhIS
twHmqQIs4tzITUQKpIc6Rzw7k/z+2+JawS2SX6d6E+IvxHAy7HfJailEFZ1EJDoH8QndAErMl8wb
lMXxvS7SXhdbRhNCXvyHU1VZaKR0yFOxcx6zk/4DJrQZv3EvM4sZ02wQ4h4mpHLbYAvoXwQZlkcZ
y33OZYBnK/HBy3aYprAnJGFJWgrxVEymJt1AbM83f7kEfUpAeg1hjVllhbMrOLTkvSI97zIXscaM
JQv2e4ix+Ig9AzJyPo3NI+Pw2QDrMyaKgpZtmKOngupDcaNx6kRPU6dNUQQQSi4A2Vkt4suDgp0W
jMCh9W0LzL9PIn5sMmtCT3cakdnl6N19LlMMip+d5waWtebFwF/C5iyj1cAZEBU1kqBBJ7js/WHl
ZFCaD2E1pcGq2gq5T3ssHwZ6Xv8CLcXY0oQX9AKLOIjfjj4XckjVC/lv3Nr+OPVfB/tHPQXY6lyv
yo5hoTkzPX0Pf+KfRnOAv+q8bufCM8BQVNhOa5Tf1yv/lEcYbHv5rwfzHHWicNBFHTQNskhJbU1Y
PhYURgdNZi5pWtkLOO6wZ/tizSRuSZdWtEd4p5pSJXYyCxi38ueNevI1U2pIVd4+72T05xju2Z7F
65BY6IrAaePqxhz6+X2weyZ6RzvQ30ksJHU3341HBNt4mYQo+XfpzJ3mgXlrisPJLsEfjqR3af+S
qerZGPRkRfD2nLUhTOW+iqEcd3by5fMmJNiH8mCw0VG6wa3TYMdPAkjAV9sx/DW86IItzZ5lAYTE
Ek0BWVxmg7i3Ror9nEfrSSW4Z+Cn+uNAYwu/dtpSyysISQcfKICV0H6/FndOdk3ISf6Egiz5A2cQ
hpqfWyjxzyqCC9nHUot/6L/8Gg4ddUw15BcKTdhYe13fhqcKMZuINfkPOGsPNrrdsjVtiymoSH/B
NO+I3wcBDz/DKah6klqYJrup7nFptOqvv2oQVjmpnTWtGyGljMQo55W8wYDYsom23wOJOYBxvjvY
L45He0imrRAtabq8wPhkbYq2i/9XOn2/inLd3chwUh6mto3byaQ/KXUtj9YKSSZ0kgjT3vPQLKpM
Aqwy7zwOB0VrNmd83L9WIiY9qGP04LlTS+DJ0Az3j53Y5VKNF8DXzo/9RL80PrGU8g6MRtBwWiv6
wjEFvhLcgUld2lWhrWGfE9Gs180HTlzaKyY/wNJMbKdrNDsIX0IcARlxmGjh3buSY37lMipDA8KA
i9p+GsWFgoAjhmwb5F3vq05QIUPTX7sbemc7aAM5PW0cNF4aQA+jl2yT7EZQJpObO452dkF8HaNK
khP9JDmoM/RNXUfixiZDlk8V/Cj6gYX/xTdrN+RxdFZHDHhgHTSQUfjJ7wbY5CgCvS9MkXJV38N8
Zl0JnbpMqD7YjJLC3HBPZA7zaL8SrL6W+nlu/otSLZ9OqyOw8kKxOC0DXCpeP2btqso+q06D0z8h
J78zm8pBNDkVd8KB2+IkD1RReyxRmY5YumEdTHF/JlZQIJFhraGuahaH3g7xItm4xYcUPyy/2aO/
FFMlXFObVRti8Bm48gpAsUgm0ci4idyJj2NHs6ufsHBRGcZQazqtglLltMrcjP5cQhhBF1OW7RqM
XeRCIlirwQjvVJsgeijTr7KQkH6Ji5ZDJsF80HL4Kvgag9k8qsW9vY76qYn9npSei8B3HIHMed4y
dx6jZBERfyPJbu7rZCVDB5mBBtjE8Xq8HseOh2T4ttcj/Uv4lCUYEFSwJp3Y8Rp3XivGXlNzdaHt
CbPIWVhLC7GLDUDHoz7Y6TR5pF/7w+C17b+K3Bqd8w45t4diL9rBxW4cQ7fhysxzdT8WkPoQTM6Y
Gg29ZIjQQNNzBTqJ6BDfUEKRLqGGDvg95BaWYM/6WS3pACcpjBr+HhdkHxk6ALa8UfWjI5EMQF4C
AABRGl8+mxX6HsAnuVgNwubpUX0SRaSB66fWLs6iEd+p5aRRJNuw0BvQjCjLxFdHdldigywIJlWn
h4vkqoxuTxF0azwHQBzMOAC+Mt/TWreHd1JDQPJBNLhGyNsdiPbYJWHB27sM8Lt5kW4TxtpQRQA5
T1ss1dUqh0jMUfYbBs3Ry+9agy22Q+EH4GaXnVQfiEHF1srDNuPAIP70kAKN5iSCVqPvFEUavDdG
Q1NxfWQ4O1MNkbnxhhUYt286A5QwQH2EVIbTf/eWaBwb97vARqlpKiePtgbNqMky2h4CCb3Lp3MF
q1RXNI+t3k7X9eWCveJMnMNaiZLTmkIloWwGsXa4VIQlheXD+rjJBlEhU1UDAfJhuse9YdZB97z1
o8yd/k8FSXLmBMRwVf0UEVplljTtpLJm8f2t0IqpcF0uvuaX5RV6YHUjXcQI7cbAYLJdCmS6aEHg
HraQ/k1FqzBWF28hQ8tiuI+A5tydlVr+BbeltrU+hrEl87A7v+k+LaA8fujHaXQys0AiC3QKHQJw
tq5uREB+Z6k8VT3CHjXNub+JgSFqWbLiz3vabrJnZ70DY7K17JuFCY81wL9IZvCBdUe1qBc3unFZ
5Az2ALW/J4bOsDi7KdXA3F80rME0snmxJ3w8u8vF5M9BJa4bgX14cOBwDGVLEc9/+iwxdIU/fNFB
CydJazC7/OKepKrktF5ayHuNFWYfAtLoPhn2XhR0k+TJ93L8DmkJ0TNKnOK6BdxJnIXgcoCI/sQK
PLcRrADRDRVlkDV7d5ErDCEfWOMjoPNmLrDVYjEQaqppepu/l51x1tFTZgwxfhKbs40uJMGC2SFI
Qb8m0uspEnpuS4WsaqzqXaq9XyDhJCXarh/2NGy/LrcyYl2vgUWwBkZkvuLeG9AJ5Ux6bEv8n5AP
1UnYKomlngybGrfCFb6CpozwUOcY8QmEp//LCGxHHyBMSS3ovuIw32gNag5g2ntmMlk9iHses7sq
NFsLU3dJ7CeXmrzVRc0xh3UVwY5nx4y77kJAgI3SKAwBjP2iZRkRD69ojA4SOzgxsIaRGFAxVccf
F5hkbJYA28i5H8sGOz8fCviNtGQc12d4RZA8yOzME1tBnvJoFYPPXX4tQzYpVCJVSfFbjpoFuEAz
K7Ntn6IFM/Th/JIXZFKhw4m3WaQNy6ivqHLQpgNHQBLwIUh45aeKPFRayPrA709EJQcp7VJFAjhb
yNQc2A1VF9Mcdy99x1kJh5Dn1/RCmq8LEXuRJeRRSyrTTcqwYvFZgA7eeOhOE7TlTuRgL1PiOWnJ
ha8LqguMAYD/M6oj/nfZa8WCojZVuRI4lf2WoHKdibwBJwpCWpLfvy0VfR7V2UWiazw+RnweWdGP
yEPQ4KO6JrbWXI0unhEC2JnvegzK1cicbIuT+lfXeZObNHq3CP5bOYueYRpUwqzyF0k+lt65VBXc
DnFkDanrqeJUvTEauokRyxB6MMrZm7a2zudqnFaoYUwfNtWdeA8BmJtFMzXClZeQncdOcNrZx/x8
oA4qavBJksR5AhZHCd4tkIX4h7YC/qTPxpz3w9XkQBXuhD4gDlEFkOueD5/52ZIvzrcCJ9JA0ymO
aCaI8grDJB5G1v5VNBYPlOG8trDQ4Had/Zv0u1p8YdAs33ERBW+Akx+HDmB6BYpg7RFEsdo6Jsny
xbC8MxH4V1/6rWXNNDcOYmBZjm/RXuzI8+J9Aggzh6kqM0cfhLMddhHPyHa4E8DyJ5IrW0gZAO6g
CZdAaUJEa2IgcHZfgXVe3U0A3Z5gymOuugCz9A87Eb7naLc93cTSDmWaiL6p09WNF+6SNJFt/fGt
RggTRX477Qg5ypeBUwGwRD9OqTCmaLW/zcAapEGtwbCiflxh89W84ZZq2z+ZP2Hx8Of9eRy600RO
Ub3Lx1CkGJfGxmrHJYO++uteSm3/TPS7xvif+5XiP38M0TLMgOdLksXXYEWO3dMSvLwhmJqh3S4j
ZjO8nRYWFuxetSJBlrFRrRav3r6IZWWClZqlbe4+//lv4QKTO9kCRqGTjg1KTBr5oHXXgs943Os8
ihRIlq0ZvmqlVs3x7ipIVXC5RTVzUUT0XsWKU1Eo/rlE52eTwcteI/gdoXweUg9brtXt96j4XInk
92b6knjdu/V5g/F6vt+ML6CWLtOP+FDVhqVEcFfhKpxMIahTelgzM5MYaxGVdaWqxel9lAzAnLWL
3ercHCm3gV3lak96id6JFUBct2ogFUwUajOR9tmxVlPYI7If965gjszxkJXjmPdnmz6ugSnjMeDo
cMwPBLO7oowcb0bF4Mjsr/asyQnUH1Xpg1G3x7d3lN8PZHUlSNLbXJ/ZIGxpkckgXYJm1lzCE3EZ
Uhe2ONCC5xotpnoM5jHCxMnJ4tDhTNP9KJGA60YjzD0n7fevnFssxgCCZFRqpIotPaMP0I/U5CJh
lvA6pzEfosOj0VbUhPYUO5BhUNBvthQxjt6vXB78qyKfP+wTZCOdY0aXewD6itieuFFN6PSrDbYV
/uXNU68LSFdyHBZVRLjZZ4yfuc9P4sCUx/3KFW7egeXPMBUkl3iyITZJmvApkf8wvqWvK4VwnGem
AYsgtvUPU3wljaU5vVGvgHhm++u4xnJfq7uJT7rsrTrOExYBynrX3Tk/o+obUboYcFUfvUIsRHYk
es74vBFTmmSrvJqr0qOatqEdM7iwWbG7FB7V15H8LL/H1SsACiCRerDozcw5lo1fQC3+XxSZ6b7o
ahi+D6U1YKVeFQvv92prnIPR6lphHCmgfyl3vFNacOE8O0euYzjLdSDe8u7UYqSNKw2HLBLUTGf6
srUShdZAXmj5wXvUxW7I1cPfXUZNlOH4enyO/gfN5OszIEtqtTDSfS3prW6/5UOZvoabXY9oSH3J
dQaoXROHjoObrxHa7lOTRRZkjB4G4DX4ZPfWsbl0jE+LT7YDxsa2Tqd0CCRal+OqDRG/LtfnqKWw
asr0eISpSA4kXQcAJqDPyr30ft5AnDHp5hN5+SZX/zjGzh2yrL1eS78d+aDWA8joHnIOgBQSUhku
U+bkdkdsqWRq2NR79UWeL9zTnqCK9X8jDJcKnmI/STgmqih4gOSl0DPqtfXDjwUdaNjf5xyyGxEZ
nL5UN/dh+fpfe/2GSrJo4awBKOfSUn9Y/cQNYkdDTOkXPqFb69owe5SFSR+BgaQ0RA4BrCHuobLJ
DiZc9FDlHTyGBHMh6RjDMSATLOv+25DNVCo3HVbEzNWdFqTWqZaAxDFLB4tt03AF9pzBG9cuqKmi
jlil0ZR3oyj0x4pYk7GNHZGpNLfU4MTx/UZcAERmBnI/Xj3IavrPbpyqVUI2Fop+r5+THYAF7wkh
uvltqzErqN/lnU6PLdGh6DGxERAm/pOX2RB9Yg3/YDyvl9W/37im+Pn6PL2n0FMb7PQ1f9PBghRN
dpDI0op57Yg3dHRdwWiUJF59AUWQV+on0bnhVXoXhujhlO0zvX8dg50FqNQl8YPME1aQqivqDVo7
2N+yeP1tyURGUzmUc7d3Qtp4NhpWfmN51xCnUnNui3g6b5TEge1ubk5a6dhinAvruH7QAzfbMu7m
W+cgta0dU+a6UMFylnDXqOWFl/kEgvEEGYL1ju3+JWjM2+KACaWTJp2UjjU8O98Zo1jUA+WsJA9N
gF5vHNK2Z6x9wx4DoxucmUypmFfMOnMtjgEekW6gOJxx+IppMSAdpkPw0+OUgdPX0vBekLkPcNf6
v71Ap6EVl6emAQgGYO72XdFy7RC4xefSeulPbUCmqk557LKMSdhS7V3eCZceM43iMecNX7+cCif2
RY+buhQLhTGeH0dhbjBnwZvJrQncuGoOER66Y0gTHzq/EdXQMCykFYDldM+acqGjlbHFBt0HjIBY
B8R0S78cO8IfTAV7jh1q6SeGYr93iAPCfBenoqKxI0REIr7XfVIbgj4Ionuzb5obHQDlaRny9wOk
Oce+mnwKD39azEATEadB6/YFBQVlOjj+nNsXgrv7p8/SUEUsMkcaUJSWQM4VmuUJ9pW7sRMU8gij
y2jBcvWzLmjsFe88KpUfg8eePlSgz0oH8kbNODcG/eEjKA4plc/jQx9cv/tEUBcz/ZXJ9N1QZTpe
m3MWupD4JKX50pmCnh4w4Jkx1relebrSRQoZUwy5ANVL6dUiFzVsrZgcfgPb1R3WxeZwyvqlV/V3
DN0009803dhWnkDcsfP2KOIiAWfDG3JaV2lqGgd/8BVVW/XshhEsAF/ri+fQ+sIEE4iXHMGxbhwP
8vJ/X8+pdCijacvbaRlZf1h0Kmkvr33LfAGqVhjBBg5C2HC46CO8NhU+3k8zpDLUZ6/s1cp4XrNB
lgnV9ygaAty/0A+5HuCdp3oVG0PsYd75v3WJOiTMvdXLJNJt2MMAKHjlDgC6bpMxAqGVlvO5waiD
g8zGXOf4fvTxQb9TXXUI+R1DRy5COzsMoFJ+hvqfQQrbbx/8yk6226ivT3dvOhFm8UcuuzMJm8wL
ViAUel8ZiQ/J5LTww9jdlZaDMbicsDJwnvMWste2EN6xWQ90vguENQT/ZoaZl9SueLGIt3OlqW6z
6siSaoiexn8X7eW/sMVZJFnIk7ogEVrPob9dStLfEv22z/IVyL+yf3BR41w51cg5gT9ccsBzRmv8
gpUZ9nUuEz0sKTCP1Hr7weCtmh7zQdtb4tN8BQBk2CcEYpXP0ib/iiyc+bcoE5ohLr70OSBD0YCV
LLg2Fd11rpUJbUb/4YZWGQifcBkLIwDxvJW8Vt8JvBuzV6ye2fvW5YXievCW/97YIFfkw+2/BUF7
kLhiivflO/eqxysMcVUn/N2MqPYuTNo8ekcrFjHx7aI4e3gi3F3GZwDj/1Pfccewv25a/Uwj6tSV
R/hwRJdMkjGhRExyRzhLRP1++rFmzCI7S5aC3JMlHvD+dxEQFIFiFf6m+G5BYKlvqEqk9CCS/7mM
hSTbkLbsXmA1M/XMrgMCXSA3S9a8QyGRaCJZJm4QaQhmU5Ln8q4/ZRGJyYwa7Ydw1byFRTuvIwGc
odM6S5YPDTX43fGOcSHzXOXvBX9u6iKNKvt7y/dI4YNb7UkOKo6SMxyusxtRF7FjOWJpHou6t84l
/WJzDf0xCWur3s/bgIwCYKgqePowJR6zESbyJfT0Mxpr8ckzf8QKbcIq0UyHgWDDONwf/r8HoXec
fBlDM3cp8plRwLr0CMx5g5LF+CNqJxjfgXE7OdY4bWGNjF92hR4jJoeUH8NljYoWr5iyYwlusKfv
AoxGKNDASc2NQ2wLNfGKms6T+5S4b4UqCagQDmtqdYqjdznFAZIb384W0FvVP9CgiwSp4pzg6lf7
YMAKPkhIOkGRWZAzZTq+F8sejvbA7GIqkfA+q2StYVjh1C2Q/OcHk8tAZYGszHGNhmebL6+BMPNq
WG3uYAr7l7CoVkNq3CnBrB5ir1D6avnPFNcpkEDOxMg58rmj3kaCfcxEv3ZjdMhlkqEwIgydGWqp
XPhMLWEcDh24rfuR019Xb0M8hvK/biPR6+/e6xfqyTqYGLfLEoYoC7LCloju1zQhyZCImsu2LnPm
p1f1h4P0i1dPXmREhgKFjdbmCdv255KXCozBO5tDkpVURRe6vb+x6bTmTLDskmoKuBM4mBZ0dB1S
Jr7/zayxMzGMf0ZyY6BQgvHZgYrQM/VR53Bk3Taw5uZzZYt1bHU27yOymVp4tawwMFzJRg4lWi1Q
rdVG/+yO4UZGgjK4crms5UDNSMe0o66FuLcuBQ53BggM1fWEn5p2gJXq3or4ByTqwxkyAi3nrvfq
Wn3GxqKSRQXJPAkvzY1e8xSsMboWyKuqTGERKmEoUkLBVxVEbGmvmcsbW/oDQT7q28QKX2PxRgx+
qdtxR/AuqCipaZHXcz8H9S8WPcbqNTspRGQtNdlVLzFgDXf0BZdUs3UUxHuorXgIYyFQZNlAaY1h
o2sHuczPjdDg6VFyKNiv6zQSqTI1oBJkR0OLWObcjshTZjhkWhwrqOy2NfUKSytdpnbpnUG7I2+3
jckWbkKQJdwGzcQZLlyvEm1ibam2VxrgnaSsj8qhsPGmoJrAi6zulCzn+zqUGHeZJnPVzNSJaLtz
7MJsfAjQiihAEvC8MiM/a8wiG0xxEN8bH5ZD+UP70ozk9L+5Yz0uJvXr4JgH2jxUSgKfuCAT0tFh
TNMGJ+wiJI0Lbpzy1o6I8aqn8xhI5/pkhKX9axsn+5pcfU+UcaIJZR+vPrxzHAVUxN9N2kySOMQ9
J0L1lMTbu3Fbg1qdhWqaPWAyG1+YzrEBzIMs1XMlyxNGwynNqb5C6FuqP6JFU6BM3lHEjR6lNCRA
dhuIAdz5zawsEF6EvE5jWhhYLiCwqXeysA9MQz/564H6VrK44zYn2GyMSgtrcoBtRoOC5ahzT5f0
tlXGvjoKiBjckgsmcllbIjp8pmlyL0PUwdxSuwaXChiPgyEiEHqz2coaJ+4qSh5rClz70pEhX7ER
9b3Z/HYjL/yrECRNG6yjwCMJU7W4JhBBV+Scds5rQW5dTY5lCADFfh2YJ5nuJEJQlIH7fazgq6es
/+djJFHegQwjOcc4qf0s5jcolZEsUKzcB77FI6aFuDHDvlo2RoULuD22BPUSH8hqodpYLJMjgBrl
GOzoyi5ITR1SueQDKisD5+/kCC7LqfjZ454a5fSsfP6cH1HlvDauJ/4ckahQ8cR2VFctbg8NAMdZ
1ixBtXdwDPAt3RlguNxF9lJAszB0c1OF3XygcLf9dqCKp0z5Lbd6K0whhC/KGf0Bdotqs8EMP+eX
gyilsVIFbKySl105tsvwk6WWocC4wUCQv/hQb1dYwbKx3tWNpM9FPSteiLVsyyPL11qc/MtOw9O0
Gw+y3a260mxlBIeQDNJkvC53ofGiyRskHJ6e0KnSt2wjpH4RzWz23IXRKcF3Xwq6rr44+zKqBTX/
2DHZbQAkCI0yYL2rRRT6zzqh7Cg0pS2Uq0Tv9yPaWsN+Iq2I5bTPLj4ZrwZlM8HtIdisNT3lvC0I
V9EX8wEXHe5h9TBZhBv703LodkJ0l6eLdzqs53TVeqEw+UamwScnhFL5LNQvxoe8qjPDVP5wJgiZ
EcN3lnwAEzo6OcNyv8RE2qIBb+eYiWuOQTv259EFzdIf05Yb2xpFp8cHQdp5Ws1JNAH8vHutxt3n
Z1CILElGtCmwITJbuE9DdzkROYcxpaonsuDdc6QDYybDULlJoZcTnFIvqINubdT0MQQl5ZWMgx0m
AW9xbWX+5n6wVZ5J39I+xjyPUcGXahvnVwu70ao2N8OwZvY6uJsmXqpi1oH87Fmg1LosKxm5pcUa
dqz7CrLoTyvOMsiAh97xhI52CIoICuWGvBtPR3yAkq4gzg7CF6+4KLK6Qr8SWe11bdfS3+pjRlmI
7nA0Guv9Elh3wTSTtpSdeFdncSymHq0qV4tOwjOEQJ0DTIMaCY6I7tExPLml3ZoRS3CqAp2BF4JR
d+4VcJnSxtwZBB/M4/IKs7QrfyPxlx+yuALEkNMQJ8WEsZIq4Ew17yk8xZ4RsuF/6SConK1WEqYQ
5G9yGeTtmn1Lk1AhMbKEZL6QPnjx2GQ3gSArk8Xtggk1qYdjmK+5/AqOeBr5CB3DblOPHABf3EKH
0MFoCZ0599ssJKj2/AdhxcYNFTxyI1s7utKgiqinGWV6q+D6CG7CuTkbMuQHwsAN6QBlxNxmERM7
s2GJnU2q1iinMz6f4tcYY2R6/Td/kbSJo+BJSjIu2ELKyHadq9HsEeKfT1kDasc8KsU5jPXfeX+F
yigbbeE+qjX1FI/afngKvxQJMUbyJ+7TxOF9v4PRcIGD7vmIV7ScJLSoKmELfXLUNrEqfZgi8w24
LHENw/6poUoGBMv4ZZYyUJ093eBuQXEiept1zaUD3LHiyBapzdXpL7XVHXoPhJlPfIK4X1IfWKGL
UF2Xn36hOoHCq/089M8Z4Id+logyWQOkB2uz5TYQ+6MBOj1BmHlNrwb3+/NSr3NMZmcEVGlL3KYH
RIKTPQV+WHQ+R7PFguiA2O8KZ8EmeoTEh8pf7KV/WFdirtWWj57v/Rb14E6nK8aCt91DnCET7Qp3
Kt4u1pWFHYGNPuqLArlF2zb7vNNlBJ95Pf+5bREwhlYIiekDvjmFyw1GB76YB6e+LZPfE/eKhArJ
cmYLlYJaXFt6zwfUa4lL4E4cq4q+PXdc+xq0AzbCwA3V+3r3vKmuM4ih/8hxCDJbVVUVhvQbOiiH
rVRJdKaOF81eRDgi2niDnFgNebTbUsF8MnrQy+yw6mW/Q8LW54S4/lPxzmJLGUIkmS3w3RDhCrl5
4eIC5Dd1p0GCDN9M1ulME0Mb3RrLe1zQcTOeYMlLvYlOJoNWL/uEgQebktlHlaGS3Jnek5VTSvtW
6DZP5WHEnuKOz7SzX4Ef6V356oGg4/L+spA4zsLgPq5uil5H1suhvBxlIS2Oyia9vJ2q9asjEubH
nqtB1njH0OI+Z0iZRaWcXRaKbqob8HQgdO20/gvfmtZRzKdBOwNFoIQRQvHe+vtc/Qrp7cd+WZtu
hewSCpxkjDKLmpsHDO2E8PN9fKAwYtFHmAjYvwmNYPNOOODrE3yAvomSjOmW6h7yzSXIqgQWwyrx
AYiSmIJA7ICOh7r1ZAY1ewj0GPrV4JTmZnWNknca80Z3qCtDboT/i7Dpu3EUjl+QyYUC1/l2GYX1
+biUYg7n4nkIwC+3+SIu0jOR1oA3GPAiklOiHQlJty8X6r0dztiJo5+PU1PaPz62YpDniORlLncN
EEOvK6tPGZNrZC1NUVn10NI7RHUSf+VHG89tQYLnWEUQEh9Prfvf+zzQoiZPrDzxe5F488mV7KzJ
1WFw1k7rdd4bPnIMpPcY+bhF5Ubmq9gMcWlEL9M/xCtDuytqjPymPgWInh97sngQbMrLbYUJwbVb
VejbpbR+UlBc1y2mE9qFEymwSfIosKu0v/oyCt66g6YzJuuA7nucm/nZkYhYbuBNyz6mT0Rv+90b
1YLBrMkbE5024Xf/NXyIWK5x67Uya9gEaWo4eHsohURmjogfk5Xb1AuzAlQNuH3BfGeMaJsx0zfz
khikMA4KrNazXFpNoBUoeT0GG6+Q922NMkKCmI8nhiZS7CAeMxqhMZBSyJgYgaVc41DfyePmD/CA
xcXEvh/VGzO8UBHqBMLb4o9WTpb5tPWDBVJ7XRKIpdp/f89DePWpubN6inZroEJdg/H3ryQSD2+J
YyZBHFvha9qJFCegwvCD7GbnPRig5/myPFzboibWY+hcLHdH9im9h0rmma+feZRpGrtZHb/eINuJ
VG0RRs/SDpCM9MjkRAiV0nyIIBIo8fQyzUS+fnou3AKY1zJPXayzQV8sxONpEdr9GljbJ4dQkxuj
U9MZqGZVrAW9mpR6LLVeqFFaqcuGAxCFRwic4by3GbDafbv/SePd0M7BbpziRth47GPlea0pdQp9
lGc2UfbtU1IlJj664Q25fsAa/McE20KihaazTy7+bzKLxEmqGg5LQ6Ky5w01nPCd/E9M1aQORCIl
0SooGgFZzjyFcbjEwBraI6gp5iO9GlEawt7dr3c8oHFHjRB4RLDy+SHojRao3R5o7V4IRJRjfdx2
WIXvAzN+PMb8IfvdujjjarPxyQs+Zb56Fg7tYjPLJTBzqW0tZr6JjaCgAckBM2vpgV0fq3iAD9du
HkrKCoAwSqqIspTL+32I3D2vWvErViSoGzxCA92dlWiFNB2iQVZ+/lDKHAJrkP49CanWQZsTpgRC
OidtrQc5KwBQKTrXEAxVlRn8GCd2Ujh3x0c8QsDV0l6I9ekff2OtAYJvxtOx7hLVK9bA0SUL7FLD
WlkhGaW1DVJHu5p6aFG14J3OxHvPmLqYysGR2UU27FL9z7Zw9DHi95fLQkgfmnOY6YZ9cyEtUIR9
5DKuIcNL0HjWnlAaNqe9AJ4hQ1ptTh1aR+DaBfEzWrFSwNAVairRkenwB5ouvEzq0RO0+AlvakSV
eG9YNEi2g3NcxXXbIrIT936dKXoaO1oFWhGWHuEZ7vVvcs06PnA1b3vQqy3XW2Oq8PXGd2xIywaQ
Tlbb5M36MXwJT/PpoKlchJ4sMOsstZyZi35PuY9V6GpXAAripPhiUlJah69odnGBWi76Ar9ZIqgR
K1/qvy17BTxcnuEHMA4YWLRyeEV+mrGlABEnV+VCn9OE2ohAxHNMaOKC8cPhgr/URl05wMuGDkQL
SfO/09teIS0SqqLU3wNYgUx0nA6Zqm0myEFIBvnMROhtiO9mWMj+gp9N6OfXsl1lTa5x+wXwwgrY
yloN9QuKNS8YFgqwkIHylJzPLMQZ/QMZhmgDVsklDnpk9FKi/iyJAC0AheLyMrVklqp9GQbdakwb
BdgOCdYhhJN9e0gY0WHiMBAGCHPh9O0OEPJY0CZN1N7ONBthoGGofQ8AuQCJoa4CKbCYLvufLqgB
TRcLFgsbEDbtveCHSOCpprpjdoGRs+ujAKNo6gr/V3Qycrf8cBCP//jrHrpEAjSrSNcETK4SBQYY
3lyFIBA9PwoVwZJg9kLWoMH2hVvuoTuTjw+GjVv6bDAEPbnSVOiBSgU6rw0WZhabjCoCOJ/k6l/U
YjUiRGqbuvSnwdqjxPuyCAWkZL7QnhMC/PdRv0zR/0RNku4y8X4C9X372Ix4CQ38PDXPwDo9rIRP
HoRxBKERLV98xyXl4fuLOQJwyudwHjWtWbrl36dg6A49sgr3AFnFWkIV6QwRzK3AzMNSuV+fhWF/
AKNYvrJRVbyU7bGdbGtClbalGS+t1saE27pVlPBuXT4SSs9Gic1BWKyP7lnAQn0lPjozSLqaUwDj
0vLWLfLcY1esRqHxv8VH9wOiFmsTIBqU09Q4pMBEkZBp+9VtrsJlbDM8h1g5lGedpWjzT9usstbG
3LqUL8pwHivLrFRNpo4HvlKwRRxCDE1JUCsQPNvMEAVpgpWYKkRylgkM9+YUDCww/p6iD77rbNVq
1jGwB/FuUBfn/t8fF+okl+3iU0uD6oh0Vnd0kSD2gpXzgx/iXBv8Ft9lsgKyJVz7Ny13u7B6m4gI
07AI4MhfPvKftzaOTCYD4Mrzmf3prWIIXA37E7Vc05yOhPUFbCB60yHWThfFw6i/ECzBCPlsExGR
HtE3dwcBDv7mSugYYN9ILlBhA6cCHnyeWNkDlO5FF5nRbclp/YI/Ih7cV3cPLRqpHGqFN17j8wnk
Pl3TYIfbOIKr+dk76hcEiwqAf6ObXDYjaIAaBFHGjyWqOZf7tqyEZ5IssWrHchVq1CXuIVEXA4pn
n38HRT8cXskFyUtl7YsccXBxoDhXWtsqU1SfGosmT11PrftGLhg9XV2w5TuXtNKNxBQXqBZSGk4j
NTm7+6S3E7In5wtISQdqPnveMNnfcSAfpqKAoxz3HPiF6eYsLFKV5c4WyYcfn/NYXF67mRGAVAgv
8TUIfas/XvjSZTWc5RwIQFAB8HNlYOS3qlweZB1Z+WhMqrYdU1Pj6Z5jbyLGAwvTUgXbvSSJQ8p+
Nn3F6NKphRGsrEYtiK/oXJz7wUfz5DZH0LPausa6etIvrNY9VAqSvz3LY/qcGyMztS8zYxIsGyEQ
5RGEng+hXWE5oVUZ6e7OeaWKrwz9E7AvZ+pxtN1nhh/fXPfQQQwrPK4NnzIS7nQO2JCnhIUoJobV
DGcyHxXNL9CPwxHs4JMmsfiF1P7qJCjqkyoN/U8rw4kfggj9DFtkM2D/wBXDdixsFhWZ2mQjM/AZ
2H+3arilKGvMwWynpzefd/ben9xZoDv7gN1rjZn1GxIhGTNeNM+ShQ5K/TIE7hGp7sgJFaK8PDTN
nqnDopPzRotnjQDKm8zAHLFzEPS7xteKP1gAI/+/vLnBcFH65J0uK96kF1eX4FciKvDf109s/UbK
uXhliNVJsAqGgA2oZ7nwp0prwIkb8Nd3Kloh8iSSoh+x3RiWxveRnThI7ob1mL5trFO+Y09+0prE
NH+47WXjY+n6lR2WKfcWX3ZLJ4q3b/9oSHf1aW80R6lIfZsMXSBjCvvWoeLnEbfxi8BOj0UtMmhp
dv9fPz01Ra3xkgAEtgDuEZRf4ic6/NysC2Iuv7A2QDWp+Oqx3Nl8aS0XyByhcVYe2muWAWjkoUQk
0iYLehu7pZjhphhEqo5cMyHiZD4GCDYl1p6GWKpePdWzVXmHPLaG0ofMro6f/lr32uoJqHquga7i
du6NSp7+lf8E4a+b3ZH1PucwZO2rfAV3qSEDll3pxvAwbZW3bKnWpFw3DemHuXCctKEHOvBO11NB
0qGglXZ1cG1wB8aTbtSaiG9w/lK/DK814gSHH3w7SqWMNRmKd8QnmNVDDSJTaUOIvpR6vN9LwndV
F6XlpiRSIZGz3QEOOyd3NFoX/p1H20iU+mgBgtVdCcja5ZQJ5i0Nq77aguizCEZHv7CmhDLji+gq
DzvE2jzJm7g1YolmqMt4qScKS0HZYEmRAXRSBAQaVaIw/sAFrKHiJMWrfCOxGUC1dU0OVmSvEmru
M97htYepv+GmAFrRvf1e/vxODh6NA5Qu3jiGq9qfvgH1geBmpQt1avKzBUHkI0fdVc3N+Qq3bzaE
uCWa16EQ/lncraE38f/3t1qZsD5hgpGfn9obzdWYftXjexu2KKm4D2RKpfnDpuFaqEcu5WlQM6RP
Oblr8lvyorSJTfgWT9X0kEvPic/bUMOG5gbDPU5pa6/Spuj8fikA1kw0mfrp0hOlOElDO6SAppOm
GMFHxEcSw6bnehAlkeqfHduFZu5Pv2wd+B9lOdexVQFl3103WHHBb/kznkSoxUjDlCHS+1hADXfS
R8ib3eO1L9x9S+i3xSSQ8C7CVgXWaN6rX0OFcxaufbRv7iemGDJMsnF/6WrMMEO4N7CNuk+hWwJ3
aE8F4IH01cIdM34K71ej+eQ7qwH6pGz8olTRsz5sdUI33SWrNEhOcy4VMpZh9doHHyYglw7PqVBd
+3U3NtWU8H2Lek9EacV6Xo52tPYkmvCtp5fR2SpK/PLFqlN9iBUV6Nv5cqpgrz5fGqyya9UZSdcH
H6UJYxrWAm4dXeyRbHrGqNipScPUbgmTyhyz3t/avU+06pvkeWUPB1gCIVgr8UccfheI7W8o/cQv
TBfWnmK1BwhP02Z2dRkqjlIY++JAiw7l3ZqFvL6wAGqhQAyI35wYV/tAlYQNoZhXkMVmBv+eCAJQ
BT1mI5FMK+tZGrc9eqi6fOmos1qO7mTAHN6C+uQlPcnozTRQIqNVVlPm/9IeUrPlq8Kw4OT7P4JZ
nBROhn0wNnBxNCJ39zIxGVFB32Oc47sCBb8KjWt1IB3QTSHkBqSTnAPV6MS4P5PxOgPHIpujFJEH
/s+PQCXQfbbCNBpUFq77O/890v5ma1D343ohLe07PNj8nwZrSBt5PBNwKif1Z7WmfqeOEdjfxiSx
VTdUfYcsk53HejLV/hSNaNpc+wM2SoeT8xeCCoCaCenR7C94LNRcbswjRcIForG7jNWJqVVhK93S
S+RUWyIicnQOMjSHZJE2SqxOJofxhfjmSBTOVHBSS2N+wB4L9rFOrU5metz0MEt8WVJGlAJT8lhY
p4VbO8A88zRuISkQsk+SwQnoAnQ/JxWvvjIah5mjNl63q5D0vURsHY8o5FN5rr7zH5Tev5U++f4l
PkNXpKnh32UIeKt/eB5fib/ZR4T9pYKYwbTv0s29gR/VqcRK9FkiehEOsaMrUmC/7SXg4h05sxpr
Nbw9jousGEg48IZMs6HSVC+i3C9Hsg3gpwSohs8JRgW/B9RQiYpJAZOba2VOWQ1cg6mQrd3f3k8M
yeswSdfNeaq4DKx892Z/wfMJSskCeDAvgSMpzLvUvmqCxHjmxFQZ14loZPqCaJ1ZDBGX/nnu5RsY
HEBlCvOVENbFk3f0HdGNGPo+gU4wFLZKpA9nMeD/n7rsuqYz84LtGGK8ZOltCQzkL+QLhHeVFQ2N
Y3CEf5CgiMaOwHJqz7Rrma/X1zkXP7jZHlbckZMSrYlvQT6lnnvm0qbl8lQfa7cO8j3/HV/k5Q7/
6UoDqbpo8JTJpYCYg/qPV4+IUn9NsBcXglYDf0wu3WgDB1J+NqzziNqEli8m1wtNmDzS2Y8TZM3O
3xNAzVzliy+balx8MaHjZISolw6Dd6avS/SVSFQNR5G3YKz/UWWFwERGvzanilYzYcEtM+MMYbKq
j9qEI1FgP0WgWKr+buDod+/nbeTlQ5GLFz3wjYA79Xz3G6zGvFp/5/KTACz2OaiOtilB8O+InZa9
1CS2DNdWCDUnjzNbCNfrQW9hcTMIze+QgwrCzn7H+74y2uuQNG2uP7ThJIJfKnlXd+64YdfzcP3U
GsUPmktdoLl8F3DyGH+tYUgiNNpMGL6imAC70RL+V0BH+71evbNBNJ0bOmZJaSjyI67PLZZ5dYES
WGQjmMkDwoPf/Krfd+pkZSCxjmgp2inRdpbvPp/KIDKRUtyO7mzDxepkMuR6t5Qei8v3va2eDWye
KqsmZy1Cu/4nCnqQkWKqdk3l/HvGYj9mLTS8s1CWFXXgaovJFWDfL/51v+XhGj5hDnt/vjDhHMMy
8jodu/hWntTpQEzzF6HSm2Co1m+bMD7eT+OzSUs+D8Mycvk5B13kxSW/K2QvWM+LbXuVipe3KX52
t0A1RPuW8wZCuRQ+RcEat2GcmfxY39wTf4dHUpioZ87YcspnbTRf9FoCv6Je/8sSbcZz2gQOGF4q
7fULF4M2YGt2soWsMqnLU5L8ZN1/YzXq6LgOQtIcjMbWBiCn5+fGxKAE58r6vfVHXxNJ9N1aYti+
wjPH3MQ/l+h5/icM4vXBPAZ/SsKoZQkuAmY5MpJltN+wOtPogmkNJI54WUtW9Mvn9oa7z5Iadeze
XuzTOMFcTfuQ97P9s/SzBPU4f8JIPetRuV/1jWJxdBeUAmsFfOawL4M2pMyWMoAb0RpROZKh61cK
OB5Z5JevhLHGV3WeYRzFXXV1BEdJrfwSZOeEsB4IYC+w7+fqApC9kmO3CZWxz7vv4hywy8GvFMXl
jC3r5sh4E+DDgt8gZ6I+XigvOBqQFAiub78QqoUHqM0PZJXL2dSfiR+jEVMPA5xabVp0zJ+Fvsu4
8fbXHBbfIeVTNu1Ds8OcuDzX/XmkBVk1kR3Bgxpxuf3u+z8jAfSQgXo5t/2dqRryPiUX1fse5oRH
3MC0DRs3uOylqj/hJyG4ifgbEs+ugrjpnQHZqDJ2KxJSqD3+56Fkg90m/FUC8ScreaF6ffi3Hqmp
CEP80gV4JIpnRPfTCK0wEVJkGuZbJ36gjoKxKjXPelDqcOugeGqhHSHYLomhE7XHgQNmb51BJOS7
5EC0bjiegl4vVliGUSXkF8r6YdWlmADbLm5maooAWvbRae3N4nPhM7uIIw5hYgdR9tMxcx9bB+4t
Qiehyrn8EILfNsJAdfam3xNvWmttusfTkBxbfaGRDx3oFM1Yp6sT6aYVB7Op7EZ6DlA/D4bHFHfZ
tqasUfkLKt8mKx6yf3U4FwZuv1PrECA3gzpzIoLKyC0IPgMQH57o8AktnMDYTlEeqyM6zIDoRM+i
xD9BrEPNgO08VEzEw5vwq2Ph+xeIsVwbVU6QP/P9Py6nFoalJg5oGEjV3pqpHPjYbg2Hi9padcDa
ulfe0VaFS37pxMlhZp88w0ViliK4zVimfHduj/eHLPZmWxQq7fI4kqrbV0TbU+W5xpnYQrbq6RPr
DQpporBZoY+rfNyuh/uM3Pd8cq1exV1b/dmsbRn/emss0Rm+b32PRw8mg6ttuvgNzi6NMeXWfutF
OOnoLPOIhbVCGLZNoDoyRGDFR85otDNkMj6xETs9V/4IIgF/iGKRjBr7ZPw5Qs8Zv+wWX6GnBDIV
2GF0VVlipDHO8RvzJN1utNgvQNAsTADLSszLPHoN5ysgu7VGR4fCm/OK212o4c2j2QLZRW7OAO9K
gJAJOGvlPuAeRgBJKIRvhQpSmaZG3SsrpZxYVVQTkDUR
`protect end_protected
| mit | 9766e70a84cfc1e0be01ac52147af3a0 | 0.945508 | 1.827691 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/if_statement/rule_002_test_input.fixed_parenthesis_insert.vhd | 1 | 1,554 |
architecture RTL of FIFO is
begin
process
begin
if (a = '1') then
b <= '0';
elsif (c = '1') then
b <= '1';
elsif (a(3 downto 0) = 0) then
b <= '0';
elsif (a(3 downto 0) + f(34, 56, 72) - g(f(35, 25, 60) downto h(45, 32))) then
b <= '1';
elsif ((a or b) and (c or d)) then
b <= '0';
end if;
-- Violations below
if (a = '1') then
b <= '0';
elsif (c = '1') then
b <= '1';
elsif (a(3 downto 0) = 0) then
b <= '0';
elsif (a(3 downto 0) + f(34, 56, 72) - g(f(35, 25, 60) downto h(45, 32))) then
b <= '1';
elsif ((a or b) and (c or d)) then
b <= '0';
end if;
end process;
process begin
if ((x(k) = '1') and (v_y = '0')) then
b <= '0';
end if;
if (((ctrl_done_d1 = '0') and (CTRL_DONE = '1')) or (dev_addr = dev_addr_prv)) then
b <= '0';
end if;
end process;
process begin
if ((sync_reset) = '1') then
b <= '0';
end if;
if(a='1') then
b <= '0';
end if;
if( a='1') then
b <= '0';
end if;
if ( a='1') then
b <= '0';
end if;
if (a='1')then
b <= '0';
end if;
if (a='1' )then
b <= '0';
end if;
if (a='1' ) then
b <= '0';
end if;
end process;
process begin
if (something) then
b <= 0;
elsif (something_else) then
b <= 1;
end if;
if (something) then
b <= 0;
elsif (something_else) then
b <= 1;
end if;
end process;
end architecture RTL;
| gpl-3.0 | 60661e019b4bd0f78f0ca396df8ac4b5 | 0.427928 | 2.846154 | false | false | false | false |
siavooshpayandehazad/TTU_CPU_Project | pico_CPU_pipelined_MIPS32/DPU.vhd | 1 | 3,292 | --Copyright (C) 2017 Siavoosh Payandeh Azad
-- DPU has one fixed input which is coming directly from Register-File
-- The other input is selectable between Rfile, Memory, Control
library IEEE;
use IEEE.std_logic_1164.all;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_misc.all;
use IEEE.Numeric_Std.all;
use work.pico_cpu.all;
--DPU entity
entity DPU is
generic (BitWidth: integer);
port (
rst: in std_logic;
clk: in std_logic;
Data_in_mem: in std_logic_vector (BitWidth-1 downto 0);
Data_in_RegFile_1: in std_logic_vector (BitWidth-1 downto 0);
Data_in_RegFile_2: in std_logic_vector (BitWidth-1 downto 0);
Data_in_control_2: in std_logic_vector (BitWidth-1 downto 0);
ALUCommand: in ALU_COMMAND;
Mux_Cont_2: in DPU_IN_MUX;
DPU_OV : out std_logic;
Result : out std_logic_vector (2*BitWidth-1 downto 0);
Result_ACC : out std_logic_vector (2*BitWidth-1 downto 0)
);
end DPU;
--Architecture of the DPU
architecture RTL of DPU is
---------------------------------------------
-- Signals
---------------------------------------------
signal ACC_in, ACC_out: std_logic_vector (2*BitWidth-1 downto 0);
signal Mux_Out_1, Mux_Out_2: std_logic_vector (BitWidth-1 downto 0):= (others=>'0');
---------------------------------------------
-- Flags
---------------------------------------------
signal OV_Flag_Value, Cout :std_logic := '0';
begin
ALU_comp: ALU
generic map (BitWidth => BitWidth)
port map (Mux_Out_1, Mux_Out_2, ALUCommand, OV_Flag_Value, Cout, ACC_in);
---------------------------------------------
-- Registers and Flags
---------------------------------------------
CLOCK_PROCESS:process (clk,rst)
begin
if rst = '1' then
ACC_out<=(others =>'0');
elsif clk'event and clk= '1' then
if ALUCommand = ALU_MULT or ALUCommand = ALU_MULTU or ALUCommand = ALU_MTHI or
ALUCommand = ALU_MTLO or ALUCommand = ALU_DIV or ALUCommand = ALU_DIVU then
ACC_out <= ACC_in;
elsif ALUCommand = ALU_MADD then
ACC_out <= std_logic_vector(signed(ACC_in) + signed(ACC_out));
elsif ALUCommand = ALU_MADDU then
ACC_out <= std_logic_vector(unsigned(ACC_in) + unsigned(ACC_out));
elsif ALUCommand = ALU_MSUB then
ACC_out <= std_logic_vector(signed(ACC_in) - signed(ACC_out));
elsif ALUCommand = ALU_MSUBU then
ACC_out <= std_logic_vector(unsigned(ACC_in) - unsigned(ACC_out));
end if;
end if;
end process;
---------------------------------------------
-- ALU Input multiplexer
---------------------------------------------
Mux_Out_1 <= Data_in_RegFile_1;
INPUT_MUX_2:process (Data_in_mem, Data_in_control_2, Data_in_RegFile_2, Mux_Cont_2)
begin
case Mux_Cont_2 is
when MEM => Mux_Out_2 <= Data_in_mem;
when CONT => Mux_Out_2 <= Data_in_control_2;
when RFILE => Mux_Out_2 <= Data_in_RegFile_2;
when ONE => Mux_Out_2 <= std_logic_vector(to_unsigned(1, BitWidth));
when others => Mux_Out_2 <= std_logic_vector(to_unsigned(0, BitWidth));
end case;
end process;
Result <= ACC_in;
Result_ACC <= ACC_out;
DPU_OV <= OV_Flag_Value;
end RTL;
| gpl-2.0 | 4d15ec7e5dfd3e5aeb3a18374bcce3ce | 0.555286 | 3.551241 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/case/rule_015_test_input.vhd | 1 | 589 |
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_1;
PROC_2 : process (a, b, c) is
begin
case boolean_1 IS
when STATE_1=>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_2;
PROC_3 : process (a, b, c) is
begin
case boolean_1 Is
when STATE_1=>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_3;
end architecture ARCH;
| gpl-3.0 | 5074b98b41f725147479441f3ec5c891 | 0.4618 | 3.308989 | false | false | false | false |
Yarr/Yarr-fw | rtl/spartan6/rx-core/decode_8b10b/decode_8b10b_lut.vhd | 2 | 7,895 | ---------------------------------------------------------------------------
--
-- Module : decode_8b10b_lut.vhd
--
-- Version : 1.1
--
-- Last Update : 2008-10-31
--
-- Project : 8b/10b Decoder Reference Design
--
-- Description : LUT-based Decoder for decoding 8b/10b encoded symbols
--
-- Company : Xilinx, Inc.
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
--
-- History
--
-- Date Version Description
--
-- 10/31/2008 1.1 Initial release
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
-----------------------------------------------------------------------------
-- Entity Declaration
-----------------------------------------------------------------------------
ENTITY decode_8b10b_lut IS
GENERIC (
C_HAS_BPORTS : INTEGER := 0;
C_HAS_CODE_ERR : INTEGER := 0;
C_HAS_CODE_ERR_B : INTEGER := 0;
C_HAS_DISP_ERR : INTEGER := 0;
C_HAS_DISP_ERR_B : INTEGER := 0;
C_HAS_DISP_IN : INTEGER := 0;
C_HAS_DISP_IN_B : INTEGER := 0;
C_HAS_ND : INTEGER := 0;
C_HAS_ND_B : INTEGER := 0;
C_HAS_SYM_DISP : INTEGER := 0;
C_HAS_SYM_DISP_B : INTEGER := 0;
C_HAS_RUN_DISP : INTEGER := 0;
C_HAS_RUN_DISP_B : INTEGER := 0;
C_SINIT_DOUT : STRING := "00000000";
C_SINIT_DOUT_B : STRING := "00000000";
C_SINIT_KOUT : INTEGER := 0;
C_SINIT_KOUT_B : INTEGER := 0;
C_SINIT_RUN_DISP : INTEGER := 0;
C_SINIT_RUN_DISP_B : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC := '0';
DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;
KOUT : OUT STD_LOGIC ;
CE : IN STD_LOGIC := '0';
CE_B : IN STD_LOGIC := '0';
CLK_B : IN STD_LOGIC := '0';
DIN_B : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DISP_IN : IN STD_LOGIC := '0';
DISP_IN_B : IN STD_LOGIC := '0';
SINIT : IN STD_LOGIC := '0';
SINIT_B : IN STD_LOGIC := '0';
CODE_ERR : OUT STD_LOGIC := '0';
CODE_ERR_B : OUT STD_LOGIC := '0';
DISP_ERR : OUT STD_LOGIC := '0';
DISP_ERR_B : OUT STD_LOGIC := '0';
DOUT_B : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;
KOUT_B : OUT STD_LOGIC ;
ND : OUT STD_LOGIC := '0';
ND_B : OUT STD_LOGIC := '0';
RUN_DISP : OUT STD_LOGIC ;
RUN_DISP_B : OUT STD_LOGIC ;
SYM_DISP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;
SYM_DISP_B : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END decode_8b10b_lut;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
ARCHITECTURE xilinx OF decode_8b10b_lut IS
-------------------------------------------------------------------------------
-- Begin Architecture
-------------------------------------------------------------------------------
BEGIN
----Instantiate the first decoder (A decoder)--------------------------------
deca : entity work.decode_8b10b_lut_base
GENERIC MAP (
C_HAS_CODE_ERR => C_HAS_CODE_ERR,
C_HAS_DISP_ERR => C_HAS_DISP_ERR,
C_HAS_DISP_IN => C_HAS_DISP_IN,
C_HAS_ND => C_HAS_ND,
C_HAS_SYM_DISP => C_HAS_SYM_DISP,
C_HAS_RUN_DISP => C_HAS_RUN_DISP,
C_SINIT_DOUT => C_SINIT_DOUT,
C_SINIT_KOUT => C_SINIT_KOUT,
C_SINIT_RUN_DISP => C_SINIT_RUN_DISP
)
PORT MAP (
CLK => CLK,
DIN => DIN,
DOUT => DOUT,
KOUT => KOUT,
CE => CE,
DISP_IN => DISP_IN,
SINIT => SINIT,
CODE_ERR => CODE_ERR,
DISP_ERR => DISP_ERR,
ND => ND,
RUN_DISP => RUN_DISP,
SYM_DISP => SYM_DISP
);
gdecb : IF (C_HAS_BPORTS=1) GENERATE
----Instantiate second decoder (B decoder, only if bports are present)------
decb : entity work.decode_8b10b_lut_base
GENERIC MAP (
C_HAS_CODE_ERR => C_HAS_CODE_ERR_B,
C_HAS_DISP_ERR => C_HAS_DISP_ERR_B,
C_HAS_DISP_IN => C_HAS_DISP_IN_B,
C_HAS_ND => C_HAS_ND_B,
C_HAS_SYM_DISP => C_HAS_SYM_DISP_B,
C_HAS_RUN_DISP => C_HAS_RUN_DISP_B,
C_SINIT_DOUT => C_SINIT_DOUT_B,
C_SINIT_KOUT => C_SINIT_KOUT_B,
C_SINIT_RUN_DISP => C_SINIT_RUN_DISP_B
)
PORT MAP (
CLK => CLK_B,
DIN => DIN_B,
DOUT => DOUT_B,
KOUT => KOUT_B,
CE => CE_B,
DISP_IN => DISP_IN_B,
SINIT => SINIT_B,
CODE_ERR => CODE_ERR_B,
DISP_ERR => DISP_ERR_B,
ND => ND_B,
RUN_DISP => RUN_DISP_B,
SYM_DISP => SYM_DISP_B
);
END GENERATE gdecb;
END xilinx ;
| gpl-3.0 | e72af2bf9666b913b390c204e35dd852 | 0.449525 | 4.063304 | false | false | false | false |
spzSource/MPFSM.RegFile.Sort | MPFSM_RegFile_Sort/MPFSM_RegFile_Sort_Design/src/ROM.vhd | 1 | 3,227 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use commands.all;
entity MicroROM is
port(
read_enable : in std_logic;
address : in std_logic_vector(7 downto 0);
data_output : out std_logic_vector(27 downto 0)
);
end MicroROM;
architecture MicroROM_Behaviour of MicroROM is
subtype ram_address is std_logic_vector(7 downto 0);
subtype op_code is std_logic_vector(3 downto 0);
--
-- type and sub-types declarations
--
subtype instruction is std_logic_vector(27 downto 0);
type ROM_type is array (0 to 255) of instruction;
constant I_ADDR_MAX : ram_address := "00000101";
constant J_ADDR_MAX : ram_address := "00000110";
constant I_ADDR : ram_address := "00000111";
constant J_ADDR : ram_address := "00001000";
constant ONE_ADDR : ram_address := "00001001";
constant ZERO_ADDR : ram_address := "00001010";
constant TEMP_1_ADDR : ram_address := "00001011";
constant TEMP_2_ADDR : ram_address := "00001100";
constant TEMP_3_ADDR : ram_address := "00001101";
constant Z_ADDR : ram_address := "11111111";
--
-- Represents the set of instructions as read only (constant) memory.
--
constant ROM : ROM_type := (
ADD_OP & ZERO_ADDR & ZERO_ADDR & I_ADDR, -- 00000000
ADD_OP & ZERO_ADDR & ONE_ADDR & J_ADDR, -- 00000001
SUB_OP & I_ADDR_MAX & I_ADDR & TEMP_1_ADDR, -- 00000010
JZ_OP & "00010011" & Z_ADDR & Z_ADDR, -- 00000011
ADD_OP & ONE_ADDR & I_ADDR & J_ADDR, -- 00000100
SUB_OP & J_ADDR_MAX & J_ADDR & TEMP_1_ADDR, -- 00000101
JZ_OP & "00010000" & Z_ADDR & Z_ADDR, -- 00000110
LOAD_FROM_INEDEX_TO_ADDR_OP & I_ADDR & Z_ADDR & TEMP_1_ADDR, -- 00000111
LOAD_FROM_INEDEX_TO_ADDR_OP & J_ADDR & Z_ADDR & TEMP_2_ADDR, -- 00001000
SUB_OP & TEMP_2_ADDR & TEMP_1_ADDR & TEMP_3_ADDR, -- 00001001
JNSB_OP & "00001101" & Z_ADDR & Z_ADDR, -- 00001010
LOAD_FROM_ADDR_TO_INDEX_OP & TEMP_1_ADDR & J_ADDR & Z_ADDR, -- 00001011
LOAD_FROM_ADDR_TO_INDEX_OP & TEMP_2_ADDR & I_ADDR & Z_ADDR, -- 00001100
ADD_OP & J_ADDR & ONE_ADDR & J_ADDR, -- 00001101
ADD_OP & ZERO_ADDR & ZERO_ADDR & ZERO_ADDR, -- 00001110
JZ_OP & "00000101" & Z_ADDR & Z_ADDR, -- 00001111
ADD_OP & I_ADDR & ONE_ADDR & I_ADDR, -- 00010000
ADD_OP & ZERO_ADDR & ZERO_ADDR & ZERO_ADDR, -- 00010001
JZ_OP & "00000010" & Z_ADDR & Z_ADDR, -- 00010010
others => HALT_OP & "00000000" & "00000000" & "00000000"
);
signal data : instruction;
begin
--
-- Move instruction to the output by specified address
--
data <= ROM(CONV_INTEGER(address));
TRISTATE_BUFFERS : process(read_enable, data)
begin
if (read_enable = '1') then
data_output <= data;
else
data_output <= (others => 'Z');
end if;
end process;
end MicroROM_Behaviour;
| mit | a0c722ac36080111e4f3eda1cc926eed | 0.561202 | 2.909829 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/case/rule_014_test_input.vhd | 1 | 589 |
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_1;
PROC_2 : process (a, b, c) is
begin
CASE boolean_1 is
when STATE_1=>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_2;
PROC_3 : process (a, b, c) is
begin
Case boolean_1 is
when STATE_1=>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_3;
end architecture ARCH;
| gpl-3.0 | f062134ffca625e780d1a44501c64dff | 0.4618 | 3.308989 | false | false | false | false |
rjarzmik/mips_processor | Control/Control_Decode_Dependencies.vhd | 1 | 4,919 | -------------------------------------------------------------------------------
-- Title : Decode dependencies
-- Project : Source files in two directories, custom library name, VHDL'87
-------------------------------------------------------------------------------
-- File : Control_Decode_Dependencies.vhd
-- Author : Robert Jarzmik <[email protected]>
-- Company :
-- Created : 2016-11-28
-- Last update: 2016-12-14
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Dtall the decode (Read After Write)
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-11-28 1.0 rj Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.cpu_defs.all;
-------------------------------------------------------------------------------
entity Control_Decode_Dependencies is
generic (
NB_REGISTERS : integer
);
port (
clk : in std_logic;
rst : in std_logic;
-- Decode source registers
signal rsi : in natural range 0 to NB_REGISTERS - 1;
signal rti : in natural range 0 to NB_REGISTERS - 1;
-- Decode to Execute
signal i_di2ex_reg1 : in register_port_type;
signal i_di2ex_reg2 : in register_port_type;
-- Execute to Memory
signal i_ex2mem_reg1 : in register_port_type;
signal i_ex2mem_reg2 : in register_port_type;
-- Memory internal pipe
signal i_mem2ctrl_stage1_reg1 : in register_port_type;
signal i_mem2ctrl_stage1_reg2 : in register_port_type;
signal i_mem2ctrl_stage2_reg1 : in register_port_type;
signal i_mem2ctrl_stage2_reg2 : in register_port_type;
-- Memory to WriteBack
signal i_mem2wb_reg1 : in register_port_type;
signal i_mem2wb_reg2 : in register_port_type;
-- Writeback to Decode
signal i_wb2di_reg1 : in register_port_type;
signal i_wb2di_reg2 : in register_port_type;
-- Dependencies
signal o_raw_detected : out std_logic
);
end entity Control_Decode_Dependencies;
-------------------------------------------------------------------------------
architecture rtl of Control_Decode_Dependencies is
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
begin -- architecture rtl
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
o_raw_detected <= '1' when
(i_di2ex_reg1.we = '1' and i_di2ex_reg1.idx = rsi) or
(i_di2ex_reg2.we = '1' and i_di2ex_reg2.idx = rsi) or
(i_ex2mem_reg1.we = '1' and i_ex2mem_reg1.idx = rsi) or
(i_ex2mem_reg2.we = '1' and i_ex2mem_reg2.idx = rsi) or
(i_mem2ctrl_stage1_reg1.we = '1' and i_mem2ctrl_stage1_reg1.idx = rsi) or
(i_mem2ctrl_stage1_reg2.we = '1' and i_mem2ctrl_stage1_reg2.idx = rsi) or
(i_mem2ctrl_stage2_reg1.we = '1' and i_mem2ctrl_stage2_reg1.idx = rsi) or
(i_mem2ctrl_stage2_reg2.we = '1' and i_mem2ctrl_stage2_reg2.idx = rsi) or
(i_mem2wb_reg1.we = '1' and i_mem2wb_reg1.idx = rsi) or
(i_mem2wb_reg2.we = '1' and i_mem2wb_reg2.idx = rsi) or
(i_wb2di_reg1.we = '1' and i_wb2di_reg1.idx = rsi) or
(i_wb2di_reg2.we = '1' and i_wb2di_reg2.idx = rsi) or
(i_ex2mem_reg1.we = '1' and i_ex2mem_reg1.idx = rti) or
(i_ex2mem_reg2.we = '1' and i_ex2mem_reg2.idx = rti) or
(i_mem2ctrl_stage1_reg1.we = '1' and i_mem2ctrl_stage1_reg1.idx = rti) or
(i_mem2ctrl_stage1_reg2.we = '1' and i_mem2ctrl_stage1_reg2.idx = rti) or
(i_mem2ctrl_stage2_reg1.we = '1' and i_mem2ctrl_stage2_reg1.idx = rti) or
(i_mem2ctrl_stage2_reg2.we = '1' and i_mem2ctrl_stage2_reg2.idx = rti) or
(i_mem2wb_reg1.we = '1' and i_mem2wb_reg1.idx = rti) or
(i_mem2wb_reg2.we = '1' and i_mem2wb_reg2.idx = rti) or
(i_wb2di_reg1.we = '1' and i_wb2di_reg1.idx = rti) or
(i_wb2di_reg2.we = '1' and i_wb2di_reg2.idx = rti)
else '0';
end architecture rtl;
-------------------------------------------------------------------------------
| gpl-3.0 | 17ce37627eb54cae0f14e7ff6066cfa3 | 0.451718 | 3.577455 | false | false | false | false |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/cascaded_integrator_comb/cic_compiler_v4_0/hdl/int_comb_stage_unfolded.vhd | 1 | 37,452 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
gP1Bu4dA0S9mdgrgtx9yJFWj9+XAaHZSccCJsWMCAXCJsAA0PUiZuxLF564RcZjdoHzyweWCcYZ4
JbTs8j7AyQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
CQN6Zkth+TWvd44PPdEyAC1pnrLKeSt7I7CXykuYBxrVvZFOmcGVcS4imcXhjMq4kKHK2CwwrmZK
VdmHARVxk0JZQ62d61gXdf/EXJcLXtV7U+VVsJyXmfmY4caQDacYMmGNSmKs3Q8ByLwg5v2HcwHj
W53rqRe63Vd7WvNUNAE=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QpM9umwLPZ/zaRSLkL9V5PgFe9s4uZtEkVX23GPlRyiBGwME3JN40Q5bItsLllBhG+QqAp6Dodpw
zajhlZt0O4pfCvzqDHIE0MGmnTwhSm8lyKnIv+pQJ0viWj8XQTzcn3Pl8vfnHvJRXNhMqqUM1ClM
YrnIYTNG/n1PuTmKGf5yTbUSya9RfjaMBX4AiYm1DWvj7qISAMumXztaOqCMYM+gJbM2iR+EioQk
qd4GgATgha1FZiX/SdrV0DaVaYSpxZjWAahkKm0cTZ9Rhgol5dIIjUWmTZIn5JDf9VJCz+EJHm9Z
PA2Ea7lCPeKqCtlc/HYNVt5xls5/lET9hBZvww==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
tWrIIaOsvVxMUWwLlDi3uYAnKe7XS6oe0fV2SkNzNof/HLs06OpvFogWdDdUFTqCCjUj9P0Xnl+C
KqrmODJvc3d8SPt634z7/C+KsMago5tCRdEZIFhzuEl4Q17/0QCHLieDQV89sFopQ67TFaQuVELc
yINyvBRpThWviTl/bu8=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
h+A63wGrXAvSpcMhf9OAdqqBj7IGkCXV/JhsOSibpMkJI5N1ldImrA+lwTUmGp+4r1O+ljDYXyws
uvOmWDoEi+K8WmPc5gvxpOi2gJjnhaHRICekBCIQviHTQ0FfqLYaZtayUoy1P6efsarqFGebD82I
KUOlgvjnF9th3JvILEyZvW+gvvuX1rln3u7+Grc5543eXtzmkunhQ5Dz/32ZgWt7OrmDLPCgqep4
sBMersq8WYPmqu4fwPzd87axItgM1x/qaP2dFVSMqqXaBQdjXD6W7y8vZiKvTW72P0iWQKUE+Ve7
XWGys6saSeNukFqeggwRFON/OrREcb05bcBEmg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 25984)
`protect data_block
W+uZPmfaSC2qzKAMG8y0QcU7G6/+0x5Keu9Eo96cD4yuUmqB17W4//uc4DzSgNuKHYtBDNo7VRUz
PU94eClZ/gC07a2lCMOl2f/QG0ivHW8kU1WoYe9vbAXkkUipOka4ctY7VQnQ69pesllJMAv4iOEY
/syR+3/QHZGCaKpJeGZZDyuofcYBuYKtiVPDCa+PjpUAMUFCbxqoSyqiO733uU8jitfs914UuK7R
BH2BtpsrfFVPyyp0SWA/URbgvtxiQ8faCFRt7qj+n27KHVtrkIukNIlyDzi7y20X4qTkoCQ/A8Do
MBwqlZYjGnQaoSpNSRagZ4CPAsC0UsbsFAcM207zISbeXgT16i53XGEB0/OD5ZAmA3QSyM31IZao
i82NY2pToAO/Yh5Q7DdlBsI3GchE5kfJ0t5ahvLoMgV3DMqCfujWJH7xN7o1LceMeoLiHY/KI01V
ebV4Mkx9EAv+hdTyYPniAmVjA2vJqJuTc5VmCUtKRM6XafgEjZUUrhIuiL4mmTQP0b6v1E4E5lOo
w6CqD8XYPwj+pZr20yBx8+p3zIPsmmWYcPKQ/hkGR2ELIKgzR2DyX1QlZWy3M04kBh/oLmpo4F6N
k4u3g4aGzlrp9fDGSPEiY0vSijB0J5Lz6Vsi3ovEiLEvcmhunRXNQE4G4KZD4resFSqoQbjqQer9
bZqSpSf55cHC7ptwxVAojNZchuSdHBChx/6034yS8ztnAeVKBgwjXH9aJUMWPAY/D8fG3ONR9vC5
lqx8+gKD3y3hLzdu3LD9eiQAjBnb/tnzKfGardTxlRgIarKkx2x6XOrs3NJJ1DXUr+rXNNyTAgkT
sbX1UTS3Fqsdj/4hdMNpKPUbyY9Ax2hxOcYfwWP2zmTlT1qWZ2hVh5ZryfclbFhy4JcdMQPLambg
ncnL/xIKDGQcjR4hSSzHcyEagRwJb9W2eXFfxiPSWaOmGys2c1Lb1Txih22622QTsXpUePZDd9B0
z9GZx797wa4iE1ymOTYC5AP6vGW4gez/hPDcJW7jTtwsXEvX7fyRf5TwugRG4dMHR4oSkqB41vEj
7AoYNaA7czyw72JNIrbaUWfX/9wB+C+SXJRdr/S4XWud9rABvhy6Cg7dnwzjxUR5sj+k1AI6WcX7
INXEsWJAdHHu2itdp7BjYg3t5vLgd+nEW3q8IMeSND+wVYN2tQvYjL+CHIJD6yZ873hFozOn6iR8
TaqosO/HFzI8108XcTRk6BgS8W4/doBvguCNHc/Ryg6r2ykAB9RLaLLBuzQKbLZfXY9+PUvD4Acx
4fKt34A6eHfxoFsY+YvvTJCzPlcJXId9hZ7Df+egjFQxQ7Ygebfz9dzpGNvjQrLG6+oogmorU0cY
rJvzeJl1TMswOnuvPlGYDa5C2+sqn0OiL9qXCILZ+I7V2ihimIoUCVsPwjH3BBdupg7VIte4VffV
oJgBhiFq3x1paJHwSZ1geRM9DU6W1IuUm63Np5ynDoYAX+ujadcglSg1RboNuvwqfUGKrWkyp7RK
pxSJ3LA8gbqTkkZwTNlo9HRvNYrkvgUpmkJeWVetnjzv3ACyCqRkorpPt5J/STGtCotJQufP8dkV
M48m9nfvCP7uFaxnFZYf4WP3Or9NSFRDKxGh/h8/olcweD/Q8VnlXXWENVUaQdz325ZASBgvarta
nZvTtie9dCvHDXTGs50rJo3+AelGqWfqt5IzpOTaLtb6Sm9j8DiGbjtX4ZL5j2BERoicxHaM0iiJ
eFkxktoXCQ3CtIqszj5VieWkh9TyWe7uoIiFuFalF0GmI9fuNIR52DqUuGAECCsLSqdEUwxcSRPt
eGaE6pIkb6SdZQqvmnjWeyaVZNi9gcuTyIIWjE+nT8gAZQ875eqPvJ0Qg59fSSuSm8e6s+X4681Z
yXS2Vo+hEdxYtZQ/ynsB+f1k9ZZzoThyRAoRnrTL1AchAAAR0sIAVxa+IywLCleUJBdyR1DWuodF
J/1ypSunKi8x6tyemzeRKK8MeIga7cIyZvdwsbRAa0e9N38sjxpEEpSgqnwHAomDqOJap/pvqnJ/
D3vn/9LlFxJhlOV/hTEakKSx6Z9J6//qbtfeDp1viY7mqKjCYtN4vLArdkwKaNIOi70q0TphNNxT
6RMiRLifrMyZ2xaDpjpoRheG4IO+2JduLfRv0NSgpqvjzviOBBs8c67jKDfqDTz5NTzZdZuWh6Py
dWM7ViXLgjivvIPyRYS0L83Hmj4mmbE9RGsdsf5ACUxEaJCdAys2Pc1lv6+3l4DW6jrwJVBIESWY
pf0SY3mXCfbDpzwGMjeohiqiP6FyhXwlE1KdlzRLjQLaxGoQ7+nc77JuRUlykYR9Bsf5DqvamQS2
zzi45enmvFbMAYb7KEsLQB7qXIoh6gwyllKvgw6TwCBy93bzEhO2ioOUOBc4Az7xXx/IaXHIblHu
gpjh9ex8fB42RYnIayb/INmYTEBceAtWs9ctB6u0XhdX3wwJ/uAOI4K3hxXGb5z50vAzPm3559Po
lnCNapwu1lKPFp7enBtk/hY6s4cwUxi5FIVlkqvsAmY2UTKE1DagwqXb6e9NqvX/PprrQeH5j5e4
V8SpFOBAjFRRt5xc9pNTWlMKVVcDb0DzloyVLIgQGYTGNTD9Igv37WEUHtWk0QLMY8CTX79btHS5
MX9QlTnCUqHRj6Vzv/dzZ9EK/DCG/Enh1Or/DvO/g0MlqWY7c2gEv4Y+SSWFpMOn3RWYZLWAJ1ub
tvWavIs/xXu9EbE8p9yCdOoyVquPxKk/TLFxoFyeQnDaNL/ShC58Ldmmrc9og2b6RgIoCpPT46kw
egZQxagcmcM6rtsfhJEbODSKMKh1SrJ3pcPDEJZC5bLnFI4W5RWka5HRb83jSo/Fx05qPSj1p3b6
ywimMx1wFT05OLP02LjIUvaw08YOhodsdslUX03VvrFICAxNWDRSCjtkw24eNAkGzMF5ZDvv1qjM
SKi9akIGkyQsJpYEwguIGkuKWw/033mDbdljJziRSx5ao+0ifaBiQezZPAz+RFJwWyaTv6GO+IGd
I9BE94T0swtFyFHqMTTXvXfMridnBrF5p4rLdAuGE+i/E4WGdI/rMxPefOrpXGS3otdhFesaYUhR
EvBHM4QYiYqifaurKGpx4tLfAJdMr1BldPmcoZZhBfuHDDQ/zlNyDkNt0HH0J+MiOLvuC1R5JzKU
PMeANnb2GG+uiOlSmcD5TsI5de5fp0RmYvFQaaEkmM4Rw157lyBBqC3j0yH4ET52oFoBCAe5Q1Tj
Z0hkzLrE0xVUWoqaiTqRa+inrxJzlMSS1hZbIh9TXRjGfVgNNydRnK//6FIlQ1SdKsr5zt1P9ZJt
LSatCG8I0NR+7FmllbEb0FaWGqfo486WqGNzBm5ARZzp4F37FweCPg97UpSHEWI29WWv6EIrM54h
c6S5KvuPtxQDIlXoIYdJRo44LryiY3RmTipWE0JiTruCUrOdhakujGiFQmUzmyQiL9IJ1wT++Emg
GI0UFdBD8CQn494Fw5fUBaQnBR/xx+BKRZCeWHJYsey/6jwC0/8E9fqTYhop6GGbZPUkmWI0OKVJ
Tlbd7hoxkIOWKG/mdwQ7a+x27OlSamAkfvUa/ufrRvxc2+C0zYQatIdFKRaimwCvz0oG3HxsA2uD
C7zAX2f9MzA/WdDO1aR+3e8wFMiOAZDE62P8EyFW9wKFUIMqyV4SqssrIH5kewEfaB+3GK/WobOn
qnoFJVMKV4VyoRYJFtlBCTewkUDrOV9A9A1xrOyvDA7uNosNH2CZ5CXR1/AOKcSqZinoCMT0XfEX
CwVauFEtyM/ALj2zYe/+LpcWEO3J7ANWm6EUlUQwQHaRgxkX1FDq6XE0t5LcLgR7I9aYt4CtSDs9
v/bbCWowtF1QHp0NuyR0rWcRkeVk6iZdKTSvjKvwHmoFH+dNJQ5q+hf2mcWzfGvLB9qL/0Y6pj1z
5jdTuC5MP3QOrpB/oJ6TR7xulpUMKuO4oMNY5xxKiLFYA3pEyimnqRMHloK8H32lkGsaPkiBV8Yl
PTzsU2iHsJk3884Bf8Vcu3pZOllVkfZKqhBgCR+C+xQvImRr/VHR+DZNgiXXFQM9juG/+PqJN9+C
8BkX0ZKgz2dWLZGDrRJIOIg0QqlTmrKustZ54k4t0gifZmruG1xhfRvMsY3WNQIisqjgkvV63XzV
8lfhnPl/9TbFuDox21DJNUg/qKzjtQvkIJ2FjTkbkXcV9MZtzuTfMeO5fHZpYy5kAE5OjWOYWark
PpTDHAwJivLA/LUjsAj3RU0ul3rNzaDR+icyMsFj2SrTA8t/9fnRY7u317qz7d+k/118gRQEOIgL
U+j1G8PNqmMxwzjHYjhlznypBcsYP+QuvEqmP0b4lg3NoLNI9XiBSO+aD6rOUYsYPhRpgzEnVqiZ
8y/8Dk9drgl0E5u4VIAy+5NgGvbGFyxOUvYusimgPNHY2vwseAJumkoDv4Oop9ty6p7z7/M0oXAz
bA/d4zvrHgnu9chDgmoKqtjAej5kWGNMvfu4lfDvYx5vYLb8tDFyRQJ1d8mSNS7N4QIAc/QC1Iea
qPjNHwa1mucbkhCRx+PRvPfyh+GvUJcCR4dgb4f9B5Ag7/neNQPSbafDiSUZfPyNrS/lh98dw8Im
xFrT7rmSVwB8jpCjsnoRjeHj6EHQk0NE4fNzj58JiMtB4rIPLn+qHpvieZNlAe/4sqkhykMgq37k
opfbwYX9Z9Yy9bwHNTY5frNng1oW20tmmuI+kFrtQwnMivTuNQfsmHufjMeTxWjHnd4yoO/Tpcr1
kC5IqAZVJ8Z03wj/S11aiyqLA/Ddevgd28s0ObNK+LCGB9sFaM3mvB8/M6mQ+/oB9DolpIUdGozm
qnFm9wxyryu0AMjxuMVJvt2wl/uj1ITWBiTu7/QP4r28jTsPfIt2MrPhkM0Zng1RtQuB7iKbcURt
RGP82wUSimbp2EsYqFqnxo9JdJoYF8sfJaCEQlda5Jaa9BRPy25+pXdIvmBbbt1HrYcepoSVzI4P
pgnJDs/pKNi33aC9vee6+sAV1/InYjTZ26y51drpx7CB2S9eRXSO9DnLq/UCyTQPDxw/D1Ya4OXV
Mfi5qpL7jeI6xKpYX+mm3VAJoLTToZyf5TTlw7tr2a8sgv7uMfeRK4h6acR9djyQrGA+54F6FIUm
hNyW25Rlg+VUilOWloGWS563lxjtyJcCW3gAwhgd/W22FLX1RK/tcneRu9DgODLe49DeecYOxXjG
k8Sq9YK7alWF5i/pI9rA4G0KPOxCEEDRf/RcZlxChLZa+js4RfaxuAjZvOBJFiaXZnmZ3r+d9zcu
4LnOvj222CugiwWXKBW6O+e1V2t/5rCMQOzsuPR1JFf9ok5TuaTS0JNe8zSpj41fd2WN/ZNPrWN9
dpPxdQb6ROW6cDC8xMQZomOf4en25nY1ZUod2eZbAjj7HDjSdQD4ck5cS+xNCxxLBwIEnBSYd/8v
yzvsV3A4Kp8geCLLbOpf403yMCgvBolcKVzT6Fu20E71OQZw8H4/BhwecDxA4YPFYSwxyPi3Mu4l
lp8+62XTK572Y92aua6vAdL4Gd9jbftw6DYmKa+6MuOdB7yRINtN+GMAsFwGHLAR8S+fKOFnw/4t
BBzDWahwIRP+weXJj1WxMtRTSEDYMw+qZT7jMvpX+d+Fa43h+muZszhegYEauUe5OEly0K3n6v/R
EPzxxmEOYPqyZVc+huQ1zjj+Io50dkTijaW4y2mZS2eoPJ5GZ7AFN4YOcC2ggqAEyFlHp2M6o7tL
gFViF/na4XVLqEbBhnHtk/D34n2Lohgzy0ZF7iGGm8sAZMBW7QST5dKCk7J2eluUm9Jrgr92x+b1
kJhp5dlEPRxgmHP2YZYotVN3d51GEgTFpzOTg35at1++1O1VzoYxKfgnlso5HXkjh7DwAX79GqV8
YXl6tw4x0kxICLqLkB6Hs5Q7vNwF0bIMnFqE9kQfo/+WOTrd8l+UuXgE8U571F3mN6sLIVZHSniO
NokYa67FDYx7c4fZarpb1v4qsBhLQdDYk2bRdRwnTa004SoE1Po7rbn6YxvBYp4Beeaa4N1m2ffU
QDVfSCZ4WFHL2RgB9TcxILnEKknufNI8jrdcBGG8hj9Ty+zWf8Hvmz8rMYhHyCQI8vzGZYiJlq2m
qMWsYOoCkyDj39kDlHMaCRPAL21sCFCs288N2aycBWt8Y2ZGaJeclPaVCC4ZzGkUbNOMHwq91zsm
mcw/zCs2YR7L04cukMHtCh+qvrzLlQyFQsBNr0DfAKcvB09B/7CuoRsTUo1F0tza110/TZRuiHFv
0WBDY0aZvb4B1VBZvq0hkzEHupYgveV5KlYglWXP6CSwzxjmbwFfJgntcxdmNr3o4kNsM64bqJjt
FN8MxVxdFBigOi5dMEIck0v/dA0gSwLBlR/IEizcgOzF5BhOMK0W7sWZHoPHc0ltHOMmNhbHGLXl
pkrGPXTsk8NVRvC9ZfKDVtwmHpemPBc4URmG9m/ML3EYnQl63w/gSKAJ51wl8Mke/sQ5aBzLrMDp
9KQacCKaOWQuw3/XDSQncNREuxofgXKg4FCEFvxX0NJ+zu3UXq95d31hfGGX2ybfvVHrHA/TFQdx
ejtRBppm4lDHjaMi0PEGXh9E4xemEvustE7lzyjjUvCQFeQYHvUfitDfaFmd8mDYiAvmEXEO/LMs
LR2tjJPyyeIwamxTGKtUBOEQO3CbU2Re/Gq44Z1bpGQBrfYAoHPNZ0Qs0nDJoXgP8peCIWSX8KsK
XPriJFiURT1wah9xdff765V8OQ8av3zwzltGB6TowO+hHOgg40s2ERrI9PYwx3gTJqqNVXR1AFhk
fiMY6vkLZePd2RliVTI0kKAaDWYuEvdDHmAbDVXEIlGGWA9R2sCccZvzqbW+l4Y3RFWMjWZgS5Kl
WUJ323eIk6Gyv7YXTDpdYzk9PRHgeS1y1Z5+hjRgIgeTozmw2ubnA8h2CCzmanlyGsQGdsN7yIa+
S2IUmS+okrjnlshlU5XiEhQ4+fwWEKLGxo/EVxuZrLC4NYfCwHjcKbGbgEbHDoxUmUzrzaxEPeES
Fk8fz6Nc/RGdSYaBuYeadAwYG8Q9ZY6iIWVDGPHmfGdEAaLkGs1whEqKpeS6VgoiXeElEbBvPPfr
rJMMHAvYPefSr8ZOTb2H2lqBvBUUX3QlYvibrZ37HS0N2bE8vlkqbWKZbG42/2CzD/mVNtn26bgS
QVUJ/+42BPq6vpDhcYYrpX0InQxKUD1Qhhx2iQEJxCOxIQms1/02GXV0n3VYT5Ir1VTir38hnef8
RSi/L+v2OOg3te6izUTRfYf3OVP4xDSw11YjXbFXCOXsx13Kc/rZBpl5sFIgqGZFkV3P0ApO/rz2
hgAx+kpTel34nqZAYyTL+gYniQbT7nilgaxQCPw/mG5PeGByK6qVpVy8pprLMfHn9qhjdsmNqayu
zKZK6Ubs9fJoolK0ypANOB8mGQRVMLexgsjFhE5jSmbj5iYAR/f/9uFJbcmqPSRMiB5hgKH4yHiu
4duM2goWKZ/kJoqaFH0qj1+DJU2ngO1uUxUgrPE8pu5BnGuCjz8m1Fzdnwsb0JyrFEmkg9B2gunh
jwPUn+AJsEFbW1ui68KJE1ppCIoBImMzvk5HKZ0H9kLIY2HwvyMSON8JlPDrLxkJ01FENkfALO7c
ZCvrtSzUJeO46/1ytlfs9H/ivdz9oEEvnLjnhxBrqJ8igAOSyp1n99yBIBl4HjnQe6aKm3tGgBbd
GLxdtHK2EQahdkgjAXJYciyOWe7HILO4S11uaP36Gib9F1gfCwuSfImCV+gF3LKsJlUVdBoq+unu
5Ptv23rgLxtv14guswfbAL1QKINfCtNRYiXTauISMkJVpCR458yZnf03xJvCibVzDz6kgyCFYDqN
p9ST/h6iaXwEGxeJVaBH+tIuuIj8Not3ElhSMwWlN+IcPh6DLfwbosaQvetimBVkvLGd0uup1Ris
Ua89RKadRJn5mYacMuyRI8JhgnN5Gn0ia6oUZaddx4Cu8u+2id3LMrFlDaLnJZV321mh34z4wvYL
PcpiLVmePgTQMStpxmBM0PnmjkHiJDanXtVLT27pMDY8uwAu3LoHz3xKtfbUhWQIRfTgf1ADe56O
Uf47EJaM52MHWh5AnEZCDhYE1FR0uq4Z7H+nUVn3aJI6bS4Ew8SWD8Wh5vXCtvGvsPC4XDAwQ0j+
AZoUzSLy1toamHXtuewGMKsK+aBh8MOe6JOffbYql79QHVFqjak85rlqdlv6s1v3aoS/N2QNf/oU
U2khTrhkZOLb1QvOuWCLUb4eCU2sStGv3j6xs2OGmSLRc+tamfWd8kcWfOZnYiJRqNBHgbTvMVsf
OfB25Q9K7nVUK3bjgxaT1lDTl5PuRFxFP6wKlMEheeTohexXPOpGG0Gerug+eDj3v+NNUBgXcv9Z
kjwsi/2BuByVW6IVKJGgpmpWVYBlq3LPzJFLekOzlNcf6AqrnsvKSdQXCBpsagZ/hXj/+nm8dQV3
l/KRQLqZORRkieLKMwjN9dmiMa7LFrr1wQTuGq3/UHhBjlOLgx7Q7NJz0pFIsJyNi0ii329mptCw
sSC5Zs/eHXyVOPZyQH1ry5EBG8GaLbv+/dzIAANgzs/hzvtejXL2s1qz8/aV+kOuzhlkispWc/T3
wUFFx7wpVTVJuSFRJ6kL37biw5L/hHM71+xohGaO5ooZ9EzJq0aGkI3s37J9Kgq2BYaWYpel/jVn
NqPlRs+a9JmcabDVslf/5GpaA7Vw/4e3iYKlocgEPpVVHOuivl7YXrPF9hgJJnoSW8cAUQzQJHsb
ZhzhvPAOu8pZ1uaRv8GI8NvNh1mmHgyx1weDyP/YxDmPTYMrZm84oC4HlgHdWfdaiG7ocBCy6IwI
OCfWJrrI5JrpUH5qwFkl+Utr4HVlgf/+yRwHWOXvN77aNMYOo+BxAt7/Pl1asaLiU6yBdHKeGzGT
3LVcZBC6wWYkkCbXC+bXtfXQL2rRK+uNu9mH8QQkZlK0FD5VJmotlOaw4FWnTdkq4jPKZilMb87n
Uib/r/0cd5ydm8Wx3n+5krCB13YNgyu7RueUgXapLT1Xv1ixOG8i8sSpPSnVLOzGsgbfIgNMZGBS
jKKBC8gYy6F11wLdOij7hvN8xgcaWeh4mJVk42AF+B5TVfp/ipGf54ZFPEvynayjQSLesVY78wim
m50SqQf7TUWIZj4Qrdi8jSqEiZTQAtCl72+x7TrE9ppk8jziDtMX5M68fEI9BKOgWZ+PzDnRLNLW
V1Q4oxryDLsNmGepdDHOzod0Jnf457gyfJM2sfY+TUHe8eZ4/GjPtMW4VwOMvsXNUYhlqNz2m0A/
ZTxhP+V+4yQiDpdXs0xGXhEZ56WCWjx0+BxUc37XmZiU73G4oAlmhF5WSo/ObQw73PWz/5kh74re
03tFBTC6e5COrcNilRbmPNMKS5+ctVahDGNTzuedWCVqppQDpbNnbWcf4n+vtkxD96qaOYoSc913
uxbA6nlwDanOzuYf2B5VNCgVvoxUZzM5RLyjMNuQ2UgtHT6DLWk5EuVGgRp6NGsE0Gz34DACd1q5
kbhM/oh4cujVD4v8sIhV7cvn5m2JpQV1xG9MAZNfO4jerRcI1Zvrv8t/lh5oUqqKFA2QautB1XJO
JCkgofdx307gDAr9ujunE+hh0MbLsw4cfpfBGFJVUFRGSJZq6KRNczoDLVJc+bnwFmiBBTRygYVg
pQaJCxWTszNXM7aeJFw/cChFlwOHshXZn0sA6tYkFFiJ9RJ3wJvtXX0lYhcEvVgSovwmjiwVoB4t
K6XKkQaLPpp8XI3uksXeP7htj4Kg69SN3W+j2nhU9rBg68dWjR0LfEr1Y9yilt6SVq7EYGWweA3l
99l7OaEgr8tT1h3S47lIqG38thk0bLdFiJiyj1Z+C8b8zTT7i6wvLHtNDk8WBuxNpRy/OQk7ba5j
7YJ5R7aZm2ZOEhbRAVRBV55nFbSWVzz2gyDlgcZzWoeHMaEHPufGcoQgjM4cLSpbMk3WEXU0N1jn
R2EXTJfhHTlrjvZE2GU2J0dtw61N+tg7gCGiZsl3SYSwU5Cxj+5w2tVht9eyDNNbxMkP32nGu/97
6fQyj4+/TwYTk0H67V9urRMEyICetxdpShOB18Xz27iEHIxQUCgYwlr+jzYGe6t6PGOiSYCqV7sH
NoGL11tC4xPeMUigiH2YB22Wq116ghgaXGTq0Sz+yFaft9YhNtKjS4ZISsmD/V/WulrL3UT8zNQ6
DXk1AXNAkxIE/Mh/dtBpeujOoI2Bnf0W3MmI7QJI0awB4wuEYBCjWrdhx1jpnPfYjF8f90mBGFwO
Pug3MNhy2N0dcS6z0kQqZv5Dbb3twr3f838A4c+Nb6oRdHkUF+TQ3nG1xbj+/RKZctnOwL3nX9yl
zZIIWwsm3E9okb5xkGtNn41v+5dy7OED2dsqu/uMKaIhhtfbwP0jrZsop3Q5ObH3mKE5O4vgLYkM
x3ZoH+ddrLAQKkcHFZDqUzuknTmqn0CpbjZqq2Q8M+kl96n+MB3s1DvUH14f3Ryiyam8iBU1xlqh
7JphcakSqeNhxtY3Pe57dN8eRWe09PO8IebMfrBHGu4kupXqXJz1GoQMBHmlve9Pija7gs9H85r9
Xxww4TVZIfGK0nMSadrQ7Zt2rSvNdpUV0RCA1B/Zb1AUfLW/HPuJYFdH2iy14hX8izbRVNxwIw1P
eNripL+AKaR3nkdvH5CRFCDdSwz2+hm0l4RT9RFOOF6jorT+3tjrLog/937ACcoSzeOtJaKg9oEm
76Pn01NXBvt4YYoJLjoBH9tdf4blX1OSeTJxzzWoXlp3331TFMVsW+VbjhH4q3LjwprE/Q69zooB
FW96s/qmd3adzh5XO2UnkfKsl47R0gUZPn8AzOxTt73NGNkf2kiShjANmPMMD/zIqcqDAtVm6MP2
7DirYknEwDscyzUb0Ups7lpV9gfoDHuN+eOgGZIzMUE82P614UoIrimlP/9J9MuA5wUzhXoTAPa3
MedsXfbN6Sm6rNoPpFW0NeIFFfmjDm8tNDdvV9awLbev8ySLhieGKI0eJuEqaxXcX8fLbwUXvfTN
rCbdvPl9M7BxoHui/7bOd2JRLNoX/3wrEY0NKdKjjo9wPNtLK0H4nIA2hyOcLWAUzRm7Ji6VTV23
bn/wmetvP/0zn+7AHuLQxikAKtYwGvDVbLQ3EBmpOiMfbRUleZ4I0M7KheF0FYDsuAgjxRxnFrj8
wYcy0U7HI3awHu9xueGybMQLM3AHHF7hky3DtoEDwXxWbBjwwPjiv5PYwGmK7o3PLYkjw2JQPYrm
9C6mg+clOnTC3c1iGO0qx7Ql7qtaxUk5DNET6igrB0v2ru66wiYMlPo4DZDzVB1D6EUyvwEQ/u6o
GepkgmvKcGydQcGM2NiEwzUslXbdTp8p48b4poCY12rtueokfx45izjq+2Bsh+YbmH21QrRaMmip
5lFDjxk7ooJS28R2plopTH46KCBbFLY+c1lS9anK9tPoqf/+NX1zC4dNAsFDfljkSb8LfMtUbK9r
quEHzgQcQF4lLQnJ0ZxVCFvaQpnaqi/TEXoFEOCCUCNeu0XLRbIJ7X6VlvssdawixFOOZRULVSFM
wIsvyM9lt7wlHnS4UOynA0yJ1NHsNqzrF7AJMYVbJshkf0sKyNxFxPjVDaP7O23123i23+BiDSNV
UuUGUPPmKGK20FGtjaD0pkEeTKTbSSx5FT2hwiKz7I1H7xzP9Ps7Jrlwv9x49SWmG8fEZkvkNz34
BeKhTG0jlir8qYhCb2iwW9ZV7Q1ITmulb7gPxve0PoB56PylVRwGOrEXLHFE4QFdNs0KfNKAYWHE
U379fSLbeKn7bWC/6QaoxA3R1aReE0ZnFrR64WDy+Et6ErIR3L1Fl1Mt1rVR7VyuhnAsWxLCwObt
wDzUaQkKWkNh0w46sst3LJ8sAura+i70CEbllP7eYBIcS3hx5bpC2+ADCWLKSOe4Z00X3gfp2CB7
tOUySSkMJ+RGiT2ek/z6SzgBGSyNIs9LiGKJtUi8PWqSLvOVnLAmI2paXbvlhY1IAwfjbwKVx8op
U4jBta8NWdj+rW3MecdMwR3HJ8HvvbBPR7LrbhEF1vlODYcZjdkHhky8+73D6kJDKFA35ZIlyXE0
30083441nRmwfVKnzFUsyCqN/UCQxSBnXZNRR8agU5JlxDcT6JEBkyj563DPPcqfENeO1ns67SLm
iWIDCahq2DfJZ5qXoeHjyse1eJSUzryKfX7R1aksgDTxVqkeb1x8q0QJD5vDShLR6vhmsvdA6pVC
q4A5O0WufhpCv340/QSNd9OFuiT5o3OSWDZbvBurFTTyNGzKQTYFxHcN5oAdj7ydQricxc+PEWA5
+ANxelspI5xnTJU4GdnshCJIvf0Ifz0Cya4BoII6+HGaprvywS2uzgdA9HbEvpyk4unep9n2aGqM
bSGpm/45ynvGGW34AK4VGYHSC/dmJuJ2WCrFwBOAi/ApCzmz5s1BZN6PiaMWZFzCYTeYNZwuqHx8
DyW56T+tFu0suMXeixXjlEkRQhd2HRl1fTkUmdDx7aefnH0D55Lmq44u5GlEidMg6ajXwCzecmmn
my4Ne4yRk5Om704vS/cbLsuVw9b5Rhdvhb1ozZXZz7jqivXwkXZwEhF3K28KJeBM6F61dL9Vj9EB
7ubRGOqMkj9qfaVQjQzPpy6SdJDu0fqYIvQf0ZFNLuRtH8+T7dpJD5XVNVaeTTyEBC6cHM79RhgC
ZJaP5Xeu8UuBjRJAphx5AZ5R8nCyJf3ewljz1okTwwX/n6FT2iVyWqn1JJ5XlkvvAA9uPjiU7feG
quT83GsMucXeE5z87xH+mPpLdNaQ681KJSKcAWODl5J8AnoHrt9vz6Y4FuKk/CbxHyh6f9a03WAy
ylWCHSEH55AWz440tj8+Iv0puOuKGmydg1d999nDlGi2+NZKzZ8lnG1sF043rifKrnSMeChke552
RUgHwebbdzcxkPtDqvPCol/OgZ9ZrA+vzl2DBTvmXO/l+fwx/XcZVv9eSLDrkMbY2ox3Z35kydNW
jYdihsH8bQ5J8yQMYky/zirh+MZP8JK4dxD30aS5UYRViR7aDVdnAB7gMQ7fe0OsR6zCclh4KASy
4+tQmOjJ/ckQ9gbeOJ/5refRE7fqTnVdUTgvgMOZniu6gdHs8OrnX3nxw2If+7vt2klr7ov7adQD
ru3l+kaEF5rwVRp69DJo4AlU0oul/wUQnDUwp7dbppPCgHZgoY13pFN3YdhjP+PS2TIYUwZQm2y7
ZiGk7+4qF1p7MqjPU1JDIHuRZqRUQsN6g0ZjPs1/JPNxsaT+9lNRrLch73AOOiX/zVqbcH9NNafw
NkkaF5Bn4ROx/f1bQBwaTLr20ZOKHOgHvwCiKti8CsstwsDmbxpJQcJ0rAPWbLlq/azfJ//+A/LZ
INeAQ3IgWjMQ13SMOtyjwvKC9df8No499qQPOcjtevNew0knooGrTdpVl4HBtPrq6ApbC4M7LuEM
k1X7FH+ITLMCWyz/mgwEWLRLxLu3FNJPNDojqLrGWj5e6OTGC/FqQn/B+fXrt24RZs5EDJDrV46b
v/3pg2ZRdPWr/4eRsVJC6j6cZLxZW/zsD0C6wwzK3BsYW3ShI7w1SKReYJ6ey+df1sFF+1W6DSMa
t2Uz/2ysov7MP5JaHyHgkv2o0FDAVNpOpuT7t8jmCGv057K1caCtlO5ZzztC3EN0NBrDFy03Oae1
3XC+HIV23BC2m60h2RxGBVCKtU2QPAW3zwFn+6cSuFNB0Sra9x4yGWwHsq3DDYz+jOMISgRBMMPS
9OdyoqZtOaY/tEStnt+MQ+zxRS6YC2uFWm9pva6K8hxcBa2KPlk2wI0f3FdgklGMD6hXmpy42KzG
lCQ3lK0AcFxo1UMvZSWKb6UfK41LMrOysUlFSRrfZXPiDjcHpq+r2hPAANIM5wiUOhqpirTT70/u
gWDU87lMpIGApoSrm44T07vqzQqzOEBsHPOzNdvtXwNBY/fPHuD/QvT3EIKwbtuEZxhcLDoIhEIg
dtL4r6BD5gCc/dUi1ZqNGvOioIkvgYj0yXIqSbP7ZaN9lB0mePlym9WMcxfxLoTkFQzYv814cBoW
Q+lVR2SUjk517PRLyuMQp9ujXPqwYkQu7NafY8p00upDqYC9WtITUwG14Z2TDN91BTBvo7jIbWAH
vQdANj3Qymh+/astli6b0ZLyvmlJAYyfHNX/V99wevxEqHvzcNHl/m2w+5w4aKGy9C47cM6BoVaY
lFhtjbgxJ/g1ipUg4snpjT1LdJJ+2sd9y/4af21FRU4uZL3XZQXb9ZowgMMOv9rO9Hoa1USe7WTV
chx5qpNesoOht7O9Ia9AakasUiWrtzA9BryWAv0arVKKWZvGkZwlVoWKscWtWQT5JMSpH+oeS2wC
zdhwtTAnkL3nMHZt/C03JIHIcoof3m2JcwlIGyf7M1AZiE+jXnBw8vCvnsXkMvTC4TzqUfwJOuRC
qFYEW6icd0+YVmnrLo7nZGLx5hoMRFkOW44dWFr0Vb8iRlwTt+mywajZ2I9PVhSMp16O/7GX2wIG
IH511hIixoBhW+UJbZM46I4CZ6aryJ7XXSYIeEQFknG/719l3ac4FlxM0AYVn+0MmiYpQUVC6Eyw
PPR5kVBNKNX2dmCkqS9bovz2FzOPVNMOxi8nS1x8RPpJb4+WGQMtAShdSgNhOG8gGMORFvBGAFZP
3sc0LJeyCZpKrcLqQQkX3egu6Y4wLeHMsp+SyGHK7jyrBss1+31gM8BmZfRjJt/n8NodBpsZQI+v
6JOlWabA8RvQnSSjsjO+Yb7DyaXsemDEDZx68TUER5wG0DYLc2FpSPcM1QW+S9G79gNKh0LTl60C
GbZu9u3YBGEilb+M8P8x+YMsS/trNxCCyTW7AD3fRkKHHoYGkS6goZQSXYWUMAmZH9nONCv62yOW
eDVGgQgB/PrDOcIpKwkAQjAz9oR+KeSaD2Cljkv5wRa2EDwLBCxCgbOY2lG/LJ+RbqFAXmwFFw2r
5qz28WAGJa0l6w6S9tqCs/aqYCtjWW7mdZz+LmJSvhiOqx2tOqa2ZsasoWCBZChbIgC5F8X8137/
4SVnuKHk+Zz65gbBlQyCb84gLzTMf2/KcXFUPm7Zvaq4+EdZkSw7+poq2UCnaURRzyNML8KsJOpk
AG3RLoL/We8RfYdj8Fd5gycepPpC2Hi4ZzZgHN+Tn5IDujRkn06PkeQVCGWmWLabCZsxWdGJqGf2
4wTe3HyljGzwA0/OBAMoFQp9R0Ni24ygbD0Mp7vAzJ66El1QWsaO9WCTRqMdjxCIQtOGQsRj+w39
kZr3bkRlaxlihnQ/GBmmVN84CdCpAX41Ka/978qDgURPlxY6SZE0pIb9mO/BOIiZvkh6DDiXtwVI
BUZO5ojQ158QOd33fzL3MuhM0QlqfALcRjpWjaDJFYMxkt33NZrhEazZp8WfBW6LSu/ZdXS7sYLk
H47paFJ1doSoG0zO/u67lboWCJyQyOatzBBGjbNZ1JwDZTceZP3VCCWGihrzhTxwrALyb8UZ93hZ
BedZ5J/45exyXeXWxM8bS263lbbTrAYc3lA37tCq1K36DaleJAaN4S7X4BaYFuo0j8XQrlBaIzjY
fcz1l40NffFJzM50uWg+BA095Kiy2d0C6xKxAc7sGEIVW010AV7PGFJ8ugoes3Xvk+ZhO/pl5L2x
ACjYw08ZXNF3JhRor/sGOFOSiq0EcMAQ3vMoGeO79Tfow4j6kPvbFVtdmFgiOQXd+wNjIRbd8U6d
Hfd1qvBp8fUHgNaxE9OxWExXUrkoYyvjJlUGgSjmAFsu+/rj+Ql/CJjnS6CJbbAvDRYrdaNBu4Cz
1wgMf+JDQuVMomu1qNjDwGZkSRkP6Riom90hB6uI4B8U1iW9/XGnWi3a7eejnjE2kWCSh+fyzTK+
teUnHzl41AYyhqmQgC/wVuIdLkm/7J7guzY9uwx1ljtuOdepk/BY9/RmM/X5HsFP+kGzsABMc3+p
dd40lx7KZw8uH2/WWH27QIab0IEhdZ9iQq0GP2ARQk694ry+E1ugga7EoV6RRWVH5usqIqfdzML+
qf0as3X/ffHZknhx1tAqSKJON1xjmnDmASu9xI296U2qVFHHmt+JpzDi8YA32kFXk3181avxZs8b
NwLMWSHeyw0nNwgj0D5efwDBZw9QxOKOCUGO7+IeXhI3uDPU9BGwfWLqQ8x1akRVjTuligSDvrcv
wvUcZJtPD+xv0wrbyLyEjx6qcAxlTXymvZ43s2fI7YiYfXqi4NMFo/4Kv+NydQVNi4bLECNNW2wV
ybeRnWmTp/z2k+WCiyhvY5wS7rXVARarPqJ21zNRT9CMMYxqokDRxuoZEeYB3rtnbi38GPNiKxQc
IRNIcJlzpXXfpfCo87ziGPMWHI1cuKE++iE7BdSZFKJY2agIWBaIf45vbYoLmAPGqvXUw3DTL3Fk
eriw9ReF42pnBMC39dVh8EYOlb6nNXpc6sZnZcdomVozH3UxEsI3m2R/qyLDQhZnjNuWSIUVGoBf
UGI0qN0bnOIwOrrPDN4rk6oyuNGfSJFgHuTRUi1nR0ofrC+b3TD57vSDOjY5oXi2mGMZfQaaAPK3
0MAbc0qMAmNqkXzXwTf10JZxTg53AjGYweKxHxsqWXLyuRUJCoJJ4j9agWVPBL/byZLarHm3VUAI
Pt2s2aGDFH2C7HGoONSSp5tDYjRwaNwXoNsVYmahdC1gUpOoNUL6W5crefDRYGn1qjRTbDMrRVph
hiur9RVixcNL63Lu2hrcSxHW9AMRMIIVw4JY1RvPWVA9u9e7EKSsT37WuZRQEcq+DdC0xCqz6jUO
yW94e2gB8KVKSX0WgPLLpzl2U271k0xP/KbtyxSUx/oW3TNbmxXOV5o17YCEO5chs210MZUuGJXU
1LfFOiZOPmgEsnYGq/N79wQmA3BpkGokp1sS2T4LMpRKust7tIuZRtnpDNIhR+DVcV8o3WsKa2FO
UNGQQDVLKNvINff3iN7TmAYBBD1gNuQm1mS95/2U9Lqvm2GZl36n3E0FJfdopuwRUyKqbt68Udk6
8+elQB8HW38ejwK2O8Y4vr4HntHbV6Qy3vl0bv30fRPbTntdgcjdBU1DqTt6OKs+oZlihBSbEdqw
M6yhjJTjj7G0ZkUDNsZUekdHLyf9kP6Tsx51ruFpg/sNvXF7oPBZ+p+XasHY5k60mUOgUsB9XiqU
2S8TK4QFqWANR9lAkLSDYRopEkSNiUQRtBTJhQGaoTkedXxxlMwbfMH6hl6ztfqIXSWK7X1YJlYg
qT0S6zXRqSqjuflAF/eJxhX89j6/ZYCLJ287WbRPc4IEMCQKBqtfllwGG7GSQguWOQZNcrF1VfJD
G8W2/dtGp2gz3Au3OFfFPodMQKn+48ytRFfeBUm5uKqEI8sqE0+XqPytHHxYoTHHQhrMJAnDqFsS
0CdTCxsy9zfF/8UXhJ+tnnTTLGOA7vIS2c7rWF93Dx6dgMUpPlWXgbI5A7afrWCABf5GqzEDRcgL
pAMJ0RL3pR1nUStE2gGEJ1sL+k9B5FKklAGYPYyMmy5qT6z4fqybAOoRU2sYBioAsy+PYNG1EYyU
UW9vzFSjjhF0sUHiXIgngK97q1qMQxCGiQfZxVhBSIthJqrqNjFcqyOZ4Jmatn/IgXkL+lQPe0Qu
PYhiJwZBhHp1N1jV6qNQSTa6ZWuWqDCfWTP/dA4N/Pzrjj2i6ljcIr7bif9OpVBq4398WQ9+F0/8
lh8GQdE6jxkt+NAUOfKI3nKn79BHWnyrzcjq+yXGTtThTwgtMk7171xxuwtw9vd6abUjPQIx0Pos
AoLQzlDBkpmlxUiwMwzGtkd24uaWjDvcmbaEds/s6O/7gwONZAQfmHslcGHRFz38v+AHpcyyv9Zs
qT+YvWvdXrARkoBCpLMoOSjp6B0VarD2Zw4Q+HpEuNOJiRsIVomw9qbVQPzbAGDLDULzkyabffp0
74zICQpC2KIjFArelJ4MK2P85Bj1mV1ikpmW7P2WBxmvtg/vNOdG8kJF+4N32gubITBxD+YwpzQr
bKDx1/yJhp135dgEJAEu/+tg4HLG4ydteFcwhetU0CA2JVfHdnyOaPvUr9gvhEw8/fiUSc2BppQ2
9gBmag2O6fyjNcBjq1e0N+TXi7uNaTMzDm1lxJpqiOKHFpsvPbhUSKVOmn08rJUcqQ8E0buCz0tY
QVB/EZUGtgWj9YteYDrv3/lxNkcIzANE/k6wO9gTbr4ODiJtOMwQow1ZfrxWG/bEfqIXa7qSdinz
FbpbQAiAJjYVHznE0XsJLWvK6UrEsQPOCWu2rUsjzd1zhlA9gUlzp5QvbXgqkbc3EKemQXixjpoR
2k4jMXsEQHq6plClxWbO9UoKDeha1mGqnye7wAOL25vvpS3uUw1Z/DrbbjbjuWtp8eNy9S7tI5/M
H/uCksCSkfUTFSk41r6Z6BP4zdYIb3Q+koFI6KQMHFgnWlh8C9NETLeWkESU3Uc1zHdN9zutd7fE
zauVizWO+oz+yCuGOPnaP3eVzctJ4F/TCwp0HE68wIhOuS98SRA6ImO1ECjwgeU+Qc9b3DypX0C/
mB5Uk1SbUa8ZLtFAImJ8vEyfwIxRV9oP0TrKoNYGgsCIN07zeZtGqoez8MXjYJDaRjafw987v0le
RbozJ4/FeFz4HriOeqb6E1E3ZXw18mT0Hrwc1lOCvwkEo7yXLmNnmlYaCuhNqNm93w9zCKPV66to
BoUX2gg5hlS28M53PX8YapBecYDPzcyOpPrO5hIRE/cLq4Eh4UjzV9DrOl3GZoDf/KnOOYFRAshv
bQRIF/HDRzvNfuFkm+HkriAwSXHN+3EnKYcmfud4o7JL3pIWzY2nOlzYjXgQJy5i3y83o7e8VEVg
sD/588MZ14J2ov2G0Oa3QnX11BYFaWb4r+ritAdzOjgNFwskXkEWewWceU5eJTlhauazMe/EF+XS
mL5Y01kqTMZJ7tNEgu6mqDJzTxSim2gga8SV+R3gbGSuGodWnmAgurN+BNK2mUI5LpRMVorMOgDM
SfNDMldZHxwlJ1B6c0bLmxldLGSwbr1VYo1RBn3furxEW8AYq0OIMGtsIF63uUPuYBJw4/5wuuba
E7Q+XrCOtWkbnGa8ow6XSgXaTutRXfaWMzZtq3SOOhc0US05gg7B1oUQdM7s5/QUsRKow1THIEJA
OcpgDODp1f9OHXFM3dAoHrWQzyBVfsJKPTJj7D/Zcgm5asn9zmm2KF9zzti1271W2lmBfVEux6iq
tLEnniscuQFrIqn8jttKNRoUHdkLnsp1FMI/rLcES9fFuZlevxsjehKUR3nOElqAXJcNaGfTtY8X
9h2yFYKFsKGt7eTs+FHA9ZEmJQtZ+rSjiDrYr6W+QhLkUeXUiFGCP4E5y+PDHfE5J1KPsD6tPpj4
Bj0wCH6apb0w6iYMQwTFLqv/jeYCdZk1D6OuPrn11QulRYp1GgRN/kyKxvoei4dG72twsfNGZYKY
+01ypPIat10EwcPVo6GpWUo/l1ScXHEJS/7CUauOxC3PZknNXJWKqTSedeAS6wfEIWoyZpP+DBx3
Eg6KwVTqns1Ctg4HfQ1Q55HX48aLDcX99+kXuEgWRwyKJ53y69q/xnfhNjgMJbIcRQxI2ZrGVPgs
dpRijZETO/HABlqoIWusm7BS93CI9k3K7sfUgTZf49Ng54fxkj+pp11bzADWHvqfbzKip/1LmLKu
vChFwg57n33L4IxBzt4CvqIRP24L5Ba6szp8SktCWANiDlKfCWkWLgRorAnR5MaF97Yk8+J7VWHL
fEhu+r3q8gkhJVLLCrNcn8+ZyvwKJUKo5CxYMHfZYRzsNMZxFx4kugVEJr35ELRqZ+hkrJQrtULX
XlkZkIV55lZMmgMdkRxj1k5PiUm0Cdcnx4+kFJUK/iXD3mQNkG5URZTllHc4hsjorGMwEpxW7dIB
yu6hm5plzoIOnZ3ixjEFsSc5ArO+GaSVe2fXb8ziKJysukUkJ5OuIWrIHAh0yfneK3sEd1fGxg+o
67BYtbb1mxFziOEov1uak7frhDCoQYc71WcFf0cguxYzu1ne7Zz1Tfh+eJ4YcFj65+BROgIfHiuX
XmvZ1KAVsxoRFsz10BR17rcn8mA0vZWetelUf1qINl0rjMOY0VEIwOCbtSuOWmMcXeY3FiT8aUCI
ACwKSsQfZ/5mfJeF5LGE9iTfNYKrcbaTYPAKS40pbSJINCpjXd5xbUHu7uln4zaYhaTxqbyElCkk
uDzArwEatXF8gn1PCEwlpT+9myhlTP166fAOPxWeNzP/+XP9YpTGH8OfgGMi71zd1wJmmZV6jFYr
syUc7/ZLd3azXmhwn0RUMxEr6jeOQMn7b2fJuyhLJ7lbMnZyij/2GPO2K6CPb9NtM0CFn42qSdmx
gwNrum72gPvswjLw2o9yh7kjHQaaJ2xhNSRwIZQ4jcLKbTC9WtCe2m+xAV4NLThUQDZPSVAPICQC
v0kJDobidqUAaHtPbQ6gRB0nVBlG9jvCcDTPTJnUfglrFTjhcTG5dgHZudOW6p1L42URqMNdy/1k
cD9SUJX0USGD8z4NIqdyWqOt74TV0gbnbj/QXzfgkCbd5a+Xx1gt0Fd/kCE3oNzERw1sMIOpGiih
xVs2mQXh5q0FrP8u5EFjmfBCCp12bpx8nF8YaiFH7NMGtZmd0fkJCsHtNSfX8oEqfTMlLLt0X2Mb
bMKdfba8AnZQxsZpWNud6f4aDrPciA/ITOHBj7TAB0fw82A/BEKDjDm0sk7RZU3oXtepRfjIZM7r
CCm2M2CA0deinCT2G7tBU8rLI6CULihZX7brXHj2hH/1OHQBNuE9TWsYHn6mgrnYNocz0XDisoGB
cznGgnhbS1/IbYBRf7OVrsOSgji6dNCAG/ywvESW8Jm/aghb9L0YTVryuO01egzljZyzaEJaCXfT
Nvki4hZmnvNiAz8kxNXziCNbde5LqzAJQMP4rtX75rUeCiGbONqnvzMNX3UzCPppGqUAwb5qOR5n
uWOjqy8lbjq/IrOI9pwJvQWZIe2YRsVkTgQO1yPcPOt2ivoqdUNoaV9HAxXyOrMDxp4qvwzL5TUl
nH9Gf1qijiOybE54pwSNvtg8o9n9p7Atp/eqOUCUPFWQJxLRG6r2AMVFDaPCUuynvLsvr27nWS75
mFWh8PYfBSjSzDe07IXL0ql3GUGGwCBDfqQNs+EucWKuvAa9Pz8JYax/avFhykKVIQvTpMy+Z31G
/puwzpG3c40hOPpRh2OyKPbCLUUfPm40d/MBQW8/THxl2FgFdYOQWQTcz/c/0Nyy+C5TAS+Vyml3
avEyCf76JT3eKKywq6SaE5be1lOj5ft544hDfxuEFRNfPtc0ZougMR9t06/LbHVhtNAdYv5ICLhv
M9pKx8o2I5HuMSd1IordbVq5hMQ5IKXForb0llCZIsIA93EPKgbTBdewGeJR59jnHcUNUfr71S2d
bEBItdNS7gpGzWIrJcAZAiD3bEub6iuRUPui3m+/Y1W1PmGmJZz5pFSy88nSJklzyY6ZtMoFdX5T
caNPL/AdoPOqGwys4Hbs0TqtxXZEajruLu9HEaVcLqjGdCooRUGqp66U09RyJCgKk7vwLSpbt2ci
7DuKX5LBNlyssVtCWHPbS+HR7UUkxim/7aVCp2f5+L4YhFscTirMPHuTsk751xwcZVG+tQ0t4SD1
XBqHmAzZRcn1BeP2BmC752PCG0mtzEFELo0vswkivBOHzjUKERLF3S9ZALdaHfYXAmlYWHAoTvdY
RtAMS9U0QxmU6lvp4/icNsQ4QazEiVbP0DGsBs82X78SWA5pQ50CvYffIOdVE8Ga48ozS1qnmQKJ
nFC1xMfvFVQKnMV0sECy8dIEWZJfCfTN1mWXYYbYJqOLPuGN3nQWv/uJTszUo0zHYJJizGe6MkVO
hA1YOw3otmnQcDO/QIHflHsxd/SI6/2lMhByp1ByktBvfItIqeWHL7V9bS/6y0Qm/5HqhGIT9WuB
oWlZ2BMeqv+5ykIwbLzaXDjjrNs0mD1rzYpCHqZ74eHB0HpHuhSDCgca0o4xICUtaLk17PTemHpk
BT/cCDT2Y21RhE9aCb7G7M50wrdFdZkbdB/2CpAd42e+58v7lWKwdds7D7j8itLApATgmwtN5cEa
YJcRAwstY/eiT6EYKqJzihWPPGpo6hEYH70CvcGHgTYQi5/axzXukWUu4jXkP2qt9mRaGn5rUwlX
DbprEaTx34wAbB8aT5g5Ujz9J6OhWftztm9hoen2r8bclxw9APo/8D832nYyZSJUtxKqfHYtuQsK
sBs2FkpqTNe9XapDiG8qba7DBdVvFk96nqUM/n07AYU7tphUxF6OfeATSJ+bv2bnA437AOZ5wNrg
3LkffdxRdeu3nrdJG9antc8s52NMqzATRGaWP1hTxRWKI+QvarZbtR0kUqrt3kMtHgm8HaP4MX+s
fXggQoIngs2hLQ4ArgUrjL4q5wuLxjsvKOkh4tUYgx6QI7iNoVN3lTb3Z2artN2eYWIHL8SwXgTF
NojKGvWdmxHg5S5P1s+VtAovni/MVe68SBWT9Q2hx28KycvaASb8vuM0iYCshktm0LgMgO9xnFfb
0m1noFBQdIOd9hOcj+SxmvgKIgF5YqyS3FVCb0NUJ1yNdGT29ygXc853Glp17zeq7dC3msYyr5rQ
UVR7WIY4MpNS2MAPph7jI1eUS4QozQn5GuOyO5CVoIciDBnbUOntNmNPECkSIT4+1nJQr17pZdM1
6Wqxnqae5ErpH2Vv6x51yMSeWwa3MD8YxHcxp5JpnimcU/UJIxzPX5xqSSoufmtSlW7XEpi6Ulz7
VfHeOKPLgZ+fDJCVIAfEGsHwMKu+uFwkJzrU3yeUM8EgUoz/PqDRjaWRwcvC4T3ZRhkMq7/iiPLY
xZqUHJx4OsjzsoEZGz19g2AKiEsZS6m5hqxypaONcCb6+YwaP3ZgysjFgI9ZxQvlngRinnCpQTY0
BoYzyH3/82zqLxU/7kdbt4pQ8f4obfX0PriFy88S27yIskzW1my7ik5/gn+DhYzQSYj/c94/WePV
Eod8GDvDefS2TrqilqU3zdl9HQIesQyZc7kFsIzFmpfmSxwRu+6GS8PRFs2+brEcDfxyb9TKSsnT
ZbdLQlsKJBwWsjqNMbN16ne/5YX1ky/CPghzboggWrxzAvHhXi8R7BceFRGV6Jc7QsD1ijWGJF6y
hr+GzT2vulZNEU8nQO9xmRX0CD+0DL6gCXW9Vb5sWbk3a/G/DnAbZsfT4gO2TsRI13uff6hLi2Pa
/6bO+EkmBhjouPUeYeHQg0HJnu8YnXZx0cUvSM3YvP/l32TV0oah0qNFFo501MQiIi80v7FepEoF
++F4PCy2dWnTHQafVaaV6IyazBvqqMeouB3FYZog/V73kFLjTBhLrXbbGSuiBhGTxUU5my0WMXDI
klpchIEZGGmyw/KiONohfG/u7zNuls+S8XLxJ+4YbVzsFM2s9hn2IV2Zu1soQjtN2YR7Dz/4bydO
BZc/dOzqKNjj6DyFRAQ7KcQKO+UXz0GqNMtCijwKb0F9hGfSJujnGASEyjwJzNTNW6QI/32PcyhS
nI5fGFDdGU9QmW4rnoPy3NmXpGVYj4vTg4+u0p/gfSiFORc/TvSuPvJZIK0fe6RTxkkizdEJGUQ0
iLRS7OIfEdfHmIPjCWTxWNTNQnDsbSgZ96mFsjpHvOX/6hcVxtTKnflk/Rgb+KC/jtwkPvwr1SVM
I28SxHdOVlU4SxEgXcSO5MlAeoeIUaC2HKWEHmo0kvYQVPdXAWk2XcLVTXnN9uy7aedsQdxWviw+
4/Nd4GWra2SOZ9brd/Z+BmZQrxXQQLNCmJ+VgwCy3NZ/VKvLDDfZ1WDcWrHvt4xaCzaZPP6IJnIy
y53GGtVyVS9w26shWoH4rnM0AtVkpR9AthCQdiamBq2wlOGdhqRRlen73b4X6WLXN9QiIFpJ1h3h
WKItXRM2hbTGa0WaVduTBImWroOGxix5hq0Bhz0TOdNaXDjL+9/zJGv2PpPIIN9K2nTpR0BFuDyP
DjKPF2KW0dqUXePT1sXLEdejZyzetwJT2MYM+pBm7NA1c6mAepHhhaJav1D54Fk7IGCSoknnkGm0
ZBRJTTxdrHAEstIK0iRuGnVR3D46nFjQwugDYzJVXkYozj/jL3Nq38MFy6hbS1FlkZ/J1fonCS/3
pcz7BEera+Ygf66sPIZ0Iu62zx5XhalPGmEYcAyXJvUC1jxoPIcMCi/uygePgO6vG2tOpi8+O7tl
mBYiUHiufvSf7ObCirkvR6Tpnqgs1wLWrmKeBF2TGXjcjvkturzY3+mioXrmcSzU9EEPhHuZxQsB
SjbzPBHnhUxnpejELMZX7BRpkoKAvvdjl/q3geulx6mjpd10Ja8YAgY5EFNtrj1RbMsK5IJyAK4w
+VDG+WIlctWHawSh5T4qgh1jpEAmynGKfhaE/qhscpoZU/Nbgmw3QIg/gcIkbAfPEh7AoYq3WQvS
hJqqwbK7MnpNtMdG+mcSSR7t938jSWeSY3VZ+6ohZfVs7Tsxo2D8Poj+yaD3JkN0WrEADiwiYfHs
LZPKBHIUL2ax/IcDXdmwCWIp14uge+2QHo/ceIoobuTxt26Oze/WJaIKsAnhzMSkoDlKJoURR6LP
oOI1zG667GaIO0wGpxiicCXEzTdupZs6Rg1HVBqXY07iRd6WtYD0prZNSF0LPv5ABr4MeQFc/Ktw
mGZBE3TT8c/bvpNq8wf1tdu+vXxpwsEBKyKCGxOAcktYuFPDSA9tEDpXqbnoCcgLbgT7VIIpTwYp
zy8B5Z8b6mGDmy1AeHy5sADWJWpkZsyPbuuDb4qP5+9FL/nkXZqJtJKYmab77yJzW2V+A9a7LMH2
5dnkan3UrSHc55YUI5T/0TMfE7kBxxb08ewIKIsm9gyK/9U5gTcn2kw5+6sJq+oDZ7CXduIheGrX
OWAjP0sYjY5ZLeAiejf2X7kZnpZtNbhkv2NOgxmBmiVQfgHklwC0S3phukH8efaXqyrTnGQxnawJ
Za/mbB0sLoOYcjBVF8hkoUUIpF8rxCqOIvhbOHqVbuaKY8LmXd9U9Cy8CbN96vEYWMPRcM6jTBrk
QT6NqUh6XOZZ13WlRtR7sDSE+4gXhb662G4l56klErQtmnJzhHPmwfQ4u64l8iR4apliUvGAQBbD
WJrk8Mjq28NIjuaK0WIyiGwdstEqAFGwl99ZvCWmmMeDHuS0fkEsxROhaaUqgK9IXLVA1MJnpyNi
29Qm2ymtGzcRGGNMHd+oIrlHY6zy+zcV+M3HuQTTPbkbiBZRIcWx9PMf3iKmTRduKFvnZegZhPdK
aCAPPGiW+0Ioa6GImyfO+xtsVhUOfrDsfPp5k25d+EMfkxGZRi33DLk5bfECf8STptwZcUltCjtc
IeWPPxq5lPyimAbkc11pM6Y3s1vaWpKZm2DqKsUsqvuyaOu+wYuZsEb7W0lp7ZfKYtrAfznechX5
hP10CP6ekXCjH4cxRe5B4fFuY0VhVmQwtDE9D+0shIW63tRjcvwTl0NhqHSpGbP4tk4I6hHyrTBg
cjV1nQmVoUcFHXffU9dkLrqL7WA2WK0VjmTUXoHK2MIkHifcgCa3Y2t0OB3JQIIe2TSIV0G2j4Jg
kQLug2jIY44KRvx3fEuKa981V3QZxA3kculVORe3JRrmTpEWIQWYpWhxgDejNL3j4H6gdcPX20EN
Gzh8Jmc3MlolXOlLyRTlR+OzQ+Bv1TB7CiF35uYFPp1RkJXrV9hstI1zvT4gPpSetEWUv4dendmC
UFluP1L93YIIyaOLxC3QRIz07rlX3BDVf2xU2ehhE3TZFr7JCybaddFcPngK+2b3IQ6tFQKPO/it
WUBep5R2EdTHec6fTd1VX6MQm7r82kjxgrBZmOKHww82rxwPMnsDaXEcEVw4rpLk+/U9SallGJka
bvMsspYr8bzP9zcdQgFxnQmPq+i3TpEG4Hvy0+CqocuFFj7V6G3Hb3twbuAr8oPghqN9LFo503sS
mUkzQkrAahK/AdVgJE7AWG0CG985B6mIdAzxOQ1FzcG64qXNTRwKrzX6f5OhadJCLGSuRjCZWDfO
x9vPb1Mru12GN7UVaSrkvqSs6J3JhdRjubgWNpmzxrrLZWKGGDp7aAF6I1+UQD3owxlGzEnrXBzo
1/TppEUejfw6Ls2L9tOKloS79SXx16F8Iah6zv5jgN5rqGASEFolHq7AHFl+3MvQB8/k5MpHQV/a
c/X6aXpLr67RWDAsKvdogaLi1142vmefd16ebjJqbixJGdEnKItJlDnNLeTLCd8JDc1o/yevxwmO
lDTLIoI/BUg6ytCbsrt9aYvBp8lCo8tZwpWMh7qXy5DCcCLAwrHS94BzOUZ7KNXchJsQlYF33bFC
ZLTzG53Bl8rcMiwXAq91oEG5NZgBSzhYniDM/3gQgu2oJ4gRHZx/SHp6d5i06w4hRWlzWVzzaifk
A8yhzuNHKFDEemTqeuZxnvmeTpx8++AjKTHAmHZDO/uBvMgBh6sP9NsEuTIM3H6wSCVEisW/XR+U
3c2n+0r9nJ5u0//Ngv8SqsH6ctC/JxqAp/elNxiq3EGJS162eowL83mxQBoa5UUFqpgI8/flVB1a
oTFYeSl2+9Thf0jUinS5zDaoyCIMJTlTmwRUO1hu9pKEEjy3QfuO43BaVxoZ1F9dWq57z4nkO3ku
wglQ8/jeGJ5IF+u+l5fL8uOht9MLCnh8zRm0XYuJ7PxK8GjkeboGrItvx2zQn31AuIFV1cTyWmdt
KavW3ChfBeVx9qJ3n8mKMIlpOAAxwo4C9KLoAqIDKQJRvqYc0QOifLgUXiHMeZ2Qg6F0XefQRTCl
CdzHx7PDh+FXYga4YqDX09DZawCjlIiJZFoZZEtPTw3xew8gIGMaVq1B+zHf2Nkp4MBZdRpcNInZ
K4T5wK1QcVjRJHnLlQKaLgh1SUPc+HTraFs3Xp5v/SmwnF1YzgIvl3Nqr4ckE0mh8xpIvOsK5uVL
Eu5MLAWiGDh9gKSWNIL0/srFw7IsbJogDkcXBYLV9QEb+wYp7og/U/PNuqs2uQsjfkVcJaGFnq23
mQ1Wv2cGIRKrepm2UYcuJ8iKTEGTKjSDSvhuDMfcdratRUOMwqVo1d5y3IlPV6UOp+WqTgINubJ1
ECU0vGZIO/iCcD7VndBkAxsB+KqzPMM7G7hGH7dQPpzPKIv8mxelrI1x1sIIyAQLjrEb1hRoP+Pb
7wg1zJ+zk4xj3l1QIkgjOCPWS0WOIObrFr6taBs+OG5WDmenOOBxXyOwZD8kM5ZFWCgtyAfpcKo1
yxX0AWxJhAWa3enuBoJZmOzpb+R7vHbg1AxT4NLFtOfNPUQUPob/4Ise6V3YAvdO6PGx2Ep4unf2
nExaNqGWY3g6NdTKTZpCjCjSd+H6HK70l50Qy+UpUqLJD6MEC9QTLdv7yPd7aggIydb+zv1OLLyk
dBAWueyhXWVFx3/5XeOpAi/EsSnzSEN6tzpOyQcu1TMxfarwiXQABNWkO8kxiCWl8sD46A9OTzJG
sNGQ+bFOZydphyvoglWHmHo+wy56tzMqQ0olEE38vUJkzWydHSiYASjQZGi9fRr8b61E0FHmCXu3
iMa7rFoRJSkjPsO8n/ReAHHdMs4Rxe0hB46EaKJ319rA6765Fqt43jHIFEREavxfnBi9t0sWm8Fd
RCaX7kefh9rtUwD97kNlF8ZnAVkfbqNjpg46fOOuGuyW2FCnjRZAEK1aU1ypRxuxliqmOsXOgAKm
CFXM8OxPP1UoU9nhGTZVTVzBBpK9ou7viq0fvHx13hl+iqmUP78adjQ9pf2jVI6dipcnU0w+X4+W
5GqKZJnvzvY4OaVl8HLhmKDZxhEScmo9i3n8i3WZDwBpd76BzLUENHS8dm1uAxlFWgwAEYD1xUC+
v6195I+01Cw94Q9i4W68t/hjbuUTltCbT6BAzdEIPqO7LQNYAVdju9vE4hfpRmyDkJ1YJd2RwW2j
mn9d8RFb23fXfsmoXM4jd23nUHnQdhRcAkjK1Fummr9Ei3pFu4/UE853LgfqK3GLI0jLNhpeGmRJ
wGlHcpalkVytpjcGY052FtWQkxvYt23/GSa1978ESiLGpPJY+sfquPOxhlAErsLhGu056oJB9JVS
7igH2MAeJJFJWtx5jErpJrHojwcl5D9/Zk3XF/gQnJYRV9Qh1Uy+y7zr0ZnJhigoyqsvHafB1vJF
s+O8pMyq8jp9mJwTGwleoC8G2mTVigapOZbpapDZFvIE0TKsskJnY5r4fX9bqX8dmIfP3VbXwYWg
lRqLH5RkTS6fLX7Je+HC3pF/nnYtYT+ihMfjYXfwsu1DILsZ6OG9U1sR82fXEjR3aiEfnwXe92bg
MnEPRzJMZHSgtoUGSQlOA2GKMXFpyr18finMCUQBnr4ALqxdL9KlsJaLT1ob6wOUspiM3hB1Qc1p
Q0AaR3uvWgJm/XUuEcbhC/hVGrEkYHndeKwLBgYAhGTo2GlZrJM7zAzw0cJ6i5xa8zNezfTaRokL
cikr3T/CwNt8Ve06XvRrYCFytqqBVu+/bFPnKHJ4gQoo2plDdO0mz5vUo+1lvV2TYOoIOhdSxhaU
bVpXzuDY1PoRZ3vYzIpCdYHZ1vQ1vu9xkiNGtJ1kQ62S6fYWwH+UnPzS2UZETMdFDb9GmsnC/y3i
SSPADSBoPTOK57Y/yf8q8nimWWa2fVSoxhfRshvoXrtU+vyTDArZf4hfuFtfXwk9pWTYoce89IcI
Iq0iA1aJNqbO86O81tu4LAmiAqNPH1tK+iqIlgrWiMeLUnqtsnQ5Nxpl7RYLpDS9huH35JapgySe
zvRUpX9yEaR8Kk3gSGQEKWk2hd3M8S01t1vV4MjR0A6IAmd5ykAGD35mZkRpio3c9blZQet/w+i5
rmOPZgjyHNqQ8DhwDwhnuRNOI0EA/Vh1mh0VyxrGCPIszGCbvP6/+Ytx/32sV4nJsyEglQJHYiC0
Ia9OaUgAuM8dfOxPyhOxdY96ihlmJsAL1cMUpJkA3onc3F6P9/yqYh5mMxYXIodRf/OfgNXIDYJ9
BaLybnqoi7xGAmgDiyF/38Emdw6JP3yrLbcx6iaSkXnZHSysKhZuyVsxrccegvh85Ktf+6JsrrDy
0dYxmshr5/Q1IC1oiMATdftgUbds7hRoR8+4ViB8Yb5yWAHksVsxLypKwMf4NF3iGxqLlljr3a4R
JiyVCTMSE6m3tnpQ7iYgcFD6aI1hRzhfi37pG3/w6xy3PHMyNnxflof7Fuo5GfyJr1jt8RKATJM5
09H7bD9Hjsj9AmIDKeRrl2DlwPSiMCkf24JjFrQLE3YWVgmFNIPK/Ra4NXqgq96crBfZd5TBrg6r
G0krTxKjWnB9l+I3925bSFjPICFj1PlcS0OIydUK7q6hpm+tYjptPYhOkFHMd5weyyBALHGygBxD
OdRi9OzL4d4UnVerEXwwlpQIx1cYWw523hW5I4vp2C+7BLsJ4wkxrcZNMJLcdFPVp8UnHygFPcGi
+U7BPXDtegH8StFu9SZs77KFkfuKjzDbognSg5e/BOT3ewxeO1R0711UaPwXjmxe4B7l68TJ9IHe
rjaCJAVZ3d3+nuEd7APYH7nv7Cuj+MILOKUm5R08vsGP78s/GuZk1IWGdd2rAz3hOnPASkqHc1ZJ
bhZ3Ji4PqcR2DAL+AlBkEiapegiGi2VyA0UFAM9o6TTqzA/wS3VKCkoyCrGYF9/UY3DSYTMEWLTd
wFitHEcYseuaWcfR0B7skh6qSRQ3zTUyLbSfCiwYBgll+e5Epg9twcXSGNGIGMBzrHWfBPbGsbKr
A7Wtuxq0GbOom6aVV8slbCglNWnoMiLza5O8UhJ1xZKCQDobE3/9Q2TFiUjoz/JWM/WRyAcitdzj
keHm7zBmWX2x3Ftg62s1IZtAyx+cu77Ld8+3D7eIuS+PXX/GXOwovPRGJ1BG4MBETEYdcoLUavHd
Wj1f0XXn+GiNqK9LdZFWL1yUCS5PjqU+IMYn5J//xS2Y90MOkw8LLL9yfA2UUJQXxO5MQfJZRUxp
t7WH0Iwmny/unqArNguDWEoWErR/q21FcWh5JOJnG5nNvra33eQUb8dWE/iH9XwrwrxqbALecIen
hatHAOZLDkD5j71F3rFG+IRXJDD0yUhChKy8NxiKVc07JXWkDzw3R0J+ctwRH3Kg5TpEwSaRue7Y
ylVDI6BPX65kUB71FThPU03YXVXGZQGpyZatp+5uc044iiDlKpQBiupFvEYJySLL1VsKciaMIKTA
epmwEMcEqA9JUJUvD16jCAUYoFf5znwhrmMCy8wcu7/gZ14cAiIkPlBD1XllCEGbj1r+c97njFqn
JCEW6dzgaAP3aVCnReagBSt299GA0hMsvo+QRODqvUOdFWIEgru487x8cxgk9AtsF/VQx3DFDlZ2
nRiSIEHIDcAWxzg060Tt35aAnm6F+Yq6BBiSJ9IL5R7kTYrnEUrLtOJEUzgeUhityiYuGZpp8sX3
7NvCeSYgzVJDg1PkXWg8FikSgcGtZf5mJ38MDMV0ahhBHsQSJVSHXo/rwdrdWciNYebfLuo8doOe
jEqcnvGkgWcLgkmL+OdG+MXDlqwek9q2chuakmZxDpLeWL3JzbEGJ/aEppgy17lBj/9+KdE97t9w
ABYOSnXuN2tvdCCzrlkdurSdMe3IzPU0LHNbtDkIUc0p9ocRMketvN5gKJw2CBnwSeM12i/V03w0
mTKy8gXjdUJKL37ShzJ+6SrVRtIyTdexiYxS2Md96evCfD8LKD9rDTZF92UW0iSyLARB1B7AXKM9
z9mN8tf+LTY1Hn6rda10c8h+cYC0FG3FRbw3QMhbZyBAVJvgLDTMfjjwYdY2oMfVx/Iu1aD0j/hM
7I57csV8e+Er17NwX6jRK/oK6rgr3LtbOPwmo11VYWCxEKptMvo0RzvWrifjlMLLKP+on0f1jt9f
9uinb31rdA+Db91CFhhY4XWsbEDnkV9/huSu266c/m+LuZEnK4Ri5MyXFWNsIpRYPjezopsaJeTs
/aU7WIrRC1eUtPQKFzKSQ8aXZctaD75rCbGVram3bFgGoA2TsILiUN/EScYhVUfb7Es3P/GJvEla
8w0RkGfsi/sMkv9JjtaPL6JC9q4TnUOBvSmmdcNwBskK8v3P1GV9NxV7JybgroaL0DAytZdKYAll
yljMIZTiYBOwNhF4ccW8UuJqPuNhGGho+6DleIBNtNqA9M99dg929l3z+Cz3x5da4RDTMKK9wOa4
TyenCFAbvf6EtqKXXpVQz9j67uKxdzfC97yklxeST3pOxVP4QthrvdJnv71NsBF/d/SIVickA7bB
4SQiiFFLcJsE/GqWQi4eQRzj5ixobe7eFs+1F4FeooxlSvB62MzP+IPu8xrNQjoR8xLaqB1l2Ls7
sdw0g2akrdr/FGsjov97rHWongJXd97pORSmlBgKRB+2stGQMj1/bWydYnWnEQZcKWGuW62VZr0R
2BiUkIdupI6LoxNgFRE6xz+txWBkA0wRVUTIVg8gwEnZZmWK5AQgj8y18lHf5nVI266a61rFnLVP
kCEKMw4g44lNzFsorr33acq9Xk0BW3hlEmKbudI9vmMJUdM9xssS8XXcvle3HLUwf1U+/oSeJxbP
NNAaRF7rgzow+nCrAL6LT2ByHRVxBCKbDrRtzDYB8Shj2q7ruCokII9okzAkZgW7PLU2nNMO7rdM
t0/cdRyAMzxS6Q2xVn+GLLR0h4UXIhSCei/Zxkki+zXXnF6D/Z4qQDJmSkGe8+tVn6uWR4lcaRAW
/sxTW7k5CXM8HcNC3DJQoCHucoW5yR7drjg6oT7L7ev62dY6XWMBGlwUwPhznyOBoeZOPP6nxczt
MHaFvZ5Plopjsl9Qzlhz579362beZi0s/jqnv2uUToSV+a5nj3x8+G4KeJcCr6ddITl3yHN5hbuC
KZ5QdtHEkFWN9SfRv7P0anuyFpJoJvtPjHHZ/5uWMTbkGEtjXwYgPYTV31ZQXBMbEGFNC/MMXmfV
43YOTLbeWLALEodY/tlPaXxGmaOnLt/dpGeJeRQV3naeqkcds2LCqSuTkJhmQfDNh5VBrJuFTM3v
rzCFiqlhVHlX/DWyCGMP/p6bxdGe6vM5WKoLxfW/hRSNmN+ehgPpTi1fjKCOjRlpgphP8Dbe2AGr
vydtwTM7k0gobsPVLC77Ahb3iLOVtvsy9ofBucBZJohtmKRcSWojqTkgqBEXddEAje0FFuYrhcHy
J50RR3WZGIsIe4jY9RLZsgEgRMCLgZsCgbkcFGU4Al7iuMKezoBd6yLOVCZ4dnv/lK0nKqiTJT1/
zhcHZgsVHAM7JbFUeZF/6/mBR8fkl5u+B7+dQBSnCZ/q1+s/3v6+HoENG6aMDfOU9MxuWvYZIu5n
zUn68wX8cPa6hKvIkG1rKlksBJUloEeBP2abonZk4U458PlbFZi7SMrMfr5RBb5o31mG+bzviTLc
2qkbHgPEe9I27yOTCU95ev5AaTZyzPnmavsvwaFFbf4wE0pFkZA/28D6X37eWZIdFyqQxRE6Fy5b
AxbSLUO9mnNJxushQHTXl1yuO3I7jHS82Q1vaSDm1WLYuP1GVY5xzq9SzfaE4gZW/y8yivTz7klk
4kg09gdCttYe+09tc3GXJTJ6lOF1bWZOpjf+oQOOX9neuNlvIA9TinFPG0aIDSMFO4IE+RgUBbCf
NTveOYSDYXdvKgyQ424kXcIGrtcJLRlkLxpwKjFgz01QXCo+RCp5gPlhdvbgkag6K8T/ghIYC1c+
jFHXmk6TqpB6TVkQBDGHf1/T8z34b8+c5JqQFEhe4WQtVfH9yHZXqjBr1IclPWBUhx3eGcRNJHrT
PFMp8qWxtve0D5Qh0imAPGB/p9IQXNLAx/aAQnphrnpeWNS0zEeaHmNBBA1DGVBXTZ4h89bPQBJh
/duSNoh2UJWqCyfIQFRr/Ylv7HJT8sEQmQvxUwVmOBF173x0xOIqtaremGz/HEmiKafmQY/pDMZR
1ED4v1VQmMbzH+QTOzpbLSRVyjS06hBdsFHaxM6RvINR3cUo0juhCTEkmS9znBiifQsZRTk6rgYy
XZ9G6k13Kn/OJ4iTfFclLdrCCX2gu7IIkY5a/keTr8efrQAYyzHhLJ6fjHZyAjQoZweXXjIIO+gY
JRmw7/JzSy6EUkVe0OrKfcvEiVXuHc+WPveFVHenBMMAuLRHdZ07irxY5H5cMxBUS7EmV/X/bJ9Z
L8OL0JtCHnYGW16BL+BvxbflxIUomsYcNG59GI85ZuCGRknLD7uGaN6xPKve4lAMzkUPooS7hakb
YFwiX0iMIYHy+iOrc9xlxkAstGq9NNXS6WQWIPDa4W9y6KQDPa8mo3D5gwL8wAWwFhF7tw3pFQSW
i0RKSMit3j0kWyuN6XoI2mzaHpQFb3uyJ6eO3rS72p1MTZgRdFveVDrR9t/R5BTv+16Pj1YRKSlK
f6ZELWf02o+eu+sIsi9o7SOIzEcE8LcX9WIqFqE28+kIC92lisIJQx1newPXrBaY/u4GzUWfD9mu
Nmo+679zIW0/1eLXHLyKKH3Fxl0tfl5PI1/83UaWCbkrZWLJ/iRb8ebt49Ev5E3dtvctFk3L7Fvf
0IBsptGZc0E15/Dm28KZFK6Aj+lH84O7NyutStItkuZOkq44NIOjkblVpbrvrP/euUPiRO9yiViB
kpcY25ZmEWq1Pkq0h/9AYhai1URdxWxTxsgZ5/ybPs5jIYnfvf0IB9tSSngGmULVVJaPa0OrHQTa
afGjTOd22InrPc2AdFLZipYSMFxh77VrGz/3hBVfL37jpAG9RmgwZfjHULBED8iP3Jf2pQP//MTj
0woM0WWWCEvT3/QRW+kOA5gVVMB+R15TCESkl08cfWg82W+42e0Sr2TY2CwkNWReOLCO7aMV7/AR
kGsACvT0L5754v3siVYZG0wwpUYXbQDoxcexM+u7xsOdLLIOIP5G9aDJgOw9g0ecD7ak21TyTrMB
lQB+awiaOUJcbCmjNFAVU+W/0Of+t5LqcayKoleJolN1M4jvoiHhTO5h5HIeo55AWpW/7rPGQ9L7
XRh+iGP+1n8sJc4+owEiXFKtqXlu1ezzfsTZ4IC/Lap7xmFF6iu6jXfr6fuPB+DkA7SHb1ulB7Wp
8twi4Anp3S1CyzIdAFoIus0y1W6vpKbfjtb5jVoQoYkk4fcy8MBPatHxGs8rhUbeZcR6MS6LYJRf
VZFaXyf8yi0y4W/kSwVwWJLoXCy7zM+9FhKI10FL296ybrStxSWF1g4zE1dpyAhsjXotRxLpfXOh
/CkmjykxrNKslr/CyGquYKiQ3HKHDEKKVnVDvjp42NIGGj72+gpQb5FmV4iD34Xfb2HTnXlc6bOh
giBLhUV68LM7Z9SXRiEMye6vvxNXuV/byOoux8dPcmPOoklvKk1HLuuN2nKLqbcb7M0wf1dn9IDR
xLx3GnshcQLAnecyg9VSm9cL0JRy2tiU6uslNNZT9DFCiPb/CfRjpPgbgmbBQcMkb+zi1sNzszqm
Vbmr3rReTf2zFYHNRDZsRlb4TODWFUNYGGILyRzEsu7Y4Z3YJvnyh/yYWD248B+Hgw==
`protect end_protected
| mit | 0b0129ba09c6981c27fb636ba537c478 | 0.949375 | 1.839399 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/ramfifo/rd_handshaking_flags.vhd | 2 | 13,849 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
g4bOKxH8o8kx+mMm905f6D4OkEocbTFEuOWnUlAfDz1JgJyC6q0p8s2CTZXnuRD91Wkr7h7Uw7qz
zlt/r43CPQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
aRU3pqJpFkn/YtzyQL0xqvh4XCSm9jHEAEUEXsTHjc0bznNqVeU4hZJYzdEX46dwlbI5D/PzRZOS
MfkQxhrbFE/f5RAj10oegIaYb53LzKyr/O3HxR1OttWoMSpb9bYPHfn6wvnr4JTwRqkwfOxbp8TL
SGmY5apk2qiOmD0jXY0=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
mGexMw79Xu8QWIQA4dGeXI6BvuB3WIJ/+UQ79wpmeScWNwmuIl3yg7NxEeXgfThmAyqwFoYs++Zc
3ZevvgtDd4JiDkRWqyfMqmFo/qFr4Xfc42DYuWk0MQLHh9VHCQur+6Akxc2tzx+eiKUfVLSo4Kax
Kdpt7LHFIxLwxItkotio0YPjfjVQkMPzmJo3ytmXzALi6R7Xr+MtLZPnynVf3Yx6hG4CYYbMRd2V
Gq7ACzYarx0KVnybj8rcBdMaJVFvhABQTE4Ut6KGCilwV7CI48NI+7TEi0djn81ju55lftNU/96k
79TxuAMl7vC/0G/LnVznyHnsEpVtw/iGEBAitQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
NVbOLeB7E0vOZjx29WOwYeP1FD89o8H3pM8BLNd6mFbZ+Lq0LHGQdEPgABUJXSJ5wSnmLgUYsYOr
7AMz179dK84JUkvHc1TWuLIN5zWLyPr5FUSwRIu8XAxrueCzYVHjM41INtyVom6auDKY44b9URJf
tpuyOqzeFbcgStWmyck=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
t+IxTdyWKgZTKR4Wvy/QpnokiOtVt3oS1s5wqZAztM01e3h5YPIxEQPPIxjXbbZ05c2TScag4ULO
Cuf6DgzfY4Jb11N7IuyHae4Ou9JBQRDJnCDCDJIhUvZSwcF3Rtv4QY4t6tMPnMl1g46Ex70xMz87
McwTbMvnsu4vKNnpQ/8uZ4YbKdXcT3H+tMOqNyKK+QS44hxbWk5nxE6b2vrwBh8DWEVcxRR1oADF
Aq9Rtx2lzeBl5y7v27CEb1c1hHVWiT/48krssUpMQT86GKPc3J52fNn6up35nNU6riBSQrej7OvA
Ui32nNvEGauJrWDnyGvVCAcGOeQtQ5PfwHaAcQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8512)
`protect data_block
rARr7nwpXCUulV14X85/9Aj722WRSUOV6pOcU1mA3V2/C1o9SUUICcCs+ScZArdtMAp5ZUwPPrOu
0wJl7yL40wrDIlBHAsHqYBQKY2LGJTgxsgRU+odQ3BG09kIO80Vdh7gXFSlL3DVC4CzXAxcXYm8U
OT93GIjwOTtyRDDpJ5LyVPCfS/b34Qp4HrF/dGipuQyLlp4aYZ8YIF4SgV6aWAEMxxxQ43Y8lP94
yecv2gsP2npB5WoTD1X/enzgqLQ4I/Lc58CnMC8IrdPN7yfJm7SzGibEm241Y6P2fASB5Ne1znDY
Hqgo6Kl+ALzP3lqZKF8g4yJTeuGahiIrv3xwePeymN7HS9mPXFgZcHjt62tBBN6vOv4qG26dzVjt
4W6j1BEopqOzsLRl/HQnW5eROrTfJRUSyAVzgQC2oGp9H3KnI/MpIKFFDTdS776bPdGdJUhjN58X
2qZ2rfKSHRAPmiwG0X1rR6pcBpmK8XraeGHUnPvAC2db0yK7ZAeTNtBEAri/KVav1/RRn0/QUMdc
xM1m0joQ0/N7nUelRMgQGHKLGsxYkWMFcbo9gC2lAAijZ8tY6Qy8ZKwVdYJLynvsnzVo43fQBpqZ
mHw5MahZtOyJsUtgFNTa9xyC/FmhjoBzs1A4HXhrdvLgbmUNqCecFvf8fHqySJhgS6qksKnSuVPC
aKnpTEfCkYUOpk9J74k0PRBk3VQDq6p7YUa9/3JJPsH9KurcV16iq2NYGVSB1jOxxEFMulNzwVLz
fb3LSq4syaZqq5jsybBPD3RR9EFXvok8laUrlvk5CGABVJrJFZu8gg61uSqjjxrfuAKO5LjJWDiz
XPfxfoSFmd7ik/GtTpl1zM32+wq/tERcMeXPlWUk1pvZLZeKqc/4IR0xI3ekVAx4Prd1Bh4WUcvG
0PrlPDec+g/9CLSVnYpq2oRnkVoSZnEZ2qCaja7EJ0PRQvYtc6LMucDr5xvK3vfspKbPlt7MDwqd
f8ioaAUGEzVbeOUERA/R7C91CMdlm9LfvuBQNItwWzRjZWyejx0RYeRCN98XmkX4SYRyk7yf62Ow
NZYb5Qn4WeJwyZ8/LQnbMahopv69HfD3F9S1qcnUP64AbjDIHg3UyeedoMYPGNPnyr2jrGHUyy/B
5abqXLfmwUoah5YIOJ8oZ3Dbm6IAsdN1fd7NgEzjpjTPrnzWGuPtiDIxIDsfJB5zgxwSJrvNIBhE
PpV8YxgohkPmMfBaXvtXYxYpW2D1osA23Hf6oBBS92aKnI9Rc6eAstQEkTnl/1Wst7dBkzTa55KI
kz21M/SQtbdk1lhFK/VXgiwGvv9qQZOLtIGFit8gxnTpGrIm9wlOLX9/dHTt550a8vRXiYTiU4Vu
x7yIGaifTI+JZSQlhQaj4SJeRjpOkPYA+uL+dTt5rQH+Uh5UhK12uHHUQlrD9Hl1rlW8JY9lX6H9
ETus4JYhLaHQ3kL4ZbrOui8KFaJTATzggu3cfpOy1svzwEn7TbhL/WLq+meCbwjy43JvqOfgbisP
X/+NYxMoiLpMSsdau8bW5jdCkbGFdpiIbtKgdNVb6hC9u8l3WcFk2BykCNvAZhUHb77ayebsBsQm
1ECXTOT1g4knUBie7+WgKrQ13rc16n4XAR1mqAn6EQJ0sGyhZVEmN9/vNzEIpS1gboxxPHIl1LTK
jVOCg02A6E7jv/USVdN1NLCy0OHpObYptPuggTwN5clatMDlUEA7PWDlVQI2fb9gADsGsvAEvDWF
/Qq/o5+HH+y5oQn0vHuu9n4546oED2Pr1khnLdiAPC3vvvbWY3Jfhx2hhI9zEzsyT2FUwhncSRYG
QuOP1ybH2WU0QF6xpYr6FqspyooLO3jyc02LRHBK72UEoFrm9RNdtuNI382Klr5VzE5dcZor7Au3
mRpl8bZ23bm6p4PcYuIfruYlWuyFd70j77d0kYnGatGdohbRr6gQC0hBlsYxCPLyctUG5isJnSka
r+UNWB1D+hs6RC5FNu5B+j+UWydjGTw7vOBHfbD4glztR5KHUmneFOsCTq0k/vs8Lxc85PxDc37a
oi2Ii9eertXAqV0f9eXGogNIDGvlS+7/4C7SFutfFb3DZr6wfcx5Jv6KRqVQm6hej1rXGBbebyZW
qs4JUQrTsPpyiOKNqozTCL0QXnIpXegLH51T0bgwpxUjErbMN8zAAS5xQhZWo8kNv+yzM8VolfZI
/3okLmYsrQovlXTb02eOfrFj+LvGuc91MDIqbN0ZApsGtviW49ORN/e8Kue5bvYxsdcz8i7WIyV7
ZUt2XGnsURDYTS44D3H/f2ZBgeh+dmZRqyRDfrBt+5MjpNeuEqJpwEKc26ECMXG+2vkv6VQ/krIw
OcETwASqWbxa4QScy6Hdj8TifNRIurufPmt4WBMMMWa6Sqv93t32Jv9tsia34lu+Dh/SdBuwb6r6
9M0dyANmRh7+JjPkpPlo4F0WQcPoqILF5Vhu5WEaVtC8b3o/w2+fReE/oLZkMCsSvQHcKR/1IdeJ
YQ5FTdtIIzIWNRzoKopGVAqyDHbsvn7YTpPOPiaWx2El2IguOdVxJboSAo6nUv3pS9wsyqglzOn1
qH6ecq0OASfELdMKqgjal9+w5yh60x6Yo9q5iwrWFlvx0syFF5GZibEdILiotAkgzb1tC3RAOG8D
OxQ/R1md65mj+JoVbsnEwnB/3SA88EHYyQLvGd1UFpLME+d4Ktpy2iIhj88nG0xYVv66YSmCiEkT
Nci8vRBckFmSlsvnrTZV0LLJyHnnaRXkZfujrhTU/cNWkNbLswMsgcJRgdVzOCIAfP7IUhDzuPe2
Tq0KK317nqBbZXgC8lNft/nZv4EdZym/HZ9H2TFNNzLIdu5m6fMblO+pZu9a58gaksL4IlF5geFP
STEE9d8b1aF+OqNhu7sYI1pQtQk5QRXREu8KPSofUQ4eTH2ooMJGTc4TK2sboIFY6nbTy2K/abgv
1A5P0SFW21/RLtD7Lvle0NdZg85GHauubvIsdK3S1OK5L+Q1I0nZ8YHjA6pmR8okvDQpU/9CEXcq
1IMXJ18UW1cA5gRZAJeJx3C9KhwJrvcyzzSF4EyHsVAlUtDvyLk39ROySSOD75Nki47IpP3zgfMm
k/wEBhS52PNUSlE/408Fjjveb8mR6mb3wxPCeSbXK5PF9OEQJ5BKjk1nxqrtvocemi4Zsd/h3lrP
TMJQqVro0jnHGvhAGHTHzguo1F0cWnUSqoWdAMbHx74krtKDkvNQae8suC1od0tvbRVsqgZ5XURC
JALS/YHfewrR4LJ3IquTz0b9uGLLSOLjORDbI3VSx/+Ap0dOXE+vo9VWgtgeS7P8u8CxnX7KNpA9
0mLtcenJ94B0bmE+vmQa86wdXeH6aoKpAqDdIzKjSGIxjuRxSw2lqsEe6VqP+glwdA+HGDW3EnTm
ZfCWfL8a3hnq4YmnZD15zfJp4YJ/30G3XDFB/ymt3WpN5VLBpy4Ssse86fnltXHJAXKq3ak7UYc4
sNZvq4Z4snISEvm3n9xG8Ca5YNhUmShgXFP6d+5Pa0IATYWDm9LDn8E0CUjT3q3OVDV1AK5Rgiwr
rzfIHzWTcf8NAmaTuwAiiMuTbJipVK1qUIxOOvu2M1G0NocjhQF9JkorZDqBfWfxio9hdQ5coxlA
Nl9PFAvlhBL/+uMOJNUs7duHxorl8RD/HaE4tPzOf2/FSSyB5Q0qC2lfUmY8RPZzj8r7Kf5U5pLa
dB1x8Gi3GdT037xOIXkOeWtJS1HgQ//KkcofEa5lM7Y0KHczHlcJ0E1tDpGfP9Jc6tbPH/WP3ixZ
P/K9BpexIJaSfFr3i4Wt7ZNeofsy2QYdJdGDeHaPNDN+dxioy6aECDiO593SJfLv//vTYQGmtEKq
4uASumhXU6mKGQB4212X6cgntrTN9eVtCmtBeS4YzidSedXW+DUEpFFNBGRRIDSn4rg+9unaPWAT
hrjyMngji8WFUm24RXKLEdfN1ybXgqx9xjp17p5dnFyWUQpSeRLOtVbqxhKOAJCXo700SJQerxeB
umn9JZNL+4Mc1Civth0LpR6yOdlwJAg4F0QQ17KOImjkCR1uHgfJVnoCwUVG/0G1hgv6Gou1uXee
7/q5HoqimKgrnE8alpnuN/SXnolM9Ls0U4zaxeyPQ7SvhYPp5eWRRvfud+73iU/h9UwYwr59PTb/
rGbLvMmas8du2FfLPw/vsVhSnuiCx3gBrMKvgoPbK34YzN6HsqvFkjYzrhNOSpaJovpZO/odZm11
DVVcvVYc/nrMY1tOkvPHYlw0RZ4mWFbEfVBlKJ4BgQqOZLvBFvn1/g9fHG8Vdlm0ua6a8Q+coMG/
IjYWYV25qbGaLhzJQjEXLte3phnIhKswlhn+ADkfv/Lp93OUZ5yFWRLoIBQPYlDQCOSsJHIQeGg9
yll0F0z6yfi+BF/kID8rgM7Ky+UPz138CEg2L2NwG+dLtfNLz6K0kKy5nsEcUGRVheYEUnvwDxvH
2Njfz6WAJSzbcZ/TJ009Jje1KskdpB29TcPaEPQjwx9+OlMfZokbBKNnq2LC/en2hNg53EdGnZVH
TWECJlpxgtIywOlDkDLxsPqDv8pCh7BYW7jhuhoooII7sUNSDKoTCw0wu2wlCWLL1tP2HCKMcs71
s1QrusdP2AZGcUefeyxvBJswk14a0lJaEGBWpOhtn/z92z4SURk6fow/ACIlVpc8ZWInwtw+bMaX
rL9mmw9gm8hecEG9pntlT/lo/tuW3GuR0AfgiDX44turTtBg4mkuJVWI+Ka31amoqLl6mZwzZkEM
l/oJYigjHefVOqexw6XAjNohf+irUSpjSZ8XUf1VpzT2+qR90jCW3abcDPsBtaplgI8R8TY6nUNN
J7PgbS9c5PlHZ6wzwJH51G+WzljWK2Jzmhmpjyzqw3WSO72X9FaTQWO8B8x1xY5oXYGz8TJ6/L1f
zcYOOOk4Sf+UzTFVBpZR+tq8UsEYEtWrseZxzc+ibLEX6YRpYaizFXTFUypLK2MkqDqKtD7TC7oK
oWq1lDdo5ajVeRaA0ywPDQeKcgrZV6eKTmk6S0wMTfvQXJskaYGWTCb7M4wq5T4v5zcnGUsRM+Yo
hiYZzy2CZeKxeCyeyi++11OCNAepItbIou/eLbF2bMn6tl2byzrvg6hsyBfCDx5UBFKtkEeC1eoL
x44CkqHg7hGlg41EHqaMWI3yb2l2s8/kOENgaRRDO7ivX/NqSsyYWht8hC8BBRmVJ7CdH55or+if
WE8tXs+YXBXPwsaV52tkcVZbviaNdPyQQGIniUp2S0Xc1xRkw/Xzdkhr53zd0mQhW8Z4uyX/aruz
gIQAMpDYCqXxqP5gQ77W6NGYnbnTXWWatusvHe7wVDzFRQAOAfHplRCSKwYJp2J1PdquYP9ealco
X2QmaPtlu/bv+a6ewyCtmdm2z1tWvp5GN4CRdgKfaReJG2x8E5XfqZVop1VKwnk+nVd7kvqMc8cF
+80FVvG0cumMT+mCqurFRoOYOvsPz09QmsFNPMKrBIUL2CllqwO/NVSVRif+wRmbUErJOICgJTcs
q89SEfkJCnm/ZV1Zf5KBhVOBtyfeLUIXFrksJPt6xFTPiy7xyILatFbYaW70EPPD0bj42r4kcWLg
P35fFM9pDbTGZUeSy+GVrqNtv79cyY1GSLxqOtuhHaPnn2CbOca6CZNAPyoRM8LGjuW3ufTgvCc9
q25MoyGk8IPy4YBT18NWedWfNrxEP79iuzXZ4Am1nyEV1OYrxwdLOxrVooi4e1/RmJ+YZ32TmfUS
BWL78p9Plo4NEe7ZPxKlBpSTdkUtJ/K3tnfTi1hYWzdHNHIscrBADbyF1d58t0bYyfGsn0/IqbJ4
w8SEKnbXlzafA48xBtJfh69/ub/V89Qh9kVIHFmX/8JMQN30TlfsFAf1u/8YInwItCIqA/U+kaP9
E+FL7tQDu6Mcq7v+6p7q1WTmAy9rIXthVIrp7apa9O2vudgEsc+EC0nGdRZzSmBpMvFzJ3Bif8jc
DEo0pD3/0Twi/z1JHsZMtV3M20kZhSpX10c7Ph9Zt0ipL2FTUrC3egC17dFsjfDP1QSTV4XCG37w
gGWjxJlBZA5JAOPtKSA9bS9CddbcmMJStdtLe2m4d/69ao5xM6E/Jpck3WDmd8C+v0OHXJt9ajCT
XitoWxjW7yYMNQwXQOOA+eMjDwZz7bclacM9l3UAiP3o5Xx799djmjPBPgaoQuX6QvVtJd/awxk+
g2gO1RCoKMUr6lMjVIw3vzqZgaGZlL6ciQ7i++KnjmNEOEWsy2oBLp5wluS2SvkheTn2yhCmAS21
3XQwCjFX8NW5rMFlpEAMG7rqEFTA06Q7hqO/M080phfsrZn1EQmFPkjaQdCBow0tHhzURcRuYIVG
6YTZPyVPzhsGkAC4Tq7M8QcdPPdeQBbtyEmYgqIyIa5jQMlZT3rti0Tddqkp6KEhZYronNs8rTw1
BKllK6Wb8oRf/WoEV5PO0sPk+EJc1OxwRVLjOGQYMgtibmQ8C0MDC3AJHqyvJVekcLPXy5eTlzju
NRFEyk7c/5oFv65MvnuPTMr/VnmzT7ObmwQ/gYtrz4/yByMz8gTgyJ77oKEKFvn1NNqLgp+7SlXv
iSxNZQ+ZdRFAe7zds6qVBpMibIpIf+rlWiPVV87N+6bbzMW9EClEcuCRX0PE3Ka/DqHMY06jAn/X
X8eS6IlFZ4i7N9QMZrkXJLsmCitx6G66NOnXmpuFX5Yuon7zTMd0+vPKQsAd73jMe/K2IbvhfDMl
K9CJwJYXtwp1PNUDmaldk7EE4yU6DpHmg9FqVd/3/wue5IcPvoA63HE4EKfiyDp6dsxqCjiswvrn
IVw/X9EfNZRC7Kp5PyuHyo3c5Z2k1B5Ptg5y1oHt69T0nQGKQIgs4J/mBS3lOu1erBjK0bvN7Nsy
nlQSmBmmk+3MMSqMuLaLdQtLyDCiH3JMG62I7cyo416qoxwqSEoo9Bzm0weLeyEOrMaoJ/m5Pc4w
gyMzg4+x/smGG1brfHsFdfMbjfiUDsWA/sAPaSD8tEd02luVdIGPGRpeINNMXqJ1icWj9fSOsa0+
PoRq1Rt96sVkxTB+50mCvI1kcU+0X1K0Nl8T/WW/I3wtcwqQn4L6FUF6fXuCnsLjDPirF3nkxhsk
Wyk13SA5J33TqnAtp8b/ZutNg1E6aJr4u7QilPqXImrRfnlgywJpq8y0AoeiMpJkSUuSFcjtjdoN
TXomGhkBjDvUGDwbVuPHRSuOWWW1xyspwK/ZWfx9ZrdYgFOu1ZPSWuHl3I7hNIcOWn8iInyryPEw
2YwNf5H0zoQfNy95YNJHx2op1KqRqpQ8yhGzMTUX2cwa/2KnOiESxaYQIHirn4yDJYTioT3mywxW
4MOEP/M5yk+CU/IlXQxykHwShJhyb9sWJNurDiiEZjqW4/RStWGlgrhW6sRStpnC8napY4mvCnAo
s3CvZWecnYpRGEUxid6fPxQIhtym9mX5KycwLKSTA0RhehThb9Ao2Ggs+cXafSUyqiufCty9d1BK
Z5FQDNuYPkR0ugkrueY9Pg3YyqWgTyTiMmy4Q2srD7mR3RTOztRttP+kKE8fdra7ny32Iz2Jn0dK
IFE6mHVEGtM/0sjYn57YaJ3ZbalWjf+hRCvgvWmf6gf2iZcSu2wJsGfrwIUCol5bVQllN+04X50e
+mBW+sfUmaqr6QOlJVsHCyVKc9vGwwv+P9bGSR5cfMrz7Bzz/s/IxoFxC+CbwHjsDiO0gjUGvjD5
U8B6vI/BUv4/qmsIqymCnDoiyzP65cJKAnod6MidseYLPYZuZHy2ZFKJV7ydPHATMBTcdq/tD2m1
kKQAoxKWKS2VZAHKO1p7u9vDivoZaHt0yR43fb6OirlGp/JVrRGPl8kBMkSR77+Hw2oPtA1OyUdn
3TyQXlmnpJ/dlv8D8gGVX8rbR1xweK0r4HbfEtxU1mG7M3UeBmCjnDf8RnOxPAss6FhOARVY0qnx
W1t5gTRhysAhV50Sz3SQ/A7qnHw4Qnxhu4AnRYKwKcODbyd68KoNEeeEpeyW/ZXH6nL4YtCs5mQf
z+WugDMJCjxGcjYp78ybwczTg817luDwCdcnbh1STQewYPvCh5V6bXHDWGg0KcM+ogPBqVyO88au
+EMwJcOv0SLFqthlg9FR1SqK8xPUJSKqm7qN1RgiLNVyw0hFtD7ONpWe+bNwKY4OvN58tA9GGo5y
uoixZYbyc41AOjJRqooQ78nY2i6bb7GxP4nLPSqNIViFFOO58tRzGzqqRnlNXf3Y/wCsuF57RmYn
7SVe5CM3Gs1pmRWzcX2RfW5Ek/GmGLO65aXqyE87JNVUtiKH0U5nXxzDlUUWbIt5CcM/YwmkhJJt
O4B4p1lZLNxDJvO/sbypijBDh1ABGdWiJFUUOev7EwwDGqNBRLpzxpfUaA2qU6g4YO+OBWQUgtur
AaGIX+ZgAPskJkLObfMS4xYpOPi8/3ExXdDXoXW/Qu6QrqXpOgJxKwGrMfyshDUFptM559bjAvle
WoE2aiGkSCFoRCfkc7nozWFZF2yrooLXNx2lmS3dksJlRHFVpD3ZuU5Ub99ThIjXj6sMSlVkiFUR
dQVaXrnmiH3zi7L6l91MW4ZEjvLcpgkhtBvbEN26V7rXPKnzxQVvdDLgc/9mCxzwdliA7XKAoii8
RtdV0M6NQLX+h4+FRfwbsQgS7FHNayL291vm/xSacvw0nh+/7nIed+rxQL/TdYL/QqxAsP1cabWm
YVxtwthTmZUwfvbBlKrpxCy+Fs7vd+5Ponbj+noT+itTbru7ZpCcqseVW0snSRJJhYEu4F2Su4ou
8fm/U79muXYKivZ6mh544qIeB30ptHlQWWtwLhqWsOMwGJzEY40Dt9T36UT8bcwdCrSmlxlPwdcD
c9Z022rj7Y6VLyZdxFV6yQQpcv6ldkq3JWk4DB7/t/VVTvYjNryFQwvlTdzfjU1vIpQknSM8F8L2
Pb1TgKS34hPDfBKLO3CZENtXpa3sHvmO37a5CqWbdaF2HjDcrTR4oJnPL8Rb2/iw0X1UDuwDcmfd
Pm8rBmX41jeYAFaBa1xtOuFAlF3qmpIWTKjFD0JbGymG1tqJ3FtF4RyZgWXbL9Xkyk+TyemibBLK
yTLXtJiZUpFtNBzawZrPMVeM/W1p5UcnzpGXDxpKi8APmMRmtmiUBVmjYwPXcsNoTvSIlCDnrAea
GeYlHqoEx156jfB8OVqeDgSxt+bsNns5tOekPeo2YzzfdDnL6B4JRH8a9UDkZ3bDE81ELIZucAwQ
mSYG0EoMj/I2sHkiOjjGvxY09eahJMI6mHBcCNWaxv/LxwjpFKxGBuY/Dr0b0+q0spZAJfMs2oGL
4uV/VxIetDbGn0C6Am7G0TEnjMjaTxqu3vzmKvbG8GQj7CDHUUUw90pytEqGruaV+gQvxEStAE1L
byJWaKzqsAyNycpTPEu44sFei44IdhPXXLXnQe+QKJnrtvcTioNA4bGRVeh9fw1ZYN384IqTO3xk
AzNmC5u/cVG5ncwB7BZMR6/CT8B97QARydqoXVE2ImnAVzfsJosD69mW8MQyhWVjWPYsJ4fjmb7O
4ZJZpRIpElI2M6HW9Xv6YoGxVFPIbmfbU5QTjZW43zgcWDfwihz5O/7SEBosd8DURi3Ub3w/Zkjc
ITR2ROObYRANaImF0iagJpjR+tz7m+aOknJvBZB/CuH3HPTNMF3A/nwyNMn0U0YunULvubZaAkjk
ra+bnNvDZLpK2RaY13saNOEeexefywxTeWuRqkigtdP8TzujaZZtBbe8vkELZXOizAR4GmhK8rJj
DunEQb+5oJ7oJDLtVoeqEGGMjDo3CqPL9Ioi1gJ6JHYsNAQFetHtEzksIMqBBUKkHbjqnVraaH6F
TpvxDOGLVMtDaglO/FVICLW+g3W5uX9C2uWCPQNRbtJMRl5DZ7ymfaGxG6yNwzGhniOYJOTzNrP1
RFu+2iYNI9vt8fE1FsKjlYXCdboOw1En31jDD/u4me9+mUX4xZpqRlZh81fEMMV2LUi35g3lV/hd
3oNCypooffdpFBkuM/a3njUCew7pk+WcolIRWldvLznZp7ijxZm2Unva4rN0hKHcJdhYTe5hPtIQ
aJoKSeZvHkzxteWUPTTLcdkSh7sK7jLxSKnkt0w9vR736tMdXKSdFkjSQzP3DDiElrAPoizmSwy2
AHsm2monuPMjZkXV6neEosFV/sxaRxBJP8yp2Yuh77mYuEl5UEhE7SYekhN8tx6ixkYsBt02SwJd
qHVCnG3wek/mf+mkkdP7bfrFwXJOKtTah05Ib7yW8KrLP+wCqzwvdJrpMCxJHIy1Hr+M6dGENtU/
RHRRLkpMj8hGlZBKdpxP1DLewQFMLqR3tOLnSDHWLGoSIm/M/LXoeIfcKnzcpE6r72dO1LMMXNRU
PgZsaM4eGI5xQx5IiF5OAiATrJILloptfSRWqrmppA8wpS3JWPgHn4oj4V+2VoFmRyfCswOUf9+Y
/zvSrjTlcO7us90s1r4NWCy9vRhlzGQxl+tejYifD1YMFZtsdZyhP9oIq2mmLK51cBfuS5EKjiwV
ntZoc0jT0n8fjN9aYjvINy/iREvJclLTQNDOcJ+EZTxgvRdSVmBDXwin+/AIIKYNY/MqdLnMqvy4
Z/HSUNoai99UKkO3ig9viB7aE3EHi9w3sFljkhI2PRQM5eO2YzTuM6tqgzZypX98veO/agcjas/U
ogE7/rwkGr742LJ/hbwBbNXrNmAtLi1jYaJXW5up0CqYzihIPmgqNQ8xWLgDDMk+aY1TpP3kxfhT
D75kiB+fBYS/r/yE2xBbPQPqFp5BZ/OT0LCyNLQTsFmq70FLDc9Zg0fR42thNnq/eJK7bbhp6Ba0
3bzJ21NNbK1f2qIuyxCdva6fphbqRJNA89PY5B8T7Rvmt6oxfe6VWV6OPbNROT86qIYAnMkoNjvP
X3cbF8V908GXQm5aQLc2wn0aGCCT80s6DB5gDibQTtTp8pT/TqpsNvuPwtOEbXpNaTI/xgQzjZCE
t3Q5PRFO48azFz/MNX5l+axayPGpuKz/I5kGOpcFIhWjlajgclw4LFp6ksTL9i4IefD53U5sKH7w
qaUsT0Nv+efgA5AXTq39gQ4OewaIm0ZOLkoBJnZ/yRbcpbwj/OKa3pU6uS9vnsIo9HePDFV8JHD+
ujguEnvSsvyTRkl6hxJ4qhpeAsYzXNkqEoOhOsD44v7Xw0rIv6cqt0EDIkoN/+1n/g/disKEjKbv
AzH7MHG3Yn554Xpv51GiW2SqZYob+A1+Nn1yVXd7R6uBditpkuBxGu/5Uwd46cB+xgTVwJDffMYM
CBGYdP6RWHPz5pqZRl4g7wkU2A==
`protect end_protected
| bsd-2-clause | bcb017aa07037f7c0eb4cb9f759f2f09 | 0.934797 | 1.883449 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_wr_demux.vhd | 1 | 76,127 | -------------------------------------------------------------------------------
-- axi_datamover_wr_demux.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_wr_demux.vhd
--
-- Description:
-- This file implements the DataMover Master Write Strobe De-Multiplexer.
-- This is needed when the native data width of the DataMover is narrower
-- than the AXI4 Write Data Channel.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_datamover_wr_demux.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
--
-- History:
-- DET 02/15/2011 Initial Version for EDK 13.2
--
-- DET 6/20/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Added 512 and 1024 data width support
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_wr_demux is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the select control bus
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the width of the AXI4 Write Data Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32
-- Indicates the native data width of the DataMover S2MM. If
-- S2MM Store and Forward with upsizer is enabled, the width is
-- the AXi4 Write Data Channel, else it is the S2MM Stream data width.
);
port (
-- AXI MMap Data Channel Input --------------------------------------------
--
wstrb_in : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- data input --
----------------------------------------------------------------------------
-- AXI Master Stream ------------------------------------------------------
--
demux_wstrb_out : Out std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); --
--De-Mux strb output --
----------------------------------------------------------------------------
-- Command Calculator Interface --------------------------------------------
--
debeat_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap Data --
-- Width). --
----------------------------------------------------------------------------
);
end entity axi_datamover_wr_demux;
architecture implementation of axi_datamover_wr_demux is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Decalarations -------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_mux_sel_width
--
-- Function Description:
-- Calculates the number of needed bits for the Mux Select control
-- based on the number of input channels to the mux.
--
-- Note that the number of input mux channels are always a
-- power of 2.
--
-------------------------------------------------------------------
function func_mux_sel_width (num_channels : integer) return integer is
Variable var_sel_width : integer := 0;
begin
case num_channels is
--when 2 =>
-- var_sel_width := 1;
when 4 =>
var_sel_width := 2;
when 8 =>
var_sel_width := 3;
when 16 =>
var_sel_width := 4;
when 32 =>
var_sel_width := 5;
when 64 =>
var_sel_width := 6;
when 128 =>
var_sel_width := 7;
when others =>
var_sel_width := 1;
end case;
Return (var_sel_width);
end function func_mux_sel_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_sel_ls_index
--
-- Function Description:
-- Calculates the LS index of the select field to rip from the
-- input select bus.
--
-- Note that the number of input mux channels are always a
-- power of 2.
--
-------------------------------------------------------------------
function func_sel_ls_index (stream_width : integer) return integer is
Variable var_sel_ls_index : integer := 0;
begin
case stream_width is
when 8 =>
var_sel_ls_index := 0;
when 16 =>
var_sel_ls_index := 1;
when 32 =>
var_sel_ls_index := 2;
when 64 =>
var_sel_ls_index := 3;
when 128 =>
var_sel_ls_index := 4;
when 256 =>
var_sel_ls_index := 5;
when 512 =>
var_sel_ls_index := 6;
when others => -- assume 1024 bit width
var_sel_ls_index := 7;
end case;
Return (var_sel_ls_index);
end function func_sel_ls_index;
-- Constant Decalarations -------------------------------------------------
Constant OMIT_DEMUX : boolean := (C_STREAM_DWIDTH = C_MMAP_DWIDTH);
Constant INCLUDE_DEMUX : boolean := not(OMIT_DEMUX);
Constant STREAM_WSTB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant MMAP_WSTB_WIDTH : integer := C_MMAP_DWIDTH/8;
Constant NUM_MUX_CHANNELS : integer := MMAP_WSTB_WIDTH/STREAM_WSTB_WIDTH;
Constant MUX_SEL_WIDTH : integer := func_mux_sel_width(NUM_MUX_CHANNELS);
Constant MUX_SEL_LS_INDEX : integer := func_sel_ls_index(C_STREAM_DWIDTH);
-- Signal Declarations --------------------------------------------
signal sig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the Output data port
demux_wstrb_out <= sig_demux_wstrb_out;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_STRM_EQ_MMAP
--
-- If Generate Description:
-- This IfGen implements the case where the Stream Data Width is
-- the same as the Memeory Map read Data width.
--
--
------------------------------------------------------------
GEN_STRM_EQ_MMAP : if (OMIT_DEMUX) generate
begin
sig_demux_wstrb_out <= wstrb_in;
end generate GEN_STRM_EQ_MMAP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2XN
--
-- If Generate Description:
-- 2 channel demux case
--
--
------------------------------------------------------------
GEN_2XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 2) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_2XN_DEMUX
--
-- Process Description:
-- Implement the 2XN DeMux
--
-------------------------------------------------------------
DO_2XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when others => -- 1 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
end case;
end process DO_2XN_DEMUX;
end generate GEN_2XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4XN
--
-- If Generate Description:
-- 4 channel demux case
--
--
------------------------------------------------------------
GEN_4XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 4) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_4XN_DEMUX
--
-- Process Description:
-- Implement the 4XN DeMux
--
-------------------------------------------------------------
DO_4XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when others => -- 3 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
end case;
end process DO_4XN_DEMUX;
end generate GEN_4XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8XN
--
-- If Generate Description:
-- 8 channel demux case
--
--
------------------------------------------------------------
GEN_8XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 8) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_8XN_DEMUX
--
-- Process Description:
-- Implement the 8XN DeMux
--
-------------------------------------------------------------
DO_8XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when others => -- 7 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
end case;
end process DO_8XN_DEMUX;
end generate GEN_8XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16XN
--
-- If Generate Description:
-- 16 channel demux case
--
--
------------------------------------------------------------
GEN_16XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 16) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_16XN_DEMUX
--
-- Process Description:
-- Implement the 16XN DeMux
--
-------------------------------------------------------------
DO_16XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when others => -- 15 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
end case;
end process DO_16XN_DEMUX;
end generate GEN_16XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32XN
--
-- If Generate Description:
-- 32 channel demux case
--
--
------------------------------------------------------------
GEN_32XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 32) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_32XN_DEMUX
--
-- Process Description:
-- Implement the 32XN DeMux
--
-------------------------------------------------------------
DO_32XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when 15 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
when 16 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*17)-1 downto STREAM_WSTB_WIDTH*16) <= wstrb_in;
when 17 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*18)-1 downto STREAM_WSTB_WIDTH*17) <= wstrb_in;
when 18 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*19)-1 downto STREAM_WSTB_WIDTH*18) <= wstrb_in;
when 19 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*20)-1 downto STREAM_WSTB_WIDTH*19) <= wstrb_in;
when 20 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*21)-1 downto STREAM_WSTB_WIDTH*20) <= wstrb_in;
when 21 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*22)-1 downto STREAM_WSTB_WIDTH*21) <= wstrb_in;
when 22 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*23)-1 downto STREAM_WSTB_WIDTH*22) <= wstrb_in;
when 23 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*24)-1 downto STREAM_WSTB_WIDTH*23) <= wstrb_in;
when 24 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*25)-1 downto STREAM_WSTB_WIDTH*24) <= wstrb_in;
when 25 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*26)-1 downto STREAM_WSTB_WIDTH*25) <= wstrb_in;
when 26 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*27)-1 downto STREAM_WSTB_WIDTH*26) <= wstrb_in;
when 27 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*28)-1 downto STREAM_WSTB_WIDTH*27) <= wstrb_in;
when 28 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*29)-1 downto STREAM_WSTB_WIDTH*28) <= wstrb_in;
when 29 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*30)-1 downto STREAM_WSTB_WIDTH*29) <= wstrb_in;
when 30 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*31)-1 downto STREAM_WSTB_WIDTH*30) <= wstrb_in;
when others => -- 31 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*32)-1 downto STREAM_WSTB_WIDTH*31) <= wstrb_in;
end case;
end process DO_32XN_DEMUX;
end generate GEN_32XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64XN
--
-- If Generate Description:
-- 64 channel demux case
--
--
------------------------------------------------------------
GEN_64XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 64) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_64XN_DEMUX
--
-- Process Description:
-- Implement the 32XN DeMux
--
-------------------------------------------------------------
DO_64XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when 15 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
when 16 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*17)-1 downto STREAM_WSTB_WIDTH*16) <= wstrb_in;
when 17 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*18)-1 downto STREAM_WSTB_WIDTH*17) <= wstrb_in;
when 18 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*19)-1 downto STREAM_WSTB_WIDTH*18) <= wstrb_in;
when 19 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*20)-1 downto STREAM_WSTB_WIDTH*19) <= wstrb_in;
when 20 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*21)-1 downto STREAM_WSTB_WIDTH*20) <= wstrb_in;
when 21 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*22)-1 downto STREAM_WSTB_WIDTH*21) <= wstrb_in;
when 22 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*23)-1 downto STREAM_WSTB_WIDTH*22) <= wstrb_in;
when 23 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*24)-1 downto STREAM_WSTB_WIDTH*23) <= wstrb_in;
when 24 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*25)-1 downto STREAM_WSTB_WIDTH*24) <= wstrb_in;
when 25 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*26)-1 downto STREAM_WSTB_WIDTH*25) <= wstrb_in;
when 26 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*27)-1 downto STREAM_WSTB_WIDTH*26) <= wstrb_in;
when 27 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*28)-1 downto STREAM_WSTB_WIDTH*27) <= wstrb_in;
when 28 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*29)-1 downto STREAM_WSTB_WIDTH*28) <= wstrb_in;
when 29 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*30)-1 downto STREAM_WSTB_WIDTH*29) <= wstrb_in;
when 30 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*31)-1 downto STREAM_WSTB_WIDTH*30) <= wstrb_in;
when 31 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*32)-1 downto STREAM_WSTB_WIDTH*31) <= wstrb_in;
when 32 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*33)-1 downto STREAM_WSTB_WIDTH*32) <= wstrb_in;
when 33 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*34)-1 downto STREAM_WSTB_WIDTH*33) <= wstrb_in;
when 34 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*35)-1 downto STREAM_WSTB_WIDTH*34) <= wstrb_in;
when 35 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*36)-1 downto STREAM_WSTB_WIDTH*35) <= wstrb_in;
when 36 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*37)-1 downto STREAM_WSTB_WIDTH*36) <= wstrb_in;
when 37 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*38)-1 downto STREAM_WSTB_WIDTH*37) <= wstrb_in;
when 38 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*39)-1 downto STREAM_WSTB_WIDTH*38) <= wstrb_in;
when 39 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*40)-1 downto STREAM_WSTB_WIDTH*39) <= wstrb_in;
when 40 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*41)-1 downto STREAM_WSTB_WIDTH*40) <= wstrb_in;
when 41 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*42)-1 downto STREAM_WSTB_WIDTH*41) <= wstrb_in;
when 42 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*43)-1 downto STREAM_WSTB_WIDTH*42) <= wstrb_in;
when 43 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*44)-1 downto STREAM_WSTB_WIDTH*43) <= wstrb_in;
when 44 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*45)-1 downto STREAM_WSTB_WIDTH*44) <= wstrb_in;
when 45 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*46)-1 downto STREAM_WSTB_WIDTH*45) <= wstrb_in;
when 46 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*47)-1 downto STREAM_WSTB_WIDTH*46) <= wstrb_in;
when 47 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*48)-1 downto STREAM_WSTB_WIDTH*47) <= wstrb_in;
when 48 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*49)-1 downto STREAM_WSTB_WIDTH*48) <= wstrb_in;
when 49 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*50)-1 downto STREAM_WSTB_WIDTH*49) <= wstrb_in;
when 50 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*51)-1 downto STREAM_WSTB_WIDTH*50) <= wstrb_in;
when 51 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*52)-1 downto STREAM_WSTB_WIDTH*51) <= wstrb_in;
when 52 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*53)-1 downto STREAM_WSTB_WIDTH*52) <= wstrb_in;
when 53 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*54)-1 downto STREAM_WSTB_WIDTH*53) <= wstrb_in;
when 54 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*55)-1 downto STREAM_WSTB_WIDTH*54) <= wstrb_in;
when 55 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*56)-1 downto STREAM_WSTB_WIDTH*55) <= wstrb_in;
when 56 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*57)-1 downto STREAM_WSTB_WIDTH*56) <= wstrb_in;
when 57 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*58)-1 downto STREAM_WSTB_WIDTH*57) <= wstrb_in;
when 58 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*59)-1 downto STREAM_WSTB_WIDTH*58) <= wstrb_in;
when 59 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*60)-1 downto STREAM_WSTB_WIDTH*59) <= wstrb_in;
when 60 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*61)-1 downto STREAM_WSTB_WIDTH*60) <= wstrb_in;
when 61 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*62)-1 downto STREAM_WSTB_WIDTH*61) <= wstrb_in;
when 62 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*63)-1 downto STREAM_WSTB_WIDTH*62) <= wstrb_in;
when others => -- 63 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*64)-1 downto STREAM_WSTB_WIDTH*63) <= wstrb_in;
end case;
end process DO_64XN_DEMUX;
end generate GEN_64XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128XN
--
-- If Generate Description:
-- 128 channel demux case
--
--
------------------------------------------------------------
GEN_128XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 128) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_128XN_DEMUX
--
-- Process Description:
-- Implement the 32XN DeMux
--
-------------------------------------------------------------
DO_128XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when 15 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
when 16 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*17)-1 downto STREAM_WSTB_WIDTH*16) <= wstrb_in;
when 17 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*18)-1 downto STREAM_WSTB_WIDTH*17) <= wstrb_in;
when 18 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*19)-1 downto STREAM_WSTB_WIDTH*18) <= wstrb_in;
when 19 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*20)-1 downto STREAM_WSTB_WIDTH*19) <= wstrb_in;
when 20 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*21)-1 downto STREAM_WSTB_WIDTH*20) <= wstrb_in;
when 21 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*22)-1 downto STREAM_WSTB_WIDTH*21) <= wstrb_in;
when 22 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*23)-1 downto STREAM_WSTB_WIDTH*22) <= wstrb_in;
when 23 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*24)-1 downto STREAM_WSTB_WIDTH*23) <= wstrb_in;
when 24 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*25)-1 downto STREAM_WSTB_WIDTH*24) <= wstrb_in;
when 25 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*26)-1 downto STREAM_WSTB_WIDTH*25) <= wstrb_in;
when 26 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*27)-1 downto STREAM_WSTB_WIDTH*26) <= wstrb_in;
when 27 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*28)-1 downto STREAM_WSTB_WIDTH*27) <= wstrb_in;
when 28 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*29)-1 downto STREAM_WSTB_WIDTH*28) <= wstrb_in;
when 29 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*30)-1 downto STREAM_WSTB_WIDTH*29) <= wstrb_in;
when 30 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*31)-1 downto STREAM_WSTB_WIDTH*30) <= wstrb_in;
when 31 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*32)-1 downto STREAM_WSTB_WIDTH*31) <= wstrb_in;
when 32 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*33)-1 downto STREAM_WSTB_WIDTH*32) <= wstrb_in;
when 33 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*34)-1 downto STREAM_WSTB_WIDTH*33) <= wstrb_in;
when 34 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*35)-1 downto STREAM_WSTB_WIDTH*34) <= wstrb_in;
when 35 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*36)-1 downto STREAM_WSTB_WIDTH*35) <= wstrb_in;
when 36 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*37)-1 downto STREAM_WSTB_WIDTH*36) <= wstrb_in;
when 37 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*38)-1 downto STREAM_WSTB_WIDTH*37) <= wstrb_in;
when 38 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*39)-1 downto STREAM_WSTB_WIDTH*38) <= wstrb_in;
when 39 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*40)-1 downto STREAM_WSTB_WIDTH*39) <= wstrb_in;
when 40 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*41)-1 downto STREAM_WSTB_WIDTH*40) <= wstrb_in;
when 41 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*42)-1 downto STREAM_WSTB_WIDTH*41) <= wstrb_in;
when 42 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*43)-1 downto STREAM_WSTB_WIDTH*42) <= wstrb_in;
when 43 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*44)-1 downto STREAM_WSTB_WIDTH*43) <= wstrb_in;
when 44 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*45)-1 downto STREAM_WSTB_WIDTH*44) <= wstrb_in;
when 45 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*46)-1 downto STREAM_WSTB_WIDTH*45) <= wstrb_in;
when 46 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*47)-1 downto STREAM_WSTB_WIDTH*46) <= wstrb_in;
when 47 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*48)-1 downto STREAM_WSTB_WIDTH*47) <= wstrb_in;
when 48 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*49)-1 downto STREAM_WSTB_WIDTH*48) <= wstrb_in;
when 49 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*50)-1 downto STREAM_WSTB_WIDTH*49) <= wstrb_in;
when 50 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*51)-1 downto STREAM_WSTB_WIDTH*50) <= wstrb_in;
when 51 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*52)-1 downto STREAM_WSTB_WIDTH*51) <= wstrb_in;
when 52 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*53)-1 downto STREAM_WSTB_WIDTH*52) <= wstrb_in;
when 53 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*54)-1 downto STREAM_WSTB_WIDTH*53) <= wstrb_in;
when 54 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*55)-1 downto STREAM_WSTB_WIDTH*54) <= wstrb_in;
when 55 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*56)-1 downto STREAM_WSTB_WIDTH*55) <= wstrb_in;
when 56 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*57)-1 downto STREAM_WSTB_WIDTH*56) <= wstrb_in;
when 57 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*58)-1 downto STREAM_WSTB_WIDTH*57) <= wstrb_in;
when 58 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*59)-1 downto STREAM_WSTB_WIDTH*58) <= wstrb_in;
when 59 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*60)-1 downto STREAM_WSTB_WIDTH*59) <= wstrb_in;
when 60 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*61)-1 downto STREAM_WSTB_WIDTH*60) <= wstrb_in;
when 61 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*62)-1 downto STREAM_WSTB_WIDTH*61) <= wstrb_in;
when 62 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*63)-1 downto STREAM_WSTB_WIDTH*62) <= wstrb_in;
when 63 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*64)-1 downto STREAM_WSTB_WIDTH*63) <= wstrb_in;
when 64 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*65)-1 downto STREAM_WSTB_WIDTH*64) <= wstrb_in;
when 65 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*66)-1 downto STREAM_WSTB_WIDTH*65) <= wstrb_in;
when 66 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*67)-1 downto STREAM_WSTB_WIDTH*66) <= wstrb_in;
when 67 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*68)-1 downto STREAM_WSTB_WIDTH*67) <= wstrb_in;
when 68 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*69)-1 downto STREAM_WSTB_WIDTH*68) <= wstrb_in;
when 69 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*70)-1 downto STREAM_WSTB_WIDTH*69) <= wstrb_in;
when 70 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*71)-1 downto STREAM_WSTB_WIDTH*70) <= wstrb_in;
when 71 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*72)-1 downto STREAM_WSTB_WIDTH*71) <= wstrb_in;
when 72 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*73)-1 downto STREAM_WSTB_WIDTH*72) <= wstrb_in;
when 73 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*74)-1 downto STREAM_WSTB_WIDTH*73) <= wstrb_in;
when 74 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*75)-1 downto STREAM_WSTB_WIDTH*74) <= wstrb_in;
when 75 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*76)-1 downto STREAM_WSTB_WIDTH*75) <= wstrb_in;
when 76 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*77)-1 downto STREAM_WSTB_WIDTH*76) <= wstrb_in;
when 77 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*78)-1 downto STREAM_WSTB_WIDTH*77) <= wstrb_in;
when 78 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*79)-1 downto STREAM_WSTB_WIDTH*78) <= wstrb_in;
when 79 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*80)-1 downto STREAM_WSTB_WIDTH*79) <= wstrb_in;
when 80 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*81)-1 downto STREAM_WSTB_WIDTH*80) <= wstrb_in;
when 81 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*82)-1 downto STREAM_WSTB_WIDTH*81) <= wstrb_in;
when 82 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*83)-1 downto STREAM_WSTB_WIDTH*82) <= wstrb_in;
when 83 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*84)-1 downto STREAM_WSTB_WIDTH*83) <= wstrb_in;
when 84 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*85)-1 downto STREAM_WSTB_WIDTH*84) <= wstrb_in;
when 85 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*86)-1 downto STREAM_WSTB_WIDTH*85) <= wstrb_in;
when 86 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*87)-1 downto STREAM_WSTB_WIDTH*86) <= wstrb_in;
when 87 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*88)-1 downto STREAM_WSTB_WIDTH*87) <= wstrb_in;
when 88 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*89)-1 downto STREAM_WSTB_WIDTH*88) <= wstrb_in;
when 89 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*90)-1 downto STREAM_WSTB_WIDTH*89) <= wstrb_in;
when 90 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*91)-1 downto STREAM_WSTB_WIDTH*90) <= wstrb_in;
when 91 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*92)-1 downto STREAM_WSTB_WIDTH*91) <= wstrb_in;
when 92 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*93)-1 downto STREAM_WSTB_WIDTH*92) <= wstrb_in;
when 93 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*94)-1 downto STREAM_WSTB_WIDTH*93) <= wstrb_in;
when 94 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*95)-1 downto STREAM_WSTB_WIDTH*94) <= wstrb_in;
when 95 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*96)-1 downto STREAM_WSTB_WIDTH*95) <= wstrb_in;
when 96 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*97 )-1 downto STREAM_WSTB_WIDTH*96 ) <= wstrb_in;
when 97 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*98 )-1 downto STREAM_WSTB_WIDTH*97 ) <= wstrb_in;
when 98 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*99 )-1 downto STREAM_WSTB_WIDTH*98 ) <= wstrb_in;
when 99 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*100)-1 downto STREAM_WSTB_WIDTH*99 ) <= wstrb_in;
when 100 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*101)-1 downto STREAM_WSTB_WIDTH*100) <= wstrb_in;
when 101 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*102)-1 downto STREAM_WSTB_WIDTH*101) <= wstrb_in;
when 102 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*103)-1 downto STREAM_WSTB_WIDTH*102) <= wstrb_in;
when 103 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*104)-1 downto STREAM_WSTB_WIDTH*103) <= wstrb_in;
when 104 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*105)-1 downto STREAM_WSTB_WIDTH*104) <= wstrb_in;
when 105 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*106)-1 downto STREAM_WSTB_WIDTH*105) <= wstrb_in;
when 106 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*107)-1 downto STREAM_WSTB_WIDTH*106) <= wstrb_in;
when 107 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*108)-1 downto STREAM_WSTB_WIDTH*107) <= wstrb_in;
when 108 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*109)-1 downto STREAM_WSTB_WIDTH*108) <= wstrb_in;
when 109 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*110)-1 downto STREAM_WSTB_WIDTH*109) <= wstrb_in;
when 110 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*111)-1 downto STREAM_WSTB_WIDTH*110) <= wstrb_in;
when 111 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*112)-1 downto STREAM_WSTB_WIDTH*111) <= wstrb_in;
when 112 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*113)-1 downto STREAM_WSTB_WIDTH*112) <= wstrb_in;
when 113 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*114)-1 downto STREAM_WSTB_WIDTH*113) <= wstrb_in;
when 114 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*115)-1 downto STREAM_WSTB_WIDTH*114) <= wstrb_in;
when 115 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*116)-1 downto STREAM_WSTB_WIDTH*115) <= wstrb_in;
when 116 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*117)-1 downto STREAM_WSTB_WIDTH*116) <= wstrb_in;
when 117 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*118)-1 downto STREAM_WSTB_WIDTH*117) <= wstrb_in;
when 118 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*119)-1 downto STREAM_WSTB_WIDTH*118) <= wstrb_in;
when 119 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*120)-1 downto STREAM_WSTB_WIDTH*119) <= wstrb_in;
when 120 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*121)-1 downto STREAM_WSTB_WIDTH*120) <= wstrb_in;
when 121 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*122)-1 downto STREAM_WSTB_WIDTH*121) <= wstrb_in;
when 122 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*123)-1 downto STREAM_WSTB_WIDTH*122) <= wstrb_in;
when 123 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*124)-1 downto STREAM_WSTB_WIDTH*123) <= wstrb_in;
when 124 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*125)-1 downto STREAM_WSTB_WIDTH*124) <= wstrb_in;
when 125 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*126)-1 downto STREAM_WSTB_WIDTH*125) <= wstrb_in;
when 126 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*127)-1 downto STREAM_WSTB_WIDTH*126) <= wstrb_in;
when others => -- 127 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*128)-1 downto STREAM_WSTB_WIDTH*127) <= wstrb_in;
end case;
end process DO_128XN_DEMUX;
end generate GEN_128XN;
end implementation;
| bsd-2-clause | 03f3f18ee9488a51acd537f49fb38258 | 0.389244 | 5.159753 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/generic/rule_007_test_input.vhd | 1 | 1,897 |
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32;
prefix_GENERIC_suffix : integer := 20
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32;
PREFIX_GENERIC_suffix : integer := 20
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32;
prefix_GENERIC_SUFFIX : integer := 20
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32;
PREFIX_GENERIC_SUFFIX : integer := 20
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
entity FIFO is
generic(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32;
prefix_generic_suffix : integer := 20
);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
entity FIFO is
generic(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32;
PREFIX_generic_suffix : integer := 20
);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
entity FIFO is
generic(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32;
prefix_generic_SUFFIX : integer := 20
);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
entity FIFO is
generic(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32;
PREFIX_generic_SUFFIX : integer := 20
);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
| gpl-3.0 | 2bff0be493caa0635cb1abea00995b4e | 0.573537 | 3.120066 | false | false | false | false |
Yarr/Yarr-fw | rtl/kintex7/wbexp-core/l2p_arbiter.vhd | 1 | 9,232 | -------------------------------------------------------------------------------
-- --
-- CERN BE-CO-HT GN4124 core for PCIe FMC carrier --
-- http://www.ohwr.org/projects/gn4124-core --
-------------------------------------------------------------------------------
--
-- unit name: GN4124 core arbiter (arbiter.vhd)
--
-- authors: Simon Deprez ([email protected])
-- Matthieu Cattin ([email protected])
--
-- date: 12-08-2010
--
-- version: 0.1
--
-- description: Arbitrates PCIe accesses between Wishbone master,
-- L2P DMA master and P2L DMA master
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- last changes: 23-09-2010 (mcattin) Add FF on data path and
-- change valid request logic
-- 26.02.2014 (theim) Changed priority order (swapped LDM <-> PDM)
-- 20.12.2016 (astaux) Apdapted for AXI-Stream bus
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity l2p_arbiter is
generic(
axis_data_width_c : integer := 64
);
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- From Wishbone master (wbm) to arbiter (arb)
wbm_arb_tdata_i : in std_logic_vector (axis_data_width_c - 1 downto 0);
wbm_arb_tkeep_i : in std_logic_vector (axis_data_width_c/8 - 1 downto 0);
wbm_arb_tlast_i : in std_logic;
wbm_arb_tvalid_i : in std_logic;
wbm_arb_tready_o : out std_logic;
wbm_arb_req_i : in std_logic;
arb_wbm_gnt_o : out std_logic;
---------------------------------------------------------
-- From P2L DMA master (pdm) to arbiter (arb)
pdm_arb_tdata_i : in std_logic_vector (axis_data_width_c - 1 downto 0);
pdm_arb_tkeep_i : in std_logic_vector (axis_data_width_c/8 - 1 downto 0);
pdm_arb_tlast_i : in std_logic;
pdm_arb_tvalid_i : in std_logic;
pdm_arb_tready_o : out std_logic;
pdm_arb_req_i : in std_logic;
arb_pdm_gnt_o : out std_logic;
---------------------------------------------------------
-- From L2P DMA master (ldm) to arbiter (arb)
ldm_arb_tdata_i : in std_logic_vector (axis_data_width_c - 1 downto 0);
ldm_arb_tkeep_i : in std_logic_vector (axis_data_width_c/8 - 1 downto 0);
ldm_arb_tlast_i : in std_logic;
ldm_arb_tvalid_i : in std_logic;
ldm_arb_tready_o : out std_logic;
ldm_arb_req_i : in std_logic;
arb_ldm_gnt_o : out std_logic;
---------------------------------------------------------
-- From arbiter (arb) to pcie_tx (tx)
axis_tx_tdata_o : out STD_LOGIC_VECTOR (axis_data_width_c - 1 downto 0);
axis_tx_tkeep_o : out STD_LOGIC_VECTOR (axis_data_width_c/8 - 1 downto 0);
axis_tx_tuser_o : out STD_LOGIC_VECTOR (3 downto 0);
axis_tx_tlast_o : out STD_LOGIC;
axis_tx_tvalid_o : out STD_LOGIC;
axis_tx_tready_i : in STD_LOGIC;
---------------------------------------------------------
-- Debug
eop_do : out std_logic
);
end l2p_arbiter;
architecture rtl of l2p_arbiter is
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal wbm_arb_req_valid : std_logic;
signal pdm_arb_req_valid : std_logic;
signal ldm_arb_req_valid : std_logic;
signal arb_wbm_gnt : std_logic;
signal arb_pdm_gnt : std_logic;
signal arb_ldm_gnt : std_logic;
signal eop : std_logic; -- End of packet
signal axis_tx_tvalid_t : std_logic;
signal axis_tx_tlast_t : std_logic;
signal axis_tx_tdata_t : std_logic_vector(axis_data_width_c - 1 downto 0);
signal axis_tx_tkeep_t : std_logic_vector(axis_data_width_c/8 - 1 downto 0);
constant c_RST_ACTIVE : std_logic := '0';
begin
-- A request is valid only if the access not already granted to another source
wbm_arb_req_valid <= wbm_arb_req_i and (not(arb_pdm_gnt) and not(arb_ldm_gnt));
pdm_arb_req_valid <= pdm_arb_req_i and (not(arb_wbm_gnt) and not(arb_ldm_gnt));
ldm_arb_req_valid <= ldm_arb_req_i and (not(arb_wbm_gnt) and not(arb_pdm_gnt));
eop_do <= eop;
-- Detect end of packet to delimit the arbitration phase
-- eop <= ((arb_wbm_gnt and not(wbm_arb_dframe_i) and wbm_arb_valid_i) or
-- (arb_pdm_gnt and not(pdm_arb_dframe_i) and pdm_arb_valid_i) or
-- (arb_ldm_gnt and not(ldm_arb_dframe_i) and ldm_arb_valid_i));
process (clk_i, rst_n_i)
begin
if (rst_n_i = c_RST_ACTIVE) then
eop <= '0';
elsif rising_edge(clk_i) then
if ((arb_wbm_gnt = '1' and wbm_arb_tlast_i = '1') or
(arb_pdm_gnt = '1' and pdm_arb_tlast_i = '1') or
(arb_ldm_gnt = '1' and ldm_arb_tlast_i = '1')) then
eop <= '1';
else
eop <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Arbitration is started when a valid request is present and ends when the
-- EOP condition is detected
--
-- Strict priority arbitration scheme
-- Highest : WBM request
-- : LDM request
-- Lowest : PDM request
-----------------------------------------------------------------------------
process (clk_i, rst_n_i)
begin
if(rst_n_i = c_RST_ACTIVE) then
arb_wbm_gnt <= '0';
arb_pdm_gnt <= '0';
arb_ldm_gnt <= '0';
elsif rising_edge(clk_i) then
--if (arb_req_valid = '1') then
if (eop = '1') then
arb_wbm_gnt <= '0';
arb_pdm_gnt <= '0';
arb_ldm_gnt <= '0';
elsif (wbm_arb_req_valid = '1') then
arb_wbm_gnt <= '1';
arb_pdm_gnt <= '0';
arb_ldm_gnt <= '0';
elsif (ldm_arb_req_valid = '1') then
arb_wbm_gnt <= '0';
arb_pdm_gnt <= '0';
arb_ldm_gnt <= '1';
elsif (pdm_arb_req_valid = '1') then
arb_wbm_gnt <= '0';
arb_pdm_gnt <= '1';
arb_ldm_gnt <= '0';
end if;
end if;
end process;
process (clk_i, rst_n_i)
begin
if rst_n_i = '0' then
axis_tx_tvalid_t <= '0';
axis_tx_tlast_t <= '0';
axis_tx_tdata_t <= (others => '0');
axis_tx_tkeep_t <= (others => '0');
elsif rising_edge(clk_i) then
if arb_wbm_gnt = '1' then
axis_tx_tvalid_t <= wbm_arb_tvalid_i;
axis_tx_tlast_t <= wbm_arb_tlast_i;
axis_tx_tdata_t <= wbm_arb_tdata_i;
axis_tx_tkeep_t <= wbm_arb_tkeep_i;
elsif arb_pdm_gnt = '1' then
axis_tx_tvalid_t <= pdm_arb_tvalid_i;
axis_tx_tlast_t <= pdm_arb_tlast_i;
axis_tx_tdata_t <= pdm_arb_tdata_i;
axis_tx_tkeep_t <= pdm_arb_tkeep_i;
elsif arb_ldm_gnt = '1' then
axis_tx_tvalid_t <= ldm_arb_tvalid_i;
axis_tx_tlast_t <= ldm_arb_tlast_i;
axis_tx_tdata_t <= ldm_arb_tdata_i;
axis_tx_tkeep_t <= ldm_arb_tkeep_i;
else
axis_tx_tvalid_t <= '0';
axis_tx_tlast_t <= '0';
axis_tx_tdata_t <= (others => '0');
axis_tx_tkeep_t <= (others => '0');
end if;
end if;
end process;
process (clk_i, rst_n_i)
begin
if rst_n_i = c_RST_ACTIVE then
axis_tx_tvalid_o <= '0';
axis_tx_tlast_o <= '0';
axis_tx_tdata_o <= (others => '0');
axis_tx_tkeep_o <= (others => '0');
elsif rising_edge(clk_i) then
axis_tx_tvalid_o <= axis_tx_tvalid_t;
axis_tx_tlast_o <= axis_tx_tlast_t;
axis_tx_tdata_o <= axis_tx_tdata_t;
axis_tx_tkeep_o <= axis_tx_tkeep_t;
end if;
end process;
arb_wbm_gnt_o <= arb_wbm_gnt;
arb_pdm_gnt_o <= arb_pdm_gnt;
arb_ldm_gnt_o <= arb_ldm_gnt;
wbm_arb_tready_o <= axis_tx_tready_i and arb_wbm_gnt;
pdm_arb_tready_o <= axis_tx_tready_i and arb_pdm_gnt;
ldm_arb_tready_o <= axis_tx_tready_i and arb_ldm_gnt;
axis_tx_tuser_o <= "0000";
end rtl;
| gpl-3.0 | afdde28358ae54dd079f7c4a608706bf | 0.504224 | 3.395366 | false | false | false | false |
Logistic1994/CPU | module_Rn.vhd | 1 | 2,113 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:07:20 05/20/2015
-- Design Name:
-- Module Name: module_Rn - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity module_Rn is
port(
clk_RN: in std_logic;
nreset: in std_logic;
Rn_CS: in std_logic; -- µ±Rn_CS='0'²¢ÇÒ´¦ÓÚ¶ÁµÄʱºò£¬¶ÁÈ¡RDÀïÃæµÄÊý¾Ý
nRi_EN: in std_logic; -- µÍµçƽÓÐЧ
RDRi, WRRi: in std_logic; -- ¸ßµçƽÓÐЧ
RS: in std_logic;
RD: in std_logic;
datai: in std_logic_vector(7 downto 0);
datao: out std_logic_vector(7 downto 0);
do: out std_logic);
end module_Rn;
architecture Behavioral of module_Rn is
signal d0, d1: std_logic_vector(7 downto 0);
begin
process(nreset, clk_RN)
begin
if nreset = '0' then
d0 <= (others => '0');
d1 <= (others => '0');
elsif rising_edge(clk_RN) then
if nRi_EN = '0' then
if RDRi = '1' then
if Rn_CS = '1' then
if RS = '0' then
datao <= d0;
do <= '1';
else
datao <= d1;
do <= '1';
end if;
else
if RD = '0' then
datao <= d0;
do <= '1';
else
datao <= d1;
do <= '1';
end if;
end if;
elsif WRRi = '1' then
if RD = '0' then
d0 <= datai;
else
d1 <= datai;
end if;
datao <= (others => 'Z');
do <= '0';
else
datao <= (others => 'Z');
do <= '0';
end if;
else
datao <= (others => 'Z');
do <= '0';
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | 7fbcc50d9cd959ca7a79742bc2361dfe | 0.522953 | 2.878747 | false | false | false | false |
NicoLedwith/Dr.AluOpysel | RAT_MCU/VGA_Stuff/RAT_Wrapper_vga_only_F14.vhd | 1 | 9,163 | ----------------------------------------------------------------------------------
-- Company: RAT Technologies
-- Engineer: Various RAT rats
--
-- Create Date: 1/31/2012
-- Design Name:
-- Module Name: RAT_wrapper - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Wrapper for RAT MCU including a VGA Driver. This model provides a
-- template to interface the RAT MCU and VGA Driver to the Nexys2 board.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RAT_wrapper is
Port ( LEDS : out STD_LOGIC_VECTOR (7 downto 0);
SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0);
SSEG_EN : out STD_LOGIC_VECTOR (3 downto 0);
SWITCHES : in STD_LOGIC_VECTOR (7 downto 0);
RESET : in STD_LOGIC;
CLK : in STD_LOGIC;
-- VGA support signals -----------------------------
VGA_RGB : out std_logic_vector(7 downto 0);
VGA_HS : out std_logic;
VGA_VS : out std_logic);
end RAT_wrapper;
architecture Behavioral of RAT_wrapper is
-------------------------------------------------------------------------------
-- INPUT PORT IDS -------------------------------------------------------------
-- Right now, the only possible inputs are the switches
-- In future labs you can add more port IDs, and you'll have
-- to add constants here for the mux below
CONSTANT SWITCHES_ID : STD_LOGIC_VECTOR (7 downto 0) := x"20";
CONSTANT VGA_READ_ID : STD_LOGIC_VECTOR(7 downto 0) := x"93";
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- OUTPUT PORT IDS ------------------------------------------------------------
-- In future labs you can add more port IDs
CONSTANT LEDS_ID : STD_LOGIC_VECTOR (7 downto 0) := X"40";
CONSTANT SEGMENTS_ID : STD_LOGIC_VECTOR (7 downto 0) := X"82";
CONSTANT DISP_EN_ID : STD_LOGIC_VECTOR (7 downto 0) := X"83";
CONSTANT VGA_HADDR_ID : STD_LOGIC_VECTOR(7 downto 0) := x"90";
CONSTANT VGA_LADDR_ID : STD_LOGIC_VECTOR(7 downto 0) := x"91";
CONSTANT VGA_WRITE_ID : STD_LOGIC_VECTOR(7 downto 0) := x"92";
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Declare RAT_MCU ------------------------------------------------------------
component RAT_MCU
Port ( IN_PORT : in STD_LOGIC_VECTOR (7 downto 0);
OUT_PORT : out STD_LOGIC_VECTOR (7 downto 0);
PORT_ID : out STD_LOGIC_VECTOR (7 downto 0);
IO_STRB : out STD_LOGIC;
RESET : in STD_LOGIC;
INT : in STD_LOGIC;
CLK : in STD_LOGIC);
end component RAT_MCU;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Declare VGA Driver ---------------------------------------------------------
component vgaDriverBuffer is
Port (CLK, we : in std_logic;
wa : in std_logic_vector (10 downto 0);
wd : in std_logic_vector (7 downto 0);
Rout : out std_logic_vector(2 downto 0);
Gout : out std_logic_vector(2 downto 0);
Bout : out std_logic_vector(1 downto 0);
HS : out std_logic;
VS : out std_logic;
pixelData : out std_logic_vector(7 downto 0));
end component;
-------------------------------------------------------------------------------
-- Declare one_shot -----------------------------------------------------------
--component db_1shot
-- Port ( A, CLK: in STD_LOGIC;
-- A_DB : out STD_LOGIC);
--end component;
-- Signals for connecting RAT_MCU to RAT_wrapper -------------------------------
signal s_input_port : std_logic_vector (7 downto 0);
signal s_output_port : std_logic_vector (7 downto 0);
signal s_port_id : std_logic_vector (7 downto 0);
signal s_load : std_logic;
--signal s_interrupt : std_logic;
-- VGA signals
signal s_vga_we : std_logic; -- Write enable
signal r_vga_wa : std_logic_vector(10 downto 0); -- Address to read from/write to
signal r_vga_wd : std_logic_vector(7 downto 0); -- Pixel data to write to framebuffer
signal r_vgaData : std_logic_vector(7 downto 0); -- Pixel data read from framebuffer
-- Register definitions for output devices ------------------------------------
signal r_LEDS : std_logic_vector (7 downto 0) := (others => '0');
signal r_SEGMENTS : std_logic_vector (7 downto 0) := (others => '0');
signal r_DISP_EN : std_logic_vector (3 downto 0) := (others => '0');
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Instantiate the one-shot ---------------------------------------------
--my_db: db_1shot
--Port map ( A => BUTTON,
-- CLK => CLK,
-- A_DB => s_interrupt);
-------------------------------------------------------------------------------
-- Instantiate RAT_MCU --------------------------------------------------------
MCU: RAT_MCU
port map( IN_PORT => s_input_port,
OUT_PORT => s_output_port,
PORT_ID => s_port_id,
RESET => RESET,
IO_STRB => s_load,
INT => '0', -- s_interrupt,
CLK => CLK);
-------------------------------------------------------------------------------
-- Instantiate the VGA Driver
VGA: vgaDriverBuffer
port map(CLK => CLK,
WE => s_vga_we,
WA => r_vga_wa,
WD => r_vga_wd,
Rout => VGA_RGB(7 downto 5),
Gout => VGA_RGB(4 downto 2),
Bout => VGA_RGB(1 downto 0),
HS => VGA_HS,
VS => VGA_VS,
pixelData => r_vgaData);
-------------------------------------------------------------------------------
-- MUX for selecting what input to read ---------------------------------------
-------------------------------------------------------------------------------
inputs: process(s_port_id, SWITCHES)
begin
if (s_port_id = SWITCHES_ID) then
s_input_port <= SWITCHES;
elsif (s_port_id = VGA_READ_ID) then
s_input_port <= r_vgaData;
else
s_input_port <= x"00";
end if;
end process inputs;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- MUX for updating output registers ------------------------------------------
-- Register updates depend on rising clock edge and asserted load signal
-------------------------------------------------------------------------------
outputs: process(CLK)
begin
if (rising_edge(CLK)) then
if (s_load = '1') then
-- the register definition for the LEDS
if (s_port_id = LEDS_ID) then
r_LEDS <= s_output_port;
elsif (s_port_id = SEGMENTS_ID) then
r_SEGMENTS <= s_output_port;
elsif (s_port_id = DISP_EN_ID) then
r_DISP_EN <= s_output_port(3 downto 0);
-- VGA support -------------------------------------------
elsif (s_port_id = VGA_HADDR_ID) then
r_vga_wa(10 downto 8) <= s_output_port(2 downto 0);
elsif (s_port_id = VGA_LADDR_ID) then
r_vga_wa(7 downto 0) <= s_output_port;
elsif (s_port_id = VGA_WRITE_ID) then
r_vga_wd <= s_output_port;
end if;
if (s_port_id = VGA_WRITE_ID ) then
s_vga_we <= '1';
else
s_vga_we <= '0';
end if;
end if;
end if;
end process outputs;
-------------------------------------------------------------------------------
-- Register Interface Assignments ---------------------------------------------
LEDS <= r_LEDS;
SEGMENTS <= r_SEGMENTS;
SSEG_EN <= r_DISP_EN;
-------------------------------------------------------------------------------
end Behavioral;
| mit | 79bb80e08cc8e5a8093899ea3b8cb0e3 | 0.382953 | 4.863588 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/concurrent/rule_005_test_input.vhd | 1 | 548 |
architecture RTL of FIFO is
begin
-- These are passing
postponed a <= b;
postponed a <= when c = '0' else '1';
postponed with z select
a <= b when z = "000",
c when z = "001";
a <= b;
a <= when c = '0' else '1';
with z select
a <= b when z = "000",
c when z = "001";
-- These are failing
SIG_LABEL : postponed a <= b;
SIG_LABEL : postponed a <= when c = '0' else '1';
SIG_LABEL : postponed with z select
a <= b when z = "000",
c when z = "001";
end architecture RTL;
| gpl-3.0 | 9c5344a6b2c7513633f19ba0bd3aa716 | 0.521898 | 3.341463 | false | false | false | false |
Yarr/Yarr-fw | rtl/kintex7/wbexp-core/p2l_decoder.vhd | 1 | 14,172 | ----------------------------------------------------------------------------------
-- Company: LBNL
-- Engineer: Arnaud Sautaux
-- E-Mail: [email protected]
--
-- Project: YARR
-- Module: P2L Packet decoder
-- Description: Decodes PCIe packet coming from an AXI-stream bus
----------------------------------------------------------------------------------
-- Changelog:
-- 17.02.2017 - Module sperated from the Wishbone Master
-- 06.06.2017 - Last update by Arnaud
----------------------------------------------------------------------------------
library IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
use work.wshexp_core_pkg.all;
entity p2l_decoder is
Port (
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
-- From Slave AXI-Stream
s_axis_rx_tdata_i : in STD_LOGIC_VECTOR (64 - 1 downto 0);
s_axis_rx_tkeep_i : in STD_LOGIC_VECTOR (64/8 - 1 downto 0);
s_axis_rx_tuser_i : in STD_LOGIC_VECTOR (21 downto 0);
s_axis_rx_tlast_i : in STD_LOGIC;
s_axis_rx_tvalid_i : in STD_LOGIC;
s_axis_rx_tready_o : out STD_LOGIC;
-- To the wishbone master
pd_wbm_address_o : out STD_LOGIC_VECTOR(63 downto 0);
pd_wbm_data_o : out STD_LOGIC_VECTOR(31 downto 0);
pd_wbm_valid_o : out std_logic;
pd_wbm_hdr_rid_o : out std_logic_vector(15 downto 0); -- Requester ID
pd_wbm_hdr_tag_o : out std_logic_vector(7 downto 0);
pd_wbm_target_mrd_o : out std_logic; -- Target memory read
pd_wbm_target_mwr_o : out std_logic; -- Target memory write
wbm_pd_ready_i : in std_logic;
-- to L2P DMA
pd_pdm_data_valid_o : out std_logic; -- Indicates Data is valid
pd_pdm_data_valid_w_o : out std_logic_vector(1 downto 0);
pd_pdm_data_last_o : out std_logic; -- Indicates end of the packet
pd_pdm_keep_o : out std_logic_vector(7 downto 0);
pd_pdm_data_o : out std_logic_vector(63 downto 0); -- Data
--debug outputs
states_do : out STD_LOGIC_VECTOR(3 downto 0);
pd_op_o : out STD_LOGIC_VECTOR(2 downto 0);
pd_header_type_o : out STD_LOGIC;
pd_payload_length_o : out STD_LOGIC_VECTOR(9 downto 0)
);
end p2l_decoder;
architecture Behavioral of p2l_decoder is
constant axis_data_width_c : integer := 64;
constant address_mask_c : STD_LOGIC_VECTOR(64-1 downto 0) := X"00000000" & X"000FFFFF"; -- depends on pcie memory size
constant fmt_h3dw_nodata_c : STD_LOGIC_VECTOR (3 - 1 downto 0):= "000";
constant fmt_h3dw_data_c : STD_LOGIC_VECTOR (3 - 1 downto 0):= "001";
constant fmt_h4dw_nodata_c : STD_LOGIC_VECTOR (3 - 1 downto 0):= "010";
constant fmt_h4dw_data_c : STD_LOGIC_VECTOR (3 - 1 downto 0):= "011";
constant fmt_tlp_prefix_c : STD_LOGIC_VECTOR (3 - 1 downto 0):= "100";
constant tlp_type_Mr_c : STD_LOGIC_VECTOR (5 - 1 downto 0):= "00000";
constant tlp_type_Cpl_c : STD_LOGIC_VECTOR (5 - 1 downto 0):= "01010";
type state_t is (idle,hd0_rx, hd1_rx, lastdata_rx, data_rx);
signal state_s : state_t;
signal previous_state_s : state_t;
signal payload_length_s : STD_LOGIC_VECTOR(9 downto 0);
signal bar_hit_s : STD_LOGIC_VECTOR(6 downto 0);
type tlp_type_t is (MRd,MRdLk,MWr,IORd,IOWr,CfgRd0,CfgWr0,CfgRd1,CfgWr1,TCfgRd,TCfgWr,Msg,MsgD,Cpl,CplD,CplLk,CplDLk,LPrfx,unknown);
signal tlp_type_s : tlp_type_t;
type header_t is (H3DW,H4DW);
signal header_type_s : header_t;
type bool_t is (false,true);
signal payload_s : bool_t;
signal tlp_prefix : bool_t;
signal address_s : STD_LOGIC_VECTOR(64-1 downto 0);
signal data_s : STD_LOGIC_VECTOR(32-1 downto 0);
signal s_axis_rx_tdata_s : STD_LOGIC_VECTOR (axis_data_width_c - 1 downto 0);
signal s_axis_rx_tkeep_s : STD_LOGIC_VECTOR (axis_data_width_c/8 - 1 downto 0);
signal s_axis_rx_tkeep_1_s : STD_LOGIC_VECTOR (axis_data_width_c/8 - 1 downto 0);
signal s_axis_rx_tuser_s : STD_LOGIC_VECTOR (21 downto 0);
signal s_axis_rx_tvalid_s : STD_LOGIC;
signal s_axis_rx_tlast_s : STD_LOGIC;
signal s_axis_rx_tready_s : STD_LOGIC;
signal s_axis_rx_tlast_1_s : STD_LOGIC;
signal s_axis_rx_tdata_0_s : STD_LOGIC_VECTOR (axis_data_width_c - 1 downto 0);
signal s_axis_rx_tdata_1_s : STD_LOGIC_VECTOR (axis_data_width_c - 1 downto 0);
signal pd_pdm_keep_0_s : std_logic_vector(7 downto 0);
signal pd_pdm_keep_1_s : std_logic_vector(7 downto 0);
signal pd_op_s : STD_LOGIC_VECTOR(2 downto 0);
signal pd_wbm_hdr_rid_s : std_logic_vector(15 downto 0); -- Requester ID
--signal pd_wbm_hdr_cid_s : std_logic_vector(15 downto 0); -- Completer ID
signal pd_wbm_hdr_tag_s : std_logic_vector(7 downto 0);
signal pd_wbm_target_mrd_s : std_logic; -- Target memory read
signal pd_wbm_target_mwr_s : std_logic;
signal data_cnt_s : unsigned(9 downto 0);
signal byte_swap_c : STD_LOGIC_VECTOR (1 downto 0);
begin
byte_swap_c <= "11";
state_p:process(rst_i,clk_i)
begin
if rst_i = '1' then
--if s_axis_rx_tvalid_i = '1' then
state_s <= idle;
--end if;
elsif clk_i = '1' and clk_i'event then
case state_s is
when idle =>
state_s <= hd0_rx;
when hd0_rx =>
if s_axis_rx_tvalid_s = '1' then
state_s <= hd1_rx; --
end if;
when hd1_rx =>
if s_axis_rx_tvalid_s = '1' then
if s_axis_rx_tvalid_i = '1' and s_axis_rx_tlast_i = '1' and s_axis_rx_tvalid_i = '1' then
state_s <= lastdata_rx;
elsif s_axis_rx_tlast_s = '0' then
state_s <= data_rx;
elsif s_axis_rx_tlast_s = '1' then
state_s <= hd0_rx;
end if;
end if;
when lastdata_rx =>
state_s <= hd0_rx;
when data_rx =>
if s_axis_rx_tlast_i = '1' and s_axis_rx_tvalid_i = '1' then
state_s <= lastdata_rx;
end if;
end case;
end if;
end process state_p;
delay_p: process(clk_i,rst_i)
begin
if rst_i = '1' then
s_axis_rx_tdata_s <= (others => '0');
s_axis_rx_tkeep_s <= (others => '0');
s_axis_rx_tuser_s <= (others => '0');
s_axis_rx_tvalid_s <= '0';
s_axis_rx_tlast_s <= '0';
previous_state_s <= hd1_rx;
elsif clk_i = '1' and clk_i'event then
s_axis_rx_tdata_s <= s_axis_rx_tdata_i;
s_axis_rx_tkeep_s <= s_axis_rx_tkeep_i;
s_axis_rx_tkeep_1_s <= s_axis_rx_tkeep_s;
s_axis_rx_tuser_s <= s_axis_rx_tuser_i;
s_axis_rx_tvalid_s <= s_axis_rx_tvalid_i;
s_axis_rx_tlast_s <= s_axis_rx_tlast_i and s_axis_rx_tvalid_i;
s_axis_rx_tlast_1_s <= s_axis_rx_tlast_s;
previous_state_s <= state_s;
end if;
end process delay_p;
data_counter_p : process(clk_i,rst_i)
begin
if rst_i = '1' then
data_cnt_s <= (others => '0');
elsif clk_i = '1' and clk_i'event then
case state_s is
when hd0_rx =>
data_cnt_s <= unsigned(s_axis_rx_tdata_s(9 downto 0));
when hd1_rx =>
data_cnt_s <= data_cnt_s - 1;
when data_rx =>
if s_axis_rx_tvalid_s = '1' then
data_cnt_s <= data_cnt_s - 2;
end if;
when lastdata_rx =>
if s_axis_rx_tvalid_s = '1' then
if s_axis_rx_tkeep_s = X"0F" then
data_cnt_s <= data_cnt_s - 1;
elsif s_axis_rx_tkeep_s = X"FF" then
data_cnt_s <= data_cnt_s - 2;
end if;
end if;
when others =>
end case;
end if;
end process data_counter_p;
reg_p: process(rst_i,clk_i)
begin
if rst_i = '1' then
address_s <= (others => '0');
tlp_type_s <= unknown;
header_type_s <= H4DW;
data_s <= (others => '0');
pd_wbm_hdr_rid_s <= (others => '0');
pd_wbm_hdr_tag_s <= (others => '0');
pd_wbm_target_mrd_s <= '0';
pd_wbm_target_mwr_s <= '0';
elsif clk_i = '1' and clk_i'event then
case state_s is
when idle =>
address_s <= (others => '0');
tlp_type_s <= unknown;
header_type_s <= H4DW;
data_s <= (others => '0');
pd_wbm_hdr_rid_s <= (others => '0');
pd_wbm_hdr_tag_s <= (others => '0');
pd_wbm_target_mrd_s <= '0';
pd_wbm_target_mwr_s <= '0';
when hd0_rx =>
bar_hit_s <= s_axis_rx_tuser_s(8 downto 2);
payload_length_s <= s_axis_rx_tdata_s(9 downto 0);
pd_wbm_hdr_rid_s <= s_axis_rx_tdata_s(63 downto 48);
pd_wbm_target_mrd_s <= '0';
pd_wbm_target_mwr_s <= '0';
case s_axis_rx_tdata_s(31 downto 24) is
when "00000000" =>
tlp_type_s <= MRd;
header_type_s <= H3DW;
pd_wbm_target_mrd_s <= '1';
when "00100000" =>
tlp_type_s <= MRd;
header_type_s <= H4DW;
when "00000001" =>
tlp_type_s <= MRdLk;
header_type_s <= H3DW;
when "00100001" =>
tlp_type_s <= MRdLk;
header_type_s <= H4DW;
when "01000000" =>
tlp_type_s <= MWr;
header_type_s <= H3DW;
pd_wbm_target_mwr_s <= '1';
when "01100000" =>
tlp_type_s <= MWr;
header_type_s <= H4DW;
when "00000010" =>
tlp_type_s <= IORd;
header_type_s <= H3DW;
when "01000010" =>
tlp_type_s <= IOWr;
header_type_s <= H3DW;
when "00000100" =>
tlp_type_s <= CfgRd0;
header_type_s <= H3DW;
when "01000100" =>
tlp_type_s <= CfgWr0;
header_type_s <= H3DW;
when "00000101" =>
tlp_type_s <= CfgRd1;
header_type_s <= H3DW;
when "01000101" =>
tlp_type_s <= CfgWr1;
header_type_s <= H3DW;
when "00011011" =>
tlp_type_s <= TCfgRd;
header_type_s <= H3DW;
when "01011011" =>
tlp_type_s <= TCfgWr;
header_type_s <= H3DW;
when "00001010" =>
tlp_type_s <= Cpl;
header_type_s <= H3DW;
when "01001010" =>
tlp_type_s <= CplD;
header_type_s <= H3DW;
when "00001011" =>
tlp_type_s <= CplLk;
header_type_s <= H3DW;
when "01001011" =>
tlp_type_s <= CplDLk;
header_type_s <= H3DW;
when others =>
if s_axis_rx_tdata_s(31 downto 27) = "00110" then
tlp_type_s <= Msg;
header_type_s <= H4DW;
elsif s_axis_rx_tdata_s(31 downto 27) = "01110" then
tlp_type_s <= MsgD;
header_type_s <= H4DW;
elsif s_axis_rx_tdata_s(31 downto 28) = "1000" then
tlp_type_s <= LPrfx;
header_type_s <= H3DW;
else
tlp_type_s <= unknown;
header_type_s <= H4DW;
end if;
end case;
when hd1_rx =>
if header_type_s = H3DW then -- d0h2_rx
address_s <= X"00000000" & s_axis_rx_tdata_s(31 downto 0) and address_mask_c; -- see 2.2.4.1. in pcie spec
address_s(1 downto 0) <= "00";
data_s <= s_axis_rx_tdata_s(63 downto 32);
else -- H4DW h3h2_rx
address_s(63 downto 32) <= s_axis_rx_tdata_s(31 downto 0) and address_mask_c(63 downto 32);
address_s(31 downto 0) <= s_axis_rx_tdata_s(63 downto 36) & "0000" and address_mask_c(31 downto 0);
end if;
when data_rx =>
when lastdata_rx =>
when others =>
end case;
end if;
end process reg_p;
pd_header_type_o <= '1' when header_type_s = H4DW else '0';
pd_wbm_hdr_rid_o <= pd_wbm_hdr_rid_s;
pd_wbm_hdr_tag_o <= pd_wbm_hdr_tag_s;
pd_wbm_target_mrd_o <= pd_wbm_target_mrd_s;
pd_wbm_target_mwr_o <= pd_wbm_target_mwr_s;
p2l_data_delay_p : process(clk_i)
begin
if (clk_i'event and clk_i = '1') then
s_axis_rx_tdata_0_s <= s_axis_rx_tdata_i;
s_axis_rx_tdata_1_s <= s_axis_rx_tdata_0_s;
pd_pdm_keep_0_s <= s_axis_rx_tkeep_i;
pd_pdm_keep_1_s <= pd_pdm_keep_0_s;
end if;
end process p2l_data_delay_p;
pd_pdm_data_o <=
f_byte_swap(true,data_s, byte_swap_c) & f_byte_swap(true,data_s, byte_swap_c) when payload_length_s = "0000000001" else
f_byte_swap(true, s_axis_rx_tdata_0_s(31 downto 0), byte_swap_c) & f_byte_swap(true, s_axis_rx_tdata_1_s(63 downto 32), byte_swap_c);
pd_pdm_data_valid_o <= s_axis_rx_tvalid_s when (state_s = data_rx or state_s = lastdata_rx) and pd_op_s = "011"
else '0';
pd_pdm_data_last_o <=
s_axis_rx_tlast_s when ( state_s = lastdata_rx and s_axis_rx_tkeep_i = X"0F" and pd_op_s = "011") else
'1' when s_axis_rx_tkeep_1_s = X"FF" and s_axis_rx_tlast_1_s = '1'and pd_op_s = "011" else
'0';
pd_pdm_data_valid_w_o(1) <=
s_axis_rx_tvalid_s when (state_s = data_rx or state_s = lastdata_rx) and pd_op_s = "011" and pd_pdm_keep_0_s(3 downto 0) = X"F" else
'0';
pd_pdm_data_valid_w_o(0) <=
s_axis_rx_tvalid_s when (state_s = data_rx or state_s = lastdata_rx) and pd_op_s = "011" and pd_pdm_keep_1_s(7 downto 4) = X"F" else
'1' when pd_op_s = "011" and s_axis_rx_tlast_s = '1' and state_s = hd0_rx else
'1' when s_axis_rx_tkeep_1_s = X"FF" and s_axis_rx_tlast_1_s = '1'and pd_op_s = "011" else
'0';
pd_pdm_keep_o <= pd_pdm_keep_0_s(3 downto 0) & pd_pdm_keep_1_s(7 downto 4);
pd_wbm_valid_o <= '1' when previous_state_s = hd1_rx and s_axis_rx_tlast_1_s = '1' and (pd_op_s = "001" or pd_op_s = "010") else '0';
s_axis_rx_tready_s <= wbm_pd_ready_i;
s_axis_rx_tready_o <= s_axis_rx_tready_s;
pd_payload_length_o <= payload_length_s;
pd_wbm_address_o <= address_s;
pd_wbm_data_o <= f_byte_swap(true,data_s, byte_swap_c);
pd_op_o <= pd_op_s;
debug_output_p:process (state_s,header_type_s,tlp_type_s)
begin
case tlp_type_s is
when MRd =>
pd_op_s <= "001";
when MWr =>
pd_op_s <= "010";
when CplD =>
pd_op_s <= "011";
when others =>
pd_op_s <= "000";
end case;
case state_s is
when idle =>
states_do <= "0000";
when hd0_rx =>
states_do <= "0001";
when hd1_rx =>
states_do <= "0010";
when data_rx =>
states_do <= "0011";
when lastdata_rx =>
states_do <= "0100";
end case;
end process debug_output_p;
end;
| gpl-3.0 | 28f25ec2d0d0f4da1e6d13a0f4821a66 | 0.548335 | 2.624444 | false | false | false | false |
Yarr/Yarr-fw | rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/sim/cmd_gen.vhd | 20 | 39,433 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: cmd_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:27 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module genreates different type of commands, address,
-- burst_length to mcb_flow_control module.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY cmd_gen IS
GENERIC (
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
TCQ : TIME := 100 ps;
PORT_MODE : STRING := "BI_MODE";
NUM_DQ_PINS : INTEGER := 8;
DATA_PATTERN : STRING := "DGEN_ALL";
CMD_PATTERN : STRING := "CGEN_ALL";
ADDR_WIDTH : INTEGER := 30;
DWIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 0;
MEM_COL_WIDTH : INTEGER := 10;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
run_traffic_i : IN STD_LOGIC;
rd_buff_avail_i : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
force_wrcmd_gen_i : IN STD_LOGIC;
start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_i : IN STD_LOGIC;
addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mode_load_i : IN STD_LOGIC;
fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bram_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
bram_valid_i : IN STD_LOGIC;
bram_rdy_o : OUT STD_LOGIC;
reading_rd_data_i : IN STD_LOGIC;
rdy_i : IN STD_LOGIC;
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-- m_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_o_vld : OUT STD_LOGIC
);
END cmd_gen;
ARCHITECTURE trans OF cmd_gen IS
constant PRBS_ADDR_WIDTH : INTEGER := 32;
constant INSTR_PRBS_WIDTH : INTEGER := 16;
constant BL_PRBS_WIDTH : INTEGER := 16;
constant BRAM_DATAL_MODE : std_logic_vector(3 downto 0) := "0000";
constant FIXED_DATA_MODE : std_logic_vector(3 downto 0) := "0001";
constant ADDR_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant HAMMER_DATA_MODE : std_logic_vector(3 downto 0) := "0011";
constant NEIGHBOR_DATA_MODE : std_logic_vector(3 downto 0) := "0100";
constant WALKING1_DATA_MODE : std_logic_vector(3 downto 0) := "0101";
constant WALKING0_DATA_MODE : std_logic_vector(3 downto 0) := "0110";
constant PRBS_DATA_MODE : std_logic_vector(3 downto 0) := "0111";
COMPONENT pipeline_inserter IS
GENERIC (
DATA_WIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 1
);
PORT (
data_i : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
clk_i : IN STD_LOGIC;
en_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cmd_prbs_gen IS
GENERIC (
TCQ : time := 100 ps;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 29;
DWIDTH : INTEGER := 32;
PRBS_CMD : STRING := "ADDRESS";
PRBS_WIDTH : INTEGER := 64;
SEED_WIDTH : INTEGER := 32;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
prbs_seed_init : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
);
END COMPONENT;
function BOOLEAN_TO_STD_LOGIC(A : in BOOLEAN) return std_logic is
begin
if A = true then
return '1';
else
return '0';
end if;
end function BOOLEAN_TO_STD_LOGIC;
SIGNAL INC_COUNTS : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL addr_mode_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bl_mode_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL addr_counts : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL prbs_bl : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL instr_out : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL prbs_instr_a : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_instr_b : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_brlen : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL prbs_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL seq_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL fixed_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bl_out : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL bl_out_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_d1 : STD_LOGIC;
SIGNAL mode_load_d2 : STD_LOGIC;
SIGNAL mode_load_pulse : STD_LOGIC;
SIGNAL pipe_data_o : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL cmd_clk_en : STD_LOGIC;
SIGNAL pipe_out_vld : STD_LOGIC;
SIGNAL end_addr_range : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL force_bl1 : STD_LOGIC;
SIGNAL A0_G_E0 : STD_LOGIC;
SIGNAL A1_G_E1 : STD_LOGIC;
SIGNAL A2_G_E2 : STD_LOGIC;
SIGNAL A3_G_E3 : STD_LOGIC;
SIGNAL AC3_G_E3 : STD_LOGIC;
SIGNAL AC2_G_E2 : STD_LOGIC;
SIGNAL AC1_G_E1 : STD_LOGIC;
SIGNAL bl_out_clk_en : STD_LOGIC;
SIGNAL pipe_data_in : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL instr_vld : STD_LOGIC;
SIGNAL bl_out_vld : STD_LOGIC;
SIGNAL cmd_vld : STD_LOGIC;
SIGNAL run_traffic_r : STD_LOGIC;
SIGNAL run_traffic_pulse : STD_LOGIC;
SIGNAL pipe_data_in_vld : STD_LOGIC;
SIGNAL gen_addr_larger : STD_LOGIC;
SIGNAL buf_avail_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_counts_asked : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts_total : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL instr_vld_dly1 : STD_LOGIC;
SIGNAL first_load_pulse : STD_LOGIC;
SIGNAL mem_init_done : STD_LOGIC;
SIGNAL i : INTEGER;
SIGNAL force_wrcmd_gen : STD_LOGIC;
SIGNAL force_smallvalue : STD_LOGIC;
SIGNAL end_addr_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL force_rd_counts : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL force_rd : STD_LOGIC;
SIGNAL addr_counts_next_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL refresh_cmd_en : STD_LOGIC;
SIGNAL refresh_timer : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL refresh_prbs : STD_LOGIC;
SIGNAL cmd_clk_en_r : STD_LOGIC;
signal instr_mode_reg : std_logic_vector(3 downto 0);
-- X-HDL generated signals
SIGNAL xhdl4 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL xhdl12 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL xhdl14 : STD_LOGIC_VECTOR(5 DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL bl_o_xhdl0 : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_pulse_r1 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
bl_o <= bl_o_xhdl0;
addr_o <= pipe_data_o(31 DOWNTO 0);
instr_o <= pipe_data_o(34 DOWNTO 32);
bl_o_xhdl0 <= pipe_data_o(40 DOWNTO 35);
cmd_o_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_out_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_data_o <= pipe_data_in;
cv1 : IF (CMD_PATTERN = "CGEN_BRAM") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en;
END IF;
END PROCESS;
END GENERATE;
cv3 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL" OR CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_FIXED") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse);
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
run_traffic_r <= run_traffic_i ;
IF ( run_traffic_i= '1' AND run_traffic_r = '0' ) THEN
run_traffic_pulse <= '1' ;
ELSE
run_traffic_pulse <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_clk_en <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_vld <= bl_out_clk_en ;
pipe_data_in_vld <= instr_vld ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
first_load_pulse <= '1' ;
ELSIF (mode_load_pulse = '1') THEN
first_load_pulse <= '0' ;
ELSE
first_load_pulse <= first_load_pulse ;
END IF;
END IF;
END PROCESS;
cmd_clk_en <= (rdy_i AND pipe_out_vld AND run_traffic_i) OR (mode_load_pulse AND BOOLEAN_TO_STD_LOGIC(CMD_PATTERN = "CGEN_BRAM"));
pipe_in_s6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(0)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 9) & "000000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 10) & "0000000000") ;
END IF;
ELSE
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSIF (DWIDTH = 128) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
pipe_in_v6 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(1)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS <= 144)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 7) & "0000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
END IF;
ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 24)) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000");
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
END IF;
ELSIF (NUM_DQ_PINS = 8) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- pipe_m_addr_o : IF (FAMILY = "VIRTEX6") GENERATE
-- PROCESS (clk_i)
-- BEGIN
-- IF (clk_i'EVENT AND clk_i = '1') THEN
-- IF ((rst_i(1)) = '1') THEN
-- m_addr_o(31 DOWNTO 0) <= start_addr_i ;
-- ELSIF (instr_vld = '1') THEN
-- IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
-- m_addr_o(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS < 256)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 6) & "000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 5) & "00000") ;
-- ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
-- ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 17)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
-- ELSIF ((NUM_DQ_PINS = 8) OR (NUM_DQ_PINS = 9)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
--
-- END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
force_wrcmd_gen <= '0' ;
ELSIF (buf_avail_r = "0111111") THEN
force_wrcmd_gen <= '0' ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1' AND pipe_data_in(41 DOWNTO 35) > "0010000") THEN
force_wrcmd_gen <= '1' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_mode_reg <= instr_mode_i ;
END IF;
END PROCESS;
-- **********************************************
PROCESS (clk_i) BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(40 DOWNTO 32) <= "000000000";
force_smallvalue <= '0';
ELSIF (instr_vld = '1') THEN
IF (instr_mode_reg = 0) THEN
pipe_data_in(34 DOWNTO 32) <= instr_out ;
ELSIF (instr_out(2) = '1') THEN
pipe_data_in(34 DOWNTO 32) <= "100" ;
ELSIF (FAMILY = "SPARTAN6" AND PORT_MODE = "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2 downto 1) & '1' ;
ELSIF ((force_wrcmd_gen = '1' OR buf_avail_r <= "0001111") AND FAMILY = "SPARTAN6" AND PORT_MODE /= "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2) & "00";
ELSE
pipe_data_in(34 DOWNTO 32) <= instr_out;
END IF;
----********* condition the generated bl value except if TG is programmed for BRAM interface'
---- if the generated address is close to end address range, the bl_out will be altered to 1.
--
IF (bl_mode_i = 0) THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF ( FAMILY = "VIRTEX6") THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF (force_bl1 = '1' AND (bl_mode_reg = "10") AND FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= "000001" ;
-- **********************************************
ELSIF (buf_avail_r(5 DOWNTO 0) >= "111100" AND buf_avail_r(6) = '0' AND pipe_data_in(32) = '1' AND FAMILY = "SPARTAN6") THEN
IF (bl_mode_reg = "10") THEN
force_smallvalue <= NOT(force_smallvalue) ;
END IF;
IF (buf_avail_r(6) = '1' AND bl_mode_reg = "10") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 1) & '1') ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
ELSIF (buf_avail_r < "1000000" AND rd_buff_avail_i >= "0000000" AND instr_out(0) = '1' AND (bl_mode_reg = "10")) THEN
IF (FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 0)) + '1' ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
END IF; --IF (bl_mode_i = 0) THEN
END IF; --IF ((rst_i(2)) = '1') THEN
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(41) <= '0' ;
ELSIF (cmd_vld = '1') THEN
pipe_data_in(41) <= instr_vld ;
ELSIF ((rdy_i AND pipe_out_vld) = '1') THEN
pipe_data_in(41) <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld_dly1 <= instr_vld;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_counts_asked <= (others => '0') ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1') THEN
IF (pipe_data_in(40 DOWNTO 35) = "000000") THEN
rd_data_counts_asked <= rd_data_counts_asked + 64 ;
ELSE
rd_data_counts_asked <= rd_data_counts_asked + ('0' & (pipe_data_in(40 DOWNTO 35)));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_received_counts <= (others => '0');
rd_data_received_counts_total <= (others => '0');
ELSIF (reading_rd_data_i = '1') THEN
rd_data_received_counts <= rd_data_received_counts + '1';
rd_data_received_counts_total <= rd_data_received_counts_total + "0000000000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
buf_avail_r <= (rd_data_received_counts + 64) - rd_data_counts_asked;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
IF (CMD_PATTERN = "CGEN_BRAM") THEN
addr_mode_reg <= "000";
ELSE
addr_mode_reg <= "011";
END IF;
ELSIF (mode_load_pulse = '1') THEN
addr_mode_reg <= addr_mode_i;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_mode_reg <= bl_mode_i;
END IF;
mode_load_d1 <= mode_load_i;
mode_load_d2 <= mode_load_d1;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse <= mode_load_d1 AND NOT(mode_load_d2);
END IF;
END PROCESS;
xhdl4 <= addr_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
addr_out <= start_addr_i;
ELSE
CASE xhdl4 IS
WHEN "000" =>
addr_out <= bram_addr_i;
WHEN "001" =>
addr_out <= fixed_addr;
WHEN "010" =>
addr_out <= prbs_addr;
WHEN "011" =>
addr_out <= ("00" & seq_addr(29 DOWNTO 0));
WHEN "100" =>
-- addr_out <= (prbs_addr(31 DOWNTO 6) & "000000");
addr_out <= ("000" & seq_addr(6 DOWNTO 2) & seq_addr(23 DOWNTO 0));--(prbs_addr(31 DOWNTO 6) & "000000");
WHEN "101" =>
addr_out <= (prbs_addr(31 DOWNTO 20) & seq_addr(19 DOWNTO 0));
-- addr_out <= (prbs_addr(31 DOWNTO MEM_COL_WIDTH) & seq_addr(MEM_COL_WIDTH - 1 DOWNTO 0));
WHEN OTHERS =>
addr_out <= (others => '0');--"00000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
xhdl5 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
addr_prbs_gen : cmd_prbs_gen
GENERIC MAP (
family => FAMILY,
addr_width => 32,
dwidth => DWIDTH,
prbs_width => 32,
seed_width => 32,
prbs_eaddr_mask_pos => PRBS_EADDR_MASK_POS,
prbs_saddr_mask_pos => PRBS_SADDR_MASK_POS,
prbs_eaddr => PRBS_EADDR,
prbs_saddr => PRBS_SADDR
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => mode_load_pulse,
prbs_seed_i => cmd_seed_i(31 DOWNTO 0),
prbs_o => prbs_addr
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 8) >= end_addr_i(31 DOWNTO 8)) THEN
gen_addr_larger <= '1';
ELSE
gen_addr_larger <= '0';
END IF;
END IF;
END PROCESS;
xhdl6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mem_init_done = '1') THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),11));
ELSE
IF (fixed_bl_i = "000000") THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8)*(64), 11));
ELSE
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(fixed_bl_i))),11));
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
xhdl7 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (NUM_DQ_PINS >= 128 AND NUM_DQ_PINS <= 144) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(64 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 64 AND NUM_DQ_PINS < 128) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(32 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 32 AND NUM_DQ_PINS < 64) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(16 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 16 OR NUM_DQ_PINS = 24) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(8 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 8 OR NUM_DQ_PINS = 9) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(4 * (MEM_BURST_LEN/4), 11));
END IF;
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_r <= end_addr_i - std_logic_vector(to_unsigned(DWIDTH/8*to_integer(unsigned(fixed_bl_i)),32)) + "00000000000000000000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_r(31 DOWNTO 24)) THEN
AC3_G_E3 <= '1';
ELSE
AC3_G_E3 <= '0';
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_r(23 DOWNTO 16)) THEN
AC2_G_E2 <= '1';
ELSE
AC2_G_E2 <= '0';
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_r(15 DOWNTO 8)) THEN
AC1_G_E1 <= '1';
ELSE
AC1_G_E1 <= '0';
END IF;
END IF;
END PROCESS;
-- xhdl8 : IF (CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_ALL") GENERATE
seq_addr <= addr_counts;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse_r1 <= mode_load_pulse;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_range <= end_addr_i(15 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),16)) + "0000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
addr_counts_next_r <= addr_counts + (INC_COUNTS);
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_clk_en_r <= cmd_clk_en;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
addr_counts <= start_addr_i;
mem_init_done <= '0';
ELSIF ((cmd_clk_en_r OR mode_load_pulse_r1) = '1') THEN
-- IF ((DWIDTH = 32 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR (DWIDTH = 64 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR ((DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND FAMILY = "SPARTAN6") OR (DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6") OR (DWIDTH >= 256 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6"))) THEN
IF (addr_counts_next_r >= end_addr_i) THEN
addr_counts <= start_addr_i;
mem_init_done <= '1';
ELSIF (addr_counts < end_addr_r) THEN
addr_counts <= addr_counts + INC_COUNTS;
END IF;
END IF;
END IF;
END PROCESS;
--END GENERATE;
xhdl9 : IF (CMD_PATTERN = "CGEN_FIXED" OR CMD_PATTERN = "CGEN_ALL") GENERATE
fixed_addr <= (fixed_addr_i(31 DOWNTO 2) & "00") WHEN (DWIDTH = 32) ELSE
(fixed_addr_i(31 DOWNTO 3) & "000") WHEN (DWIDTH = 64) ELSE
(fixed_addr_i(31 DOWNTO 4) & "0000") WHEN (DWIDTH = 128) ELSE
(fixed_addr_i(31 DOWNTO 5) & "00000") WHEN (DWIDTH = 256) ELSE
(fixed_addr_i(31 DOWNTO 6) & "000000");
END GENERATE;
xhdl10 : IF (CMD_PATTERN = "CGEN_BRAM" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bram_rdy_o <= (run_traffic_i AND cmd_clk_en AND bram_valid_i) OR (mode_load_pulse);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd_counts <= (others => '0');--"0000000000";
ELSIF (instr_vld = '1') THEN
force_rd_counts <= force_rd_counts + "0000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd <= '0';
ELSIF ((force_rd_counts(3)) = '1') THEN
force_rd <= '1';
ELSE
force_rd <= '0';
END IF;
END IF;
END PROCESS;
-- adding refresh timer to limit the amount of issuing refresh command.
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_timer <= (others => '0');
ELSE
refresh_timer <= refresh_timer + 1;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_cmd_en <= '0';
ELSIF (refresh_timer = "1111111111") THEN
refresh_cmd_en <= '1';
ELSIF ((cmd_clk_en and refresh_cmd_en) = '1') THEN
refresh_cmd_en <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (FAMILY = "SPARTAN6") THEN
refresh_prbs <= prbs_instr_b(3) and refresh_cmd_en;
ELSE
refresh_prbs <= '0';
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (instr_mode_i)
BEGIN
IF ((instr_mode_i > "0010") and (FAMILY = "VIRTEX6")) THEN
report "Error ! Not valid instruction mode";
END IF;
END PROCESS;
--synthesis translate_on
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
CASE instr_mode_i IS
WHEN "0000" =>
instr_out <= bram_instr_i;
WHEN "0001" =>
instr_out <= fixed_instr_i;
WHEN "0010" =>
instr_out <= ("00" & (prbs_instr_a(0) OR force_rd));
WHEN "0011" =>
instr_out <= ("00" & prbs_instr_a(0));
WHEN "0100" =>
instr_out <= ('0' & prbs_instr_b(0) & prbs_instr_a(0));
WHEN "0101" =>
instr_out <= (refresh_prbs & prbs_instr_b(0) & prbs_instr_a(0));
WHEN OTHERS =>
instr_out <= ("00" & prbs_instr_a(0));
END CASE;
END IF;
END PROCESS;
xhdl11 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
instr_prbs_gen_a : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(14 DOWNTO 0),
prbs_o => prbs_instr_a
);
instr_prbs_gen_b : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_instr_b
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_i(31 DOWNTO 24)) THEN
A3_G_E3 <= '1' ;
ELSE
A3_G_E3 <= '0' ;
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_i(23 DOWNTO 16)) THEN
A2_G_E2 <= '1' ;
ELSE
A2_G_E2 <= '0' ;
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_i(15 DOWNTO 8)) THEN
A1_G_E1 <= '1' ;
ELSE
A1_G_E1 <= '0' ;
END IF;
IF (addr_out(7 DOWNTO 0) > (end_addr_i(7 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) + '1') ) THEN -- OK
A0_G_E0 <= '1' ;
ELSE
A0_G_E0 <= '0' ;
END IF;
END IF;
END PROCESS;
--testout <= std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),testout'length)) + '1';
PROCESS (addr_out,buf_avail_r, bl_out, end_addr_i, rst_i)
BEGIN
IF ((rst_i(5)) = '1') THEN
force_bl1 <= '0';
ELSIF (addr_out + std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) >= end_addr_i) OR
(buf_avail_r <= 50 and PORT_MODE = "RD_MODE") THEN
force_bl1 <= '1' ;
ELSE
force_bl1 <= '0' ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(6)) = '1') THEN
bl_out_reg <= fixed_bl_i;
ELSIF (bl_out_vld = '1') THEN
bl_out_reg <= bl_out;
END IF;
END IF;
END PROCESS;
xhdl12 <= bl_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_out <= fixed_bl_i;
ELSIF (cmd_clk_en = '1') THEN
CASE xhdl12 IS
WHEN "00" =>
bl_out <= bram_bl_i;
WHEN "01" =>
bl_out <= fixed_bl_i;
WHEN "10" =>
bl_out <= prbs_brlen;
WHEN OTHERS =>
bl_out <= "000001";
END CASE;
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (bl_out)
BEGIN
IF (bl_out > "000010" AND FAMILY = "VIRTEX6") THEN
report "Error ! Not valid burst length"; --severity ERROR;
END IF;
END PROCESS;
--synthesis translate_on
xhdl13 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bl_prbs_gen : cmd_prbs_gen
GENERIC MAP (
TCQ => TCQ,
family => FAMILY,
prbs_cmd => "BLEN",
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_bl
);
END GENERATE;
-- xhdl14 <= "000001" WHEN (prbs_bl(5 DOWNTO 0) = "000000") ELSE prbs_bl(5 DOWNTO 0);
PROCESS (prbs_bl) BEGIN
IF (FAMILY = "SPARTAN6") THEN
if (prbs_bl(5 DOWNTO 0) = "000000") then
-- prbs_brlen <= xhdl14;
prbs_brlen <= "000001";
else
prbs_brlen <= prbs_bl(5 DOWNTO 0);
end if;
ELSE
prbs_brlen <= "000010";
END IF;
END PROCESS;
END trans;
| gpl-3.0 | 52a68c11fb37417f73b23bfdd358f13e | 0.495803 | 3.449051 | false | false | false | false |
lvd2/zxevo | fpga/sdload/trunk/sim_models/T80a.vhd | 5 | 7,837 | -- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core, asynchronous top level
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0211 : Fixed interrupt cycle
--
-- 0235 : Updated for T80 interface change
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
-- 0247 : Fixed bus req/ack cycle
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80a is
generic(
Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
D : inout std_logic_vector(7 downto 0);
D_I : in std_logic_vector(7 downto 0);
D_O : out std_logic_vector(7 downto 0);
ResetPC : in std_logic_vector(15 downto 0);
ResetSP : in std_logic_vector(15 downto 0)
);
end T80a;
architecture rtl of T80a is
signal CEN : std_logic;
signal Reset_s : std_logic;
signal IntCycle_n : std_logic;
signal IORQ : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal MREQ : std_logic;
signal MReq_Inhibit : std_logic;
signal Req_Inhibit : std_logic;
signal RD : std_logic;
signal MREQ_n_i : std_logic;
signal IORQ_n_i : std_logic;
signal RD_n_i : std_logic;
signal WR_n_i : std_logic;
signal RFSH_n_i : std_logic;
signal BUSAK_n_i : std_logic;
signal A_i : std_logic_vector(15 downto 0);
signal DO : std_logic_vector(7 downto 0);
signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
signal Wait_s : std_logic;
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
CEN <= '1';
BUSAK_n <= BUSAK_n_i;
MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
RD_n_i <= not RD or Req_Inhibit;
MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
D_O <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
Reset_s <= '0';
elsif CLK_n'event and CLK_n = '1' then
Reset_s <= '1';
end if;
end process;
u0 : T80
generic map(
Mode => Mode,
IOWait => 1)
port map(
CEN => CEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n_i,
HALT_n => HALT_n,
WAIT_n => Wait_s,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => Reset_s,
BUSRQ_n => BUSRQ_n, BUSAK_n => BUSAK_n_i,
CLK_n => CLK_n,
A => A_i,
DInst => D_I, -- D -> D_I
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n,
ResetPC => ResetPC,
ResetSP => ResetSP
);
process (CLK_n)
begin
if CLK_n'event and CLK_n = '0' then
Wait_s <= WAIT_n;
if TState = "011" and BUSAK_n_i = '1' then
DI_Reg <= to_x01(D_I); -- D -> D_I
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
WR_n_i <= '1';
elsif CLK_n'event and CLK_n = '1' then
WR_n_i <= '1';
if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!!
WR_n_i <= not Write;
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
Req_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '1' then
if MCycle = "001" and TState = "010" then
Req_Inhibit <= '1';
else
Req_Inhibit <= '0';
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
MReq_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" and TState = "010" then
MReq_Inhibit <= '1';
else
MReq_Inhibit <= '0';
end if;
end if;
end process;
process(Reset_s,CLK_n)
begin
if Reset_s = '0' then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" then
if TState = "001" then
RD <= IntCycle_n;
MREQ <= IntCycle_n;
IORQ_n_i <= IntCycle_n;
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '1';
end if;
if TState = "100" then
MREQ <= '0';
end if;
else
if TState = "001" and NoRead = '0' then
RD <= not Write;
IORQ_n_i <= not IORQ;
MREQ <= not IORQ;
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
end if;
end if;
end if;
end process;
end;
| gpl-3.0 | f956601c1d5fa3d995a56a56bca385a0 | 0.564502 | 3.022368 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/vhdlFile/conditional_force_assignment/classification_test_input.vhd | 1 | 1,338 |
architecture RTL of ENTITY_NAME is
begin
process
begin
SEL_LABEL : some target <= force in some expression when some condition else
some expression when some condition else
some expression;
SEL_LABEL : some target <= force some expression when some condition else
some expression when some condition else
some expression;
SEL_LABEL : some target <= force some expression when some condition else
some expression when some condition;
SEL_LABEL : some target <= force some expression when some condition;
-- Remove the labels
some target <= force in some expression when some condition else
some expression when some condition else
some expression;
some target <= force some expression when some condition else
some expression when some condition else
some expression;
some target <= force some expression when some condition else
some expression when some condition;
some target <= force some expression when some condition;
end process;
end architecture RTL;
| gpl-3.0 | 9eaf88d7d956b590a88d11650473653b | 0.579223 | 6.861538 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/after/rule_003_test_input.vhd | 1 | 759 |
architecture ARCH of ENTITY is
begin
CLK_PROC : process (reset, clk) is
begin
if (reset = '1') then
a <= '0';
b <= '1';
c <= '0';
d <= '1';
elsif (clk'event and clk = '1') then
a <= b after 1 ns;
b <= c after 1 ns;
c <= d after 1 ns;
d <= e after 1 ns;
end if;
end process CLK_PROC;
-- Violations
CLK_PROC : process (reset, clk) is
begin
if (reset = '1') then
a <= '0' after 1 ns;
b <= '1' after 1 ns;
c <= '0';
d <= '1' after 1 ns;
elsif (clk'event and clk = '1') then
a <= b after 1 ns;
b <= c after 1 ns;
c <= d after 1 ns;
d <= e after 1 ns;
end if;
end process CLK_PROC;
end architecture ARCH;
| gpl-3.0 | 3d5233464d2f3ec5ab29793e831b3013 | 0.466403 | 3.189076 | false | false | false | false |
NicoLedwith/Dr.AluOpysel | RAT_MCU/vga_clk_div.vhd | 1 | 805 | --
-- Declares a clock divider to synchronize the VGA scanlines
--
-- Original author: unknown
--
-- Peter Heatwole, Aaron Barton
-- CPE233, Winter 2012, CalPoly
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity vga_clk_div is
port(clk : in std_logic;
clkout : out std_logic);
end vga_clk_div;
architecture Behavioral of vga_clk_div is
signal tmp_clkf : std_logic;
begin
my_div_fast: process (clk,tmp_clkf)
variable div_cnt : integer := 0;
begin
if (rising_edge(clk)) then
if (div_cnt = 1) then
tmp_clkf <= not tmp_clkf;
div_cnt := 0;
else
div_cnt := div_cnt + 1;
end if;
end if;
clkout <= tmp_clkf;
end process my_div_fast;
end Behavioral;
| mit | b4d05c4017766c7701d0e76a027eb39c | 0.565217 | 3.396624 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/if_statement/rule_034_test_input.vhd | 1 | 566 |
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end IF;
end IF;
end process;
end architecture RTL;
| gpl-3.0 | f51052943dc3996c17532442b41341ea | 0.379859 | 3.19774 | false | false | false | false |
okaxaki/vm2413 | LinearTable.vhd | 2 | 2,333 | --
-- LinearTable.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity LinearTable is port (
clk : in std_logic;
reset : in std_logic;
addr : in SIGNED_DB_TYPE;
data : out SIGNED_LI_TYPE
);
end LinearTable;
architecture RTL of LinearTable is
constant TABLE_WIDTH : integer := 2 ** (DB_TYPE'high+1);
type LOG2LIN_TYPE is array (0 to TABLE_WIDTH-1) of LI_TYPE;
constant log2lin_data : LOG2LIN_TYPE := (
"111111111","111101001","111010100","111000000",
"110101101","110011011","110001010","101111001",
"101101001","101011010","101001011","100111101",
"100110000","100100011","100010111","100001011",
"100000000","011110101","011101010","011100000",
"011010111","011001110","011000101","010111101",
"010110101","010101101","010100110","010011111",
"010011000","010010010","010001011","010000110",
"010000000","001111010","001110101","001110000",
"001101011","001100111","001100011","001011110",
"001011010","001010111","001010011","001001111",
"001001100","001001001","001000110","001000011",
"001000000","000111101","000111011","000111000",
"000110110","000110011","000110001","000101111",
"000101101","000101011","000101001","000101000",
"000100110","000100100","000100011","000100001",
"000100000","000011110","000011101","000011100",
"000011011","000011001","000011000","000010111",
"000010110","000010101","000010100","000010100",
"000010011","000010010","000010001","000010000",
"000010000","000001111","000001110","000001110",
"000001101","000001101","000001100","000001011",
"000001011","000001010","000001010","000001010",
"000001001","000001001","000001000","000001000",
"000001000","000000111","000000111","000000111",
"000000110","000000110","000000110","000000101",
"000000101","000000101","000000101","000000101",
"000000100","000000100","000000100","000000100",
"000000100","000000011","000000011","000000011",
"000000011","000000011","000000011","000000011",
"000000010","000000010","000000010","000000010",
"000000010","000000010","000000010","000000000"
);
begin
process (clk)
begin
if clk'event and clk = '1' then
data <= ( sign=>addr.sign, value=>log2lin_data(CONV_INTEGER(addr.value)) );
end if;
end process;
end RTL;
| mit | 1055f6b1a533aa2662472189ee9ab7f8 | 0.684955 | 3.934233 | false | false | false | false |
Jorge9314/ElectronicaDigital | Impresora2D/RS232.vhd | 1 | 1,712 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RS232 is
Port ( clk : in STD_LOGIC;
-- Trasmisor --
Entrada_8bits : in STD_LOGIC_VECTOR (7 downto 0);
Activador_Envio_Mensaje : in STD_LOGIC;
Salida_1bit : out STD_LOGIC := '1';
-- Receptor --
Entrada_1bit : in STD_LOGIC;
Mensaje_8bits : out STD_LOGIC_VECTOR (7 downto 0) := "00000000";
Activador_Entrega_Mensaje : out STD_LOGIC := '0');
end RS232;
architecture arq_RS232 of RS232 is
component Divisor_Frecuencia
Port(
clk : in STD_LOGIC;
Salida : out STD_LOGIC
);
end component;
component Reception_8bits
Port(
Divisor_Frecuencia : in STD_LOGIC;
Entrada : in STD_LOGIC;
Mensaje : out STD_LOGIC_VECTOR (7 downto 0);
Confirmado : out STD_LOGIC
);
end component;
component Transmission_8bits
Port(
Divisor_Frecuencia : in STD_LOGIC;
Entrada : in STD_LOGIC_VECTOR (7 downto 0);
Activo : in STD_LOGIC;
Salida : out STD_LOGIC
);
end component;
signal Divisor_FrecuenciaAUX : std_logic := '1';
begin
Divisor_Frecuencia1 : Divisor_Frecuencia
Port map(
clk => clk,
Salida => Divisor_FrecuenciaAUX
);
Reception_8bits1 : Reception_8bits
Port map(
Divisor_Frecuencia => Divisor_FrecuenciaAUX,
Entrada => Entrada_1bit,
Mensaje => Mensaje_8bits,
Confirmado => Activador_Entrega_Mensaje
);
Transmission_8bits1 : Transmission_8bits
Port map(
Divisor_Frecuencia => Divisor_FrecuenciaAUX,
Entrada => Entrada_8bits,
Activo => Activador_Envio_Mensaje,
Salida => Salida_1bit
);
end arq_RS232;
| gpl-3.0 | 09db7a00b9b34256279d63479ca8f57d | 0.617407 | 3.298651 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/axi_bram_ctrl_top.vhd | 1 | 43,385 | -------------------------------------------------------------------------------
-- axi_bram_ctrl_top.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: axi_bram_ctrl_top.vhd
--
-- Description: This file is the top level module for the AXI BRAM
-- controller IP core.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl_top.vhd (v3_0)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- ecc_gen.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/1/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Remove library version # dependency. Replace with work library.
-- ^^^^^^
-- JLJ 2/9/2011 v1.03a
-- ~~~~~~
-- Update Create_Size_Default function to support 512 & 1024-bit BRAM.
-- Replace usage of Create_Size_Default function.
-- ^^^^^^
-- JLJ 2/15/2011 v1.03a
-- ~~~~~~
-- Initial integration of Hsiao ECC algorithm.
-- Add C_ECC_TYPE top level parameter on full_axi module.
-- Update ECC signal sizes for 128-bit support.
-- ^^^^^^
-- JLJ 2/16/2011 v1.03a
-- ~~~~~~
-- Update WE size based on 128-bit ECC configuration.
-- ^^^^^^
-- JLJ 2/22/2011 v1.03a
-- ~~~~~~
-- Add C_ECC_TYPE top level parameter on axi_lite module.
-- ^^^^^^
-- JLJ 2/23/2011 v1.03a
-- ~~~~~~
-- Set C_ECC_TYPE = 1 for Hsiao DV regressions.
-- ^^^^^^
-- JLJ 2/24/2011 v1.03a
-- ~~~~~~
-- Move Find_ECC_Size function to package.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Add comments as noted in Spyglass runs.
-- ^^^^^^
-- JLJ 5/6/2011 v1.03a
-- ~~~~~~
-- Remove C_FAMILY from top level.
-- Remove C_FAMILY in axi_lite sub module.
-- ^^^^^^
-- JLJ 6/23/2011 v1.03a
-- ~~~~~~
-- Migrate 9-bit ECC to 16-bit ECC for 128-bit BRAM data width.
-- ^^^^^^
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
library work;
use work.axi_lite;
use work.full_axi;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity axi_bram_ctrl_top is
generic (
-- AXI Parameters
C_BRAM_ADDR_WIDTH : integer := 12;
-- Width of AXI address bus (in bits)
C_S_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_S_AXI_ID_WIDTH : INTEGER := 4;
-- AXI ID vector width
C_S_AXI_PROTOCOL : string := "AXI4";
-- Set to AXI4LITE to optimize out burst transaction support
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER := 1;
-- Support for narrow burst operations
C_SINGLE_PORT_BRAM : INTEGER := 0;
-- Enable single port usage of BRAM
-- C_FAMILY : string := "virtex6";
-- Specify the target architecture type
-- AXI-Lite Register Parameters
C_S_AXI_CTRL_ADDR_WIDTH : integer := 32;
-- Width of AXI-Lite address bus (in bits)
C_S_AXI_CTRL_DATA_WIDTH : integer := 32;
-- Width of AXI-Lite data bus (in bits)
-- ECC Parameters
C_ECC : integer := 0;
-- Enables or disables ECC functionality
C_FAULT_INJECT : integer := 0;
-- Enable fault injection registers
-- (default = disabled)
C_ECC_ONOFF_RESET_VALUE : integer := 1
-- By default, ECC checking is on
-- (can disable ECC @ reset by setting this to 0)
-- Reserved parameters for future implementations.
-- C_ENABLE_AXI_CTRL_REG_IF : integer := 1;
-- By default the ECC AXI-Lite register interface is enabled
-- C_CE_FAILING_REGISTERS : integer := 1;
-- Enable CE (correctable error) failing registers
-- C_UE_FAILING_REGISTERS : integer := 1;
-- Enable UE (uncorrectable error) failing registers
-- C_ECC_STATUS_REGISTERS : integer := 1;
-- Enable ECC status registers
-- C_ECC_ONOFF_REGISTER : integer := 1;
-- Enable ECC on/off control register
-- C_CE_COUNTER_WIDTH : integer := 0
-- Selects CE counter width/threshold to assert ECC_Interrupt
);
port (
-- AXI Interface Signals
-- AXI Clock and Reset
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
ECC_Interrupt : out std_logic := '0';
ECC_UE : out std_logic := '0';
-- AXI Write Address Channel Signals (AW)
S_AXI_AWID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_AWLOCK : in std_logic;
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
-- AXI Write Data Channel Signals (W)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector(C_S_AXI_DATA_WIDTH/8-1 downto 0);
S_AXI_WLAST : in std_logic;
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
-- AXI Write Data Response Channel Signals (B)
S_AXI_BID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
-- AXI Read Address Channel Signals (AR)
S_AXI_ARID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ARLOCK : in std_logic;
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
-- AXI Read Data Channel Signals (R)
S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RLAST : out std_logic;
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- AXI-Lite ECC Register Interface Signals
-- AXI-Lite Clock and Reset
-- Note: AXI-Lite Control IF and AXI IF share the same clock.
-- S_AXI_CTRL_ACLK : in std_logic;
-- S_AXI_CTRL_ARESETN : in std_logic;
-- AXI-Lite Write Address Channel Signals (AW)
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
-- AXI-Lite Write Data Channel Signals (W)
S_AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
-- AXI-Lite Write Data Response Channel Signals (B)
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
-- AXI-Lite Read Address Channel Signals (AR)
S_AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
-- AXI-Lite Read Data Channel Signals (R)
S_AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
-- BRAM Interface Signals (Port A)
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_En_A : out std_logic;
BRAM_WE_A : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_Addr_A : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
BRAM_WrData_A : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_RdData_A : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
-- BRAM Interface Signals (Port B)
BRAM_Rst_B : out std_logic;
BRAM_Clk_B : out std_logic;
BRAM_En_B : out std_logic;
BRAM_WE_B : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_Addr_B : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
BRAM_WrData_B : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_RdData_B : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0)
);
end entity axi_bram_ctrl_top;
-------------------------------------------------------------------------------
architecture implementation of axi_bram_ctrl_top is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- All functions defined in axi_bram_ctrl_funcs package.
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-- Model behavior of AXI Interconnect in simulation for wrapping of ID values.
constant C_SIM_ONLY : std_logic := '1';
-- Reset active level (common through core)
constant C_RESET_ACTIVE : std_logic := '0';
-- Create top level constant to assign fixed value to ARSIZE and AWSIZE
-- when narrow bursting is parameterized out of the IP core instantiation.
-- constant AXI_FIXED_SIZE_WO_NARROW : std_logic_vector (2 downto 0) := Create_Size_Default;
-- v1.03a
constant AXI_FIXED_SIZE_WO_NARROW : integer := log2 (C_S_AXI_DATA_WIDTH/8);
-- Only instantiate logic based on C_S_AXI_PROTOCOL.
constant IF_IS_AXI4 : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4"));
constant IF_IS_AXI4LITE : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4LITE"));
-- Determine external ECC width.
-- Use function defined in axi_bram_ctrl_funcs package.
constant C_ECC_WIDTH : integer := Find_ECC_Size (C_ECC, C_S_AXI_DATA_WIDTH);
constant C_ECC_FULL_BIT_WIDTH : integer := Find_ECC_Full_Bit_Size (C_ECC, C_S_AXI_DATA_WIDTH);
-- Set internal parameters for ECC register enabling when C_ECC = 1
constant C_ENABLE_AXI_CTRL_REG_IF_I : integer := C_ECC;
constant C_CE_FAILING_REGISTERS_I : integer := C_ECC;
constant C_UE_FAILING_REGISTERS_I : integer := 0; -- Remove all UE registers
-- Catastrophic error indicated with ECC_UE & Interrupt flags.
constant C_ECC_STATUS_REGISTERS_I : integer := C_ECC;
constant C_ECC_ONOFF_REGISTER_I : integer := C_ECC;
constant C_CE_COUNTER_WIDTH : integer := 8 * C_ECC;
-- Counter only sized when C_ECC = 1.
-- Selects CE counter width/threshold to assert ECC_Interrupt
-- Hard coded at 8-bits to capture and count up to 256 correctable errors.
constant C_ECC_TYPE : integer := 1; -- v1.03a
-- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
-- Internal BRAM Signals
-- Port A
signal bram_en_a_int : std_logic := '0';
signal bram_we_a_int : std_logic_vector (((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto 0) := (others => '0');
signal bram_addr_a_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal bram_wrdata_a_int : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0');
signal bram_rddata_a_int : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0');
-- Port B
signal bram_addr_b_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal bram_en_b_int : std_logic := '0';
signal bram_we_b_int : std_logic_vector (((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto 0) := (others => '0');
signal bram_wrdata_b_int : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0');
signal bram_rddata_b_int : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0');
signal axi_awsize_int : std_logic_vector(2 downto 0) := (others => '0');
signal axi_arsize_int : std_logic_vector(2 downto 0) := (others => '0');
signal S_AXI_ARREADY_int : std_logic := '0';
signal S_AXI_AWREADY_int : std_logic := '0';
signal S_AXI_RID_int : std_logic_vector (C_S_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal S_AXI_BID_int : std_logic_vector (C_S_AXI_ID_WIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
-- *** BRAM Port A Output Signals ***
BRAM_Rst_A <= not (S_AXI_ARESETN);
BRAM_Clk_A <= S_AXI_ACLK;
BRAM_En_A <= bram_en_a_int;
BRAM_WE_A ((((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH)/8) - 1) downto (C_ECC_FULL_BIT_WIDTH/8)) <= bram_we_a_int((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
BRAM_Addr_A <= bram_addr_a_int;
bram_rddata_a_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= BRAM_RdData_A ((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_FULL_BIT_WIDTH));
BRAM_WrData_A ((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_FULL_BIT_WIDTH)) <= bram_wrdata_a_int(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Added for 13.3
-- Drive unused upper ECC bits to '0'
-- For bram_block compatibility, must drive unused upper bits to '0' for ECC 128-bit use case.
GEN_128_ECC_WR: if (C_S_AXI_DATA_WIDTH = 128) and (C_ECC = 1) generate
begin
BRAM_WrData_A ((C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_WIDTH)) <= (others => '0');
BRAM_WrData_A ((C_ECC_WIDTH-1) downto 0) <= bram_wrdata_a_int(C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH);
BRAM_WE_A ((C_ECC_FULL_BIT_WIDTH/8) - 1 downto 0) <= bram_we_a_int(((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto (C_S_AXI_DATA_WIDTH/8));
bram_rddata_a_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH) <= BRAM_RdData_A ((C_ECC_WIDTH-1) downto 0);
end generate GEN_128_ECC_WR;
GEN_ECC_WR: if ( not (C_S_AXI_DATA_WIDTH = 128) and (C_ECC = 1)) generate
begin
BRAM_WrData_A ((C_ECC_WIDTH - 1) downto 0) <= bram_wrdata_a_int(C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH);
BRAM_WE_A ((C_ECC_FULL_BIT_WIDTH/8) - 1 downto 0) <= bram_we_a_int(((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto (C_S_AXI_DATA_WIDTH/8));
bram_rddata_a_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH) <= BRAM_RdData_A ((C_ECC_WIDTH-1) downto 0);
end generate GEN_ECC_WR;
-- *** BRAM Port B Output Signals ***
GEN_PORT_B: if (C_SINGLE_PORT_BRAM = 0) generate
begin
BRAM_Rst_B <= not (S_AXI_ARESETN);
BRAM_WE_B ((((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH)/8) - 1) downto (C_ECC_FULL_BIT_WIDTH/8)) <= bram_we_b_int((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
BRAM_Addr_B <= bram_addr_b_int;
BRAM_En_B <= bram_en_b_int;
bram_rddata_b_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= BRAM_RdData_B ((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_FULL_BIT_WIDTH));
BRAM_WrData_B ((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_FULL_BIT_WIDTH)) <= bram_wrdata_b_int(C_S_AXI_DATA_WIDTH-1 downto 0);
-- 13.3
-- BRAM_WrData_B <= bram_wrdata_b_int;
-- Added for 13.3
-- Drive unused upper ECC bits to '0'
-- For bram_block compatibility, must drive unused upper bits to '0' for ECC 128-bit use case.
GEN_128_ECC_WR: if (C_S_AXI_DATA_WIDTH = 128) and (C_ECC = 1) generate
begin
BRAM_WrData_B ((C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_WIDTH)) <= (others => '0');
BRAM_WrData_B ((C_ECC_WIDTH-1) downto 0) <= bram_wrdata_b_int(C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH);
BRAM_WE_B ((C_ECC_FULL_BIT_WIDTH/8) - 1 downto 0) <= bram_we_b_int(((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto (C_S_AXI_DATA_WIDTH/8));
bram_rddata_b_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH) <= BRAM_RdData_B ((C_ECC_WIDTH-1) downto 0);
end generate GEN_128_ECC_WR;
GEN_ECC_WR: if ( not (C_S_AXI_DATA_WIDTH = 128) and (C_ECC = 1)) generate
begin
BRAM_WrData_B ((C_ECC_WIDTH - 1) downto 0) <= bram_wrdata_b_int(C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH);
BRAM_WE_B ((C_ECC_FULL_BIT_WIDTH/8) - 1 downto 0) <= bram_we_b_int(((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto (C_S_AXI_DATA_WIDTH/8));
bram_rddata_b_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH) <= BRAM_RdData_B ((C_ECC_WIDTH-1) downto 0);
end generate GEN_ECC_WR;
end generate GEN_PORT_B;
GEN_NO_PORT_B: if (C_SINGLE_PORT_BRAM = 1) generate
begin
BRAM_Rst_B <= '0';
BRAM_WE_B <= (others => '0');
BRAM_WrData_B <= (others => '0');
BRAM_Addr_B <= (others => '0');
BRAM_En_B <= '0';
end generate GEN_NO_PORT_B;
---------------------------------------------------------------------------
--
-- Generate: GEN_BRAM_CLK_B
-- Purpose: Only drive BRAM_Clk_B when dual port BRAM is enabled.
--
---------------------------------------------------------------------------
GEN_BRAM_CLK_B: if (C_SINGLE_PORT_BRAM = 0) generate
begin
BRAM_Clk_B <= S_AXI_ACLK;
end generate GEN_BRAM_CLK_B;
---------------------------------------------------------------------------
--
-- Generate: GEN_NO_BRAM_CLK_B
-- Purpose: Drive default value for BRAM_Clk_B when single port
-- BRAM is enabled and no clock is necessary on the inactive
-- BRAM port.
--
---------------------------------------------------------------------------
GEN_NO_BRAM_CLK_B: if (C_SINGLE_PORT_BRAM = 1) generate
begin
BRAM_Clk_B <= '0';
end generate GEN_NO_BRAM_CLK_B;
---------------------------------------------------------------------------
-- Generate top level ARSIZE and AWSIZE signals for rd_chnl and wr_chnl
-- respectively, based on design parameter setting of generic,
-- C_S_AXI_SUPPORTS_NARROW_BURST.
---------------------------------------------------------------------------
--
-- Generate: GEN_W_NARROW
-- Purpose: Create internal AWSIZE and ARSIZE signal for write and
-- read channel modules based on top level AXI signal inputs.
--
---------------------------------------------------------------------------
GEN_W_NARROW: if (C_S_AXI_SUPPORTS_NARROW_BURST = 1) and (IF_IS_AXI4) generate
begin
axi_awsize_int <= S_AXI_AWSIZE;
axi_arsize_int <= S_AXI_ARSIZE;
end generate GEN_W_NARROW;
---------------------------------------------------------------------------
--
-- Generate: GEN_WO_NARROW
-- Purpose: Create internal AWSIZE and ARSIZE signal for write and
-- read channel modules based on hard coded
-- value that indicates all AXI transfers will be equal in
-- size to the AXI data bus.
--
---------------------------------------------------------------------------
GEN_WO_NARROW: if (C_S_AXI_SUPPORTS_NARROW_BURST = 0) or (IF_IS_AXI4LITE) generate
begin
-- axi_awsize_int <= AXI_FIXED_SIZE_WO_NARROW; -- When AXI-LITE (no narrow transfers supported)
-- axi_arsize_int <= AXI_FIXED_SIZE_WO_NARROW;
-- v1.03a
axi_awsize_int <= std_logic_vector (to_unsigned (AXI_FIXED_SIZE_WO_NARROW, 3));
axi_arsize_int <= std_logic_vector (to_unsigned (AXI_FIXED_SIZE_WO_NARROW, 3));
end generate GEN_WO_NARROW;
S_AXI_ARREADY <= S_AXI_ARREADY_int;
S_AXI_AWREADY <= S_AXI_AWREADY_int;
---------------------------------------------------------------------------
--
-- Generate: GEN_AXI_LITE
-- Purpose: Create internal signals for lower level write and read
-- channel modules to discard unused AXI signals when the
-- AXI protocol is set up for AXI-LITE.
--
---------------------------------------------------------------------------
GEN_AXI4LITE: if (IF_IS_AXI4LITE) generate
begin
-- For simulation purposes ONLY
-- AXI Interconnect handles this in real system topologies.
S_AXI_BID <= S_AXI_BID_int;
S_AXI_RID <= S_AXI_RID_int;
-----------------------------------------------------------------------
--
-- Generate: GEN_SIM_ONLY
-- Purpose: Mimic behavior of AXI Interconnect in simulation.
-- In real hardware system, AXI Interconnect stores and
-- wraps value of ARID to RID and AWID to BID.
--
-----------------------------------------------------------------------
GEN_SIM_ONLY: if (C_SIM_ONLY = '1') generate
begin
-------------------------------------------------------------------
-- Must register and wrap the AWID signal
REG_BID: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = C_RESET_ACTIVE) then
S_AXI_BID_int <= (others => '0');
elsif (S_AXI_AWVALID = '1') and (S_AXI_AWREADY_int = '1') then
S_AXI_BID_int <= S_AXI_AWID;
else
S_AXI_BID_int <= S_AXI_BID_int;
end if;
end if;
end process REG_BID;
-------------------------------------------------------------------
-- Must register and wrap the ARID signal
REG_RID: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = C_RESET_ACTIVE) then
S_AXI_RID_int <= (others => '0');
elsif (S_AXI_ARVALID = '1') and (S_AXI_ARREADY_int = '1') then
S_AXI_RID_int <= S_AXI_ARID;
else
S_AXI_RID_int <= S_AXI_RID_int;
end if;
end if;
end process REG_RID;
-------------------------------------------------------------------
end generate GEN_SIM_ONLY;
---------------------------------------------------------------------------
--
-- Generate: GEN_HW
-- Purpose: Drive default values of RID and BID. In real system
-- these are left unconnected and AXI Interconnect is
-- responsible for values.
--
---------------------------------------------------------------------------
GEN_HW: if (C_SIM_ONLY = '0') generate
begin
S_AXI_BID_int <= (others => '0');
S_AXI_RID_int <= (others => '0');
end generate GEN_HW;
---------------------------------------------------------------------------
-- Instance: I_AXI_LITE
--
-- Description:
-- This module is for the AXI-Lite
-- instantiation of the BRAM controller interface.
--
-- Responsible for shared address pipelining between the
-- write address (AW) and read address (AR) channels.
-- Controls (seperately) the data flows for the write data
-- (W), write response (B), and read data (R) channels.
--
-- Creates a shared port to BRAM (for all read and write
-- transactions) or dual BRAM port utilization based on a
-- generic parameter setting.
--
-- Instantiates ECC register block if enabled and
-- generates ECC logic, when enabled.
--
--
---------------------------------------------------------------------------
I_AXI_LITE : entity work.axi_lite
generic map (
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
-- C_FAMILY => C_FAMILY ,
C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH ,
C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH ,
C_ECC => C_ECC ,
C_ECC_TYPE => C_ECC_TYPE , -- v1.03a
C_ECC_WIDTH => C_ECC_WIDTH , -- 8-bits for ECC (32 & 64-bit data widths)
C_ENABLE_AXI_CTRL_REG_IF => C_ENABLE_AXI_CTRL_REG_IF_I , -- Use internal constants determined by C_ECC
C_FAULT_INJECT => C_FAULT_INJECT ,
C_CE_FAILING_REGISTERS => C_CE_FAILING_REGISTERS_I ,
C_UE_FAILING_REGISTERS => C_UE_FAILING_REGISTERS_I ,
C_ECC_STATUS_REGISTERS => C_ECC_STATUS_REGISTERS_I ,
C_ECC_ONOFF_REGISTER => C_ECC_ONOFF_REGISTER_I ,
C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE ,
C_CE_COUNTER_WIDTH => C_CE_COUNTER_WIDTH
)
port map (
S_AXI_AClk => S_AXI_ACLK ,
S_AXI_AResetn => S_AXI_ARESETN ,
ECC_Interrupt => ECC_Interrupt ,
ECC_UE => ECC_UE ,
AXI_AWADDR => S_AXI_AWADDR ,
AXI_AWVALID => S_AXI_AWVALID ,
AXI_AWREADY => S_AXI_AWREADY_int ,
AXI_WDATA => S_AXI_WDATA ,
AXI_WSTRB => S_AXI_WSTRB ,
AXI_WVALID => S_AXI_WVALID ,
AXI_WREADY => S_AXI_WREADY ,
AXI_BRESP => S_AXI_BRESP ,
AXI_BVALID => S_AXI_BVALID ,
AXI_BREADY => S_AXI_BREADY ,
AXI_ARADDR => S_AXI_ARADDR ,
AXI_ARVALID => S_AXI_ARVALID ,
AXI_ARREADY => S_AXI_ARREADY_int ,
AXI_RDATA => S_AXI_RDATA ,
AXI_RRESP => S_AXI_RRESP ,
AXI_RLAST => S_AXI_RLAST ,
AXI_RVALID => S_AXI_RVALID ,
AXI_RREADY => S_AXI_RREADY ,
-- Add AXI-Lite ECC Register Ports
-- Note: AXI-Lite Control IF and AXI IF share the same clock.
-- S_AXI_CTRL_ACLK => S_AXI_CTRL_ACLK ,
-- S_AXI_CTRL_ARESETN => S_AXI_CTRL_ARESETN ,
AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID ,
AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY ,
AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR ,
AXI_CTRL_WDATA => S_AXI_CTRL_WDATA ,
AXI_CTRL_WVALID => S_AXI_CTRL_WVALID ,
AXI_CTRL_WREADY => S_AXI_CTRL_WREADY ,
AXI_CTRL_BRESP => S_AXI_CTRL_BRESP ,
AXI_CTRL_BVALID => S_AXI_CTRL_BVALID ,
AXI_CTRL_BREADY => S_AXI_CTRL_BREADY ,
AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR ,
AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID ,
AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY ,
AXI_CTRL_RDATA => S_AXI_CTRL_RDATA ,
AXI_CTRL_RRESP => S_AXI_CTRL_RRESP ,
AXI_CTRL_RVALID => S_AXI_CTRL_RVALID ,
AXI_CTRL_RREADY => S_AXI_CTRL_RREADY ,
BRAM_En_A => bram_en_a_int ,
BRAM_WE_A => bram_we_a_int ,
BRAM_Addr_A => bram_addr_a_int ,
BRAM_WrData_A => bram_wrdata_a_int ,
BRAM_RdData_A => bram_rddata_a_int ,
BRAM_En_B => bram_en_b_int ,
BRAM_WE_B => bram_we_b_int ,
BRAM_Addr_B => bram_addr_b_int ,
BRAM_WrData_B => bram_wrdata_b_int ,
BRAM_RdData_B => bram_rddata_b_int
);
end generate GEN_AXI4LITE;
---------------------------------------------------------------------------
--
-- Generate: GEN_AXI
-- Purpose: Only create internal signals for lower level write and read
-- channel modules to assign AXI signals when the
-- AXI protocol is set up for non AXI-LITE IF connections.
-- For AXI4, all AXI signals are assigned to lower level modules.
--
-- For AXI-Lite connections, generate statement above will
-- create default values on these signals (assigned here).
--
---------------------------------------------------------------------------
GEN_AXI4: if (IF_IS_AXI4) generate
begin
---------------------------------------------------------------------------
-- Instance: I_FULL_AXI
--
-- Description:
-- Full AXI BRAM controller logic.
-- Instantiates wr_chnl and rd_chnl modules.
-- If enabled, ECC register interface is included.
--
---------------------------------------------------------------------------
I_FULL_AXI : entity work.full_axi
generic map (
C_S_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
C_S_AXI_SUPPORTS_NARROW_BURST => C_S_AXI_SUPPORTS_NARROW_BURST ,
C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH ,
C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH ,
C_ECC => C_ECC ,
C_ECC_WIDTH => C_ECC_WIDTH , -- 8-bits for ECC (32 & 64-bit data widths)
C_ECC_TYPE => C_ECC_TYPE , -- v1.03a
C_FAULT_INJECT => C_FAULT_INJECT ,
C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE ,
C_ENABLE_AXI_CTRL_REG_IF => C_ENABLE_AXI_CTRL_REG_IF_I , -- Use internal constants determined by C_ECC
C_CE_FAILING_REGISTERS => C_CE_FAILING_REGISTERS_I ,
C_UE_FAILING_REGISTERS => C_UE_FAILING_REGISTERS_I ,
C_ECC_STATUS_REGISTERS => C_ECC_STATUS_REGISTERS_I ,
C_ECC_ONOFF_REGISTER => C_ECC_ONOFF_REGISTER_I ,
C_CE_COUNTER_WIDTH => C_CE_COUNTER_WIDTH
)
port map (
S_AXI_AClk => S_AXI_ACLK ,
S_AXI_AResetn => S_AXI_ARESETN ,
ECC_Interrupt => ECC_Interrupt ,
ECC_UE => ECC_UE ,
S_AXI_AWID => S_AXI_AWID ,
S_AXI_AWADDR => S_AXI_AWADDR(C_S_AXI_ADDR_WIDTH-1 downto 0),
S_AXI_AWLEN => S_AXI_AWLEN ,
S_AXI_AWSIZE => axi_awsize_int ,
S_AXI_AWBURST => S_AXI_AWBURST ,
S_AXI_AWLOCK => S_AXI_AWLOCK ,
S_AXI_AWCACHE => S_AXI_AWCACHE ,
S_AXI_AWPROT => S_AXI_AWPROT ,
S_AXI_AWVALID => S_AXI_AWVALID ,
S_AXI_AWREADY => S_AXI_AWREADY_int ,
S_AXI_WDATA => S_AXI_WDATA ,
S_AXI_WSTRB => S_AXI_WSTRB ,
S_AXI_WLAST => S_AXI_WLAST ,
S_AXI_WVALID => S_AXI_WVALID ,
S_AXI_WREADY => S_AXI_WREADY ,
S_AXI_BID => S_AXI_BID ,
S_AXI_BRESP => S_AXI_BRESP ,
S_AXI_BVALID => S_AXI_BVALID ,
S_AXI_BREADY => S_AXI_BREADY ,
S_AXI_ARID => S_AXI_ARID ,
S_AXI_ARADDR => S_AXI_ARADDR(C_S_AXI_ADDR_WIDTH-1 downto 0),
S_AXI_ARLEN => S_AXI_ARLEN ,
S_AXI_ARSIZE => axi_arsize_int ,
S_AXI_ARBURST => S_AXI_ARBURST ,
S_AXI_ARLOCK => S_AXI_ARLOCK ,
S_AXI_ARCACHE => S_AXI_ARCACHE ,
S_AXI_ARPROT => S_AXI_ARPROT ,
S_AXI_ARVALID => S_AXI_ARVALID ,
S_AXI_ARREADY => S_AXI_ARREADY_int ,
S_AXI_RID => S_AXI_RID ,
S_AXI_RDATA => S_AXI_RDATA ,
S_AXI_RRESP => S_AXI_RRESP ,
S_AXI_RLAST => S_AXI_RLAST ,
S_AXI_RVALID => S_AXI_RVALID ,
S_AXI_RREADY => S_AXI_RREADY ,
-- Add AXI-Lite ECC Register Ports
-- Note: AXI-Lite Control IF and AXI IF share the same clock.
-- S_AXI_CTRL_ACLK => S_AXI_CTRL_ACLK ,
-- S_AXI_CTRL_ARESETN => S_AXI_CTRL_ARESETN ,
S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID ,
S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY ,
S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR ,
S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA ,
S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID ,
S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY ,
S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP ,
S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID ,
S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY ,
S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR ,
S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID ,
S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY ,
S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA ,
S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP ,
S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID ,
S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY ,
BRAM_En_A => bram_en_a_int ,
BRAM_WE_A => bram_we_a_int ,
BRAM_WrData_A => bram_wrdata_a_int ,
BRAM_Addr_A => bram_addr_a_int ,
BRAM_RdData_A => bram_rddata_a_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) ,
BRAM_En_B => bram_en_b_int ,
BRAM_WE_B => bram_we_b_int ,
BRAM_Addr_B => bram_addr_b_int ,
BRAM_WrData_B => bram_wrdata_b_int ,
BRAM_RdData_B => bram_rddata_b_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0)
);
-- v1.02a
-- Seperate instantiations for wr_chnl and rd_chnl moved to
-- full_axi module.
end generate GEN_AXI4;
end architecture implementation;
| bsd-2-clause | 7144368b0a717293af767899ec4f42a8 | 0.463962 | 3.790407 | false | false | false | false |
Jorge9314/ElectronicaDigital | Impresora2D/Divisor_Frecuencia.vhd | 1 | 569 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Divisor_Frecuencia is
Port ( clk : in STD_LOGIC;
Salida : out STD_LOGIC := '0');
end Divisor_Frecuencia;
architecture arq_Divisor_Frecuencia of Divisor_Frecuencia is
constant repeticion : integer := 5208;
shared variable contador : integer := repeticion;
begin
process begin
wait until rising_edge(clk);
if contador > 0 then
Salida <= '0';
contador := contador - 1;
else
Salida <= '1';
contador := repeticion;
end if;
end process;
end arq_Divisor_Frecuencia;
| gpl-3.0 | a8cbe62f8fdef99b15e438201fd4a658 | 0.666081 | 3.427711 | false | false | false | false |
Yarr/Yarr-fw | rtl/i2c-master/i2c_master_bit_ctrl.vhd | 2 | 15,439 | -- ==================================================================
-- >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- ------------------------------------------------------------------
-- Copyright (c) 2013 by Lattice Semiconductor Corporation
-- ALL RIGHTS RESERVED
-- ------------------------------------------------------------------
--
-- Permission:
--
-- Lattice SG Pte. Ltd. grants permission to use this code
-- pursuant to the terms of the Lattice Reference Design License Agreement.
--
--
-- Disclaimer:
--
-- This VHDL or Verilog source code is intended as a design reference
-- which illustrates how these types of functions can be implemented.
-- It is the user's responsibility to verify their design for
-- consistency and functionality through the use of formal
-- verification methods. Lattice provides no warranty
-- regarding the use or functionality of this code.
--
-- --------------------------------------------------------------------
--
-- Lattice SG Pte. Ltd.
-- 101 Thomson Road, United Square #07-02
-- Singapore 307591
--
--
-- TEL: 1-800-Lattice (USA and Canada)
-- +65-6631-2000 (Singapore)
-- +1-503-268-8001 (other locations)
--
-- web: http:--www.latticesemi.com/
-- email: [email protected]
--
-- --------------------------------------------------------------------
-- Code Revision History :
-- --------------------------------------------------------------------
-- Ver: | Author |Mod. Date |Changes Made:
-- V1.0 |K.P. | 7/09 | Initial ver for VHDL
-- | converted from LSC ref design RD1046
-- --------------------------------------------------------------------
--/////////////////////////////////////
--// Bit controller section
--/////////////////////////////////////
--//
--// Translate simple commands into SCL/SDA transitions
--// Each command has 5 states, A/B/C/D/idle
--//
--// start: SCL ~~~~~~~~~~\____
--// SDA ~~~~~~~~\______
--// x | A | B | C | D | i
--//
--// repstart SCL ____/~~~~\___
--// SDA __/~~~\______
--// x | A | B | C | D | i
--//
--// stop SCL ____/~~~~~~~~
--// SDA ==\____/~~~~~
--// x | A | B | C | D | i
--//
--//- write SCL ____/~~~~\____
--// SDA ==X=========X=
--// x | A | B | C | D | i
--//
--//- read SCL ____/~~~~\____
--// SDA XXXX=====XXXX
--// x | A | B | C | D | i
--//
--
--// Timing: Normal mode Fast mode
--///////////////////////////////////////////////////////////////////////
--// Fscl 100KHz 400KHz
--// Th_scl 4.0us 0.6us High period of SCL
--// Tl_scl 4.7us 1.3us Low period of SCL
--// Tsu:sta 4.7us 0.6us setup time for a repeated start condition
--// Tsu:sto 4.0us 0.6us setup time for a stop conditon
--// Tbuf 4.7us 1.3us Bus free time between a stop and start condition
--//
--
-- --------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity i2c_master_bit_ctrl is
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
clk_cnt : in std_logic_vector(15 downto 0); -- clock prescale value
ena : in std_logic; -- core enable signal
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command complete acknowledge
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- i2c bus arbitration lost
din : in std_logic;
dout : out std_logic;
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable (active low)
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable (active low)
);
end;
architecture arch of i2c_master_bit_ctrl is
--attribute UGROUP:string;
--attribute UGROUP of arch : label is "bit_group";
signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs
signal dscl_oen : std_logic; -- delayed scl_oen
signal sda_chk : std_logic; -- check SDA output (Multi-master arbitration)
signal clk_en : std_logic; -- clock generation signals
signal slave_wait : std_logic;
-- bus status controller signals
signal dSCL,dSDA : std_logic;
signal sta_condition : std_logic;
signal sto_condition : std_logic;
signal cmd_stop : std_logic;
signal cnt : std_logic_vector(15 downto 0); -- clock divider counter
signal scl_oen_int : std_logic;
signal sda_oen_int : std_logic;
signal busy_int : std_logic;
signal al_int : std_logic;
-- state machine variable
signal c_state : std_logic_vector(16 downto 0);
constant idle : std_logic_vector(16 downto 0) := "00000000000000000";
constant start_a : std_logic_vector(16 downto 0) := "00000000000000001";
constant start_b : std_logic_vector(16 downto 0) := "00000000000000010";
constant start_c : std_logic_vector(16 downto 0) := "00000000000000100";
constant start_d : std_logic_vector(16 downto 0) := "00000000000001000";
constant start_e : std_logic_vector(16 downto 0) := "00000000000010000";
constant stop_a : std_logic_vector(16 downto 0) := "00000000000100000";
constant stop_b : std_logic_vector(16 downto 0) := "00000000001000000";
constant stop_c : std_logic_vector(16 downto 0) := "00000000010000000";
constant stop_d : std_logic_vector(16 downto 0) := "00000000100000000";
constant rd_a : std_logic_vector(16 downto 0) := "00000001000000000";
constant rd_b : std_logic_vector(16 downto 0) := "00000010000000000";
constant rd_c : std_logic_vector(16 downto 0) := "00000100000000000";
constant rd_d : std_logic_vector(16 downto 0) := "00001000000000000";
constant wr_a : std_logic_vector(16 downto 0) := "00010000000000000";
constant wr_b : std_logic_vector(16 downto 0) := "00100000000000000";
constant wr_c : std_logic_vector(16 downto 0) := "01000000000000000";
constant wr_d : std_logic_vector(16 downto 0) := "10000000000000000";
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "1000";
begin
scl_oen <= scl_oen_int;
sda_oen <= sda_oen_int;
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
-- delay scl_oen
process(clk)
begin
if rising_edge(clk) then
dscl_oen <= scl_oen_int;
end if;
end process;
slave_wait <= '1' when ((dscl_oen = '1') AND (sSCL = '0')) else '0';
-- generate clk enable signal
process(clk,nReset)
begin
if (nReset = '0') then
cnt <= (others => '0');
clk_en <= '1';
elsif rising_edge(clk) then
if (rst = '1') then
cnt <= (others => '0');
clk_en <= '1';
elsif ((cnt = "0000000000000000") OR (ena = '0')) then
cnt <= clk_cnt;
clk_en <= '1';
elsif (slave_wait = '1') then
cnt <= cnt;
clk_en <= '0';
else
cnt <= cnt - '1';
clk_en <= '0';
end if;
end if;
end process;
-- synchronize SCL and SDA inputs
-- reduce metastability risc
process(clk,nReset)
begin
if (nReset = '0') then
sSCL <= '1';
sSDA <= '1';
dSCL <= '1';
dSDA <= '1';
elsif rising_edge(clk) then
if (rst = '1') then
sSCL <= '1';
sSDA <= '1';
dSCL <= '1';
dSDA <= '1';
else
dSCL <= sSCL;
dSDA <= sSDA;
if ((scl_i = '1') OR (scl_i = 'H')) then
sSCL <= '1';
else
sSCL <= '0';
end if;
if ((sda_i = '1') OR (sda_i = 'H')) then
sSDA <= '1';
else
sSDA <= '0';
end if;
end if;
end if;
end process;
-- detect start condition => detect falling edge on SDA while SCL is high
-- detect stop condition => detect rising edge on SDA while SCL is high
process(clk,nReset)
begin
if (nReset = '0') then
sta_condition <= '0';
sto_condition <= '0';
elsif rising_edge(clk) then
if (rst = '1') then
sta_condition <= '0';
sto_condition <= '0';
else
sta_condition <= NOT(sSDA) AND dSDA AND sSCL;
sto_condition <= sSDA AND NOT(dSDA) AND sSCL;
end if;
end if;
end process;
-- generate i2c bus busy signal
process(clk,nReset)
begin
if (nReset = '0') then
busy_int <= '0';
elsif rising_edge(clk) then
if (rst = '1') then
busy_int <= '0';
else
busy_int <= (sta_condition OR busy_int) AND NOT(sto_condition);
end if;
end if;
end process;
busy <= busy_int;
-- generate arbitration lost signal
-- aribitration lost when:
-- 1) master drives SDA high, but the i2c bus is low
-- 2) stop detected while not requested
process(clk,nReset)
begin
if (nReset = '0') then
cmd_stop <= '0';
elsif rising_edge(clk) then
if (rst = '1') then
cmd_stop <= '0';
elsif (clk_en = '1') then
if (cmd = I2C_CMD_STOP) then
cmd_stop <= '1';
else
cmd_stop <= '0';
end if;
end if;
end if;
end process;
process(clk,nReset)
begin
if (nReset = '0') then
al_int <= '0';
elsif rising_edge(clk) then
if (rst = '1') then
al_int <= '0';
else
if (((sda_chk = '1') AND (sSDA = '0') AND (sda_oen_int = '1')) OR ((c_state /= idle) AND (sto_condition = '1') AND (cmd_stop = '0'))) then
al_int <= '1';
else
al_int <= '0';
end if;
end if;
end if;
end process;
al <= al_int;
-- generate dout signal (store SDA on rising edge of SCL)
process(clk)
begin
if rising_edge(clk) then
if ((sSCL = '1') AND (dSCL = '0')) then
dout <= sSDA;
end if;
end if;
end process;
--generate state machine
process(clk,nReset)
begin
if (nReset = '0') then
c_state <= idle;
cmd_ack <= '0';
scl_oen_int <= '1';
sda_oen_int <= '1';
sda_chk <= '0';
elsif rising_edge(clk) then
if ((rst = '1') OR (al_int = '1')) then
c_state <= idle;
cmd_ack <= '0';
scl_oen_int <= '1';
sda_oen_int <= '1';
sda_chk <= '0';
else
cmd_ack <= '0'; --default no command acknowledge + assert cmd_ack only 1clk cycle
if (clk_en = '1') then
case (c_state) is
when idle =>
case (cmd) is
when I2C_CMD_START => c_state <= start_a;
when I2C_CMD_STOP => c_state <= stop_a;
when I2C_CMD_WRITE => c_state <= wr_a;
when I2C_CMD_READ => c_state <= rd_a;
when others => c_state <= idle;
end case;
scl_oen_int <= scl_oen_int; -- keep SCL in same state
sda_oen_int <= sda_oen_int; -- keep SDA in same state
sda_chk <= '0'; -- don't check SDA output
when start_a => -- start
c_state <= start_b;
scl_oen_int <= scl_oen_int; -- keep SCL in same state
sda_oen_int <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA output
when start_b =>
c_state <= start_c;
scl_oen_int <= '1'; -- set SCL high
sda_oen_int <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA output
when start_c =>
c_state <= start_d;
scl_oen_int <= '1'; -- keep SCL high
sda_oen_int <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA output
when start_d =>
c_state <= start_e;
scl_oen_int <= '1'; -- keep SCL high
sda_oen_int <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA output
when start_e =>
c_state <= idle;
cmd_ack <= '1';
scl_oen_int <= '0'; -- set SCL low
sda_oen_int <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA output
when stop_a => -- stop
c_state <= stop_b;
scl_oen_int <= '0'; -- keep SCL low
sda_oen_int <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA output
when stop_b =>
c_state <= stop_c;
scl_oen_int <= '1'; -- set SCL high
sda_oen_int <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA output
when stop_c =>
c_state <= stop_d;
scl_oen_int <= '1'; -- keep SCL high
sda_oen_int <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA output
when stop_d =>
c_state <= idle;
cmd_ack <= '1';
scl_oen_int <= '1'; -- keep SCL high
sda_oen_int <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA output
when rd_a => -- read
c_state <= rd_b;
scl_oen_int <= '0'; -- keep SCL low
sda_oen_int <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA output
when rd_b =>
c_state <= rd_c;
scl_oen_int <= '1'; -- set SCL high
sda_oen_int <= '1'; -- keep SDA tri-stated
sda_chk <= '0'; -- don't check SDA output
when rd_c =>
c_state <= rd_d;
scl_oen_int <= '1'; -- keep SCL high
sda_oen_int <= '1'; -- keep SDA tri-stated
sda_chk <= '0'; -- don't check SDA output
when rd_d =>
c_state <= idle;
cmd_ack <= '1';
scl_oen_int <= '0'; -- set SCL low
sda_oen_int <= '1'; -- keep SDA tri-stated
sda_chk <= '0'; -- don't check SDA output
when wr_a => -- write
c_state <= wr_b;
scl_oen_int <= '0'; -- keep SCL low
sda_oen_int <= din; -- set SDA
sda_chk <= '0'; -- don't check SDA output (SCL low)
when wr_b =>
c_state <= wr_c;
scl_oen_int <= '1'; -- set SCL high
sda_oen_int <= din; -- keep SDA
sda_chk <= '1'; -- check SDA output
when wr_c =>
c_state <= wr_d;
scl_oen_int <= '1'; -- keep SCL high
sda_oen_int <= din;
sda_chk <= '1'; -- check SDA output
when wr_d =>
c_state <= idle;
cmd_ack <= '1';
scl_oen_int <= '0'; -- set SCL low
sda_oen_int <= din;
sda_chk <= '0'; -- don't check SDA output (SCL low)
when others => NULL;
end case;
end if;
end if;
end if;
end process;
-- assign scl and sda output (always gnd)
scl_o <= '0';
sda_o <= '0';
end arch;
| gpl-3.0 | 8a7fbf8e8db0847e17bce2fbfbf67729 | 0.486107 | 3.231268 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/component/rule_017_test_input.fixed.vhd | 1 | 681 |
architecture RTl of FIFO is
component fifo is
generic (
gen1 : integer := 0; -- Comment
gen2 : integer := 1; -- Comment
gen3 : integer := 2 -- Comment
);
port (
sig1 : std_logic; -- Comment
sig2 : std_logic; -- Comment
sig3 : std_logic -- Comment
);
end component fifo;
-- Failures below
component fifo is
generic (
gen1 : integer := 0; -- Comment
gen2 : integer := 1; -- Comment
gen3 : integer := 2 -- Comment
);
port (
sig1 : std_logic; -- Comment
sig2 : std_logic; -- Comment
sig3 : std_logic -- Comment
);
end component fifo;
begin
end architecture RTL;
| gpl-3.0 | dbd43fb048d68f90b04a45af969cf6ce | 0.544787 | 3.783333 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/styles/indent_only/turbocodes/iteration_synth.vhd | 1 | 10,448 | ----------------------------------------------------------------------
---- ----
---- iteration_synth.vhd ----
---- ----
---- This file is part of the turbo decoder IP core project ----
---- http://www.opencores.org/projects/turbocodes/ ----
---- ----
---- Author(s): ----
---- - David Brochart([email protected]) ----
---- ----
---- All additional information is available in the README.txt ----
---- file. ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2005 Authors ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
architecture synth of iteration is
signal zout1 : ARRAY4c;
signal zout2 : ARRAY4c;
signal zout1Perm : ARRAY4c;
signal zoutInt1 : ARRAY4c;
signal zout2Int : ARRAY4c;
signal tmp0 : std_logic_vector(Z_WIDTH * 4 + SIG_WIDTH * 2 - 1 downto 0);
signal tmp1 : std_logic_vector(Z_WIDTH * 4 + SIG_WIDTH * 2 - 1 downto 0);
signal tmp2 : std_logic_vector(SIG_WIDTH * 6 - 1 downto 0);
signal tmp3 : std_logic_vector(SIG_WIDTH * 6 - 1 downto 0);
signal tmp4 : std_logic_vector(SIG_WIDTH * 4 - 1 downto 0);
signal tmp5 : std_logic_vector(SIG_WIDTH * 4 - 1 downto 0);
signal tmp6 : std_logic_vector(Z_WIDTH * 4 - 1 downto 0);
signal tmp7 : std_logic_vector(Z_WIDTH * 4 - 1 downto 0);
signal tmp8 : std_logic_vector(SIG_WIDTH * 6 - 1 downto 0);
signal tmp9 : std_logic_vector(SIG_WIDTH * 6 - 1 downto 0);
signal tmp10 : std_logic_vector(SIG_WIDTH * 8 - 1 downto 0);
signal tmp11 : std_logic_vector(SIG_WIDTH * 8 - 1 downto 0);
signal abDel1Perm : ARRAY2a;
signal abDel1PermInt: ARRAY2a;
signal aDel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal bDel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal yDel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal wDel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal yIntDel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal wIntDel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal aDel2 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal bDel2 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal yDel2 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal wDel2 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal aDecInt : std_logic;
signal bDecInt : std_logic;
signal aDel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal bDel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal yDel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal wDel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal yIntDel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal wIntDel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal yIntDel4 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal wIntDel4 : std_logic_vector(SIG_WIDTH - 1 downto 0);
begin
sova_i0 : sova port map (
clk => clk,
rst => rst,
aNoisy => a,
bNoisy => b,
yNoisy => y,
wNoisy => w,
zin => zin,
zout => zout1,
aClean => aDec,
bClean => bDec
);
zPermut_i0 : zPermut generic map (
flip => (TREL1_LEN + TREL2_LEN + 2 + delay + 1) mod 2
)
port map (
flipflop => flipflop,
z => zout1,
zPerm => zout1Perm
);
tmp0 <= zout1Perm(0) & zout1Perm(1) & zout1Perm(2) & zout1Perm(3) & abDel1Perm(0) & abDel1Perm(1);
interleaver_i0 : interleaver generic map (
delay => TREL1_LEN + TREL2_LEN + 2 + delay,
way => 0
)
port map (
clk => clk,
rst => rst,
d => tmp0,
q => tmp1
);
zoutInt1(0) <= tmp1(Z_WIDTH * 4 + SIG_WIDTH * 2 - 1 downto Z_WIDTH * 3 + SIG_WIDTH * 2);
zoutInt1(1) <= tmp1(Z_WIDTH * 3 + SIG_WIDTH * 2 - 1 downto Z_WIDTH * 2 + SIG_WIDTH * 2);
zoutInt1(2) <= tmp1(Z_WIDTH * 2 + SIG_WIDTH * 2 - 1 downto Z_WIDTH * 1 + SIG_WIDTH * 2);
zoutInt1(3) <= tmp1(Z_WIDTH * 1 + SIG_WIDTH * 2 - 1 downto Z_WIDTH * 0 + SIG_WIDTH * 2);
abDel1PermInt(0) <= tmp1(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1);
abDel1PermInt(1) <= tmp1(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0);
tmp2 <= a & b & y & w & yInt & wInt;
delayer_i0 : delayer generic map (
delay => TREL1_LEN + TREL2_LEN
)
port map (
clk => clk,
rst => rst,
d => tmp2,
q => tmp3
);
aDel1 <= tmp3(SIG_WIDTH * 6 - 1 downto SIG_WIDTH * 5);
bDel1 <= tmp3(SIG_WIDTH * 5 - 1 downto SIG_WIDTH * 4);
yDel1 <= tmp3(SIG_WIDTH * 4 - 1 downto SIG_WIDTH * 3);
wDel1 <= tmp3(SIG_WIDTH * 3 - 1 downto SIG_WIDTH * 2);
yIntDel1 <= tmp3(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1);
wIntDel1 <= tmp3(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0);
abPermut_i0 : abPermut generic map (
flip => (TREL1_LEN + TREL2_LEN + 2 + delay + 1) mod 2
)
port map (
flipflop => flipflop,
a => aDel1,
b => bDel1,
abPerm => abDel1Perm
);
tmp4 <= aDel1 & bDel1 & yDel1 & wDel1;
delayer_i1 : delayer generic map (
delay => FRSIZE
)
port map (
clk => clk,
rst => rst,
d => tmp4,
q => tmp5
);
aDel2 <= tmp5(SIG_WIDTH * 4 - 1 downto SIG_WIDTH * 3);
bDel2 <= tmp5(SIG_WIDTH * 3 - 1 downto SIG_WIDTH * 2);
yDel2 <= tmp5(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1);
wDel2 <= tmp5(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0);
sova_i1 : sova port map (
clk => clk,
rst => rst,
aNoisy => abDel1PermInt(1),
bNoisy => abDel1PermInt(0),
yNoisy => yIntDel1,
wNoisy => wIntDel1,
zin => zoutInt1,
zout => zout2,
aClean => aDecInt,
bClean => bDecInt
);
tmp6 <= zout2(0) & zout2(1) & zout2(2) & zout2(3);
deinterleaver_i0 : interleaver generic map (
delay => 2 * (TREL1_LEN + TREL2_LEN + 2) + FRSIZE + delay,
way => 1
)
port map (
clk => clk,
rst => rst,
d => tmp6,
q => tmp7
);
zout2Int(0) <= tmp7(Z_WIDTH * 4 - 1 downto Z_WIDTH * 3);
zout2Int(1) <= tmp7(Z_WIDTH * 3 - 1 downto Z_WIDTH * 2);
zout2Int(2) <= tmp7(Z_WIDTH * 2 - 1 downto Z_WIDTH * 1);
zout2Int(3) <= tmp7(Z_WIDTH * 1 - 1 downto Z_WIDTH * 0);
zPermut_i1 : zPermut generic map (
flip => (2 * (TREL1_LEN + TREL2_LEN + 2) + FRSIZE + delay) mod 2
)
port map (
flipflop => flipflop,
z => zout2Int,
zPerm => zout
);
tmp8 <= aDel2 & bDel2 & yDel2 & wDel2 & yIntDel1 & wIntDel1;
delayer_i2 : delayer generic map (
delay => TREL1_LEN + TREL2_LEN
)
port map (
clk => clk,
rst => rst,
d => tmp8,
q => tmp9
);
aDel3 <= tmp9(SIG_WIDTH * 6 - 1 downto SIG_WIDTH * 5);
bDel3 <= tmp9(SIG_WIDTH * 5 - 1 downto SIG_WIDTH * 4);
yDel3 <= tmp9(SIG_WIDTH * 4 - 1 downto SIG_WIDTH * 3);
wDel3 <= tmp9(SIG_WIDTH * 3 - 1 downto SIG_WIDTH * 2);
yIntDel3 <= tmp9(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1);
wIntDel3 <= tmp9(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0);
tmp10 <= aDel3 & bDel3 & yDel3 & wDel3 & yIntDel3 & wIntDel3 & yIntDel4 & wIntDel4;
delayer_i3 : delayer generic map (
delay => FRSIZE
)
port map (
clk => clk,
rst => rst,
d => tmp10,
q => tmp11
);
aDel <= tmp11(SIG_WIDTH * 8 - 1 downto SIG_WIDTH * 7);
bDel <= tmp11(SIG_WIDTH * 7 - 1 downto SIG_WIDTH * 6);
yDel <= tmp11(SIG_WIDTH * 6 - 1 downto SIG_WIDTH * 5);
wDel <= tmp11(SIG_WIDTH * 5 - 1 downto SIG_WIDTH * 4);
yIntDel4 <= tmp11(SIG_WIDTH * 4 - 1 downto SIG_WIDTH * 3);
wIntDel4 <= tmp11(SIG_WIDTH * 3 - 1 downto SIG_WIDTH * 2);
yIntDel <= tmp11(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1);
wIntDel <= tmp11(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0);
end;
| gpl-3.0 | e8e8a03191154803dc05f78b1b92c598 | 0.474445 | 3.451602 | false | false | false | false |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/demo_tb/tb_lp_FIR.vhd | 1 | 10,412 | --------------------------------------------------------------------------------
-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Description:
-- This is an example testbench for the FIR Compiler IP core.
-- The testbench has been generated by Vivado to accompany the IP core
-- instance you have generated.
--
-- This testbench is for demonstration purposes only. See note below for
-- instructions on how to use it with your core.
--
-- See the FIR Compiler product guide for further information
-- about this core.
--
--------------------------------------------------------------------------------
-- Using this testbench
--
-- This testbench instantiates your generated FIR Compiler core
-- instance named "lp_FIR".
--
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
-- documentation for details.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_lp_FIR is
end tb_lp_FIR;
architecture tb of tb_lp_FIR is
-----------------------------------------------------------------------
-- Timing constants
-----------------------------------------------------------------------
constant CLOCK_PERIOD : time := 100 ns;
constant T_HOLD : time := 10 ns;
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
-----------------------------------------------------------------------
-- DUT signals
-----------------------------------------------------------------------
-- General signals
signal aclk : std_logic := '0'; -- the master clock
-- Data slave channel signals
signal s_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal s_axis_data_tready : std_logic := '1'; -- slave is ready
signal s_axis_data_tdata : std_logic_vector(23 downto 0) := (others => '0'); -- data payload
-- Data master channel signals
signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal m_axis_data_tdata : std_logic_vector(23 downto 0) := (others => '0'); -- data payload
-----------------------------------------------------------------------
-- Aliases for AXI channel TDATA and TUSER fields
-- These are a convenience for viewing data in a simulator waveform viewer.
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
-- to prevent the simulator optimizing away these signals.
-----------------------------------------------------------------------
-- Data slave channel alias signals
signal s_axis_data_tdata_data : std_logic_vector(21 downto 0) := (others => '0');
-- Data master channel alias signals
signal m_axis_data_tdata_data : std_logic_vector(21 downto 0) := (others => '0');
begin
-----------------------------------------------------------------------
-- Instantiate the DUT
-----------------------------------------------------------------------
dut : entity work.lp_FIR
port map (
aclk => aclk,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tdata => s_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tdata => m_axis_data_tdata
);
-----------------------------------------------------------------------
-- Generate clock
-----------------------------------------------------------------------
clock_gen : process
begin
aclk <= '0';
wait for CLOCK_PERIOD;
loop
aclk <= '0';
wait for CLOCK_PERIOD/2;
aclk <= '1';
wait for CLOCK_PERIOD/2;
end loop;
end process clock_gen;
-----------------------------------------------------------------------
-- Generate inputs
-----------------------------------------------------------------------
stimuli : process
-- Procedure to drive a number of input samples with specific data
-- data is the data value to drive on the tdata signal
-- samples is the number of zero-data input samples to drive
procedure drive_data ( data : std_logic_vector(23 downto 0);
samples : natural := 1 ) is
variable ip_count : integer := 0;
begin
ip_count := 0;
loop
s_axis_data_tvalid <= '1';
s_axis_data_tdata <= data;
loop
wait until rising_edge(aclk);
exit when s_axis_data_tready = '1';
end loop;
ip_count := ip_count + 1;
wait for T_HOLD;
-- Input rate is 1 input each 32 clock cycles: drive valid inputs at this rate
s_axis_data_tvalid <= '0';
wait for CLOCK_PERIOD * 31;
exit when ip_count >= samples;
end loop;
end procedure drive_data;
-- Procedure to drive a number of zero-data input samples
-- samples is the number of zero-data input samples to drive
procedure drive_zeros ( samples : natural := 1 ) is
begin
drive_data((others => '0'), samples);
end procedure drive_zeros;
-- Procedure to drive an impulse and let the impulse response emerge on the data master channel
-- samples is the number of input samples to drive; default is enough for impulse response output to emerge
procedure drive_impulse ( samples : natural := 168 ) is
variable impulse : std_logic_vector(23 downto 0);
begin
impulse := (others => '0'); -- initialize unused bits to zero
impulse(21 downto 0) := "0100000000000000000000";
drive_data(impulse);
if samples > 1 then
drive_zeros(samples-1);
end if;
end procedure drive_impulse;
begin
-- Drive inputs T_HOLD time after rising edge of clock
wait until rising_edge(aclk);
wait for T_HOLD;
-- Drive a single impulse and let the impulse response emerge
drive_impulse;
-- Drive another impulse, during which demonstrate use and effect of AXI handshaking signals
drive_impulse(2); -- start of impulse; data is now zero
s_axis_data_tvalid <= '0';
wait for CLOCK_PERIOD * 160; -- provide no data for 5 input samples worth
drive_zeros(2); -- 2 normal input samples
s_axis_data_tvalid <= '1';
wait for CLOCK_PERIOD * 160; -- provide data as fast as the core can accept it for 5 input samples worth
drive_zeros(159); -- back to normal operation
-- End of test
report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
wait;
end process stimuli;
-----------------------------------------------------------------------
-- Check outputs
-----------------------------------------------------------------------
check_outputs : process
variable check_ok : boolean := true;
begin
-- Check outputs T_STROBE time after rising edge of clock
wait until rising_edge(aclk);
wait for T_STROBE;
-- Do not check the output payload values, as this requires the behavioral model
-- which would make this demonstration testbench unwieldy.
-- Instead, check the protocol of the master DATA channel:
-- check that the payload is valid (not X) when TVALID is high
if m_axis_data_tvalid = '1' then
if is_x(m_axis_data_tdata) then
report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
check_ok := false;
end if;
end if;
assert check_ok
report "ERROR: terminating test with failures." severity failure;
end process check_outputs;
-----------------------------------------------------------------------
-- Assign TDATA / TUSER fields to aliases, for easy simulator waveform viewing
-----------------------------------------------------------------------
-- Data slave channel alias signals
s_axis_data_tdata_data <= s_axis_data_tdata(21 downto 0);
-- Data master channel alias signals: update these only when they are valid
m_axis_data_tdata_data <= m_axis_data_tdata(21 downto 0) when m_axis_data_tvalid = '1';
end tb;
| mit | 605428fe4bf2fe5c5ab3499baa97d49e | 0.573089 | 4.769583 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/ramfifo/rd_bin_cntr.vhd | 2 | 13,156 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
pPl+03jlK10cCBV1V4N4IryO2Uh615S9HgQ2EwCvejDrNilbqYF7JR0Hwdh9/DdiAkevxVe5a8tf
EOKqPEuUtA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Q5pB/hx2KeGwnwKAjjNaN3rV6sGRarY5tHDT5DVK/uXpwbolqWwWoa6IHGUQDK9Jkb75Ng84eHWe
aeO1DPKHGa0klvHJtAaiJuA46NR/WWLGlvDzne1oRbV2i4z4aCqiDXKUsFbInPfasDLk+QbjJJzx
Fc38NR39dVGIdx5hfD0=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
MleU/+kC2BoSeZXTE4/XxID+Ls9qAvG3aiAUn1/gqYiT4tVSJzGWuw3CZfMxsUSJjb0an5XXMd+7
MXYX7Ph6x0210BmCxIRUpA17ybQaxnE226i6/3SR3afCUZXwhdq7uaKhRAq9DhzZ9L5Xht4Qyg//
l9wda13tSFG7cNiRLzvIDThBWNvYHXG2481Glx7R/iqyGAeuknvV1T2Hk5R1Zm/wUodJgVg/UBv2
yL73jfzPOWRIzj9VDFQqL6LzwQwzLN7rbFUVmdOCgopYk1+R562Sf8ndaY25XLSqefvjwPw/EPo6
AeLooPL2vKFYqx5v3An3cTQjRAUHOah/sQ+jJA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
wZl7yn+xQz8zAzQ/uf4Mk/+9OA0tvBViExyWlhFv0xoAfqo47bQJW9aD0jxv0ALkhfD8x/yzOh/U
qLtt60ShAU1CI1yJPcNpq7msABO80JOMSrwlgr8jh9BGOvQ7yiIvnfz1v8hcztWQnZ2U2wV/nJKx
/izcGvV+zZ0fRTGTIsM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
l1UrCVHRrpvp6/+Exf0nwdQwIqiDqzc8p3g/SKIY+2/ZGwVjThOqO2AEbJfvgF06gre+CeSkcFfE
SCYLeUMTpdXF0bEmOJ7uAIwsjrljVBFx/OHLpZ5FJmk0CE8Yl2IaR3nrvQnwG+qK0HSNdoNweJWv
bBlljHcYwLBMGrVHge9iXE81MC4Y3q8U7nYlAgudrrsy7k1Ca9yH4kRPltNVdQrE8Vz1dWwjvc44
mt4nqhfqg/KXGv7ViFpCZaqMR7faUpd78Sfuimjpnkal0RHG2fVhfSG9na/45xBGMN5T1Q11tA39
GIu2APVfqBoWlEJEFhxu+Jf8DYYCn6Y379tZKQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8000)
`protect data_block
t4qyAmrBqJmzAz7xHeg7QBjUypSOb+6LdEIHX4Wkaz3f60CGwd4y1W3+kOeVshGZ9uFXEuVqr2cB
ZfElaywlTDqwzmuox2DF98c3EFUZfh+zMl5b7qt/ThIntNrsqhoHjw/FzVZjMLBkqvWREilFdlm9
7HnyPVthFECCbVzjfPoPOFNepTUxb4/ASlr5lyib5qfwJF4W0OboojimBiA7WflUniJ2f7estetq
ZxSr05h1ouHTr4o1OAp5DdUFjzl1jpqwLPVKuoV18zH4/MFFYqlC10OOqOQKGPRY1BwBndKXpxmd
YkhV1rmzyjRIWeWvnbew74+Rwagrcp22LWfrvQLXu2WzuBGCw3cciW71gQnDhdFNkKPwNw2GzU0b
HJjxMVAcVMeMcrVFlcZlIy1+XuuR2Xt0dveJ+HtJbqZ20MmRsUMvpqPkuMdkZV7nNugHTHjZRkQr
tw/J1VwxxtSbBEOdyMY/6qFSzoOAwMna1/U3j84gSYpdPjVJZk+xFzDNyZsZpBGkU6JXUjVvycHS
K5TEyLqZtbBTZPTero66+r4gF0rg5Bn93GTy0HhbR/gKnQxdoIKCJ4IBIiFGfFKxFzNVW8wwj//V
eaknnW7R1fUxMdgBF0RA1IW81YsRQWrqsFMC6UH1sXzx8gitu5F0UTbR0Wpx414xdbfqZRPhrKQi
nNvZDapCBuC+fKS8nI5HTV2nGkIPsk3oACtekW5KRnBPR/wdYj5a65Es2bzZCrTol5TndUsr6mPv
Wr5Nq26rIXEQRUphb/sCGtOqW5PvRz52LNyS79yaf0qsiPeanpk1J/Q0qY7dUrBFm2cMpWe3UeRX
fuesmZGH8g6W6ek+B+YX+H9xJiH2FhckO4wd2tdnvKRoU0Im9PQdt7nmKhcSwZ+CKssnNv5g8DJg
uzkGY+EtPv8f87RMx0hKEpCAt+rKyCLkqEZaV7D/wWx1F9LITAny4MO+Pi+lgTC//aYI+dKaudcF
8O4Mx3I2zVjmPojkdqECWN3Xc2S8EQGDmP8SVGc1+ISuZZraFeVFRXT74ALAFrloMeyeL6npUt89
XGYpr2DO2GQY/hBunYCdOTTTxEKAOYlE5OJ2txepZU7Okp4xg0uFMAsD3HsPm3ZDiXCgo6TtFHzA
wGsH5cVNaoWNwLRDIrZr/yvY2qsOYc3Kt/k8CeLDoZ645Xd3I0DOE3fEfrk+PWtvfSO6GWS7be9g
vU94g6h+HbZ6VXg1O6SITeluIwuzPImUAG+NvEhKXU06MgN7/mHZWBQC36/mPCJqTY66mSOUFIZ6
i7Tu/S03R329WAFPABpkW7sQwlA8q2HDhGsfPStfsg4Xz3AZWmjSaY/QgPuVUh1uXcxP9y3C/B5G
L+em9Mh+R949mOW/0v2sJKXnKki2XBYjX0ZnxCn+77TWevI00rjs4zQFGI2h8DhS9wve8AqVP9+w
tTn8mDac4HZEHpHSPRV3BC2aOw/2dQcaw2J7HnP/4AkhS72rN9JT1J14jzEvJozOnLk6+0FKbn3x
j07TGwotqAReHWQiIFtyjKA+YXWKhyg7ab0BzyKuiYJ6qfI8ugyxo6xFN/r7dOL6lF7d8iCvIGhc
2jHRQtpZzkJbibCHBMEaMnYeaKlkEwQWQl77+W2HGfG4gMERJu1BxTWaH2JjScfG3Q8Q6pt5RQs+
xKTNAdL/pBI6TES5nhGOBerHk7+lXkNzcccvAE7NwO+Pcu6trPGNc/BUjSzsh3ln8e1rX8aVyT2G
islYHehvvXKij0JgslkhUapgYGBUmSzOr9XSUs4V5+YdOiM4RP56q9IpYlf+a8NMRVnBeBs1LHDk
jG6Pm0WPEpl3M1bw0EUDPxhVkMB2oNl+uubAJLxTZXNJoAdk5JARctjfHdU3OmlfTwDOR+ZCtzgl
iiVkf4WFaRAYHrKGBYN+uALMnBl4jktM7W+fhRgdW2+Jv5WsAUoFAdlxGzE8xaHYU2fsbRn14wHt
Q52yAqDK/y4OLn46Mqmj8dDlxc8/ircSmVxUIa+FV6BrEqs5TrUgY9Hbr7EAbF7IJST1rbbC1dj8
i2rB/4nvQH+SY5bUaQrGLXpmkmHRu9vDt2vWc+Dv38h9w5styXTTH+1XoBvpaZPCqrpfO/ZPLkPf
X9hpydn5R479ACD+QmhtnuFC5FWOKLlgHU4bYRPeU+ACVZvNdigCmEtOlKRjq6uCx0Ej23AYEm2R
4KHQNFwQGsVyMDoLGKDBTy0kzQPbOwh43UYH1Cd0TyHycpoXZW9j3DTA+WE9HVGMiL+6d0L9k5Ih
1yS+AzLNW93q3LwfBpk0DMFT1DCJz31lb0d8MA5IbTpiRqlgmC9DatnSsiqq5Zy0g5lmpIrvt0QA
p3EckMG69CSHOmHd1OI+eA8PeOfK9xtGRR6EI2NZHv6qO+lmKHAgZCA3Iuz0/DCe1PW0nqdRYsRc
W1xAK1oN4o4szcYL+81A4Wlrqo3GxRcsXS7xoC+ACtKKoR9CqFXFQSdBTRBd2MP4hPsUt2JJDMg0
DIZTbVuu3ZpzpMvcyZppO5hXl/eAh0TBBfHn69yYRC0oW4WxHU7Xtnpik/60KLd2hWmaTzJxtY5B
kHslhJUtF4uq6dQpyAgzALKgbOzhOHX8qWhVKFxHsfCQw8ZpfRel8aaqZm2qtP6IFhJ6vrjOs6IN
Cj3UlZKrOj+GbmWHTjjy3Or4ZJ7Z8HQk1OslEdYerandBIdHWXwiETjfY+mDRPb5986nvKV74GqC
MDwvDtuFN9QNDDrRStW2j4g4JFkGN7tdFOmjBCmpFZU+Z8IQDQJWXwMx5eC700/Z70nC/GDobLwx
JXHPolh7Gx6dBgWRWWeGF0Mh/6+jOMV+8cvAYGWPSBwxxbhvo8S6PBp26Ob5ucBJ9m34nmlsFwit
VuiuZLxYCGDIgxLMpjQ/dIRxsegG8DIlAqvrSDmeGF0gTkVGh0LPjC9rTvPiv0XAuMJCJNFqp6Tc
GwuT+Gbm9bYWA7ZSzvg9OQA+/vvgRm9peIQMWNcqESGwlpF4WJQrD8/xNP264DcZtp7HAwyQUK52
qw9r9WExA1bydUyraO0sN5uMuT1naw1bPIFxJ61oPYZ3e907roOC31ls0Jh1IrTNPZysU610N5Yg
vzxbtDJrLLXQcPJG3C/zYUH28DVRtR0mPT/c97X/FF9pk7gKf1PdI2F9xF86kONujYePFJ+SLIAb
b1ECRNtYPuvncrcWC49DX0ZFziII2eG4bvTauwxcfUO0+cUS7TYMVRBxBsdxd+d86weMhueD60sw
q4vW87urpqVkM26BjZhBaQBnmpn0AqI0O6AliDWFCX32dfphe0JvuKcrFioLVFqp+Wm6MGKDJH2t
/5NTmG4v1wTFCb2gWT20/epznFGrqCiC9khoxJyK/gqFtI+bQDYMRqKsHfJxjnB/b0hccU9qcsPP
5IltvfvyoaIoz4GFGFVVrr/ilevyOwRzx2S62bsaqsjzgQ4KKP8OXMIg2tRUvhHyo1sFTe9M09zA
lhb4MOaB1q7K7n0+jxPrqUE4Bto5kYyd26GLWuXSgnZmxm0ADmQMzHJDr+0EOL8RADzWmaGuT/HH
7SHhXickxw83yAyNSyoQnpwMlcCFay82aNGAowYmKTUfN8vNe/6Pj26fZYkmDLme47b6SFAqb3/h
Q3xbi5ezRMrKNJP96JTP6SQuiSPLOcY07ZSEgslgND601qiws9mo46QPASnEGSsxy65n6Tw2hAuA
ZtnkdmoJu9tlmRR02KNEN0JAjs3/tV7aGZUIhAtbqM91CGxk8qUM0FZrQUDAz5cd6wY+r2kFapE0
M1Wi43fofdey/c2nEWyLxxKXKI1LLMADJeM8ho4oXusdL69aZAoWOQX01C+4pwm92JJ9UyyJupnk
qGK4D+6oSt0h0eimSmZmwJXscTbUksvMHVyFyVliTS9s5OijAHFnghN/4oY+BikotAmxq9V0Pf/g
DrVgQNppULHWim0G6nWYkZmFqbPab59ebIdyusb/9eQxvlpRKaviorhdnki3m35x9FVynrfACGE3
wnDyDgB3U1M2fjWPyZXigxqd4kBEidZUAVyuAbRlAqvRmEDBGZJbf2zVZ2FfyvIJVcxujFd5FNLY
nCxPVf675JrKHkA8K5OfN/jqUxMEQEWcwLdqRwU4gvX+/ksVf16N0cOdra01xgq8pYlpv3HjiT7h
9O4nZjm8DCxfUjq2NcBMW1SuuLzu/4/aFAiMFSruD49dUEvkO5QC+GlAgR4o3pQcqcU/5rxzvJ5v
w23V0vH28cmhGWPSKYIaAPhrZjaIq5jpzM3qBvhl3PNv7KDaobqONh9CWabiQhJDxBBEmz7sJzpO
8pRWeVfFJ0kWWAjzyR+ZDtTciDKo7r12JJfMD/cYHoFF+/CTS0/i0cypf1RkY8ppU7DlarsJTjQZ
0N+LrxxVt9sJ0WKB8McIlnpUbeAiyUxCKmwE6sjjZ1lf8wOfaaSDwgBPEoBa+2aKK/LyE+xkZkg5
gZ3APbUpdJLTQ0D6UPrUQEUQjZS8sp4BgpeUCES2vqzMRUSN1kpFXkgbSENIQl8h7RQUXp4AP/il
T6Bfh22FVEva5HtHcbM3ufCLQzJQL+k5gRJ8iRYmcikCENHzJDDoWx7Vd33DESfX2bqnVY+edMd9
HzedzuYK4+ZcihWVq3WQeyczKk+VgvqYcqZBWaR6wwbDrj7tSIkq2lq4HVhsnxaPp5cBcFKPi+8g
//HDPHBsOAct0ov0dfyQdYJozag9y/GX88wa8EM+Rluh94aGXWNk0PvXauQHnuwWw17jetbnWlaa
XMgmdGpUJGsMqwA7R3MAO8UcgKhfx2Ghp6ucnjiI0z/12//yA+lBIbw1gVO4dnI3qnlgOImglM+g
y3OIPHq7i55a4ji2SV3hSa78ifbgsrta0sD4YaRjPJAUJ5n4ld7NdDRibMu68ND2Tmm/EnwbB+Fc
Sze2UhWle51NmhsnyFNIGo2yHC9f623gKxXEMxZb3F0rlBO4nqYi3PF/LctSfyDJ6NHLbHQlOVFx
a8VItcNBS/ZJLssEaH92h0T4Q73M0gm2jkwpqe5WikYch/7cWpUCZ/EhFeNtdJnm950fVhZmecPi
/6g53lEz5Gxc81AtGh3uxLr0h+3RtIJhQf+7pZcmgm9bOBiyUajPz9mO450uBpu8Y5XvnfHHBLX8
Z+6jOmigm2i7ZXeuuPr8H+VTwDfukvhXRZ0f+iHS3EMJ3gKztZFNy8ijTBozBVUvfqKHgZp4sDVg
R2EJed2opo9+AfvJGumn0AL93HYwl9Q9wjDIST+VC3HOPh2IkgFSkLtjLSlSeQLteaYqU+qKk0Ul
CBx2/nDk07L1EPGhluM38F2oduqSaKejC1U1Ol+CJWuprH7j2bnafUtndS0Y4lBLDLRukWaGyMp1
yU2jYAwAniLNidXD2+NjexS/+HgVl0Jae3toHCRNIu9M510n4xzKhr+2/R/pWAqnPYDBCDBhri2l
3Z8qapGWrkBYZyZoZ0ZHR2GM3Q6i+XlHUDjhtuCKrMWHXWAv8A0St9R/ViuIv8vZ6BmLGK5+xDQR
GwMn90FQkCzQPtrlnT8ectEAMDk0OWNGbO97VY3CnMLH+pBifcGoCK8UHzxw57gTo/9X0hr67v9R
bmtbIBCwaGxXTnFJF7cS46pi0ahu2GM7H93Ne1oRJ+Dsi8P2gDBjNu4MB8/fBjO2z5EVLQT7MyA+
vIkkPetzWwtlTYzqo/fou5xnKAmhkia00cy5sjuy60Qcf75AD9p/OPiW4V6zk65T1k8n5NWNrR60
8PI0gWSkKJz7KFGSDPAYeyde74Kd/NzQ/c2ggdQFQH2jc4OjVWmbfr3v03umSlNdq+NcgXIqJxip
kNXHT5N/pG2oVGRuhyRENNZked8BIcVCacf8CMPb/dLsL1RuVYLyli7qioUbmF2Pcc11OczuciLk
ejHDN55bG/dNRUgC0wGxw365WiGn1p7/4pxM323cbouJGBN+1fXTd/lMQtMmjMKVjYK86+UaoE6K
BiTYVhMr3Yguh5wrjwzGzdzuw2gt7GhG2fjd0F0vbny8czQudmXJCKuQMpXt2FcmbxOgMP5F7Xyy
gT1bdcZSDIDE4DRvWeuRXHc+xv+69N/DqbChpn3T10YJ7/unwO2q8+IcS7ySNqchxBxnoCd7S/EP
qjmocE+jmxZhx9OnPBDRRbSOyeP22jVjeNvnTNzXTPit4uft0y1TfHMV4NzUJns6jRr8iXE8CeT5
fm0ZmJnJvq4xOE6fRuARRKPtScfKxXW0gck6Y+AGBOmcGkOh5UZcfU5W8vicG8wIODYmidWe/4Mr
lvnhJiZfyljdBYSe2fsrVqy/S36l2sXc77IRT9mJzuy95J8lV+s2hvRARNWRlegeq0VCJpK8COGy
qISkJMQpKyRhtvWtdiAFzt3ubuh6yjlEmSvT2WhlkI61ud+FjuTMLa9D04rGphLBhsEIC7Hsgmsi
+6up+rA15TvpcycW9gayCQ7SvMU0/TEvbtgAcYxJ5hDn0OeMuMsaoWkM/KV3bHJ3WeQauwYYbWCy
QjRL1AudZI8WAQ8dz6vWWsFkWGkTIsTXwKQCHZnoGeZPwNqbjOThrxG2kgQTfVHmKTvloorGZRfv
ooRZ9S/AxWzfZ8UrkpKBnGmaBZi8HCTFoY2l/fbBHrT+i2i/TQeKeKx1LSKb0zFzdY9M0URWV1op
zE+6bGDHdtF1jqzoD5uE6qsnXxKXPIjx+ZuEpaVHmePD88OjzbDEGLuSqjAYtoNdRkUQKrKwIMRT
t4k+osjqsG3bvfoiK9YsSsgjrf6c5F3W7lxal8plL4JkBdQVS/Rr14dX0kmgziEkIVDx1sNw+tNj
sQevvemIBFwdL5qPhkxXASKs2mMbx8l/PhQiFvfN1kguK4aEil3xuRPhIITrVaV1vQkqvZrLynHs
sS/INh5WAKg5yq6aoeI63zHxjbJNpnJ8M8SNOdCW/iLsgE8KF0PBnE0MEhijlDGKJSUafycA9J6/
TNiE2T8Qu6zFjBCIEYCrmgwpt8U1eXomKisNIClJfkSFcTGvJuGSNyQff1XBJYQ/vRltfCzKtjtP
vy7qPgYnWV0ajNrG5+Bk0zY0zLovYNZnJHYtyEUG7gld7tl2/CbWHiPL9EjLXPdMzT5e6RwDEw7x
NvgPQhmgLHxUAAPcfxG+KdQocygGBuNUiCwKoQISz7af3NgliUOPYkAhDuY7yr4KWUP6kMHhRkQk
iq9aEedLZidWZOTKPYAL8/z911o4/KlKXOZy+uwthePrCm3q+WABV2fsAeWpCHBwy5SutYVgcbzF
MP/hcG2rParlIlV8ESWqPS+sQKWTuCgpIqh4hqkTfqvBbTChGO7wHFnaOgbDDd3Hcu0/VZaHdoaM
mnTUqfgHHdXZptGc23xqqw2IVGGVTY3OInwN+kEOroBNxgFjZn8aItL2JIzu7iHuLZ6RbQP0SkH2
XowUUCQNkxDzTgQIBZ6KrManL/XWm91Gep6Au31JXYBJQ6i7pMcZBgksTYiYGvZGjQnBh5Z4GZJW
X3hGUVQz/BwcQhvib7CyzQ9cTBZNxFifxG37kr06OCWyAPyk/yw7LcOlbkPpNeyKvyaXLYxSELqn
Q1n5dWDsL544xhH4Y6EwzJly2suuuvvlyFMu4rmytI+rCGnrooDbrcWg23cX7z4DGEMzh2w/7iur
Z/ZMRLBGU+gGc6lGytr15tUzftrFIWDShmF8H/Y5/IcghpgJgXGaP4bpU8dn3cmfREbrEibcdKRZ
bknVEwjNzIwdx/nadYU+odrDTEJwcruHFhST3hMPujAFIzGkzm4VMvZTg6MgrmElEABa72795GPC
caqRGHUseILNbKACqOUamKeu3lBK9YNeuIB/b0jygki7l9X+ApXPI8IlrSgj+deSwzutGM/ohKNP
Xgu9tY+ijuoY0voZ3WDICxfw9SPUpqgz6d9L0gS149cnkkUb24nY6d67wFSq9RKPFCG3QP6yzROP
fF+D3DB19m+oOfkGo1LasFAW2uCKspwY+NQhKA6qp+82QfcaOvfXCT3rcl1WGnq+e2AHHcaIE7y7
kpVwE8jWiFIgPCAh6cjNOo4CC7FBxo1vUEMPPZVsycTvR4JRDfbiLG9uXZaiAxYyGbjCXLswyPiR
hWaW3v4h62qFeUzvPcDKtKRTTZyj/18dIh2ZA7Mghu+ZCg43lYuF/t9RgsauJG3h2cBKnCblsW2G
NJH3Ai81tGUU4vkBMaltd5CetamJQLi1ZPTtQXFkImKOvY+ZlJEu50/mih6c5CGk4OyDrBozb4MO
HLzzGWsWZZZ9USh4Ww8fnHJ3r4sAxekNZvTy/JjGTgWL2QtsKtP899JLEJtRIXB9ROw6APEJQuSd
IC1MxHmTzIT0fLkXPhQksyuYfBuhRGNfeqm3g82HpjdraFEdWi05rpY6mpUe0z3kg60RCoPBwvf0
Nf3jpqFVFrnHGjWQLB8uS6mebuwtDqyTdPfbMFD4KIcfgRvqV68OoiMBZ0iMjruGVVdeMJhThQgw
zKXQ+tJP0m693QV58kRs1PM43eHAc2SOthiZOoRqpZyrOofqiYEhQzVq6fvSWMN0DPdIzbFu3kox
13rEYafnWTbaNdd4SC+rMphbnn4ZWOZqsk19mnax2s53YlglQvKhXPCJOy8WjccnyUUTME7AdC3z
r4CKIo16VSuS9p07ihpDYI4TrfHHxLlmKcuC36aQpXn5MLe0JoKHVRwGughjUwJPjjOqjWUl2xHF
1eFGbcSag/667k1IznEdwuvHEtU1ER7N82wMmuDkvK/eZwmhl9YiEfuuGz9E49A1vYFwbJHXNE3y
m/NfJ9RbGOp3FIhVWRn5o7+bK/G5bTtlIi/BvJQKXwPG22Opm41hf8v6ekWNDEpRg+r4MFTJUsEp
J3dBdoxhWWX9hbMTSsRm72JWSVObyoTsykixKiZwcyg4ovxhH63oOd0h6HJygYNet8NfZt/h+gpy
dMyheIoRunZywfgiN0pPn8YIcz7zQaPJ21MdsVTWojfedd/voSmXf1QX7vkCqnEQca15yzJsOmZG
9gr/VkI1AbfGa+APhPvR0IX+7cZWPY5pbwutzZgT5Xpm1h6kmW5Fvgwa/LDUsZYi5VaDzCvV4imA
SsptmDSA/31Efi6/HXvqoP8Vk2V4mmw6sxOMUSzHDCFjekfPsL6zfVRo6k952ZLZs0MixT3CjldZ
BmnKTNyNLDmtTmNIdNWdCUbnKXUSXvbbpJvfJJGr8fQc/eboxbjBlUz0sdh33/3xGfZY47giwnKi
8yH4mxNKks/VzxR+ZisTjQFCQxPe7an2gALFwz+hK4DCkKJ5LMPHJycpKoW+M2UiqX3fBHoCKfzL
/XpaMAHabjTSf9PROlJsvojJj5vT2e1R8Gz6fgCHO40LdGLW9btgAX1wAtXIP2TJ9eAIq41WOhDu
a4jFhHYtR+eCXuI6OVl4HPcKGv0Lh646wyRgnlb54tTU7GtP6veL6NWOSICYxZre3mKQkDzgU8ps
jRBZoE8tHNt9L6kG2WY2MOxH+AgqPBJmm9zpzGTckkXETf0VOnb3zAGueI/5neH+ukYn1O+0fbtP
ToLQfRr75efSAhP/NM34xYZA8YC67BtJ/SvybeTm52IIAani2oM3HwcQq8RHQI7Q6szlfoZ3HajI
Dj4tf9B+D5f5XKqonLTcCe+lYPcjcERZzDNitdae54g8JrXl/g4mGjJZeDkCgbruFmaWoZg27kcN
vVqWuv2eOM73QyaEYJVbFzTqYwY5Io6aM4kQ8j/dP5WgO0y1PvkDNo/Xk5tqWElr3bCwFlpkHv7V
8UwGf1lbeaxzTxWIvGHCpTzsSAPvMGCmXPOqiF0PmgNDvNoGf3E8rEblYrrRHhCBb7iLI1oN1GJE
beOEy3YizmN+xpErMvGfM5MhHjhyxz3Lxnq86HOaMfZTGpedx8Joj9JYNyFSyqBQkEl5kddPVBpC
VDjbgtAxvuMPUUdulBuxroi4JrzJcO4guUouuzFvizJdQ+xCn9YF4DY01RC6cpylkpkjRNPqPzNE
Fz5T/kXeigSMaDlAH+lbK/ATdH1kXIRJSoAXJuco9KvUg52azeKqhj/ZQ4l+wcqrzoUavmsvPX7J
nEYKEvSCpapRDhzbCP8h4pxcNB679PE8S349T9NmDyxhLDC2XlAjXG174ctTFs4CxfCt5+XA7GHh
5TNbdCCZElKCDVdyb5TjZd/JEXW0tR0xpjrUtqhbwAa0LsHbavWNCKyfcIzYAfh6Wz6ZPwuMhhWw
3kcTHf4+G8Z05VVWAirI/C/8cMhY6sGfYFd9B4++k38+thKSnN792xq6Gxsjt/xVh9bWU0ZEXgIJ
nW4NcN85bU+pL+A5AAb/xSpLvng3pGP4MAJoBL5oM3iFr8dLZ/9ad31gt0tYlX/6AK6ge+x0LFF9
vAfuhYjcCATseLO1ttsHBbv2UhmbPcOGDtGURNmtDua6fh4NDz+6//ksq7PInlT922x2tG6KNoDV
zTFRNKzeQKYYr3+o4BUSQYzw7dbyLc2tSuksLq85ZYgNd012B49Vt4tMEx4hx//aTwTmsOi1RtmS
sIoIPA4ZQ7/W76sDYMJG/YMHOamSz2jpJWuO3nv4wUMP2ZMQF6qLQ86MWX619/QJjwAFxVM2t42N
cucaAmBDXv3mgvBERp4ucJOSjmM=
`protect end_protected
| bsd-2-clause | e4c4bcb14130108a33f59c96c2786bd7 | 0.93121 | 1.898413 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/styles/jcl/alignments.fixed.vhd | 1 | 1,451 |
package body my_pkg is
procedure some_proc (
a : integer;
b : integer
) is
constant some_const : integer_vector :=
some_proc(
arg1, arg2, arg3, arg4,
arg5, arg6, arg7
);
variable a, b, c, d, e, f, g : integer;
constant some_const : integer_vector :=
some_proc(
arg1, arg2, arg3, arg4,
arg5, arg6, arg7
);
begin
some_var := other_proc(a, b, c
d, e, f, g, h
i, j, k, l, m
);
some_other_var := other_other_proc(z);
end procedure some_proc;
end package body my_pkg;
architecture ARCH of ENT is
begin
PROC_LABEL : process is
begin
var1 := 1;
sig1 <= 2 &
3 &
4;
sig2 <= 5;
sig3 <= 6;
end process PROC_LABEL;
PROC2_LABEL : process is
begin
if rising_edge(some_clk) then
a <= b;
end if;
end process PROC_LABEL;
end architecture ARCH;
| gpl-3.0 | e2d6e6ba74ea182d825d0d1dde6b4ead | 0.338387 | 4.952218 | false | false | false | false |
rjarzmik/mips_processor | Control/Bypass.vhd | 1 | 4,765 | -------------------------------------------------------------------------------
-- Title : Bypass future register writes to Decode stage
-- Project : Source files in two directories, custom library name, VHDL'87
-------------------------------------------------------------------------------
-- File : Bypass.vhd
-- Author : Robert Jarzmik <[email protected]>
-- Company :
-- Created : 2016-12-12
-- Last update: 2017-01-04
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Bypassing values before they are commited to register file
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-12-12 1.0 rj Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cpu_defs.all;
-------------------------------------------------------------------------------
entity Bypass is
generic (
NB_REGISTERS : positive
);
port (
clk : in std_logic;
rst : in std_logic;
-- Inputs
--- Bypass sources
signal i_ex2mem_reg1 : in register_port_type;
signal i_ex2mem_reg2 : in register_port_type;
signal i_mem2m1_reg1 : in register_port_type;
signal i_mem2m1_reg2 : in register_port_type;
signal i_m12m2_reg1 : in register_port_type;
signal i_m12m2_reg2 : in register_port_type;
signal i_mem2wb_reg1 : in register_port_type;
signal i_mem2wb_reg2 : in register_port_type;
signal i_wb2di_reg1 : in register_port_type;
signal i_wb2di_reg2 : in register_port_type;
--- Bypass register targets
signal i_src_reg1_idx : in natural range 0 to NB_REGISTERS - 1;
signal i_src_reg2_idx : in natural range 0 to NB_REGISTERS - 1;
-- Outputs
signal o_reg1 : out register_port_type;
signal o_reg2 : out register_port_type
);
end entity Bypass;
-------------------------------------------------------------------------------
architecture rtl of Bypass is
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
constant NOT_FOUND_REG : register_port_type := (we => '0', idx => 0, data => (others => 'X'));
begin -- architecture rtl
o_reg1 <= i_ex2mem_reg1 when i_ex2mem_reg1.we = '1' and i_ex2mem_reg1.idx = i_src_reg1_idx else
i_ex2mem_reg2 when i_ex2mem_reg2.we = '1' and i_ex2mem_reg2.idx = i_src_reg1_idx else
i_mem2m1_reg1 when i_mem2m1_reg1.we = '1' and i_mem2m1_reg1.idx = i_src_reg1_idx else
i_mem2m1_reg2 when i_mem2m1_reg2.we = '1' and i_mem2m1_reg2.idx = i_src_reg1_idx else
i_m12m2_reg1 when i_m12m2_reg1.we = '1' and i_m12m2_reg1.idx = i_src_reg1_idx else
i_m12m2_reg2 when i_m12m2_reg2.we = '1' and i_m12m2_reg2.idx = i_src_reg1_idx else
i_mem2wb_reg1 when i_mem2wb_reg1.we = '1' and i_mem2wb_reg1.idx = i_src_reg1_idx else
i_mem2wb_reg2 when i_mem2wb_reg2.we = '1' and i_mem2wb_reg2.idx = i_src_reg1_idx else
i_wb2di_reg1 when i_wb2di_reg1.we = '1' and i_wb2di_reg1.idx = i_src_reg1_idx else
i_wb2di_reg1 when i_wb2di_reg1.we = '1' and i_wb2di_reg1.idx = i_src_reg1_idx else
NOT_FOUND_REG;
o_reg2 <= i_ex2mem_reg1 when i_ex2mem_reg1.we = '1' and i_ex2mem_reg1.idx = i_src_reg2_idx else
i_ex2mem_reg2 when i_ex2mem_reg2.we = '1' and i_ex2mem_reg2.idx = i_src_reg2_idx else
i_mem2m1_reg1 when i_mem2m1_reg1.we = '1' and i_mem2m1_reg1.idx = i_src_reg2_idx else
i_mem2m1_reg2 when i_mem2m1_reg2.we = '1' and i_mem2m1_reg2.idx = i_src_reg2_idx else
i_m12m2_reg1 when i_m12m2_reg1.we = '1' and i_m12m2_reg1.idx = i_src_reg2_idx else
i_m12m2_reg2 when i_m12m2_reg2.we = '1' and i_m12m2_reg2.idx = i_src_reg2_idx else
i_mem2wb_reg1 when i_mem2wb_reg1.we = '1' and i_mem2wb_reg1.idx = i_src_reg2_idx else
i_mem2wb_reg2 when i_mem2wb_reg2.we = '1' and i_mem2wb_reg2.idx = i_src_reg2_idx else
i_wb2di_reg1 when i_wb2di_reg1.we = '1' and i_wb2di_reg1.idx = i_src_reg2_idx else
i_wb2di_reg1 when i_wb2di_reg1.we = '1' and i_wb2di_reg1.idx = i_src_reg2_idx else
NOT_FOUND_REG;
end architecture rtl;
-------------------------------------------------------------------------------
| gpl-3.0 | 3545cde395de775b15e039ca40e4d1a5 | 0.50724 | 3.025397 | false | false | false | false |
rjarzmik/mips_processor | Caches/cache_data_mem.vhd | 1 | 4,233 | -------------------------------------------------------------------------------
-- Title : Cache content memory
-- Project : Source files in two directories, custom library name, VHDL'87
-------------------------------------------------------------------------------
-- File : cache_data_mem.vhd
-- Author : Robert Jarzmik <[email protected]>
-- Company :
-- Created : 2016-12-17
-- Last update: 2016-12-28
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-12-17 1.0 rj Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.cache_defs.all;
-------------------------------------------------------------------------------
entity cache_data_mem is
generic (
DEBUG : boolean := false
);
port (
clk : in std_logic;
-- Reader
i_raddr : in addr_t;
i_re : in std_logic;
i_rway : in natural range 0 to NB_WAYS - 1;
--- o_rdata = o_data_by_way(i_rway)
o_rdata : out data_t;
-- Writer
i_waddr : in addr_t;
i_wway : in way_selector_t; -- write way by way
i_wdata : in data_t
);
end entity cache_data_mem;
-------------------------------------------------------------------------------
architecture str of cache_data_mem is
constant data_one_nb_bits : natural := integer(ceil(log2(real(DATA_WIDTH / 8))));
constant data_line_nb_bits : natural := DATAS_PER_LINE_WIDTH;
constant data_set_nb_bits : natural := data_one_nb_bits + data_line_nb_bits;
constant index_nb_bits : natural := INDEX_WIDTH;
-- Entry anatomy, ie. entry for a given address index
--- entry [ [way_M-1_data] [way_M-2_data] ... [way_0_data] ]
--- way_X_data = cached data
subtype cache_entry_t is data_vector(0 to NB_WAYS - 1);
-- Tag Status Memories interface
subtype mem_addr_t is std_logic_vector(data_line_nb_bits + index_nb_bits - 1 downto 0);
subtype mem_entry_t is std_logic_vector(NB_WAYS * DATA_WIDTH - 1 downto 0);
signal mem_raddr : mem_addr_t;
signal mem_waddr : mem_addr_t;
signal mem_read_data : cache_entry_t := (others => (others => '0'));
signal mem_write_data : cache_entry_t := (others => (others => '0'));
signal mem_rren : way_selector_t := (others => '0');
signal mem_wren : way_selector_t := (others => '0');
function get_mem_addr(i_addr : addr_t) return mem_addr_t is
variable index : natural range 0 to NB_LINES - 1;
variable data_in_line : natural range 0 to DATAS_PER_LINE - 1;
begin
index := get_address_index(i_addr);
data_in_line := get_data_set_index(i_addr);
return std_logic_vector(to_unsigned(index, INDEX_WIDTH)) &
std_logic_vector(to_unsigned(data_in_line, DATAS_PER_LINE_WIDTH));
end function get_mem_addr;
begin -- architecture str
cd : for i in 0 to NB_WAYS - 1 generate
cdata : entity work.memory_cacheline_internal
generic map (
ADDR_WIDTH => index_nb_bits + data_line_nb_bits,
DEBUG_IDX => i,
DEBUG => DEBUG)
port map (
clock => clk,
rren => mem_rren(i),
raddr => mem_raddr,
waddr => mem_waddr,
data => mem_write_data(i),
wren => mem_wren(i),
q => mem_read_data(i));
end generate cd;
mem_raddr <= get_mem_addr(i_raddr);
mem_waddr <= get_mem_addr(i_waddr);
mem_rrens : for way in mem_rren'range generate
mem_rren(way) <= i_re;
end generate mem_rrens;
mem_wren <= i_wway;
o_rdata_mux : entity work.data_t_mux
generic map (NB => NB_WAYS)
port map (i_rway, mem_read_data, o_rdata);
memwdatas : for way in mem_write_data'range generate
mem_write_data(way) <= i_wdata;
end generate;
end architecture str;
-------------------------------------------------------------------------------
| gpl-3.0 | 407e6693ae6c64b6f47ae7310845dd96 | 0.509331 | 3.59949 | false | false | false | false |
NicoLedwith/Dr.AluOpysel | test/prog_rom.vhd | 1 | 19,877 | -----------------------------------------------------------------------------
-- Definition of a single port ROM for RATASM defined by prog_rom.psm
--
-- Generated by RATASM Assembler
--
-- Standard IEEE libraries
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
-----------------------------------------------------------------------------
entity prog_rom is
port ( ADDRESS : in std_logic_vector(9 downto 0);
INSTRUCTION : out std_logic_vector(17 downto 0);
CLK : in std_logic);
end prog_rom;
architecture low_level_definition of prog_rom is
-----------------------------------------------------------------------------
-- Attributes to define ROM contents during implementation synthesis.
-- The information is repeated in the generic map for functional simulation.
-----------------------------------------------------------------------------
attribute INIT_00 : string;
attribute INIT_01 : string;
attribute INIT_02 : string;
attribute INIT_03 : string;
attribute INIT_04 : string;
attribute INIT_05 : string;
attribute INIT_06 : string;
attribute INIT_07 : string;
attribute INIT_08 : string;
attribute INIT_09 : string;
attribute INIT_0A : string;
attribute INIT_0B : string;
attribute INIT_0C : string;
attribute INIT_0D : string;
attribute INIT_0E : string;
attribute INIT_0F : string;
attribute INIT_10 : string;
attribute INIT_11 : string;
attribute INIT_12 : string;
attribute INIT_13 : string;
attribute INIT_14 : string;
attribute INIT_15 : string;
attribute INIT_16 : string;
attribute INIT_17 : string;
attribute INIT_18 : string;
attribute INIT_19 : string;
attribute INIT_1A : string;
attribute INIT_1B : string;
attribute INIT_1C : string;
attribute INIT_1D : string;
attribute INIT_1E : string;
attribute INIT_1F : string;
attribute INIT_20 : string;
attribute INIT_21 : string;
attribute INIT_22 : string;
attribute INIT_23 : string;
attribute INIT_24 : string;
attribute INIT_25 : string;
attribute INIT_26 : string;
attribute INIT_27 : string;
attribute INIT_28 : string;
attribute INIT_29 : string;
attribute INIT_2A : string;
attribute INIT_2B : string;
attribute INIT_2C : string;
attribute INIT_2D : string;
attribute INIT_2E : string;
attribute INIT_2F : string;
attribute INIT_30 : string;
attribute INIT_31 : string;
attribute INIT_32 : string;
attribute INIT_33 : string;
attribute INIT_34 : string;
attribute INIT_35 : string;
attribute INIT_36 : string;
attribute INIT_37 : string;
attribute INIT_38 : string;
attribute INIT_39 : string;
attribute INIT_3A : string;
attribute INIT_3B : string;
attribute INIT_3C : string;
attribute INIT_3D : string;
attribute INIT_3E : string;
attribute INIT_3F : string;
attribute INITP_00 : string;
attribute INITP_01 : string;
attribute INITP_02 : string;
attribute INITP_03 : string;
attribute INITP_04 : string;
attribute INITP_05 : string;
attribute INITP_06 : string;
attribute INITP_07 : string;
----------------------------------------------------------------------
-- Attributes to define ROM contents during implementation synthesis.
----------------------------------------------------------------------
attribute INIT_00 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_01 of ram_1024_x_18 : label is "86B981F181098179A000871969276712680066C087C9663F68124D3967118779";
attribute INIT_02 of ram_1024_x_18 : label is "6712800287C966C0880148918002815187C966004899A178D301D201478980E8";
attribute INIT_03 of ram_1024_x_18 : label is "822B0D11800287C9680187C966C0680087C95341682687C96600524151396827";
attribute INIT_04 of ram_1024_x_18 : label is "823086B9842186B9831186B9828186B98779A0018002822882324D9082324D98";
attribute INIT_05 of ram_1024_x_18 : label is "690C671468088719690C670F68088719690C670A680887496914670A68086607";
attribute INIT_06 of ram_1024_x_18 : label is "670A681A87C967CA681987496911670D681D87496914670A6818660780028719";
attribute INIT_07 of ram_1024_x_18 : label is "87C96713681B87C96714681A87C96714681987C9670C681C87C9670B681B87C9";
attribute INIT_08 of ram_1024_x_18 : label is "87C9670B681087496914670A681587496914670A680F6607800287C96712681C";
attribute INIT_09 of ram_1024_x_18 : label is "681387C96710681387C9670F681287C9670E681287C9670D681187C9670C6811";
attribute INIT_0A of ram_1024_x_18 : label is "858987C9663F68124769CD014E69800287C96713681487C96712681487C96711";
attribute INIT_0B of ram_1024_x_18 : label is "6812670C8002858987C9663F681247698D014E69800287C96600681247718002";
attribute INIT_0C of ram_1024_x_18 : label is "85F185B186B98109854986B981098549800287C9660068126713800287C96600";
attribute INIT_0D of ram_1024_x_18 : label is "86D33C0086E3DB017B1FDC017CFFDD017DFFA00386B98109861985B186B98109";
attribute INIT_0E of ram_1024_x_18 : label is "6600800287534748870187C98901800287234848880187C98901800286C33D00";
attribute INIT_0F of ram_1024_x_18 : label is "2540A8090401041F053F454144398002878B0D1E8D0187196927680047696D00";
attribute INIT_10 of ram_1024_x_18 : label is "0000000000000000000000000000000080024692449045912580A82104018000";
attribute INIT_11 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_12 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_13 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_14 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_15 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_16 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_17 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_18 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_19 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_20 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_21 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_22 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_23 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_24 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_25 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_26 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_27 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_28 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_29 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_30 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_31 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_32 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_33 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_34 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_35 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_36 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_37 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_38 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_39 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3F of ram_1024_x_18 : label is "8640000000000000000000000000000000000000000000000000000000000000";
attribute INITP_00 of ram_1024_x_18 : label is "3CF3CF3CF3CFCFF4FCFCFCFF0000140034CF0CC3D38430A0004FF3CC00000000";
attribute INITP_01 of ram_1024_x_18 : label is "868138F3D089089222EED00000004FD3F43C84F10F213CF3CF3CF3CF3CFCFF4F";
attribute INITP_02 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000007F85";
attribute INITP_03 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_04 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_07 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
begin
----------------------------------------------------------------------
--Instantiate the Xilinx primitive for a block RAM
--INIT values repeated to define contents for functional simulation
----------------------------------------------------------------------
ram_1024_x_18: RAMB16_S18
--synthesitranslate_off
--INIT values repeated to define contents for functional simulation
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"86B981F181098179A000871969276712680066C087C9663F68124D3967118779",
INIT_02 => X"6712800287C966C0880148918002815187C966004899A178D301D201478980E8",
INIT_03 => X"822B0D11800287C9680187C966C0680087C95341682687C96600524151396827",
INIT_04 => X"823086B9842186B9831186B9828186B98779A0018002822882324D9082324D98",
INIT_05 => X"690C671468088719690C670F68088719690C670A680887496914670A68086607",
INIT_06 => X"670A681A87C967CA681987496911670D681D87496914670A6818660780028719",
INIT_07 => X"87C96713681B87C96714681A87C96714681987C9670C681C87C9670B681B87C9",
INIT_08 => X"87C9670B681087496914670A681587496914670A680F6607800287C96712681C",
INIT_09 => X"681387C96710681387C9670F681287C9670E681287C9670D681187C9670C6811",
INIT_0A => X"858987C9663F68124769CD014E69800287C96713681487C96712681487C96711",
INIT_0B => X"6812670C8002858987C9663F681247698D014E69800287C96600681247718002",
INIT_0C => X"85F185B186B98109854986B981098549800287C9660068126713800287C96600",
INIT_0D => X"86D33C0086E3DB017B1FDC017CFFDD017DFFA00386B98109861985B186B98109",
INIT_0E => X"6600800287534748870187C98901800287234848880187C98901800286C33D00",
INIT_0F => X"2540A8090401041F053F454144398002878B0D1E8D0187196927680047696D00",
INIT_10 => X"0000000000000000000000000000000080024692449045912580A82104018000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"8640000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"3CF3CF3CF3CFCFF4FCFCFCFF0000140034CF0CC3D38430A0004FF3CC00000000",
INITP_01 => X"868138F3D089089222EED00000004FD3F43C84F10F213CF3CF3CF3CF3CFCFF4F",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000007F85",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
--synthesis translate_on
port map( DI => "0000000000000000",
DIP => "00",
EN => '1',
WE => '0',
SSR => '0',
CLK => clk,
ADDR => address,
DO => INSTRUCTION(15 downto 0),
DOP => INSTRUCTION(17 downto 16));
--
end low_level_definition;
--
----------------------------------------------------------------------
-- END OF FILE prog_rom.vhd
----------------------------------------------------------------------
| mit | 7cf20870847acbeef237ba08d0714231 | 0.735725 | 5.02452 | false | false | false | false |
Yarr/Yarr-fw | rtl/spartan6/rx-core/decode_8b10b/decode_8b10b_top.vhd | 2 | 12,826 | -------------------------------------------------------------------------------
--
-- Module : decode_8b10b_top.vhd
--
-- Version : 1.1
--
-- Last Update : 2008-10-31
--
-- Project : 8b/10b Decoder Reference Design
--
-- Description : Core wrapper file
--
-- Company : Xilinx, Inc.
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
--
-- History
--
-- Date Version Description
--
-- 10/31/2008 1.1 Initial release
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
library work;
USE work.decode_8b10b_pkg.ALL;
library decode_8b10b;
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
ENTITY decode_8b10b_top IS
GENERIC (
C_DECODE_TYPE : INTEGER := 0;
C_HAS_BPORTS : INTEGER := 0;
C_HAS_CE : INTEGER := 0;
C_HAS_CODE_ERR : INTEGER := 0;
C_HAS_DISP_ERR : INTEGER := 0;
C_HAS_DISP_IN : INTEGER := 0;
C_HAS_ND : INTEGER := 0;
C_HAS_RUN_DISP : INTEGER := 0;
C_HAS_SINIT : INTEGER := 0;
C_HAS_SYM_DISP : INTEGER := 0;
C_SINIT_VAL : STRING(1 TO 10) := "0000000000";
C_SINIT_VAL_B : STRING(1 TO 10) := "0000000000"
);
PORT (
CLK : IN STD_LOGIC := '0';
DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;
KOUT : OUT STD_LOGIC ;
CE : IN STD_LOGIC := '0';
CE_B : IN STD_LOGIC := '0';
CLK_B : IN STD_LOGIC := '0';
DIN_B : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DISP_IN : IN STD_LOGIC := '0';
DISP_IN_B : IN STD_LOGIC := '0';
SINIT : IN STD_LOGIC := '0';
SINIT_B : IN STD_LOGIC := '0';
CODE_ERR : OUT STD_LOGIC := '0';
CODE_ERR_B : OUT STD_LOGIC := '0';
DISP_ERR : OUT STD_LOGIC := '0';
DISP_ERR_B : OUT STD_LOGIC := '0';
DOUT_B : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;
KOUT_B : OUT STD_LOGIC ;
ND : OUT STD_LOGIC := '0';
ND_B : OUT STD_LOGIC := '0';
RUN_DISP : OUT STD_LOGIC ;
RUN_DISP_B : OUT STD_LOGIC ;
SYM_DISP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;
SYM_DISP_B : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
--------------------------------------------------------------------------------
-- Port Definitions:
--------------------------------------------------------------------------------
-- Mandatory Pins
-- CLK : Clock Input
-- DIN : Encoded Symbol Input
-- DOUT : Data Output, decoded data byte
-- KOUT : Command Output
-------------------------------------------------------------------------
-- Optional Pins
-- CE : Clock Enable
-- CE_B : Clock Enable (B port)
-- CLK_B : Clock Input (B port)
-- DIN_B : Encoded Symbol Input (B port)
-- DISP_IN : Disparity Input (running disparity in)
-- DISP_IN_B : Disparity Input (running disparity in) (B port)
-- SINIT : Synchronous Initialization. Resets core to known state.
-- SINIT_B : Synchronous Initialization. Resets core to known state.
-- (B port)
-- CODE_ERR : Code Error, indicates that input symbol did not correspond
-- to a valid member of the code set.
-- CODE_ERR_B : Code Error, indicates that input symbol did not correspond
-- to a valid member of the code set. (B port)
-- DISP_ERR : Disparity Error
-- DISP_ERR_B : Disparity Error (B port)
-- DOUT_B : Data Output, decoded data byte (B port)
-- KOUT_B : Command Output (B port)
-- ND : New Data
-- ND_B : New Data (B port)
-- RUN_DISP : Running Disparity
-- RUN_DISP_B : Running Disparity (B port)
-- SYM_DISP : Symbol Disparity
-- SYM_DISP_B : Symbol Disparity (B port)
-------------------------------------------------------------------------
END decode_8b10b_top;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
ARCHITECTURE xilinx OF decode_8b10b_top IS
CONSTANT SINIT_DOUT : STRING(1 TO 8) := C_SINIT_VAL(1 TO 8);
CONSTANT SINIT_DOUT_B : STRING(1 TO 8) := C_SINIT_VAL_B(1 TO 8);
CONSTANT SINIT_RD : INTEGER := calc_init_val_rd(C_SINIT_VAL);
-- converts C_SINIT_VAL string to integer
CONSTANT SINIT_RD_B : INTEGER := calc_init_val_rd(C_SINIT_VAL_B);
-- converts C_SINIT_VAL_B string to integer
-- If C_HAS_BPORTS=1, the optional B ports are configured the same way as the
-- optional A ports. Otherwise, all the B ports are disabled.
CONSTANT C_HAS_CE_B : INTEGER := has_bport(C_HAS_BPORTS, C_HAS_CE);
CONSTANT C_HAS_CODE_ERR_B : INTEGER := has_bport(C_HAS_BPORTS, C_HAS_CODE_ERR);
CONSTANT C_HAS_DISP_ERR_B : INTEGER := has_bport(C_HAS_BPORTS, C_HAS_DISP_ERR);
CONSTANT C_HAS_DISP_IN_B : INTEGER := has_bport(C_HAS_BPORTS, C_HAS_DISP_IN);
CONSTANT C_HAS_ND_B : INTEGER := has_bport(C_HAS_BPORTS, C_HAS_ND);
CONSTANT C_HAS_RUN_DISP_B : INTEGER := has_bport(C_HAS_BPORTS, C_HAS_RUN_DISP);
CONSTANT C_HAS_SINIT_B : INTEGER := has_bport(C_HAS_BPORTS, C_HAS_SINIT);
CONSTANT C_HAS_SYM_DISP_B : INTEGER := has_bport(C_HAS_BPORTS, C_HAS_SYM_DISP);
-------------------------------------------------------------------------------
-- BEGIN ARCHITECTURE
-------------------------------------------------------------------------------
BEGIN
dec : entity work.decode_8b10b_rtl
GENERIC MAP (
C_DECODE_TYPE => C_DECODE_TYPE,
C_ELABORATION_DIR => "./../../src/",
C_HAS_BPORTS => C_HAS_BPORTS,
C_HAS_CE => C_HAS_CE,
C_HAS_CE_B => C_HAS_CE_B,
C_HAS_CODE_ERR => C_HAS_CODE_ERR,
C_HAS_CODE_ERR_B => C_HAS_CODE_ERR_B,
C_HAS_DISP_ERR => C_HAS_DISP_ERR,
C_HAS_DISP_ERR_B => C_HAS_DISP_ERR_B,
C_HAS_DISP_IN => C_HAS_DISP_IN,
C_HAS_DISP_IN_B => C_HAS_DISP_IN_B,
C_HAS_ND => C_HAS_ND,
C_HAS_ND_B => C_HAS_ND_B,
C_HAS_RUN_DISP => C_HAS_RUN_DISP,
C_HAS_RUN_DISP_B => C_HAS_RUN_DISP_B,
C_HAS_SINIT => C_HAS_SINIT,
C_HAS_SINIT_B => C_HAS_SINIT_B,
C_HAS_SYM_DISP => C_HAS_SYM_DISP,
C_HAS_SYM_DISP_B => C_HAS_SYM_DISP_B,
C_SINIT_DOUT => SINIT_DOUT,
C_SINIT_DOUT_B => SINIT_DOUT_B,
C_SINIT_KOUT => 0,
C_SINIT_KOUT_B => 0,
C_SINIT_RUN_DISP => SINIT_RD,
C_SINIT_RUN_DISP_B => SINIT_RD_B
)
PORT MAP(
CLK => CLK,
DIN => DIN,
DOUT => DOUT,
KOUT => KOUT,
CE => CE,
CE_B => CE_B,
CLK_B => CLK_B,
DIN_B => DIN_B,
DISP_IN => DISP_IN,
DISP_IN_B => DISP_IN_B,
SINIT => SINIT,
SINIT_B => SINIT_B,
CODE_ERR => CODE_ERR,
CODE_ERR_B => CODE_ERR_B,
DISP_ERR => DISP_ERR,
DISP_ERR_B => DISP_ERR_B,
DOUT_B => DOUT_B,
KOUT_B => KOUT_B,
ND => ND,
ND_B => ND_B,
RUN_DISP => RUN_DISP,
RUN_DISP_B => RUN_DISP_B,
SYM_DISP => SYM_DISP,
SYM_DISP_B => SYM_DISP_B
);
--------------------------------------------------------------------------------
-- Generic Definitions:
--------------------------------------------------------------------------------
-- C_DECODE_TYPE : Implementation: 0=Slice based, 1=BlockRam
-- C_ELABORATION_DIR : Directory path for mif file
-- C_HAS_BPORTS : 1 indicates second decoder should be generated
-- C_HAS_CE : 1 indicates ce port is present
-- C_HAS_CE_B : 1 indicates ce_b port is present (if c_has_bports=1)
-- C_HAS_CODE_ERR : 1 indicates code_err port is present
-- C_HAS_CODE_ERR_B : 1 indicates code_err_b port is present
-- (if c_has_bports=1)
-- C_HAS_DISP_ERR : 1 indicates disp_err port is present
-- C_HAS_DISP_ERR_B : 1 indicates disp_err_b port is present
-- (if c_has_bports=1)
-- C_HAS_DISP_IN : 1 indicates disp_in port is present
-- C_HAS_DISP_IN_B : 1 indicates disp_in_b port is present
-- (if c_has_bports=1)
-- C_HAS_ND : 1 indicates nd port is present
-- C_HAS_ND_B : 1 indicates nd_b port is present (if c_has_bports=1)
-- C_HAS_RUN_DISP : 1 indicates run_disp port is present
-- C_HAS_RUN_DISP_B : 1 indicates run_disp_b port is present
-- (if c_has_bports=1)
-- C_HAS_SINIT : 1 indicates sinit port is present
-- C_HAS_SINIT_B : 1 indicates sinit_b port is present
-- (if c_has_bports=1)
-- C_HAS_SYM_DISP : 1 indicates sym_disp port is present
-- C_HAS_SYM_DISP_B : 1 indicates sym_disp_b port is present
-- (if c_has_bports=1)
-- C_SINIT_DOUT : 8-bit binary string, dout value when sinit is active
-- C_SINIT_DOUT_B : 8-bit binary string, dout_b value when sinit_b is
-- active
-- C_SINIT_KOUT : controls kout output when sinit is active
-- C_SINIT_KOUT_B : controls kout_b output when sinit_b is active
-- C_SINIT_RUN_DISP : Initializes run_disp (and disp_in) value to
-- positive(1) or negative(0)
-- C_SINIT_RUN_DISP_B : Initializes run_disp_b (and disp_in_b) value to
-- positive(1) or negative(0)
--------------------------------------------------------------------------------
END xilinx;
| gpl-3.0 | d4bed7ed3740d06b02e8c8ed77ca298e | 0.478325 | 3.753585 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_dma_v7_1/hdl/src/vhdl/axi_dma_reset.vhd | 1 | 39,154 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_reset.vhd
-- Description: This entity encompasses the reset logic (soft and hard) for
-- distribution to the axi_vdma core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library proc_common_v4_0;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_reset is
generic(
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_AXI_PRMRY_ACLK_FREQ_HZ : integer := 100000000;
-- Primary clock frequency in hertz
C_AXI_SCNDRY_ACLK_FREQ_HZ : integer := 100000000
-- Secondary clock frequency in hertz
);
port (
-- Clock Sources
m_axi_sg_aclk : in std_logic ; --
axi_prmry_aclk : in std_logic ; --
--
-- Hard Reset --
axi_resetn : in std_logic ; --
--
-- Soft Reset --
soft_reset : in std_logic ; --
soft_reset_clr : out std_logic := '0' ; --
soft_reset_done : in std_logic ; --
--
--
all_idle : in std_logic ; --
stop : in std_logic ; --
halt : out std_logic := '0' ; --
halt_cmplt : in std_logic ; --
--
-- Secondary Reset --
scndry_resetn : out std_logic := '1' ; --
-- AXI Upsizer and Line Buffer --
prmry_resetn : out std_logic := '0' ; --
-- AXI DataMover Primary Reset (Raw) --
dm_prmry_resetn : out std_logic := '1' ; --
-- AXI DataMover Secondary Reset (Raw) --
dm_scndry_resetn : out std_logic := '1' ; --
-- AXI Primary Stream Reset Outputs --
prmry_reset_out_n : out std_logic := '1' ; --
-- AXI Alternat Stream Reset Outputs --
altrnt_reset_out_n : out std_logic := '1' --
);
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of scndry_resetn : signal is "TRUE";
Attribute KEEP of prmry_resetn : signal is "TRUE";
Attribute KEEP of dm_scndry_resetn : signal is "TRUE";
Attribute KEEP of dm_prmry_resetn : signal is "TRUE";
Attribute KEEP of prmry_reset_out_n : signal is "TRUE";
Attribute KEEP of altrnt_reset_out_n : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of scndry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of prmry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of dm_scndry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of dm_prmry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of prmry_reset_out_n : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of altrnt_reset_out_n: signal is "no";
end axi_dma_reset;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_reset is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Soft Reset Support
signal s_soft_reset_i : std_logic := '0';
signal s_soft_reset_i_d1 : std_logic := '0';
signal s_soft_reset_i_re : std_logic := '0';
signal assert_sftrst_d1 : std_logic := '0';
signal min_assert_sftrst : std_logic := '0';
signal min_assert_sftrst_d1_cdc_tig : std_logic := '0';
--ATTRIBUTE async_reg OF min_assert_sftrst_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF min_assert_sftrst : SIGNAL IS "true";
signal p_min_assert_sftrst : std_logic := '0';
signal sft_rst_dly1 : std_logic := '0';
signal sft_rst_dly2 : std_logic := '0';
signal sft_rst_dly3 : std_logic := '0';
signal sft_rst_dly4 : std_logic := '0';
signal sft_rst_dly5 : std_logic := '0';
signal sft_rst_dly6 : std_logic := '0';
signal sft_rst_dly7 : std_logic := '0';
signal sft_rst_dly8 : std_logic := '0';
signal sft_rst_dly9 : std_logic := '0';
signal sft_rst_dly10 : std_logic := '0';
signal sft_rst_dly11 : std_logic := '0';
signal sft_rst_dly12 : std_logic := '0';
signal sft_rst_dly13 : std_logic := '0';
signal sft_rst_dly14 : std_logic := '0';
signal sft_rst_dly15 : std_logic := '0';
signal sft_rst_dly16 : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
-- Soft Reset to Primary clock domain signals
signal p_soft_reset : std_logic := '0';
signal p_soft_reset_d1_cdc_tig : std_logic := '0';
signal p_soft_reset_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF p_soft_reset_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_soft_reset_d2 : SIGNAL IS "true";
signal p_soft_reset_d3 : std_logic := '0';
signal p_soft_reset_re : std_logic := '0';
-- Qualified soft reset in primary clock domain for
-- generating mimimum reset pulse for soft reset
signal p_soft_reset_i : std_logic := '0';
signal p_soft_reset_i_d1 : std_logic := '0';
signal p_soft_reset_i_re : std_logic := '0';
-- Graceful halt control
signal halt_cmplt_d1_cdc_tig : std_logic := '0';
signal s_halt_cmplt : std_logic := '0';
--ATTRIBUTE async_reg OF halt_cmplt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s_halt_cmplt : SIGNAL IS "true";
signal p_halt_d1_cdc_tig : std_logic := '0';
signal p_halt : std_logic := '0';
--ATTRIBUTE async_reg OF p_halt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_halt : SIGNAL IS "true";
signal s_halt : std_logic := '0';
-- composite reset (hard and soft)
signal resetn_i : std_logic := '1';
signal scndry_resetn_i : std_logic := '1';
signal axi_resetn_d1_cdc_tig : std_logic := '1';
signal axi_resetn_d2 : std_logic := '1';
--ATTRIBUTE async_reg OF axi_resetn_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF axi_resetn_d2 : SIGNAL IS "true";
signal halt_i : std_logic := '0';
signal p_all_idle : std_logic := '1';
signal p_all_idle_d1_cdc_tig : std_logic := '1';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Internal Hard Reset
-- Generate reset on hardware reset or soft reset
-------------------------------------------------------------------------------
resetn_i <= '0' when s_soft_reset_i = '1'
or min_assert_sftrst = '1'
or axi_resetn = '0'
else '1';
-------------------------------------------------------------------------------
-- Minimum Reset Logic for Soft Reset
-------------------------------------------------------------------------------
-- Register to generate rising edge on soft reset and falling edge
-- on reset assertion.
REG_SFTRST_FOR_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
s_soft_reset_i_d1 <= s_soft_reset_i;
assert_sftrst_d1 <= min_assert_sftrst;
-- Register soft reset from DMACR to create
-- rising edge pulse
soft_reset_d1 <= soft_reset;
end if;
end process REG_SFTRST_FOR_RE;
-- rising edge pulse on internal soft reset
s_soft_reset_i_re <= s_soft_reset_i and not s_soft_reset_i_d1;
-- CR605883
-- rising edge pulse on DMACR soft reset
REG_SOFT_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
soft_reset_re <= soft_reset and not soft_reset_d1;
end if;
end process REG_SOFT_RE;
-- falling edge detection on min soft rst to clear soft reset
-- bit in register module
soft_reset_clr <= (not min_assert_sftrst and assert_sftrst_d1)
or (not axi_resetn);
-------------------------------------------------------------------------------
-- Generate Reset for synchronous configuration
-------------------------------------------------------------------------------
GNE_SYNC_RESET : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- On start of soft reset shift pulse through to assert
-- 7 clock later. Used to set minimum 8clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
MIN_PULSE_GEN : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
elsif(all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 8 clocks.
MIN_RESET_ASSERTION : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
min_assert_sftrst <= '1';
elsif(sft_rst_dly7 = '1')then
min_assert_sftrst <= '0';
end if;
end if;
end process MIN_RESET_ASSERTION;
-------------------------------------------------------------------------------
-- Soft Reset Support
-------------------------------------------------------------------------------
-- Generate reset on hardware reset or soft reset if system is idle
-- On soft reset or error
-- mm2s dma controller will idle immediatly
-- sg fetch engine will complete current task and idle (desc's will flush)
-- sg update engine will update all completed descriptors then idle
REG_SOFT_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset = '1'
and all_idle = '1' and halt_cmplt = '1')then
s_soft_reset_i <= '1';
elsif(soft_reset_done = '1')then
s_soft_reset_i <= '0';
end if;
end if;
end process REG_SOFT_RESET;
-- Halt datamover on soft_reset or on error. Halt will stay
-- asserted until s_soft_reset_i assertion which occurs when
-- halt is complete or hard reset
REG_DM_HALT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(resetn_i = '0')then
halt_i <= '0';
elsif(soft_reset_re = '1' or stop = '1')then
halt_i <= '1';
end if;
end if;
end process REG_DM_HALT;
halt <= halt_i;
-- AXI Stream reset output
REG_STRM_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
prmry_reset_out_n <= resetn_i and not s_soft_reset_i;
end if;
end process REG_STRM_RESET_OUT;
-- If in Scatter Gather mode and status control stream included
GEN_ALT_RESET_OUT : if C_INCLUDE_SG = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- AXI Stream reset output
REG_ALT_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
altrnt_reset_out_n <= resetn_i and not s_soft_reset_i;
end if;
end process REG_ALT_RESET_OUT;
end generate GEN_ALT_RESET_OUT;
-- If in Simple mode or status control stream excluded
GEN_NO_ALT_RESET_OUT : if C_INCLUDE_SG = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
altrnt_reset_out_n <= '1';
end generate GEN_NO_ALT_RESET_OUT;
-- Registered primary and secondary resets out
REG_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
prmry_resetn <= resetn_i;
scndry_resetn <= resetn_i;
end if;
end process REG_RESET_OUT;
-- AXI DataMover Primary Reset (Raw)
dm_prmry_resetn <= resetn_i;
-- AXI DataMover Secondary Reset (Raw)
dm_scndry_resetn <= resetn_i;
end generate GNE_SYNC_RESET;
-------------------------------------------------------------------------------
-- Generate Reset for asynchronous configuration
-------------------------------------------------------------------------------
GEN_ASYNC_RESET : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Primary clock is slower or equal to secondary therefore...
-- For Halt - can simply pass secondary clock version of soft reset
-- rising edge into p_halt assertion
-- For Min Rst Assertion - can simply use secondary logic version of min pulse genator
GEN_PRMRY_GRTR_EQL_SCNDRY : if C_AXI_PRMRY_ACLK_FREQ_HZ >= C_AXI_SCNDRY_ACLK_FREQ_HZ generate
begin
-- CR605883 - Register to provide pure register output for synchronizer
REG_HALT_CONDITIONS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
s_halt <= soft_reset_re or stop;
end if;
end process REG_HALT_CONDITIONS;
-- Halt data mover on soft reset assertion, error (i.e. stop=1) or
-- not running
HALT_PROCESS : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s_halt,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_halt,
scndry_vect_out => open
);
-- HALT_PROCESS : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- --p_halt_d1_cdc_tig <= soft_reset_re or stop; -- CR605883
-- p_halt_d1_cdc_tig <= s_halt; -- CR605883
-- p_halt <= p_halt_d1_cdc_tig;
-- end if;
-- end process HALT_PROCESS;
-- On start of soft reset shift pulse through to assert
-- 7 clock later. Used to set minimum 8clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
-- Adding 5 more flops to make up for 5 stages of Sync flops
MIN_PULSE_GEN : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
sft_rst_dly8 <= '0';
sft_rst_dly9 <= '0';
sft_rst_dly10 <= '0';
sft_rst_dly11 <= '0';
sft_rst_dly12 <= '0';
sft_rst_dly13 <= '0';
sft_rst_dly14 <= '0';
sft_rst_dly15 <= '0';
sft_rst_dly16 <= '0';
elsif(all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
sft_rst_dly8 <= sft_rst_dly7;
sft_rst_dly9 <= sft_rst_dly8;
sft_rst_dly10 <= sft_rst_dly9;
sft_rst_dly11 <= sft_rst_dly10;
sft_rst_dly12 <= sft_rst_dly11;
sft_rst_dly13 <= sft_rst_dly12;
sft_rst_dly14 <= sft_rst_dly13;
sft_rst_dly15 <= sft_rst_dly14;
sft_rst_dly16 <= sft_rst_dly15;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 8 clocks.
MIN_RESET_ASSERTION : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
min_assert_sftrst <= '1';
elsif(sft_rst_dly16 = '1')then
min_assert_sftrst <= '0';
end if;
end if;
end process MIN_RESET_ASSERTION;
end generate GEN_PRMRY_GRTR_EQL_SCNDRY;
-- Primary clock is running slower than secondary therefore need to use a primary clock
-- based rising edge version of soft_reset for primary halt assertion
GEN_PRMRY_LESS_SCNDRY : if C_AXI_PRMRY_ACLK_FREQ_HZ < C_AXI_SCNDRY_ACLK_FREQ_HZ generate
signal soft_halt_int : std_logic := '0';
begin
-- Halt data mover on soft reset assertion, error (i.e. stop=1) or
-- not running
soft_halt_int <= p_soft_reset_re or stop;
HALT_PROCESS : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => soft_halt_int,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_halt,
scndry_vect_out => open
);
-- HALT_PROCESS : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- p_halt_d1_cdc_tig <= p_soft_reset_re or stop;
-- p_halt <= p_halt_d1_cdc_tig;
-- end if;
-- end process HALT_PROCESS;
REG_IDLE2PRMRY : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => all_idle,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_all_idle,
scndry_vect_out => open
);
-- REG_IDLE2PRMRY : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- p_all_idle_d1_cdc_tig <= all_idle;
-- p_all_idle <= p_all_idle_d1_cdc_tig;
-- end if;
-- end process REG_IDLE2PRMRY;
-- On start of soft reset shift pulse through to assert
-- 7 clock later. Used to set minimum 8clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
MIN_PULSE_GEN : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
--if(p_soft_reset_re = '1')then
if(p_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
sft_rst_dly8 <= '0';
sft_rst_dly9 <= '0';
sft_rst_dly10 <= '0';
sft_rst_dly11 <= '0';
sft_rst_dly12 <= '0';
sft_rst_dly13 <= '0';
sft_rst_dly14 <= '0';
sft_rst_dly15 <= '0';
sft_rst_dly16 <= '0';
elsif(p_all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
sft_rst_dly8 <= sft_rst_dly7;
sft_rst_dly9 <= sft_rst_dly8;
sft_rst_dly10 <= sft_rst_dly9;
sft_rst_dly11 <= sft_rst_dly10;
sft_rst_dly12 <= sft_rst_dly11;
sft_rst_dly13 <= sft_rst_dly12;
sft_rst_dly14 <= sft_rst_dly13;
sft_rst_dly15 <= sft_rst_dly14;
sft_rst_dly16 <= sft_rst_dly15;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 8 primary clocks.
MIN_RESET_ASSERTION : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
--if(p_soft_reset_re = '1')then
if(p_soft_reset_i_re = '1')then
p_min_assert_sftrst <= '1';
elsif(sft_rst_dly16 = '1')then
p_min_assert_sftrst <= '0';
end if;
end if;
end process MIN_RESET_ASSERTION;
-- register minimum reset pulse back to secondary domain
REG_MINRST2SCNDRY : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => p_min_assert_sftrst,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => min_assert_sftrst,
scndry_vect_out => open
);
-- REG_MINRST2SCNDRY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- min_assert_sftrst_d1_cdc_tig <= p_min_assert_sftrst;
-- min_assert_sftrst <= min_assert_sftrst_d1_cdc_tig;
-- end if;
-- end process REG_MINRST2SCNDRY;
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
-- Generate reset on hardware reset or soft reset if system is idle
REG_P_SOFT_RESET : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_soft_reset = '1'
and p_all_idle = '1'
and halt_cmplt = '1')then
p_soft_reset_i <= '1';
else
p_soft_reset_i <= '0';
end if;
end if;
end process REG_P_SOFT_RESET;
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
-- Register qualified soft reset flag for generating rising edge
-- pulse for starting minimum reset pulse
REG_SOFT2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
p_soft_reset_i_d1 <= p_soft_reset_i;
end if;
end process REG_SOFT2PRMRY;
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
-- Generate rising edge pulse on qualified soft reset for min pulse
-- logic.
p_soft_reset_i_re <= p_soft_reset_i and not p_soft_reset_i_d1;
end generate GEN_PRMRY_LESS_SCNDRY;
-- Double register halt complete flag from primary to secondary
-- clock domain.
-- Note: halt complete stays asserted until halt clears therefore
-- only need to double register from fast to slow clock domain.
REG_HALT_CMPLT_IN : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => halt_cmplt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s_halt_cmplt,
scndry_vect_out => open
);
-- REG_HALT_CMPLT_IN : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
--
-- halt_cmplt_d1_cdc_tig <= halt_cmplt;
-- s_halt_cmplt <= halt_cmplt_d1_cdc_tig;
-- end if;
-- end process REG_HALT_CMPLT_IN;
-------------------------------------------------------------------------------
-- Soft Reset Support
-------------------------------------------------------------------------------
-- Generate reset on hardware reset or soft reset if system is idle
REG_SOFT_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset = '1'
and all_idle = '1'
and s_halt_cmplt = '1')then
s_soft_reset_i <= '1';
elsif(soft_reset_done = '1')then
s_soft_reset_i <= '0';
end if;
end if;
end process REG_SOFT_RESET;
-- Register soft reset flag into primary domain to correcly
-- halt data mover
REG_SOFT2PRMRY : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => soft_reset,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_soft_reset_d2,
scndry_vect_out => open
);
REG_SOFT2PRMRY1 : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- p_soft_reset_d1_cdc_tig <= soft_reset;
-- p_soft_reset_d2 <= p_soft_reset_d1_cdc_tig;
p_soft_reset_d3 <= p_soft_reset_d2;
end if;
end process REG_SOFT2PRMRY1;
-- Generate rising edge pulse for use with p_halt creation
p_soft_reset_re <= p_soft_reset_d2 and not p_soft_reset_d3;
-- used to mask halt reset below
p_soft_reset <= p_soft_reset_d2;
-- Halt datamover on soft_reset or on error. Halt will stay
-- asserted until s_soft_reset_i assertion which occurs when
-- halt is complete or hard reset
REG_DM_HALT : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(axi_resetn_d2 = '0')then
halt_i <= '0';
elsif(p_halt = '1')then
halt_i <= '1';
end if;
end if;
end process REG_DM_HALT;
halt <= halt_i;
-- CR605883 (CDC) Create pure register out for synchronizer
REG_CMB_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
scndry_resetn_i <= resetn_i;
end if;
end process REG_CMB_RESET;
-- Sync to mm2s primary and register resets out
REG_RESET_OUT : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => scndry_resetn_i,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => axi_resetn_d2,
scndry_vect_out => open
);
-- REG_RESET_OUT : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- --axi_resetn_d1_cdc_tig <= resetn_i; -- CR605883
-- axi_resetn_d1_cdc_tig <= scndry_resetn_i;
-- axi_resetn_d2 <= axi_resetn_d1_cdc_tig;
-- end if;
-- end process REG_RESET_OUT;
-- Register resets out to AXI DMA Logic
REG_SRESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
scndry_resetn <= resetn_i;
end if;
end process REG_SRESET_OUT;
-- AXI Stream reset output
prmry_reset_out_n <= axi_resetn_d2;
-- If in Scatter Gather mode and status control stream included
GEN_ALT_RESET_OUT : if C_INCLUDE_SG = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- AXI Stream alternate reset output
altrnt_reset_out_n <= axi_resetn_d2;
end generate GEN_ALT_RESET_OUT;
-- If in Simple Mode or status control stream excluded.
GEN_NO_ALT_RESET_OUT : if C_INCLUDE_SG = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
altrnt_reset_out_n <= '1';
end generate GEN_NO_ALT_RESET_OUT;
-- Register primary reset
prmry_resetn <= axi_resetn_d2;
-- AXI DataMover Primary Reset
dm_prmry_resetn <= axi_resetn_d2;
-- AXI DataMover Secondary Reset
dm_scndry_resetn <= resetn_i;
end generate GEN_ASYNC_RESET;
end implementation;
| bsd-2-clause | deab2eeedcf0e7f11d15282f5ecd2816 | 0.461026 | 4.150747 | false | false | false | false |
Yarr/Yarr-fw | rtl/kintex7/rx-core/aurora_rx_channel.vhd | 1 | 9,393 | -- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: RX channel
-- # Aurora style rx code
-- ####################################
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim ;
use unisim.vcomponents.all ;
entity aurora_rx_channel is
generic (
g_NUM_LANES : integer range 1 to 4 := 1
);
port (
-- Sys connect
rst_n_i : in std_logic;
clk_rx_i : in std_logic; -- Fabric clock (serdes/8)
clk_serdes_i : in std_logic; -- IO clock
-- Input
enable_i : in std_logic;
rx_data_i_p : in std_logic_vector(g_NUM_LANES-1 downto 0);
rx_data_i_n : in std_logic_vector(g_NUM_LANES-1 downto 0);
rx_polarity_i : in std_logic_vector(g_NUM_LANES-1 downto 0);
trig_tag_i : in std_logic_vector(63 downto 0);
-- Output
rx_data_o : out std_logic_vector(63 downto 0);
rx_valid_o : out std_logic;
rx_stat_o : out std_logic_vector(7 downto 0)
);
end aurora_rx_channel;
architecture behavioral of aurora_rx_channel is
function log2_ceil(val : integer) return natural is
variable result : natural;
begin
for i in 0 to g_NUM_LANES-1 loop
if (val <= (2 ** i)) then
result := i;
exit;
end if;
end loop;
return result;
end function;
constant c_ALL_ZEROS : std_logic_vector(g_NUM_LANES-1 downto 0) := (others => '0');
component aurora_rx_lane
port (
-- Sys connect
rst_n_i : in std_logic;
clk_rx_i : in std_logic;
clk_serdes_i : in std_logic;
-- Input
rx_data_i_p : in std_logic;
rx_data_i_n : in std_logic;
rx_polarity_i : in std_logic;
-- Output
rx_data_o : out std_logic_vector(63 downto 0);
rx_header_o : out std_logic_vector(1 downto 0);
rx_valid_o : out std_logic;
rx_stat_o : out std_logic_vector(7 downto 0)
);
end component aurora_rx_lane;
component rr_arbiter
generic (
g_CHANNELS : integer := g_NUM_LANES
);
port (
-- sys connect
clk_i : in std_logic;
rst_i : in std_logic;
-- requests
req_i : in std_logic_vector(g_NUM_LANES-1 downto 0);
-- grants
gnt_o : out std_logic_vector(g_NUM_LANES-1 downto 0)
);
end component rr_arbiter;
COMPONENT rx_lane_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
constant c_AURORA_IDLE : std_logic_vector(7 downto 0) := x"78";
constant c_AURORA_SEP : std_logic_vector(7 downto 0) := x"1E";
signal rx_data_s : std_logic_vector(63 downto 0);
signal rx_valid_s : std_logic;
type rx_data_array is array (g_NUM_LANES-1 downto 0) of std_logic_vector(63 downto 0);
signal rx_data : rx_data_array;
type rx_header_array is array (g_NUM_LANES-1 downto 0) of std_logic_vector(1 downto 0);
signal rx_header : rx_header_array;
type rx_status_array is array (g_NUM_LANES-1 downto 0) of std_logic_vector(7 downto 0);
signal rx_status : rx_status_array;
signal rx_polarity : std_logic_vector(g_NUM_LANES-1 downto 0);
signal rx_data_valid : std_logic_vector(g_NUM_LANES-1 downto 0);
signal rx_fifo_dout :rx_data_array;
signal rx_fifo_din : rx_data_array;
signal rx_fifo_full : std_logic_vector(g_NUM_LANES-1 downto 0);
signal rx_fifo_empty : std_logic_vector(g_NUM_LANES-1 downto 0);
signal rx_fifo_rden : std_logic_vector(g_NUM_LANES-1 downto 0);
signal rx_fifo_rden_t : std_logic_vector(g_NUM_LANES-1 downto 0);
signal rx_fifo_wren : std_logic_vector(g_NUM_LANES-1 downto 0);
signal channel : integer range 0 to g_NUM_LANES-1;
COMPONENT ila_rx_dma_wb
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe8 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT ;
begin
rx_data_o <= rx_data_s;
rx_valid_o <= rx_valid_s;
-- Arbiter
cmp_rr_arbiter : rr_arbiter port map (
clk_i => clk_rx_i,
rst_i => not rst_n_i,
req_i => not rx_fifo_empty,
gnt_o => rx_fifo_rden_t
);
reg_proc : process(clk_rx_i, rst_n_i)
begin
if (rst_n_i = '0') then
rx_fifo_rden <= (others => '0');
rx_data_s <= (others => '0');
rx_valid_s <= '0';
channel <= 0;
rx_polarity <= (others => '0');
elsif rising_edge(clk_rx_i) then
rx_fifo_rden <= rx_fifo_rden_t;
rx_polarity <= rx_polarity_i;
channel <= log2_ceil(to_integer(unsigned(rx_fifo_rden_t)));
if (unsigned(rx_fifo_rden) = 0 or ((rx_fifo_rden and rx_fifo_empty) = rx_fifo_rden)) then
rx_valid_s <= '0';
rx_data_s <= x"DEADBEEFDEADBEEF";
else
rx_valid_s <= '1';
rx_data_s <= rx_fifo_dout(channel);
end if;
end if;
end process reg_proc;
lane_loop: for I in 0 to g_NUM_LANES-1 generate
lane_cmp : aurora_rx_lane port map (
rst_n_i => rst_n_i,
clk_rx_i => clk_rx_i,
clk_serdes_i => clk_serdes_i,
rx_data_i_p => rx_data_i_p(I),
rx_data_i_n => rx_data_i_n(I),
rx_polarity_i => rx_polarity(I),
rx_data_o => rx_data(I),
rx_header_o => rx_header(I),
rx_valid_o => rx_data_valid(I),
rx_stat_o => rx_status(I)
);
rx_stat_o(I) <= rx_status(I)(1);
-- TODO need to save register reads!
-- TODO use
-- We expect these types of data:
-- b01 - D[63:0] - 64 bit data
-- b10 - 0x1E - 0x04 - 0xXXXX - D[31:0] - 32 bit data
-- b10 - 0x1E - 0x00 - 0x0000 - 0x00000000 - 0 bit data
-- b10 - 0x78 - Flag[7:0] - 0xXXXX - 0xXXXXXXXX - Idle
-- b10 - 0xB4 - D[55:0] - Register read (MM)
-- Swapping [63:32] and [31:0] to reverse swapping by casting 64-bit to uint32_t
rx_fifo_din(I) <= rx_data(I)(31 downto 0) & rx_data(I)(63 downto 32) when (rx_header(I) = "01") else
rx_data(I)(31 downto 0) & x"FFFFFFFF" when (rx_data(I)(63 downto 56) = c_AURORA_SEP) else
rx_data(I)(31 downto 0) & rx_data(I)(63 downto 32) when ((rx_header(I) = "10") and (rx_data(I)(63 downto 56) = x"55")) else
rx_data(I)(31 downto 0) & rx_data(I)(63 downto 32) when ((rx_header(I) = "10") and (rx_data(I)(63 downto 56) = x"99")) else
rx_data(I)(31 downto 0) & rx_data(I)(63 downto 32) when ((rx_header(I) = "10") and (rx_data(I)(63 downto 56) = x"D2")) else
x"FFFFFFFFFFFFFFFF";
rx_fifo_wren(I) <= rx_data_valid(I) when (rx_header(I) = "01") else
rx_data_valid(I) when ((rx_data(I)(63 downto 56) = c_AURORA_SEP) and (rx_data(I)(55 downto 48) = x"04")) else
rx_data_valid(I) when ((rx_header(I) = "10") and (rx_data(I)(63 downto 56) = x"55")) else
rx_data_valid(I) when ((rx_header(I) = "10") and (rx_data(I)(63 downto 56) = x"99")) else
rx_data_valid(I) when ((rx_header(I) = "10") and (rx_data(I)(63 downto 56) = x"D2")) else
'0';
cmp_lane_fifo : rx_lane_fifo PORT MAP (
rst => not rst_n_i,
wr_clk => clk_rx_i,
rd_clk => clk_rx_i,
din => rx_fifo_din(I),
wr_en => rx_fifo_wren(I) and enable_i,
rd_en => rx_fifo_rden(I),
dout => rx_fifo_dout(I),
full => rx_fifo_full(I),
empty => rx_fifo_empty(I)
);
end generate lane_loop;
-- aurora_channel_debug : ila_rx_dma_wb
-- PORT MAP (
-- clk => clk_rx_i,
-- probe0 => x"00000000",
-- probe1 => rx_data_s,
-- probe2 => rx_fifo_din(0),
-- probe3(0) => rx_fifo_wren(0),
-- --probe4(0) => rx_fifo_wren(1),
-- probe4(0) => '0',
-- --probe5(0) => rx_fifo_wren(2),
-- probe5(0) => '0',
-- --probe6(0) => rx_fifo_wren(3),
-- probe6(0) => '0',
-- probe7(0) => rx_valid_s,
-- probe8 => x"00000000",
-- probe9(0) => rx_fifo_rden(0),
-- probe10(0) => rx_fifo_empty(0),
-- probe11(0) => '0'
-- );
end behavioral;
| gpl-3.0 | c27c61af503548e05d253459f194fbd9 | 0.520388 | 3.121635 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/vhdlFile/case_statement/classification_test_input.vhd | 1 | 892 |
architecture RTL of ENTITY_NAME is
begin
process
begin
C1: case ? x is
when 1 => Out_1 <= 0;
when 2 => Out_1 <= 1;
when 3 => Out_1 <= 2;
end case ? C1;
C1: case x is
when 1 => Out_1 <= 0;
when 2 => Out_1 <= 1;
when 3 => Out_1 <= 2;
end case C1;
case x is
when 1 => Out_1 <= 0;
when 2 => Out_1 <= 1;
when 3 => Out_1 <= 2;
end case;
end process;
process
begin
C3: case Code_Variable is
when ADD | SUB => Operation := 0;
when MULT | DIV => Operation := 1;
end case C3;
end process;
-- Check others
process begin
case x is
when others => Out_1 <= 0;
end case;
end process;
process begin
case foo(i) is
end case;
end process;
-- Testing combined case and ?
process begin
case? is
end case;
end process;
end architecture RTL;
| gpl-3.0 | ce417bb96226d79209383face4ea0886 | 0.520179 | 3.378788 | false | false | false | false |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/fir_compiler_v7_1/hdl/fir_compiler_v7_1_viv_comp.vhd | 2 | 13,565 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
FAaroWniYno/mQkbjCOTPT94RF7QGuTWz1suO0sXxJjpU4HO4ysdGIqrIYDKVHf7hil/8bOK1R+M
rhBk1K2wEw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
HOlmbjvu+CvxCH+2lOYEgws7NJgtAkwZFRZ10+jhyB9JwZkSakSR/nAA/MNGPvXQWdIZwE4tsTl4
jcVt9T5nx0gTZHmvYdL3vIApl7TYmq6jlS9RMp+9BwPO1Kx7nQ7a0mqNLW986w9WXei74Okq25mz
WlvTdIa9kqZiGa7VXN0=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
OoK+Nut1ThXPTQJbrMk59IZWC6cLrNJtzqgodYkanvAWdgjVIVb5SmALSel5BS9psAElfE0wLQxy
avu7a9Yz+ZgMIgajw7t3nX6TET+E1Bm8Deso5Ub9lmzeEvVqgl4MVWJNuGnNAaHFJrnGQFX5wzQY
PGX6/bon9f1hFNaLv8S7v/g5Q2fSkXiz9VwtMwR0BavuwFmEN1zCMGeu2Gd7C0Wy6ypIxlAPR5yV
1Nez5Ke47XMtHVaBdIhkQr6P7LTZMb58NZLvAFKEM4GOMFf/PbpSeK296ZLYycU293323ybg/JqM
ZqBoCj7m6P9hIPRE7ClEMl1v9U5LAmje/KAqHw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
05BE3HwNq178ILIPhkdkh/pICfeniOUTbRo/K4NlxOOcsgyVVIjaitodhlMmjRPBnLBIudLxQrME
ptJw0pk4RMyJOEgc867q9ol7Zow6I18ATqU0+IVp+7vrN8q4ICJxAs/N5APKYOb/R7YGyxl5037w
Kgok7vw5kJNzgfWB/gA=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bmSeqLQSjhLtl/YsKBq6Ym+siPVmTOtGMCjyyhUL9/BbyUgDD/GzZUxRRU5iMz4kkXuCfG/43qNn
yXuMwQXiWVXc/8oiwkHTblmvk/LIVCH+gWsxHOOWlwgwneD8PY8vt/hDIwg0jB8EYUnQGCYEetQF
aoOqE1wjkiLZPlZJywbAHo5BtG6aIu9G99qE8+QFnjbpP0qTo8yowO5BarmPQdBCcmElo8yg6aFu
b/X2/f8or5M/MZJ4dpk7dgubMF6ij20wMPZFuZZ4Gp05Fk72K6q8BhJSzevWmEd8lAKX5IHCUVmE
WO/BE/qekLc/uc+Uu+5R7wSCM1d6pGi1zdc8hQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8304)
`protect data_block
C8MUYWIjbc1V6hx57ID+GKGqF/mOADAb/4EdDI/IsmDI0vKgLNK4qGMwTo41GhVWofTDNgY8BvvZ
os9P40tLEY/MORMCTqCN3U4Z4A7AYgw54pZ5c3kydrulpq+OrW5vVWXAKxj8/gq/QfAmGtkEh9SL
NESXTsNrWi9uBePCqr7/I737kWKtDJjGfCgRs09sSEnh4jXjQ+dgS4Yg5SlDf5V+zmtfIidK+BNq
KkZRkJYLB70mG4hrtHzgUAQJeDZYjznShitoWxEdaY70BqZ9m3lhaJNJyr2xJmDjn9y3+EYP3TyZ
b/f2N56Uu6fT81uWxPRhsdT5TsSEDw5gbvKf37H3PW71XGLnFUcx9bfoGRMm7OrjcvEDwfCc8qOX
kLqOAZePh1TUmyyCeqh2zz+NyqZDbZNjUPZyDVs2de/QE+biP3cjeZUyG99RT5SY8qLVAVKhIcwT
k0Zpdi80Vx8jWqCeFaSWasCnE3F4mShIDARflamWiix1ko2qa1Itf4hnIPo/YAZerWigA7Kh8Ssx
rkgmXm8ISzU12vvMyXvTvVn7KuPHgWeTaSBeBx3piPPFukogeGBgqplvYylbLIG2thMkFiJDYOIb
c90m+JvITXrimqV5jju6hsvFB0yKt7qZBE1qMA30Xwu+fggiJbvzWmRMLbSSN9lN/UyQ7VEClU2l
z+V7zBXiLlZbhl7HUTGiQ7KS83cnGuypvp2Oz+TK0XgcyOtpi0oQhUFEM676e3Ds43n3syeTZVML
R5g/W3qTH7G8hlMMjuHJoghDIr1sT/KdoGTpH8bHB2jSpp85HCfCzZd1hyAFmQZ6qEGDQon2qBjV
msY74oqbMb7tFa/ChUBOg24JMqPq6OjBGSlbvSFWDGgAK8tl3oljRPNBMSPW22bdLxJCDENLvKEa
NdAeB50Qzw8U2egQ9reTwq0rRowgNduHtIgY1MKJMNVuwlFPZ2lnIdJJYnzRw76iIEupD1Pp3uz3
xyeB1K8shfzV1fZtQKyimAS89aPsSnhZt3gZS4jGhH6NEyMGYjfIdUiDhFkkQt+FLrKy7hD5dmji
VkvaxcuUY1+b28gcX+9/Mft1c/FhyQR/aj0bIexdjbP5N6ZFTJQeZi5CD0hy5JcKuLF87WASkxQ3
9MN9beUKv3qg2+NH97pSto/bPEDuvfbTYNBcWPs8fNagVJDRhkfBL6dMLroAbkGj1fpaFKWxbvum
VF5rhhoQlj9o5kOzW+oF1K12jtKNgjA4caCFuEe+W49m6TKQjjhmNfmL9iobudIjkW/pZfO5ZJiJ
cseVNSybnfi96of1orVHKsAh9EPCxbVY3QdZYCzlEaLSxmsKrMepAww0IL4ZAnrO8eo2ps9tPwab
k903uPMMiOazcEbWUdFGoNKWdU4GimzjIuwGXUoPpXVv2dig/Zo86PyW8RCEtjGUDBGBpSld5yaT
AKiyyNupgEMOVthyDhbBWJn6lm4bmcMKBXJEtPnETX+lPGL5jLUB5v+PwvCHIfovnSM2lH/hQD1p
OASBjfNko6k/i01drneWRGq3iTGiwbLYyfs4wDAx6SNZ7HBQLUf0mkbR0zW7CbC6STJolY73hERs
E/0fl1rQ+FYvI2MiafkMdF9/udrXUGxq689quLizvfrOP7HMyMSvASZtPitSmWazV3IKocTdZ6sq
MxAfrfynyZo3LQh6PfvPx/zYhCGj1v0bBBWNhGTIviHhC8dAtxBJTBdOKq3gLhrFB0ZaDYRmgpAx
2ij1vsFSb6njraJFp6MmolBdrbj97hBXX7wXOaiaC+2HLW4BnytNTWLxhOn83Zx15REP5eXrTeDY
+Df7siozSMmw1V34Z41CvDc5BA//6E7vo/DX0nhHvivGk3DFBgc+lCpBmTRB3Vc4I5McY8AWNIeR
LiNb1POM6e7PzvR4+W4DxzSYPFV5BGlsEGET865Lb4GqZx1HcM8jzptgV7zuINrqTomMQPxV88KO
Zyk9QFV2ft9RKX9fjJliQva5pA+KNkEr2+IGHUA21BOOC9Lb846PW4I0iuoA/zh42+weTLtmCqt3
ru97puXumnoePu5gRuo1PDVJAxPy4Xw8YgBDW9ghl09lQz+FSjDwJtYDTl753RMdRAjzAVrpcHcM
io2Upx08jgzvt7imhcTOAOB+Ht00tqYq9PaqC3qO6xttwH279541+H6ulSMZZQTMtkHqVroM00M8
6o+RWEPUDLOCnP8ckkAT7N0nPzhaUmx0SWnMLy1quihqwgBCuOcE8vkW6CAjyPkxsHPrObY8hEFZ
fSic+gWB2mRwqXvZiuSi2TNbdOp7k5R+sLiTQvf07eUV0OwxnQ0WB8GNfGGQvmErEn4HAKbn5gVX
UsjNOc6l4paJrejqJlAXN4vXCsaKgM8N55uQ6ehcOVJYgefbeca71UqRaeV+3bfbQDl1zmpgq7lS
lo6WhozOF4YagBQ8TzjjBBSK7/OZTU39i7Gkp/TVFRmBkfpYPS14eIj7L0ecFFvVouHKjU7f9z1n
9CauVht/90ATbChv5I46T4mQcPPTZQ1XKzN9BjqrT6pRGy+ltfWpJVvHPlzaUCBkeQ2EEk+CDP+T
UQG6TR3QYTCGC6igOfr5RM5x8Kzn+rQCxOd77FOHw589Bf6+1P0fDxup1xiNHBLy7WcX57MkPpsT
kJNhS4CxsR/TgOwnh3MwJMI8vj5ugCy8hWGPPL9zl861B8lzsynE9FBbwbULabkFqY9f8N9d53Ho
4cjNfbzn7+twzr9I2fWHsRmgPV/fF7D31Q3nBtWO3j0vXEnjyn6OloOr0Yiek/LS9FqIli9+82x3
KpUUDKtCgdgfbTXLZUZJVx/+AzLc7iDHOJi22+geJF/pd6tiIXRCMol2zFCwNhR/ltoEYGEVilYn
OCy2r/mt8ACmoTMFjsLetfYDB6Q9jqxaF0lufaI9OI9JV/jTSxPs5NzTJvcsW/sSbaGAXH7kQyyR
f7GBmFVr+/2IOjHAYGCrirIAUJqpeqECy6sm6RmoKOgEW4Ow7lRHfS8i/cUKqaRek6zyJd6UpkZV
DLq4BLaacAr7paq8FQtvqyw2V105pLmxlTnk4eN47JepK9NjIit6rY8M1QSTYD7459frGy2yccjC
tfOjjnpOHpsx9jJTtFSNNClNyKqrondR7pkc8Zjj0GAHARE0vhcSCkm227k/4giuV61YN+4dauxc
6cViRgIJ76FKVa4qFma1AiPDWu+7Q5IWtx58elGT4x9Wam5CntZav/I+HqQy0B6R7sqfHL81kmhQ
jgbut9klUGg7LRJFK+X7o6pJ/NbnWES73IpEoVSKsC83xn1W6dASQZiefePFEFoSv4vKlWovHnWZ
02nvjgepoLQ5RwcI740fnjAVjDYRN6aH6vVufohHja++V6MqRz588+pJjsI/m/S96LUTJNzZ8H3W
gp3sSF/X02mm/4QVqgafID6na0Q+xOk6FWZO9bCQI1RvetWOExZ2rlq8zPQs8tVpuO6MVuUcOvBS
IFEC7pg0vkBI3USVGP5fzwSZxDAXjTjS+6szTnOKZTY6xtyx16wuJeMwTGvXKcNJ1ECzh8yg1dLN
RHYn9NZLZOtkYfr8grMCSiOgVdWUiWyUl36wdZMKRsMeT4pRBMFRvee26hwAy9Lsy6gyCpNnZyZi
T12mc3EbFhxDBxDo3wVDUJ9O6OplX08SgvNHS+9TKOFzigsHaM7d2aESFytvDXLBm3T7b3vStqFN
mIxVE9FF2si48eCAb0ud2VoE+j4YhZ18FOmzMfnlJiMvoiYbr8PV3G4aDlPot2wJfCMYgCzB5vqB
El7Owtmf3Gd2B9Q3aF3/v1NKvZzUlxazRCBP7QvEt33kMXrcEbvKD9gmccXcKpF7usnP82iMLydW
P9zLe8JMsSs9PbQmXXFNH4VXL9foVnlR8aKcsHIYJ1gRunLp4onZL8xhvnp9IUcTtd/DKDMcwFua
f+DyT+ogiRWxIrZWvAsnDq2ZVBhMb1dNDHr2/JYhxGrmORneQSMc6i4epJYRlh5BwlvAnRN0P5vB
3MupZ5Ba6duHRO43mK/+xXc30A+I+4AM1+H2ey4HFK4HpiMvGoRDeETtt5noKCs+rb9HLFL47RnL
xGkJCseYxa6gzuc04gVaLSgNJK/47Tcv4eSyoXBUsL8D3x5/zLW7rXTqIP2g6F4IsqDf8iiQ0Vw1
t1fU22IFa1wdX1jm6/hG/L8Icm6DppTM4V1/LC81uW3NaOorkdnSbquYPijkFImufE/qzBkty/eD
BAO5CK8V6cg1I5/7OmhMXbBv6c2DRDIs6vNR9CxQP0l9kGIOTGIca9nf7tp+U8WvPjMzwsaGwzau
emWNuHaq60pHzVsFD/fKks6QC3dcE0L81N8ftH8aUEuxoJbkJwjB8cTdgzLNRbHRbeeY/VZtgt6n
2xXKA/RzgPPSOjGdsWFBgOR7QgmXnZHNz5ABHPKmjQOAPISaMvvgXSsgOZ5jP0DD0fyQpLuGRNa0
dF8dO95pe5tBK2BhOi2OAXBtQ1slnExWgWsOseXsEzlg2+8EO5KI1oZWGblDrTfOc+SyuZ5x01ra
aUjXLI3aUTeD/Sszjpj7F+Cu27rMIgAwEQyjhrzIHsxdZx2zgGCK+6vD1bwsN8ibyBK6JCQUHIWo
M/k01g6JA6bG1ffrI9b1FAKg4oloyWmXmtD0JXstNoRXGupT77VmP50wHllvRINYRTvrq3BcNRG3
KVHB1Snu2gC2KjCYNpIoO7nCSy5AIappxRn9TgNWzepb2JLUsBCJJbSJ0O4rwbmklMvJIKIq8aam
VYetHEu6dN5oDl1YRGw7zasvAjCW5KXmOmtRH+EoM69oi5SIzBD1uePGv5mIb0xNfdWS/7UvGKq5
/1+GlOw8m0DWGjx+FYcWLpyxXwh32Hhj6NDvjyAEZmHx0Kvr33hNV0TII60vuCiBtOuqrezebTsa
IzwJCeICTrgYoiOROY/L9jO/N3SXztMXbjcKlN0evi+WoMiL2d486Y+JIp8IeQuLtbO+JlJepsRQ
CdYKWlXm3ReLIJOtQydRE+JvFE2xXZh1OBRumJLpHnsYNSdWz3w7Z+PF0Bu0fGs9gt6UtD8QGVPF
AMHYwT7xTYmGk5H85J03HUjOvqCTkY46krJ84oEFYZ2e1+OdBZhub20Ee06Um18aJjerQsnDJgEp
+dCTF+otRUnq7XpAROPFFxXdko3hsjbgjsDBDYhB0GcoSC+1EwggulDS1BPYaBDg95ebc89lmGHL
WGoR/cDG9UDYf0DPYaivarrKuc1bgGAcbY9hUtYUYTeOk3oFtHy6dbEoggpSVZ25lSCyEi4evHWN
odusOOgIUa41gNvkVj+pMjryZHxT1siQM/4/9l1K9/o4sae+pYNb0gMty6K5V02gsRJ8Z4B/ydxd
XiZxfHFD7sbO2wsct0+QGhiy6MFhmTexpooNjhmClhxecsTWmBE+wnJust4hLgiC2DzHehlGtD/X
+H+ULkNS+vY3glbdILEbUPNqu6H6MFyP8+3+e2ximxEJ/iWzLAjJFfExSoxzfeW2tp8Z8FhJDPc/
JFMmiZJt4/TF0rrTwhG4Xgg51Pl9D1DG8ilptoNFcr5g9lNpEr29R4rmyE5El9Pz9S2QD2oo1ZuI
nWjDDdsmm1yh23b1I4fmG7E6/NHkcrwnBFl+cA9sGM18xwAfPE8ErGB5hZznPZO95T+OYCS2Fcwh
gdH3V0N7VGvA4IdKj7acLn/KRLhpnnTYkiG6bEEvNZuOrOVoZGS8HArXsyn4vK61jtKUD8VPC81P
jVMfR1KBLoa0vBSts1BXYXqq9GTAygWKn1qIOuu+1xxLRgBbLuXJs2BILCf+q3aqQg6VPyEDSlja
eYxrQpTI1OSXbNE5wgBDrvNVJxu/+gjUnx6qy8UOmg1dm9CiFDMrbuWhGHHhc1/x6y7jqfs7qRur
U3+0+D4k+GoL/6EhgBMeM6zmAfNT/DT25ORm3zXLh7+8BxR5/XisY5xF881n1cr62/Xs4wgQQ2LI
/UIVz88DkHe4r7Eww0WbiEkrcxpn2cNOoOkmVZ9g2F+zxyfPOaTYVvl7zNEx2JTEsUpNDOpc6uDU
fh41PwYVz0HM/KxH+CI69IoT/UC4Fo0waxwjloRTLAHDUSnvKcvDJTmaHKs/6jzXocfm9fMp8K0C
GdVueFJdN+HXOTXzOkHZFENoDWthLszI6O80/SIIaVz6pJuvWKPRsQptuK72XRfOByasrf2s1cFY
l6Q9XdJdnO+MymMzU4lKctaY4t+aeoPm2SQfh3hGYgpmub2uHa+Mrs7vlNwAHGSzPWBhtM3Uand7
k6XzIBg+Roc/IFF/+Do7NYXTgaqqhtAPxBGQnOjYuZBH2W8tbj8MZNYiwYULOrP3oh2xnTWnUEZs
sC8xmGxVcrDdDj4W9PSz2WMM3FX6LmlpNSWVXoqIFJ1jwXiCYCjaIUOeDtSgs6BKquaaagb4Zjb1
CTO7grM2SNsPnnq5ZwC+O1GqPAehTftX53y+tBtrtZ3/NOLwTr+D43K47vi/vhmJcRVvJj3CuGrx
W859ssZ7vLXx68iz7uqHrAC7ALaQELMwtrmnad+d5y+lWcTcac4tF99GfBZseDXglf/iyQEcBmPc
Oie0KzLbF0wkKgWB4hukPkHjbuwO7P1Pa0nF2OeA1jpyhpyJNAUW0dsi9nwrxySD2atH8GS7BaVR
QEEQ61v7u34DhemaAVPDAy/qjgYDg/vSxuOno+hbPmizeg9RcZ5srNfrFKMJmuceeMqGHBwpDiaE
YEeneNW5KAxwhH9a6s4G4zMJ1SkooAlh2sGsPFuFo9X6622LlmqPdaHl1BdstzNxDHCa0xepdLdz
WESE1Bcz4q7zLLHOokDMpjZaFUfA29X3dvOKDKyjKqn+WZhjj60yBInkJttyaRF93UhqiE5jQC8u
uL4yLmMQQTPFR6LFgAysHufRbTUWxndwgXpUYTKY/wfk8PjBpSSR0Yuhl5nbBlMvqpibPbk8BwSy
n3qOzGT5L2HFSGlBz0Y01XL/OLXyvamZsYGxFMtxvgbQ9mmksmVTVwla8pG6J4QhjgpC1MuAKhZk
0eFIwnEzsN2O7jWPLhNrxAIeuvmS0nBzLYuLvkqz/A9MGsS/XiJFbXKSO1i47bUbg87tss0gKnkR
NXHn/ebtyqeW1xHQsf96UOpaHjUke0MS8+KVyuiUOqSfRZPHCcNO3IIeH4hJvt8gDspmesu68xtf
PDoACBK12OT0G4qXWKDG8JsUzSKBcmWBMTnL1dAR1I2jQYw02/JEXYBHur7aSRuNa+E10CSCOQ4C
YEyrCKCzrvNfyL4apjG15oTLQU9d2258X9tAXkcFvHQgFs7gYzb7Wxc/patoTO4SEp4E0a/pl02v
oFsGogozT1qp6oh1zPXTv1MDTIQL4ooo4wHTN2t2+jRCceYNn3Fa7+NWwihr4k6Gd1RpAjLl2Y7J
3lMGaOefY7SpJhvFHv6ZKzs5PRIgxE8uaRjgG+PLOyZPNfPxi3Okolp61T9ooCELI2ZESxH1FsQk
N1eLXGXEvK9+217xUgmF6G+eVXen4HCNMRJF9mHQ/+NS0voRDT/SZZQl1bIyWjmECaCD26JlwFz1
46TxXS0PywFhIPLQRQ6QR7YEopn3n6pcUg59H0bH+G+hzPcHSVuk3Y325HU93aMpavDvUCOfCvhe
MOaMHSUKkGg+LdV+bUk+GiLYlpapGYhWZkXWuzr/WszzvQNeAqsz2lfMTZ6cUT5Z+J427LVYn5vs
byww5ju79KqEW/1rrkw4okyyAzyeEsn026L+zoA+kH3H+CU6RqMTzsr8qBn7hMLOVhecg/16i4sM
KpRm4gVArdsia6dI5K5Mmnb9yt++xTxM7l87zZ0AHN80NVOQTjKlMhj8VuHAi6jjLCvzFmdeMhX2
BR3a+C2nEU/8HVRf8754UqcVXZ/zRLMoVC7aa4FbfuuN5Wgy/So86bh/4gOINKAPmKMdvnayZr+P
+soRon+1E4mx32jpNHWA7Idhq219de7EgDLXtT7y9Q8OHRCOu6TYTDqhqfwcxWz7eomcI/yI3GzW
Pnh0CwwcYPeR/7smLM5VOQhSIJJfqu6P/CF7bqytB66k50a1e/HzeiCXe46Gm5QHEwQqdwTdR09K
BwjXcm361/IjLoAtkNGiTNSGAi79zSKQJXqIFA5QITQnbqL/rY/uAAXg9yql6IaH2rqQy+qwrixv
P2h/AYv6pkytbfdFrWt4AKtc5/Kn4yf8wKVtnfYz+U632X695PuJZAZexSLoyfyIZ9rGitosBLtA
ym51USE3pWkec4iqJjLgOhhRKbe8UnSxIMSPcHc3ietksCQxjt8RcszLWHiTZuzIjdzTdXp//uWH
yt5moJ2wSpzlKrhSGAg9aFTeqABEvVm/2njme5fdGsRmChEM337GAsY0if6kwnZ39ulIWrRG7/mN
zYiAb3b8AfU1/prmB5D1ye6l3gOdsKqMeTR/KOr9cxk5Wguc08n+FF91mlqs6bx9g0go4qL3G0XU
ukt5iMlyGjz0KwNTsmv7+StCtsk/bzdbLDo4UMNKGuJVbNlLuPDI4sImhWGK1MQ/prRHnchzblMv
Zahe3rYzqgPwVcaxwzPd14sHuP8R5g7DHgUKRnKGaBgF+uT2liZnYQlNmlyc4cjbmbGMq9wCz9tu
l9333XxIBznQ3lMQ6TruQw9ugCtGsV2Ww/6oCs6TQT9Cp1B8j0oaM1pggoy3eS8IQBs9p18g12tg
4GFaRPg6+aWwwcIPxi3Ri4JIc0jr8/MZv+rwq2NrCs5gQUiUGQHUXDBT+kfZgFcet9F3IojV9j4D
aXk739rJTh/xwQ9n49/ZSmYRudItA0fW3WvXu3vx6gA4h2eKbt540hsN7O120w5ukVlZU2f/lzhk
Sg+Ffz/4pwP1a0d7ccBCIake6G5wkD02mNBG0HFJpH3Sp2yPrKAHrGTMutvrbzkknVg7UlIQcm5m
jQSCW57+CSFP/NMHRYbqoPsTnSD0iYepOiWtjQC5pbfbHrrSmRg/R043pFCMtgHtQMi2cmkPpbtP
dQvDM0u1Tle0f/fCd94BvzMwikAJ0vn9NYoo12I42SrZ0iBkMYTcLpGjcuQ0yrl7ypbbUFSGEyJb
2AJjsWJxi1g+b14ytYOgmA9fn55x/mDW3KUVbp9TdVcZh3YmwwBhTc2knaClTKRrzf8m5ImJT1Pl
lPdY7Qve7jWwyyRpq5NUn935bwXwpfUmxtyoL/JKgGpuRSg8hgWSFYBgSg0gG9Sd3fkYht+mx4Xs
MK7foqFI2JL15BVz279/RlNOMjDCwWsomB0RzlArq33Cjm0nVG0nzcjXmK0zdgqEbLHHk5LUn5Pq
JHa3iCb3dTO1kSwitp+LxbPKwfbKyF0waiWYG3zacDeMDNWrjtTBVSNHbwJclvGKLe0U4/rRqwlA
VMICw2fO3oDPZI4JtOAEBQD+xvGMyhbYJXQPYK50/q67LNZ6VXySv81f38DXpxmxzqZ/ax5WDuQX
bKSzivBEiGb5FT+cyboZWtTdJd5Vc3XOT+Zf/2RNpinxntHPc1uM55guL39bU2quCXMiqZRjvuxc
eTGILPH1YZZPSvxGCGoFRsy1OSpUeatUY2xmY6y9A6FP4B+K3f2wB6vJ5uK5xc0F04Rnu9d8+2VX
Xex/AT91ZGBzKuZDPHU5CRDnufuXqr8Ey/0uQUyxJMGzcz5HiD2NmhhrK9n3tUcq64ht2mYmgMqi
m+Kizj+Wk11tfl6jXyrExj/W9wgztAEQ/UNGrmlSgqcCpsRoUD4QI1pfnLriu8hE4lG9jHEKeV2W
1tD16gL+OIGc/Df98ZolPQl1Eh1ZoGxpGCrLal+/NQc3VpkHmLKbkndyR8pTuOL4Wq+qlVTFeZL0
SaTtCTfDEUmpAsKnQxShnVkX7ipKK/mpVUCppv+mN//JczaQNAVzqsctilcYjSgVvjelO8PzXjVN
+lWMBIy3BCeMef7vAg8Iy+jLirm+LBATCqLmKmJfOq5DWRB85tNBPWJ8vqjw69aiXDRIGQLH4+6t
hWPpRfgbRxjB8Z6xf3FRO5toNQ8G7qVixUznk+ZQyOiA7DvcxXgDyUKedG4sB5SI8TahBMcJQO7Y
eGCTCRAEIE4wwal7Ke0aSFlmE9IOujp5tI1P3b2PlwYhHtAQbukvlbyV7y/sJJF4Uspd2Nz0zsde
S9VRco5iAmwIQRFir5ZfNGmuujRXPZ5BdYnSMt+8bfZuQW1F+G1TxnPP7411z326JhWf10/l+K4k
rnFfmXU4DXit4nutRuuRUaY7PhEhNuoLqo1SgumHcyB5b3t/0otsKdZyoU4TqKoqJX7/49CI8QeU
zzX+jwt9KV7FmE/FyQf4Iz+R+fE5UyiEJW1pO+GMAp5VxReyzkWi6wVSN56U37tOwVepAcOfGhss
y1xaE3zj/VBoCml9+64CxcIMVwIzF3wYX38S+u3eeV0UPZe1BY2oh+aokxUuy7XgLcCKWW6Xj+eY
14GqffnbWcl+FKu9zRj/aOaqEmV164pZhwxVoE+9rXO+b/jx3po8ZNry6LQbG4fm7gsvJXDrQbRb
EIeKN5+wWavU4EY9hP2EsE2RHEzODadEPDu+LgdENASpWY2pj1oDfrI5M/ZlC/vd7lHuh6kidgFt
39ZDuHCU104JMAmmzUuiGG7+4751Y/pD5YOSxTsjONWZVgFiBgK6/LZBZT4i/Fwt2YyrHpgiTl1M
Sae24oXfBqTxEzhJiCkzADkB7Ez4KrB6VZ9G4LQE559FqDgTgdqHzKjmisGWS5aez4Qnd57hJSVf
sckSrp5PGjhYR6AfI8ayYZtLAnsCQTs5aPXk8okAWuhiUwg3pYNVDmuQWz0hvPw1beAFLktHJp8l
s118xL9nT8nGWAlqHW0iruCBPrQa0rS/o2R5mxh42EHYmVjzCVihV0ESltTbu4yQ+DfbXgOUrV+H
x7dtjlERXzOTBeQFkTVjjLLk1EKBKdDGDGKUq3KgBFnMCzxHdmrRBzygxoQsp+U1tD3AesaSXgdU
NNYylJ87lS56bSH4vb2JqdMFelJdO4DUj1aevCNtpIYMjrDXBBEk
`protect end_protected
| mit | 388708f3179f49a6647da40bcb9b1f1f | 0.931589 | 1.884289 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_sg_v4_1/hdl/src/vhdl/axi_sg_fifo.vhd | 1 | 24,357 |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_fifo.vhd
-- Version: initial
-- Description:
-- This file is a wrapper file for the Synchronous FIFO used by the DataMover.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.proc_common_pkg.clog2;
use proc_common_v4_0.srl_fifo_f;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_sfifo_autord;
use axi_sg_v4_1.axi_sg_afifo_autord;
-------------------------------------------------------------------------------
entity axi_sg_fifo is
generic (
C_DWIDTH : integer := 32 ;
-- Bit width of the FIFO
C_DEPTH : integer := 4 ;
-- Depth of the fifo in fifo width words
C_IS_ASYNC : Integer range 0 to 1 := 0 ;
-- 0 = Syncronous FIFO
-- 1 = Asynchronous (2 clock) FIFO
C_PRIM_TYPE : Integer range 0 to 2 := 2 ;
-- 0 = Register
-- 1 = Block Memory
-- 2 = SRL
C_FAMILY : String := "virtex7"
-- Specifies the Target FPGA device family
);
port (
-- Write Clock and reset -----------------
fifo_wr_reset : In std_logic; --
fifo_wr_clk : In std_logic; --
------------------------------------------
-- Write Side ------------------------------------------------------
fifo_wr_tvalid : In std_logic; --
fifo_wr_tready : Out std_logic; --
fifo_wr_tdata : In std_logic_vector(C_DWIDTH-1 downto 0); --
fifo_wr_full : Out std_logic; --
--------------------------------------------------------------------
-- Read Clock and reset -----------------------------------------------
fifo_async_rd_reset : In std_logic; -- only used if C_IS_ASYNC = 1 --
fifo_async_rd_clk : In std_logic; -- only used if C_IS_ASYNC = 1 --
-----------------------------------------------------------------------
-- Read Side --------------------------------------------------------
fifo_rd_tvalid : Out std_logic; --
fifo_rd_tready : In std_logic; --
fifo_rd_tdata : Out std_logic_vector(C_DWIDTH-1 downto 0); --
fifo_rd_empty : Out std_logic --
---------------------------------------------------------------------
);
end entity axi_sg_fifo;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_fifo is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- function Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_prim_type
--
-- Function Description:
-- Sorts out the FIFO Primitive type selection based on fifo
-- depth and original primitive choice.
--
-------------------------------------------------------------------
-- coverage off
function funct_get_prim_type (depth : integer;
input_prim_type : integer) return integer is
Variable temp_prim_type : Integer := 0;
begin
If (depth > 64) Then
temp_prim_type := 1; -- use BRAM
Elsif (depth <= 64 and
input_prim_type = 0) Then
temp_prim_type := 0; -- use regiaters
else
temp_prim_type := 1; -- use BRAM
End if;
Return (temp_prim_type);
end function funct_get_prim_type;
-- coverage on
-- Signal declarations
Signal sig_init_reg : std_logic := '0';
Signal sig_init_reg2 : std_logic := '0';
Signal sig_init_done : std_logic := '0';
signal sig_inhibit_rdy_n : std_logic := '0';
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INIT_REG
--
-- Process Description:
-- Registers the reset signal input.
--
-------------------------------------------------------------
IMP_INIT_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_init_reg <= '1';
sig_init_reg2 <= '1';
else
sig_init_reg <= '0';
sig_init_reg2 <= sig_init_reg;
end if;
end if;
end process IMP_INIT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INIT_DONE_REG
--
-- Process Description:
-- Create a 1 clock wide init done pulse.
--
-------------------------------------------------------------
IMP_INIT_DONE_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1' or
sig_init_done = '1') then
sig_init_done <= '0';
Elsif (sig_init_reg = '1' and
sig_init_reg2 = '1') Then
sig_init_done <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_INIT_DONE_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RDY_INHIBIT_REG
--
-- Process Description:
-- Implements a ready inhibit flop.
--
-------------------------------------------------------------
IMP_RDY_INHIBIT_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_inhibit_rdy_n <= '0';
Elsif (sig_init_done = '1') Then
sig_inhibit_rdy_n <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_RDY_INHIBIT_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SINGLE_REG
--
-- If Generate Description:
-- Implements a 1 deep register FIFO (synchronous mode only)
--
--
------------------------------------------------------------
USE_SINGLE_REG : if (C_IS_ASYNC = 0 and
C_DEPTH <= 1) generate
-- Local Constants
-- local signals
signal sig_data_in : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_regfifo_dout_reg : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_regfifo_full_reg : std_logic := '0';
signal sig_regfifo_empty_reg : std_logic := '0';
signal sig_push_regfifo : std_logic := '0';
signal sig_pop_regfifo : std_logic := '0';
begin
-- Internal signals
-- Write signals
fifo_wr_tready <= sig_regfifo_empty_reg;
fifo_wr_full <= sig_regfifo_full_reg ;
sig_push_regfifo <= fifo_wr_tvalid and
sig_regfifo_empty_reg;
sig_data_in <= fifo_wr_tdata ;
-- Read signals
fifo_rd_tdata <= sig_regfifo_dout_reg ;
fifo_rd_tvalid <= sig_regfifo_full_reg ;
fifo_rd_empty <= sig_regfifo_empty_reg;
sig_pop_regfifo <= sig_regfifo_full_reg and
fifo_rd_tready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_REG_FIFO
--
-- Process Description:
-- This process implements the data and full flag for the
-- register fifo.
--
-------------------------------------------------------------
IMP_REG_FIFO : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1' or
sig_pop_regfifo = '1') then
sig_regfifo_full_reg <= '0';
elsif (sig_push_regfifo = '1') then
sig_regfifo_full_reg <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_REG_FIFO;
IMP_REG_FIFO1 : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_regfifo_dout_reg <= (others => '0');
elsif (sig_push_regfifo = '1') then
sig_regfifo_dout_reg <= sig_data_in;
else
null; -- don't change state
end if;
end if;
end process IMP_REG_FIFO1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_REG_EMPTY_FLOP
--
-- Process Description:
-- This process implements the empty flag for the
-- register fifo.
--
-------------------------------------------------------------
IMP_REG_EMPTY_FLOP : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_regfifo_empty_reg <= '0'; -- since this is used for the ready (invertd)
-- it can't be asserted during reset
elsif (sig_pop_regfifo = '1' or
sig_init_done = '1') then
sig_regfifo_empty_reg <= '1';
elsif (sig_push_regfifo = '1') then
sig_regfifo_empty_reg <= '0';
else
null; -- don't change state
end if;
end if;
end process IMP_REG_EMPTY_FLOP;
end generate USE_SINGLE_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SRL_FIFO
--
-- If Generate Description:
-- Generates a fifo implementation usinf SRL based FIFOa
--
--
------------------------------------------------------------
USE_SRL_FIFO : if (C_IS_ASYNC = 0 and
C_DEPTH <= 64 and
C_DEPTH > 1 and
C_PRIM_TYPE = 2 ) generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant NEED_ALMOST_EMPTY : Integer := 0;
Constant NEED_ALMOST_FULL : Integer := 0;
-- local signals
signal sig_wr_full : std_logic := '0';
signal sig_wr_fifo : std_logic := '0';
signal sig_wr_ready : std_logic := '0';
signal sig_rd_fifo : std_logic := '0';
signal sig_rd_empty : std_logic := '0';
signal sig_rd_valid : std_logic := '0';
signal sig_fifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
begin
-- Write side signals
fifo_wr_tready <= sig_wr_ready;
fifo_wr_full <= sig_wr_full;
sig_wr_ready <= not(sig_wr_full) and
sig_inhibit_rdy_n;
sig_wr_fifo <= fifo_wr_tvalid and
sig_wr_ready;
sig_fifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_rd_valid;
sig_rd_valid <= not(sig_rd_empty);
fifo_rd_tdata <= sig_fifo_rd_data ;
fifo_rd_empty <= not(sig_rd_valid);
sig_rd_fifo <= sig_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_SYNC_FIFO
--
-- Description:
-- Implement the synchronous FIFO using SRL FIFO elements
--
------------------------------------------------------------
I_SYNC_FIFO : entity proc_common_v4_0.srl_fifo_f
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_FAMILY => C_FAMILY
)
port map (
Clk => fifo_wr_clk ,
Reset => fifo_wr_reset ,
FIFO_Write => sig_wr_fifo ,
Data_In => sig_fifo_wr_data ,
FIFO_Read => sig_rd_fifo ,
Data_Out => sig_fifo_rd_data ,
FIFO_Empty => sig_rd_empty ,
FIFO_Full => sig_wr_full ,
Addr => open
);
end generate USE_SRL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SYNC_FIFO
--
-- If Generate Description:
-- Instantiates a synchronous FIFO design for use in the
-- synchronous operating mode.
--
------------------------------------------------------------
USE_SYNC_FIFO : if (C_IS_ASYNC = 0 and
(C_DEPTH > 64 or
(C_DEPTH > 1 and C_PRIM_TYPE < 2 ))) generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant NEED_ALMOST_EMPTY : Integer := 0;
Constant NEED_ALMOST_FULL : Integer := 0;
Constant DATA_CNT_WIDTH : Integer := clog2(C_DEPTH)+1;
Constant PRIM_TYPE : Integer := funct_get_prim_type(C_DEPTH, C_PRIM_TYPE);
-- local signals
signal sig_wr_full : std_logic := '0';
signal sig_wr_fifo : std_logic := '0';
signal sig_wr_ready : std_logic := '0';
signal sig_rd_fifo : std_logic := '0';
signal sig_rd_valid : std_logic := '0';
signal sig_fifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
begin
-- Write side signals
fifo_wr_tready <= sig_wr_ready;
fifo_wr_full <= sig_wr_full;
sig_wr_ready <= not(sig_wr_full) and
sig_inhibit_rdy_n;
sig_wr_fifo <= fifo_wr_tvalid and
sig_wr_ready;
sig_fifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_rd_valid;
fifo_rd_tdata <= sig_fifo_rd_data ;
fifo_rd_empty <= not(sig_rd_valid);
sig_rd_fifo <= sig_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_SYNC_FIFO
--
-- Description:
-- Implement the synchronous FIFO
--
------------------------------------------------------------
I_SYNC_FIFO : entity axi_sg_v4_1.axi_sg_sfifo_autord
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_DATA_CNT_WIDTH => DATA_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => NEED_ALMOST_EMPTY ,
C_NEED_ALMOST_FULL => NEED_ALMOST_FULL ,
C_USE_BLKMEM => PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => fifo_wr_reset ,
SFIFO_Clk => fifo_wr_clk ,
SFIFO_Wr_en => sig_wr_fifo ,
SFIFO_Din => fifo_wr_tdata ,
SFIFO_Rd_en => sig_rd_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_rd_valid ,
SFIFO_Dout => sig_fifo_rd_data ,
SFIFO_Full => sig_wr_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => open ,
SFIFO_Rd_ack => open
);
end generate USE_SYNC_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_ASYNC_FIFO
--
-- If Generate Description:
-- Instantiates an asynchronous FIFO design for use in the
-- asynchronous operating mode.
--
------------------------------------------------------------
USE_ASYNC_FIFO : if (C_IS_ASYNC = 1) generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant CNT_WIDTH : Integer := clog2(C_DEPTH);
-- local signals
signal sig_async_wr_full : std_logic := '0';
signal sig_async_wr_fifo : std_logic := '0';
signal sig_async_wr_ready : std_logic := '0';
signal sig_async_rd_fifo : std_logic := '0';
signal sig_async_rd_valid : std_logic := '0';
signal sig_afifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0);
signal sig_afifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0);
signal sig_fifo_ainit : std_logic := '0';
Signal sig_init_reg : std_logic := '0';
begin
sig_fifo_ainit <= fifo_async_rd_reset or fifo_wr_reset;
-- Write side signals
fifo_wr_tready <= sig_async_wr_ready;
fifo_wr_full <= sig_async_wr_full;
sig_async_wr_ready <= not(sig_async_wr_full) and
sig_inhibit_rdy_n;
sig_async_wr_fifo <= fifo_wr_tvalid and
sig_async_wr_ready;
sig_afifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_async_rd_valid;
fifo_rd_tdata <= sig_afifo_rd_data ;
fifo_rd_empty <= not(sig_async_rd_valid);
sig_async_rd_fifo <= sig_async_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_ASYNC_FIFO
--
-- Description:
-- Implement the asynchronous FIFO
--
------------------------------------------------------------
I_ASYNC_FIFO : entity axi_sg_v4_1.axi_sg_afifo_autord
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_CNT_WIDTH => CNT_WIDTH ,
C_USE_BLKMEM => C_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
AFIFO_Ainit => sig_fifo_ainit ,
AFIFO_Wr_clk => fifo_wr_clk ,
AFIFO_Wr_en => sig_async_wr_fifo ,
AFIFO_Din => sig_afifo_wr_data ,
AFIFO_Rd_clk => fifo_async_rd_clk ,
AFIFO_Rd_en => sig_async_rd_fifo ,
AFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
AFIFO_DValid => sig_async_rd_valid,
AFIFO_Dout => sig_afifo_rd_data ,
AFIFO_Full => sig_async_wr_full ,
AFIFO_Empty => open ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
end generate USE_ASYNC_FIFO;
end imp;
| bsd-2-clause | 582c68d03d9e081264c2a4e2e4ef3c79 | 0.420413 | 4.459356 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_s2mm_full_wrap.vhd | 1 | 94,987 | -------------------------------------------------------------------------------
-- axi_datamover_s2mm_full_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_full_wrap.vhd
--
-- Description:
-- This file implements the DataMover S2MM FULL Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_datamover_s2mm_full_wrap.vhd
-- |
-- |-- axi_datamover_reset.vhd
-- |-- axi_datamover_cmd_status.vhd
-- |-- axi_datamover_wr_status_cntl.vhd
-- |-- axi_datamover_pcc.vhd
-- |-- axi_datamover_ibttcc.vhd
-- |-- axi_datamover_indet_btt.vhd
-- |-- axi_datamover_s2mm_dre.vhd
-- |-- axi_datamover_realign.vhd
-- |-- axi_datamover_addr_cntl.vhd
-- |-- axi_datamover_wrdata_cntl.vhd
-- |-- axi_datamover_skid2mm_buf.vhd
-- |-- axi_datamover_skid_buf
-- |-- axi_datamover_wr_sf
--
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
--
-- History:
-- DET 04/19/2011 Initial Version for EDK 13.3
--
-- DET 5/9/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Added General Purpose Store and Forward support.
-- ^^^^^^
--
-- DET 5/23/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Changed the name of the axi_datamover_sfcc module to
-- axi_datamover_ibttcc.
-- ^^^^^^
--
-- DET 6/15/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- -- Per CR613943
-- - Fixed an issue with the constant calculation of the number of
-- bytes transfered per data beat on the MMap AXI4 Write Data Channel.
-- This was not compensated with the inclusion of the the upsizer in
-- GP Store and Forward or INdet BTT mode.
-- ^^^^^^
--
-- DET 6/20/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Added 512 and 1024 data width support
-- ^^^^^^
--
--
-- DET 9/1/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Fixed Lint reported excesive line length for lines 2058 through 2084.
-- - Removed commented-out code as part of general cleanup.
-- - Per Lint warning, added the ports mstr2data_dre_src_align and
-- mstr2data_dre_dest_align to the PCC instance.
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all ;
-- axi_datamover Library Modules
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_reset ;
use axi_datamover_v5_1.axi_datamover_cmd_status ;
use axi_datamover_v5_1.axi_datamover_pcc ;
use axi_datamover_v5_1.axi_datamover_ibttcc ;
use axi_datamover_v5_1.axi_datamover_indet_btt ;
use axi_datamover_v5_1.axi_datamover_s2mm_realign ;
use axi_datamover_v5_1.axi_datamover_addr_cntl ;
use axi_datamover_v5_1.axi_datamover_wrdata_cntl ;
use axi_datamover_v5_1.axi_datamover_wr_status_cntl;
Use axi_datamover_v5_1.axi_datamover_skid2mm_buf ;
Use axi_datamover_v5_1.axi_datamover_skid_buf ;
Use axi_datamover_v5_1.axi_datamover_wr_sf ;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_full_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 1;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Lite S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the S2MM Command Interface
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if support for indeterminate packet lengths
-- are to be received on the input Stream interface
-- 0 = Omit support (User MUST transfer the exact number of
-- bytes on the Stream interface as specified in the BTT
-- field of the Corresponding DataMover Command)
-- 1 = Include support for indeterminate packet lengths
-- This causes FIFOs to be added and "Store and Forward"
-- behavior of the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_INCLUDE_S2MM_GP_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- S2MM (Write) General Purpose Store and Forward function
-- 0 = Omit GP Store and Forward
-- 1 = Include GP Store and Forward
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1;
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_SKID_BUF : string := "11111";
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and Reset inputs ----------------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
-------------------------------------------------------------------
-- S2MM Primary Reset input ---------------------------------------
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------------
-- S2MM Halt request input control --------------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------------------
-- S2MM Error discrete output -------------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
-------------------------------------------------------------------
-- Optional Command and Status Clock and Reset -------------------
-- Only used when C_S2MM_STSCMD_IS_ASYNC = 1 --
--
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -----------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
--------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) --------------------------------------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
s2mm_sts_wlast : out std_logic; --
----------------------------------------------------------------------------------------------------
-- Address posting controls ---------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
-------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ---------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -----------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O -----------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
-----------------------------------------------------------------
);
end entity axi_datamover_s2mm_full_wrap;
architecture implementation of axi_datamover_s2mm_full_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_wdemux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Write Strobe demux select control.
--
-------------------------------------------------------------------
function func_calc_wdemux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 7 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when 256 =>
num_addr_bits_needed := 5;
when 512 =>
num_addr_bits_needed := 6;
when others => -- 1024 bits
num_addr_bits_needed := 7;
end case;
Return (num_addr_bits_needed);
end function func_calc_wdemux_sel_bits;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_include_dre
--
-- Function Description:
-- This function desides if conditions are right for allowing DRE
-- inclusion.
--
-------------------------------------------------------------------
function func_include_dre (need_dre : integer;
needed_data_width : integer) return integer is
Variable include_dre : Integer := 0;
begin
if (need_dre = 1 and
needed_data_width < 128 and
needed_data_width > 8) Then
include_dre := 1;
Else
include_dre := 0;
End if;
Return (include_dre);
end function func_include_dre;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_align_width
--
-- Function Description:
-- This function calculates the needed DRE alignment port width\
-- based upon the inclusion of DRE and the needed bit width of the
-- DRE.
--
-------------------------------------------------------------------
function func_get_align_width (dre_included : integer;
dre_data_width : integer) return integer is
Variable align_port_width : Integer := 1;
begin
if (dre_included = 1) then
If (dre_data_width = 64) Then
align_port_width := 3;
Elsif (dre_data_width = 32) Then
align_port_width := 2;
else -- 16 bit data width
align_port_width := 1;
End if;
else
align_port_width := 1;
end if;
Return (align_port_width);
end function func_get_align_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_status_width
--
-- Function Description:
-- This function sets the width of the Status pipe depending on the
-- Store and Forward inclusion or ommision.
--
-------------------------------------------------------------------
function funct_set_status_width (store_forward_enabled : integer)
return integer is
Variable temp_status_bit_width : Integer := 8;
begin
If (store_forward_enabled = 1) Then
temp_status_bit_width := 32;
Else
temp_status_bit_width := 8;
End if;
Return (temp_status_bit_width);
end function funct_set_status_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_bits_needed
--
-- Function Description:
--
--
-------------------------------------------------------------------
function get_bits_needed (max_bytes : integer) return integer is
Variable fvar_temp_bit_width : Integer := 1;
begin
if (max_bytes <= 1) then
fvar_temp_bit_width := 1;
elsif (max_bytes <= 3) then
fvar_temp_bit_width := 2;
elsif (max_bytes <= 7) then
fvar_temp_bit_width := 3;
elsif (max_bytes <= 15) then
fvar_temp_bit_width := 4;
elsif (max_bytes <= 31) then
fvar_temp_bit_width := 5;
elsif (max_bytes <= 63) then
fvar_temp_bit_width := 6;
elsif (max_bytes <= 127) then
fvar_temp_bit_width := 7;
elsif (max_bytes <= 255) then
fvar_temp_bit_width := 8;
elsif (max_bytes <= 511) then
fvar_temp_bit_width := 9;
elsif (max_bytes <= 1023) then
fvar_temp_bit_width := 10;
elsif (max_bytes <= 2047) then
fvar_temp_bit_width := 11;
elsif (max_bytes <= 4095) then
fvar_temp_bit_width := 12;
elsif (max_bytes <= 8191) then
fvar_temp_bit_width := 13;
else -- 8k - 16K
fvar_temp_bit_width := 14;
end if;
Return (fvar_temp_bit_width);
end function get_bits_needed;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_rnd2pwr_of_2
--
-- Function Description:
-- Rounds the input value up to the nearest power of 2 between
-- 128 and 8192.
--
-------------------------------------------------------------------
function funct_rnd2pwr_of_2 (input_value : integer) return integer is
Variable temp_pwr2 : Integer := 128;
begin
if (input_value <= 128) then
temp_pwr2 := 128;
elsif (input_value <= 256) then
temp_pwr2 := 256;
elsif (input_value <= 512) then
temp_pwr2 := 512;
elsif (input_value <= 1024) then
temp_pwr2 := 1024;
elsif (input_value <= 2048) then
temp_pwr2 := 2048;
elsif (input_value <= 4096) then
temp_pwr2 := 4096;
else
temp_pwr2 := 8192;
end if;
Return (temp_pwr2);
end function funct_rnd2pwr_of_2;
-------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_need_realigner
--
-- Function Description:
-- Determines if the Realigner module needs to be included.
--
-------------------------------------------------------------------
function funct_need_realigner (indet_btt_enabled : integer;
dre_included : integer;
gp_sf_included : integer) return integer is
Variable temp_val : Integer := 0;
begin
If ((indet_btt_enabled = 1) or
(dre_included = 1) or
(gp_sf_included = 1)) Then
temp_val := 1;
else
temp_val := 0;
End if;
Return (temp_val);
end function funct_need_realigner;
-------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_width
--
-- Function Description:
-- This function calculates the address offset width needed by
-- the GP Store and Forward module with data packing.
--
-------------------------------------------------------------------
function funct_get_sf_offset_width (mmap_dwidth : integer;
stream_dwidth : integer) return integer is
Constant FCONST_WIDTH_RATIO : integer := mmap_dwidth/stream_dwidth;
Variable fvar_temp_offset_width : Integer := 1;
begin
case FCONST_WIDTH_RATIO is
when 1 =>
fvar_temp_offset_width := 1;
when 2 =>
fvar_temp_offset_width := 1;
when 4 =>
fvar_temp_offset_width := 2;
when 8 =>
fvar_temp_offset_width := 3;
when 16 =>
fvar_temp_offset_width := 4;
when 32 =>
fvar_temp_offset_width := 5;
when 64 =>
fvar_temp_offset_width := 6;
when others =>
fvar_temp_offset_width := 7;
end case;
Return (fvar_temp_offset_width);
end function funct_get_sf_offset_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_stream_width2use
--
-- Function Description:
-- This function calculates the Stream width to use for S2MM
-- modules downstream from the upsizing Store and Forward. If
-- Store and forward is present, then the effective Stream width
-- is the MMAP data width. If no Store and Forward then the Stream
-- width is the input Stream width from the User.
--
-------------------------------------------------------------------
function funct_get_stream_width2use (mmap_data_width : integer;
stream_data_width : integer;
sf_enabled : integer) return integer is
Variable fvar_temp_width : Integer := 32;
begin
If (sf_enabled > 0) Then
fvar_temp_width := mmap_data_width;
Else
fvar_temp_width := stream_data_width;
End if;
Return (fvar_temp_width);
end function funct_get_stream_width2use;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_bytes_per_dbeat
--
-- Function Description:
-- This function calculates the number of bytes transfered per
-- databeat on the MMap AXI4 Write Data Channel by the S2MM. The
-- value is based on input parameterization of included functions
-- in the S2MM block.
--
-------------------------------------------------------------------
function funct_get_bytes_per_dbeat (ibtt_enabled : integer ;
gpsf_enabled : integer ;
stream_dwidth : integer ;
mmap_dwidth : integer ) return integer is
Variable fvar_temp_bytes_per_xfer : Integer := 4;
begin
If (ibtt_enabled > 0 or
gpsf_enabled > 0) Then -- transfers will be upsized to mmap data width
fvar_temp_bytes_per_xfer := mmap_dwidth/8;
Else -- transfers will be in stream data widths (may be narrow transfers on mmap)
fvar_temp_bytes_per_xfer := stream_dwidth/8;
End if;
Return (fvar_temp_bytes_per_xfer);
end function funct_get_bytes_per_dbeat;
-- Constant Declarations ----------------------------------------
Constant SF_ENABLED : integer := C_INCLUDE_S2MM_GP_SF + C_S2MM_SUPPORT_INDET_BTT;
Constant SF_UPSIZED_SDATA_WIDTH : integer := funct_get_stream_width2use(C_S2MM_MDATA_WIDTH,
C_S2MM_SDATA_WIDTH,
SF_ENABLED);
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant IS_NOT_MM2S : integer range 0 to 1 := 0;
Constant S2MM_AWID_VALUE : integer range 0 to 255 := C_S2MM_AWID;
Constant S2MM_AWID_WIDTH : integer range 1 to 8 := C_S2MM_ID_WIDTH;
Constant S2MM_ADDR_WIDTH : integer range 32 to 64 := C_S2MM_ADDR_WIDTH;
Constant S2MM_MDATA_WIDTH : integer range 32 to 1024 := C_S2MM_MDATA_WIDTH;
Constant S2MM_SDATA_WIDTH : integer range 8 to 1024 := C_S2MM_SDATA_WIDTH;
Constant S2MM_TAG_WIDTH : integer range 1 to 8 := C_TAG_WIDTH;
Constant S2MM_CMD_WIDTH : integer := (S2MM_TAG_WIDTH+S2MM_ADDR_WIDTH+32);
Constant INCLUDE_S2MM_STSFIFO : integer range 0 to 1 := C_INCLUDE_S2MM_STSFIFO;
Constant S2MM_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_S2MM_STSCMD_FIFO_DEPTH;
Constant S2MM_STSCMD_IS_ASYNC : integer range 0 to 1 := C_S2MM_STSCMD_IS_ASYNC;
Constant S2MM_BURST_SIZE : integer range 2 to 256 := C_S2MM_BURST_SIZE;
Constant ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant WR_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant SEL_ADDR_WIDTH : integer range 2 to 7 := func_calc_wdemux_sel_bits(S2MM_MDATA_WIDTH);
Constant S2MM_BTT_USED : integer range 8 to 23 := C_S2MM_BTT_USED;
Constant BITS_PER_BYTE : integer := 8;
Constant INCLUDE_S2MM_DRE : integer range 0 to 1 := func_include_dre(C_INCLUDE_S2MM_DRE,
S2MM_SDATA_WIDTH);
Constant DRE_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant S2MM_DRE_ALIGN_WIDTH : integer range 1 to 3 := func_get_align_width(INCLUDE_S2MM_DRE,
S2MM_SDATA_WIDTH);
Constant DRE_SUPPORT_SCATTER : integer range 0 to 1 := 1;
Constant ENABLE_INDET_BTT_SF : integer range 0 to 1 := C_S2MM_SUPPORT_INDET_BTT;
Constant ENABLE_GP_SF : integer range 0 to 1 := C_INCLUDE_S2MM_GP_SF ;
Constant BYTES_PER_MMAP_DBEAT : integer := funct_get_bytes_per_dbeat(ENABLE_INDET_BTT_SF ,
ENABLE_GP_SF ,
S2MM_SDATA_WIDTH ,
S2MM_MDATA_WIDTH);
Constant MAX_BYTES_PER_BURST : integer := BYTES_PER_MMAP_DBEAT*S2MM_BURST_SIZE;
Constant IBTT_XFER_BYTES_WIDTH : integer := get_bits_needed(MAX_BYTES_PER_BURST);
Constant WR_STATUS_CNTL_FIFO_DEPTH : integer range 1 to 32 := WR_DATA_CNTL_FIFO_DEPTH+2; -- 2 added for going
-- full thresholding
-- in WSC
Constant WSC_STATUS_WIDTH : integer range 8 to 32 :=
funct_set_status_width(ENABLE_INDET_BTT_SF);
Constant WSC_BYTES_RCVD_WIDTH : integer range 8 to 32 := S2MM_BTT_USED;
Constant ADD_REALIGNER : integer := funct_need_realigner(ENABLE_INDET_BTT_SF ,
INCLUDE_S2MM_DRE ,
ENABLE_GP_SF);
-- Calculates the minimum needed depth of the GP Store and Forward FIFO
-- based on the S2MM pipeline depth and the max allowed Burst length
Constant PIPEDEPTH_BURST_LEN_PROD : integer :=
(ADDR_CNTL_FIFO_DEPTH+2) * S2MM_BURST_SIZE;
-- Assigns the depth of the optional GP Store and Forward FIFO to the nearest
-- power of 2
Constant SF_FIFO_DEPTH : integer range 128 to 8192 :=
funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD);
-- Calculate the width of the Store and Forward Starting Address Offset bus
Constant SF_STRT_OFFSET_WIDTH : integer := funct_get_sf_offset_width(S2MM_MDATA_WIDTH,
S2MM_SDATA_WIDTH);
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_s2mm_cmd_wdata : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_s2mm_cache_data : std_logic_vector(7 downto 0) := (others => '0');
signal sig_cmd2mstr_command : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_last : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2addr_data_rdy : std_logic := '0';
signal sig_data2all_tlast_error : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2wsc_calc_error : std_logic := '0';
signal sig_addr2wsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2wsc_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal sig_data2wsc_cmd_empty : std_logic := '0';
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(WSC_STATUS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2wsc_status_ready : std_logic := '0';
signal sig_wsc2stat_status_valid : std_logic := '0';
signal sig_wsc2mstr_halt_pipe : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_addr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_skid2data_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_skid2axi_wvalid : std_logic := '0';
signal sig_axi2skid_wready : std_logic := '0';
signal sig_skid2axi_wdata : std_logic_vector(S2MM_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_skid2axi_wstrb : std_logic_vector((S2MM_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_skid2axi_wlast : std_logic := '0';
signal sig_data2wsc_sof : std_logic := '0';
signal sig_data2wsc_eof : std_logic := '0';
signal sig_data2wsc_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_data2wsc_eop : std_logic := '0';
signal sig_data2wsc_bytes_rcvd : std_logic_vector(WSC_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_sf2pcc_xfer_valid : std_logic := '0';
signal sig_pcc2sf_xfer_ready : std_logic := '0';
signal sig_sf2pcc_cmd_cmplt : std_logic := '0';
signal sig_sf2pcc_packet_eop : std_logic := '0';
signal sig_sf2pcc_xfer_bytes : std_logic_vector(IBTT_XFER_BYTES_WIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tvalid : std_logic := '0';
signal sig_wdc2ibtt_tready : std_logic := '0';
signal sig_ibtt2wdc_tdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tlast : std_logic := '0';
signal sig_ibtt2wdc_eop : std_logic := '0';
signal sig_ibtt2wdc_stbs_asserted : std_logic_vector(7 downto 0) := (others => '0');
signal sig_dre2ibtt_tvalid : std_logic := '0';
signal sig_ibtt2dre_tready : std_logic := '0';
signal sig_dre2ibtt_tdata : std_logic_vector(S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_dre2ibtt_tstrb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_dre2ibtt_tlast : std_logic := '0';
signal sig_dre2ibtt_eop : std_logic := '0';
signal sig_dre2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2dre_cmd_valid : std_logic := '0';
signal sig_mstr2dre_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2dre_dre_src_align : std_logic_vector(S2MM_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2dre_dre_dest_align : std_logic_vector(S2MM_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2dre_btt : std_logic_vector(S2MM_BTT_USED-1 downto 0) := (others => '0');
signal sig_mstr2dre_drr : std_logic := '0';
signal sig_mstr2dre_eof : std_logic := '0';
signal sig_mstr2dre_cmd_cmplt : std_logic := '0';
signal sig_mstr2dre_calc_error : std_logic := '0';
signal sig_realign2wdc_eop_error : std_logic := '0';
signal sig_dre2all_halted : std_logic := '0';
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_wsc2rst_stop_cmplt : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal skid2dre_wvalid : std_logic := '0';
signal dre2skid_wready : std_logic := '0';
signal skid2dre_wdata : std_logic_vector(S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal skid2dre_wstrb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal skid2dre_wlast : std_logic := '0';
signal sig_s2mm_allow_addr_req : std_logic := '0';
signal sig_ok_to_post_wr_addr : std_logic := '0';
signal sig_s2mm_addr_req_posted : std_logic := '0';
signal sig_s2mm_wr_xfer_cmplt : std_logic := '0';
signal sig_s2mm_ld_nxt_len : std_logic := '0';
signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_ibtt2wdc_error : std_logic := '0';
signal sig_sf_strt_addr_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2dre_sf_strt_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
signal s2mm_awcache_int : std_logic_vector (3 downto 0);
signal s2mm_awuser_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug/Test Port Assignments
s2mm_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the s2mm_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (s2mm_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"CAFE1111" ; -- 32 bit Constant indicating S2MM FULL type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2wsc_status_ready;
sig_dbg_data_1(7) <= sig_wsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2wsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_wsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_wsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_wsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_wsc2stat_status(6) ; -- Slave Error
--sig_dbg_data_1(19) <= sig_wsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2wsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_wsc2stat_status_valid ; -- Status Valid Handshake
sig_dbg_data_1(29 downto 22) <= sig_mstr2data_len ; -- WDC Cmd FIFO LEN input
sig_dbg_data_1(30) <= sig_mstr2data_cmd_valid ; -- WDC Cmd FIFO Valid Inpute
sig_dbg_data_1(31) <= sig_data2mstr_cmd_ready ; -- WDC Cmd FIFO Ready Output
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADD_DEBUG_EOP
--
-- If Generate Description:
--
-- This IfGen adds in the EOP status marker to the debug
-- vector data when Indet BTT Store and Forward is enabled.
--
------------------------------------------------------------
GEN_ADD_DEBUG_EOP : if (ENABLE_INDET_BTT_SF = 1) generate
begin
sig_dbg_data_1(19) <= sig_wsc2stat_status(31) ; -- EOP Marker
end generate GEN_ADD_DEBUG_EOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DEBUG_EOP
--
-- If Generate Description:
--
-- This IfGen zeros the debug vector bit used for the EOP
-- status marker when Indet BTT Store and Forward is not
-- enabled.
--
------------------------------------------------------------
GEN_NO_DEBUG_EOP : if (ENABLE_INDET_BTT_SF = 0) generate
begin
sig_dbg_data_1(19) <= '0' ; -- EOP Marker
end generate GEN_NO_DEBUG_EOP;
---- End of Debug/Test Support --------------------------------
-- Assign the Address posting control outputs
s2mm_addr_req_posted <= sig_s2mm_addr_req_posted ;
s2mm_wr_xfer_cmplt <= sig_s2mm_wr_xfer_cmplt ;
s2mm_ld_nxt_len <= sig_s2mm_ld_nxt_len ;
s2mm_wr_len <= sig_s2mm_wr_len ;
-- Write Data Channel I/O
s2mm_wvalid <= sig_skid2axi_wvalid;
sig_axi2skid_wready <= s2mm_wready ;
s2mm_wdata <= sig_skid2axi_wdata ;
s2mm_wlast <= sig_skid2axi_wlast ;
GEN_S2MM_TKEEP_ENABLE2 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
s2mm_wstrb <= sig_skid2axi_wstrb ;
end generate GEN_S2MM_TKEEP_ENABLE2;
GEN_S2MM_TKEEP_DISABLE2 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
s2mm_wstrb <= (others => '1');
end generate GEN_S2MM_TKEEP_DISABLE2;
GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate
begin
-- Cache signal tie-off
s2mm_awcache <= "0011"; -- pre Interface-X guidelines for Masters
s2mm_awuser <= "0000"; -- pre Interface-X guidelines for Masters
sig_s2mm_cache_data <= (others => '0'); --s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate
begin
-- Cache signal tie-off
s2mm_awcache <= s2mm_awcache_int; -- pre Interface-X guidelines for Masters
s2mm_awuser <= s2mm_awuser_int; -- pre Interface-X guidelines for Masters
sig_s2mm_cache_data <= s2mm_cmd_wdata(79 downto 72);
-- sig_s2mm_cache_data <= s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE2;
-- Internal error output discrete
s2mm_err <= sig_calc2dm_calc_err or sig_data2all_tlast_error;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_s2mm_cmd_wdata <= s2mm_cmd_wdata(S2MM_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_datamover_v5_1.axi_datamover_reset
generic map (
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC
)
port map (
primary_aclk => s2mm_aclk ,
primary_aresetn => s2mm_aresetn ,
secondary_awclk => s2mm_cmdsts_awclk ,
secondary_aresetn => s2mm_cmdsts_aresetn ,
halt_req => s2mm_halt ,
halt_cmplt => s2mm_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => sig_wsc2rst_stop_cmplt ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_datamover_v5_1.axi_datamover_cmd_status
generic map (
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_S2MM_STSFIFO ,
C_STSCMD_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_STS_WIDTH => WSC_STATUS_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
secondary_awclk => s2mm_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => s2mm_cmd_wvalid ,
cmd_wready => s2mm_cmd_wready ,
cmd_wdata => sig_s2mm_cmd_wdata ,
cache_data => sig_s2mm_cache_data ,
sts_wvalid => s2mm_sts_wvalid ,
sts_wready => s2mm_sts_wready ,
sts_wdata => s2mm_sts_wdata ,
sts_wstrb => s2mm_sts_wstrb ,
sts_wlast => s2mm_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_wsc2stat_status ,
stat2mstr_status_ready => sig_stat2wsc_status_ready ,
mst2stst_status_valid => sig_wsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_WR_STATUS_CNTLR
--
-- Description:
-- Write Status Controller Block
--
------------------------------------------------------------
I_WR_STATUS_CNTLR : entity axi_datamover_v5_1.axi_datamover_wr_status_cntl
generic map (
C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF ,
C_SF_BYTES_RCVD_WIDTH => WSC_BYTES_RCVD_WIDTH ,
C_STS_FIFO_DEPTH => WR_STATUS_CNTL_FIFO_DEPTH ,
C_STS_WIDTH => WSC_STATUS_WIDTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2wsc_stop_request => sig_rst2all_stop_request ,
wsc2rst_stop_cmplt => sig_wsc2rst_stop_cmplt ,
addr2wsc_addr_posted => sig_addr2data_addr_posted ,
s2mm_bresp => s2mm_bresp ,
s2mm_bvalid => s2mm_bvalid ,
s2mm_bready => s2mm_bready ,
calc2wsc_calc_error => sig_calc2dm_calc_err ,
addr2wsc_calc_error => sig_addr2wsc_calc_error ,
addr2wsc_fifo_empty => sig_addr2wsc_cmd_fifo_empty ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_error => sig_data2wsc_calc_err ,
data2wsc_last_error => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
data2wsc_valid => sig_data2wsc_valid ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2stat_status => sig_wsc2stat_status ,
stat2wsc_status_ready => sig_stat2wsc_status_ready ,
wsc2stat_status_valid => sig_wsc2stat_status_valid ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_PCC
--
-- If Generate Description:
-- Include the normal Predictive Command Calculator function,
-- Store and Forward is not an included feature.
--
--
------------------------------------------------------------
GEN_INCLUDE_PCC : if (ENABLE_INDET_BTT_SF = 0) generate
begin
------------------------------------------------------------
-- Instance: I_MSTR_PCC
--
-- Description:
-- Predictive Command Calculator Block
--
------------------------------------------------------------
I_MSTR_PCC : entity axi_datamover_v5_1.axi_datamover_pcc
generic map (
C_IS_MM2S => IS_NOT_MM2S ,
C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_MAX_BURST_LEN => S2MM_BURST_SIZE ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_BTT_USED => S2MM_BTT_USED ,
C_SUPPORT_INDET_BTT => ENABLE_INDET_BTT_SF ,
C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH
)
port map (
-- Clock input
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => open ,
mstr2data_dre_dest_align => open ,
calc_error => sig_calc2dm_calc_err ,
dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid ,
mstr2dre_tag => sig_mstr2dre_tag ,
mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align ,
mstr2dre_btt => sig_mstr2dre_btt ,
mstr2dre_drr => sig_mstr2dre_drr ,
mstr2dre_eof => sig_mstr2dre_eof ,
mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt ,
mstr2dre_calc_error => sig_mstr2dre_calc_error ,
mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset
);
end generate GEN_INCLUDE_PCC;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_IBTTCC
--
-- If Generate Description:
-- Include the Indeterminate BTT Command Calculator function,
-- Store and Forward is enabled in the S2MM.
--
--
------------------------------------------------------------
GEN_INCLUDE_IBTTCC : if (ENABLE_INDET_BTT_SF = 1) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_MSTR_SFCC
--
-- Description:
-- Instantiates the Store and Forward Command Calculator
-- Block.
--
------------------------------------------------------------
I_S2MM_MSTR_IBTTCC : entity axi_datamover_v5_1.axi_datamover_ibttcc
generic map (
C_SF_XFER_BYTES_WIDTH => IBTT_XFER_BYTES_WIDTH ,
C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_MAX_BURST_LEN => S2MM_BURST_SIZE ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_BTT_USED => S2MM_BTT_USED ,
C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH
)
port map (
-- Clock input
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid ,
pcc2sf_xfer_ready => sig_pcc2sf_xfer_ready ,
sf2pcc_cmd_cmplt => sig_sf2pcc_cmd_cmplt ,
sf2pcc_packet_eop => sig_sf2pcc_packet_eop ,
sf2pcc_xfer_bytes => sig_sf2pcc_xfer_bytes ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err ,
dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid ,
mstr2dre_tag => sig_mstr2dre_tag ,
mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align ,
mstr2dre_btt => sig_mstr2dre_btt ,
mstr2dre_drr => sig_mstr2dre_drr ,
mstr2dre_eof => sig_mstr2dre_eof ,
mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt ,
mstr2dre_calc_error => sig_mstr2dre_calc_error ,
mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset
);
end generate GEN_INCLUDE_IBTTCC;
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_STRM_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registerd Slave Stream inputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_S2MM_STRM_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => S2MM_SDATA_WIDTH
)
port map (
-- System Ports
aclk => s2mm_aclk ,
arst => sig_mmap_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_data2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => s2mm_strm_wvalid ,
s_ready => s2mm_strm_wready ,
s_data => s2mm_strm_wdata ,
s_strb => s2mm_strm_wstrb ,
s_last => s2mm_strm_wlast ,
-- Master Side (Stream Data Output
m_valid => skid2dre_wvalid ,
m_ready => dre2skid_wready ,
m_data => skid2dre_wdata ,
m_strb => skid2dre_wstrb ,
m_last => skid2dre_wlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '0' generate
begin
skid2dre_wvalid <= s2mm_strm_wvalid;
s2mm_strm_wready <= dre2skid_wready;
skid2dre_wdata <= s2mm_strm_wdata;
skid2dre_wstrb <= s2mm_strm_wstrb;
skid2dre_wlast <= s2mm_strm_wlast;
end generate DISABLE_AXIS_SKID;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_REALIGNER
--
-- If Generate Description:
-- Omit the S2MM Realignment Engine
--
--
------------------------------------------------------------
GEN_NO_REALIGNER : if (ADD_REALIGNER = 0) generate
begin
-- Set to Always ready for DRE to PCC Command Interface
sig_dre2mstr_cmd_ready <= LOGIC_HIGH;
-- Without DRE and Scatter, the end of packet is the TLAST
--sig_dre2ibtt_eop <= skid2dre_wlast ;
sig_dre2ibtt_eop <= sig_dre2ibtt_tlast ; -- use skid buffered version
-- Cant't detect undrrun/overrun here
sig_realign2wdc_eop_error <= '0';
ENABLE_NOREALIGNER_SKID : if C_ENABLE_SKID_BUF(3) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_NO_REALIGN_SKID_BUF
--
-- Description:
-- Instance for a Skid Buffer which provides for
-- Fmax timing improvement between the Null Absorber and
-- the Write Data controller when the Realigner is not
-- present (no DRE and no Store and Forward case).
--
------------------------------------------------------------
I_NO_REALIGN_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => S2MM_SDATA_WIDTH
)
port map (
-- System Ports
aclk => s2mm_aclk ,
arst => sig_mmap_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => LOGIC_LOW ,
-- Slave Side (Null Absorber Input)
s_valid => skid2dre_wvalid ,
s_ready => dre2skid_wready ,
s_data => skid2dre_wdata ,
s_strb => skid2dre_wstrb ,
s_last => skid2dre_wlast ,
-- Master Side (Stream Data Output to WData Cntlr)
m_valid => sig_dre2ibtt_tvalid ,
m_ready => sig_ibtt2dre_tready ,
m_data => sig_dre2ibtt_tdata ,
m_strb => sig_dre2ibtt_tstrb ,
m_last => sig_dre2ibtt_tlast
);
end generate ENABLE_NOREALIGNER_SKID;
DISABLE_NOREALIGNER_SKID : if C_ENABLE_SKID_BUF(3) = '0' generate
begin
sig_dre2ibtt_tvalid <= skid2dre_wvalid;
dre2skid_wready <= sig_ibtt2dre_tready;
sig_dre2ibtt_tdata <= skid2dre_wdata;
sig_dre2ibtt_tstrb <= skid2dre_wstrb;
sig_dre2ibtt_tlast <= skid2dre_wlast;
end generate DISABLE_NOREALIGNER_SKID;
end generate GEN_NO_REALIGNER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_REALIGNER
--
-- If Generate Description:
-- Include the S2MM realigner Module. It hosts the S2MM DRE
-- and the Scatter Block.
--
-- Note that the General Purpose Store and Forward Module
-- needs the Scatter function to detect input overrun and
-- underrun events on the AXI Stream input. Thus the Realigner
-- is included whenever the GP Store and Forward is enabled.
--
------------------------------------------------------------
GEN_INCLUDE_REALIGNER : if (ADD_REALIGNER = 1) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_REALIGNER
--
-- Description:
-- Instance for the S2MM Data Realignment Module.
--
------------------------------------------------------------
I_S2MM_REALIGNER : entity axi_datamover_v5_1.axi_datamover_s2mm_realign
generic map (
C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF ,
C_INCLUDE_DRE => INCLUDE_S2MM_DRE ,
C_DRE_CNTL_FIFO_DEPTH => DRE_CNTL_FIFO_DEPTH ,
C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH ,
C_SUPPORT_SCATTER => DRE_SUPPORT_SCATTER ,
C_BTT_USED => S2MM_BTT_USED ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
-- Write Data Controller or Store and Forward I/O -------
wdc2dre_wready => sig_ibtt2dre_tready ,
dre2wdc_wvalid => sig_dre2ibtt_tvalid ,
dre2wdc_wdata => sig_dre2ibtt_tdata ,
dre2wdc_wstrb => sig_dre2ibtt_tstrb ,
dre2wdc_wlast => sig_dre2ibtt_tlast ,
dre2wdc_eop => sig_dre2ibtt_eop ,
-- Starting offset output -------------------------------
dre2sf_strt_offset => sig_sf_strt_addr_offset ,
-- AXI Slave Stream In -----------------------------------
s2mm_strm_wready => dre2skid_wready ,
s2mm_strm_wvalid => skid2dre_wvalid ,
s2mm_strm_wdata => skid2dre_wdata ,
s2mm_strm_wstrb => skid2dre_wstrb ,
s2mm_strm_wlast => skid2dre_wlast ,
-- Command Calculator Interface --------------------------
dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid ,
mstr2dre_tag => sig_mstr2dre_tag ,
mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align ,
mstr2dre_btt => sig_mstr2dre_btt ,
mstr2dre_drr => sig_mstr2dre_drr ,
mstr2dre_eof => sig_mstr2dre_eof ,
mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt ,
mstr2dre_calc_error => sig_mstr2dre_calc_error ,
mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset ,
-- Premature TLAST assertion error flag
dre2all_tlast_error => sig_realign2wdc_eop_error ,
-- DRE Halted Status
dre2all_halted => sig_dre2all_halted
);
end generate GEN_INCLUDE_REALIGNER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT_SF
--
-- If Generate Description:
-- Include the Indeterminate BTT Logic with specialized
-- Store and Forward function, This also requires the
-- Scatter Engine in the Realigner module.
--
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT_SF : if (ENABLE_INDET_BTT_SF = 1) generate
begin
-- Pass the Realigner EOP error through
sig_ibtt2wdc_error <= sig_realign2wdc_eop_error;
-- Use only external address posting enable
sig_s2mm_allow_addr_req <= s2mm_allow_addr_req ;
------------------------------------------------------------
-- Instance: I_INDET_BTT
--
-- Description:
-- Instance for the Indeterminate BTT with Store and Forward
-- module.
--
------------------------------------------------------------
I_INDET_BTT : entity axi_datamover_v5_1.axi_datamover_indet_btt
generic map (
C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
C_IBTT_XFER_BYTES_WIDTH => IBTT_XFER_BYTES_WIDTH ,
C_STRT_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ,
C_MAX_BURST_LEN => S2MM_BURST_SIZE ,
C_MMAP_DWIDTH => S2MM_MDATA_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_ENABLE_DRE => INCLUDE_S2MM_DRE ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
ibtt2wdc_stbs_asserted => sig_ibtt2wdc_stbs_asserted,
ibtt2wdc_eop => sig_ibtt2wdc_eop ,
ibtt2wdc_tdata => sig_ibtt2wdc_tdata ,
ibtt2wdc_tstrb => sig_ibtt2wdc_tstrb ,
ibtt2wdc_tlast => sig_ibtt2wdc_tlast ,
ibtt2wdc_tvalid => sig_ibtt2wdc_tvalid ,
wdc2ibtt_tready => sig_wdc2ibtt_tready ,
dre2ibtt_tvalid => sig_dre2ibtt_tvalid ,
ibtt2dre_tready => sig_ibtt2dre_tready ,
dre2ibtt_tdata => sig_dre2ibtt_tdata ,
dre2ibtt_tstrb => sig_dre2ibtt_tstrb ,
dre2ibtt_tlast => sig_dre2ibtt_tlast ,
dre2ibtt_eop => sig_dre2ibtt_eop ,
dre2ibtt_strt_addr_offset => sig_sf_strt_addr_offset ,
sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid ,
pcc2sf_xfer_ready => sig_pcc2sf_xfer_ready ,
sf2pcc_cmd_cmplt => sig_sf2pcc_cmd_cmplt ,
sf2pcc_packet_eop => sig_sf2pcc_packet_eop ,
sf2pcc_xfer_bytes => sig_sf2pcc_xfer_bytes
);
end generate GEN_ENABLE_INDET_BTT_SF;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_SF
--
-- If Generate Description:
-- Bypasses any store and Forward functions.
--
--
------------------------------------------------------------
GEN_NO_SF : if (ENABLE_INDET_BTT_SF = 0 and
ENABLE_GP_SF = 0) generate
begin
-- Use only external address posting enable
sig_s2mm_allow_addr_req <= s2mm_allow_addr_req ;
-- Housekeep unused signal in this case
sig_ok_to_post_wr_addr <= '0' ;
-- SFCC Interface Signals that are not used
sig_pcc2sf_xfer_ready <= '0' ;
sig_sf2pcc_xfer_valid <= '0' ;
sig_sf2pcc_cmd_cmplt <= '0' ;
sig_sf2pcc_packet_eop <= '0' ;
sig_sf2pcc_xfer_bytes <= (others => '0') ;
-- Just pass DRE signals through
sig_ibtt2dre_tready <= sig_wdc2ibtt_tready ;
sig_ibtt2wdc_tvalid <= sig_dre2ibtt_tvalid ;
sig_ibtt2wdc_tdata <= sig_dre2ibtt_tdata ;
sig_ibtt2wdc_tstrb <= sig_dre2ibtt_tstrb ;
sig_ibtt2wdc_tlast <= sig_dre2ibtt_tlast ;
sig_ibtt2wdc_eop <= sig_dre2ibtt_eop ;
sig_ibtt2wdc_stbs_asserted <= (others => '0') ;
-- Pass the Realigner EOP error through
sig_ibtt2wdc_error <= sig_realign2wdc_eop_error;
end generate GEN_NO_SF;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_GP_SF
--
-- If Generate Description:
-- Include the General Purpose Store and Forward module.
-- This If Generate can only be enabled when
-- Indeterminate BTT mode is not enabled. The General Purpose
-- Store and Forward is instantiated in place of the Indet
-- BTT Store and Forward.
--
------------------------------------------------------------
GEN_INCLUDE_GP_SF : if (ENABLE_INDET_BTT_SF = 0 and
ENABLE_GP_SF = 1) generate
begin
-- Merge the external address posting control with the
-- SF address posting control.
sig_s2mm_allow_addr_req <= s2mm_allow_addr_req and
sig_ok_to_post_wr_addr ;
-- Zero these out since Indet BTT is not enabled, they
-- are only used by the WDC in that mode
sig_ibtt2wdc_stbs_asserted <= (others => '0') ;
sig_ibtt2wdc_eop <= '0' ;
-- SFCC Interface Signals that are not used
sig_pcc2sf_xfer_ready <= '0' ;
sig_sf2pcc_xfer_valid <= '0' ;
sig_sf2pcc_cmd_cmplt <= '0' ;
sig_sf2pcc_packet_eop <= '0' ;
sig_sf2pcc_xfer_bytes <= (others => '0') ;
------------------------------------------------------------
-- Instance: I_S2MM_GP_SF
--
-- Description:
-- Instance for the S2MM (Write) General Purpose Store and
-- Forward Module. This module can only be enabled when
-- Indeterminate BTT mode is not enabled. It is connected
-- in place of the IBTT Module when GP SF is enabled.
--
------------------------------------------------------------
I_S2MM_GP_SF : entity axi_datamover_v5_1.axi_datamover_wr_sf
generic map (
C_WR_ADDR_PIPE_DEPTH => ADDR_CNTL_FIFO_DEPTH ,
C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
C_MMAP_DWIDTH => S2MM_MDATA_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_STRT_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset inputs -----------------------------
aclk => s2mm_aclk ,
reset => sig_mmap_rst ,
-- Slave Stream Input --------------------------------
sf2sin_tready => sig_ibtt2dre_tready ,
sin2sf_tvalid => sig_dre2ibtt_tvalid ,
sin2sf_tdata => sig_dre2ibtt_tdata ,
sin2sf_tkeep => sig_dre2ibtt_tstrb ,
sin2sf_tlast => sig_dre2ibtt_tlast ,
sin2sf_error => sig_realign2wdc_eop_error ,
-- Starting Address Offset Input ---------------------
sin2sf_strt_addr_offset => sig_sf_strt_addr_offset ,
-- DataMover Write Side Address Pipelining Control Interface --------
ok_to_post_wr_addr => sig_ok_to_post_wr_addr ,
wr_addr_posted => sig_s2mm_addr_req_posted ,
wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt ,
wr_ld_nxt_len => sig_s2mm_ld_nxt_len ,
wr_len => sig_s2mm_wr_len ,
-- Write Side Stream Out to DataMover S2MM -------------
sout2sf_tready => sig_wdc2ibtt_tready ,
sf2sout_tvalid => sig_ibtt2wdc_tvalid ,
sf2sout_tdata => sig_ibtt2wdc_tdata ,
sf2sout_tkeep => sig_ibtt2wdc_tstrb ,
sf2sout_tlast => sig_ibtt2wdc_tlast ,
sf2sout_error => sig_ibtt2wdc_error
);
end generate GEN_INCLUDE_GP_SF;
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_datamover_v5_1.axi_datamover_addr_cntl
generic map (
C_ADDR_FIFO_DEPTH => ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_ADDR_ID => S2MM_AWID_VALUE ,
C_ADDR_ID_WIDTH => S2MM_AWID_WIDTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => s2mm_awid ,
addr2axi_aaddr => s2mm_awaddr ,
addr2axi_alen => s2mm_awlen ,
addr2axi_asize => s2mm_awsize ,
addr2axi_aburst => s2mm_awburst ,
addr2axi_aprot => s2mm_awprot ,
addr2axi_avalid => s2mm_awvalid ,
addr2axi_acache => s2mm_awcache_int ,
addr2axi_auser => s2mm_awuser_int ,
axi2addr_aready => s2mm_awready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
-- mstr2addr_cache_info => sig_cache2mstr_command ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => sig_s2mm_allow_addr_req ,
addr_req_posted => sig_s2mm_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2wsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2wsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_WR_DATA_CNTL
--
-- Description:
-- Write Data Controller Block
--
------------------------------------------------------------
I_WR_DATA_CNTL : entity axi_datamover_v5_1.axi_datamover_wrdata_cntl
generic map (
C_REALIGNER_INCLUDED => ADD_REALIGNER ,
C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF ,
C_SF_BYTES_RCVD_WIDTH => WSC_BYTES_RCVD_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => WR_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => S2MM_MDATA_WIDTH ,
C_STREAM_DWIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => sig_s2mm_ld_nxt_len ,
s2mm_wr_len => sig_s2mm_wr_len ,
data2skid_saddr_lsb => sig_data2skid_addr_lsb ,
data2skid_wdata => sig_data2skid_wdata ,
data2skid_wstrb => sig_data2skid_wstrb ,
data2skid_wlast => sig_data2skid_wlast ,
data2skid_wvalid => sig_data2skid_wvalid ,
skid2data_wready => sig_skid2data_wready ,
s2mm_strm_wvalid => sig_ibtt2wdc_tvalid ,
s2mm_strm_wready => sig_wdc2ibtt_tready ,
s2mm_strm_wdata => sig_ibtt2wdc_tdata ,
s2mm_strm_wstrb => sig_ibtt2wdc_tstrb ,
s2mm_strm_wlast => sig_ibtt2wdc_tlast ,
s2mm_strm_eop => sig_ibtt2wdc_eop ,
s2mm_stbs_asserted => sig_ibtt2wdc_stbs_asserted,
realign2wdc_eop_error => sig_ibtt2wdc_error ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2all_tlast_error => sig_data2all_tlast_error ,
data2all_dcntlr_halted => sig_data2all_dcntlr_halted,
data2skid_halt => sig_data2skid_halt ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_err => sig_data2wsc_calc_err ,
data2wsc_last_err => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_valid => sig_data2wsc_valid ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
--ENABLE_AXIMMAP_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate
--begin
------------------------------------------------------------
-- Instance: I_S2MM_MMAP_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registered outputs and supports bi-dir throttling.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
------------------------------------------------------------
I_S2MM_MMAP_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid2mm_buf
generic map (
C_MDATA_WIDTH => S2MM_MDATA_WIDTH ,
C_SDATA_WIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_ADDR_LSB_WIDTH => SEL_ADDR_WIDTH
)
port map (
-- System Ports
ACLK => s2mm_aclk ,
ARST => sig_stream_rst ,
-- Slave Side (Wr Data Controller Input Side )
S_ADDR_LSB => sig_data2skid_addr_lsb,
S_VALID => sig_data2skid_wvalid ,
S_READY => sig_skid2data_wready ,
S_Data => sig_data2skid_wdata ,
S_STRB => sig_data2skid_wstrb ,
S_Last => sig_data2skid_wlast ,
-- Master Side (MMap Write Data Output Side)
M_VALID => sig_skid2axi_wvalid ,
M_READY => sig_axi2skid_wready ,
M_Data => sig_skid2axi_wdata ,
M_STRB => sig_skid2axi_wstrb ,
M_Last => sig_skid2axi_wlast
);
--end generate ENABLE_AXIMMAP_SKID;
end implementation;
| bsd-2-clause | 69e6157abae4c1933684c738a66ab3dc | 0.452241 | 4.159165 | false | false | false | false |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/axi_utils_v2_0/hdl/global_util_pkg.vhd | 3 | 87,227 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Tw98mZk6U3T9YTmAG0m4q74szHtuJJVfumtsO1kNgk07GPuNul0CKqjDe2NoQberdWMUtAEKlYgH
cBTWAOl2bQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
pnUW0ICIxfvll9MnxUjjppIaxe95jFGa10cooTr1nxZxMIohGCol+7PGM8KE84c0CxEkwhHJz/DJ
UlBQXiO3o+3zmZmp8KDalW9POcBxf7n8bSYG30qFTM04Bwmly0eWz4mW68KNhyowfjaiNTOT9P1c
F+jJbN9Rv9d8phnEdBs=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gnhvckv5qjwjOzlRuAWsm9wEF/8WqyRZsK2MwpbaTubIJv6pz6VLnqXjBdjeWo1WY1vG5sTvKs/X
jrwoT44P5bXbfl3UkzzCJklzIrVX0BecHL1IZhAv9X96d7w29r3ACZWobXFT1DGlrTp6dBVphRNn
gE0vluBC5DKHRhaOL32gld9aHrpQsC3l+rGO1ufXREmeMyeJI76Pbcl8iaYq8HH14jCMrGK2ioZv
rTKeGaxQfCxz7rZPyQqvt0tPn1LG45SFdrVds4i3R+GdYhWxLcOMQQZqs6jBuv6/r/IWA4Dm9Ibf
THZfsT/wOR81qklUHG97oGMaNTKeR7/A6SpAOQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
od0zl+rzCEjsmP1X6+Qwt/QSA2WVHaYLiuPTzGw5CO+ujpWrCbyx9EP6Eh8PZnTGnyFrr814Do8F
BvSImJITN9ONr05tn5QC7S3WpEf7kXbSA3w/PIsbHuQe2kBZcHnR2rSCjLe3t62FTHRDcGNBHgeZ
VNynCwJHK3aZBREol4k=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
CEDTW6JUGroUrWbDTp/1yMXL0mbFjUlEcOj6H7TIFpppM7vzYr1A0FpDU/Gs/g/yLp3Nf8zIOSQj
h97YaBMTyn1Ga7C/o6sdFeiseppjjwyBAHxPMSiqEfxS+To5WsMJxnJZy9WLb2cXVS36ct+onubM
cjdRedhOw33lB5wXf3L7htZbpSbsmM+rCpAhMu2cBAKOsEsbsKI4+kKy+LWdWxJbeBlXX42q86q1
YNjMyXT/sxWffDxjPAiW5WEwFu1VSx/X/PEYtzqsd8hCIztMeOG7tdxOgVZgW+YKJC3YRqf8b5Fm
gLyRr+F2u0+VIzOljO1X/a0vflr1ZEWBD7buNA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 62832)
`protect data_block
dTlLWOERQ157yCIP3AVUV1SWyqIFdiQvTQQ1qxRh3NIN3CLbfCF30hqq8dhzc7aQJxz4j2cuWF4c
8899mk+4h0dpe8cqUfoGcszN/n3j/r4PNHkPb92+0hWqqRTdsn4Wo2trHNRIwoAhXqA6CQQTh8LD
BOIMv9Ixfx2rkKJitvjNsPfBcNH9uKE3me3ykywYi8x4kdzVtHwxAIROfC+G1mwqb+/hLvmXz8Be
6XH2RIZhe9rp7OlGlfGpl9jCTvMLktVumbs/vyqY0QyaWnB7++c/zvticbor+p1jXjxvAfbiCab6
uv5WETQyAUat5jse/slXTvlKyvQVn5KgPPdXG2sRYtwl2qQE+YD3XisEwKcYFOqV8VL6LS25kJ78
cWVE7wYpzwaK5JHHRrC4nunOOzjOXwKQW4rH6wwFTq74BszsOOebJ7i3Ck41EU2PxNwl10pmhxQl
EcGYhfC7vtQ7jhkjT3TAKWJzUAiVLaMsEYh2APz7rq32ZnHBFt+u1Fogf6x7lWrac4U2dCJ+Hb8b
hFXnrMVlAB6ti2N0Bz5SkeWzCKDzcIsDSmc3CXKBoEcQcYvkLq1Xt5oXPpFs2nieqj+OwEFGAbMd
D+X4yiScDLLYbHN1eE6mNri1SuapytDSFqpazCpk2IVK7kW+MD7/g7OC6POxD4OuiL5pBttFNvCy
CV4ie5NhHGMt9llua+rxXiKSmtNwxfZl6MotgXXMCb7CzW/NRc4GSIFGZJH2/bkQja4xOHfC8D0P
vavG3qm104wFnEjbKXAQdr6Qdt5tF2/+K9ubqcJsdzW3LZhjlkRRIudkyUpl7W8aPh13EtkxNaYD
YnSYOSH7CMoAdrcmemcjz6w5XFFP07hebZQCCSSkzDxRQSvNXhQoh6Wn1P1TBFJBn+DS6iIzNemF
+lG/3KK2fHEllVIZha8HiwoWyc8sRgMxCzXjHxBexTE23z0EDsqiIZpaAPquGzReIUJCKNiU+Eet
ggOIxVFpPpOcypEoozM0h2JwowDr2f0wbPo4Npg6N72UqB9tIL2EePFKh/qtvPtpUhvgyuXsxOf/
T6OuxCWfe+TUgMISjv+wyX8Z6NyhjPctg7xCtus6HJzwL7gs9COn53UYvCsVhB5J1aKsf+V6GqXv
KfswRIk7/JgNx2p7yOOqDBU+wPSFpHprKFfmTos0rbPAkbIEYLFOuotUZw/a7yCmSsopceuzSldX
89YIfy/PVNy28oiNJ8/QOqEUuzeg7s5vE+nXtFvgDRxlJoflXp6lXOaNr6vc3nbKXUyOZozpcChh
knfRk3tgcy9TJq+qKY00ETBWp0M2EAdGBGI2xZ2gJX+zQHsn3JohSp+rCllSGkndupdj5zQn0l1n
Tp4iKvgaaRi1pQXrJAGp0p1kMTaSrJLNbkz9fgo1XTxDRTBkldLPj8Ah6nx/w7VvG+uxXNRdKv2A
4TMOKZy7oXJDZS4fjxu4w5nU65BRqujHoAGEF7itm6XJ1AtEzZmm9vA1QeZCw+vRIfrv3Qc8nM/0
oWMEt/wKw3eZRawNB9qrUY6FTb5i8vYhflbC7I1DJMOggTa0WfU7REjqJSrz9jIEXUwlNAovScLw
lQtUQRsuqHi5NCzS+JY/DVzbzisDLymKzHqPkn15i23VIU/tiQNNrP3jjlGj/Y7Hq7HROpRbd0QC
UzETc+LpPI1znSK5TPArmTMzvAlbE9vBSR6kpgSzeaQt3fq+uBs20A3KWkBzJLJ/h7wVQVmIhk+j
s9DPTCQ7DFO5ZG9U5GGv0PN9zZfv3okAJQF9mI+AwI41KOBzU6XUH2smW4jEZWauP5O+ps+m0vGN
i9ykogFljueDA9nnbWftb4lKLsCkHdLakHQfuU35IWZHSc1q/LpK1pqEG7Pivfzn7ALFOGty8T6d
Wv/WT1ebfOX8SR3A4PYmiMn7j1Rq5FkHoYswSn2eAn+tZL/fAKNGuCpelEwIvrGe+LaCaFNE75h4
+wAD0t18bu3mqCfMo+6Teh8RS/aGxHVIQlMxATEEJh6jjskwwxsLHtIPkIsJJUvRygTeLGeX4vvF
uGXMD3sLji9Ee1Mdp8EOK1AUNAXspgMuRVrXSCi/RLHsAAVTqXNXbzIoA+dlFu6MKMSFpVlZBFCQ
B+vMLqycMQud6Uqr0AJGNBjNg4+WI9agDX7u0PyLaOx0SgoSZPx6WVLVz6SsmF5hnnQ7Lbsql8lJ
eAxINWTemzVIS0SLu2UdfyELlGzNDs+XrtvxL/vhbRkzS2ipNrof4T4jSfG1x7sODEJLgDBk8iYB
ZZOLOpqUvKJJngSDmD4X2c+TTvPAtj0oU5oLQ4R1txIwbr2GK0X+TT+nZt/rgnUYz/S/mYeN5HHU
/d7fOjlx7lTw7hOF5tolbD6ok3YzqqyL/JgeEC5jBwvjBP5Uqe8S56ohN5hEe8ddc3xQjisjnO20
W+lpcNKJF7Teg19ywkhSDZEV+TNi9Jq6NOAHw7Kndl6gpjkOEQSyzOQ9QewKso2sYBi8h+Dv2apB
VBLrEwcMDz35WnoJP5OHXGEidHAbceqWCEtGFesnPZ2iD76PTaOI5BOsnJXPP51oN+MD/bicI2wA
EsPO9BmfYGwjiiAQi8ILGK64WLKgtHeeZMk1wZzEL9o8rslLpNmr8LkXbwe0HnIySK6G7LxmaGiW
LkWLJamG4PJPzw4afXDhGUHZvu8vEA1Rv2TGj+S2hqYyZXLIaXCcF83eA3Ia1zYrstUdypoqb7Us
AsXEMNX4a/FmZv1ZGnglgZCJMPeXUWNRQvP32MoImFKOY5UEgthhasVbjIQeqmHVkxKUIzBOCeKL
BuaFHOnk/Y9KK8prr5Uyyv9WxNuQIZaWruTzDG28HF1JwDx8/qnK/uJKDNS+lA+zJzvTneQ7TSeq
MdZG5d+IVOZfnqqKDPiFs62Lesjaed7k8IYBv9LqXW0KDmnRK8GoHDp48oweorONy/hwckt23XW+
61yVSmty9NZqRCkFpfotO2vcKaTqRFNbyEYxxnUF4uD+Ps+eLyMGKCGQqj5SxQgtbGkuMg+7faSH
M3F0dLAFDKSTPnr92cVAtZvhkJOOaKRT8LCwebVPN/Cq9pNcCiDDYQj/tqXspnKyZppbPCX024/b
xAqMyCQQBukiZPaILc/Pz379bay19KuL0JZYipQUW1WFNvC+O3GFeotLZ6VgAsXvkvCQP0AjHbZt
zsPJDIu9EOwRzO5YErYwgqGJC9Q287V8e9e3BtRsJgNxJIVZcQgW0jZ5xWqcYFVZAbvuX0Xcz5WW
RYPMUJlVtkZP2ukErDDrw25jv7X0qhpAXyDJ809AC0iOELvgRzMGW0WGQOF5fNJ0LIB5YR+tMtVA
rOXIb/lsebFSwjMVpmYZE7u7tq3b+YgpS5ACslPuGkBeACymCldk5J/vnqWOwaIs9nIESdToefxC
3H7oGkw4QQBPXJITb8un8jJcmI6haSLkE+fmJ7rmUqf3AvW6D0uehFt7Zvr06XL0TQL08kl4Kmg+
tX5vjMs4kqk5s9LO2R7/fytSKcoSBCKTI+QcLk5HSKPh8N4aO5qHKtf2prvHvaIRo0LNwzjXDMaU
PwhYc56Do+4C8AA7WPpfNPwBAU33RfoJH4Ij85BtYmRWPaxo90SKE/gzb4TXeuB0Fk2v44Kbsca4
BVfjubqGkQ/2OM241JpimD5TmKsMo0VPOFEu0S69KngOPTAmjTSAM5m1613KwcvKrIwI+0y9k8VA
36H6JOLg5nM+gobwP0Wv+J2FqswkJXxbJ0nPWnClgDCMVO9Pa6I9ngMNq/iubJtd/5zDYLq3Ue4S
Gxks5BED8lwtNw6HNTn/yHLJOOPBQ4bgqacYK1a9zbzf4prEDlrC25qs5O9IOdHrCXEU+yriCcwg
rztRCQzHtdl4QcSYNRP8KTTVQcHRdeSPf6gY133yaDUH51w7+kSGjHOzM7xTKFaqqNpFhllv4CGt
xr7gDF+MSD0VKODpHCMK/VWbGRtAoJpuKwKqFvpLLWjNZgW3pu/3Zwkg2280VJ51YdON7Vzuw6bi
q/tlCJygtwj3ORj7JTODpqkH5/nTHG7UOdKgzr/6Pz+8e9WcBQdEfRYPI5dUzyARlhAhNEcw0XdT
WlFIhfcNceBlWQOLGnZsLCdtT31J/I7Yw3Fzk6TWz1b9PL8D/Sb3EfSFanHCLJogJBH0AAiMhPD1
aky78BNc2HBTJXn2BKkZVLTlcltcGXiHPvxeVpWSjOZIo6iUpbJVkJwqXkuVvpCyh2p+X5QIOIY3
rFu3QMKpwCKNaxuLzhYo8iRwMZXG4s3CDz9lOfj9hrSyyFwMY/bhUX8wiYChJPOl+QKkrKa+r0wl
hvppor0xJ2I7wqhuav6j7s5C6V3R/LzNWwIiqgGhLuX8AJAvRUtWC9HlvU5OaI3Pt2TNacBp2f3q
0yO4ouWDIlO64638haKxTQ4DnkbkH4uSDY2vmMv47psQSouPhCNdjPPwADbZ291hTpS9ejd9NXNZ
lCBDEDjjkjjbmskJ9kyhiPdOo4+/ZqfT7fgoteO8gwECtdJD1wjknc97Pr6zzXVW33riJj6hCc/p
ae6ptd4WB3yEkYeZTk4DllLpcA8iId8f0m+dajuebJ9WZ2uBlJlOhZxENsD82eDZYRXH1JU8j1KP
Sh8v3FLWI9ZBkt2JCAuBjKaquV2LESuCWHysfFKRneB2zN1GjAXoVvMAUavRDw4q5yCOwxYFiTtq
7lOxVRVoGU2b89c5BYjxLJJACIcVJvb2C8CnEu7FeijfDMv+NIduf1XaiejncjvsNLusHp2J90Lq
bvmfBumd/GyffHK+FEFePt8p+FNj0Sj45OEyRYB7I+C46mGnbotAIR6xbeTkDmB8bhlAv6nO9dbk
jl12/crSlk0rNWKNHIUs61spfOeQZhl2UeTghhE96NOwvaO/Hg7aDT7lCgnZwgG23EUKyTE8h19w
NkzPkQc1bBO6m6/8COiwBlmoNQVADjMZNvA1C1Mk3RYilMunu1/+slJxiLsRlXQhErpH0VlWGHrZ
Av4lodiianG1wYq0qyGbMzH6k0D66ecXmpdYNTAREUwfu2Y//zIFEyToiGT0SdjB+meil0wcpxBI
QdfdIjRq2737PKOUt4hEqdAKHEDjn14d7U49fbT2uSzadSBq+eGY9wGx/qqPU6XQ7BQekp2hzawD
tA0rBxoniMb4IbXuzXfQhQLc0cq5n6kEXJ86nfzY8TAnuO+k/XyOPR4P0gd1ZGWIRNVELBerVafB
NYtBkjXiWy9lbXPrPV8n5pPaO2a5J9A3qIFZhF1SbDiZ0YJpQFC52CES2cSUzvZYmCdPj23MVgNU
0STmdaCMIUMJJkuaGfX43+jnRO6oIWCc/cnkBlBjKt4k3UAdGk5CNrZjwNaRrsix1Bb1RPvj6YWK
OMjIcSm8IJjfYLavC2gfhyTT5o0MRevXNO4QPw3ZYixHQDt1Q5gsX/4xenkfAKLdZf1Nbb+FvV10
WERuuUbCr5O97pD1nyaN+E61JDfOlAmumqdsPtwz7VGH89FrycGdqULYkRN5uXHJPQNOtIu4giTx
Vl9S3YiAjOVuEC5IPYW8IWfUHiRf8a+LZYLv/7RG6TpzWat2ulLY7aAoreu3qMOP4lII0iQq6etN
cTJWucIf0OOrahWB28xWWOazZsWEGJBA5/tyukt/CkiBmwLgdPLnZcOWE57wcsoHsm99NpD+Dyw9
6FfsF4jGZfLz40s927kaUV6jOK19Kw+RxzGCRFMpVqocLy7KGJjOdtsJoo38g9iQYulXEEZxVEqp
PPHEiiShdfP0ShZt9MxqC0nuzn7i7+0vEorYuyvP0+K8KcN1d192HOCgkFZ8M+8XAMulW81PV8gQ
qX2eSnX29stsMGIhVyfuu9lHnJRMcXZhpI96jNxXLgzUnG5GNjgIZUTfebK/Yz6i51h58lKg9SZd
WwQllUT/SvkeCKFr5sWtUtPTF5vUtQKi6/1N6aUlf1oUxUbT7IFiIKzTivozqcuDCVAh3mHnlrBb
/jNhiz5EhVWSbPV0kfCG/jpwduIAAFXelKv0vRygwaey7MAlbNh0TpdX+LfDStdW+EfRZLS+2WIU
NTZAMXlrZ3qRqQTxK6BFqWVPZ+UznfyQi6miJKp5SnRdzrcq0fmlZkHcL1sEsHQVsEnFRcQYEFl2
4++0lte0mXHlfj3AK1MjjIdjhYK8tn0H4HADuH/E9gLyNNRgyTVVvhiIG+VFNYHs4tIpR8P7w+/i
MOSjOOOWR1ufF9itv6C1Rpjgrc2N0mhgmeRwXgm9v118ptpO2RhkuTBAV0K55OXfaZuHXDfhVQWP
pQFTdUtANGMfshNLxndp2l8toZaF78GMAIqt7xlfSu47FL429iAcspzc7GsPz5c9ZfQweQAIrAQa
kQsJ8r3d3dlpiKyGC3Nrz3SENjMicHKYHC3mjycRRAHnx/vp7JEezEOpB1zweHR7ckZo9umNPeCc
kMXgX58hhYEzOEjqSGvGv/4wTv3NXO8GqXdc4lur6RhiJs4LJHhmRC0gXQC9N/2qRAk3YHsy9yqS
pEAk1Lx4twD62zjfRqE7JYsbxWY09FhKQYPxNhkRhJR+N1v07J9cSHXNNRN469a4YD2+boyeVzDr
RVuGDmuB9xvT35jhbcCsn50xF1mYoC78msW9tgAzX9UYO34gZkUJ+/LkgA62+9TdaUyPlIPHCKDt
33UMk0z6kNYsixDw3WTXfZMSX8vQoL2vlOWFyzSzjqMb3QOkesaOfP9ZFI/wkuwnC5dPsfiDOxll
lgD9kz29k89Nn0YPOwKYPgnxxqU2/fMZN5n1vDNKRpBD1yp9oY+h5HNb5rMTk9FM49sRc4nFt7mj
tDBw4qNBlWpTYUXqeZMDa2eTbaiOu0QPaL6YkeCLPL5C7tjfDoUF1I8ug71KewIrN1KkCzMLqdmM
PMNiaiHtXWpnBOLGS4Fh/Km5be3o/dqH437UzM2Ql2jAt8O2ArVVamqncv7oPnF9r/Znab/wxJjg
RFUJj9pM2VCsXEezIZ2tt/yQPgWvYUm8B2ahOsCwEiwlqMvvtrdwgsrUiAfcoeY0vk57SZrRLcOc
TguPw88Tr0CyNRw3FAqGIipUD5pvOcZO3rd7htpm0TmUlqwYrxqVoxUa+Q8AZmVBSQjuRinhZt4D
6yG0kqVplab9C8JwH2ZCvNZ9jlBS+AGAbWkZnwz9SHYcOFYdofrPIQXCkoxqPsmqmQVLevb/zIDC
4SSeW1E6tdmm5x2CnmrxvHKrPPn0bI3jeFshjt9p8owHl+Rp/MZoBsH1A5TngxJqpdu0Du6HthgK
VVigQ0i8LlieSpRMIot/YbRoc46RnHOLHB++xsR1AXPxaitRRtBHFcaQ0NLjoQapMxKmrZoJMDs4
FMQSDZyyC+iYnP6oCnURirFFUCpUzlJmQxYDWM5NvyfqrbcvmbMT5mfSPJ5HmXAGPMw/VuTb4GcR
rGEIB28hjGHsRxbjqbpT6mDuMuIeQ1llCM419Nwbrq+mYnqoFEvQZLqiseukfPXgmYsVZqJu0kZj
cHNJ3LRRJx86yh2KssJ+a3BSj4uCO5OmWDz13KjkUsGcS+DxpqMt12xMb6T/hpk20w4Q2lxtF1Zs
I9FPU+jPvcjq6Qa89f2vpK8B6ho2myvP4qeGyhdHGL78MmlYx41tUQt4MJZPI82B7kA46B+rM5XY
BlVZCdy3T+Yz0RoUPWsY1f6DgzdocHUxmQndMzZF1s3f2cktEeynTPBGfQTpGnIJMtNU1kN7UlkH
ifjnCYyE/lFlCW9NzgpRQ6H2uwucQvn7uzfqjSfwrZeClk1rXumwGsjZn1sTMaFHg3RJvgUEmAvb
09TrvVhQH0BfXk0VrW8gpuKMia0t68vN4+Z2vV/uS0k0UOzFmxHcmzmKUUQbyNkhkQ0H0+Q5YW/D
JkbbXxvbBDHDiEa7EljOxqF34V9UbkrCvJVBFdUdI7fC+1K9hUzILdSHEWq/6RyNebG8AWW7VAKO
2zrjyn96P+4ExnAQmIboB6XfCllYBYz09H1GBi8l9G0pC6KYyepNthwg18WfV3AEtvCFkI89btQn
O76vguqLhFnAWtnyXuere5MCxrHLjmaZwqpVnHYzV8SJfFzFqakQsZCkOOvcb+337f6JWmAwwoJC
JCKV3MU8zM0h5uZivUswsrcMBEWOzoaPQZZzHSHVBhGT989e4b+bstffenFasyzoE/0iNg3SbsnA
xN8rRT0tBLDCUKn73H+hRLyNeXbhcFSJvQqbjZL0T/goifFHWhhhZeGIEZqF3jp7g03expAXwp0Y
Ms7YnjgPGdKCo2RKqCTkcEw7bmkrGGbowBUTCQzXSrwx2fj05Q1DsuVzy9V9o/5/PBbC/4BLvspy
VAzpRmiv6+wwxsi04mthg3aUAIVUeDV/432u13EqOvUrq4xg2MtwwGYMv+A98jjyiD4CRWIQzuPh
ghAXXliRdOdZjNqa2P1/+w3AXu0+i0M5f1kY+YWNeNZB0PS1JAMCWJWHuPT5GqXWw3mK5Zsusq2L
9i3TFw0H+w9YWUdwqh3jTTPzvG59pFjZ2eoxLij98jb0Le1duo/6uheGDr+tE/UG1I+VQK6yUPhq
M3j1LApZtGVvDzmOoOzuaCgbg1MAPjzL9BfL2q+gZQLddwaw/VCLJRZ6vfd6cqzEwdVE+SsjCLVq
0Ps9fTGbQBW+yT7huOqJ0oovx/gMZzGGuMTCpv5uGU/Mw2FJ5oxZ1ZSDgmUZO233oJNvfwKFLIZ8
dvcylOwPoKkP218eQRIyrJn+/HAOzdm6pzaaImr4YGaZtfrqof718nra/B9mtDAvfChT5cbH5DLm
6ubc2eK+BmpjOw4kDbFZp6ZU4w3qE5yMqy8Lsi8Jq0uEdXUKpTd+lzpbmWAxApurGTOX1z+XdV5f
zyCn9/WyHsIN1Qluve0Mlw0MtmV8v+aM2T8rrdTzx2IZDMpT5tJ5oyfsqEi91CtZlgVObQWz5aXk
cMx44VVw7+c96yDiPicYLzf25OEDZ4gpMTa0FppOWxaSEQ3juMezS9AQPWgS6DYto7Gy7o6uOtAW
91cd5s14jd2vIYksckRvIZ3x9oIwJtaRHn2CycbbG+rtcWKyWR4SPVn9DDQwq6rP3d5Ko55Jq2Hf
9RmvzRLOLHfr6kRX6jtTd6RNZnIqh1YKXSFpPKhw5ioNgu5UTHCTCfrU78PBaQc371m21IjirgOQ
cliRuGSWI9chwexDENbn3gCgnXDTpBiNCNA7Zi7n2qydIWBxzFZkeKZrvINZooopYGUCCWe5Kinx
n47yhcfFAxhkp8hRIPvLkDNmduJ0yEeCzyhWzz+H38ofVXF+rkcCh+D/z0WnoDrzfJwswawDO9sh
34wGCY8Zuw0/efnSPOrKCHb3rcJTVrefFLCmLYlASJE5dVY+LzTENdfOOXay6i9jvi0nQXKx1OrH
JCGGIGOgh4njXxVs26bwJxvlkkb1rXUVMM1iOGpvTJRIoRH8GVzuu4L99iOZDg2FyfqhKKlsvuSd
ntDPg9HHY5dkKp+0XMb+7/4J/n/GRFZDIpgBXauTtEJvCxgUDJgNVl2pgLgm+mkgcHH2WZvigN7t
WVJL3ow4Mvnktq2Fb8uZodf2gh+p0t35+1ljAwEiJ+1BDbjib/PEXB+hwPcroWxo9UGGdVn/bU1z
kqEj06Y21RT05Z+eMORFjK52NmrUAzuTbISQ1VQkVLCqNDCdF1+ZCzILIDiibqh0f95g/hQPo8yX
0zrcYJuuN+LlOk2x8NXb5CT1tmn2xo7WAxHCWtyGGV5V7ghnOYyPkdPKnfaq3u+t+CHapHX7bTYL
15hXBlZSJ804SQ3ZSrp1yBdD0y1rwQxb+CDqrA99A4oif6+u2n17RbseJn1xrmLn2Ir+cihWgNMu
vNrwRy8eziuooS8R+nftjfPKseB6bZ+EiEYwZ8u4Y1u2A6YNvnCHhbX9q5ysCRIMca6o/t1F2oP4
fXi0wT7O5OayEvMOtMxK9oOgjPb+aQV3jRyfUlaPeOLIQvrDKj+7SRUPU83wuijMWcQHMP1PRBty
sm9gcFJc4hXuqztdWxuoYKeNQi1pGcV8uCeyj7ajjLyxi9/Revd56hp0LC3f6JxeNNPpVKqdPbk8
Bk1NrjY5sOUcP9M4dgpwPXlMZceWvIHfDmRUm6wAc+3TrGeAeEx59HssbWvo2N5B1hDpV01njmZh
7/X/myyDuIJz3LNqK6MMLxTH86Hp+VA2ignyfMs6nIhq63rlE5jVP9aaWyNAzcWS8pZGwrZD58C8
jvV11idwvrtYWqMhflH6vAgy5zgEVQOxIjnKn35OaBslNg+zDTa4F1WbXBjQYM5oSEHscsI/ewRK
ueEVsKlWEl4XTo6u2/IqZ4U25aBn/qJOwJX3Uoq8jk1I4kh6tJzmBZ1TRQUBbNqSokkhlj3SZOoK
PXqyUDB772fEi/cHwEJT0JEOpmHAdhLrN6Dr57X1ocogStneHEEHhlbGgCZcGBqWCMKPa6AUtglw
lWrPSEwYVOZv0rx45ptbwAiTD7qlA6QPxzTWLnU9qrrfk36ZNh0xpvLBZ8pau67f/tk7BQWC4N5R
5tK/AqgyLPBvCWK0/tAlyDYIl/I2Izo4HCK1jGJgScnc66fBTDL/KSocAmEJ4wQZAB3zu9Fora/A
X8/0Ln5IgVanBBh9E1MfpP6amc055FZbi/s2yJff9p7hVJavbQPbn4hHWTbIiTqyPuYoCneyLhy2
/hePxtj/zRSq37poc8nzzRdJyZxxGc38iTR83nhf8hObyO7EWnf8f4d1dOSeTaku/uMoRjtGworg
rvQZulDL5I8rZAePTlceEyDS1UygyyIkwzsuhb5IDRgEWqOyuaFxzL8zVan/EGQ4/tDd90Ka08i8
KsOp4nXLyawmzgZKoL4QrOKLVK53rk6o5DVfquMhi4ny/mlVo1pJV6RAyjTjjZzLvMWMsB5tjJqE
XlLTZETzZJ+hdCzmlfgdzp2VA+7kATX8/8WVo0l19x6E3ZP+R9NSH3RCpXTUOycIx83xo1YGLD++
oRe4AzuwHD1+1LhrUFCgfM2CNRjMaOfuPA4QujYPLHV6BhhMPv3zvjDCEfdWm6sYDyFFbvqLmb+t
7pBhEsil9Fq6aj3qVqqBJdHa68FQn9OGs0S7Va56X40s4Z+IDTyqKZ5bqC9DulNcdACOj5wI96vZ
vB6cK8FT8Ii/d4OIJKy1ne9KdS9bLEx6roIi7MWyA7PoW61NvqvPVKahFMZWO52kjftgxbY1EiqU
sUaR5E8o/Ksifpp5B8DkGSPIhH/SDgRcE4mvzcRoyxSpBRRXbhMWIG0uig/SgoH3p+2ekON0KUMf
nndK03qcrUDsEtSfIKKZqVhj8NufxDicKCB+z1tHYF1L63IyUqTE6nDImC+1F6n330OpsMI89rHq
k7mWLuKd0Msn4XkjUbEY5R4SlGVI2Z00CSxHHZrsdXiApLSAZ4DjeTeuexs9Xf8e5AO/oHFX0z81
EmAxUTGEoVfic87ly9MnUjEtk8ZyU7tuu5fE6cOg1c1Z7C3WjVDlUVS1xwPctv7oTGej5EdrHzXY
Nqu53aa/uqrJyAp6R6tM9eyfiUc/SrhlNiAZO0vst7pTeuvq05mx7RxaecFoxkrTS43N8gAIJwcY
gLpUphx9mntlR87ESfvMg+aPdyDehfFjUnyg7GzdIf13WLz1XzYnjDjEIcaAGwb40LKAxFiBJxA7
W3TcSBgB9sA22FnmkpIAIjgivXusS147vFC247yZKVrty8WcqAsckccrUtSrlURl+OL4+gq8k2AO
vV0mKkBYEd3+iaSgJl5JEqWWZewkTGK+h2sl808XwNXPh1WKhVWFozSOvHNCmVo5ue6QLNUDQVY/
4hKHeFoLjZOfatYw6lYc7C3YwL3W1NK9A49DpmorUXZaab5Mjc/qk+3tcS8vGtdmWmFQFBXzgCpU
IhvIfRUq5rqMDIpU2ZuUEkvIOoTaKvOLTjEWEYOyhuMi6wxWbpaM9aKRXk4JjmSn+PGx2NDl8W5j
aBr4txRYMDTdIXP/9hweknM1q5aF4eM6XBWupKL0N1Vu/uYlP6ZQOZEiKQa8i/Gdf66C3OJDr7sS
mPqpC78nJqU3JWKvJNW92cVTa5qWmgT1xVANLbScEnvt8UXbvc5xBxbMxXCCVCEJ8p+g+UKpomXo
Zh/5nbzyAxL+9eeS1fA3LlIITHAIy/nMIG6n3QRXTKwOVWKS4vHT+hOPva06XqjZ478n76fSBzn4
/aPpuQ+/pZ6gs25xU1dtY3rw0BhgKJgMSWq7iAPSU58HAphH3xfofBbHn/DdZYwrXSvbfLHlPP1w
rjRixtZRGRfi6VXqDZq7EG/aRQWTPsnvyqsJUa0apk612bRBzF4RhCupbLDcfTngAigR63BfEbBi
CRq/cLNJwBkksYBEiNgP3lBj7ovEl0D60BPflTTGA9xvIFjxh7myDI0ZeseSzsm3eiEiT0L6OjNI
r9mnR3uHzSpdJtUWzM2nDhITILzjsIlcZxh0F1R1NjKM06TSpjxH79CztCv+pYRmxT58IgKYXjjj
eTHvzxnPgY4tYNWLqfTG4I4oPVx4jfdAq+4pNX9rvxUX/dNMelcCJLmd7oRRQopOCq4vews7ibD1
hZ4iJqKFZnrVz6UnkTYNmh3r54oXHb47KHsUC8mI/+OXzgC1RY2rZSBam9CfDItVHKEN/wsChZ0q
kVvFmMK+lhtgoOWNrvLrGqwd3WLg7wwJNEuaIJWP9oV0nJni3oeS9gqd2VnqbuN5tFtzY2rTIV03
FcF9Ta/Squj8cDSH0rF6CNG4V6dNILxnBBQhCcF0JcyYHNBe9iUyQrSSkqSVm8VHR5/6jnaRxF99
8Qc/S1UAW9Ah+OjSqJFksfeH55X0LaN2GCmvY+B2HPDWpvhCCIePHr2Of81ZTQdgn8t//AY/i721
T+AKt+lFBWKQMHYcuakwbA20OiWMXWv3R5Ul/HAcH0kNHNRaMrQTJDe2WGDEN994FS55miku0Y/b
tP5PsfiyPMbVfgLhOknaeitANDv5uJFlYEhRj1Dr/+EJ0N2TnqO2ZqKN4Im7i3qnmNwWfbGICd3y
ljQQny6KosWoR2q3LLIPYUn6sjKuqyw12ACffOmPz89T1Fi0x8+iu+/SQtqe5E4CEOT1EqGIp8ZK
CcoOdPcWdBym6av306TQk29EzisVWCrVmxtyTion0oOf1WdHW6Gp6MePfPZrVk56EnY/b/9M9BXm
LXC/LMCzJNwtFknBPoDR2xWH1frBKCzKAkYpL+LSbrgg5EqlopkzzOpkGm2DHUTGRku8Ku+6HhAz
ic44dhlrQM4vol6WSPf2ma1Gx4okh3cStONkt9Ntk9OZU+6OSjD3/RJlyU/yn+sxgM5g6fPOD5xs
XnN+5Ksm0fWKxGU5OYFc8+C7BrrxiS/yhFouZYmRHMv8YwB0ZJGezZa2PAe4lrzG2mrqxEgwnx4y
nGysaPVkknaz0XpJM70heOYvpYGV/XP6DtlejQd1an7S6wOGD/YMUwXME2Yjr4Ov9/FuQaBvGUgT
QrD8B1GswuPPiyrGxaOP0z+MSiuU2INcxS88te1sC0SU1lJeRJ16C1kHiszbGGdUOfjBLB9DtHZ8
he1LfOPwwc14DcJ12Edcixbpb76whvxnKhjiISsToN+svO57rxNT3l/F6gNPn5XQWtMy7a/kbDvI
+djDQimE1qSb46fS45/B/p8Job4PEb5DchIrsAsJSerEmKjYHdeYiX2EyleVve4LlYsB/msB/eBs
YWs6qciOpg3EUHYwLNP44EbGuv2s+MLrdFPzPGywwTegjZzu5Eo4Zdj5915MlQEt4fVnTCkLrSmw
o1gpXAmMtuu1gBm22UDBgRLG4D0t9l5iTL8ezkarCZ8gcP0IQc1Um/th3ds0VMmgW6Mj2ni403G8
7EGXloUZgf4of6JNHalvdSnrWUmLrhr3jsNcqhxUfBvyYonhqH/EFYx5hSg+zshDz/n0eCxsSaCG
O8DVTzIcvIT0ym0mewUlWDcK+ZaP/JnJdZjp23L902MsYUrJC2KBD3gS/ObtbHAT20mStnjT+psR
LVs9AAnBy+wUo6lgmGvGrp98jbMz5XUMoGNdbJwekcHKIk7bxvwOOiPBma70KoqBkJT/caftol63
mxKHNRAIJUrdaA1WHK8lOc+/O2z0QTOu7HLU2AwC7Ej4pD0yt3shnVgga3985nFB8/AyAkdy9RpB
qvFs3pxnoh8AAfDFfWhYBgbI4kpmy/0QHjRrUZ1XVqcckl04Q0/+AcqQzIyEnYOdSy2Kee1IubfE
17CJbU1vO5IFRI6CvBtugbYdP/iIyjzzWnCZRkCQ04GJnA2cTmFJMc0Wn5W2939RUBrm6CqQ+Q40
t46jgKTkWIOL3gpEp9/gnPxwC3jSYffz2G8JsM3Ul0IANOO8I1+DXflrlcGUYsl0gYGuw+0C+qeS
rxrgBptxC0gwKluPaKkRPT3YIWtvFqMDfMXqxtPSNlMya6f8LNlohiNb54VSO3BHSCISHfIbbhHa
0F1ipwsTocqV2s8pvksnYA1FnpLdGyhC9o8dNaZpPclOm+DePyv2MuaA5VwzuG/gEp8jixxQ460D
LKAZ+bi9PgN+u8i5fhHPIKZ2hpJ3y+ceWtG03seQFy5G+2Q2C+f1+dOwg4nqWQVbee4E8Mc7XhGi
xRNKGOWzAefHgnVrPOtheit50XTsbEDJO61TBJtmB8lKguJtvMKef6njJ9puxqHth3MoQFBEdaNT
8PRIxY3AtgUmExOyhLyN6OVijT1lNFfr08OcNzofp3pct4XzH2eOjGEt/stvcJvXmM61RnFqfofp
6bm0CZTwmoq5huGUG8N+gIXFr4j0Eu4tSbiTuNKR+PEg5bX9I6BIvcKFpwMeDb4M9JErxLi1OaCU
/sQoiJs+VeddaUwkeZMNz/RdrMEepr64VSOKGsdfYDO7HaJUO7glVPYaPxBBVhx7albnbEjfGHkp
HJwSunH7i7AjIEyiimpvrnhWys7kSygcFRGCiFASefpXLriijQA8gvG3nQxdITZbflfU4tCoDlLL
RSOv9CCCzxpLpgXUA7keyRDH8xCby2ccL6+wgBHSQBPLXZ6oK/OWr83OmXZj1T9Kd3FmA79MnEW9
PxVGY0LfgkJySGPrnQIBbV+UETg+HAfZ99ewINXqEuAUW4a2ClekN8psM46Uw+1SfD6A3iT7SZXk
kI9aso6XaPYjYoOYiN6tANg5FXZJGXPPRWb52ONq8R9VRkK5cqZnnaNV3J98rNIKuBFjgiv+aPEb
twAhxxUkUwDHFGd6Q/Vhi+RddpObO14zQOVidvwUMCiK62q1rkKq6zXkFKrRU3CQy88S+psaqy1U
Q6MljRW0+BOnS+pBmqiawFBDYchUs3r/lPYAGaQMQebyDHaQ1hCb7lEZPDU4QLx7C64wA2X0bPN2
Lju6V6ysqsgyW8wLF+NmskQs4SOcjGH1I5mRVPwg6+0eNTA6P3Srg0PN7YOoQJBzR6G1Wpan9+9B
ksXVx23VDscQqZSVgrPyl4CKeIAVMcvg0w/1XgSD9KkkV4fxIYeCO5vx+LGr8SHcb8juLubwLktD
7UbsKPLsokggUsrMl192CGi1BIXfBHUXSFS4Z6JB8ofEG5D15AvJD1fitNIv4HF8Yi8o7SvpO2Ft
vExoDlbDN9R/KUxjc5E1QPIgG9phgxiVEiKU25nI5smSjK3N1ZgHqVq3egSxwcc/Bg74BAglQoft
/VKc6PTRko8ribYO4VMnpcoxc5kh1/DMNEEDnMRCafTF2JYySuFVTym/u0YuUCZK32leDEbz5c8E
tJ+lp4rtryT3h++r+auq+hZ4CqNRWo0TD8uXs56nic57grGvDa3QYziZRKYrGRfCAYbzp9daHf0K
FIjdwGn5BfccWx6NsnhIOgt2D07cbPcV7Ccn3ryjl+We3kbDt0BydM+uJrp+OXX65wqOElsw07Fr
ZisJoCSfZZVmoKsec6VrmE9/cTTplXuMaaEwwoa+9fjGuN6Kp9Gy06pgYzWYbMMeuiFdJNJwp5mu
3PnIplLYnIctU9BCqGljfh+1KGHo8QJOVuYV8um6SehpPProG6Nqif9KjSx0gyESwEQr3Q3rXzAF
1Pcx2OWPf/EL7YHn+HeBDkKFLe9PPnqgEhu6MeWzu3oh5JFdUMlhyGLmNkEQQ3atLa+uVKiLOwHa
9FGfhAh8/trTpH52bx9/VBHgz0lRFAQKgS9Kz9lV0ug1dSFIiZW1FH51Nsb2EkYsekFkSQ9mCrEM
bo2+EeLJUy9DIBCV6CfqIAXYR3p9M4wy3tSLAQRgxvAa13vEPUTHl1G0zOr9poPq3VaA11BKG65R
VXt0lRpiv5YI3f6GtOFXY4uu29QYiNaIUSbFH8T/e+D3EIMjlgyKWS4reyPLXXCVzgy13J71Kz2L
Pv1EZb0UAPHOEADh4g5KJqBEWO5uiRQ6YGu48odazNY0/DDaywyxXzcOwBCkEfaAdwM8nY3s0wN9
SVDeQfXwlP8vXFTbrc7aEb/kq7LEUSYWep6i9b0HH7Zi1IV1kFIBg00QVsEga5bjUtudjIHduzmW
DBZi5Aj4TGEiFPzlTYFPUiii1FLyy0ZsSRnaoreFnA2IxE5MizH93nnJIOdiQXzQTkEq+L0wUBeM
VKfHf3RftvuSnRmFEm9mC5QkZ9pYXd8FZbX724dfzDaT0M0Uj6TzeHC6fBJogmTTKa1VXJl7NlsS
k+aTMsH1w3RNEHIzM9Aon0bl3vvRa0z8LUDobm2umXw0SSXKmrUEHtrn2UTNJvnttIEBe4MAuI2b
2hpDik2aIFa9ld2eDaQfJRpBNHrt9/kHwiQq7FWf+iS0nDKYOnOZAHFlZ0aq66F87luG2rZdVllP
95lssXz4L3O9aJ7tK+39o3a0UWFoUKjZ644tMTAHniK2uQP0tcC4305nOPfXOXoya9NwVXqiuSxw
YoKh2EhzHg/j2Ic5YCAWTfdAtAAT+thV0mE6OBzSCkh0cG0rTSqhGp86xxYa6YyB6S2TyisylRis
B+w39vpdqI5MvZw1vSWaOEHdlSbH1NL3zSaGlxHHS0S57ORUubaUy2Vc8pfJJVJLvnf1yuVxeZ7X
LpCu6QzhcEMuS64pYxYOocw6zI2GWNkkY9pedJkYPrl7YOAcIobob06QeLRXGHfbTOFde7nmjzcx
MFjrUNZWU+cA+uWr5aCvbReiVYXtlXggml907Tfma47nwjZDb17zO2bMAzHHkG19XYuvE9XRTIOo
IhjRZvhQpCq70qaULuGX8xzHobqA+qY+ZLsqKCsjLBx8RloE7JJ4pjQMph0eekBXw96Sab0ZUAbT
oupkYxXsT/cz1BjGsoY3ww7dV5zXPCK57XCzNJvSLFWZP/0vVt3MN0VV7IGIWpHkMyXUYcVv9+Pi
naW6g6DDN8MHCf4u1LxbJOj5B8urrfBxzToJX0d6x5r4qrea2PfPjz44tjsRoOvxtY10QGG/b47y
9jC4PklyyLtwwN06b/wBuRQ5BCsbW0dSilWWOD2p5v5CD7YI+OZzeBy/fqlWd7Zaot+1je8UdQ58
m537nXuG0zopg/3HRd8mN5EAI7tGcxeYmCuckLz9bvfjucCXql1qUL8X/zzwWuPceHOaVFuYwHnr
7+OfvZffBJjtnMRsmkUZhpwf0S2C+v0X9ozPgpaKt9qBUSmFik2UEKVaR1C56jhd6Dkg6YWV2J6c
G7EIpjIaWOaBWoO4HqpaovwgSaXo5w6TNZh+/HrC33p/Lehh8dePiMtDtkSbusHSmMch7lvjJpeB
99Gbq2Q9fKtSG85rscAyAxBH1mcUQdlXkd1yH0W0mSf23tEL68fE6PUgiYeUf1NFlEv863qrRv6W
te1fT5dq6rD5C/M0s44IyxgAWxJel2VtSIPe8fkuEXnvJdUnYVg8mmE4N+gz63MbriZ9FoX9WnSn
zb9Ct+eeUJihKsg3IHXI72ipRH1okKRdJaoQkQfnzQyo7K22WCwuB/ppqDd6mjca4N1aYebF9aXo
c1RR0SBXg5y80TyZG/iV28dSr8Ora1TnHvm5/Thrs80AfDFhNVWmPGvNGt42RiIg3dPn5ZI0jSnV
om4H4MmFkUE3Tgabf3bd+7IyTIRboi5kNX8TSFnTkO2n5KYt/51WpToLh3JznT3FVCm/+sK0FJdc
zzVMI1WIp4Nj2Tio40VVvL4m+uA+jkKfeBiwvkpzMIEktIuQnMMO2JUYNwfOlnUheGGX6IBNYLVM
1KGtzOEVr1bTanoS/B7TmsoC69jYHELDKvZqmKw0io5NoH5paQVMm1NwbBt4Ozx9BHzeJFZyp+T1
MWFEhlgG7wAiw360/ZQ5JEFk4QHwvZEakyrI9a+0ClZxjylPBkh6WIjUU6NWShFrrH0P27xGiKtX
+6vn6ZvAvgE/w2mVXZgpzuaysX/Y2gNi+nbehBuDuefVGq8rfQLqFVgh6Il51NHjaULLVHr/IJJ4
XUn5yqsSHmnNV7uN1M+6+Dvyo0MeerCWFqomqE/3KAxcQZfkBNm7QbSigxq7EXxzX+8hKfIOyitm
5kcjYSysk4RNVQJQ+LJNrntR2yz/gSJXWRNZ2WDdRjzTBOczLpupMHFXeRZt9Bub75B+hcdEP/4F
tubliRl4/umJRtAI3RHOBHvMdEzkqFIvIU1UEiyhKaCeYtrYfTiNQeLuk65hySMqjxFMzeM7teSD
lLrQSW8pIouZ8Of0dM04VXfO8PGvWSksP0UoqmwayR1VDgMqvbMQssNyGXaQ1SmjXQBWzmKqysFP
ay38tjZHrF9q8ZB6m4/oCo8vwZ+Gs9drNiXVQEjy4jH5rY5MyLKJEsXSPZuF0P08lQelTyNbGb4U
zFd98iQxU8tzzZ9RrQDkDY8E/RfmDhkCQipQdDrDkH1kOEHaHvyMIidcHgd+pF9wlKHDnO+eJ5nT
FECYNqS2+ENBRZPkfi7p1W0rJUprA70uXSJBATh5Hfd76LJNqnuFGm3oWjRZPPgNfejZwt8Zfe3M
T5Grdn37tipJuItwiH0THfpuEH0LlYnVSkbYRec8ZDEr7taf1hzZyFm9NOxGML/5Qz/PqsxPZtPy
hj5Qi2sntTAzYwe3U0zXSOKE11pSISLM8ioscWuZSQPy1c3qd3nHprNIyQ0kE1U43qkdG761qNtG
ma3KObQ14u94tVe0SvLSZnxHcxKtquXzeskxkeeVwnsxz4I8a571CRUAndXQ+aLox5V35fkCpilk
ybajm1bZawiNb5w+t8cbMHV2s6AySUClKmRRJj6Bz3t1LONI6ShYZaG6W5cEYGJQnvrrDEtYf7m6
np6v6swHH921VfuY1+h0DRW3emvpnXdv0zq19RhRtVbIu4NHBs72P5vFdOmKqIQwneAoECTeOauK
WtDQ36sn3PJjV54uy1I/aTczwzuhwYH04Lo7ERMnyQizvmNUbubS84tpp3D9hkEzp1oIUtOGaT87
hwny6md7AKNfCWqsv/I1HPoYjikAVlPXZU6wiuM0s8anp6t1Wu9hIgLWMHrP2YWtlH6isoy/zUYN
bgKaJqPR84cSRdBc99GQ3AwqVCZACvgTD9DQm2RUguQoUdekmSy3eOJ0S0qjbkWJec7GKbLQ7nnJ
/a0JekGAIWo0y4lbL9JR50eLKojqs0Nmyz7W07N7Ba8wHLcc9buuuIE6regG8x2Oaz0S8uU6X3RO
CH23oje8NAxvoD37NydsgmQeBIhiKNpf4iP1+c/ypFIATuIGC8973XLQF9+A+Dn6shmcePFosZxl
x96NbkeaJJ/8Md2Y9g7T4hUIA/EhgIStZ2Krn5oQU5Ww/eAyG4QTVpQUVEQctr5XsEqBdTNXVHaC
L6sCzgXovrVGuzE140aA+8yPzpEMMtLK/Tj5YVQXoSCFhFflNYQ+G0QEJzsALRyeLbd1vasG7MT7
WGgZZkQiUd3JG5Udm8BMpJWg0+LUTOa1ih7vBG596xj7uS9semBXzPC/A8UljUibGr8JZshRLUiq
sSvn6gfbzCoWum/ztk15D/s/JH4QVuMtbL6TH+SpoT9YToVGtrLGWqmaXp+25t1kUl0enjjTqMsm
c1POuplr3Pf1u3/vHCmG3mmPBpdkFCNR8+7mUTxh9pspfkNH92fu+VQh/+7XgWyuUCjHL1KAl7sY
OeEUEbCzSl/29g8JRxlgbBVyY8TPZNKn6G9q+sgjhp00u0lHJCdHOjgD2E4U7KF6/j2HnCToGzRE
pGgeHv3qjlTHf5mOa5NvAvBAjsXDNvNTYKgF/Tq9K1Z37ozPx5VKl4dMZlUQrsxW+d7aZFriehnH
uYudqhu3pvsCyNbJii7xBo/BoTJqT2CK+30SKkfdwZK59J4o6YdaVKzHsqOc83H5hLb+MTpHmA8i
MriB1tVu05YDjXl9xKhaUUoeWV5vOVuCzJ8F8cTrdA5GCClmUcNKNeX+nQ5+p9KiqeeGM3YdLlJv
ogDOsyuAb7enaLitSHyfzfgO9ZJhUKbuqbwHoIA9j2OUKW0scuFOWBMTYUsVHBbWC67g6qeKuTCg
IBYP1QmsJ7qhcrUTUaPCa3GwcvDDC/m4/N/e22mT55xpj2wcKwsfFEPeAHur4JlIHcdvzYhDF5MQ
vkG8rNIbasyrcH55/SXp3I0yj7R1MxEu7Ehf5iDIsuKOo8Zn2VTlwCU0judkcwfaBLFMRXh/jfA9
oP5seOgt1Nau1JGyEaWia7QmwzRxxWWmz4rc2P0thhsCl8YTZvZZ+YO9bX6+t2+i9pkrltp4se2p
5gMw8n5jOfa9aLPiXEZfyFKixn0whXh0eQZAmBowe048uiFzcNVd4fZ9kflr6bkoJgvanFCEP+Ec
5RBWa2Ne6+qohKgvaVffniyYa4QKnnvR0iBiZvuBX0SE6zqY74fdIJ3O+nDycDoyfHFWpQ2dmlei
rf5aRRsKvq6y1NjuMoqCJ7yWZrkYrR38G8kXF7nmqxQQ6VqMcsiLnNUyHkp3+mRDdev/8aRcIUKA
SrI8wqen1cvrdpr8rpMZG+Ae08rayzWDu69M0eCgBgx+PjN4WvXKJc20z0NqpQkfeIvuhm8d5Jed
PIJzGzrPAui55nMF1856XaWuPHELxaUWJnX8bteUaB6m47HnKp4WwzJRkjoi2uU4P13WrvzTAYhZ
ZP4pjgYnq42lhUnc1T4M4m32XT2vF7t4iCKc4rKjq3LsoM7Yb2d0oQJkdcoD4P9e3ESca+XkfJse
u4OpoNKDtjAagY1PUqrGpTi6X0fRQ3DgRSyC4yTxOgYtTq/0lN2gblw3uTcKhDWEGFSeIX/CIyXP
7UtrpyOAbz6KRr+8ZQ4VXdMdtczZlt95+O8XA6rcwCWJozKriFodgJfLoRPUlE2g3RvQgEu3p7/9
0EAKmK14wNmg8Czftr9w30j6kbsmhx1oWbWLtAJjld4hrxjd+KpJFVX/GgvrSu3g8yXU0hXkGOZl
7/uHwM+LMZcA/7Z/cwzWirF/8Z0otlYzoFg+GFasgNXT5v1tEGpxjOSnR/+hHvDM8arKtBhQMGax
WbMwy9zvxvVWXKxZfk+JAIJBsoiYsV5ICRUaO9v/zrhiR6E0yn5XGRYcgp0AJOe4IpzfKU9iP/01
c6pYZOWf65OC+m+fd+nCSfMt6h6h8I2yAA/CbQFcZEmDE2ahdxhkXRriVRYIgnTozAYylgvam6VD
1/z+GKzVwfSAxac+n3wBol26EDG+5zAwn9GNx7zVGrnZBRLsRz20Mftwq7tR2UHvVZkFRQTn9kJq
xEB/u8GsPIdkkR/y7lSEzbXD6QHjOQf9jklnwLtiytUquhNr+Nd33tmwJcbecJhZF+rjjMa0fnlU
I4rCxHOXbo9cs8eDgHclc4UOHd9BNkkSRXQ++xFf9htdro4UQ44MxwrT0Xm3lCb3p7sxxkDyOrSe
V4SeVraU/69oS+3vivVU1f8MYymUFPruS5rhiF57IhUcE8p5eAvzx/HboaIWA0zF8VY/yMPo+hde
nWQeZ48dd9r4jpBfF85E5UJw03YpdgAsRkJgCOfX7aJhtCguyyD3jedv1ziIG7AXS7BQebCADrIl
8Q5Zt5f7gCeNn0Kx2gHNayaES4e5jpI3PkUNyITvndbI/Mwbvq7BnP4yQ/lAKJ1vX+JmrIeDZw0r
w/EyCUXR+6wCryyiaebYiPmhQI8JlDlBa4SHY8+/+uGDb0+NmJArJm3s0Lc4cmDyaLUG3WSQB7vG
9nCx+NPA2Vmew//TdaDe0gulGogl2e6jTwYu8YaTPE62irV07YB6CEuEtXj0MVUySqpregnhGdJQ
DMQjCgeiJb/MTRIx6pGUCNWPu7WCJ1FDPDuC69i3ZFq7RGAIqt3WmV11GfSDxRkNN30ZJijQsUto
Me8v5Zhx8zzXOOwd9Leb69LgQiy9KO56jDJJ9/Lkh5/7+T/JcFyKupdziSxdcNiu0QsHDAv5X3qq
G4Z0vIbLxwK3VpR3RSmHhCfQLDGAQ8cZpz9ozc+2XOoCmonj2SOgFKQX7liRoaPh1fN11NTkj3uf
F8OTPLeqtq/djGKQFORfLV20OxCyIv52vR8d5L8dfcgGkvtK74ze+JuVTVe6RPchOjWMooaZAHPu
3QujGaAyuq0sWH7sbzFV9CImKN27ahyysskboVa83K0j9mi7zcYrZNyhUeKoovcB+arQ4Qitx+To
U69R/8V3XLqN9xRgJzDI+iq9QVS0vlHLYTOeUow73hD9GcuIYb2CGNcrLgmTQAWZFJYQddiC52+l
AiDKSA0I90DBg5rtNZBXEkJR5UUiQvL+4zAZAUiigPqAt5EIZH1htKb1yXh+XRBHitpZaft4SyAY
Z7qp0arw7y2OBl8NlHEIDra8zclYmRxCpjpFbEE/0bh388DdKtzJHxfWd1Cj5P9VTqOQUUXEDACy
DLUK8RARiUjpebHyMo05/vclakqatcH2a88S5xeS2Z/eWuJ15LmfdPNMaqi+MtC62ig8cjMpXMYE
PixBMX4eGstlR0Vg5aTJEdmR7jeuZIBr3z4CeZ/Nr6KCjsJNqUwQvQn6L8rbw86pvU+isMe6LmHl
KV/L7228MjIsOZBjhfiVfg/+8gm9mdwoJadYWkzMIL2Vol8Od5O+D31rbdaICwIKOEgq24pcPFF5
l717E8Znd52lu778tp1JPPvweOpi9jRAl9ZF59GCSVCroBuGRbiH9dnyBdToHq61cqxOyWJxyTaq
ai34ocbqU6o8l42Ec6/1dcJrdkB0RNcKPvStWbMIFV/QEbQZMJReqR/8inb0ODPcijVPriqVK0h8
k45pCbanQS6B2WcqUHnGt3T2hQ4uWmIfy45yJd8GYRjDTagphgz7nn2iUifml8G7gHEab9MAQo2f
ifdW9RSY8985E+ubKH5E6a7NiUWQSEZ9y/dFsU68rL+rJBK6NoCuP0gDPrn/Ss0iXhoyPxDZAvhn
GDJntLo+CC5Au9rUBooqI5DaizlDpv7wTNhPyHQJO2lxTP7fskvxIUfa4p5yjdd3ZbhDadfZmv3s
Ar0stM82zRhiGsYJlrzfnFTghdZmDjxz8AcCHV8SkW9buc6nUThcm3Q+W09wk1BxnE+ETttV2/4i
pn4lebfKuapZN5091DT5mbITTdvuBCyU8M755Ditx8GPMkENgtv9agIFI2qRpiEsHjSBpIZQC6/k
VrPpA4/ylEpvji/AtFe11N8bVTRsJRAarLAH7EgBqRzLUFaDvfriqVn8juFm0yex7/iSDq1Iyo7E
Sh33L6m/WIjpu8wVgJFRk8aWozZ7c0HhiNIuslCsG8SIFEPYqZqsTtsZbaGAvqpY0x02hUumV5Xt
eo7e3JX94ZQDg9OGA5klH5yvewp3sfMBNA4jmrrkmvzUh/7w8nJWBkOHOtazt/RgfIZh6cHPpTK6
Lyg2wM91rGu6XvtxK3r0EI7xVjU8HeQclGnKuPKG0h7vBUZ9DwzBHByrzgCvvYaCl3QD2OocL4dH
gH/1i5LFMe6dl6nwRSmLqWdHqNLPIVEBOHFZu2TUOjlw0m4C14iYg18H1h8PXuAk8ZOmS0R6dTXh
Z/JTTcyUCvO7O9w+mnB/0eL57i2ZLR3Y8XixnNpPnqzJoR4KeB4OV8LOUxhXy479z3A5s2GqESRW
1Z4UFcDxg+JH1Z4WVlx7/8fX6lkcBVzTiP/lZF2Zuw9XFYNJp5oh+SS0vhvaM+jDeOargaFm4byf
RDdVMQQ1rwdfA9a7kZYqQX/ZGLtkpULS7hWDNPQ/wa7Wye4q25FzYB/9bQam9n0B9ZhW1E1PNQDs
nRTOEyMpHrFIrUooXOcdHS7AIegS9fZ812oa2wgKlKQ4Ul3G0FvCLDGzG9OBSIUagy3Z+smsJ0uB
LfpN8o5Yt/1woWjPrwIlX8WgDIYJZ/CC6GiksjXPZq46UM6Lb5R15npdkXGpNY/1OEvYVg3BHEyD
NzDseAQcK+xbcXLUbMsh3uOXnuNP9V+Wu7JYlt3+Qfjn95HkfdIRFP9zxewaQkcUZD4QpYwDahgv
z32nDhjcAXo+XxZ3dfQGUqs71DLmOaXUUysR48Pmd2Nf0wqpW8rDYKuehbwe5I2fwUeRpHxTv5sK
KBSse6StUpGyi4uicmEpSiVFNJbLF5Yav92Vg3JH2NIlvnf0fgfwF5OsDGTqIYmbfIgDbN3w0nsD
5H97xqOMo2yVuHM41nR+NXVnMFvPFeDOzwGd2ktPDRwPYz5takCZZamPL46FUIoiaSv1u0uXkHWL
I3vuifG/Q/KR022kdwf80fkRgM05yTHZy9zpQ0BfEbRGAV8zSE/C0I2A9d7HP40nv5BZv4O9bNMf
nyrdSxn05CMneahRCHFRbL7h/NXMiXrEh+OWRHsw0YsK6ikuDJg+CNNDcZLwIgPQzG8FDUFb6w4e
yRAFlFOx7zvVF3nYXJsIez9GKYA86t3oxHH9QbCi0T42Yi/VD1i5gNGyrGF93qLv1667aKJdbs93
w6z+VB+Y0zDZZEX/SluZToW0MflG+Rzad01KSS/DLwtXOH91qpnVaIXmgor76YayUQG7Z4rh53xW
jFwERu3EAXOnVC4Kn8PfU6w6Iy1k2mcbSexXMGJOpaYZfCso8O0Hq48doduknZfh61N4MjpnnVNy
DMT/D6ivrujSk+uO+DmCH6i1Dla+oFULOQt3X0Jydzxok8/hXmq30HAYmbrrHcKZpdYyxqwIcaTb
YKnS6VnQilQIFhNnJ2KLdMajYXgzHQxyIa8LH0iH2Gtg0+xV3NPUby+Fe73VyQXn7pfl8vy/ihuo
1Sn+NrRzy0UIzsDz7mZbiLAOY6AkkQo6HhbY/cYxlfE0QgSTJyQiqEx/YGMQsIyG4OA2cbZ6xkt4
HgGUrnHpRwkCN7V37sKISgDLTltjEagZpRzZQBMb//dM87Lz+InbrjuGL6Q2QOimEFKO8bEqKeOZ
19SjKZSmgm8iDqfl39ytlubLbI9jTsjQMIplOwGDFUwfWIveEhT5Y8DCJGUmXxGY3OdCxqEQdiNV
i/djM6mxYaTtgoEu7oxN+39VfU7LSre+qvLNjg9g5zfbgvGeJhwd49Wkn8Bvz7pigoxpPHmQWzGW
qcMWbuhUm3B96z/r8IOGGJ2w1zVe4//+TMwLvHgA8eft0/DEl2nv4GdW3H/uG2KWBAtP2E/zjm3C
xat8tbyfVNihFGwQKPpixFUjO9EqXJ1BerbMf5lcVQBMYV8k+F83If2qGcE0eSZ5rf3aTmukitEJ
lvOnJ/RIgRJCIoHLHojJgDYWH/XzR2dkNLOegfUsAG5hDic5oVnfYe+9rAMgLFGZ6/Kro8bLGdcQ
laSXe8424YoialbEeZcptemuzWM7aU39Iauvzq5prp4w+oKRPZRSidHIjjWHDHklj513ogzU/pwx
PXafcOfIEznHWI94cFJNNYG2bQrQCRZKojEi7G+qgrBRNAO3MoTus3WHtnfPzODYKbGCaTHPU0RO
oxnmHa9Ac6thN47AOBU7SSSFGwXoJUrZg/OH56UV99HT5iqdczMCUgHA2/AYjXlpoWhUvI6yAJoI
aVMJrLM46S4EqhrZQpAyKM7z7kLAsKNF5jZWl+wioIZmd9Rg8VfVWQC8tzb9KMXeiKLVyzIa2rJf
U79lv7TrLnKDMJVStPCpMkuxrWl61/mFITX1r+wfuFElGqQrx2b1RBtc8D+kYYeuduqO4rDrV9Y0
ZrrfNexECeLKti8UosdiEqhjIVye1mNl6k4Sd2L7h5UBndO3qvXC4ZTO/ybd0mR0gBS60aVBdPN0
vVD4TB22lkXbpljTnu/dg7RlPIotqAgyoeM7yPWj+fJvKohSe+oPP+TgkahK3LnhhTJtzI7KWNN0
4i26tfx5+vxO5O/XorHTnZ+Az8S7akMiA6tZJZh0QB9pa+gW8FGR174ZPydsQ6sdYw7/OpsMg2Xz
D0qlBLkS69/pWQRi+jLQiGv8rs8p7kCQYUFrgukwSVGvgnpSZ1HbP8BtIBFBO/COYSpzkflosS36
83Ury+DtvNCcppQebZEwBgbQP9xg9Tv8PD5ALQD/yiLzbHEnUAzba934Jv2ES2SYTide7mkRNM1t
WdnW7aPNETk/7BIiuZ9CZXEgjG1ET/1mIUikBgTIt7St8OAQGzBSZdB5fcuLvhID4C+brhAE5WkF
+u/DD2JCImfT58gxFKqaF6P/h6JTd4M6ZOCJCXhm0kOeTOXxmk/S1HL2m72L+w9AqnFNCUj235RA
4MLenaOBZTxMYP8P1bHwTRZVAOWrUOXVRk7ZgzqQ/VamPy77jn/lzaNMaL/OORisak7SRUHpts7f
+xsdeZeFcHuX0x1BnSFzlwmL3iGHchZY/T/Z+KVWf3O0u6dK1x98eAsLis5rQxzWI+7RvzPhYe4K
lSDi146CSH0H5PJrhbycjeqw/lrXIJjng42kVAGkOgp0BM116DjVD6u5f9bpxScM4v5lPiwjBRG+
1ez55Ul3VHa0u7d/HJ1ZE8ihINGFkGZcyUFwwi8JO7Icdk0+JizGBhm+/4YGD+el8R2XX+MSbYLD
D04zQNGA2i8u810kC3XvilNm4/flg/YZJvnKF7jTz+lq1MN6OBDe9ndt7CjNy5a8xZTg9F0KYugP
efsOD6Am2P3zENxaueBNfX3dYnBvdHjOVCcTgKC+iqYzQ5i9ATu4KFELsg3CoyjU9vfvZ8VpSHbR
GSRq4Fy5PPfLg9vmCBhdQC4kFOZKsLT+cJeIjcDFkxUge4rYx4JxydWOsjWRZ4KfA39+XjZ85JEV
wJZNT63/ZyLK56laCYiis8DIqMVHcbGr8Mg88BvtshZpHe5efa0BXkzPSXr/HNaGT5aCejsFJY94
xrNOwJH71QwgPeD43IOCU8WKKPKvNuDmQ66pdLEOFFVsw4YkvFGBQJAb57kDM6Ohan2QVaCcHlEY
1af2G6XPVLmammQW+brjwPET4M0d16G6ToeK/eCbfR3bUsmwtGvlWqLB2xIuzya4QHREiPQ0ljqf
jsYx9FHEqojwqz432VW5E/oNYICUHgkudi2QEvZPq0XRFS32y1sQjLlSo0HxUcUbuL8LmRI0XXnT
x+R3rx+KB20AtxPIOjNTVkdImOrmbmjHNjFONSwewcCVcFUTj7LbPTMqLqtX5vXw+TVqxJMIuW39
LIO9oNsHlSz56ZKKdEwfC54ghMMr70QMKZXr7XTwZ6RLrLERl7ObM08ailjvHZ6YDUYgqB9UdbJX
fqa2cuqbAGj8HrF9/JDn5dH0B08SmCarHaChphKooKNSpJAVynSaatnEg1L0Sj0wrWpXWH+lJRTS
bhLO7XE94lGiddqTe19f9i4uRuF5chVXKYpAxM3jvD6pUmnGlI4iwUqcu2W6hiA4xPOxsaokf+L0
Tp1osNRJX6/YCcK/eO3+HWnNPGU6/FpTeRygIyZUJqdHB8G5wyZ2lPSD4imZeztrwoc2MjDo7c7W
Dj0P3uSaoeZBo3Rd2dh4SWga0vRviQ4wP/iTxm2xttMQpJGD7aXFVIjE4ysKmhKtnZthAKbMBPpm
K+2EKsfmRH6ddU8qjg9sFQzuG0HzIdpJyS8UlZPHCDn5GwkDCFVAE4Z4Ay1/XbrIZJvM171rWtkS
LlG5i8zF37XA1Y6ipW8PDe0CKXjEWu1BZrQSbk+ZHENc8xDTFS5YnZg4sil+tuJvGe4uNKEOVeDn
0DkEup3890zZ+LuDff5OW6gLvwZZQ9h9IDzFPZWXngGkRkp5EyN9zUF1Osk7Gek6NKC+dzf++diW
NDIj5yfuI10IC+8mFTsduiIqga69mj6j3CZaXbaTgl+NSjOlQGFjHxEhEnYSjhGJmppDVpXrosrr
Kp/WG7S5nPbkN8kmEjJJDGwDOz+KJLkUdjQNXdlZRwNPo5snnFuPwv60ap5G/q1p/aeLVOmTUUrW
egGNwfNW9zyTwqgqwM8AQSK9jpZytlmhEpTRwvSEJZcwYJsttBrqIkn+XqaE44pTMq22hWAbQEg9
bTiGS3m1QK10XuYWhBYvSldeIe2gYmOVVBSQHD66ClY7FdsLAx+kySwZioMnUaVQ8OWBrjAG5CrK
Vr4uDM/of1CmqDiuDr4qDsauwl8yGCFK39oh86G5A/PbRnZiF3xDOG1CjLva9NI2Gc9kRZ1zEkqW
Ujl3Y/RZqv1NIPUnen8dUHxS2nHgaELITX+DxXeoq+PpPm561elw0B57tpEjU8PDbCugaifBrBTe
0EF7y0pdcCEVmx5SANYyfU5bQaQta7PXXR1sPS3TjnyVmcpWJEqcMuIbAN83tXxOqECxD6CNuWPM
lW/0O4yQqm9/e4AZYBQh2JLbKuIunLh3wnQVGMChldkEMUj0aXvtaJlO0aQSQfv9cpBtxFZ2I45O
3ws7lzaLIA62RC7lXtj7vHSkBxOhOGyV5alGLZefVBlbXXi7yFX4f7ZHj0CIlOqV5Y5iWHC6FYmZ
5zsD54/rSi9M57WUy1jC3BjPkvqD5fn5D3EbPmmwnYpnPe8gnNc6ym8vCJGRr9pLJSv+fJ1rP1iW
r0Qkp54dJe0lcmJhYZVRPSfZLfRxZLhskHvpdqDBN4WJ94L92L2uVKYPZx9i9+itCiUZgGIIQNOz
h0c6FTTwkwLESeUhG2e1ToRNiFR5KmMf8T0oUv/rh9grU1ghNsYwB7Eia4+dTD7tpBEWYMLt9kCH
r5tN0GPS9E4fUU7lZQEwLm3Ue69r9p/pNz46s7KlYXDr3xzf/hQ4POTQuoz9w4tcjV7WMLx8R3gh
g0Y6T0ncuO8wgOjTvD5p1mQJ17NzSaxZFEwzoEwezJGuocbXnBQO3VKmYeoMR9ZE9wX8OZlJbyLF
98NqaliLEGPaBUv4Z8ki+jrEWYVmh5Wg5anS1rp86lROjMgYD420al0o8l6lJuXMY7LGXn9N/kk2
B/NZEZPTElMsbMtR+o7cmtoyYabkVe9P0bHwQLiM6fW3iSGaf9xjnRXwmZ58CKDHS94CW8MSUjdb
fA5NI5KBvh9TMEgTYpDeZjMrOjsjJVQQ3ElEvPCXNRKB7qZJa1SVg4PBsuvgyyx/7CDOmmoDIBb5
3YswtFlfCtOewnocupoOuDj6eQFMkdr40sGBYULAfA+2+BkHNnP2YW6K+36RexILFecOHL+fZ2nL
iiQme0Qa3OqsOG2j8w6mBO19fVOFsQ73E5D1hnItezF3UTN23OVkOIdHnV0NxpRTiybYJ0WEB+2N
PzeUWmrH2knGQqafLllFQVVQvzNUYYtICm0s/Xgc2d3sDt5q5lRCAjWS2hZnNrwNu2pV6oiVenOK
pag+t70SPdGFJ8M/JZlpkL4dySnUfJ6JA6DH70TOmCCBCqmyTQ74sPcJlPvy09faJaQEfV9Jlpop
L6mEe6BOLUHUGZomE0UR99+nR7XtGXivC0c9uUhWPUfMFByQ3ammxK4y6exBdDlRahygQpncWxSe
iQrigMM+LTgkdsxIx8y2KZPWpuNaBBLbysT1a0iPXyYkDdPdYKayk4WSf2yn/3YIyg4FDl99wRHZ
mlXTU5Ix3ug/Kff+/TslCbLOAs+CgfpK+Gy12oBDSOUVKZYX64/xWZfbZ5gx5vtp/pyTXXZv7r4u
yd8GOZYWR3wRKhMY/7djA8B7RzlzaEfee2tdSttxj/nDFpDTWye/fIoWEGQPVR03+1cigEJ0Clvu
dfnsXWNXaculydUnYGWI+Ezynt5MNeFkrM9dDm4gAW746Uv38oWHSRisZEV5Ct3oYqZQbv6Ijyey
aWUk4HC6IzqRYAsYWQlmN+88yXtTNKimUHNrjZHsUUrsx4PShTqfLqYEXRRJ4O9rEylyHyU+NRQu
RMz+4/EbpUr2NzWpI2wVISbJGiRNi6erFFdSd/yHebMjZf5Aj/ZFU3AURk+qZohnkwMYxnKgwltw
s4Aj+M+IVcbsh4YTv1Cbbr9nm+hcAP4FVIgAF5wqhBI8oSD3vE16a9v0H33N6DL/gqKvsgrh6W+s
1sp87kFe7quz5GdTrGRGiZ8/PpMz+kPA9Tc+5t0PuS3ES79XO4u12FTuuXBKYqQjRR9E/P6MTffU
HVOzY3P4D3iQcHYOjqCbvyHC9h2Kkdhq/5rDyJTVyUWxxYIPHvC+IdupXcDb3FUvFNTsh+fJDHaL
5egK6yH2hhLHxfctqchRSTNBbf8pjWoV6+CQJO3YB3aiWMem9zSYQUXe+sPGik8q1OztcrcrQUOV
Jn/QiUVrq60x2cT0yS+hqyBXjw+iY/SW1FtWSR5IWrHcWrdtBHhZ6ew3syGZt9wDlc0xQqtnnVhY
xpBGetG+/6iCJ6jkgtPUJtxDtZCd7rjYvy4gAYZJTU7TID2UmnrubXWKWPar7c34wOu1qpoa0Xiz
vH9EHHnpJV/zkjMT9kNeBWUs2GuSkOHRJ+DogqrHXebdpKyarx/f9oGQlbJbfw+0rBNzB0UTyF0L
yBr4YWYcJtgg8r6Faw0vbLMH50MQDDMtrJmAVzCpRFL9NK2H8DH0RZhB5ixutQwwQVhLeyXMbWx3
XRSZRxX/9Upr3HqUjaRZ6KbcThlTRhcqB5pjayrEKnViLwl1RAwD2JgvGZipRrJ445GrByBy+1dG
iw0uxLl9ztNBldtvTfAnLvUUO4j6tIoQJCLA6WldfcaLY3unalDpvyP+MlUA14ATuvosx//hG9xl
4vo66xQkyn6q+733FYOQCwhRtrx4qeGZcuUgMxkPrjLlegUUDFVCgg2yl6ra50eSTktHPF5KLN2V
DapiSBrlOF94ej5ZREpMrqwcSsqTdhyxXgwBQij+T+2OQ0l7TDKY5XZhfA5QxGXc/1Tu+fbtYeuf
igcm7ye4BhP6N5pZpdc4HbyvYq+38LbddpbY2FKq4KX+Kz3cmyqZbDXX+rkncsXYJdJCCB7O9zcO
lHTn4FzjeYk7OG1R4qwWdoVV9aGu9wt3tpxoyVJNGQFxHfd4W8btYty2YpvonlKrfkLx7sWUYQ/k
8TQZQFVDWatPky59xoIOJFTZi6vN9kTL/rQDzlRXmEjZDgpTfDRlsZTgI23nPumUtujFDOUChQla
XDHsWM6z4pMjdDwuCSroDbK9kymrg5x3QSyC2WgJkCtijPanmWzteu9+j/6ImroxEJL+d+Hxn2Iz
wBi1ncaB9UHz2pizyt1uQiR+wAzhf3KZUdTA/Jlf2ittit1OCevBXIrznkZw7FaO7tp5eU26aigC
6a+RNMv+dtC4jPGszu/7QpGssfLlgsn17CjzZSrFdoLcdLqsAX7UsA3bmuljzhwEDnEjIbgkiB1q
xuBnQfInOY6KZDeZeQuyRa2Rv4iaqlmZAXXRRvRk1ZqgXk8jazRoIr850qpXD+OAJ2lWJdIZtxkE
YmLLa6tSpMEN/viiW/yDPI7Wo/Xa3bcpjLCeW3YYOGd3F11ph7E1AlSuVBtNounOx1kyYcJpGAYo
17UBR1W5Ugo1fSI8KD01NxRjorRzfRwFMoQT2uI36x/nCs41EfN9qWUDnBq1uY5/zbseWEk1zKxG
NryPGYqxKntUAR5YKofa54y0T9doW5jeviq6anOiYdcvNRBNfMxhtVu+xVWkdSFDQ5UT/Q2AVXzP
/TEL2UYB2/naHe4okAVGEO0l3iNSgHDneCexLx3z6TcBh4YlZd13qQQqGfdsNX65YgPRWi+P4lb0
nxKlsn+d8DcvvS1LRzb689TZa4QQfNsYKWkZdB5szPApLRfE4h8Np00xkyhbzSL+PQxwcw7mIrJR
avLXjPSMvgOM5Dpg7bKBPhlY6XriorTB9tQqUVzDIo2ElJuYiHIOxfjVMpp8sn2mcssr4wW0Ce78
eyFA8CsxGYe2wj1AwlVUXQbktScZD3sZv49wykQpcpm/HgFJwhEIbgUrgKbnTohgTy5ggcAo0d8i
Nfqqdooe91eZelRgy68FxpZgTWpRSRN6KPbcj+651KQPZrYaAGxC2Zj3U3GR+B24SL2NJEqo3oUO
/dbJcWhoLdyXsLmSVDFxf8POMhEtSexvr9jBdQsBmv2snOSyNdXaRUbrCXA0ZvKP8C8d6XNWJGRZ
Aus4GePv0juGyou+3391wkkzdXyyB02BSaxmsdVEsD8vEvb7ZBxiAf9Cdqld0tJOOwPHoGgVx8b7
7CrW3tXC+tA9BkGBQYgaGS9PiK8U5ViiWJJdQbxhL+1gypet4trfVsiX9NAQNMWZBpyi+GO6L14g
rcVl+l9ypWcqd0J8v8aOnJPr0rla9+ovbHmIqLWDoFVWm1F4lodFQQzGFq/ETaS1yvlZNp6HPLmt
U4E59S29spRvg8CWgg6DL0HZ2QA3O3hsuSS1TiCJ2WU0WzNOnWbjdZtb0EeZaI0gkvoIEjh0tfxU
6BtHkuPgUlTepBIER8ttUa5bV8satAU/sIBLKvu2851jatX3MVSiRxeYhOuzyRYu5lNttgpPVyfp
TIqgUJFzjEY0VcTmpYa4QmYW0xeUYx0cx1sxMbxTeYYFLlxIsUtq+3cDaOwoVO7Hg3sl5awKO2Z5
uxEe5OZxWIgCFEYP3MA3DKIgaNnvyLS3G5oLsAv+x2UqoxwV0SGTLHv5iZ7JgBGUHN+7nMOkBTgl
PdF3zc2dqYLbKjfFCx2n2zalvA3J6/cU5TccEm1j70oFYACQpiYr0mdo2VwR3ydWmo8/Uv+ZrUGt
uxD55wkc0saEw39m4oFvYTzCXWZM0/6a6KvJBW1Bec1+oFv841mIAXGbgDHZpCUY3uuHHbFe1Btm
Qq61ZVx1AB0K9Wp2Xc2IEbH4yf7bhayF5YkIXoNM/aagUbmjGRzikr1xiV7hCWgWd18n+XcralVa
lWSu5RwKTSrbR6Fa3AAz959oSLlW08DOPL24jZ1cp7fUEpIakvwQlpWX13fmttxdvGH7+4VkdlAP
ajoDCCT+nrTyzsscNcNIXyIngG+Qs9QSIZzX0hEs5iXDb2BbyVhDHycXEzl+vqx7m334dVfq369W
qAMFrruXH8GbFZaXW5csNMJ/ggo36kQU1TYihjMRLkEwK3s8ZbatWmKyBt2xVT2Vuupzznp0R6Tk
+d/0pw0X8VFGIBuqp3Y1bRZZFmVTUnldF7tvRUpY0zKUfa6u0OvNHL7nDQd0H3TrUZCB9BrJyglz
Twf6P6u7jlwiN/1Os56y/oMXjQxHEnrhXw+D0ldtXdHyuunG/sm7/RrSzp+5gMldnEkxHXTIEHWs
RxD6wJ5YjF/+pi1ZUM+EpvSgQDcE0RtnYwt8cVO86x9FpYZRagVkv9CzzG6J2j57rYVvwd18zmmh
r1UCLmnrIIemndxE7CQewm1RqVfm5/TxoLxD9lig2jA6j5R2Mtg+TFyUC5DxN2jMSBvevDXV7u6u
aztecxSYwHThGZ3eukXN/H9q79FTwcoRtrpdDJfC05VtBI0WDklOq8oMJdAHy2PA/o1miZwr830n
C7qK9gjVGdV+CN3nvZ61GQKEZQQHp3HyaZ8vNOwTr7miFVp8GxTLy/KOgwQNsPfI9vtcaRg21FG1
yJWCZNYnRlCaqUWNzRWgIytOFO4ngU11NGDX5CrD0XUrowZMJI/AXYORStOo/6Lx47ABSoAW3TvO
XkX0hbhc/00M5kpVhsM8/SY8/Uf9VL8Vgz8f3tKBC35L33C6BvKES9q0WbvikxUtCYtWA5a6fU2A
/LyW7Gdfx6Mlg7UlqbUp78OrDQYOfE4J6tLcl9AKmumGjULPjqwkmgWYiDo94id2PB06eYjACHj+
Ttbdp5Y0s8NeygzVdxmVLfa5C2PhXwpn2gYDYOHrHrmOLtPckyesw/bTdZLuwbxZDuJavQ+VrH8J
XsxFz4yhTSwkuw0RnlWkbEyLoyWmoh+8K1BInen0kjbEdL3hNWsvi55l+QEgBUYnYw10Y7md6Crt
9hg7OUJS/DkUlbQyR6m3nPMGTSdTJoDX5DebgRDODalfoiBOc89nIhtrq7iLH9KEpOUyaUv/Zobu
quTtD+XS2Nv3IsK69k3f38N+/b5m3rekJ9BX1LqdNEaPSsc553H2eyHzQbQ5mv4kundSCKyUWTOv
wcC8RfDWK2KvIbiky+FQEpepACqIgLySdSpuN7cqjE/I7Ro+WESxQUlojIAWAjJsj/+uVbsREACG
5zyc+hu1XRxSkaheUVoFRkcFlLd0YpVLD2gnZcTmOvI6sT8+4vPE0gFPfS7U0eg39MId0nEkAJox
H/uKET0EsXtMdtXM/JXUpmo89WOUHfRkvxrVFrSt5qcf7wTo+mIu66KcagmC0p0U06+uBcz98kKS
Ryo0BPFJ+fJxCijHCEyhlLJtL/6R7eNl0cwsTOQCx6Ju0zljQPngjLbWU+H4JVDgLTkfayaswX89
GVcfbX/sqhUzo8YDA0RFdsNRBDG4SyWTWhePG9nlTFfV1YeG/8GdbL3eECfX4YzxjwRjzreKL3J9
wViD+DH8vgfoUpvc1jE9xO72y0ccCfL97q2JYJsMaK4aHhwh/RKzTrVlDf4yJKStRzGnkoNTZvbF
FnSrVL3H+wuRuc2Yb0alhbgXCe8nOfURF+XlsY3dyugCZ2BqnMDNbJoDjCTPXcgZ/wCFQaqBJOoG
YAQ1wcHSnRNMskDWBnOeZBgRmzn0nQMNMkUjxPTo25kvmyP1wGIABeYvVFd2axNDWz+AAQcX6m4F
bQiKSVFhejygVBciyfc8Di4h8fpQ2/TT4sVgCqOLpVCon4sszUP6DjYuG9/2dJpz7yf03rw9Zwa1
ltLYqfrPuyXxmx1Jax+YLO4G/Wn8jkIR7bQXP2z87eslCFe1qaRvbr29ids7jasknpgNAqmfGvrc
8YBGtIDlRhRk3CJpgoBP21ZXdR+xLHNxXt0Pf5kergFCY5z21jufldyzmE0f+DaHKadCxVaR9jMG
WmN8tZvS1Y/UDaxbStreyS4QB5ibrv4HmUyMnSTMuHKSqyPRpcj21T0PZ7vk0wxSsMEeMFfhqV0c
pd1SfNdf3FWZaEaZ9wWIVeJgx2Tu0p20wwmxihSTDVqAS3v3XwEB8t0rfqpdyVY1ZpsscWyn1SIf
xz1FNctXeGUy3lObKFOC2mb/6jLpFd6hqvqFXlinz2Rl8zyif8Bctstt/bHGK0RW34VpRrUfM6v7
OeMek+UZqLIi4vHGkPiQYnuEHs0/B+xGiGkIBs376X+/7/0mrzMp7NWhSbnNY9UgltCOJOE6XC2K
9hCGmp9juTJ6v+i2O2SGogrBAZfWURZVoHRAE1kY1/2w1JarnvDx8zx58mzhnCh0wzS2fz5/xad6
GlJufh1gROj8OkeW0XCPWfIwqtqYUgu/m9Y2CngqudEpc4qEiaEEdRuasTT0o0vjA+7TsNDcI+R8
Ao38VAWBj4sMQOvM/NUhc/72aqa4l3q0ajFQnLMqzmszlkIuElMXHZxOMdvOV/Zry1gVR/CClVPH
BbKdr5m7PkwZFl1LaFb5DY2Lgy8NTtWRNrsHq2aRwfegtcplGrwyyalKrCf0uxhtY92juQw9+q24
//tLDIVeuAx9o+hwtHMTH4NFp1N/njtqMkAOcIk1++Zw2uHN29AN81qPlX/Q9QPSHp2k7jkL+B1j
bKFO5UDr4qg+CH1h0ySRl7cA3dGApUcNpIVuGAUSiLW0HuRTuOEV49Kz5we8mocMTU4fsW83UQMM
HGgtbQJV026E0RorS8lpfgmkEaDE89KCkGXf69T9AIKpH/siZydJrXW5wBRgIAJdNO8eN1l/mrAk
+MTmtys2slNvk+WHwQ/b1oyN/JH1SP49NN78nlO5kNdPxMws+TGF2jEgdPZKEIo5Xh+7VeiRGOmv
cyGYddv3xmex9SfGolymBDhQB+OAllzoig+utDEfAVWWbwTI0D7+1NQYqHo3BXqnRW5MXb3m4w9X
zdMz4CfyAiQ7U96s6ClgDDwbQd37VZr8DQEKilTce6EAfDv9w3xA93bYqpVdiUqqKB0kitQflxqa
7RVcozytKjvFN8qVSACU9MyYBfHUOeVlmv42DnnDjQag6jRWfxSPZmQgYbnTXlbBr3ErL5v91Ygn
EOeRmIsc6DUThb0oiIqzYURNmNoCNfXFNWwjT+ZqxTYJEQBmp+imAf+N2HG0JVNiLLFt7xczdEti
vuVN0OnuQJI7PKsb6o8+m6iUvSFDOhv8ZCUSHJcKoZYZ2B6GXlcabSzshZBkuvqGVLkxToFWbDxx
JFxz+mIC9446OUYxfZbllciz/M1uN3J1bOsUHxKwcI2oAcwqnlztjTbtI5Tx0JqEI3EHnRGmzVyc
DaGx7BhFh6UyA9hHmxhl+ck2g8970+eslUbBtoNYuECJxIX16nbpychQPteAEXZdeR7rhC70hDbo
jfsRcJP1uYYpH82vtIlFL3v7IhW5+e1eYliWSreq0PTSXRgAHj4vJ+SYO3w7lclW3eqiqk0N0rzn
xafvwZrqjKJ/PaoOfayebPp+zDZqjneyQDAERbcQ5IHrUMTnDNUxcM3C0ldcl3ItrpT1vO/S0w43
oBnh6WODS9jvYwdDAQYO9W0aKofvsdR5EZb6WTKJJLj2OSo64ZIVnnNmW/LseRr4m0q/rOAN7kp/
J/W5lrWHGXlMFToHinRaQ7N/Jpd41x0spZwu54Yq40A2ph5eGxjY/p/BK37ugSibUk5S7ffYb6qh
0THZuYne1gwEY2U/UL6LGxWV9ANp3FfpgUa8ayaZFz3KqJvQMbOG0+oxIR15V8mEQIf7ExttNCzg
MIbmhb13U2DZXraA6T5jkpxYIXGpX3iKdqoxU+5hGkDJ1MHkFd8k58vc6mlVfQHoEGgcKmZuFRMz
Gh9Yu8twh7AbOdHyq4+lrFMzVSu3FFsf1baQVh6tDb1pxyfob9NyTSMbdG2ehMC+CTaD1UUsoTIg
UKFT44IPUA3n/C+LaAuvb7g/f5O+UQ/1PkW+hg0qbh71nurlGyPHN8K8Z+ZGoi/fn4Wn0y1Khpfj
gvfDMswaLBeVx9ZTDF1tRuBjVc5o3zn1SxaKeSvGImquGrTfBgbt3j3Y4V+iYR7zJOtjuwfIucWU
DWlwwQGH1O0Eie7C7EFbbFVyHqCv7r4tZHI0EBKzqxCqRy743xhE4MjxZaJ9Wbc0aou/llnj4Dp8
fcobHhmkwBIToe50hOUzkcIeLPP/G+8Ju3HfP/xo61RfNwUwXJsqR1dKh5MqHNJIWsWWxxVxoEbA
/l2JxC9pdXEuOcW/Z50ZqrHSdfomjlVtb46HKSUciiMPBpZB3zZFUDXkrbg8EWRFvhtsEJfzvS/L
jKCsY0um8MIb8zPhTJmIs8Na+mNmJDgxAekd10PhdjcFd0+FfOhmqrY0mVm3HXjWjTT5UCoaIs/6
g2pinFa5rJmuDVkiiFzI2JkhAsRhgY/nKffXCSlREeNkLV91IFLYR4ZmsRN/xD90rgK6H0N4pPWo
in3eEkCyWkI8ZYGY/odenggsp2I59zyyQMj8MATQ83G75Q+ONEWftq5X003nIIRTAXVh736fjj2q
ap7/bIM+BMvtkORltyf5Iipt4lNBBBy82zfHhD81rjm4fARB41bv0cgSB37h4DqipVxKgtQqzxPR
sZPunADY8a8ts4J2laZVL7Vr1O2Utx7bnCmGO2+ffHhDfX7UPFsRKiOu8cUKcnZ3Dg3Y+HIjhdLA
U9aVTyYvYNflTz32h79Yz77WWfnXPLiIMHAf5vOzp3yvBAEb5DodWlkMOddfOCCx2U8SqGiUUOjd
iphlIYTnyLDRAdHkVz8A4k8XRPFcLumM+l3eMW86CdxeZuaiYgoBJhJ7SjwT4WkE2YpmKv2bEJml
OUidaZY8Z/4GLaC24ohL5wIxQwNGeSfnxtM7sIo6ZaImWg50+9Q1XL+NwVv7+m/jth67L8YxpQoy
8LcESI7yh3PLvwkbB6dVJXK1ijFoJX0iQ0D+EzYb1GIC92SeLC/tt2WefmlLjuwjU5m6GZwfNTTx
wz72/MiczuFlqMPvnsIWQPjq3vc02JO/arQx0vVdNikVINY9j30WRPMQI86iICm7Uch5/jXJ3vc7
tjr4z7lyyf2E4xs786P1BHb8si9ID2ecYEeXEsv8/rmv8V2ECVy52IwsehYuUoAGuDO913y6aICM
3V+TYkwEOq3DaSdvJi5JIE/3J8fKeboZQ/8xZ4EuLofMKkShJQI7/DLgx3HmpFYYN22Kx0oLTUKJ
W4MEm7mIPJDJnAu4UklImOZ0q0lEfOMIRZsPl8h5R2/N7cGsFo+Z4n94T8LRhoAXT5oiUt1fnaAT
O0T8lBRxm0hEIAbM2nFUslJgbfAEQLan6+34qKELqyXfuZLW9LsdEfFym8fIBZN/PwoRQcb6Ugwf
6bfKBwFbq1gzJ2BZMut1qBftaMCl7dMjgkdHWIPTj5BYkIqRJ2mYbz+2Jdg4hFWmNzCujfRI0qul
3M/FuleMMIQDK7NgZk4eBV07/AflcqVA1KaOZzwgtNEw56UGeWWl+OVk/KDa6/pP+1tvjOYiuXNu
z9SDUh9ToIpcRMK3uX6ThAgg2a0nbIzrykHSrZ1kjmMxj/lu6yPBNGyP468rYy4tkrDrDYOfLB1G
OXKWRg8OrilPvtYot5nIUoU88AvCMMtgWNZ5YkkveF3cZm3LzilVVHAJeFQNNy/yHQinBD9RB3/b
RTg4KE4c80dBOe//OwgG7WRIYO3QCEvPpVNFRsCU4SNzYYUtJlS9JcL5Yo/IYQLZKjRyWeO1QpLU
FE6SGlLxE5KPVn2c5PI1hTm43BLJCo5QQTWR/D6RAhC7yiiIjWgdGrud1fqPFRD7CvCNZh4xOsiM
I3d21h/4yVB7ngu+OP6vSVp4SaNa/QfUVX89eauq6GZ9nSaoDAg/IVsKZu/4vClqusSFqTYpNWDZ
cfH8xPiqiSfd74iDFuJQrbnJo6kR3M0GkuMVq8ukaIJzpUNj75OK67lUGzVZk4a2PK5W52DRKpde
0MEulsFMtE/jsC+aIlO89H/6JTDY7QKTpINCud41+3kZKtCq1xakEkxe0a4yDKGVs+cEw33DHmJe
gOBHwX9UX/U2feCIMBQMAj7mZkvt+WAvBuXA15LI/1mciqz4Xqg9DMn41K6ZrZwpLDPNgDJS6HNW
9Kp14R8OcaSTKBtCC0Yo6vFyA2H/MDMG/SJ5SM7X3AfMMp7qZMTX260+nkN+YBtgK+5hne+0LYd9
IbVK6HjKiSvCvYJsbwenLPdUSHxAvuvNYbDC+U380dvFaaYBy98PvpHTMGDW0MgXLuQ9eTGh7b5B
8AQaa8/WuNC/GJhgimkY92fO1nQPI65fN9QfNsL0mBDkmwp7f22XG2NXlXiNeyydHhZv9TFTffZo
wghEcGxjb/ZVaU50u6mJw0HFi2pMG30lnUuQiZ2jDRYe/YXR8gE1mtwvZIdSR14bKkM1vl9l7qky
8V8bNrZwuNEhe66Cf2izHNyi2BVp7jMS4PpAIOXInkJpk2gvoSs2Snu+d2JX5mjbv5UnWyrbPW8z
34DADaNwI/OmIDo1RKHRzlsohk9v0J59I1LgwHSXiXYbQs2XDi2DKvRY0WT8I0zHqn+wZv0yH3e0
5+WQo4FqL3LZshcSBM+A8DLuMS98tGlX35oe5C50xwu+hihBVoRzEbkvP099Sn5ONrMfqCcrxgRu
B3ClZegkknHTP+5ZronRGzptkz2EcQzxMqGRQyzFI+VklAZVWMwTa6KTvN+daqbLkyie5iOW41wG
GAQ8J8MSFvWYSGgM0FFy3DcGJ9Hx/JWqRQnh1MIpcx84waY4dslZ7dtKJegYofPGK6oV0PgugX/K
A7bsiDRRDHKthvI+s1e5OiNaaKuJygtKMf/pXUO2WcQDrjGy00CduZWjM4VLil3grX+03PdC9D7I
8oHnUE4xD3B1V34ikXE62JgJtPGPFkTJvBvdm3sIcj1b3UHhZKNIMLEyX9/4AP1vEBmla1FWWZDt
e5KPrh9EhbKjSD6s50vBAMRxggxDguWyfMLk7sbMA6QSSvFizjH5XDauIjF/D9Tpnb099gR70h4O
SqOnt416+xRwRUgRtNck65Ci4q/JmwznByEAQ8ctJIvuBBfhHuOnE94A0ZvuGajc4aWrrfx1KJfi
y6eesQFX8I1igvF9GY8Fp1220f3rPnyhT4xiqHb6HBJMTpd06BJlSNCGMYwglPPz8iHfNfK1wp5i
5T5AweYEDnYFDDr3XY7qRGp7bTJUEQcVOmiEO7UKGFjLMAuckq+G7hAI6AJ1UCiwP0kPxS628rT9
SpN6Qm6pMEE+RXf9giiX7fgwTAPmtKdWxZqEXqHdFF2zEF1LgxQoPubNkffod+l/+qg3tvWncQbm
4laSLiQb9jQcuo6tlbSSAFVPE8eiFAW2FYZetgtVr+zDtolvi+KlvfXVTyHWiJCoYAqGVQajsdXK
nFTtzvhQcY2vik9FfIYZ5LS/ViUrtjHFZkLSvj5DM3RXxkkDFCZ794EGxAHSSacwCrcHOw0lTGlD
Vz3AYluJb6KwcwW6ho/JQ6ohob4/Hj/S2VT1wz3JFTpUvlUt6oiHRN6WW7ZLCY6SuOQ1CkPnEoNz
G16tjJwr1CCbff+TzuISHpOB6w9y6OrnCB9fssR+Vo63R7yFkbLP545tgLsP0P7hCBaJ1WDX5F+R
0ht+XrPx9dOoVFCP3q9OeDKw3rFTRC+iCkkVAs3T+qGwKGA4412vtGY9qGArcZvFTJ7ha/qhRjLS
OajVkXfp0vgZm9LbPHH1JGt5rfZ7RG8UhrWLoqHylN7BNPJHeBOcAEDqALrHZYlHvuTNWWBpIAxW
XAaXh7/hjtzbR5RNq9D9Mu0SFWwgIhg9KfFlzPoIfrwqj8hbeA/ES/jR8nU8TJeQVNc3YbgN/GO+
wXOlIhflhtmUpiCaSdBrzeC7YH2NivITecd/yy7qQO4p384zjJ3BAReZ1g9Yt215qb0ysc9ZL9EP
V/ADR0hXrv4ljhpMt5Dj5j+OJPXZpJb5iqXfU4pMEJHx8LxTFTvhMLQLI+9LFckSSN7W9StCjVfj
ZTf3PdQ9cyaBVezQoDQanB6GJ2cy24ZsS7Qag6e3XggaW7yd47Jox/6mi6ZZbTSUa7ODcNAXBS5/
Qe3xMT68TC90J8ygdnYqkJNXiNWpKNhKpzD9oza2zgru+CUXeW6vGJm7kT66x3NO4l3RmrsnCJPx
jpyc4CdTB9JpYYPj/iYlQn0IXXCI37QqX5HXOGZ61CYJMVV8nkUl6LwGFXWYLFHYx+8R2SOm2Dpf
NY3PAhLkRCPHWQ7VzCLeyWcaGDtt4jWzNKkY237yuoyZPFer3aSlol4esujTei8CmflxwhafSvRZ
Y3Unb/aAqRGTsWhhL8ZvSFOQ4EwB/CaqAq4NTjLGcqgoZ7T8HOaXhxfCQcREKr1m8nDKHwSrQ6QW
cpdZ43vAoGXMcicHSCvaFR/1LZdGG8wPnV8TMcCwbxX9Nfh2pwz0FfeOju+i8ykWbhtY0Ueio+jQ
J5dPTUK1nobhwEHugz8nD88TJuaOZ3pFzw07TCya1VSCP5qMiaLWsO0764segsbibpfBXrdHEoGI
rKf/+0ZXbHxTBwetkeXzfSmcGI7ub9RLVcPmL9/6DPDDOxm3QdRw8qlCdiKBnOiV9gLmmw9UpdhA
VxZ0USWFR0i6dgfVj3VC0NukIzEoxaV4RnVXjYZNuxNyseeK8BXo4PN0O3p40d7H65/b9VXnUj+5
ZXIoOF88XhtWBjBHhRgfDPFxxkEtUr1JWGPPPOym+kwS5qBrihpny9R6stogx/gHJ+mnZwIW8txE
MJ2QoQxJRp8ih9Sj1rzmgF1G9EbVLRkbGvMh46ZhmMSxApTXVCpZOI+IHNEXc7Xxu1nvOQTi0HJn
U9fclLNBvR3VZG/YGXcoHd+MD68RFa0OwxsCMRWRZiPg/t9uPolspVpbIdt7sJB+xe+1RqgLs9yw
b0kY6TYnEgT1qsAQtOgfA47luIeQ9zhORdsOlXbnjEGfIGna6idGc6mxYiadHeJDYpdhHSB2/5YY
W8dADq0okycQEeOvkTBfUAsbAKFXU0BPOM1vavBgH6SnpVYBYQSTVWuF3Th8TgPqi4VUYBrg6leu
bTPvFcXyArBnyrmEvccn85NNXZtQ/TQm/AyinxcBMLmkaECbOnpmRM2gQ8FVKEIkSvur2WE9BCHX
5yr1ibn4SYWR4xUf2FTCF0N0gBc4yItf/7aCHHXwfvTmmIncO6mrmcNeRvqgfuAt6xMwti9xa3wz
mz3rzygtXyTbHxduUKA5gfoItlPrSUATZKHl9zrmaRhoZ3QpVwxXr/Ol2vemPcFBifD6eSLfk4fH
YMPBwEJdyIVi6MNLI6h2auaZ41nXL2RC4P+UeOJs/isERfDzUWZWpZXo7MEbWs9de0mPeA2Pl7/F
6q6WxgayiMjobNrK7aQKeaxs8Zeub59/N/fwZEOEZ/m/bFbxvooZpqPsO3POZZYBIBBmp35mZlBf
6LQofANiygkfJ3e3khZq9eB9U71fOqSgYY+wbKvUy5N/PccukdyjpBuCzjjgc1tgj0XtegHYxFtg
Jwt55Z3/yCN7tYoJHVLXj5iL3RI6dv+NKpBf1SY/5d4BYgSw1nqjGvHSwzrunXCi0T8idiaJFS1/
T612sql5bf1gdRvvRqmO5FRGAKVUEUsklvg/bXTbtwhrZzWNcrfTNkTvHku4BCVkWOXb81Z6Kmvn
eihX73UqKhPjTkL1K8mus7IhqUvy7FmM050tGlr2Gj/wE6Cd2o6r6GJeCjZ7Q9FI5yFHfuIA+DcK
v6O9C3QmX7eDI6n56QnfI7/nUi/74RNlPMdAo55/JVo9awyYlIydsP+LPUZFUfKgLf6ar1w4XFHH
nDIXq0onfLywrFb2fV/2IF+s0zAu0UGmkr5GBzDjy8QfeQTLdhGkWf6VvSlp2gYKiWufPAglqWzS
xFCBcHRiVA9pZ0U8hA95oNo1ELkyAjGmWNO2GcO3CSbwgNxns+DFqtGsMy6pWAB5DFfCsk8Tq87A
AoQmaJ3eXZIpCwVVGtjTUhKkTOpR0FiqSfwQCb2R67n7YVPSNF6i6MHTyLu63s8hBEQd6rasmplq
0q31LhkOzGM4EEFocW7j+0YMpSJeJxEKip5NSAH011t8hvteoYbvygP248KGNCaOgK1mVD8FBfMf
YpCHDvule+UgAxYI4w+gEMx0HgsLbjLdJry0sJYEdiDpb7Ad6GOHZVXyGAgaJDfnVnxosagZmrst
Iu5JwGGaFOHcnaESfgNv0Ekbauolsfy9fYJUQjGIC1f/EeQPx1nh0PY8aTdY6lnemCprx1gWBhmo
0RPqt+AwatvPcrfXEs41hz36lgY+b1lIP5Csk+W4fIx71S20hcMcgA5HWyB2GAPXXMEbfoa07rJq
7yWbqtYFpApjCBb+l9gL+90HGKFD3qIYMyV30PxB6q1CQqBwipT55swq/yEf1Y/hbBKd/h/T6hDz
z1pX4qhRJCBarhy+kWQwCI8dY8wlWxjtOdLbxcPMU6se8fh0saq/OaVKYXh0o/vggA1/ptldcEtn
YhDpliG7b6TPDyt0ypDzYpHdA4fDWIvpotMJaIrkbZl1Atb5vwFRLG4Hr9/j4fLIc7J75P0xxSRx
aZOHbkJl6LdOf8WADeCpXfn8Q9APg4aOdmcSknWzg5skXVXmrOzvLoy+MYplHDbC4pfFIReEcW6l
cHwh0BgQEx7jpPaE5r3TAVoGu4r/bqsZs83JuCKGQmdkQe8IX2ISbE4WThi/9vI2G2cYXa9/JM71
XHUc/B9fIc58h3AGdAAxriwWdK5jEXtN2ZvADdaiZSIsSDN8Y6Jgpiea2vEgc60E6fgkUkvXGXsL
m5CWtqzJs9rHDhOvHQOZI+2rfVaEAYN6TZRGzy4TdfEZPWYpuG9v61GgsahTu1us9jEuuNstTYLX
wPgl2Ma5o6SrZUPY65ptMIfuKXqIkiCUhKzBhZ2+EUqxkTbQBEQfqZpNZpbl9MhNFkkXSCHWWR4s
u006aXBdDNq5+Ph0MFoeYYBhWj6emqbRDOkDHhLoRQFoqeY+aCpeqlgFSb9h/9dNe9QhyNAxqzh7
ynZU9hlwHVg8/FA+D+suXeiZ7OR0y+PPEBjUjZL5lXmErFnlGB/MRo5Td3QKv0XFm9rnARS0iDjl
UB7WFLOal8TGyPWGJcovLIMD7ypTpcWiUb8fENMray2jN3Qx2Hs71XkuF/UfMIBT44mD06QgOeyj
MmSQpBKb419VWO7tTxV2LKw3ywYO/tjuHGeCgCVOOaiH9Ewq226BtV6DwMDIja/XCtcQ6ctg0nce
BgnNJamGkM7lJ5IcNGv63u978EcAIW1bmQ/trvtCMLZeJ/C05RqmRQ+jwO4PNRCgi8Icl+ViaeTj
/fPnaWvytpSxSnHpQ4nUbpHP0tK1prYn8k8jKBRXmutAs92qlSyL1/qA6t5Y+18flWXGnJ+0g+3L
jiTK1bserUoHMlGzqTNa+rd4j+JgzSjOyJQ1S1oikDUPEwWrJSUgE7QS/0+tUTVQ5zqNVP4BUfKR
m4KIYXMN/iaFbVu1+bEmrRFRt616W1wcCAnfrvbST1edy2FLYra8r95My5mTf8ku0pE0rpipIYzZ
rH5sEBWa/yVgiNov4pCVHvgK9E5mLYZnlntm62se3KyqemlZV1CCJoPAL7+WOGfFOjMAuZT1vVCA
ljE+oogsAGvBZFNeso8MDj9KL0y/rNdu+yMMgS5/8t4cwrzZW8cBogqXkMhS8P0stWR19Vi9WFBs
7LyYHX4O6cqugD5dSRt6qiDd51AsDsM5fPSse0G4kexcBiF7bPZaioh9IAE08QICqLEwEWv66Cp0
tHjoHaMpUdIIdEhXPDppVVxvOC+3MOa4nM89worm/n61jvvHq6+Kcm49ZKbcrIL4LhImalg7c3FA
8UgY8oKbWNP/FsY7Gv7OAEiaXaK+6fapoALPeQgk/2LBHbQVJPopTKInt5ugdd6DaCRuskM43O0C
uAG7lpRE1PzcLfV0OwUvGZD4B7aLEx3B1JRXCbmcTLH6igyp3K55Xrc83ROjG6YzVLatAezbqRzU
E8fshWNsiekbPyo6QKwJ7sLVTsQRiq7Up6+j7fOzYsp/8hSJ8K1qp8uuTIfP7ehZM9Sbbgcv0RpB
YBu1oHxqC+kxOE1s1L5pwQMDxThAw1Gi+cAAEccTbQ/81vvT1zU+zYXWQxFJXfks4X9s/UvqBYvh
PXiV83jm+zckV3MKPGtkYvyKaqB1Ryt+fPO4yqrtCKSb9SUbLwpoE2YGynld3stmd80N/RRpsWRh
l6d2A6l3ZIZdAo0Kgfl1DW1oOBJ8zxBS8ra3uJAIjExMq6TuGdRvRCAWJFQL3hYH9RrULlwM2T9K
E/XJnO8H2Pr1k5L5KCg5luUZYN/XKOAitLNC74TRRKuOXvcVvWoPfDsdBUewMQXavyeRNcxEH0EV
CToHxewfutAlTtQ87aEZUpQ6vK94goGr+JtJG5ftG0y4dfQPKfC8dw5Q20XYxWRrPO99u5gg6Nbr
eQZMLmvv55bC+Xu9MW4UhPPS/ciohbtFteSKtBY8LMlqqzDGQ7U5bKOeJHvDtnkrWmDkYt92uU2v
QLRb3e0nvaA9hdqwcCN8VQy2giKpgQGlAbzS3eiltr0Jerlk6DRBRd629XHePGU3OYzoXOg6B/el
KFAR7bX2vdwuEOqm8UewyDYdFbptddWyUT6+/e+uu7GKspsiyaKYL1JAoF9nkYsIHa5lyHkRLDel
5jXmNknIb06adF/nIfiYe5IWubVlCRAEwQaitiPsEWZeu6Xi2HEPhRJfGetLoWtPs/kpeR+YSfqV
pPMJsRo0qSLAlEREVEstqyU0uxq9+Mx42hbM505moKQK52BScmLmOCw81kBOKV5fqVLR1HUuJ+0S
VL0xiP46RqD053SUuQS934jZMwXApNR8vuDJMtss76Arghd5dZghjtyviMazCWeFkqpyk5fGLOJJ
K1nBv5l3NAL33XV9DUohrvj447ZtMSxe2v0XiVajGT7gNOw8KVChtjkI5tQrFy3jYvKuCLexid9e
bBpw/tG71PpgYHQlik6Lv97Joa6J0uTJQdM/FV7b4fffS4hfcAv/0nGO7neneCwj8z9zdZ/rWsR1
x/vDkrf8neSmExjV395VimqBZD9FnntugBS2QQBK2SI5LDQ74URgBSWOJ251uiNoVvc8lxjwG94n
EKpQKU/2aKbPUl0gr90VOvhZYDG9x+iRtGa4fZziwVAK8RQ/h1esN1U7do9wVr6m99oqFOGjPDZj
qMy6y4Y1qE+hBV0hCVIjUD+0grYhmjRxX1/1tT7mNQ9SEASJOIFYc58mk4ckaZtvCmobxRKhQI6c
onCyDn7o6A+PxL8Bmkx92m/ztkWI23JWpOaahi4wI29KAqo1nGIfROKHpSd9VpDMiZ7z1raIAbXN
sidzjBI+Ozl40LruaROzHTujCulJTf0jzhG1nM6Mlyb0B9rO94GHB8PokuNs0rKnYJ0Nck0nJ38w
7s88bprN/driCfm4x8EHnjnDLAFSsQuL9TckIwxhgj/TkQ+cj+mhGfOuvLLorxq1S+D44mXgMmaT
DxPtEI4+7LnT7lBBZ40axmI6XsNgc9yunC+JX83agSIDdC3hNN0DktmlbtJXA6SpB/MQgEZcspcC
4rCtJb+4pBnqB9C5G7pllcAs9edYFFEQFofIV/eEUYBV5FL8kUoEtJCSDBa1SWMJLU6i3+9FtOlQ
/kpCuMJGPTOFRWEupjPg26Yzt1qX9i+khETQOPXjhAiTvKQpunxuS3w/H5l1ciOztXMePn/fvnMS
2/jPbRWoj5Zmts0MK2f0kcZeo0bnK00lOMWsOsjdC9xMr1jMEmtWT9v23wGmW2UQyb5MZiVyQSD3
h0wORgmZzAs/ORo4dat6vGr4i8qHBkuxGbPWBfBpKExNye18idkLYJbfKkjaF9sFLtPzjYF6on24
iWZ4qsNDl+HOvfqhIT4faRRVNLCAYNHxyf2b9EOlieQfA+XsY9hX7gjEcnOcecR63K4ukVl6ECe7
WamvwmQMifAdlD61IQtSzkUx9j7TIDIg+v1/u5hXW47AMIeOxtX7YHp9STI8eJ8zxcTA8N6hSCoJ
VN52bAU5vhXOT5XS4eqoRmJ/lmJErYVWe+SsyEnJGseW7cVSzTOKC2rwk8xtEjeMH4GQDtaRq7yD
DQuaFp112tCNPwkLi4gQw6O0Yei/t7Lv9LTuT7vjn3uwcnnj5QISHQsorapZquHDMOVR3zBNiMKg
bF9qM6zOIi+F+FHinTXNKl7fGSBqhjYiytOSPU94MVyyWKM/1ypaZF0BJI3gM5SBiTwktw3oPwA/
RoU5ng+b9g23nmkn+5WcIk98aj4YQAWclDb94w6kb8ZYfwSd/S8gRq66CiV+XmlwYpbHBT2/FoJx
H0n0uJ5xwxnI/rR9pAX8RK17R2tDG65R898ohkKkgkRBRacTvYIyzlIB5wSb0UNG5b+PZKIVt68R
LINduP3b4tK0uf4uYWYfrrDK2NYciFCslZLYyU6X+biookgEb0Qym8JKEBC76QHRhwdb7zB5LD/C
5sO4k8n/SE33t92T8zYBIs9ZwAp3DXt+YBcgmBo+tED85BEn8+7eJ4E9sU0qnGBeaqMIyH4fVTcY
dDp96odTqfi4+Zt4AyZMDlOcGTKjDxzNO+PiOL2SiaW3nKqcwnfpbIv8ZyMWJm9JB5wXZLXica6Y
Ml5VI+B6BVFiOsFAejYo+F1Wir1snWabQ/fE6ABz3r1y+LPpWJu8X6y8ZVUsegzC/MgKb9MhQwAT
Q9PBC7iHyix12tIuIsoRYQXZh5cwvOJpfLSFgCF4Q2h97m9PYLpphkKOhogM/tRrXXtc/FQgR8Qn
QqoIKCeDyuM6SrApRjX1XsE0OK82g4w7AHEhz4TEctkQak37FxGNxlsdZF7NL326FnIzNdeJX3pe
7xJepfvuwkYwiiuDLTOzdu2J7Npi/afnRFHml1YrhP3ZSruG3Rc2RJFKq9wkR/5SYVR+v8kc9WCc
P1+NvVxbdTiprVyESm/6ioWJTrw1oHSunOK9Wc5F4XEslGD3PJV32xPNmyQhkMyXqLOPYoJkQVXN
uBdz4v6oOsECQGoZ5CizEc5mCwe2+qN9PQJafIAMb4/1PKPE4unjerXKLjvspLm5zY8XGYpnIDYZ
nPh7MVnz11sRYAzS1pPmo6cJVGIkm9dv8nhoSjS4mP9xMmcyIzC8H3aITZSw+1812aJa3vZgayN+
ADHnTSVqJL/tcoB/5N6DVcleWcQ/AYhMqe+S5sUf1RdwEtFTDBE99jOywRF2tAsAtDzlGGq8wryK
ShA3sGPmcMrXdCZJbiSiLLCx7+Ud19HfMZFMdyF8c690yBPzkky5ZqexEGwJ1ml97EYSC2ZStqbW
wgTq+kW3Thff3dWpzK4SCr57jBmV3d4kgo1mlP3ExJqrEaGp+zoyEOQqO01E+/IcT4dAFzOy5OG4
fdbVteANi01rrE25s8gSywN9qi+0ExyCaWEO0VP89lIkRFFJF1FOhm2NlwQBzhiJkVPQtJPUVihX
SVU+5Ds0Kfkxh/SUmSLRmpHNXcUubbVvloG/WC8FMLurBebD5w8hx51bD1jS0UFPOme173QQfs5O
5Z5a/eN8cnEWCFXG/YZMZs3UfVdd0w6fCLK9Qhpk0q4Aqu7pOCQm76bpP5xUcQH2yo26Shq8/vaJ
lEVn7OgfB8W/rKlOcrCSv791/ipVn+6iVJCclt2bhIJUXElqyLJveaUzCyFX9rmNZtly1gpdmKq8
u2f/qXEKjlIXXEgc53QoU08J02Iilj2VrDtQsGxPbDnqtSiKOzedjwHqJ2rKRO/si5TK+8xIXzWW
K1QUQiOXmSFONXsxRe4POwUrTGOZmMY+kRESVVhYYOwqJyLOlsoldoc6xlelN3o+zUCePw7FV437
9ZA6KMjsCwRYDrVoqL/1ukEs+wToMPw05rjaz5/G7V+K9obd5dROOXYxQIyiDDcQL3WM0MMArYQa
1jhD/XHi9nj1q4nWHKJQuQ8VpBU8A1sFdGaQN3i0aJsJkUcX1V/W56v4aAMxoZjHFPf6Zd/INZHM
L78q/OhDdzzx01G0miIUqH/BayH6dzJsDTabIUh8PbieCMSzKgvc+Z6aWOHWNg8NKs8GMFuIQGBf
P1/weHm3Jn8rEJMh3SHEZsP0zv7JnvQbgIt/w2mAqdZALmuMjaqdrfhagXZ2EIFTCiB8ZSFpkrCc
b17I4ytXOLbzi5Uc9j0q79GdLbn49btaADlZfsssEZu4f/Yf+odID/5n2/NCXQfPjfirWQSFN3E+
KiilbATAYdfxbkhV61ov2DIY4dybl+8QX6kEqMkzESU6cC7uS3JeLJW47WFX15iQNT00YYP+LRaF
vd/5JJHdkyDF8gd9WMIRMrLhO/kWWM6iwCaTi76JfaoidmSaQpCPXLixzan1CZPB8/k/ZG+jo7mq
ed1i6glr7Ja81OEBJBzxuAEmQ7YpdIvYT2MOityZlKADOCxXUbbWu6vioR6W+HWNbQinpdRllC0p
fHURlQdj/nN4kBBOZVGRr9VdqaIJWV6IN8wuT5+hmH0NQmAWRN+eqDLd39+94ssfaiNZ6Ka/YbeN
HkdcULRlxOb4wv+rndVTQBYHoX4C1YTIGKvVd+Ag6et2n3c0q5+W+3cu3oI0VACptrvKrIGcLeQL
HlEtjoIQf+eCFhKVaqhoJHGfzMMczbLNkmaNwn/8Sufnv5VED6HtujfUSPbOwMxrqDcVPjxACSSK
wZp0qaI4cxtYADTSHGNyppewXMoAkbKed6owTm91YXCxRSL6OkFML8T2Z1fJMT9Eaaxg0VLldsCF
TA/HrOW7kexPXenopmLbm7RTDHNjcE13pzGPu8cKXWUZ2lJ2fMZ2DVq7zmqe+R4jUE3f3DoZH4nU
iQtJHe4PLlxluHByQWwpuSLiHg6jUiI8fl8XMrtxSmW77WyqL5oD2VeOXJuu1NkSSU23jSSz8wD6
A4FYgTpKWSsNmDTxw+vwXGQyboizHGTcDTb7ST5InS05TJyaVZ6fiLf5jfFDwmk5vDVBIo9jU0oN
6AXSxLhNC4wOetVSJEFBLSbxtsN8c16SM6T/euu1gR7oIjWhzUV0Sr6fAfx1M7/U6ZdC7sC0El5n
mapc6XplYuJqCgb3rty9jdZ/eER0bXTesLnm2ajOTJebPzXnycqICe4I4MojO3wG8jUD9d4bNHWU
ZMFis5STKK7V6IfK7VTWKi5gFztUm+4mdxhvx8JkFVNE8rejGM6OAzhvyCgB1xKK89HWug2F1O9k
HtybCEk2QnqkKOujNokPcJNdq0gpnymXOFsxRxHbvqjS6Mf9ejr1zGZqZ3IQbQq1W3/9kgl8gGCy
zfIBrYIx/DwWKqajbwgfOLLi8mTtirgzqjHhTJIMbdGmO8KvjkqzRWycgng9VQDh7N9I1UZ+OuUP
vN+z0PBaQ0gibm6L3kmHfRo9PgfQVk6SW78KgnCIuH1XJAWITOPm13XljVEKYqYrNI4NIPIaokXs
+fS0Z66TIFjXyHHmP2yBup3HDSssSNTLCB2Q/vEwNb0ImGCNRM0++Fli2RvdOcaaVo2IFkUxzU6s
iXmMyAzPpzNB/38NMTUzPVXDVDoSIx+7GuuuwBx6JMhxj8ypmIqU5QXFIQB5CLOoj4YtnKQZvptA
UtOfJcPcY9v+NKjVmS2IUM0NJab/0L9QuUyaTXhz9GMSH3NqCyxM5REW8zLhOmJF7Nerv0bYjVX0
RqZ77zTnovEXc+s+izwioCmwy5R+3KpboogKAy89bi0boZTmb7Ygmjb7/9ztP+9CKG9BDDP4FK0X
1nt9zoBnUdW1jUHvyoucMvAz0hBm7AVX9q/H8lf/yzOkG0x2GFpfjFiyiVNNg/3YpUsmDp8E9ssm
2kufGQCi+8ihgyRt9By44sbpFEBhiOOQkbbVbHEGe+Ub+dmoTfRqfUxeUX8b6pBuCxEXAWyFFNSk
k1cEadHNhU5hSUh4vZ+QbQIKZRUmIpno9soDvUchDvSCP5wa0DC0pPXCuvRd2hutAURxDpjWGzRq
7zRavNjmIUOyBLKevU0AsiUk2oum/KDURIzWi4NyZlHBUSri6N+m0AgS4UHhNjtl+Ao9S1SzfGZS
80VRerXx8zaLCt8gUno/D+m70j9h3oKpa4Yezweee9rtfPbKD1ExuC/N420viSJSE91vpxs73EIv
8iYW14brgPJWVMtEWS+D8IZInFtnTOWeyPm9bhO3O1LKSFPaIw1qqgYsaZ0girKIETE4w3ia/THa
EFUgDDOUzsfPC8o6hdkc+g61TSJzrPj2ZeMqA/itEfShb4UyvreSyEVM3VichyuNcWvf/YIFnk/m
VBuFvSLe5+ydel5Ix4MeeiMEfrC3/h2By5D11krYuIi+Pm4XAemwpMMvrLsD4+W40hnoPh2GHEJw
gdfwEnJCZcsuTKPatwesrx+8uG/N2lWjo9zmBsJPVb3cIlma/xyZuFw0fgmQqmDqyxETwp40bzVa
KpaDnqubOQDa5FrRctWC2XFBJqR/bsf+mX++tXSkEeeTnrUFaSITdFyuN0feT57aVErro+R3h/1B
KGi8HPL1F9zLq7Qe1qI1cMYl/isZhbVBC6un78w0+1bN/SmksBtYX3AaR4Q8mQpYexRsiq7fy9eH
uCOGsgb1UjZXpTFSI2PdHFUFCgsXXZa1Fp/IqsIG8WrmZPJsdjLVg7G1YCDuTisXEIQU8hW97Vp5
opfbexrA0tcMwXU7n3cHsptbxuuzXTml5wZ0Bv3BZBEbM7bdomq5ojR5Uv3JQESqmwBs4K5sgt1F
MQzcU/1SbJsoh6h7OVo1kTJxyGVTc0yDxL4xlLhEBxCwWobBpXn9QF3x39H9+6BLLu+zfZ4s41a8
7RCRNZqNSi9InP0JGNGZ51F3xjw6KwC+25CVUtRkcRW2XiMXrzhzQt4F6nM4WMBL2AYH0mnxxhFd
QgVbC7AvUcwqOW84FtD8nUbdra0Ku1l96fD3CiLgUBsB0G4/YFjFWZloVEs64DdxW4LQZBtWPKiq
zCzTlG/XoYsfGd0VKUozQg9JCQejflbZostZlYWQaBmZV1/q1OjYMl68GBQuWXdKf5zTFbeHvzaS
m5wj8uRD2VYlRLp6fw4uFSmX4ZZYMy1ufk61sXQRu7x9lg+7uGFZ8EgtI8QMIlCuRhxL7V/HsiVh
GcQX4YfbU28UOGJxcoAoPrTiQrac26UMoeGnpxv/czo9tW3PGw3q53yAp8rMB9I87EfSY3eMvbw5
HX75Q8AB59ys6l3rmCXI35KrED/dvQHFhX5GjTkTx7XnzZUb0k3LH0N9u2+nCIjBWCpV2ckIsgI3
HuVJ+IhtHtXFSwXacsova/gQXedAwEMT1mj0HAFcjViCA9touaJWIb7/7KQjtqS+G6czT3up4Hfw
EfiToKEeYTVf4Nd9JApuIeaubL5Ur4FyRwJQBE0idHR90wUQTMh8IeUBM7itAO8qEIJArUxbW41f
WRRaBba9svtZsYtejHSBJjuI82HzfqBjn17GK3ngXQ4eDydENcaxOEpdutE20MNLXVfJt6mO/GoF
qdLj6hUdCK9Qpuk/bQu2xOfj6HWMUF88lmGzBZrDVZT4L1UJlqfAFwJO3jthbD6zbRLU4J3VRU6n
v9UtyHJ7ADNRl88P97KogyxjIJ3XxhhfRTzSqEYUCifeafb5L7kkj+DDdL1jC197D3pl6VPGzkmT
7/PGUjLIWf4kqg2Pk/542xv+TWySCG1/knz6zvzfrpg0HS3OKLn54C4AS/nlaZGFOhZZ9jEeMprx
XuVHofmLNBJzMM3oSNcUYzRCSd6Vnnuszn4UH301NLtd3SON1hyO5DgIhS54t9hvjG9zugItJVKK
qW+7XWEDXdZxFYPlyGhUOnXDk8Y1ZMFpEk8LRY71th4NCWo/INxm36XtzE1QR+YGrsEJY2e14LRH
9AQJjxX6zpKDyp61LuODSLzNIOE5R4Ob9XedmaPbCgpFB/dLwbnBZbLQi5lz/e1in/c7QcVf8eQf
4PHnc7yFCL9QbE2CJAZ7otZvpV3WtpJm6kRkn8502Gjki5yIBF21iUywg7uB4FgwwH1bZMynoW2C
xXuo+ZXPRZboRcRUMwckDn0scEQ3YUOqjOSBYefgdSk5MJsmoQ466dq0QBpyd/yMql7H7iS+bY3w
hQVx/dqcQmtkIzsINyZuYnTptU5WgzDgwfBkT4dfuL/akY71SkclEmU7YMRZJG9qtWPwmb9+Xz5P
BTwMVYmfq+uCjAQc9q7+LFe2g9hqcX/DKmZsLoAqW1La+YHLpPdIfDo5zzwfHgcxmrFNR6zufKCW
REH5ua8H056K6vUXSy/aEtZh30IFUgh+S6zabNXpv04krvu7L7f9eqkzV4lTE+DlWsnBLHIY8PeM
rK4hTsJnhe6J8PYBYeP/BkX1RIL7HYUnnZuO73H8tk4iJ7jq57XmbfrZHCdFrONYTK8w+Vo3wK4d
2cdAcPhxD2vXJNZ0ZSFgNqQz+D0dvJ0Owv/XwvpSKczr+Z9kNQO29GxqWkRTc5WfwIxTR5fzSsd7
VCUT6svadoRr2JV4fE/CEKicly8/VauPsKTTN7FCTwe9f66B/uAHTRS5cOHmXQlYqmdZKYyArueG
reHXe+zUSgAo9b5juWOuGUbUDzVD9f6RfVl0/rm74R+ggi2+6UlPJPeal+RQS+iwk/nhSm76h+M6
HOErh/cy0HZCe2dhDmeEh5Bs6AMkJG8PDAMdfug2lEzEgqhbtexbT7IlwJixYwwCRHHOVFRT26v3
I82GiUgxdvFQz34RzXCLoH64EPyzHA7X6FI0JbG4lXH0Ens2pxQPnzmNnkDaJ5/Mp9oP54giLs1V
b1Pgxm4JywdFG1MyeEwmFpppM5Olkv2jrr7mHTtDgBS30b7XNPVtCuoD2gTJD/QrE1wum/Pi4PC5
HJJ7CFwwELRrFILiaHE8587qI4S0Iqb5rrhyb7KUtY2QcFn1+/RsV7998Dm57Re7JSKCX6IeLEBF
uZkaxL16N2H5S91Z32xAOJJE8GWN5kR2Y19z6MhPJKuwB05ielt4FfgP3kFBvXQZ4PMx6xGHocXa
xyuJ7yrqmMOTw+HEP6NI01ygerGP8zx4n9x1GxFFENqTenU+gYULUt6iE8ZAJ0vNY0cJTmhNBeSc
HfbTqsjDJn3MU8qK7pydtULyEI5sWZAlwMhIGn7wX15I/UQ0nIV6hhsyXWMBujdy4l05OGixLLja
QJMsrqf0OfU33PhRkgBuzH/sHZd2r4GTRFWKw1/q7jJn+xbE/LaJIER+BSirSyOy1y8Jh5TZLlXH
cunJkEyWHUrDu8IDiSm7eOBfqGI+MBOfAE9h87qljp6IpR4RmPhd7BcNRUjxr1tbreruS6+q/oq5
JXcSI+xdO/h1W6JqyDPmm9FoWSoD0V4u39+0b6shAEUcGEUiOzC40Z4nqJZNZMTOoV0UNWojIuin
yGaiiuVUGTelIs5rxAwkW9FIDA7WoIeK0OsnW+U/ef0nxgzDMsgyYY3ZjY3DehOQf0lfX0q83mT9
DHHbaedN3aHl1swLfwlzX4qMnkk5NsgA0bCv9iLW6FJl/RpSRDLbOx9NFzV0ZsbhEAUXqpq2WXrG
bqXAMWJmobRsNTmH6mueiGtgitK/i0delpJl6qL6CpYArh6B+YEMmJF+9zVNmbuAZY5ZRkdUrbEG
zZ0DvtcBxh+iLtEZY8NelRv/nBZKwLOiKVe84O+NYi+6y3aPNBTR3be0gHJzrKqyTO5D0EBrUx18
BhViEVphjHdHFpEZjOB8qsXbbX0VvMoqpNlsGG1fWJ52k7kihKC0b5C+8rFMMu5JBNhPR56i03Jh
udLVa7oN3P/PaNgjFu9fqg3vqwXsEfQznuVis9Zfcuyl8i+WuNcuIWqSr2ust452enFJAI4a//Qm
DQ9gK3Iugd7LrMjBz2QoBNq6BmK+0Mvga+7ROBZqFFgmDehQpS3mWV0L+CB8l8DDJixo8I2Mv0+D
EongDN36PeNguKUkcBG6rtA4pSKxNUWaysNAF6ArDODuVXvEndOEAneqe48aCl9Fr1gmG+3yB9RS
gtGcJzwQWrOkzkq2GVBiopfcYWoZ7OGPxsY9rq/ulQieHGg4F6rzw8XmelFkeOC+LRoiuBUOfCty
K6tNMFrkznES2o4GeaArpVkKBF0CGL/6/0DV9i3a5QDzC3AcWcTBlwIfGkDz1wTBUQTxljWnbM48
5s5VowNSCb5moL1ZCJqt65z719xYhVjs1JuoiSBKD3NKHUEPbE8HPh9HMRt4I2ipPD1t+fZvBVp5
3EAzZR1diBnGP9tGR4AsDU01YbYtEjL2jwqRgYWffcTOx34ypcI1BphXkOu/wdEbKAh0a05GSoUc
RnDZ3C+RakIWoOUSYey/yMvSr/rI85dWUL79DBByc5Bf+IZuVifLnW1npbmM+/vAomM7c594buhz
7JYsg+DVhTTzeHH4uQYyNTmszhvOjwYLjXNuAP064Xmf0MgKUf/I8MnsbqZ1Z3KzEEt43hAWhDTu
r477baHQm/yNLmCz5eNz00UqdNHEEjscOsOUEdMptf4IJrzPrSrujmk1XZgRnS660RxRHp9RnNlU
BdhvRNSPSy9+/vSifl6nJ92tWoZD09ZQHSMgI3gavvk3vTfCalIunQ7WouR1H1pCDAVZnatP5pJ6
C7w4jAZYWTqOqB474zZFW4NSmZvyul9jP3q39XM1JE3UpD/wIZXkMMQ1NSet65UPZllZ9N9yl5dU
3jKgtPbWLGynpeCuwzC4OIpB92LUhteo3oA4OxzT6wSY0psaCdRWKt/flaPorFZx8VRDEahHbWXt
Pvk6mx2T+4PvS775Ag8AZ6a/WA7qqY/R0NRQh/h2JBef424lhxV/kqpOB2wL0YbLviU4FDUUbS04
lJGqD3ikALSbX+8v041qNDM8U/Wt/zGOULKxWj7hXVQFZqNmk0WAkeR27j27ejj/xg8YlXT4dA7M
vkOHLMMpo9CzyBi5anlNQ92OoE9G4qHplO8lSGbUHdQSVYPVFzMmQ+DoiOBKh1Ow7/3cYwHQbwLM
/DpALC2cR/o8uymr7x5EKtHDo0qHqgnAeJq+EcqVPObiwqynMJo3/XrcC0HlEbOcb4AY47ykkpl/
qAX03SouYgdWcCzE51ehYow2PF5beV8WAkFgkLJkqQ0yeDXJMWL7a2AshPVKxY2/Vjhu3LFEDosH
CfQtQODgepBuwbXjxPjqk5EHuGD8skSh1dAQerGw/RBiXaRwvoxz9LTzyv9/gHY7FqjXRAeP2sod
izybnYyIAExlESjMY9IfOHnHjVVDsXeO50Eivle1WxFBp1FuKXYRXuA6nqVJcAcgbCpELrl+w1BD
ASuwRYcbDsOg05LClAOeDGBthcINtueH5U96cY74VNl3uBJj6h9YbDvd4cF0IsXsEU5+SXz0yCUN
2ydYQLjJoOQtvGjdA51UUI+d4TVyDbshz8ySS1O7ZyMAQzjAaCOu/57YEz7BWNUFz6fLiSJIuquv
zHaOrHuj0IlxAF9zX+IopeJZKnZubVBO2anK46fvGcnHM2MwrtkBHdq8Ut9y7ooTD8eTShkdiwUS
4W1pEyu0BOzwaSj+thUiQT9194FrDsgsnPDUN4W0XF2l7sNygp3K7/VgwItJM/FT/n3kZ4nRBCbE
oENy1JEcx/LQ2VwXfmYzPkW5ic1cvWW+17yhs2b1xYWsnDocZcgB0dbJlem3wqrQMU/hozGFo2HO
dGV8KyQNmVngAq+bhP+jSCNS6KP4PI+NDS5oAm116QJ9VoCintZwEi/DirTnK9MeV0OnEVy9zilk
FU++2zIwlLxZKGVmeJ1xquOzebG/3oUY+NO9zvWzYEojakDX55M/yMh4KfpjJ167s75Xw04CycQc
f3VsA5uNmfbKE+B3szqb9K3QPNe1a9V/sB7+giEJFb6q/40a4mGMvfY1XI7HLD8fMELvL5V5M33f
hjTk+/4Kb25/7N8U4Sv7hGZmFR4RJd7B+lAiDW7UBPMa8DV7tleI+J37dVnT79vGB6XJkB+nCLR4
B4nkzLUqIKe2upzQ23AjULD/qS5ycDwa/qifHWJzsJTbzHFZbR49TeMJ0zWmNxBy9puVlzLhAKi+
Ypal8c0aWhgdF9AmwMSJqlRcc5h7IUCQvp7nQOiaolt4Ad6ZLXhE9zLeyk7JV6Qz9Q2TxUTEATnH
bg7mAbxhRkK6TIo4Tx4gU/BGLwERFQU8DRTp2gxcynYQhkjXbPfdYggUQ2V24HVFWNvRA74BaDSH
CEAg5XhsQvr0GVBcbDIVxXm0+/PZjHE5l40EjHe5ixqHHk86kBieZj8s1NIb0WISDV1wChfN5QeF
o33eGDcqGoBRnbBU0NGoircHAFKuEucwg9ILPic9i8Q0pHYoJ7m91VU6vZYxB8DoImJtoEYfcKBs
NJAPEPOiBEzXgPsHx7i1OsJMGikFdC6afSkW6Crtpv8ozXtOCpx4FLSNy1w1AxmPOeaE1tJbJRIQ
mvA/QId2QKLPCxMJKtJxwAmTzzTtay8NWKDzaj6vX5s/oplVIQ5nP5LCsZuOYirHMm+dBwBBJWjl
o6nvazW8INDdOpn0JkcqH3Yy5dAencIXQ3m58oJN/8rTOUWZdhKpZSKgA79kpNGjz8j+MKfem3xA
eXOnF369pNU19owdya+R6eSJp07L3uYuC9TZAVHpHT4WwgtY2S38u68Nf5OFhph4Qqc+nIG6GPxr
Mz8nnV1Jf98v95E1Xs7OUybysG8MBpFfNjsC+1jnIGhEY7b+/8rqwIwlPGKmLPagGeo6Iwj3/4Ct
5xRlWWevaezaZjS6oTCJvrJNjtsWh+E235NX98Kh6aZjx3V8zjU4BWj9jj8AVRV5VG8Lldgiyort
tyTNTevx83Nom72gV5ngZ0xbTdOBwwkwj8UygVECEwkMKbL9I5KhNhpx77wLzDccFOIf5idJw6DB
QunGcteptLk/S1Qj+y4jna0DLbEfNeRt4AbyDp9jzfpLu2ZkEPqvzZa3cNQquqtr/oNbswG5gzn7
vIJbhd8GOzB5ZsNvYqbHQUQ3DWTqYTU9gG0sihVfHF34lZQV//T7Dd+qHTxqjyhsWG0/d/e+M0tW
X30LQbnCtctuO1JArZj/PyQgGiVDL8d2t5fjSNtdPmLbw7UGzbY20HVZzCNWNMco3wX9vOVFYZi8
2AT7Ws7CRGkigCJAdjaxYNoaKMz4A3VXuEMFtynpjD/ZPPLcOLrPTC/DQJKi+HiEC8sDY9We3M3f
WMsuTRdG9z7aPqd+uSBFqyHk5prmXW7VJbXEBXAZ1QYK8s6AErQVE6QxK8TQL/0kOWS2RbGYVMIy
onpMJWMekeY0AqqXRz4vW4dZqedJhwKHdV5EAC/7+cKIWiV69KfmECdiOwjK4A61/8q6njxOLokr
/NU3ZS5sB0MNQA7aITjPkHqB4190IMLc35UUbt3H8a4HkKyQqXhWpeZlcJr1baWjlSqKUmth1DeR
f2nHZeRSE254fbCKrY8qs05Z2IDlCLe3zbM8aAU/c8g3hrzFWF3hNId6vpBrDErEw5r/fYtupdnb
ToI+7Adso8NOssj/xtPmF4urrblX+NbcPWFuS1uo/ljaohs8pGCjRwbFGvPeB9UHjz7gL8ZXDPiZ
sipswqYyM7wUSp2iL3ko+k4PmjVgAbrWQqtcHV1DX6N0EXlhUBKimNTGgl/BigVAwT90FwlTWsjH
qz4VPsyNe0gMKP4bxTJRC74IG4bLeobLPVuXevfTVZdUnidKn9gqW0Q9LRe3iCmZhL+9p7EpCpAr
AgY8k+IqqzNnCNvYY43nxQ4F2vlOnJraxFr/A0BP8rVQ+dYAvD+aJhsOWi15XXNLNHom0JzN8gXf
wTFZJ51JpDiGb5MgQDJhHaoJdNt19XDP6gN1SJ4teijT4lgMpFP9oPAmJcz+zneOe401YlqsGsNC
s5xL2r0PimA9tu+9STUhVQs/qNdu3CQjzRZsDj64i1zScCTGhaKHdGhDNUEM1ZTQUuPJCts96gEB
IzMgMaiezFPTO1kjJ6n32Qhp/fBYYJ4j1+Cy/9sx2mbFCvXMzOFbyQizEIRxLnExrmf9o4/w0Cak
JH+F1PAc5IS73WmHedQcWRoj6bR6GZGuCTmuK6zT5vf//SlVfFsoYocPFgeYCZEygJLDs/Q5x2yq
vDrOtwrqS6Ug71t4d8s1BKTLtGKY1PFcNM4g4ham8GGaie042y/GMhdTpVccVC2DPNDD1YVXZrcJ
VoDQy1JdjJs1pCqvL1old14Ka82U2Mi2aiK+KZaDjDayhdTv4/miWboHJgX3aB4ey4ZF+VcfCgVW
yz1POV/wWy/FLnYEQnxnTBiHwTx8LcQxWrUaBDyXLjDjT9S2FEE/6/1TkO0YxfJKmnXYoLyOmamK
t8/O/4uuMB7UZfUqQGHytXBMLD8dpVNBiEL0zHmhWZCadVbxCzOLcZGziPcUnxJjea3BGn2U3n8H
8IhpHAwTqrln6GVU7dloTHudoeNpLBRKfuSAvc+W6bRLksvvEfQAR70HYzi5qHHrPIh9EW3SdJ+q
dP4YEZ9DYDumvk7DguBiK+LRxXwN/cIz2TlFqv6VektDU142lhaw1fFnTiqbFn52DJYRCpeLg6nT
oqRj9QbE6kqk/cTtQCwDQprP9bKr7NareMMQBYgnujji3WWxLX9ahY6Y3TMuWgumMYmlJiz4hSlF
xsF7fCP3Ri/kLNh7n2Ri7e1WuebcR5D/xZC6/l+Dlw+LG9rfXbgLFCNPWcnP9vw2eXmeVwaXai9J
uA0kooh5hxr+8MumGEaGdcqPs+TyzpVoWmJjas7VHI2tvkGaTAqATbNzynPbgQkbF9TAYB5151Nx
R3UHeO3lAXk3+RBGm+eHcnZdk45HfxP6jzSpQzZoKt9O+efZZSxJin19/faNqkJWaGDRcvW9xGGs
9PxD25+awStaSavlhSjXEgQRtmin4kraVEXtI5U7L4utBbi1otQH3oPKl7epRD45RbBYbk1QcorW
wkdz8+qcQ3pjyz+fUaA05uyK1yfBhQPuDaaCqhMhpm5Gv0e3WYWD8s4djVG0K2evz55DZFD7meSI
JwgeNCXeHTJ6faf8rwIZG5sXLvBZaB8zzfuijZCafjwR4+lLMqLkvV19tfjPJn0U6VtcZZRifHck
pQm3jL+ruVX28wv0Aiuit+58esVz2c4jQquqU6b7MpODi+ghBKKUMm9mbD+2QsDvn8x7OR4ejKVK
u31wONffaE0X9e30qzNLOROh5i8pIJlMQKgwU4d5j1kxLs9mp5Atjrlt60ruN3DY6XBdQOv80Jq0
9cpiM5Ha8LduIiEHCkJc3MyWPOVGg3vSDjLBZRlkSBIlJcmy7S79SFuLBNh2Tp/Pb4MioPHqOc0U
oSACGNWTP95ZShMF8sfdS9I6zyECoxZ63IHorxAelWYAFMse9nlPqG1FTUZxR62xFlDtGPJ9xeiU
Tm3TiCUv+NECdZ5wcv8AlDvCvPgwSmYb462WM/6Ex1uia8gJi+zBKtpmb3vSyDHE08iIdlXHPHRe
c1h22f9xYbF05mxnExtpDMfQv3wlpX0WTy/pIKhGzpVL7dT1lQOJZAz3Osia6wJzhma0vdsosZ7P
R2r6hjbaGFLeoEg1h0gtBsjP5I9pAiBlrRYzkq28K65WyDI5Nutu+qojN68GKY02XaRv7W8Nswbi
BBLfd905q5ucG0eCPqS7qMdDpQsMTrfMP7v6yLfGv958Gp4b6ZGqRrr/Puwvvso1/X8F6/poJ9z5
8Vhop4fnH3b16xKt59nT8Y9Gf7OWStRPDrNOf+0sRhADL0uvjC+Xkzdcg6fH59abvpMEJb4AHVrl
vQfKs5wOUb6FmoB5jpWc/fWUzjT3xWzih8tahWSwWpTn2Himl+bWwzIqq0ein74+OJ8xr4VJct/Y
CuSiCULj4L2Mehh0a7qo3VzoWgmFY+sH9OdLwEiX3KY26k6/2yybLMSa/8LfZm+Duwvn4tfkM/6P
QETRj1Il6CcPuYWOt92KrJrEc1n+ESED7BVgH2PHhQAZsR1df+5nPXV+Wu+9QAbGVUsNKl7YQT+m
UiKgVWNmIp7YmwSJukDKFGRAfUbgti0h7Wz1WQQJgxpTofRVYa7tw8REDuUFJLLIOEOF4unszaA3
utJoRSBlDI9BuzAaO1PxqhtNA9fYd+wDztWcMfDyJ29k8rldmCJFzZE/JUcR7Z4CNa421V/nVdT+
ZHGZKNRjJjZ9MvpZFXmb5SNjPrbuUwov+IMeJZutwS9gcmuKZkD4lXjOWRZQom0JygPr/q8OcFXe
hvf4vee7UpO1rCwVOmuYo1RnkFrTbCCZmoK2m4DlFb7YJ16GnGpiGFj12G8bk3QZU3jVfwQE/ApF
V9C+o3oRsyUtjcLqpETh0DqLBHl9BEw1Jm7HaaZ36eUwVjfnUq6bdFxmB9hF0g/BXLSECq2k6qHA
WnrsQdVLavYVWbKpx4o6GmtXR1DX9PBrxPBfO09FCJV4MMNOak6OVyejRiU7wbGhZomN5soMNUhK
alLayDWzM8KiwYMq6Yt5f6Fqw5pT5ydpb/uvH4qRtnV7M9Pnyjancwmr7Jp2pXzP5w9rmyHSvGj4
lOlWpwCfpvr1to9fifkcuvd5bhz35+DN7U3G9tyE+hqNxoOIS4Yf0rVcA7HGIClfHXXq0Fg8Q0Il
04amnowuN1XltjVvhWZ25SJVLvBexlhaAjBAg9ijh6pA29LhAzavuN+IFymcP3SX7eEUyVU90KpK
+Mq6WkAk9iXWidS/PXP/Y7AXFKfuChT6hYiyt7knqIXVwoeJRVWlIX416mGCq78bc9rShiPnFm0P
6hAeCiY4shOmvn8Fjnf8cNrgxp2WY0dWbdBEBKQU/pW4WzIPsGCEN689AtXxyDq0mUi6jy0pJFwE
ynXHrX6QygQvyZX5o7Tk6mHzJbn4a+T/EkIF9RqItYhCwuRqxBGs/LFE8mM0ERaKkuFPYbdbr9bi
eBFFdPFtq3XhAx+fsNY2zAidJX8P4QJURbdy8E8Rv1jPKa04BpzwsNfXIkCo9A3awC5ewgOsal7h
jKwtAKphHZ6mfdBmK+Y2hBmkxGUNc42RF6829Jmu/0cb+LIiLZ+Yplo5/r68QPQp97NHZB93QNIU
gS6+35WkKYKhqvkxjTV6VoyRjCEnH4XKQSRMxKKhxIqzksBgVXxJ9tOJOA+1arLErWMmOf+ulV2c
fxzUNZB2LoVqxcPja0z1aoOLCDP0JpuuJXZXgGZ6+bl2pHvLAQik6hPnu7jjGUIPcp30hizynHDm
Kb5hPNl/zjpabtVEzbCE//0mB0zkU62htiZJAb2WyjAFL+uA6t+QeixAe6uyu/C45YYNwhUSbiJd
3dtS2kkF8Dl0GaM3Y3qbZz1qOQ9VJ7eQDHIaejMdxWsZhqbMnedyKQ1nF/V1K3njH2Lg7CTtG+Hz
nnrUpY4CYBDpEQNeqQHYKqHdwC1EFb6Ugj0Dlya1IRFMY2PitxaoE5N0RgwUnisDGiCcyT1hddKu
ArI0GpKqa2Uq8nsWif2SKXDSYAi0BbFxUG7zcNO/ny1VTIoEvJ8pGB4aro4rnJT2HbiKZwjQknfw
n7kdIOOY7QFYqP4E3uj6yE7TwwxGI+jS9IUlv1ISNYWIfPlgKtwnPHnf57evM6x4SMC2c0yfVShV
LeBoQcAVDbqu+JFz4ojq327KzV6bmJlKwylxAdiMkO/fTcyQlOBDFsLG6NxRds+tcRPEx1FxvxUG
A8jGswq7O+qjQmtWH24qsP5ogMjFOR+QPoxtpuHwB4EC3EBqTURV/LgJEbPNuWQyNpwVuaaFxPGI
HZhdw4V83YXI5C9x5WGGk0S/pqo+QnPXmwVWfivrG4wu4UuTlLEVhPW8Wv4gUERy6GdLpEbcf6mp
t3uA8b34uCudkj9aY12jeAIpm0RUDu7eO9Fvm59i3XpfQGAwd0feE+T4HiOOX42GeIf8qoq+h4ZR
1Q5KawHV9dSLhOkEDJYMaW6o26/FwMMKFGlIHmQxl7vZQGvmfbHf3PARTEzi/5kIhtImdoKvBCr9
mDvhAM6i1sNB/ElHshsgo8zyxfDEAjH9bUvOb+TKPUHFiwJocqF8mB4g9LMwrh2ajYTL1K5Euh1b
wrgOgLmnxqatuciHjb57D0JjD0LhVzVkDhuhKfSHu1HrEgTq8Bnzbdpf16GPFZeZMIj1q+TfK8EE
jhU4W1ZFju/3QaMfThc9gNV0KmJoNJ6nIylkdPXRK6DhspNggJTeyL5qjvsImcCU0kI23WrTSA4r
ptwnOtkS/+6f5Q0Iwr2FiKb/A+0E85Su8bm1rC5QdUKfMIYoTP5Lo5p902qrw7xwt7uM5Vg/MvAd
N62nGkC04wXcD4lJ6B8exnlc/5TKxYhXBXpAqBwzd7L0Uq2FqrgSrE2tjPbQL571PB2HcLtoGd7Y
neiwmHHafJh1mdjoV0+TEln3oUsMC0Uj00I+ungudGN1sJ7TVqD2dKqqDbVmCpGNGMzjj4VyR9vv
d3xr1fnUElICc3AFiqOHghOwNPDgFMlf0aMiNZl/juvvnHbFNZq8Q9XjtGs6h2tujBBEqnbvLmkN
A9tZ6aRGgTeG92V36W91MayaW9VuVC8vtKe36FZ6x+VdJ9z5XeZq2ltPOvDr6t+WBcg7Y8Vtf76I
uodyHbKpO0+oK1iXqdzvZmNFz1YQu1CWFZIm4l9dGr4C+gu/CED484QTfXKpLdQbKVHp7PKSIByK
JpYaAHzBNPSc+LHuv+wCB3E+vsjxJewGIVHMQLvyiuT4uto3/vYrxrnDk9oiWAy6/dI6Bu0IP+3D
C+YkyyepJgXaI1KLGYSK8DvyBnGxdAQWK0sAHSfOJPgmjneV+bUPE0MLucfput8pBxXwZO8En8Wc
sgxyjllnsNyAe6IdOwwIQKYHBuoaS+dm3YSfuptmtpbzSBudrQ22vIC88vXI2Oz4Ot9q7u1o1W93
AKQmeyG+xpyQ8Wt3c4L0RbCXNDlKfSYbOYznnt+f3fjxCcYvkgT1+hH4LTtAKt+/iaZzeUMW4xan
BJmVEDtkQuv6+kTmt3h2pny2KKZIpCRRBsoM9FTmoosgJnsTj1UMZdq10rXr7oZ7Y/3IVUSyfQWp
jqdU2Gt6+9ilZNdq0DBz9uv/Q0IqUYAvai2hquiqb7KRw0TpBZeU8cz3C+/Gmq7Wlfn8fL0UaLvm
akM3bYJzsIpbLyHe9O9/8788AA47WTG0DWeXdcLIqVmox6OppTPORDJaLFlDiwW9c5JohjzjUZy+
WwXRJwX0mreylHXOuJnvxi6p9sn4Anxc6HhR1EGa8kvw27dv8xcG9duRfz251dmKwzF31tBzPnr8
XbzFWojGsJdof/O9F6gFMDvd6SGyqa1buYjQaZizikVuh5IxnNmYsUks0BRFhQYsbQZJjyvpRae2
FGx4B2gZAdqaClsjOQEIy8Cc7CWUVF0Dj+kOD+nq3lL3TZJMyAk2Q7NecVa0QLhj6Y2T4IRBIeTR
+D+ajyltJzWt3Pq9dFxb1IuesWBlc8Qno+dIGis+DbE8vRMmXLyJsTLoM5rmfNR6rkuMzho7Twqa
gjxzSB+ylS3/xIIz/VgdqvpmlnzlrKu3HVGqHPlZ0IiiSJb0k3JTJRjMpwVs4TQJZX9RwzJHRo8x
KyLHAmJVDkmvCcI8sXD4DO3XKBva4ha4fyn0oR71fDg2ssBp5jht2B8u8b7jbnba6HcvY0ee9TSn
qmeJ3fWX3t+HRtUfAtQAyrapGy6ceHDPNvQeBXceRkqFfwHAHMoIoM84OHeffnQPeX8tREbtpZid
+92Hf/H3u/iGNEFC4TOCFUcmreIlisDgyX5SBVB6aJQWd6eKN06cSdCdi0maeS8q9U6mx0efernn
hTd8qtcV6W3Y7HWAFSyXpvsw8FMXsClOUhoxPo9CwJiclWtgKU4HQZf9pWRYWFTNF/PII9MgIRbn
LJxLZqfTQkHrsj7g4EfCO2+ZsUeGSXYhjtkIAMIgT/SwCjeCwha1WnKFNAnhYpvcGEMPaOJ5MDOK
rQ/m9C4Et3qHtIkyXQ7Putd3lFYoLcp5xNx7kpbFtEPUqfKj/pwT+dpaohBcQlmvaLLazU9zvnm+
ExlQwbrQuS6QzaoT8Pq9O2IxTEC5AxTza6nU+ujLm/EQbYiDJOzGlfMqtFlfUjahjzaNo84we+kO
mfoUn+cesS/LmYgv31bqoFF4OTi+Ql7uIOWHOLBhe7K32j/uWf8Zg4K8oIgkSdAreOs4229wnkdP
4J7sUDr0+1VgfnsCwTVNM19N2q4hsxUdpUsMT/fAqlvmG2IGiE6+VBEMqWYn8gsp3dWzR0Yp/TL7
4w7oMxTqe5YbXmDpriLGBjoJq8extJ4qV9kFOBxDTrfayIdP+89eUt3rC27IAKIROW5IO8OzuuT6
jnDYGV4+R/NtBofNTMkrkQaOykrcpNTSK2F7xy5aIBPucDDo4xeyZzTBm29H2CbH6r6WquCOCR1I
OxV48ShpdZctE/kMQFeGf69zZhxjLnqWdEQR0Z5V+JLtvzCEpA/QiboToWB7HmCNibuaju0dw170
Ii20F2wvZc87oNh3qvu3aI5RJYiY6UAZTwQnXLJdHaalT6Hw60sOs5P6CD2cf54cGlxO/i7dkGIp
zs+Xb/WbB44cuNFsFYswJPA3SXhskQtuzvABOL0RMHASeJAigzXcoXL99mvJkltvqp8HJe92W27D
7BhcqhztmgsMWT+Z/tZxaz5WLyZTtombVk/LUH42h+53YTd0s5Z0NWatYNHKrBEWXyb0T56WS4p8
4O/aGUjpxOuA5r7f1wUUNiXf1UmaVgRDF4wOhURUuepEDVHnD7wXVzSm+IWcKuul95yh3XwpQBzQ
ZebRpdzTs6x+Aj2/p4blq3HNKGK45UYwjoN/bDEOWY2R4t4mOp2VvNz449gIvrB7jaSnoIQh+wmd
r/mK4ZdUsM7jEB0eCeVww8rbMDZiHHfZQyBjMMyYcaJmdUXKtg83AB/YZyLlue7ltw391PbKMo3G
AgNyOaRMY5WObABP2KeMxeNkDUcFuDtlMKm19UB0saynwWX+P62zdBwIxdqFhSfGXqhRE2naeYW1
sus+lKiM+lyIMBua36VyLBasMPwOCCfhn8lR6iLMT/UXTa8123y0zfLPUxqwnSJ/gE8DpS/GP9Bb
Uoim9+/Fpj2iTvVdzRm5UyqfwLhqSwpZ4cKOpqSoOjYkuJSqMQ1e/WE4uQkGTVXYWYrH0vU6k4Zf
s9UM92EgUVbNSFdB5UJzSYlNA2NP2Lsg3uwvWuUnzzM+sxVb9fBPSrQ6icRdAURwZRWR9EUKg3nP
/7Zf6uGSQqZHHy1xzTfLiAOq8AnAogAK4SQnHJ1VHq1H8sL+bJSPT59/7+G8vQLJ8w/mnrZMpE4a
uYvmbU1QQvlOb2adXkkGFxu41fNyHdGmz0PCc4YW8scY1mbhtHoHu0r+vi9T8TOSuXV947zfirvp
qmaqZzgeMf5z1AiHnyg7iNNrj3aSXMk4XYBQIjmGq9OPsvTa6DlKkBOIeVYEQvl8uSjGRt69I6sR
Wj8Afr9dAl3XsF3TdTIxh71i+FhKDlQlAuX6iWV3RXKNzaUQ8epDTmiRi7fXYSG/sboGtFpYcdkZ
psa/svwlPgrmBk+sRzua2sGxQoJeQRm4wT9Tr2iTPXPDWSDBW1l8ROMt/uBHJWN9QiwDrhaMhnJP
PvpnsRs319DbNN9IOHJICJNe+ZBzKOZUlJNs4vNXW2KHGLaeWIdjI2/Ot0tDT9ulDW+2Kj1Q7LtD
fC+2kt6y8SiVQ9XMCtyT4PTOfIKjp3NvDiB3junEoWAL9mxlrZIj6dy8Z6EjET2DSJNeCEooW2pn
XsvYNvrtHu7rbvh6oy0H8A9FOOci50OEvgN3z2whrL0pHSEyyQwRDh3kFO5DBFAYnHKZBXYVb5OK
/aeCbQhM6+dJv7KYPyPB9Oje5QUP6Np6YMjASLHRj3qTjhMWWVBzyGlN09ZrOFpWvvDCQpe8v0SN
KpKaxkG/+0y7NQpH3TT0fF8TFdLAKrfjvp+K+qOJ9NJRuBmTEDxb3VSenJyuK5VZ0ZULvBta/i55
6AMO8YHPIu2DWB921gsln1nKQRkC34CQnIwKoUpxe6Xcal0EDvR2di/DsTparTPbx0k3mmixdt9Y
HnY0Vkjixs4P0Tn7mGgjrkKqa7duJu0oFSTQGAdAzL7iyUpPiSoMBCnRfKwNdWHBkMDUYH4Ervmc
b8RAVESk/DMgxo3PFv2PjPqTCtJXMj1IEJZFvAlT8aaetwG69yXh58RJ07rkEjuUgMevQ7AWW2df
CHud7zLnCJvr+VIRET7+4xh/439aQR84IG4oOYKeVAdqu23kGzzUB1l8+UaFDP7LYxBHkF9nbtPV
SWBbF/gAl/3RZdRMq9ofx+DDG1wKd4hRqx4ZO8wV6HHq4txpdjBPTjXsjsN/uz2Ajhbkzzd/A+ji
fQ8Kbdl3rnMEJc0rsG/Aol6PhxqCnT/+gy96QiITtVchB6qnbaSjPP6ugGY8RKvXm+XxqQkYI6wc
eZ7+1b6qjiKxvwtJL6x04Z4PXoIvMFesWI1QUDO0vNEIlaXnTz0pMt8Xh2sB7qzTuwbl/+hl+qG6
YyFm5zFZXNHYTKRtfS2yh3Hr31/8SvmgeIDkKZYAKW9wU7xVOSSF1q+nP2txo1GDEYqtgpATMsEK
PIsLonHob9Pb1xZW1aGraI+1NIHTC1Ho7RP8Ot93B/zrx6GtPZrX7UH8bor8O1KiYzpl/WVLt9XQ
i3ZChS/9E54/arMeEa03oSj0Ye4d7JnWKOkOYSViVYPGzEPa5KoRVRruYBynzI7DSThZp+PsezaD
7LX6w4T4hPDfjbjYt9AU+z6eqSPjUkWMYHhDhh06sBhR3KvKTHa0rIZFx+OMkc/wFU1AuaIT4ypO
Unq1YhnQVs+OYEPngym2ifYWPQzO8jGtD0NFGPJUXxqY3tk4lzvCQKTfuO/QTqtOUSNSGbb3xzP+
iftgfa3C1h6Uthi7kjVHJuX74LbdXDfhsK8HF8ski4N1wlkJu0kfcncujjKhzuyyuu9C0B3MSm2T
Q3AK+x2CntcFJ2akqlPnvq2uuJ81PlqB/3nPZVJXytubGisErn6rM6yW3lrbXAYzbJZCqALIBbH6
aYXPxQZNcSUlpFfhgO/cKCHYziuCKW+9lxUp2vO+5028WbS8qNEXYE9Hqj3HpLWZ3tHaDhIJ3Oqm
QW9NqTjBR/xZOSB5QE8uWIcxu3Mpl27PORt6Mg11Uad+tS9Zljy9s/FPxjKT/nEXMs+ycmC+QlHV
8IYQ3J9uL+KZ6qZjEKf5IwgxtVBbc7cZibrRgVo8x3bNeLlPyT71dVhSpVEPjCIY3EqXycrP2pln
ANFGlAFl8RUExBpG9nyCTA5AsOjHLfaZB5O4rWGHFD8Fl+izoAxXX6/WE01sKKO6yEhz9P4tMGfB
CMQZYZVUgMNMY/uASzwLjc2U9MAA8vI+0XfF7dz7eIJDrsE66QoCY8enOk2fmpCUvLd+FMvWt43/
k99hyruKeLI2G4xQrPBnhfMh3OBGs0mk6qyruS7/jiFvyKjbHw12AmiI0p96RHRsCvkbpA2FLNdD
CiPg7d92p5N+N+VZ74MKVIlNBldWBuzE8bfhcWtd8fJ4r+O40YFpl3B7oQlq9xUe2yJLqpNq4qGT
ChmphQQL6u/fzihsSMZAt21X9jVrtu4L43TvJPd9MqnYoLY7NJvHkh5Ao0x77iRAZadpXoSoAqtR
sqINbFTC0SiwAPHntL9MxinLRWuGrkm9kKJawrYwE3SSlgD+BHVF91yZoxxASVTuGxGi8x9nqmDP
N/eClW6o6oZWbx+P/E7kP6SChTsvA+nLkHQ6fli5EDCv+isCH0GZyqD9c35ILz0xdNYgW2+mjQSs
uZvMaP8jQ68BmH5AyfTOpM2pL9H8CtFCHFITuRpe15Vf2nazgrd37kW0bq15uCOWj2F2lyTkotdj
8SCx9lMuiQWFBJ6tGcYaJwuFfjHwl/u2tlFcyVYM9uqdoyQrZt/9ijsVxZ0Lz0wRlKu9A4IyOnUk
SjWv/eiaiI1DXOrc3cXA3/kgjTZ7+o6NtfFSmaRiVk4VVbauolOiUETORu7+OIaV1aeuVoySyJtc
n2NrA7CPYQAHG2maquYahdjN7h4FsBwSszThMiAFQa3wwXKzpwELMeXIc6wYyk6NrkFtFqWPvRp7
7WxmMPiS0P5Vgnv/5i+HASEckqXHEO+4YaelFUQm4uKyCWQ4eXNxSLR1tg0Srk0/PY+jEpdoaclu
kxLJM6k0qg3r/PG5B/6YQBcbeMLobdMu9bCs4EPUZDYAK1S3k/q5IQOBOTVDp0DV/TepF3oce/kp
Lw/r0c0FNuBhMeAFp7wK/CG/4zJmAEmJ8pjRgxKOVVUX9e1NTuwAxODowtGgzxKkeJvJrYUXxSQU
MpleNpxUx8WibotI98yoZY71zncXLzV9JeQdAYe8RAKDCwMiMPg9Su+eRFY1JXxOWEF9wFt1WVXd
HPt84Q93Cgt1yB14zaTQ0YT4yic8uS/kpHHBq9xAC0iUuMrE3lzPcWy0zZQodEmzt/+/+wVNqXpN
jA7FvSB/Nr5v1pehDqKntU9ABvgn+/68gzjahJhmLpWH8RHQUHKUPtTwLj08DutNcnXpZKZJfhQ+
50+PHMyI9Nf3Anev4xEdK2nmg/ZzX3pS9qUKOvKsl8QJnD9XiAV4a+UtGNvshZAB7IlyidgAxvsx
pDQG3hsHIMUfEFyO4fdRmDNZaTmw1k3WVH7YwOxyGfk9MI8Q78SWhGaV3Z2O2gRIXLoAyJ7q6QRw
CI469IAEWE9dgvcS3PA+1zTik5qQLNl4cC8RcwrqaZTw1GqK72Y5T/iuniBy2X2cEa25HYLoKvmp
SsvBUmjyRuyKUoC5rbWLqKlUqJOT50evZ8LUMY0eb/93G2PyZAszQhdEnW3BUuwdHHkcuguouP+E
96G2Gq+V97vk8vENe5TbpCWGAV4prdOudrxCdzb/zUlOyInRJ8MLig5fURy1VsTIeHAfaNNABTyT
OBAN7tCf3TTBHZ3AZOEbqUtKBddNuYH5AxLIEqVJr/LNLJlBBhdeYKSnuCHOrOIhECQOTrF1OQA8
gwwpXhBlChZCaJ7exT4zcTNwWRahG1qTNZQxWSq0MFWRAa6GmE8LHVPr7AYub6+JZu2pM8ygqQ0d
g/AWk7yD7P8VPtpXPX7mkKofQzXysv8qq4wgwbDlyuqRGLmNfcXmhil+WE+BaMrEHAfvnHAIa8uf
0CtbdqS8IZUgWx49H0w+j6SFtL1RgUc8/HJAXfEHPzueYPDPa/w5Jgud/lsHPnbgkGbIFZT+fMcA
kzJp8vd0jLkNRqocc3OfwuPiBSyDrc3YqxB8CNrgpbIIlkuUyEu82z/TNTfH2bLrX1Sk98GgX49G
0y02tu/MTqDJIV1P6n3gwtFunPXncB6LakfMngHpbirY4Rvx5oIPjEkGnITGW+2BSpwLVgs+/OSB
9OEOB4NoPA5kXmsw2JgPuniDeVyTEKebWCm40O8AWyRF07MosHPM3GMZkCkkguQhOiBIz8ipAKG1
eQdHNO97W7AdG1176j0mIJqwWKOWWMg3hg9tYlky+oeqd66LFoEqwJgjz+7YcGH/uTwClrToVZfU
zKAWkmGAL8EL8ZPlC+6qbbPT8fL6xAPUA+e2Oedpjbt1/+ovsW3Lf9bHoMLaWZfLe7dtkTZL9c/j
EFE9zfNdGhr0r2JzOS+2pIne3FS5YP3fTVyIDyTqq7icwdZNcAg0kpIoCtzudUUkLiIGTUWg1fK6
nQ5K1lCfv0+C6ZPup6jk3gdZ2cmM2aTE9rH9OI2wKRC6TE5Kbv9mivMeipQ/SEmbTXkANlOaUisr
MqACQhdMnMR5d49729p6U4L5yzqat17kem7GeRHm0Ic/Ot8XjU4gykkcqgGyzpQdJjVtG2H3p0SG
+Qd98tzCEXvcr5h5vJCDm68Tc1kITVbEKcQjyyglHoQV5tm7wgAlBmTT6THhbPeV0LGWhhNwVLzO
rZKy3SrW+oowFh6of6tBaDCpKJPqhXYI5Vf3iZYU25LUVEciZqqbQU8yBXfVfOWvgt7LA95/aafu
lzzOnd0LiycEMzPgc59cc3v/NqxE0Pddv+/Ehzke5SIFN0o1WGIMTLmbUubZq7E1+TUwB/am36qv
udEbnxhgfuf1JeKq1c/EK2jGRLJ1lUwlN6UFCSLGz3Lo7vZMiJHo2yY6aiGEygvYi9cuF1frzWcX
H9kRsN2KpMxZn91LfDPjiY4VDjtps0ZOhYj2soWe1eWab3CYwsTQU9x8xt17mHAyxhDUgMXfDQKN
YwKQsaYQ0UNY86/3Ss8hxpr1dBEgIHOo0ff28BPzAa6BGunM0GJT/YzZ+SuChrsKwEh/HUchbY4Y
ZtmntDRAEAkNQPJWQ/HyJi4iQ6kk4/O19w+VzmoDEMuYRYhgTQjdjQUPQatxJL3UkGkaUrRtY1m9
3FwBqvwf5089atrnUf1bNwjmoV/PbWw/w8Giq4u+/VEhP9bJB1+UHGWtdi6YLzX8bX6Tfmm8Vc7c
LPVJB3XLsXsJW32QmCQR6yz5WZr5sOlhKJ+rR0nActbuoFRiEENiiEdX+eBM3GpzEnr1Mv/aCGtm
kN3My3juynov2t4RJc4dJqT4TjBMroE5Yka9oRyXJv08V/iYKTmcjSJ1hJHflgOTjlm7YjiFzzOG
8faJh992gtGK88LnJSwWTEGoBvU1YA+mhgRTHR+r2KabiJciyGjdpFoSnCDBkt6J8xuAlOrao0qb
YdPBHkwe/M8+bM1fGG61NjHZ5+by++ROVnCn3V9XWmstwzH69QHBN1jUQt4Iniuq/lFRAQUXSYxq
d0fAVx3zu7FyuWx8hO/35pZN/Zn5IwJQL0dOp+oDAOVRV5aQAhgYk8nuBl0A9Btb5VT0gEROtYvQ
vohbTm++VMbF+MLShu5F2xYd1DJukjy3Zv0+3Tv2x3Lhi/ZuV3o0bpRoLWqqaOABgNTmA985L+JX
OzgR1homhJip7QIJeDAocRrIFBB6eaYXFhE1dIRI3UZv36crfID41360F/N6nAhIjw1205//p4RR
HUQqGLj9b7G3gnIiRNcAdlix+etysaXHL/L4GXE4i+1ZrVFRA+T+hMBiYSORxi/kRkM/K2mACMyn
Q0pAtlpt4qvNn/vcOdmrcOJGcRzGjKJuAAHg3dEojBI1EPrDtir8l8LdrC0IjuG+fJnKr4uGQxEY
9b4/T9b+k56ZU2qD+XG49mQlcZva32fUHZE0Q9g5WLsaSgFq45RLYwM444QFE9bfpnJDwdcVQjwZ
R2VZv4obqq2P2JlIF8mF56l4B99ABLGJ/axRTbFfYKmu8dQRUhUnmEuh/mPgXl+DfM9fI7hJIKxJ
8+2dDLTXVctKjmV3GsE72hdfT2AuJbfTi/lyjS7+WnE2warxiDB0ALN1kbsO4BiVrzrxYkY4Oa/Q
IgpJsZRiY/LFFHg3O0dIU5am3EdgB93hnfhySbfS/VMHU5Ko98MpbGJ5FtGjcDpCRt+jWTy1oMe2
r9530aVS7aIUAfIIn98cuob1SmGMl7H2gSl2PvD4ZsaU2a/mzGq3fRYoKatT3hLz9ROB6EgJHB9L
3tDU7y2qlv/OcfB2NBBusfFk9U0Vi06BzXc/cp9OpjMbLEJ/V56djXy4przqM6ejEWaezMuXE3mj
9+lnzQKEXbdj4Dfks6gaxng44r8mgCFYFeEtuWJHRfGD8KHNXjhfI/fvK2qzw+nSTIY+GTiiCBnT
r9S2HIyE0xQ0iWxxOXBx/lwZaFusob0mC49Bo/W3M36sYZ5kXAUGY/La2Jrrd710Jn5gqVaML5NP
aE8tEwYMQWeFIRSEsPDmmtS0y+bbQTUsq5BSv+RmvyMFe+sIvst4UuK2hPM79+x0sGBWYz5HOfQL
0Yre71QBeqkP7prIqX3zAzUWQ2VzQSK342NKLdtn8xkkV/JUo2RFIfqtKa4KA3x4WfZtAhjBexF7
wX7f6R06IrztYD/CpgcfIlTQK25a3mPPcd8bS69TgOliOiwY22oxIvMn3mmT6H0Fgl8gxnP26DBk
pik78DxV2uzp+ARQBb3ft28EGdy3OEWiz+wD8bTcacS+Bw/8BRaEEVKlfRCLTaN02A5udXSYPs4p
0ZZa2XUH8mJAiECS2eFvkQ3QICokJDWL89rnXzh3Exn5Jw1mX49JSVGFcjhbLVumL4ffmBvYbxJO
/6VUeXDzfAqA6AjPAsdfwnAFN/d2pr0KDAOlphRsONNAw+Qi5FjOkYPfBGs9sHxXjbgwR2aO2EiH
WdwgVaMNhG12g7pcj5TYXnfIOppqdS+gjtul/zE4Zb+sVkhuvmOrb0YivoSWV0EzRopRj3I3NjCV
RRoftlw9dh4Wlf8XWz6cJnVxdPFjH9kk2T0smcvzM8ay3u9+7tuDKXH3PgSLwCWmjB23NV3GTL+m
9Vu5OKZO5Qu9gQFjZlTYisoTMhiO2jcoBzhJxHYvCQnq4W4uZZrDodDIgPSnUfdtMwX47gv+HMV3
4nF8nv9SroLEOj5X8dxRqk6TomNDwvYKlEGR4n0dvBkwEinuGPCBGAVKwfyFE/LTUTjREHSVHD+r
zObW1fVPCBvpBFNHU02S5ZRexOBfaK9WYgP1+fjJZ77axACxklId0H/D0lS61kenQwEWrABtrUkg
rZzzDcTclonNCNW6bBv5XlEhVzEo45BNPWFcxjCWW4Y9TE2B5rm6oiGMatyw8tTup6AkAm/0bRkn
zL9HNmMAI0T+dIajYPE8NNhEvVUzi1qbMSPGXWukMMZHwIHOeG0gva9kPUBCf6f7yYnvBGsFvODO
lWVyLPHiAmmXRgSekHaq8I+XqgJ275/LEzG+i1tknodUWKBmOoFTqgHSt1MPprKtv0gIOrniQXRS
IubWhQSzBfJnrQ4flRvyYLn4FwObG+/b/ZYlwa6xO3xAJ9/6OxAMnH3bSLPKmRvWnQ9VIs5FA3uR
dKEQVq9Kn1J5KIPIQk46HGhDl8FqPaMGEWpjAMjWqB8nL1JeobphxZFtjuCUme4ydHBP43wEN1GZ
GqjX4J+T/i2EVSc+Y0DrFdfIDFtHJ5PGWVEypztNAvIv+gZurH1fgzAJ/ii0FBhUe9NN5DX+iJ07
9UUToegsZo7WGGVIMV4RJ9JUtp9RwwMX+ljsjsfaK8up6EycQpyhvV4ZKKz30bzAGLDfDOR2KblG
N+cWSxSz69S2y+EbrBVi78SimMtngYH7TqzQUdMZOB0z4vXmYOAxcaVlD4t5itpi0J8M4JwwYCeX
YTu1t2IGJxIJpl0zqQKNkAkNFY2kf3zmPQAGa77hMv24rcxyyE3Slp/f9m4t5XlrkR4DcShc73qI
nb2mpem+fYDpDkajGT5EX3qNoJ97B+uCNL8c2at8deqV/eAQSKvJshnDJEpJx5NN9n5mIEGE6DxS
3vZUBBC0DpAOFK1qa+xrdjnZWMgCGPPJqfFBVGch3oN+cnM5Dtt0T6tfC5kDufxUBg+UAYOcL83A
t5i4Qv7xnFkIOTDj/wvXz7Xfylzas3/pgjhVwfqTK6FzK+97+RzxLI/Xa+ExMD58o74VXHRuVEgl
SE4wmk2/COle6RWl37bOX95ZwVmn+yUc4wGRhhQriEuEnFxs9UZ17GdvEtjMNE7fKNkGCJd7NiCg
2+FAzJOzw2QbJ46WTn30vGxXZRlxToMeWRo7Ssk54z6hn/Vmit4D9/dDjCOES0uvAc0vuBI4IvYN
Qc34Dlhc3ernSrGPiH8d9Fn1nTflKhRYZbFDT2MFgbGynU+tGDpjr/y0tJuj8hlGRTfc/srh803P
oWbIVN1+z7C7fFKoJdD9/R4GIyqtHCo1PgNXMJI8JFAyVq+W0h872EjgdOYb1I9rL2TzLs8b2jsd
06YJIGEYaerjQ0re5mmJhX1anXMhtJuOxGqtm/maxNkLyCEXXhpl206h7ezyHu5/DuZpDXcVa8Yc
px5GzXhBZCxUulmQhjp0ZDPNk9wGcbxra9ZK27e+Pc6kWZbMUiTgZw0e7ATL8GA8aO8vXUif4Urs
S2Js9QIXoNso5aqXtNjasMIm93ko0VbfB0BgaNby1XmMHU55blSrDUgMsLxOmFawlKCj0h1BP+xo
UIP4GTajxcmqnnk9L66N0P35tOxNrEYWyDdKvtSjko7h6tCSRZccIEslwPR85dgPh4Z5XOjiSML8
Ph2CeiTyEgjXYJaIgyQmDUVjlfvzIjTK1/F574pnnTyFII6DEaIl8WZMEqS3KlXczMVFwrM70AiZ
ZQtCfDIsFk62hhobRBCFx60BqM87yo34gnzk1LDqs1Ioe0ogF2ZzGS2V96cyClVq76bGycI44Drm
3Jp8z3zhSh/GnJzjVpMgwy02x/OwkhmR11DY+9Pgx1W1SoMK5rtrkQAZfkVrR/eGTte+e/C89MKG
mO3D0jADQj3bGNl6VCWD28grqsPnJrYGaV1N9NCRGkBq8npUaKdTPaklrLBXap4g8mGmJ7w3iBmS
F2HXMAAsOIIT+dA07TsLBFsOaUJkI5+liXYcgy13KSn5R/twjvys2EOSOtnT8rIMglegdGNDnRom
iyXn6EtaZQR1kfmvp3hrDqOMCyKVI9Z8qVuKPavIkkU8friAhMD+RxFobvJSqJFK7I12LOnLsfY4
aBGJQ8Kdc0YsyPKFVOpNDxfa/4Q16EjXdPZQe5Or607nK8bxokU6FDehWdYH3JVc7lpXOJIN5e7M
TSIMhCcN0R7hQeEY1Q1ecH8uaSyH9x5cWW1SoawFW4uAEJGhmf+FSvK1CDYUsaMN6aYJsT821u1Z
0EK+TMLg3tAyKVKSKbKtvhLKsNd+CSLjH9wXFO2hAg2mPrt51mBI5RoZugfSFxGPEAT35OpSnCsY
6yYVFtmpWZPYEPHNpANyknKJMQXXtg/SUrEBwscaQLeaoH9vlCfviwNjESpKRqL8G811U73XTuNW
F6rv4vIHfYcTUl1QwomFQX9uNrf7Ye9AYdZNf6Urnmb31dnr0Fnyp0xDD7pII1Bss+cAhFaDnRtj
350dq31RiZlgQsPREzqaOT7572AwKBtAdJKxLdVMU5FVvKGzegCzvCD5wJTMowcsh8nY5WcwDvFR
1AiM6mfUNcUSshW41s8fVzwpig+Yq52JKzfWf9h4BHg3IpOxPAmKMR3K4ZSlkHffWdIlr8yEx8iP
rlYiVTVhFSj2HstM6dd12kaUt0D4wDGXFhgVisCuiIS+lcCn0C/Q4dtMewJC9agnNEWDRXnHq30j
yxxv5cY5LLX1mWj24z7RjqIezE/evplvSum6idB//5EHEQewrYTcxZAe+sLPpMNxQLEAPZJ/u0PB
Ix1hyI9lk9zJaYA+E7AGECRgMLTKJza5sX4cqNZGUf2oL5pRP4XEjsGa2JFjX3wT8ElZ1kFbYU/z
qiO/3DfdoV5l2FMEJYbRoDoA1Or2644XJShz4+fpp9EWhld643aTEKqviNYnQN6I3FBTuXF6BU2R
4MWEZJtd1sGTuV/F5wxRGwhRfaiN1wXfB6ZZYJ8M1T2/kfM5WF2JPJeJ2defJoy2e4uWU44HYNAH
7R5j7IfDrcjHresWmzil6r9tSGnXPC7UL3Tgu001/aLg9jKnkDWfWw30+F+4rPkOUnpc4r3HH7M5
64goxrejcVidpwq2UUUtnYUnqfwDFHBMxU0YrmhZaYKhvLVwlE7ygb3QjbdvTcuf58EoMhVlx0Qw
FG91CZ2h41wkDXolse4uBAwlOIUQwCrWfw8wHqn3EP/rM40v+zLKis8eA4uzPb3ke902B/R1yNwk
KhbRJH33reBrG185QnVS+lv2VkHJv7sU9i2TfNdk8UOi6FKSXFjgWm/YHWezG8R/QWgup2ktxF1q
hdmBggvbR+FGu6xTiY4YJmLCCPY5pk3v88WvRDfU26ckR2DSe4/z8ge8P80LVpZt4fpZkzzYoEtr
yrpxgS0Mj4zhMLb/dPLiHslXWLMpujzWEELxqypPlvcyRc0dfmjVaAH1l9gSst45nSgTTXyQdXr1
K6Wr3j+zU79TRsonEvO9qHUL7LcpXNpJ3iB+wiLIzDYsfZSf31MjpQn9kVoeNEtY4Z9j9dR0bmY9
wX1Ot19arRH7nwjFN4QmfENApT6Bg+R2/4NjHOSsBvsn8KRdlxSymwgTo2XqXFNfZFzGGCBf6N8v
X3lA7ZuVL4NrOxBliAmBoxMZ62GpRaqsx8CmkJtpZamj8jWHO62iypgNe1wG4SgWDkRzOi0uH26h
AwPFU7DvHr8t49fMRxG+JC167S7wcmhw2TUCYpMn7fQ0qOiA+MQq+81cMMdgauiSUDY3QI4JLm4N
p7mztDI9xHr7GB3yMDRhSkLLyyTRWhMZUa6AiU6NjB+Vbp9PGmby9E53HFdacyTpn8pyoCaRHG8Y
9jT7MGrHCNA9/Po4rzw4eNtDEBNjHohkZD3wAjV6f/dcRQ+zau231KLa5KpPNHadSY1BYmm4q/3s
piL8pbuqv6aP4ipIGgImRP+xYpFlP6+t06XT2EICioiVZvX5y0JURNtktVKg5noqq23B2mdzpRiS
pumjOPahaSsnnQSRFGMF4Cj+1l/rALJQHOmpFHDqqc2XbJdYOUjb4e2lsmaIvhugqYbH1bTsgrNi
aX6sUUhukUa8+56oltEgi+i+d52N/Wg6ZpzmXXWUZPeqODgdojrJgw17dEBHSDppTnE83IZDDULT
AOjKFlE/XgHI18c46DZ+Fs6vIurTBwSwynG30vDCvSJpOV6WbdZH0BT53eMHHighoSlsGqyTWBnF
fN7ASS1s2P17spknPYFFF7wdtohwzWNTjrv/xdj2VYr+jEeq3cFfrzSBoJWsdzGUWwXxaTg5BdFU
O0/XkcpN0ZQmK9H/SWPfe5jCcQpb0Q6IR2HekZkmHiy4Lul0ieQRYvQ8zNezEWvEkuhWprFucZKq
Q4x0uU7753WPGHKXboB7v1K8KNmkK4UByORF8pbwuHJ2lQF+hnDdKld1peVT01sNVbvjY7srSrmM
64vI6P5jzvY+yB4DMJb5p40QkJeckOm6aOgKgxUH5BkjY7ZSEkhLJDqqSOXBhm+ldEthn8FlJiVG
AU87GxbpHRvUSSBG/4jU9O8xxNO9kIwHHtL2BLR5bSookxa/EmSTZoFQMPc/0h4V/ecDphnGtgD3
kwtcDe4HUB+s3+9rzSxS/alajmpA74LiAmJuIyXwMWkrStsjsoXcFftmUFu9FWYeEFh4kffXJmo3
I9GmR8Ihk8YuxDScpBHq27K/m23jsFKeYlIoROroFwKy5mb59XzTvgntetQhfBRy+jl2QlqiWWnH
6cKy8CxagTZabNEHHPEXOPZFdVtCua0x0RTwazvuAjnaSSeT3s+kViyff+hePv1AMOAHGlH+MH+M
KcF+C1zs/LAEBTNX7ljX4q/gyb5nauTFs0zRkR041D95JjCyTONiPyV7BOtcdtzxcHQvQUBYWSVc
bLv0d0JI2farSccoFGZluo2vhr/Crqzm6X/s7+wX23IXxZ+ysP1fkfvomJhyg3yfGnZcXHCT7Xvj
HdvR4PdmMw4nIPfAkbn2wmGOX1/nP9qQ4mSStB3+fzpjv9eKL5N/xa833zY9682qsQGyA9GRRicp
Va4grkY1xgT0ROYw0odwX9jNw5PZEBj6SgxvyYWqh/XOUX60OhzwJoU0g5fBctunqs2yCSJaTqq2
w6qhLX4O0cjuIyFxYRHbnTd6CSm3eEzZ/jxt2SsELPSfgtjpIoJtyq+ElGDhwx2c6ue8PC/t+ehz
IBSdCI4mKS06lPANzisYA4AAUPnsPTQ+LFJ/mAHsicxxD1mZ/Awchw8h3tKm15TB1fC6sDYuHzde
pxXjRkjExpMLo/xBzBfKSPAd5jZ+M4I5dhD93N1QljZui0AJ+Gp/QrI+sFFnMXTEfiOUwDc9dqO+
x34VJ469YVq4A2qR2lijxPEzbTq+sNQqFJUn4+6nz2+x1o2mqAA4FNq1m+BXw5TfHmLssT2wvYk4
vycAViRyyLNl0yLM6zvb2b/fWa2wH90OHhy3aUtk0dTh1a2zbw/etgN9yFFqfoX0T7Rj0uXyasAD
y+dNPgYMw6JqlIHqCv3T6ury5NZHPDp7j6kYmEtNggJduAA67qgDAaBABX47hV4J3caQI1WN6ugt
mP1y/xF0KFT95MHGn+ydiFCtv9rJzY79XkwvbtUD+jr5PR3AffueDJojaD/wHyMvMz+NyR7/Pdhk
6niuZEpWIGnF5upegJB853hXPmraWkMR+U0q2FmtqcACeoywTIyk3UZpBT5v6bXnNKvvkeRdEaGi
CHDbDf0eGRs3vHw+gvkAYgmrPwjUobqogYrxAJrDRN60fJBN+znBKXOO2xiuWLtTUpjM+By1ebYw
yyZPlwucdjacKmVYq0xHhJ1VQ3MJ7RdvXDTHfrlMgXkoWhdsf4+ogEOCq/p8garYIS3iBeSieyMZ
2Jnm80ye84oVc4m/7e1YT/LFqNTOsqf03wgjzP69CX7/JmGqdf/3ULbOEwn4Fg6GTiMBf5WmAbjj
czuWMqLExRfFlDfHt9KcfIPt4pSTu/r0W7LiPxuhfIFuzj3IN6rM0cNNf9j1GCqVKKgtIVLkFgXq
9k6jiPhYidZ5ZDoQ5XiJ0K883YbILc7VTSr0mg/+u8ig4oe12HTulgusv9qejw5QmnPmZ38b/FAP
gx2MZPQT7/WyEs49tGt+PnciijA4+YxdWWl4Q4k5W9fZQcUrPeWfoXmeNAZFNt5G8LF6iu5izSBZ
YoWThbuvHDAPw/dJP4nNuuSDdF0CdMGL55tGT6yhMSRQUSBP+NFP7ymbrm0KARE+MPS44zjHJISa
+WgiAT8TfFrxMRftFEl0/aC9auTRRcXiFBb9Jz5XZWwwN4+/jy+6DdC64gwE+qGEznZnonQ9zEVq
Dd18VnxVqPY2RV64IFM1j9qyuE+6QvQzznWriPbo6F68CPjzKqlGgON9s3h2eb+jgnTrfgXh6BxG
nDyclnMc72ZGh5DcYelKHORl/qn2mtgcA5Kp/P78VM6ndfVQenEB8OM8SStjhgVm92iFF2L1pQIg
gCZp9tisOMlYhROzFORZZN6Pa0W3tFzaUzTFITCCaAqiSwp97Zs8j/uzWKaDlBO248i0N7LDQq25
4Zb0giKqYc6SItJqBqTmtulbfPe4CupLJyg9U1HCQe4ccTprrfCCJazXE+GHA0e2+cdlJn+ZmbzO
/AYxOlYsDFmHV42XITwluSMJAQ35KckURw9FM+BuBX7id1voYChVyhJY0EZqDUwt5IFrbMKA+2rN
Dc9WjoBr7cRyLYA8ZigJmBHNNSCpBG9ru4OPydHaHI/9f/CutYWdvXWwkri8JTQAOI4DFB5U715O
kCfC7ON/vlZabdQlujmq/LdNmHc9uvgcuoKCbxukdu0FJJA9b4QDTU0KnE+P3qm/pB8MQ5j2lM4i
P8kpZ8KKVJya0yhQ+hVCO39I8f2ApNI8Yn9VVpIsmLIpi+80LBcxuFM2Z6MvZ/Pa2MavLtVuiFLX
uWrGQWt+etbx2vCx1G/JUq7MJjj+9i+B86eY2EP89MMjdhAtXWZhrmVfBX0kNggBdehQcQFDTHPc
N4WSIK2SMTP4LsBInzfdGmc3xZM5rOiWC5h7gR+7mksHAWyumO9lGeZ9nYLv+ZGp1m5xaZOx9uss
3gB2XkoUys/J4kN/byRdLPl46oLzXaFbMRcI8WhsA2VKpV38vrYWyaq93D6vUURkGZ0WPGHDnGcS
+7Xv2f/BuDkAd3qNdlaZsJsAOye9GQc503T+YdSgpFYLYwrKSuCKcpDKqIy5FhIc1t9HFH5zwmxs
nzrf+/1wobZzNaZKUMPWEyM1ZoSx+92tD8yserV8w6BVpo+3rVJIHBNT5Tp/4CyameYo1y1YFeGF
7Nt0LNP0E0a4H744kam9kBAUvkDdmGuRp6ruz5bysD+CXJwNKl0jJ1iVbsQfN4SFmRAa3LCcsG8j
T8QodPB79Nwxn81xS/c8xhlYcLjqio+jVDegLJDv1OxHIzKRiv2ZZ+b87GTnpWNSsgpwlPvUxOhb
19LK8Uym+33+PsPnaVPUEcH8DMcmaDoearCSrVhEveGEOi0Fb0DvJRsk7wglK+4TTCVx1kC59tu5
ptH58zYIexe79GUJmWcRuflu0tsJnYvJeTlLzzK2r9NBNOtuoCsiRhneHBpCfoWHMi/jUb6kUgDx
IYmp9OjnROp4PUI+4r1qL771GTk8+SqHA9YkV3Ilub1SI9d5xFkGokhWhH/f6dgNu5JmbjNTLqSi
KKAUDs9CKVlBqnn8/aq4CWyhjhsMzaXGokcLBu97cnnq/rnD8DWiYwJOLDupOKHqaAOTyHHvY+Yb
yPiwNglzVCjD8xbICcjw8WUtfFqNCXz5iNWJ6tqTFtD1KFxN8YKaP6q+uYmRHmzOPhAoiWoG7A0g
79vP3WEEPX2nJngzValgqn3uiTRmFlNaavjX5bGUiDnxH6OcYhdXgcI0uDvdhK5Uri6ZDhgtJhBM
U32VGNRrpJXmrpEauUpl801SwbOsUWw/Rb5Y3w+QSBBAJ1a2QG/s60eSc9gC36AIIDZKcwIfVuAl
MyanaO7oXPM6Bjn0Vw/eN6bo32gIyJAyQHefHOysNWBl0s0kPHTqeZ7V0/Hhnobfux39aj+Txx/w
WZrnQqKkSXvaoBfMBOndbtMPpTzIUtzsJml+zlPoK4iOXjDaV5l9f/A09tvQn85cx5FajZH1k+k5
WvI9r5SPZSTtmoGsk2kvUkfkB25yJS/61FT3oLuWfMrChc8oEATxrZukOcdHNdT+HD5weMl8Og/d
0TzZXrS5Z1ixDv+w8Bk4lkuSsRt2VAlg7SaiKmwyTCgDouk438CRLueROd2MOozEJo4Mlp62pRfv
JQZaTGPc1LuFTKOKpC2VAxFV1A0hcaucH587TBmBaGkeL2QG1liYJkejOivqw/YjVUDspEzxslM/
hZAInxybd/cqiHoYb+mH26zcwsnF+BMJV5RNBJxi5zBW8heOy+Y5VoYW/uskYnNU8a7V9cRJia7v
6cAKqB9f/CV59Uw8h1flcDROdP6yutjWPXmH4aT7MwqxonyhOPBkKHAWmRxukv5zwt2k747sj/TO
bp73kUW081xPi0yI04wx4asf1p8kBPUFkn3SR9YsT8pkCmYGKXbDaXUApfUlfNYgZk7iBLaiDKId
PJbZ5jsQMXHUDIMMfSv+qIyD0UxF/mDkQQoeEa1/y73GoYoJNNbiE9Dl6HJZVCS76IgA8X0ol05L
Zg3FaG9pXEf/eBTkDCWyxyvpA7269Ar7UNoKyk5qJfkEP9sbsC/1d+YX8u62rIOPntY4oLrYQrL1
mmdL+esgBWo9CsZpZCH9GkYNCVHg/eJLvXeuUskbY65nQlZ7hb+4j0C/3LFTL3C1g+862xHv9exe
4GOPTQ2Njs9sPRf15BLsiJ9FznxVOZbzTt46tVRBlvRNtZ4UHmmib02Ds9hIZ3oZtVVU9tBSL87c
VequQVhiMEZEmQp63bwGEElDbxPRXOsM0fYpnTUlF72lpiNbUvO9G++hZNtUik9WPj753Xyw8ol+
SuB7z6HP6Te9ZeUFNqgZf2qhsD8naqht4vz5iLqGg/RcCHGfT3KAXKQdjurS3zP/cA6km9o7d/6Y
gYeUD620gylzsBUcp2+/hT2Y7/TFE5o0yui/N3HIDEC1xEM5V1GsF5EpJ/VjHpT3xtUOoJO92Lfl
7BKZiNs8KKbwYcP8l6JPkk51niYahb3lWzAh4vN48On2vLQV/PzEMzFXK/apUJdt7lXsExXR96xG
0dTSBSlGcknOThjfR4re1TEmPgFyF0ahe+/Ce0GXaVWXSVa8kugYdqaUOlNI99AcYOrSpTgXtZGe
oyNufYfGe2xVFUxUOT/U/kiKrIQcI10Gf8UhyoASdKI8SJYcuiy8yBjYntdo+xI+w18JS3vp0IPM
/ugY17kYQknMuL4Mglez3SsvrBEMGg4nSftSzZ2JmDsWty2zKF+pg3U+4daj9CT4K2vEeiAV43Mo
UhMAWZMewIbNd5193fclJAz5BgiFOFh2i7B1uoFMGaeotvInfFJ8A35nkXXx01Da243blbHpvuUO
ly0WYjZ/GhmRIh9rmyUS+SNNU6iemL5S4YDp+tnIa1rGzYyLfXMkSGULpiMqX6x5rjUhubIW1b/W
5kILUXITud3qCVYEMiZ4gVWNJBToXPVjJfa5K/IqGv1WtdFB83yBACLAKskBeMyuujA3lFdTxnLB
//CqjSec5zbjOkBSkRCeHGjLSDbAXk6UlOLMSHy87qpwnhdk6ZZ/JcGDMA4ZOvl3kzl3fMZ5uhva
4toT1LXQPpy2nFrW/36eeFc4Uqau6yX7rZUW0b+ZExPhvdTaDxGGUqDF5Y/x1vSBKMVrlXGh28gA
4r7pX24k+HGwMRUlmTmNYpc7
`protect end_protected
| mit | 5bb63e4d65f50d5497a859e6c5198c4c | 0.952962 | 1.818214 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/generate/rule_003_test_input.vhd | 1 | 419 |
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
end generate;
IF_LABEL : if a = '1' generate
end generate;
CASE_LABEL : case data generate
end generate;
-- Violations below
FOR_LABEL: for i in 0 to 7 generate
end generate;
a <= b;
IF_LABEL : if a = '1' generate
end generate;
b <= c;
CASE_LABEL : case data generate
end generate;
c <= d;
end;
| gpl-3.0 | b338d2f2f906ec89122c633e82020ef0 | 0.615752 | 3.379032 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/if_statement/rule_027_test_input.fixed_upper.vhd | 1 | 566 |
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
ELSE
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
ELSE
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
ELSE
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
ELSE
z <= 'Z';
end if;
end if;
end process;
end architecture RTL;
| gpl-3.0 | a9bf400f7d201aee98db1fc2ae5ac19f | 0.379859 | 3.19774 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/fifo_generator_top.vhd | 2 | 34,425 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
DjXQaT9F31fosyYRaG1Uo6gZbVO5OGjdfQCr7Z8lo1MZiMNDhSkJCmCyeLNV/JWpbsAQpXn1l+Ol
pqNHN0F3xA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
L49KGpoY+h+5aedjMscH+i9cQuDk2QKC9MmUqucGo2R5YyBeGt9Tw0IFWaRHEx08BcROYJiqz85Z
l45DBawZlWIgF0nxkRm2dBaeQj4yFlCz1DFev36vl6ocHoJYZQQphtBrOjUj2mnGvrhuEfBDlyrA
te4UYLdH6lmWVhIwEuA=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
tK/Oi5gCl1vSNMcN/hLovMhIIH6YwzOy22zSL6ic+G2bpefi3iRcYlC7Gh9SMATxB776pCi/Tk/H
b8vpFjFlBI7/vr05H1tbrryj/LY+nyhUhfex38l5B1WC/miIT/PpuRgm8rSmgKv4Zs4J+3CLg6tL
2Z6PrIrVabG4loS3jCUD/HATBguaKsur7K+35CP1HaG77lGi7m+4Hb148sBe4Qzipr/5usk12apt
REYy2P4U28VjP9cGJtZoNC/68tRs3ptkSxyGrkJjWUEgILbpbav1XRpIlyFH+K5MUbbc1HumdpE4
nGjOK+7qPAbQiG5Se80nsdKHj8Jm4Js7xt6mtw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
wEAV6gVNHHl6St6UNSFN0mvO8pJIj3YasIG6CD8hRLAedoSDDa/qJ1XQI4O+F7jk8viVcdY4zm28
L7qtWlus4NcAenl0RWiQajqfvMh4AU79RzNQQzn4lUbcOPvueJV3oETdhhCyRZd7693xPDWDtQSW
q8HVqGQWMsM9l288okQ=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
tbYL4pwKL1+pNF+qGjYtGkK7cdc+MKJbywWyiyyEHhv6+ueqcdHTSWdLK/6IZMKBVQUY89qmzRPu
LQ0aJTDGrB8dSSZMu2/EgzLj6bR5aWbaN89gc8rraR36tC3YvPtlmoCFv3q9nW5PKcBrreTP3AOd
nfqeenJHyyWjUHu9XBWcR+C2s3Ph7oxlCs8BJf37Y3KehDgdrTKJgx2aJ2Cpzx5PrDb61BGkMTi6
hM1+bLmxn7InN/KUbAwqKa1DFXUGNIF01f/cQu7dInwF+Pm83xnjLOeFQcTHKc5XKpgSrprQzr0B
0vPPPqjnyW4PxadlsRIlxFpl2iBOUIJITf9qow==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 23744)
`protect data_block
4epkPmYNzN5HcAsLautWBgziTa6wcSztWoFmhIEN6ws5vIVhIx+DpWE8zW98Mx6D6JyhPDKMrtJd
FXuhRsHf0LGM2xAuIacv9UIAGEPID2NwGt+2JtK25uwxonAVImXJpgQ6ZDemJAh5H1tGJuVLFvy3
kZ9GDH/ngubWOPmm/yaSb4vg+8N11/DPA+KNMHflPa1wdLDgA5sddAWjckrlw+CKToFTsYPm//WD
H3SwhX5ArqyvE4hS7jee/gqTJxT+H+fay+s7IJ1vYwUaywEMQNOpYhDQsLjZZF3mYgn2CSYXOZOK
jiic63yYLhhhFmTjWBZhizJuAy1qA7KGQ+wgGe9pDflMXE7tSPo5Vcw+bW1je5Lw/L/RXvZAHUkW
jGHNpngW/BpdE4wVHyEyUD/rlkV4sZ8PIwX34yecYAyXTN6TaGjMaCmtdpqfSjcQQ0WUQ5t0TibN
WmZbwM+5XYXZHGmOLvRo/E2KnH9preFOuxtktWfQQaWaM1lgYVVUUE5fPzUIz+UDZTJL7Hgxx3E7
ibXPhTX43MLb543stjxNvAdNzQ/77oj54PkokOWlAiNPYZr5EokYF/rIy6edWm+T0m+VPoM2YNAe
HM3+E5MqdGpYB5w0ULg+Kbaoy2Dri9oveHMXN9XoDBv81pEeLF6rNxGaXffLVaOpnt9HAWoW4EIZ
OaTO0HgH5KPcT5YQr3JI3GbqCkNKu1eJ1xnIv1sOi1Tvf4v+8U2DTC1EdUvw32baLAPGw1u5fekf
b0w/C5iUg2feVljlCcJ+3xBiOcDRYdybCFZYcZpbZg9uP/BW8vuNvmwAsalf0plUPZYwTfBNTrYg
+y0p9NeMjUVyx+Fk21CwGmeG6Mz1RMFFk6TSfz4x9p5PsclcCUbx//8oESC++RlfX4MZyU/eo4vm
ace8w8Thb5ItxA5pqY34qe9JKdw3k4B4eg6KKkRIB4dDfcSgQWPbZJ1pT9g0Se1UtA9aXtU1UfO8
h131KQpcY3rnNBLRmSggef4I+38uNFDVnRPUj6UJZxCnzn4pP8AJflpbNF/k2m4Fcmb+Uq1kmi7A
z2zCnBcOwYg9yPvEmXfy1SwpEnZyQhQ6JLY8hLfR2jZIFAIPaE88/xozEwXQFqJP6WSNZfQCHBVu
vqDL06F4TFho3CQxfbj7sDYHAi6vaA3Zf+pM6OdFG61bsTDxVG3xailuVn7JLcCTsm6vb5dduk/C
0jJLshef7GheXMwS9xNGZ2q8cJuB/GukceOentQIfnS6aQ1tU4HRZ7iymNoNuUZQcrYMZOMaZ9eW
E/1U6APxSy56S5DUzysmkeGSus7IxutTJwBLdwsnj0VYULQnC9agLOeTsLdn5jvciKW62ieyy5rK
bnt6OsTIm+8CZh6rn5y9P4+u999ehuUsnntOrvcU8a2RcuY5/dsyzc0/kRH9oqh8C1Ko9ssCZCi3
/2tDtup4meMJPJZZlWGaswoI1xqFZYrXOBfFUK8Y8xgjrzUjHmg5FkiJKO1w3eJn4or4PtaZfzwN
GmlbJ4pTjG90/HP1IMRGzrJRDNc6ap/2H1oo2lVKxDBfz/3WCB7ee+SynOtlNLSXvtLjAKkf1Iuq
ayde0z90Ota5sXKnhWPVtAa+uhz4ntH9FpMq8cYZ5zk1B7cjhNNcF9tO+qALj7Fni0oU45/+OKJQ
O3AUDSPLc4xnqxs6OM4FFAzpnpmsg5iUnSvdq7E4H6LHgXDxEWd3PR9he/2zxxPFcpki19XqPtBq
XtMasensEtJd2C23NNR3DsqfaCO3dGxCmD5ZYLRjutVKBLc/e1G1ZlzmgqC5vvEJ+yvSMazUATK3
xXMhRTmGrxukFQBh8z6qE4EMRakGiQmE+9DuHR7OmbvZBD0oVfMEUehxcL9mKp0lLGCIolWJEPob
B91zg9AFN206vK1vct7h60giOe8S1o21XW3BujyTONnftFXFFQ+C+nMtM/MKoRmRnfDCxgHPqI5N
7UIgcag3pKKvtZhNf/9AlHaa0JCjyPUWPWQ5omBbcNl6c2f3rsmP0tfIIM2nMZ7VJpp5rOoCN6gE
xqHRM9LHsDRKOnH6w7gUOC6NOU0tsyfUD3lQ+zS0Q+dCVutrGuStzgD2XubVshwsHaHKhVj0bb+X
kmn89hBtERmEuNamE0EZTodQahMc3JAM1qkrEShXFTF92moqrJ73qloDqJSrD8NkZ2KZDGtH7BIX
pkJtDDWIKsvQBMERLqiaIzp40Q0TyJUQUQBGOruuF/URx6iureHvLfiSNy/uf9LTBqnqLVdCzJc+
4d5giIyWQTOO8VQRBzQX7hlQChTC5sxHuNoPortFBbPliXT/hEOgYDooZYOnL6DSc4YHwJLa74WI
rpHOZHdXf7/GZJQ9QcsyRok2gdqyXuzbDYjfy7nTN7vUv/fytZthQ3ShmQ7p8+j4Er6eaTpL5VHz
rrPaRVvqUu6CKhXAdezkmmN39FAgvnG2xKVkri3g5Ys5ENAgkrcj+y5k/4ZvI3Zhh0gOXcKQO1KR
cCyND2G75eT60qDfXwn5TXb8zXV769u0VpZ3ix4WGgz1Njye1qhc6J9Jao+C+UrJbAu+WMidspnu
VQXnpKyZWIZBEALR5lK92j+4R4aooThTrMMCanWIi96bWHJtAK5fWhd0XzOzrey9OuLSV6wASIvm
CVwqfGW5IIc2suLXi9CP8XKaze1CTdE/AX/l9STPDcndugSEIy/tvpvqw3WHMju210yIR7PoMGrz
D4ddDZktalJLgSi2D6N/3Ttf+DF358A5aAuNO53awskMQ5Gt7usQgbzrapcfHdd3j6OVgEoGm6W/
LvSGBCGNQgTGOQPplxSX07WyL17Z3M8eGKNOAJme9GunBAKvF4ibs2VNlDCQFg4o2Dqy4Up+riyB
FRAXRoRQni1Bu3aS/gBhbZwjJWBfhc79MvarmAMtZqC+uBMB9Y/Bd4fWkODXi9RB/BDq/3oL1e9Y
AW1RYi7NV6D9TLWI0Eajl8tSGoa6W3/k4lvXBcIHCo9lpF/iiJ97y4+0YBu55qibsn3XDKRq4vHF
kBYRyVUERTQXF77R4KHykb4IAXe5DLwBQkcsj4Wx2tLAlM5WlGMKvAJ5ndluiVNuaz3KCLyMuje7
umQEErvfDz3rRXBAvJSsjtAfZZXRMcx4mO1MhM/D4RVAopV72ZymaURRwt3FwOIta7O/9DT0dkY1
5xdIgDUDS99L4Egfcn+ryJtWmCyOlbzb5EBFS21VnsvXDmv4Xq3KUzyLWr3q5utXn00pFFgop6WO
+pqpa2Ya0Gn+Nr/jOqNJAMY8674+b0WIt1CLYtCXPi/YHbdcrvAafyd4scUZ0geJyO9D0ptA7neQ
Xlv0EWSQRMqxp5DaQY2Irsmh95S1bjuvEXQpgFWHmqiEVKOoEhB9EwVaEdg2n7AbRQkoL19lh5bz
f47fF8itAqFfFIqoeRDInKLx8N/HtPGQA4fw94SQ3B2+R3xpiin6bBmxCZqJTkGN4yUQjHpMsXhE
u0u+W5D4rF09X4lrNFxBdC6f3kIzm84Ez/BpcbsWb/azkG3GI+laUPSdVr+1SyOhSdqTiOlgJnOL
/jIWBCc6P5aad95IcPNrd8kzPssqFlg42xwVR4VY82qEEGadB9ybZZdQUZuZHDiMPJwRFsCkMhHk
SazNZYyRtzwJBAEFWlTJRyTDLDCcka0TI+R7do1y1HupOILOhdByHOI3FG3lzjjR9+S0FpkOdLoH
xwAa1KWrWzPdgDeysXTeHvVU6X8N6ZRfyLEMaThBZSudA5J32jAqFm68eg9cq92d68doFrdsj6Ow
sqRepG3Vek+56i9ykAThpDazYHrX0jv4ZadPueXjXD9NZEQ50JapKtSTJWqTEcdKcGQLuu2CwtBx
d1JhJxMXKc9rUAfzzKLukIyfdbmOSF2l9if8r7iSHHkIR/Akcw4QwWmBcqgcUtw4j2H8QSxiIwVz
IOqlDSzHPBOhMrI5GFfylhn4MVbfryzpLSJdXIgXjfWxzCsQ8qL8vxkp8aGWp4CXLhyEbzuk+aNJ
VdWTCeEsSWfer9Fti/JofE8StLccL8KbTIbVnM6vRf1lRErRL8+MvWFc/Lwdd2FXRKyIPgE9qK1P
LHowgt1AWOCluCoJgjIx272qDSbNU1pauEfB+f597WosWcfz5Ni4vzEtegjTWzbZro4irKt6ZCUv
Dx/IsNN5QVixO4sD0b3xjMZ0Ij0anIZ0GMvYr0qNbDZO/iGZhezB8q7wyHCleSxKQdXkfSIdY7PS
Or7v7JhlTW8vxU4bmjBdbSaOFc0vHNNLr0609iRhM62/cz7LkAYo3q1pMzXrGK3oIy9aZo71DT/l
9QiSR3jUk5hoB1gCbaUbavSUOAVPhRdY1xVu+FXtIzEqnwa+WGS/OCoIy2g2kovoGKElszGejVlf
7QK96VHtr84p2P19N83Vb1M+iITM0+dgtXq+FEjQlN7fPfVr8vCtKhXiP7yCpVvmy+4qxu3dZGsV
DjZzm+YX9v+vFdRfe4Lm/Mm64z+TZs81WAmk6HRlvOk6VWa5za4wr+RywyHYehxMybV/Xtqmuqem
Xzt5zIgTxzKzTmQUY2sa7tKtfIelKeygyaHT9s7yzFcpOzoaxTdu6IiH+KtBuZEQxHSIpcq35EMG
VZ9PUoH6tra/1fNcZkXVgIGuPkae6t58O49citUtjqnf8iSVEAa9rMXiwZd5ttmALhwaSqBucjOw
nOC963XVH0iWdOfXf1phR3eL9y3OzL27qHmtr9Vx9xqOTCtSRicDltWYlMBmUdfqg5fjHGMJUWit
BVMYYnrV5mEWB60pNdrrExBwHIqvEWmo8B8FZtW5pdlDru/cmr/pd488drjd3Qo3jBwvbBXGAcs4
MdgIW43pUQ88AVolcRq2SX1GXZabEn+dkts6fDAFS/own2pW+0pexcIJa6QQ0V05j+hkPPtocxji
vt6peiwdkQCseS9hn7iJzzNY0p5TU/bTovxu2Dv1qHZubrrXtEVlLonMWunxDi0zmHsUnNjwrsKG
CjDp5rpL7tl+QfZvLaRH8Yd/i3K8gZe/7WAOq68JbMrey/9fPaLAs+fja9Dzj3NpYeJ11coj1fIZ
Hnz5LF/+sV26vU0YiexNSBLuXRR0sGnIWakMTI3imRzeXZrhgfIOeYNvTwTrVwYPKIe6qd2OiPR7
u2Lhs3cv98BrvSKt2FSuA0B4x6MCBryEUXBR1TAQTPNwNZXI21XI2w5ao2aNhfsEem5ORGsQOmfC
dVUfP8LTlp8luydfM/WyJDsCkItgKCh44EMVIgVB6OeqThnQrQ3VKPEggNLOBlNqiaTDD+Q0IEvU
XsLjYl//MxgmHcikZC6oh3bo/mAOC3C6RKqYU92fvIvHqP8mCZkD9y7AcEvfblsha8Dr2ij4IM8Z
lnFRQMhC2Bf2eg4VZ7UhVn4/+bXObA7O2H5/tLyuE6F7Lhteh5IhYyI3IHYc17l9rVfdvCXwAFRi
ISOkXFBLQT4u+lqi9MZrCtI6W+5dE2y8xbJ5SCp441G/WIFnLmC3MquzcIWUMJXnUhEBNJ4NFJpY
benNhHQWvsNlYIJ4nSaS3R0jpndHroiPz/hg2lDw+wQYizOZTaGsg2+QemKzAJdHNzAonujLJTLK
I50JaGJcWPIcKloI1u+J5BgW3fjpJUXzTUeldsBUR9PA+6bOWh34BKe7T++MGLCi7GRR9TyTxhcf
rnMtQs2AXtRCncitbmBm16CZTFd1IxDqNFZlAFE//58apWxd2UPMoSA/t31QkiGf7yYHy/ZGxrvV
AS9VvOE7w+6MRzzeUkkAiAHP972QVLV6ikZQ7tLTnNs1wnKlI2GJ8SChTfn4hYBemPKmVrussQBb
a5x3ip9fmM7aI5s/KiMljrSARRnaAuZKhMfR+ySrRnYika5ClFvFY/ijtAB7URMhG2BfIL/sz6wl
qDXV2Ar4nHotgbEJAMcA+rUYo+poGKVemNjEd/IgV53MD+0bJLl/c3MDRhx96BiqOtqCYL/DZjMR
XYAXP0+t/juudmqJ6ENICtRCUFeU53Ruu+Ok37hI09LTUziDlaeyokr+FnacTepAwcZbHn4UwM+O
vliYWjBD9xhbu7+5elS4rrtoUtxyf6W6w5uG7IXml72rVXB51zs8Oek71cJG4aWV+CIPfSEEgM8e
ib/z/DH8JWC9IDK5KxtJC73suE4wUcCktdY+XAytwNywDepzvJPa4tqYC0GYSx7veFAWoCqZ1kbl
5+j/kT7FUhlRZd5aaRNkhwM7UrPHe0z73WnTDBmjGGNWJ7Gf8NkOpMqg8FM63IgFyTFPZyBHVxdt
WrcN9i7ItpuXCBhOFkp1yLFSP55cM0StEZDCB7gNBS+Xfc2W/34OfZ84RjRQRIUrTlJd/gxlPkx9
DH5gM4gADohxc6+dMc8HGn7fR2kUAYJr43JZWYUjCS8Gjf2kzrWZ6qxmzHwTcax7n6KldBY/iv0P
MjbK3PNLkGxNxkOvJ7Zr5MDps0rj5NdnyMtNpc+ctIJduNr2P1Uv1zFVnOMbe3UY973zqsDk0Scp
99xVqK6HypYfc6qQYX5CvWpd+1x0HoXwvEPsbNtzweKlF7Ns088tsJOFQ+QSsPiecOcHhipzML6t
pDJUVujk+IwVqgp8Ph/bsCICPp5FFr+mESRehKPq3QpiaL6VxF8LunwIFXAtJqnZdHDLN4LPX0Rw
6yNf3reF/DmzUJWIEKMISfzAgwp2JztTaEWlizjoXPcv4G1smyVxX9EOBTpq4CbZXojxsLTpgAT5
EXYQzM5LsUo1bZ194L3ytKanaiuAQdHb3Tk1KftlwdVIhSLwvbUqIvEGoM41W7rxAxEZR2JeALpi
Nk8jDbtc2FlnYqXvgJ8AkWfrH6eZdrOLkfLKD2r4VO30gI6qYKitPJl6Ztu6fjMhrQm8VZwtpHr6
ckL7Cj3hv9anNZJDyx1NdlRMol8Ev7CfWwhAsoUI4gIBVmb/EoA5fIDwgAyJ2mgJD3LLBALw+rSe
p5qWOEDEJFGap2Z+TIeFFhi8uBQ7pK1IcFDCpJJ/+wcxNa91SbTqe0RQ6Bvsvts1RYM6bqMsMzuf
HdF++DwMfe77tsst2Jwq+YQpHo/pGyKCKUYtEGlby2zAb21puYUsqDxXC1C3Va5msBOc+mWQ1Uo9
tIJtQMS/1LJgTu+pYD4viJg5jASR7y9s25VfnYGjK67E6lyY9jZ+rAOjM49+XCwXQyK5BmS5+jEp
tkHlvi7J++edWDEfQucpASukYl7JFnkxmpxgo8HFfbx1P77krpqY0Ej7UELXdlbFXfeKt4OXX7BQ
H5pTY0uHhrbW9zvLEy9CDAZL0CaD6d1Y0zLPcnCPmALq9ih4JOR9/j9e5DIJ1xOUwBW0lMEUTl4P
DdkG4sNxtlkfHNkAkB2auKdmMfb0r68N6PRwzBVc8H2uVLo8luQKqmUMmkI5HRPiYJ/Nshn79qNV
zO/x0BW/sJePFm6CEEg8bk2yRIBspYQ8DcRjJinqZE7IkAZNVyMc3K7IGDDZEbWe7ZMvwRMUaEX3
jqj/wxBZnhQi8aXO93NexsMgkAcGqppRQ32M3AgZSGezPJLY22eqbsspMrrYUWsthRTv7PY1uQlf
ZE6QtWruNteUgF9HJ08IDU03Vpj72XCQRjj/9fm8pOjo/nfm/3LZWVkhUFev1xv2bNRftGDgQ5wR
WGlaSKTUoYdT65dnPofitcZEsKzxNrq5EDY+AFZ9Bh99Sh4afhfBv2HzLh2UUzaNDIxVRUWJY0+6
F4ZzLxHUSyOGEjTw1dvHkYo31l9JtrkdI3HIu5gIeSKDTOZViSRY6HkfV+N2EeS+qd8oohLlnRq0
GZDkJJnMuf44SIGYyfGEo0FymINvtQhIQaTQEKs7uWINhJC6hjBI5Bm7l1m0XE4KOjLgaUNwTqKs
oR81WZkpK6yvx1nFvuNLJfuti97rAGFWH1UYC0GfElorVMWt1puNjLlIdGP8UhhsKDjN9//3n/lb
JDEILteuJIP+/W2DimSuLYbqUG509tocj2jW+LYWo7yUutZw5S/YLdsB202yETZDT4xGVIbceUub
QXaNvx9NDctegBFL8MbkLKnnofoxREt4D3y14SS64lB03mfdy7xqH6iOXyCkpbyPHf+q8fp28Kr6
4TgduKszDxYBdwKhHy+FnZmN2QJ11SpnGkCiyCT/S6Yb37FBWDpECALP5tGZAyiUR4hGi3/5gQ9c
OMGrc3RocdU9SjvwvLw4zaPd3j1x0bMDGFKvndo+4sI8iwqiW+CVph2KBIpo7cHU0TT9+FTn6D2f
qRe+fNlSsgjGHmfyKyTOcH0GkUOH1BrYSwKiJnWK57HdNTEcKstlmzQiitdwXVrJrozWVrFZEt6u
nmcZ9qme1l1iGLDUgCIPypVbJyaFWYkzjmtbZgL+xlWd3ixFYXxYKg1IeKQJYmj9uAJcCZpQzBfV
BeqFOFwHlf6Rfstc15N2Hgp1erqtu9qneWNwAhROtG9za2Q9FXYJo30eEfZgIYltQi7WDJ4A70D8
bxWKLM1mrSkgkYGHjZzc9+EOYm0OvvxqhXbC1vCMZ3dja0IGUn5DB81OrYWmlGaodpcqnymW80t5
Dkt0EW4F32pAj/eXIt5W9k9er8xKGDOHCS1J9I4K+EYL+DLCQseyfUtpH2ETL+WzqSl24EPG9Ir3
18K005jUE/y1S7YdvKgLvfD6L4NPWR4yh7gbu/qoPLJcTlWmQH9SJ9acKPLhbGurIHLrT+SveGF2
2PUWVMNrKQpWfWjPt5LhJS2X4nbFvL6dnPyEtPzCAxc70z/FZzGiFx4X9WI/1NC+Lp8tc1/KrIoA
pdL5axw4nVMiw7jSz3jTLGZnNNftFnal+JNzxXevnxatFhxGxf5YMCJVqCPZw0BloNAu3J+81N8H
jjLg4JFWETPRYVVVowb/7JxEtE6IqwYyIF/tr3p+C/1HUc7jb3ZvvGhH/WBI7xtJmwNds+CezeIM
OFwHGT3wlGtLdRUnaJjiFUalVHCJE+wbL7B+2Jkiud9jthKQRqeK49SlPf5Rae7hahLXDIstkPzW
EjtsJ5zszxU1+2ywupoxr0JeiItzV3c/Cm2O1uJhGh5AZ9H7IGGXbTcL2ybWehSI9MHr3Fe4zCuj
fbadS3y7gWrIz1jrGzXnZJwsNIo1p0SdpTq8F+WNSj48cVIZcVVwu9j8WbfhKBeNblGXz/GfFZi1
xHQuuRDoY5kmDzp3SgnpkPPHwTOO1pmqE6OLdiAdtIdKlTvPpeHYop5fPNp2IMMpPvDEHPSk8eWh
EcK7o37zfvX25WkPYtxjRI7fBgc/7JUAaiCDUwWGY2OdAxzpG43Ac4nNF8ERP/ki/4nPD5DWfyq6
5aQgUWm71VBou6pihNdQiSZjqxT8MP83rPoU9404R+cfz8GE5GJw0x1qXAKPJQ3Z+pc8JdZ1Rtbn
XSbgiN78XtiyTxqzOqhoRePbP7RXSo2AeqrKbv57Eli5lXGsQ1bs7kfQeNVMIwNZHlreCVi3CsNx
M8T6B1UlJJ6m0GY0Zf7GioGVK5nx4rx6p8oDBc4epkRoQeuCPN08x7lWYZvGACyktrndDi1eAOuw
xz7NveqzypMcBpdgtXEbauItUK1/2F8yzBNPPpX8n3nsxQNDsalOVnIjKlt7iqaJxxXcOh+jS9SD
tibk2gubXpgebpO2O9MVe0BwNfEviqErNzqGCyOvJBkg9Ej7srp3yZeYIbyCtglq/54YnU2WbGB+
NDw++lLsc/vKKmEkYeU/KPCibm9yADLEgFBYXxz+p0+Wth4DXJ/d9gjTJlUPInnkG7nwTG0xoxVw
3mpsiPh0/KCFFCkuCg8267tkY8anQWq+AU1Bw4MpTFZC7o6py5QALyPdCO+2fu269grkUzxeMMQ6
JQyVHNQIT5vfDsT1+c7hOIM2bxlTimRYOoE0/hVwNjTjqLyvMW4UiLAnAz9A9z1jGx0ua1X7KlUX
hHD8M9QCydPn4BHmSG7VgyWzxJqbjNSL28TW/Ik6VPmpVIDsgTHpij1cJEMGBLyqvSUxRVv1FgZ+
6dhSLsW409xxou+m/LxCupWMr5Ce+i0GErknux+RsWpcBdwTkLoNJiODXrR4fU2F1EV9ONSfvIM9
tLnCqBxlLmgJDGsjrRonKlBrpAWTgy6uvEjVsnofpCWx5DT9rT3ef9hT7CAb88asD3+4Q9ugvjEz
IT1nuekAMAtMcb9jr8Sr33ftyaRxutw+1aLskZg+Jo/1frqhK4XOeHo1uA4hp/d0Kzryz2OguDXX
NTQB8O2UzHVrwt01+kxpAkxZtWgMKQHZOWmXV7ZxMNHbmy1dRCXbUfEkIga9tL4nFxjrRYEqiQfG
IG3LkGjwWMh+4biqYj8CfK4pEqtI5DLVT2Mr8rhp5/Jo+hfusAJGcBbSNwDfztHUJIx8xdEbj0m1
R7jlKUA1BTQ1HUr8COs8ftezfQaOitlKvrzaProPiESgLK9pCEgE5dmw7LMyyF2SNdLR3pvDJGYM
U1sQ6VfD+ohu2We9951JAhSeDfU9p04rNh/+KY49eq5RTfeMRJhriF66rcFZBe23TIWD9kjaAsAO
9ZhwBx3w4hl915PNYEBQ8FzL/Fj3jdSB5FjXjlZnKyJivAYrtnws7GLN0uVq5BEuZqmsV3puHTLP
Wo4RO5ZOq7RpbU2eQ2ytdPMEhKjd8GZw7aD/bfc3We5nmsx3HdzZPXTXFyVWJRrCdDcIBWke/a4t
CXcBEdKBQ+aeDhvDDNR+/ddfVUUmYog/TExRplgq4h9jGVs1C0CD2EERDSZ8jvGXNPnBvznG6zfe
30MW9Esc5AwyNiUnx/jLb+1HDUPx6+yFwMQxxmbj0yXqO8SVZ0PTd8gR6a8/b1+lI8XbY13ETNRJ
yrIZBRDl9HE8oKf0AHOyTqWjD68g3Ptrm3cLr5O56Wrvf8aBzRB0uXpdBatM0J039kpDxC3fCcwL
hSMyOYI0msd3mvbMJ1+ku5hQsMb00OUDL2OTtaTBjF7gkksqhBDj0cCrJKdGCULaVw50iMYOclpB
RaNQ6arhcsUbMsGcjUObqhDjRR1umSmjaZ2Rk5p8llkhpFNhi7YeGtcs3sWmvD8TIJGBsO5ARgvY
C6Q1bFpYbKZFjewTZ6T/FLRqnb2RWD+V0YfkG3A5nUmkpdhzgK79rSRTQINv+3u3wnIlRxBbEiuT
XaNreQTDU8pdjKkfajR64LcpNN8mje75OjYbyy71w0mBx8pFFCsVR2JdKh4RDQmBLHh/gZNwgEzq
ESOR3Maeq3ANzlginNwD35mDf6nxDA4HqQhD0zO0SIZrVn1dotP9soerhjExqIXDBAz7mPu6kmfE
6a4KBKYnGqz02XWw0njBM4M6+MBRY6N+JQAG79IWUV84aYONe4pzzVbdpMpAUK5rf6ntMOuVrwHC
Y9nm+8Y3Ny/+M12zJQk6nuDsAZXawlaibbzWQUZ1sUwrUUZ4WY1BWcsf4hPxfqwMlw5umEQVe22F
/DhmwIzh6didP2VXvqJLzz1jpMcvLAcO12650NxnZkUzrHTo+Wc74WGPbbkTt6avXpabZKVPHje0
s1tnapom7N38uxkp7HLqFPpuhrDSM+dbQcctZYjYA9Hyreo/I+wEm+ZpWvHkF8Sk4F+Laf5kr+Lm
jzXwV/MhJy4/vY6dDIvUNiC1O0dIgu5yIjdk5Ut71w++oFRHnlWaBmuuT/ifTn5jZkn6XajK5tGe
F+JRqawVqndTgUvMxVxBDOYa6pokvgpAGfHrWGijI0vvKvgmw8YGtfHeDDRxewBzl8XIWT1mJ5bT
rrLoP/1/RWyobsXRSRPwtXuiO84oRGVcIy47jE4efK84fUpkFFPLXOnPjVk1Q6by8V8x8XBqUSzS
e66QIE0TMfO/0H5Eez2Aucg6LqPbZORG3Ed+Hnm273se6mrTd7vnQ0EdlmWbzDGIgSVzvJ/R4c96
IhzJj16ieGmbS7O7RCSY/VUcS/AiS6aK+y+44gec8MMP1YU5eDSgApopFdvlLR+6c5ZG63WlT1EU
1ncfv9XO/9LuCnXPFj0vwwkEI8MB9UrO1lnz1V0YpdUZyR8jmCB6eXmg8ypcXMHTthb6HQvj4c/7
z7yo1PU0whmwBwR4oS8ShNG9BIhYLCIfMLNHVmMWtv6YosnLNvbIU2JcJ4EUWgUEPmHH0HlFSkJ1
oJJP3kdZL9uEonyztkF87A/YXOX89E/+w5CpzsYMD/cROzdjCG6R1hVahnTs/N73aQmdRQLWLisS
9sUzHiTf99uUICqJFaz0hD9O/UX8FWxXBl9Hac6EUNkfhUhdkFqfyBo3RH1aD4cAsyJBSosb545h
vcECRYwk1VWzFwwyhMunHDucbUnuCAzOSqcZbF25SJN8YrF/Z0wQCPDeVuQAR3iP0tYMjVvEJHkL
XO1qXHKdlItiqgSvLHOAtAcycXqTVhOhAGzKU9K//5vRhz9PTva7/3CKqGEvnOJcpC2/iQoayXKw
YcILUUzhMmRfz66mOLj3c/3tP6ksyd4P6VBHyO3+RHPDa1eAyIvHmOxjYVmOHJG2pZQcKtPOCu7S
ciYjQ7OfF/Rq5WqarkLL0NY/D8yEXSei0wYyxRusD3jn84Ms/+osYBY3hz/rL5RNgjGecCqXWQNc
yXE5rn4fGjveSNeNXr/8bVW3ZJrOegBo9BprfEVqv2CRJbVEVBTQz+O6fjQF8F6QL++yPRNnmz94
9kkW+Vn7xXNmqghsB/9kLvMTeF3ZanrNw035BegoGfuo2VzIiBfmNXU+SsvLYUA2MFYnlKO4D/wO
Alrp/U+cBe/rFvuHuktgNma4AvJuB8NXarYxWB3O/9FDQZVohIBAEIHpvhJAS3O+vPeIWBkC9wvX
uvm5CpNiJWp58K5oeGvQUx+hxUQ0lBktY98pOyVGBNtx4pcaB8zEbZKEkR3bCiksL9qOmsiZdqIm
IcW7AAHuJeTMcpwzrCJACWSmhQ4EF6uJ9kvTHCTC+f+HJaZNO5mxp0wukRkFIMUY0WcwR68Tu162
KVC/u6uNXcnp6Hte3DWEO9r+/MDu+4cXOuPwUhcC9R7s+xn57O6g57E9yP0JeR65Oqaa5drNUcdn
3vi66RI4jLpx9GiJ/4dBVFD38IUEIhDe/aG+QDVtK4Zhm907CA1Gp3x7kxqZaYJitvFo+QYMur/0
CiM1reWQy5xy7z+Cho3oGepTskEDoCjuezbwE70awbF9vOZpA1NiVYxv7wXDtcxpKBHrshhdabS8
cajd1oFNWkiYcFG2ed6POprtHiipqYDLa33aL/4sbwBqaYigKkIUo3ze2jD94Xn99TTGPUTygEM5
gNMcQh1wVceb/+daeF3lYkMI1erosKVVUSPpz0EiZLKMLJjqV5AtuzAqh9kHEKbclAqeS+0SPmgg
A1axvqdGKDaJIQxIp7mW4ExDOIgWus7pDGK55YOAMRq6wpz9GulMm/SZMeeEq3UlAUOgwsMV4YZk
7jtO4EIFTKFTOmw2wXdqiz+nQHEWEGKHOkgrOMmEWNYqexFqBPWXnLQj1poEs07iwIah2/mu86YV
HC9nhjFRwoGn6mGgRrRI9QE+8rDuDKM45wjLJCjfwC047RDOEOW+Fg8msw6JYmonaKLk8/NlS5CN
ljSgJ9bEz45ArvjbqwTsdw9EyFXnMb9aaegI8MjclXpCTTQ/N0Y14zNVAedL+RCiMMNtPjCPK0dz
0uo2jxQX8U3dF6It5grh8aA/y4zUWnSApITV8urEix5LZuKiQN5c8JW0nPSbcdFbOSkHi71CmBGk
RvPp1vdJdp9P4Pwt4D/mBQ/CCYSK8aG41Ba0j+BhOoPBJcz47O43sTAISFgGrdOL8JDoSkY+oY4F
nVxOL0kKvLrgpdTwslR76iB/UXwrfmQwBthxjPIUQsL85ZTSkEIo7Ejxgy9PmOQ4C6/sBkY1bjL8
HEAwb5K02WPHCk2LekR8QOyDt1qyukXKc+KuMcem0qUtE17uNPbz2g71PbGar9sQDSmvDqT0emca
mNdcpLY6SHhxJeQGnKH9CxgY8PLn4AHyhB+QDa4N7n6Y5WUVmz5BYVm9PeKu7/wzudXGxA3TvPIc
rxO/t5AvKOpc2sPUTiceCdceARZtP1l9idoDJ16Q2CY1QS2wAH7pIs0lNhbILLb3h07vGcjdlP9o
mzhL+eJ85UJ6L9M0Gc0KXcYpdFRlJjJcLfBapg13I06Mxtva1uOZ5XFmuPufAt8ymi3J4F5J3Fyw
QjvC/Tb2g0uf85kiTm2H42DLqhgSvxz15CbmgOWmMaqmgf+4o/ohXoiHOZf5UopznoT7w1hm/Odr
xLE+aRC250RLlvQAMNLJdUP+kSEnvFzW1krIXvZLYioi+UYkRJnrCdqGYo/597jTJOP607AeEY65
ifZlnTW1ZBVXf+aSdebbFtkSEtV4X2aWmOW8bRrp4kBX59Q9AbPKFVcUtL0ruhNWvntSXPckA9C3
hdxiuIqxrPQ4plBjV4CWHmIJBTq66P8bh2ochWpTrghTiAtGV59YQCpndiRd8pxdeZsOtLA7asmb
83PMg15fTAijMkHqYt9RhAMFfAYfdQ5BIMOBwNYduMXAX2K+QQQR0/xzHd+aL/8OK0/e/zMDlWtY
8IoC9gKm2QWM+ApfFCJ/BxH+IIiYX/EovqBtHAz1CSn61uM0Kg4gNo1R0bzxw+mCP5KEbexAWycq
AEX2aGONEcr6N5lP5YkOHvdQoWdoP6BxozM1+VGp3wWH2NBzhF0KQiOlrpaqqphkvi3KvDW2XvIZ
lO6Ej9PcEUkLCbCPTMzx0efiH7RsJrOuGzrrUFVaMHLkP3NObLu/rpKexr5mapHCE6+sZ7HDLUnk
F6zrnd8ObM1xkQUPjL5sVUKjhGgu2vHBMBgFoPrL6ime0PPGYxSRSEF7sX0+2PD1xQtY5TI7mrFk
jSwv3DPyklu6TIJEQE+hJqCipY9knyP59GPA2u0Nfzjp6boncRp9+1jLaBhiUmoFXKYbzWFGWpgB
6UX34f1ImV5T/+DJKsiqlh60oGyiSZi3RhN+Ib+pzZZaPIE+THe4pnOEVevrBE/qmPV8eyEyo7JE
i7kRPP8PF1opsj8ydeDCogbVO+dXnetbqj/QEoD5l1cGJJOeYKDcxVVuNXxL1gCGnOrkDx5X4hWd
EpFwnh95AsgfyNziPrDiuZz8+QdIkh8LIVIA6xFnbO9GrIVViqxkkwnLr1YIqk5eiSLMDjB/cQrS
xUMOmHqK6qM0Fw5U/S/5N6zCVTVvBtlyvUWoSq4gM+sOies9SzFbjyXNcuKX46hHv9n+EblnkOkd
MGFSoFJPAeTuXvTRbRKWLAzXhEUyP9mAJqBrcN8G9/nApAND83VNe9BhKaxnsxVV+q/d7gUg90g1
TedvbYXO/PJgyo4t5b46vJ4Cn4kYdDqDo0imKVX4CpUmI/vZS+SIXpABi52cPKNclqOWy97Ophfb
2xHVIvuHJcKaGHGg41vIsB+ZJ56DqVAv2Lr+yGSnVVtHyxig9wKVFu74F0S6z9AQLkaZ80N2UPcr
p/97PKGcA/KdkgR9pF/hqfTfwY8Pof0QzzXd2Df3Tq02pVdQxJ4Ud8q63sK3mAMq2UY/FgDSp+ul
y1S2UEOIC6zYhcX5boorJr+UXILhvqchE5BsH9nQVWM4huOp0aE1Zpg0gJgMqpXIaFN/MYkueBQ/
KW1EO4wsdpxoYWA+HDtqEGxba66Dc0OmqfRyUrYNwjXW0Qav+v45MdCIpzjsp5wClP6E9BlLhMjD
0cotJVr99IrQoqKXw5AwsbJUymdy/vfG0rM/8LGPZZUeuXnU6RxO8qyz51wYikHLAo6fNroFPxoR
f8qTy3MZfQ3YmzISo4EF4fbE+TG484zi7yuG/1ikqbOCed3V8T+QPjY0NFSHs6M87/aFJRB0xPc1
8X/W2yYWPwzvYfSPh/XIlpqbTkrWKB3O3HtYDqLoUVMKPQjHVJfTmuIvhX0uOg2SFmLnJYW4aL4R
tN1252mQxgyAnVaq1EllLqq2FqQdW8TEodyP0NGSfkEkGTVPBzwc+1TqPBjSOAkKixbBrlTz2d84
n/+qNuFOogP4u6PqpWkBuW4UzAhFB1TInFaPkweu63T9D6LBUybPgtuXqUw9Rhc/wn1J1Z7xWJPp
La21YJGdZ1Q35IflIqJ+NtG76/mPsWhCOjsuqXlJ/fR/GksAkVH+FDB50/UitUqibEaz6XaI4Dt6
Nd8ui0QawBGqjap47RlI8dS20TuecvKAXSbeRCkE+WpQI99z53CnuhaxY2IUuXf/IE98VmhS3Qsb
5iacEuz7zzveoVyLVdy+xdEtua+NOP5p0D1GbmAetjtVf5F20gIm0U4iOOPQUcOgWE1YdyCg4fkN
Fp9CLT8DE9GDiOzSM2t9bowlOCUNdngYIcrOmszNstX10iL8In/8IdpQ8cSXOhIqK8t9PLaon9jW
V2L1ktm2nirUxsuvNUR9M3HFzo95OQ11mhvFsiAjblQurYfiC0wSoBB4x8BKsFMVrgplxICWcq3A
/TseWHROKqOsWzJs9i+PLT/dYlRy3IN3F/fkuMwwlEDvgDAVYlSU6wCTyLAoCnIokbRWXK0x4n07
lTClm57D7SGuZg2kT/sv58AEaeYq6c9u5gLNAAdwHEyhyNYH1CXs2eCqKViaUUCfZxgbGUB/NA/p
FfXsSyLb10gYzyfCfK3ZGRro+NdfN9dJroJsTxwWxnWufpWjIb/eyma584aZx1pONXRDQbE3y0/G
I2OsOQZhSNVatpgk29J/5C/9bhno2QuBq2SAbJzt6d0GfNxQtFiTNkmjYj8UiDcyiYpmuanayN16
Jswxzbp5I8w0rw+yZfozT1kTu9HXhXlgftenLAu6fxMl17rsl66zJU4/FBDbqAaWGC2+HuDDbBxR
pbvxaqJ+nOSifBFhKnEryp8dfzA0yuJT59wRoFpP+zR6riNUkmnMfPbe22YBVsaJ/7JP0odjV4py
SedmYq093H6wpxraejEaK+sXlPYotoHj5I1O0YVmnFPXUD8WkBT4yu2OYC3L1RpKhKk7KRSmTNvI
EFIbKXjVxVbOEP7ipDgnvV6z2URyKEb+53DeIJsBOdYCxUdASMqJX3Jyjz2S1QlxxR9cE757E7jr
V1ugZGY4hosre5ZNrIDMVH5tuld0bwwxQ4j0oFsx3W3T2leeAgVr5oyXmxBf6nm+BdokcJ+Y60+B
p9uM8xX2SslqNEv4t4Vd/RT623+c5OGKAgO/rwB7mFrpEdcocCtNYTwtzl5yXL8PNVQnmbFl+8HY
xlSVjWmFve8yWfUy78aka1s82G87y0Y3Z0Cf04e3QRRv4RhR/E6acCRN5stTrRgQhC20sTpGt9nO
89A/QDf1NjtkdoREgQfqwo37JXAWRoyGMEa9hhQfeHp61Fqg5BLes75FXYzf6bqchBTNkpxgw81o
bjmjm5ELyJ/55D24jzieh3LGKq5sbjSVjUyWJYc01oiuTb3l826TV7I05fLtKudblFdrBEH1JxRM
i7f4AhKk6XfYpsz5KsWoqOtYglYep2BivIE+61QrQXCPX9EKVqxMMY5yNz4IUa9FzBxL35hlf1cB
iCv/cq47SMTtJ9LOufMn3FSPQrKhjKoyhDILc0U/gICm4ess0U/IszU37C1JVdA0w7aPqqOuZddS
B+OgFMiIVdbSPD6EONH+5uWoio35y9t1R5t0M/sVIh2+whqADigch5btCbNTtmX02Kohwq4riU64
IerMXedD0X81PEKuvIjElSjP9h046CuGlv9zL0+267knZflDGVSboj1hWyvz5JmR29Qm4dncROB8
qLLYuf1ehIBN3Q9gPZ7T/QAFDsrjz/xU4YBH1AvzUg88zMptifLKmOsikNJ59SG7eZgeBGkZybWU
nsC1dS2Muq64Mv284x7kVALA7G5hZ82p1QWvkvnq9lncL97oxaO8j+hE7Oeyd94Bn8G8i2Bgr98X
lctfU1SVhM62IFj+ilSS34GGKO3ivcgIcs+RdakPwrKlfPQYouUklMZumTjHVD42Ofp3PpV9LJq1
fuNszdnp0jnpSRsc+veqYjiZuWvmu+Lr4b4vt3L+ebWkR4FtaJ5rW/hdYoKc3K53C4HftRLH3QM0
Kmy9p53m1+4xU22BhfciqXzvLshTAvlkQC0DmJBA0AUCgHh3PkJcZqEvqwsNPu8noCJZvnGGwom2
blPzby0Uu7ZNdmvDJKfoR46EfxsTT39CscAhXq4ZmY2//IZPlcDvkuWQitDr+mjvgfojlg1RJxCT
o7y/XysVeodlejJVptC7/4Mw4XmX2nBhqxvgtKX8F9rItfDTLPIhvFn3if4uuPHQLn4N33KbUZ44
MgYnlDwhgF6R/cTSy7worVATk8ixcWqR89nAbZBlYstM0+XlkY7Ij3K9LRLwUaxw9xjwFqI9rvEF
V04t+gw3QBcsZ5sMqSpDgaoBB1Z0yJBSqEA0e0FCsHNgU/VYXShW6GQbFkJ0lkfuLh+2pyx7vx/s
lSJdK7yFqMEnksbp5QCWcDpZ3E1DGUwa9zkeeUoNqsZBNZHjA78zKPI88ANSySTTzdPYM3ZfRHXg
DLE8uD+Qh/nRKJSPbzxEYnh9nuHdNvjSY/Ooh3DY6Qz9bQPNd+fJGvlT5veDOLgyuMtX47oHOLCA
ed9sdHjFtYnavjPnhVEAvMk0o/QB6fsejWq99183O5AwxTVZaRiP9MRsHVztTOLOzHVW+optph6C
GEds1iMga/wC78T/NTmMi72mB8it5rIgDScVnGNMghMV9scv3YVb4Bt0BXCRJjG57qyZ8kiezOmA
PEERtSuLewNQiCvf3Y4uOxD/mVWEAKzpRvJ3aWsOXLnhNM9RmRbmkR7DAYWQHOGb0m3VyeBTZCdI
uma1Z+TXjwbxqHijJuqTvRETkLtsjQpZFZ5cQrXZ5kn2R5KqDgbMoFilB5M/SveD+WoHBp/FugQ/
KVl5v6glMvz02VPlS/mo9kKJ0UHQzEOfY225otID/QKEKoSDFBgBxXGtwl9j9RvOcnMGWWTJqONE
pzmrzSqT4gX3KHdnXwSDojVIdpDXs3nkvz8P+zFcpkPO3xRAFI9eMarNSV6eK5Gifb7D6ZSGPXNJ
mMh3Gjy7zdnMyJLIWLNlA7mwWclsbzoL42wCU2xZM4liLOFviMbG6bhH0XS0W8WctVTOu1pAI7eh
legWUfyi2mN6kQyqtoL5mRS3dpNRpkvFGEeZFCurGlpFwa7/ZdreI42KynB/X7NvuGGnFXSl3K7F
kY3dzUcjVhzaeL4Fj7Ayja9Axe9xP4aNyQXjzY3HJ75YzOi/+/uXUT0OEaOkrzv+PeNMwc8UGsoU
mLwGBLfvK/Jyz9AmmnGjucY2uX5h/iwQbIMW80TFtKFz6loE97mHEX3GghqPes4ZCdl+2mQKPlPb
Cqy2uG0L0kBf1Rydvmenrkr/iFQ5dKrxRaTSSQoG3YmC8vaLtdZFQOuaBFzlYdZ9wuKip3aru4AI
j/aF1I5MdzrZj+sOQjtIXtNzqLb4aBudms8yQdfCxlHz/Qz3foeLSH7w0NPozUXnbPKzt6INFC8c
s0dmBl6Ay1kUOjlV7PF8AsaAYtx8cMwHR5//8Y9Fbw2YkmkIxz/96XyE6qiWvqVyvJLamXlqaAd0
T9iw77+hmW5yEi70RrTdABWYfGLIgM1dUxWOQ3upvJvBgvvrs5cg3kawJ3BJTNeRIU+XyX8WFxml
ixaYu+WH3VtclLati6V7ShQrzEV3zHgd1xz3lzBdtn4rv7bIG+Y7ay1/+6nzsoDOWOqu143MidAI
fkyQ14W0KHC0wQhaByi4vn7VsMFpebr+4GVaH6Zk3CVovIyTdLRvrNh3X11X9d2WOHVJTBXHkrQz
SD/didTVyN/nuDsqh7SZv4Gi26hetPwKlarFw9f1Lkg0ouVOC2DHIQ/j+Xs1sguRaruDhCGRTxSs
IDXserKuy4obKbNFTxYMN8iRqVCMccMaleOlXMPP3nS4Ur4mpAK+hkQO/Gkvr0fyPTdm6/prfC4c
5LS+1ZgENdBy0DsDZcPRkzY7ikOYejdo5oE+DwNlYOdG9/CK324ZgE7EjYuLGcbGe0xzOgnrMaH0
TM2NTbaK4iJX1UHGBUE914jsrM5nJEoDLoeUGe9uqzFIf7UX3MkkQAnDL1Xdb6WaS6LXvjryrY7v
OM636jUtrC1qquBDPe3IZPYvKm2AiahI3KRmg2pWnXqzFZjSJ+RtArAz4YcS6rig4BtUNmzuiOdb
TSb7VnirpagBSxoJ3+6TcUE7NN3P9NKbLgnYOC1sftKej5Mezgkyyj7A3g4LB1055Z9o+FeBpF6z
kSG2Tj7Om5ae61k6L6qYSOr/tvCikxz8Dw8PhCNaV03S+KJ773Ha+PGa8K3vl4uUILfhvHC0CWfD
6piHbL0CIcxLX/QguB6/Didbw7oV2HWWvBKXpFScfUioxvRpMDXkvnZR7K6BXan6gtr4OjglwymB
p2YotLWyKjqyah73/n2+FFAQ5oZCy15gGOyfT7ojkKUjxij01AEgXTiqiIy8x0Qka9OepsRF8MEq
cMKSI8svKZglb+L5zLxxhJdi7UC672TaD4zUsol2VJSoL4hrCc4JH3cXLbDxz485rBznWJHB62Ol
HdJ/j0CxjV7LaOwP2fIkbXfWW+McBThvQgiobTKsvXcWQ1rRg8Qio8OrBvg9VRx+079KxdQT7j1o
ZpLjD+DNBDvXKzbSB6DQo1w5U4kvJ+FEAnDsH1lGIYPi6ACbCxusOHnFmxCitHuQcwr+eetThXkR
3Ylb1JnrHPF5Uvw/8/OK8+Wd7OGatv9ifKPwofaLDpk+5sd9KGf+Wu11qziWsd5sIj128fiRcuTg
vqHUwn4tHboZOYs6dFv5ENYO9vcWu4TFI3nS98afVeTCDrWSLIn5dvDfU8XyRIyrG/Ux1X1GxKIs
NSvh6RDjo+bv9fQJGPE6S7xgKTKOmg/V8poWeaUxSry2OvjMvTk7iMWmdWLrz3hqCFQKkxfma5D4
7qHbrkioss9yNQNxCiKch5MdCGa8PHMxeDG+Mo2OoiiboRBjF52yLjZBAorV46E8S1NSWvRqeurB
+6MCxw1VQn5C9xlqVCIkzBoyHsCdKexSAjTHotTM5zzl6pj+5Xgjm1D/gTHtBvH11m1XIIxIACHk
lo9JVWypGgeXHbaR5k9/cVKWxihfUe2JG8Ih/Wvelo5bpjsJgoY56ercu/6bpoJiW6Q807iqCxYr
yA45Z381McvRfgdmVXpXCEP5df0zdKs+v1f6fyDmnAxlNOg7UUo5YGT2GKDlJXx1DH05mDTE9kO4
Dy2JBQBA4j3R21DYslp8Mm5KdczvEzbSh9jR/eMrCiHFsPlwUiIYGPEMmnl290g5XJJlK/a+QNw8
1D0p/3REEV1+iPh9k4hVxJSUreertHzFP1Bwad2KJGsKCJNRwrKb9oZ9K3zPR7lvo8Y6+ud2HDYR
3d9ttFyZ99Rn/ADzjEKliBYzngz8f508iVCr/Y7XvWPDlqVhuJiBwDi6BIhYwjKSLYqdERf2ORVk
Rf5KX4YCtOZ5ym6KwkCXGi3PbdeLAj3sdwo4VyMnm3q95g4rXT7CNbIYA7CFueGZF+sY6R3ppF2A
E59ar412gUGXfbGWNYd3f/vUux59SVcu7gpHSv73M2xc8CehpKq4icDDP3Deqc1egFJEa+XyAExB
YQEPr72GGuScOX7T6E1SVyAnCELPM4I/SIzktYmFrdvN8cgmvgcr5re/ZouGfHVMLRBHfKlWtfWD
4UULKza7aMijo+TudroRzERkCkn/vMB2baX4V0HGVz7EaWmg5j8VazLm4sPkBg+oRYkSw6MKcCQD
O4BoM4uwMM2+0UhEDXaiZjBGvexWkpgMnEZZKc0V1ik5gWdZn/LqijAearjRwCCOEpxNZF35b5XH
pVWAmyojqTQKHk7Wi4h9NVSlO4TwSD8nsA/Q0tCxW4t0rhK8yKNxso4YASUOE89Ng2SJvh5UadAY
PAq2JxNa0gDQxYDOPiAavX38CX3G/mP7PNYmxmTlOchznebm87kNIZKC/Sfa7/UOHZDwTaEBlCpW
A8Z3pwtD5HSEjziHCFlsPD0BZzce7v3gwKw+cZpRNIu/GEVWKZ/Jmwylp9k+nSRcDDcO5PsFFVY8
i/olWdUDfgLDIYF67ECtwjd0hO1kGa1HnzVtVb7HbR+vt3wEE8O+zEPv/Zd6p5wrkXzoGIdOBBBq
1mnaOx7tH/TFySacmSKDVwurJTmCl18vIfsieF9yhAQ0WskDJ01yaVpAtnBz48F8M1GeTIQiaxS8
Sz1rZZvzLlnpj973rwKdbSzz2XeJ/1fZlgJMH3BTxthn6FRfL8rY0IyQG18amkBRUjuOw7WJ4b7P
dcOCKZluklME5/6YNY+moUTgWQ6YC+zat/DxmE8cr1PRiHIPKnyAdLgQ128WDMH1UDhPoBaZ6sbX
XLfDF3t6YHVPn5F2M2XGlmlLOc1VtBeVHgSK+t1f1AfG2rl0I09NBrn4sEdUPQ4OkS1nhIJGq+Op
JLi+hwRZlFvyj53HmTAlLVxl4yDMgH9Uw21DDwxpc9sCDT5NFPLsefenRn+tswitVxxoKKUbImnW
r9bYQjS5w5wsq20eoUQASpkZ8hWbzLZn3sNwvo2ju3MnOdIzjAHWbWZMjdkKv6aUop0KTXMhjJH/
u4XbFNlGwFYvBAhocffiPlxp9tb9Gf4L1vVRogDqb6ABnLLPUEctElHJae8W/hAZseyfsyQ/fXcW
qLFdsC3pT7E1NhPka1AoVZOk8blCs//hcGkQ5HFlvR2FYVuZDoamU6rtUSpRbFbhLPr+TGUVGrRs
QQnZwHw2WtSk/A0r8k4HGnoU1lwNTstL8OcArSOtKotS2aGdmsNqyi/UTLeGy/VbPMaS88l1DGVB
mHbykc8mBbclJxNt+LH+VCCBXMXnDv6Ey29tAWlHq3i3VwGp26LjunqtAdMvLwa+EsvUiaN2lXo6
lTJYYBzlc8TbDC19P3ICsn1xAWMzXz1vxpw8jRIyI1XZ0yQmpnpSVqUItBhTl8KChGcXQB0/qOz7
WbuQhhKldNOVvt9CjF8Q8X/x+/Km6SCGyK8xGP2GlVNhh6ZrwOfFh7KoID5w9g6Kh1szO7gm/Ikm
REFCQgpTklo9ropAKKX6S5vezqAJ+h3UxULIO2QUTYThkk890p1NyfDHKSaNq56JJYshUh17jmcD
Li2uI2PgfSfatFXsP2GydFjP/lkU7R443moeWwqaoYdBKjOGnFHBsFvRVqzCQcmHzdOucWpTPdcQ
am6r0Ju7mAE2n4dclJp7DcSMPdlGnLorTWkD0eBqwAqgvRXLUINEf1crq64bWBeSewNOIy4D/UBE
CRyE8bdfNkAqEtkqshtsOQGBpTgPKI7+tOW6pFA6QB8PL76EiUop9y13mbnpm/Xw+hTqkgMe3QCT
n7TG7GebUcU/uNMLjlLJI/KC+Jz6m3f2ZpJ/VM7neBt8yPLNvtNjApEYjZlqYhMagJbz005J4eHg
7fbsmD8js/RRer4bwiqeBklBbyZau9h7FqDcyR8Wva0/A89irjsQ7JzuetFQKsjMSiOEgJSwfhrC
1x+FAuLs8CNONtwdWLM6yrZ4A+yj9ya7Zg7Iowt559jCaopDTBJa1Z05QFppzIcC/ZeymgXMWFmd
HAM1vTkDIIvKBpENk6/OLhq3c1rrC/DPwU7T9xVA5AD2xBjrAvimcGBw8k8Csm9NzpsweAjeZBXJ
+uUDV8c6CEzKkfEVbcNeXNAms0ipVbgV1kwTNPo1pJmRIKdZNxkaYLH61dS9I45QHcd6IMyDJDQd
zXS4THfnM3+0Jficj/DfmzoQrDabfXGr/QoWTj9LMCwJ69e9QAgbu2t3L58CiaZE/p2igTDyzGT9
a07MF4aiArvN85iZv5axcjffa/zjIA/cpAqhjmhls5cb8D/sPxNxnLZO/BXdEGk/CvGM3QYJyhFk
L5s3SOOejbVtMaTaiB4+I66IAjCPc264oqN7j+TFu990mXXvmDNNgrGZzoDiW/AKSJKWCYunsOy7
dLI7VWzPZQWKOPD7WVJ+9TfASTOkT+EKE1nAiO2PwJVeDJPMlvWJo6YRv98P5xtL2YiUbbzTto1x
zGSps9LUEoBdksWdWJ53gNwi8ZOMSgOxQky7bnxNkZTUIyoyg6OWNQ7FALsy9CgToy5+WMnS+uV1
ESJx0j48JTDImcVwi/T1EKE6oNhBD4TFZixOEGtbYmzHUG133pS7ga0Nvd0UQUVfVR038bhd3ovy
dRlMIbH70X13Oh4jgdHib+C8ocoVvNvWjaOtmmM5Ou7NLzT4/FapxnumLKTL0Qv2LKZ4s3go5PXO
LiE6Rwe/cSNyXjc0XiElfLyN6/IA/naJiM43KeOXcSAMu0Sui19Lh9KqUxwpp9EChXQi6HBKJ7t5
Z2+9LCjbHRH8RW634IX2bUHoZyyk8h5weU5zCgXoZFsw7t/7Rf/8TLgDPonUaftwcHRX8smRWtw2
lxxUqdK4zmwrHduN1m7+FQGzykbVwY/pITm0lx5YUGBovOo50Q0jV4RJ8dUpDXoWt2pssVpMali8
3jCZStLjl+aHFIK1UTsVqqcy9doSHBUvFtLobl+C/dnD+CxjRrN8VvRA0bi/gSAoPWdHCpuY70Od
LM004Imoo3nayNDFq3w8hhHlurYr7ScMdQ0TzWDjtQxHai9JjoZfkhVihlDCIulRGDjtZ7+eFuOV
SNBnptTWxza7YxFt2XOipofx1LicB9e9GRGbYgOU/gv6i/9KDkyUOg1n63LxzaS9bdptfgvGEDrI
1tzaiWQ2hTZXnNWgPDcfvhDva3oemPQPg9vPWBHmWEZVddTqhxdmQROqEE//aE6eAtbSaq0q3xRy
k+LafYegYhJ4pnIUqLdA9udiMhrME0pBmlSbscv7CTW7DjaxTjhkova2CbrZEKUnVzfXdcJysRxU
rwrgXjLfsAWCaVQgsVgYJfDOp8vsl7EnGA2NsmEGViEUCIczEBLT3GIw+alm5QK0M9oIHhEHE1uO
SHlfRj4XOGBhI2VnX9o8bcYrAATWdBgOaZg5DK8Ro7+/Jed5HQv1zL9vpgC/iz6np8xDboEjVwkg
s/L3iSo3qaHfbsZkn7jK8zifwro7Gq3uLlBjIq843kRgwGU43yeP17hH5zxHikXX0SowVjm1p8Wt
iOYI4C8b5v/401pASEsPzhGIVE1aqkDHYb41yDBAz2KLTARY3r/60a3vNInK75Ox5Q1CdViic/Qz
vLe5Zd03wKqyNyNWd+DiV8BmSZW1hFz376ixbdHhoKerQwe7fBYj3iFMUnmA9K5m7gYbOfS4U7aI
a/aRH5vzxGOufZSKyazHpQRckV7+hJIshtDMBbA7BhRznSS9dYYSL1mUQeh8GeBCaT6g6e3TsNpr
KEvIJe9Y+8qyEQmAfd/ggbr01SaE2fMgmLyf5bL9HWs2nKdGI9q3LQJyZlwiljXqDp9KeFrSfIrW
0tu8hOnjeTNm/b48/gyJ5bQh2+kcZjH+Y84ZG58wAhMq0Gn47nGnxWwebnaW7WnaDdDlNruazVgX
FP0pHphBU1ECmvktGmhX67ODylI9mfa4FMz8ExA1meRVPve9qyCga16OmvFkbDvbnOteRiPSp/ns
4Mlu9Z6wxPgkIw28z1m/58QlK2+GjWhVL393cWdphwUf0rbJuhLVVW5HZy3XvRUFseTm2K/bSAPb
ZszA2IxqseTurbn/YUyf3VW9dOUdL1zBvUiqX3xgR5nD/jrFzKQ8WRTxcXJb/arxGGV/gpauh5hv
qFIBcW5b1wr5WSXIy7W7ttdBnx/bn/jhEUPBlLijBoM18NaF2ngLGZbfwJqFKJNWtIC7qqHxCggZ
bRE/HuntWIBLkPpL/B4MA8YcdMuB8nMISIHVRnRtjWAYF9RJfnQ7SuhPUYBnbIqfJOKvXa+Mafqs
+5NqUJ3f/hK3Bnip65opuhCrBo+vzW8Zlr0u5oa4alhHII5VXGf561AhZthij33XUWjMR5OgBc++
wn5VqifbDJS9KhrOoqTRyyMHo9Yz3ni9VA8x8tlsA7aaTTYZrg1VSmP3S9yQnn3Br2WzxxKJaNEo
rnWMMICHQPKcRh6UEVXZ68u1Ph595kiO9uxtnKaitX3P/xhNc7zxjyTLTRSepTPc/HrBuUy4XPJd
54gFL4zDvdJ8HWqTLnVuCRrl4IFqDCgBK013JNvcAzoov/H81hvUf5k3gZjO/RRPVL1zfeIyU+r+
2AbrwYrtZ6GvjV/IyaG7O9HzU9xw+Q/NzRtqfpOTzEnKJWxvBBOYdcAKH41Ho1g5cOkPPRPdJWz4
vof3JrDUHjnj30aFPhjb/YaxJCdj8dFwFm/aubpSeOo84wJi1APc9AOXH2Z7p26Ag/69z7vLJWL+
nWQMNXitmkwK5AXNOZflD5u1I9fLrAU61X/pVmxe0kyrXxPGtOviIiVoQV+Lzq/sxD8zT2zQa3De
iADIMu/o4g3oP3AhjFMe0+vid5HnIWrv9+dYLKqAEggov3J6IYUsbXlzARLJH+pyWMKKXjyOiubT
CM/haROF1DEmphP9pbvhatKqRXgcdM+pGXR6sA4DfoKsAGMj70ST7QONTHXmXWPQt8SxDtODVEfb
Mm9UPNBIZ8CSwNfy0GM09/SenNXxrHHNUfk7+1ifAud2bRRdHKnW6fgYdFKDg3TdUzLwZa4k/W0v
Zy5/mGYnt3ccMiWXj407kaFNNZeRoIMiywRmZ4uLWIbpHPYxgj1BZisQvMcwCkSBNN3m4pgvx+s0
V7+aNIRJKk4eujmt4SUhSdZj1+niphZ6nCSyDF/aZ0LoFW0G03rKrUTPRZLmX0iME61AS8sWrQqT
9ZLW2vumLsoknn1Lvo+pqQ1ZLzkTdkC/HiDDpBFUJH2wW8Lf7M38MGknDpWApUJ36UH/SQ5j4fE5
80jB0P4/FaAlhMHlukXZUJjP3tlBKQ7Cl3eTlr61yA64joZfFDvLSbxEit3A5Z2iNUsSxINekSqR
InQuQr4h2DEZD0Crct9SYMSBAzNhZNf1N070hSQlTeuqcpXjGZtBxYx1L4C8qsuhFIfC6ghHyZcH
0jSM12gRmgmXXShiWKBTk0lONJClUaxRBYKEG+DF92aW9ZIg7RLzqClSVNGQJyItBUyBYy7ctUTa
a+EEsRPbL/2i3yf5be8DR+90QBhFFG4dU9YEEood0YOWJQnQBwaGS75JXg0TSy6Hsn6JKllN6eKJ
qavxgWZIVCPVg7twhwAUR/Sy2pqRyHZpvaH3MDvcazd676th21ePONmlvB3S2U2JoshSGG3xUHJX
NG1WNHS9TrgZyVVjLnOIze38HMS0Pv96euTNq1yRadm1h3nzwv1mGWiMhqA21FgwLDuqweGakp0b
l7SeJkCMUf3NTr1B1Ij/i6ytBl54tWeEasDQD7smrvFDfSSGEgheLJoQWJ8k5Ys9ks1o96u/AUsI
SxPKnp9j33G+esimkj1i5RGjdMJNmcV+69tBPkceYOoyqDAFvFh3CM0mZBGED6AzyLLs+tW1cfWv
hOSh/9wj3Z+8pIO0t5rEUftxRilR9useJKX3bYUKySuMJK8OW+i/Zi9ON4fzqpdDRRPlO0gXCNQE
PkStwvthtE4R9o/1E7bvtJlgQtx5N+s9tc4I3EvGGtUBoE72DEHpTDhx/Q1rgGeHri/OxV4LicOu
xJLyxUvIHjusCD+23rkMqIosMEmTvUyDW1Deo1VV16BfZeYgO+Wcyi8xly6GsbpK446XAuWlzl1R
O0DqbKLFYqRzSdv8jnkw0aRSoX2BR5R6fMDPeDgfCIeCt1JRFuluArXg3kG+Q0XD14BEWLYrZXbo
7ZFNWsb6U+oYHjw02KX5veA3UsYHU41FjO9kMsWLzG9R5Ep82yJoL3vWWVkmBMHBxqyntBQ0/zfv
JxZx1BwZX7LhBmCBOcGlvj1JrnicvHLdiSpbLj9tPnobQymzm3rzjVNzq2my+PT5XXNgSoACaPpg
euhoQOLTMtT7IJ+2Vn6xp3J6TvvWlMHCekEifvAVL07nk1AWpcTwgKzOw+SYeKUWcbqN4nJh+7BW
RhL4HCcFJdfZZNCBDg458bJfAdGNVDf4ZQtVtYmT4DFmKWj/B8Kw1rObzhz3GH/wKXMGB6dVLb+c
fKq7xxwEvvnwlbhVEz8Qe6455pzsJqd/2gNsp7prVFYYXzq3wwRP+PMlCWTSXoCLqYNUWS53zbLO
uYQ4BhjTgfRruHCNZ/fcYT7HVK4yAWNdqTcQvWdGWln9FasgzDNedhYd8bCHhChzkZp6dauLqaeO
HJWRy+TM1aCoEzh0G2iWk1/7xo3hFaduLiMMIB49zJs+GyAUEBUM3hU+ggvg1M+mL6FwmMxFD/tN
BfcEuvvroqWyP6zuaNMUJYMDumf9FUCq5TYXQvmUCTn2kO9tO5Y60/O0rINNRmZSmVFXx1vYHfxO
SBZDoTPdBGzKxlIccfVt4x9rjTQbNdCuyGWnspKRQaChAAeIZV/xYzGXoxzGuC0JJ+tqWfvFkdlD
jbVZgFheXunBcFGoGHdsnmZS7H6cTPuEDiSkjPns23remFnKeCLUNF/tb8FnQ3T1aNNLXBMKhHzf
wg3EAl74fOEcbgrNR7VmVMRWldClhRtkqaa9iKj47xeKDng2zYLnlyBR7J931dK5d202cddJj9x+
CL9RHwc3snjlo62YU2z0R7Ev5CYT6URXwhtuO/1cCE7LL1X5vzbS4W38mk1rQ3yBYvSDDvBx0Rbu
QJKaJVJM7GgHhbmgGiP5xA1Al1eZRuEC3ylPFHn2RsBcYJrPnu8O3rP0crFqB+jnCnNgsjSsS1Il
nRvAjcE7ygvz4onvQ+NX53+JbQ6MogT4FIrhLDxIyrG9u2goO4XwuZ4nL/we96VBHz3hL+wo4SJt
Q1lAnrH8ZNdYdGnWfxHEXf8ixg9mD/iTfG1ZIa8AtCP0tPl7A+3OjkxIFibQGzwuYxTeV2NTC5R1
K/KP31Wb5EbeYG83CpF++ToGD3C8WnewnJSW0TPS+8xjkvpeoQzEcNInv9pfxw9qaPBHq01XMNX1
2JZx4YX8LEzSDDqAZSHtJ5Y+x8iBcAndOZwdPAHqGUVVzPMa+QQJyf0p72B0D86yU/ZV8UOOtEsA
dOGdII+DJ2vnCx9TWB13zGhATyqX6rhResH/0+iVyfi+MWwRaU7CeSDDHuvAaHEipkXWNJOiiPt5
QjlGabOChX6FDxhqoU0AxGBWOqtkaVjc5fsDr08QlAYnM86P/uF9LRBUwWsrtBxjQPAIn7Blbgsg
gmY2jdfmVw4ojMKSyq0cEhTOBFezIcS8Rm2HjOIRn2OzMOCmKOdjCDojVUrsskljUL97Q1BiRPTJ
VdjZAnpgJhwUhLePLU5p4upoq3gI4gottlF3QUsB74SplNFyjn7ECLvxdglxI3J2xIbwhWK36JNY
pwziMh8apV1bBQq8RjHEeF0cr65mY+RRecM25YeWolKicuwF8r42cRPCBhfrcydh952cxjZCcBBu
jIHv7dAdE67NTxe987aMQEawg3Vyo5jhIgn+4ADBYmwgB5F7cr/AVDdtkC8Kh0W6h2cnDUkjXwnx
Jsk8kEWM129G4nzNHZeCDjIOkhOhSxcmR/9UFATi8ug2mZl6fwsEwTnqdnyvgV10ziKQetGsSoWa
CfxBkwaIlze4jd7yDnyS94bxToFZ8dp6yTeHkgluEyRj1R/yqDfO6m7rDVbPsVCfdkBGaund5u2B
gJGBzMMNoNNt0xYORRWDLq/HS+Ic/fXRJdAisdKoXbOkH0WPSXAkuH7PqBRfDlrRFTf3B+TLfmNU
P+rPK7ZA2760urCwh6VR+Y777NrD4c/9ynRIQPi0Rql8zwMjjOKOxlvovpJDUpSLZ+sVLJyi6aua
UUyzZ3tN4u96ccVcHRXaj02jHuWZCg6JwpvkVXPUk04v8nr6jQGVhvs2YHTkdS4/gYeC/KdbB+6I
1LIfR+Eh2AjTsUGYWCzaeRS4p7QmzYdeiO+G7+i0RitC20ZNiyaDY0xV2gxvbIlOhjWL0whtiTYb
kYGcIQKM0sKPV2Xd+BVKmetei9gmvBeW1rl81rV0Y7E1rt9VjdnuYkBqgGFAVoZhNh/Wm4HgwMwj
WzEYwK3NOi8IG5VLVX+ZBT5lZa1X6ytKve97y3+cu0cR6cz3e4GvWmwBtCzcwrRjp6MaHf5hexvr
TfoVRnGjmmtuvI5cXrcUiyY1gN7wD2jKa/r/2uOqXRTZB9V8a6j2gD1mlLMzuLOkh9Ws2o6iCf1R
Ld4xRxveyyiS3nEa1TpusEJGpgXGMcx4FSQO4oYPpoInxwFv1MDHhmaDPOdX9vtKPBWZFNo6Zh8J
I2oB4KlsBJ0oEsajbnMZeY6fyTPKsxkHMhm1gfOy7fd3sLdbXdaDhG+NphPJuaRXXFNtyM+LgkqW
LMD+jhuboO7oh34ffsK/DbueyhPsY/KIYmHgiUJOhHnJFc0I2vy8D5h4n9qxRrX1zsD16bIb/Q4o
uO4o+5OzBBwReA6D7oqC9z55x2iYA10ijtkB9gsTE6XkV2OeCD2fcEJKpN2TA4C/SzXEAyzM43J6
CFV1gmtTKTnXaaKZzsKmr+xtCpWPwZf1PBPALBj63P7jqEVXZoVTPkR4IpX5gnSuKl24fqYQXcBM
7ZIUYlY9a6NviAlsp7k8DyRi7hjZ9MMBmeBSFav4pIWlvGng7ozrUna6G6uIzdrbVzvW0HqVKCwJ
MMErrEEEsGkKsfEpRVjbJcE1n9Whwb7imDFKGYQ05iRPJtfmzct4DMaKEUyFel2b26YDuFDnLixa
/aOE/nPItclb2O6nkUzeNnjf2Vw2HB/G3FYsYSsJryZHgD7v2Shf8279km1MSOUqwHdjwXATXPje
z2YU68ux7Te8ir6bVpmx8y7V6VHw4P0faVeGZGNb3ub08rV99AwON52MkerevICsCdUPJVj4MuPo
TPnGRTLxp3PRBoMjW+1WAPdq38JpeIJNUDX4jU2XP0tGK6W9Ci1BvTB8iv0nuQ/epLHJBz4jvOUV
qhOoT0l8/yZKkmECe3LVc99qys7Qlh7xAk+67Oj39lnSV46gskxeiqEG08EaaduKWVUuitz37jrh
v/a70ST3FAR+6VJ0VbZiKkPaCYijrXxca6uLHfga/urVGh48/nABU8KRpTWRR1VUOuT2Oiy/exUR
yY8/uo9SgkYKTj+8PApdUPYScHU0ymYvpcBY57/nBH7orurt9DhfgdtSkTertqmGGdOW5yxcBF47
xAI+7AcgD9lQBiebDHabTbrgW2/qEWzS/1Rw5StxDFuLM2uIFyPykitW1GQeSdAIRUeOLx6mHZqB
MbBKVmW90HaoYmElug/YQwwb/Hq2PiuUTi8nYiKcsyCpPmLvXuDJtkolEzYug5Z+h7V9aU8nw1h0
NcRykqcwmq6LMbAsieq70kupiPgxw0YvKamGZL2IQyGCzEUePlizk4U1cutPrsxz/H7kWsxh0TEH
JVQizBVOip0j3nmcOjabVd/i8UHvHIrYiWBrXts+LYbeB7ZcBKTP5CU/eJsG8PkqNvui93ZMUVmi
iVTVHgYOeF7pYeI+jVJTnB/mHz5sx8NCsa4jmHSSRWlfSYcQVYwMZ8mwCDQ0fU0/gJaiXvHJnUrO
4JohQNz+pQgStZRafQcDeAEpwpkuV8mLWQ1vKVgWf6E=
`protect end_protected
| bsd-2-clause | 63eb2ef0a7f5ba19feea4dfb5d53db6e | 0.947393 | 1.841401 | false | false | false | false |
Yarr/Yarr-fw | syn/kintex7/app_pkg.vhd | 1 | 33,391 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/11/2017 10:26:23 AM
-- Design Name:
-- Module Name: app_package - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work;
use work.board_pkg.all;
package app_pkg is
--constant c_TX_CHANNELS : integer := 8;
--constant c_RX_CHANNELS : integer := 8;
component simple_counter is
Port (
enable_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
clk_i : in STD_LOGIC;
count_o : out STD_LOGIC_VECTOR (28 downto 0);
gray_count_o : out STD_LOGIC_VECTOR (28 downto 0)
);
end component;
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- _clk_640___640.000______0.000______50.0______468.793____919.522
-- _clk_160___160.000______0.000______50.0______568.382____919.522
-- __clk_80____80.000______0.000______50.0______625.965____919.522
-- __clk_40____40.000______0.000______50.0______689.448____919.522
-- clk_40_90____40.000_____90.000______50.0______689.448____919.522
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_____________250____________0.010
component clk_gen
port
(-- Clock in ports
clk_250_in : in std_logic;
-- Clock out ports
clk_300 : out std_logic;
clk_640 : out std_logic;
clk_160 : out std_logic;
clk_80 : out std_logic;
clk_40 : out std_logic;
clk_40_90 : out std_logic;
clk_250 : out std_logic;
-- Status and control signals
reset : in std_logic;
locked : out std_logic
);
end component;
--//----------------------------------------------------------------------------
--// Output Output Phase Duty Cycle Pk-to-Pk Phase
--// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
--//----------------------------------------------------------------------------
--// __clk_40____40.000______0.000______50.0______161.245____154.081
--// __clk_80____80.000______0.000______50.0______143.262____154.081
--// _clk_160___160.000______0.000______50.0______128.042____154.081
--// _clk_320___320.000______0.000______50.0______114.518____154.081
--// _clk_640___640.000______0.000______50.0______102.510____154.081
--// _clk_300___320.000______0.000______50.0______114.518____154.081
--// _clk_250___256.000______0.000______50.0______118.698____154.081
--//
--//----------------------------------------------------------------------------
--// Input Clock Freq (MHz) Input Jitter (UI)
--//----------------------------------------------------------------------------
--// __primary_________200.000____________0.010
component clk_200_gen
port
(-- Clock in ports
clk_200_in : in std_logic;
-- Clock out ports
clk_40 : out std_logic;
clk_80 : out std_logic;
clk_160 : out std_logic;
clk_320 : out std_logic;
clk_640 : out std_logic;
clk_300 : out std_logic;
clk_250 : out std_logic;
-- Status and control signals
resetn : in std_logic;
locked : out std_logic
);
end component;
COMPONENT axis_data_fifo_0
PORT (
s_axis_aresetn : IN STD_LOGIC;
s_axis_aclk : IN STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tuser : IN STD_LOGIC_VECTOR(21 DOWNTO 0);
m_axis_aclk : IN STD_LOGIC;
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tuser : OUT STD_LOGIC_VECTOR(21 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT axis_data_fifo_1
PORT (
s_axis_aresetn : IN STD_LOGIC;
s_axis_aclk : IN STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_aclk : IN STD_LOGIC;
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
component synchronizer is
port (
-- Sys connect
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Async input
async_in : in std_logic;
sync_out : out std_logic
);
end component;
component wshexp_core is
Generic(
AXI_BUS_WIDTH : integer := 64
);
Port (
clk_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
--sys_clk_n_i : IN STD_LOGIC;
--sys_clk_p_i : IN STD_LOGIC;
rst_i : in STD_LOGIC;
--user_lnk_up_i : in STD_LOGIC;
--user_app_rdy_i : in STD_LOGIC;
---------------------------------------------------------
-- AXI-Stream bus
m_axis_tx_tready_i : in STD_LOGIC;
m_axis_tx_tdata_o : out STD_LOGIC_VECTOR(AXI_BUS_WIDTH-1 DOWNTO 0);
m_axis_tx_tkeep_o : out STD_LOGIC_VECTOR(AXI_BUS_WIDTH/8-1 DOWNTO 0);
m_axis_tx_tlast_o : out STD_LOGIC;
m_axis_tx_tvalid_o : out STD_LOGIC;
m_axis_tx_tuser_o : out STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_rx_tdata_i : in STD_LOGIC_VECTOR(AXI_BUS_WIDTH-1 DOWNTO 0);
s_axis_rx_tkeep_i : in STD_LOGIC_VECTOR(AXI_BUS_WIDTH/8-1 DOWNTO 0);
s_axis_rx_tlast_i : in STD_LOGIC;
s_axis_rx_tvalid_i : in STD_LOGIC;
s_axis_rx_tready_o : out STD_LOGIC;
s_axis_rx_tuser_i : in STD_LOGIC_VECTOR(21 DOWNTO 0);
---------------------------------------------------------
-- DMA wishbone interface (master pipelined)
dma_adr_o : out std_logic_vector(31 downto 0); -- Adress
dma_dat_o : out std_logic_vector(63 downto 0); -- Data out
dma_dat_i : in std_logic_vector(63 downto 0); -- Data in
dma_sel_o : out std_logic_vector(7 downto 0); -- Byte select
dma_cyc_o : out std_logic; -- Read or write cycle
dma_stb_o : out std_logic; -- Read or write strobe
dma_we_o : out std_logic; -- Write
dma_ack_i : in std_logic; -- Acknowledge
dma_stall_i : in std_logic; -- for pipelined Wishbone
---------------------------------------------------------
-- CSR wishbone interface (master classic)
csr_adr_o : out std_logic_vector(31 downto 0);
csr_dat_o : out std_logic_vector(31 downto 0);
csr_sel_o : out std_logic_vector(3 downto 0);
csr_stb_o : out std_logic;
csr_we_o : out std_logic;
csr_cyc_o : out std_logic;
csr_dat_i : in std_logic_vector(31 downto 0);
csr_ack_i : in std_logic;
csr_stall_i : in std_logic;
csr_err_i : in std_logic;
csr_rty_i : in std_logic; -- not used internally
csr_int_i : in std_logic; -- not used internally
---------------------------------------------------------
-- DMA registers wishbone interface (slave classic)
dma_reg_adr_i : in std_logic_vector(31 downto 0);
dma_reg_dat_i : in std_logic_vector(31 downto 0);
dma_reg_sel_i : in std_logic_vector(3 downto 0);
dma_reg_stb_i : in std_logic;
dma_reg_we_i : in std_logic;
dma_reg_cyc_i : in std_logic;
dma_reg_dat_o : out std_logic_vector(31 downto 0);
dma_reg_ack_o : out std_logic;
dma_reg_stall_o : out std_logic;
---------------------------------------------------------
-- PCIe interrupt config
cfg_interrupt_o : out STD_LOGIC;
cfg_interrupt_rdy_i : in STD_LOGIC;
cfg_interrupt_assert_o : out STD_LOGIC;
cfg_interrupt_di_o : out STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_interrupt_do_i : in STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_interrupt_mmenable_i : in STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_interrupt_msienable_i : in STD_LOGIC;
cfg_interrupt_msixenable_i : in STD_LOGIC;
cfg_interrupt_msixfm_i : in STD_LOGIC;
cfg_interrupt_stat_o : out STD_LOGIC;
cfg_pciecap_interrupt_msgnum_o : out STD_LOGIC_VECTOR(4 DOWNTO 0);
---------------------------------------------------------
-- PCIe ID
cfg_bus_number_i : in STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_device_number_i : in STD_LOGIC_VECTOR(4 DOWNTO 0);
cfg_function_number_i : in STD_LOGIC_VECTOR(2 DOWNTO 0)
);
end component;
component k_bram is
generic (
constant ADDR_WIDTH : integer := 9+4;
constant DATA_WIDTH : integer := 64
);
Port (
-- SYS CON
clk : in std_logic;
rst : in std_logic;
-- Wishbone Slave in
wb_adr_i : in std_logic_vector(9+4-1 downto 0);
wb_dat_i : in std_logic_vector(64-1 downto 0);
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_lock_i : in std_logic; -- nyi
-- Wishbone Slave out
wb_dat_o : out std_logic_vector(64-1 downto 0);
wb_ack_o : out std_logic
);
end component;
component k_dual_bram is
Port (
-- SYS CON
clk_i : in std_logic;
rst_i : in std_logic;
-- Wishbone Slave in
wba_adr_i : in std_logic_vector(32-1 downto 0);
wba_dat_i : in std_logic_vector(64-1 downto 0);
wba_we_i : in std_logic;
wba_stb_i : in std_logic;
wba_cyc_i : in std_logic;
-- Wishbone Slave out
wba_dat_o : out std_logic_vector(64-1 downto 0);
wba_ack_o : out std_logic;
-- Wishbone Slave in
wbb_adr_i : in std_logic_vector(32-1 downto 0);
wbb_dat_i : in std_logic_vector(64-1 downto 0);
wbb_we_i : in std_logic;
wbb_stb_i : in std_logic;
wbb_cyc_i : in std_logic;
-- Wishbone Slave out
wbb_dat_o : out std_logic_vector(64-1 downto 0);
wbb_ack_o : out std_logic
);
end component;
component wb_addr_decoder is
generic
(
g_WINDOW_SIZE : integer := 18; -- Number of bits to address periph on the board (32-bit word address)
g_WB_SLAVES_NB : integer := 2
);
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- wishbone master interface
wbm_adr_i : in std_logic_vector(31 downto 0); -- Address
wbm_dat_i : in std_logic_vector(31 downto 0); -- Data out
wbm_sel_i : in std_logic_vector(3 downto 0); -- Byte select
wbm_stb_i : in std_logic; -- Strobe
wbm_we_i : in std_logic; -- Write
wbm_cyc_i : in std_logic; -- Cycle
wbm_dat_o : out std_logic_vector(31 downto 0); -- Data in
wbm_ack_o : out std_logic; -- Acknowledge
wbm_stall_o : out std_logic; -- Stall
---------------------------------------------------------
-- wishbone slaves interface
wb_adr_o : out std_logic_vector(31 downto 0); -- Address
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic; -- Strobe
wb_we_o : out std_logic; -- Write
wb_cyc_o : out std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Cycle
wb_dat_i : in std_logic_vector((32*g_WB_SLAVES_NB)-1 downto 0); -- Data in
wb_ack_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Acknowledge
wb_stall_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0) -- Stall
);
end component;
component ctrl_regs is
port (
-- Sys connect
wb_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Register Outputs R/W
ctrl_reg_0_o : out std_logic_vector(31 downto 0);
ctrl_reg_1_o : out std_logic_vector(31 downto 0);
ctrl_reg_2_o : out std_logic_vector(31 downto 0);
ctrl_reg_3_o : out std_logic_vector(31 downto 0);
ctrl_reg_4_o : out std_logic_vector(31 downto 0);
ctrl_reg_5_o : out std_logic_vector(31 downto 0);
-- Static registers RO
static_reg_0_o : out std_logic_vector(31 downto 0);
static_reg_1_o : out std_logic_vector(31 downto 0);
static_reg_2_o : out std_logic_vector(31 downto 0);
static_reg_3_o : out std_logic_vector(31 downto 0)
);
end component;
component mig_7series_0
port (
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(14 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
app_addr : in std_logic_vector(28 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(511 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(63 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(511 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
-- System Clock Ports
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_rst : in std_logic
);
end component mig_7series_0;
component ddr3_ctrl_wb
generic(
g_BYTE_ADDR_WIDTH : integer := 29;
g_MASK_SIZE : integer := 8;
g_DATA_PORT_SIZE : integer := 64
);
port(
----------------------------------------------------------------------------
-- Reset input (active low)
----------------------------------------------------------------------------
rst_n_i : in std_logic;
----------------------------------------------------------------------------
-- Status
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- DDR controller port
----------------------------------------------------------------------------
ddr_addr_o : out std_logic_vector(28 downto 0);
ddr_cmd_o : out std_logic_vector(2 downto 0);
ddr_cmd_en_o : out std_logic;
ddr_wdf_data_o : out std_logic_vector(511 downto 0);
ddr_wdf_end_o : out std_logic;
ddr_wdf_mask_o : out std_logic_vector(63 downto 0);
ddr_wdf_wren_o : out std_logic;
ddr_rd_data_i : in std_logic_vector(511 downto 0);
ddr_rd_data_end_i : in std_logic;
ddr_rd_data_valid_i : in std_logic;
ddr_rdy_i : in std_logic;
ddr_wdf_rdy_i : in std_logic;
ddr_sr_req_o : out std_logic;
ddr_ref_req_o : out std_logic;
ddr_zq_req_o : out std_logic;
ddr_sr_active_i : in std_logic;
ddr_ref_ack_i : in std_logic;
ddr_zq_ack_i : in std_logic;
ddr_ui_clk_i : in std_logic;
ddr_ui_clk_sync_rst_i : in std_logic;
ddr_init_calib_complete_i : in std_logic;
----------------------------------------------------------------------------
-- Wishbone bus port
----------------------------------------------------------------------------
wb_clk_i : in std_logic;
wb_sel_i : in std_logic_vector(g_MASK_SIZE - 1 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_addr_i : in std_logic_vector(31 downto 0);
wb_data_i : in std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
wb_data_o : out std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
----------------------------------------------------------------------------
-- Wishbone bus port
----------------------------------------------------------------------------
wb1_sel_i : in std_logic_vector(g_MASK_SIZE - 1 downto 0);
wb1_cyc_i : in std_logic;
wb1_stb_i : in std_logic;
wb1_we_i : in std_logic;
wb1_addr_i : in std_logic_vector(32 - 1 downto 0);
wb1_data_i : in std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
wb1_data_o : out std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
wb1_ack_o : out std_logic;
wb1_stall_o : out std_logic;
----------------------------------------------------------------------------
-- Debug ports
----------------------------------------------------------------------------
ddr_wb_rd_mask_dout_do : out std_logic_vector(7 downto 0);
ddr_wb_rd_mask_addr_dout_do : out std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
ddr_rd_mask_rd_data_count_do : out std_logic_vector(3 downto 0);
ddr_rd_data_rd_data_count_do : out std_logic_vector(3 downto 0);
ddr_rd_fifo_full_do : out std_logic_vector(1 downto 0);
ddr_rd_fifo_empty_do : out std_logic_vector(1 downto 0);
ddr_rd_fifo_rd_do : out std_logic_vector(1 downto 0)
);
end component ddr3_ctrl_wb;
component wb_tx_core
generic (
g_NUM_TX : integer range 1 to 32 := c_TX_CHANNELS
);
port (
-- Sys connect
wb_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- TX
tx_clk_i : in std_logic;
tx_data_o : out std_logic_vector(g_NUM_TX-1 downto 0);
trig_pulse_o : out std_logic;
-- TRIGGER
ext_trig_i : in std_logic
);
end component;
component wb_rx_core
generic (
g_NUM_RX : integer range 1 to 32 := c_RX_CHANNELS;
g_TYPE : string := c_FE_TYPE;
g_NUM_LANES : integer range 1 to 4 := c_RX_NUM_LANES
);
port (
-- Sys connect
wb_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- RX IN
rx_clk_i : in std_logic;
rx_serdes_clk_i : in std_logic;
rx_data_i_p : in std_logic_vector((g_NUM_RX*g_NUM_LANES)-1 downto 0);
rx_data_i_n : in std_logic_vector((g_NUM_RX*g_NUM_LANES)-1 downto 0);
trig_tag_i : in std_logic_vector(31 downto 0);
-- RX OUT (sync to sys_clk)
rx_valid_o : out std_logic;
rx_data_o : out std_logic_vector(63 downto 0);
busy_o : out std_logic;
debug_o : out std_logic_vector(31 downto 0)
);
end component;
component wb_rx_bridge is
port (
-- Sys Connect
sys_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Wishbone DMA Master Interface
dma_clk_i : in std_logic;
dma_adr_o : out std_logic_vector(31 downto 0);
dma_dat_o : out std_logic_vector(63 downto 0);
dma_dat_i : in std_logic_vector(63 downto 0);
dma_cyc_o : out std_logic;
dma_stb_o : out std_logic;
dma_we_o : out std_logic;
dma_ack_i : in std_logic;
dma_stall_i : in std_logic;
-- Rx Interface
rx_data_i : in std_logic_vector(63 downto 0);
rx_valid_i : in std_logic;
-- Status in
trig_pulse_i : in std_logic;
-- Status out
irq_o : out std_logic;
busy_o : out std_logic
);
end component;
component i2c_master_wb_top
port (
wb_clk_i : in std_logic;
wb_rst_i : in std_logic;
arst_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(7 downto 0);
wb_dat_o : out std_logic_vector(7 downto 0);
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_ack_o : out std_logic;
wb_inta_o: out std_logic;
scl : inout std_logic;
sda : inout std_logic
);
end component;
component wb_trigger_logic
port (
-- Sys connect
wb_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
-- To/From outside world
ext_trig_i : in std_logic_vector(3 downto 0);
ext_trig_o : out std_logic;
ext_busy_i : in std_logic;
ext_busy_o : out std_logic;
-- Eudet TLU
eudet_clk_o : out std_logic;
eudet_busy_o : out std_logic;
eudet_trig_i : in std_logic;
eudet_rst_i : in std_logic;
-- To/From inside world
clk_i : in std_logic;
--int_trig_i : in std_logic_vector(3 downto 0);
--int_trig_o : out std_logic;
--int_busy_i : in std_logic;
trig_tag : out std_logic_vector(31 downto 0);
debug_o : out std_logic_vector(31 downto 0)
);
end component;
COMPONENT ila_axis
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe6 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe10 : IN STD_LOGIC_VECTOR(21 DOWNTO 0);
probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe16 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe17 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe20 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe21 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
probe22 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe23 : IN STD_LOGIC_VECTOR(28 DOWNTO 0)
);
END COMPONENT ;
COMPONENT ila_wsh_pipe
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)--;
-- probe9 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-- probe10 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
-- probe11 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
-- probe12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
-- probe13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
-- probe14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
-- probe15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
-- probe16 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
-- probe17 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-- probe18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
-- probe19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
-- probe20 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT ;
COMPONENT ila_ddr
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(511 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe7 : IN STD_LOGIC_VECTOR(511 DOWNTO 0);
probe8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT ;
COMPONENT ila_rx_dma_wb
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe8 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT ;
end app_pkg;
package body app_pkg is
end app_pkg;
| gpl-3.0 | 9a2a2d61d56b33949963b7ce5c6c61df | 0.450061 | 3.743805 | false | false | false | false |
rjarzmik/mips_processor | Caches/DualPort_Cache_tb.vhd | 1 | 5,896 | -------------------------------------------------------------------------------
-- Title : Testbench for design "DualPort_Cache"
-- Project : Source files in two directories, custom library name, VHDL'87
-------------------------------------------------------------------------------
-- File : DualPort_Cache_tb.vhd
-- Author : Robert Jarzmik <[email protected]>
-- Company :
-- Created : 2016-11-19
-- Last update: 2016-11-19
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-11-19 1.0 rj Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity DualPort_Cache_tb is
end entity DualPort_Cache_tb;
-------------------------------------------------------------------------------
architecture passthrough of DualPort_Cache_tb is
-- component generics
constant ADDR_WIDTH : integer := 32;
constant DATA_WIDTH : integer := 32;
-- component ports
signal clk : std_logic := '1';
signal rst : std_logic := '1';
signal i_porta_req : std_logic;
signal i_porta_we : std_logic;
signal i_porta_addr : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal i_porta_write_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal o_porta_read_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal o_porta_valid : std_logic;
signal i_portb_req : std_logic;
signal i_portb_we : std_logic;
signal i_portb_addr : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal i_portb_write_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal o_portb_read_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal o_portb_valid : std_logic;
signal o_memory_req : std_logic;
signal o_memory_we : std_logic;
signal o_memory_addr : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal o_memory_write_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal i_memory_read_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal i_memory_valid : std_logic;
-- memory simulator
type memory is array(0 to 7) of std_logic_vector(DATA_WIDTH - 1 downto 0);
constant rom : memory := (
x"00000000",
x"20050004",
x"00000008",
x"0000000c",
x"00000010",
x"00000014",
x"00000018",
x"0000001c"
);
begin -- architecture passthrough
-- component instantiation
DUT : entity work.DualPort_Cache
generic map (
ADDR_WIDTH => ADDR_WIDTH,
DATA_WIDTH => DATA_WIDTH)
port map (
clk => clk,
rst => rst,
i_porta_req => i_porta_req,
i_porta_we => i_porta_we,
i_porta_addr => i_porta_addr,
i_porta_write_data => i_porta_write_data,
o_porta_read_data => o_porta_read_data,
o_porta_valid => o_porta_valid,
i_portb_req => i_portb_req,
i_portb_we => i_portb_we,
i_portb_addr => i_portb_addr,
i_portb_write_data => i_portb_write_data,
o_portb_read_data => o_portb_read_data,
o_portb_valid => o_portb_valid,
o_memory_req => o_memory_req,
o_memory_we => o_memory_we,
o_memory_addr => o_memory_addr,
o_memory_write_data => o_memory_write_data,
i_memory_read_data => i_memory_read_data,
i_memory_valid => i_memory_valid);
-- reset
rst <= '0' after 24 ps;
-- clock generation
clk <= not clk after 10 ps;
-- waveform generation
WaveGen_Proc : process
variable nb_clk : natural := 0;
begin
-- insert signal assignments here
wait until Clk = '1';
nb_clk := nb_clk + 1;
case nb_clk is
when 2 | 4 | 6 | 8 | 10 | 12 | 14 | 16 | 22 =>
i_porta_we <= '0';
i_porta_addr <= std_logic_vector(to_unsigned(2 * nb_clk, ADDR_WIDTH));
i_porta_req <= '1';
when others =>
i_porta_req <= '0';
i_porta_addr <= (others => 'X');
end case;
end process WaveGen_Proc;
-- memory simulator
--InstantaneousMemorySim : process(clk, rst, o_memory_req)
--begin
-- if rst = '0' and o_memory_req = '1' then
-- if rising_edge(clk) then
-- i_memory_read_data <= rom((to_integer(unsigned(o_memory_addr)) / 4) mod 8);
-- i_memory_valid <= '1';
-- end if;
-- end if;
--end process InstantaneousMemorySim;
-- memory simulator
OneCycleMemorySim : process(clk, rst, o_memory_req)
variable clk_req : natural := 0;
begin
if rst = '0' then
if rising_edge(clk) then
if o_memory_req = '0' then
i_memory_valid <= '0';
i_memory_read_data <= (others => 'X');
end if;
if o_memory_req = '1' then
clk_req := clk_req + 1;
end if;
if clk_req > 0 then
clk_req := 0;
i_memory_read_data <= rom((to_integer(unsigned(o_memory_addr)) / 4) mod 8);
i_memory_valid <= '1';
end if;
end if;
end if;
end process OneCycleMemorySim;
end architecture passthrough;
-------------------------------------------------------------------------------
configuration DualPort_Cache_tb_passthrough_cfg of DualPort_Cache_tb is
for passthrough
end for;
end DualPort_Cache_tb_passthrough_cfg;
-------------------------------------------------------------------------------
| gpl-3.0 | 4bea8db9d601d41df79879d00567fdc6 | 0.499661 | 3.726928 | false | false | false | false |
niketancm/tsea26 | lab2-3/rtl/saturation.vhd | 1 | 1,010 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity saturation is
port (
value_i : in signed(39 downto 0);
do_sat_i : in std_logic;
value_o : out signed(39 downto 0);
did_sat_o : out std_logic);
end saturation;
architecture saturation_rtl of saturation is
begin -- saturation_rtl
sat_logic:process(do_sat_i,value_i)
begin
L1:if(do_sat_i = '0') then
value_o <= value_i;
did_sat_o <= '0';
else
L2:if(value_i(38 downto 31) /= "00000000" and value_i(39) = '0') then --Saturate to Max +ve Value.
value_o <= x"007FFFFFFF";
did_sat_o <= '1';
elsif(value_i(38 downto 31) /= "11111111" and value_i(39) = '1') then --Saturate to max -ve value.
value_o <= x"ff80000000";
did_sat_o <= '1';
else
value_o <= value_i;
did_sat_o <= '0';
end if L2;
end if L1;
end process sat_logic;
end saturation_rtl;
| gpl-2.0 | b2ed6bd29bb080152b3aee57e2f20347 | 0.542574 | 3.117284 | false | false | false | false |
rjarzmik/mips_processor | Caches/mask_feeder_tb.vhd | 1 | 4,188 | -------------------------------------------------------------------------------
-- Title : Testbench for design "mask_feeder"
-- Project : Source files in two directories, custom library name, VHDL'87
-------------------------------------------------------------------------------
-- File : mask_feeder_tb.vhd
-- Author : Robert Jarzmik <[email protected]>
-- Company :
-- Created : 2016-12-21
-- Last update: 2016-12-22
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-12-21 1.0 rj Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity mask_feeder_tb is
end entity mask_feeder_tb;
-------------------------------------------------------------------------------
architecture str of mask_feeder_tb is
-- component generics
constant WIDTH : natural := 8;
-- component ports
signal clk : std_logic := '1';
signal sclr : std_logic;
signal sdata : std_logic_vector(WIDTH - 1 downto 0);
signal bclrena : std_logic;
signal bclr : natural range 0 to WIDTH - 1;
signal fbitset : natural range 0 to WIDTH - 1;
signal allclear : std_logic;
signal dbg_data : std_logic_vector(WIDTH - 1 downto 0);
signal clkena : std_logic := '1';
begin -- architecture str
-- component instantiation
DUT : entity work.mask_feeder
generic map (
WIDTH => WIDTH)
port map (
clk => clk,
sclr => sclr,
sdata => sdata,
bclrena => bclrena,
bclr => bclr,
fbitset => fbitset,
allclear => allclear,
dbg_data => dbg_data);
-- clock generation
clk <= (clkena and not clk) after 5 ps;
clkena <= '0' after 120 ps;
sclr <= '0' after 0 ps, '1' after 10 ps, '0' after 20 ps;
sdata <= x"5e";
bclrena <= '0' after 0 ps, '1' after 20 ps, '0' after 120 ps;
bclr <= 5 after 21 ps, 6 after 31 ps, 7 after 41 ps, 7 after 51 ps,
4 after 60 ps, 3 after 71 ps, 2 after 81 ps, 1 after 91 ps,
0 after 101 ps;
-- waveform generation
WaveGen_Proc : process
begin
wait until Clk = '1';
report "FBitSet=" & integer'image(fbitset) &
", allclear=" & std_logic'image(allclear) &
", bclr=" & integer'image(bclr) &
", dbg_data = " & to_bstring(dbg_data);
end process WaveGen_Proc;
-- asserts
asserter : process
begin
wait until Clk = '1' and NOW = 20 ps;
assert fbitset = 6 severity error;
assert allclear = '0';
wait until Clk = '1'; -- 30 ps;
assert fbitset = 6 severity error;
assert allclear = '0';
wait until Clk = '1'; -- 40 ps
assert fbitset = 6 severity error;
assert allclear = '0';
wait until Clk = '1'; -- 50 ps
assert fbitset = 4 severity error;
assert allclear = '0';
wait until Clk = '1'; -- 60 ps
assert fbitset = 4 severity error;
assert allclear = '0';
wait until Clk = '1'; -- 70 ps
assert fbitset = 3 severity error;
assert allclear = '0';
wait until Clk = '1'; -- 80 ps
assert fbitset = 3 severity error;
assert allclear = '0';
wait until Clk = '1'; -- 90 ps
assert fbitset = 2 severity error;
assert allclear = '0';
wait until Clk = '1'; -- 100 ps
assert fbitset = 1 severity error;
assert allclear = '0';
wait until Clk = '1'; -- 110 ps
assert fbitset = 0 severity error;
assert allclear = '1';
end process asserter;
end architecture str;
-------------------------------------------------------------------------------
configuration mask_feeder_tb_str_cfg of mask_feeder_tb is
for str
end for;
end mask_feeder_tb_str_cfg;
-------------------------------------------------------------------------------
| gpl-3.0 | 8c8b3d03a9ce24fc65bcc7dccfd90982 | 0.483524 | 4.062076 | false | false | false | false |
rjarzmik/mips_processor | Caches/cache_line_streamer_tb.vhd | 1 | 8,968 | -------------------------------------------------------------------------------
-- Title : Testbench for design "cache_line_streamer"
-- Project : Source files in two directories, custom library name, VHDL'87
-------------------------------------------------------------------------------
-- File : cache_line_streamer_tb.vhd
-- Author : Robert Jarzmik <[email protected]>
-- Company :
-- Created : 2016-12-22
-- Last update: 2016-12-26
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-12-22 1.0 rj Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cache_defs.all;
-------------------------------------------------------------------------------
entity cache_line_streamer_tb is
end entity cache_line_streamer_tb;
-------------------------------------------------------------------------------
architecture test of cache_line_streamer_tb is
-- component generics
constant ADDR_WIDTH : natural := 32;
constant DATA_WIDTH : natural := 32;
constant DATAS_PER_LINE_WIDTH : natural := 3;
constant MEMORY_LATENCY : natural := 3;
-- component ports
signal clk : std_logic := '1';
signal rst : std_logic := '1';
signal i_req : cls_op;
signal creq : cache_request_t;
signal cresp : cache_response_t;
signal o_memory_req : std_logic;
signal o_memory_we : std_logic;
signal o_memory_addr : addr_t;
signal i_memory_rdata : data_t;
signal o_memory_wdata : data_t;
signal i_memory_done : std_logic;
-- clock
signal clkena : std_logic := '1';
signal test_refill_done : boolean := false;
function get_ireq_str(req : cls_op) return string is
begin
case req is
when cls_none => return "none";
when cls_refill => return "refill";
when cls_flush => return "flush";
end case;
end function get_ireq_str;
function cline_to_hstring(cline : cache_line_t;
i : natural) return string is
begin
if i = 0 then
return to_hstring(cline(i));
else
return to_hstring(cline(i)) & ":" & cline_to_hstring(cline, i - 1);
end if;
end function cline_to_hstring;
begin -- architecture test
-- component instantiation
DUT : entity work.cache_line_streamer
generic map (
ADDR_WIDTH => ADDR_WIDTH,
DATA_WIDTH => DATA_WIDTH,
DATAS_PER_LINE_WIDTH => DATAS_PER_LINE_WIDTH)
port map (
clk => clk,
rst => rst,
i_creq => creq,
o_cresp => cresp,
o_memory_req => o_memory_req,
o_memory_we => o_memory_we,
o_memory_addr => o_memory_addr,
i_memory_rdata => i_memory_rdata,
o_memory_wdata => o_memory_wdata,
i_memory_done => i_memory_done);
-- memory simulator
Simulated_Memory_1 : entity work.Simulated_Memory
generic map (
ADDR_WIDTH => ADDR_WIDTH,
DATA_WIDTH => DATA_WIDTH,
MEMORY_ADDR_WIDTH => 16,
MEMORY_LATENCY => MEMORY_LATENCY)
port map (
clk => clk,
rst => rst,
i_memory_req => o_memory_req,
i_memory_we => o_memory_we,
i_memory_addr => o_memory_addr,
i_memory_write_data => o_memory_wdata,
o_memory_read_data => i_memory_rdata,
o_memory_valid => i_memory_done);
-- clock generation
rst <= '0' after 12 ps;
clk <= (clkena and not clk) after 5 ps;
clkena <= '0' after 340 ps;
creq.req <= cls_refill after 28 ps,
cls_none after 35 ps,
cls_flush after 198 ps,
cls_none after 207 ps;
creq.addr <= std_logic_vector(to_unsigned(16#0060#, ADDR_WIDTH)) after 21 ps;
creq.sel <= (6 => '1', 4 => '1', 2 => '1', 0 => '1', others => '0');
creq.cline(6) <= x"66666666";
creq.cline(4) <= x"44444444";
creq.cline(2) <= x"22222222";
creq.cline(0) <= x"00000000";
-- waveform generation
WaveGen_Proc : process
begin
wait until Clk = '1';
if not test_refill_done then
report "i_req=" & get_ireq_str(creq.req) &
", cresp.rdy=" & std_logic'image(cresp.rdy) &
", cresp.done=" & std_logic'image(cresp.done) &
", cresp.cline = " & cline_to_hstring(cresp.cline, cresp.cline'length - 1);
else
report "i_req=" & get_ireq_str(creq.req) &
", cresp.rdy=" & std_logic'image(cresp.rdy) &
", cresp.done=" & std_logic'image(cresp.done) &
", o_memory_req=" & std_logic'image(o_memory_req) &
", o_memory_addr=" & to_hstring(o_memory_addr) &
", o_memory_wdata=" & to_hstring(o_memory_wdata) &
", i_memory_done=" & std_logic'image(i_memory_done);
end if;
end process WaveGen_Proc;
refill_watch : process
begin
wait for 1 ps;
-- wait until NOW = 1 ps;
assert cresp.rdy = '0' report "During reset ready must be 0";
wait until rst = '0';
wait until clk = '1';
wait until clk = '1';
assert cresp.rdy = '1' report "after reset ready must be 1";
wait until clk = '1';
assert cresp.rdy = '0' report "after request ready must be 0";
assert cresp.done = '0' report "after request done must be 0";
wait for (MEMORY_LATENCY * 4 + 2) * 10 ps;
assert cresp.rdy = '1' report "after refilling, ready must be 1";
assert cresp.done = '1' report "after refilling, done must be 1";
-- Expected data: 0x160 + idx * 4
assert cresp.cline(6) = x"00000178"
report "Data at index 7 not refilled correctly";
assert cresp.cline(4) = x"00000170"
report "Data at index 4 not refilled correctly";
assert cresp.cline(2) = x"00000168"
report "Data at index 2 not refilled correctly";
assert cresp.cline(0) = x"00000160"
report "Data at index 0 not refilled correctly";
wait until clk = '1';
assert cresp.rdy = '1' report "while idling, ready must be 1";
wait until clk = '1';
assert cresp.rdy = '1' report "while idling, ready must be 1";
test_refill_done <= true;
wait on rst;
end process refill_watch;
flush_watch : process
begin
wait until test_refill_done = true;
wait until clk = '1';
-- wait until NOW = 1 ps;
assert o_memory_req = '1' report "memory request should be asserted";
assert o_memory_addr = x"00000078" report "memory request target address incorrect";
assert o_memory_wdata = x"66666666" report "memory request wrong data sent";
assert cresp.rdy = '0' report "after request ready must be 1";
assert cresp.done = '0' report "after request done must be 0";
wait for MEMORY_LATENCY * 10 ps;
assert cresp.rdy = '0' report "after request ready must be 1";
assert cresp.done = '0' report "after request done must be 0";
assert o_memory_req = '1' report "memory request should be asserted";
assert o_memory_addr = x"00000070" report "memory request target address incorrect";
assert o_memory_wdata = x"44444444" report "memory request wrong data sent";
wait for MEMORY_LATENCY * 10 ps;
assert cresp.rdy = '0' report "after request ready must be 1";
assert cresp.done = '0' report "after request done must be 0";
assert o_memory_req = '1' report "memory request should be asserted";
assert o_memory_addr = x"00000068" report "memory request target address incorrect";
assert o_memory_wdata = x"22222222" report "memory request wrong data sent";
wait for MEMORY_LATENCY * 10 ps;
assert cresp.rdy = '0' report "after request ready must be 1";
assert cresp.done = '0' report "after request done must be 0";
assert o_memory_req = '1' report "memory request should be asserted";
assert o_memory_addr = x"00000060" report "memory request target address incorrect";
assert o_memory_wdata = x"00000000" report "memory request wrong data sent";
wait for MEMORY_LATENCY * 10 ps;
wait until clk = '1';
wait until clk = '1';
assert cresp.done = '1' report "last request has not completed";
assert cresp.rdy = '1' report "after flushing ready must be 1";
assert cresp.done = '1' report "after flushing, done must be 1";
wait until clk = '1';
wait on rst;
end process flush_watch;
end architecture test;
-------------------------------------------------------------------------------
configuration cache_line_streamer_tb_test_cfg of cache_line_streamer_tb is
for test
end for;
end cache_line_streamer_tb_test_cfg;
-------------------------------------------------------------------------------
| gpl-3.0 | 5dda6175658ffa748899502bf5beadae | 0.561441 | 3.660408 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/rd_chnl.vhd | 1 | 206,628 | -------------------------------------------------------------------------------
-- rd_chnl.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: rd_chnl.vhd
--
-- Description: This file is the top level module for the AXI BRAM
-- controller read channel interfaces. Controls all
-- handshaking and data flow on the AXI read address (AR)
-- and read data (R) channels.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Minor code cleanup.
-- Remove library version # dependency. Replace with work library.
-- ^^^^^^
-- JLJ 2/3/2011 v1.03a
-- ~~~~~~
-- Edits for scalability and support of 512 and 1024-bit data widths.
-- ^^^^^^
-- JLJ 2/14/2011 v1.03a
-- ~~~~~~
-- Initial integration of Hsiao ECC algorithm.
-- Add C_ECC_TYPE top level parameter.
-- Similar edits as wr_chnl on Hsiao ECC code.
-- ^^^^^^
-- JLJ 2/18/2011 v1.03a
-- ~~~~~~
-- Update for usage of ecc_gen.vhd module directly from MIG.
-- Clean-up XST warnings.
-- ^^^^^^
-- JLJ 2/22/2011 v1.03a
-- ~~~~~~
-- Found issue with ECC decoding on read path. Remove MSB '0' usage
-- in syndrome calculation, since h_matrix is based on 32 + 7 = 39 bits.
-- Modify read data signal used in single bit error correction.
-- ^^^^^^
-- JLJ 2/23/2011 v1.03a
-- ~~~~~~
-- Move all MIG functions to package body.
-- ^^^^^^
-- JLJ 3/2/2011 v1.03a
-- ~~~~~~
-- Fix XST handling for DIV functions. Create seperate process when
-- divisor is not constant and a power of two.
-- ^^^^^^
-- JLJ 3/15/2011 v1.03a
-- ~~~~~~
-- Clean-up unused signal, narrow_addr_inc.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Add comments as noted in Spyglass runs. And general code clean-up.
-- ^^^^^^
-- JLJ 4/21/2011 v1.03a
-- ~~~~~~
-- Code clean up.
-- Add defaults to araddr_pipe_sel & axi_arready_int when in single port mode.
-- Remove use of IF_IS_AXI4 constant.
-- ^^^^^^
-- JLJ 4/22/2011 v1.03a
-- ~~~~~~
-- Code clean up.
-- ^^^^^^
-- JLJ 5/6/2011 v1.03a
-- ~~~~~~
-- Remove usage of C_FAMILY.
-- Hard code C_USE_LUT6 constant.
-- ^^^^^^
-- JLJ 5/26/2011 v1.03a
-- ~~~~~~
-- With CR # 609695, update else clause for narrow_burst_cnt_ld to
-- remove simulation warnings when axi_byte_div_curr_arsize = zero.
-- ^^^^^^
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.wrap_brst;
use work.ua_narrow;
use work.checkbit_handler;
use work.checkbit_handler_64;
use work.correct_one_bit;
use work.correct_one_bit_64;
use work.ecc_gen;
use work.parity;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity rd_chnl is
generic (
-- C_FAMILY : string := "virtex6";
-- Specify the target architecture type
C_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_BRAM_ADDR_ADJUST_FACTOR : integer := 2;
-- Adjust factor to BRAM address width based on data width (in bits)
C_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_AXI_ID_WIDTH : integer := 4;
-- AXI ID vector width
C_S_AXI_SUPPORTS_NARROW : integer := 1;
-- Support for narrow burst operations
C_S_AXI_PROTOCOL : string := "AXI4";
-- Set to "AXI4LITE" to optimize out burst transaction support
C_SINGLE_PORT_BRAM : integer := 0;
-- Enable single port usage of BRAM
C_ECC : integer := 0;
-- Enables or disables ECC functionality
C_ECC_WIDTH : integer := 8;
-- Width of ECC data vector
C_ECC_TYPE : integer := 0 -- v1.03a
-- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code
);
port (
-- AXI Global Signals
S_AXI_AClk : in std_logic;
S_AXI_AResetn : in std_logic;
-- AXI Read Address Channel Signals (AR)
AXI_ARID : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0);
AXI_ARADDR : in std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0);
AXI_ARLEN : in std_logic_vector(7 downto 0);
-- Specifies the number of data transfers in the burst
-- "0000 0000" 1 data transfer
-- "0000 0001" 2 data transfers
-- ...
-- "1111 1111" 256 data transfers
AXI_ARSIZE : in std_logic_vector(2 downto 0);
-- Specifies the max number of data bytes to transfer in each data beat
-- "000" 1 byte to transfer
-- "001" 2 bytes to transfer
-- "010" 3 bytes to transfer
-- ...
AXI_ARBURST : in std_logic_vector(1 downto 0);
-- Specifies burst type
-- "00" FIXED = Fixed burst address (handled as INCR)
-- "01" INCR = Increment burst address
-- "10" WRAP = Incrementing address burst that wraps to lower order address at boundary
-- "11" Reserved (not checked)
AXI_ARLOCK : in std_logic;
AXI_ARCACHE : in std_logic_vector(3 downto 0);
AXI_ARPROT : in std_logic_vector(2 downto 0);
AXI_ARVALID : in std_logic;
AXI_ARREADY : out std_logic;
-- AXI Read Data Channel Signals (R)
AXI_RID : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0);
AXI_RDATA : out std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0);
AXI_RRESP : out std_logic_vector(1 downto 0);
AXI_RLAST : out std_logic;
AXI_RVALID : out std_logic;
AXI_RREADY : in std_logic;
-- ECC Register Interface Signals
Enable_ECC : in std_logic;
BRAM_Addr_En : out std_logic;
CE_Failing_We : out std_logic := '0';
Sl_CE : out std_logic := '0';
Sl_UE : out std_logic := '0';
-- Single Port Arbitration Signals
Arb2AR_Active : in std_logic;
AR2Arb_Active_Clr : out std_logic := '0';
Sng_BRAM_Addr_Ld_En : out std_logic := '0';
Sng_BRAM_Addr_Ld : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0');
Sng_BRAM_Addr_Inc : out std_logic := '0';
Sng_BRAM_Addr : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR);
-- BRAM Read Port Interface Signals
BRAM_En : out std_logic;
BRAM_Addr : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto 0);
BRAM_RdData : in std_logic_vector (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0)
);
end entity rd_chnl;
-------------------------------------------------------------------------------
architecture implementation of rd_chnl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- All functions defined in axi_bram_ctrl_funcs package.
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-- Reset active level (common through core)
constant C_RESET_ACTIVE : std_logic := '0';
constant RESP_OKAY : std_logic_vector (1 downto 0) := "00"; -- Normal access OK response
constant RESP_SLVERR : std_logic_vector (1 downto 0) := "10"; -- Slave error
-- For future support. constant RESP_EXOKAY : std_logic_vector (1 downto 0) := "01"; -- Exclusive access OK response
-- For future support. constant RESP_DECERR : std_logic_vector (1 downto 0) := "11"; -- Decode error
-- Set constants for ARLEN equal to a count of one or two beats.
constant AXI_ARLEN_ONE : std_logic_vector(7 downto 0) := (others => '0');
constant AXI_ARLEN_TWO : std_logic_vector(7 downto 0) := "00000001";
-- Modify C_BRAM_ADDR_SIZE to be adjusted for BRAM data width
-- When BRAM data width = 32 bits, BRAM_Addr (1:0) = "00"
-- When BRAM data width = 64 bits, BRAM_Addr (2:0) = "000"
-- When BRAM data width = 128 bits, BRAM_Addr (3:0) = "0000"
-- When BRAM data width = 256 bits, BRAM_Addr (4:0) = "00000"
-- Move to full_axi module
-- constant C_BRAM_ADDR_ADJUST_FACTOR : integer := log2 (C_AXI_DATA_WIDTH/8);
-- Not used
-- constant C_BRAM_ADDR_ADJUST : integer := C_AXI_ADDR_WIDTH - C_BRAM_ADDR_ADJUST_FACTOR;
-- Determine maximum size for narrow burst length counter
-- When C_AXI_DATA_WIDTH = 32, minimum narrow width burst is 8 bits
-- resulting in a count 3 downto 0 => so minimum counter width = 2 bits.
-- When C_AXI_DATA_WIDTH = 256, minimum narrow width burst is 8 bits
-- resulting in a count 31 downto 0 => so minimum counter width = 5 bits.
constant C_NARROW_BURST_CNT_LEN : integer := log2 (C_AXI_DATA_WIDTH/8);
constant NARROW_CNT_MAX : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
-- Max length burst count AXI4 specification
constant C_MAX_BRST_CNT : integer := 256;
constant C_BRST_CNT_SIZE : integer := log2 (C_MAX_BRST_CNT);
-- When the burst count = 0
constant C_BRST_CNT_ZERO : std_logic_vector(C_BRST_CNT_SIZE-1 downto 0) := (others => '0');
-- Burst count = 1
constant C_BRST_CNT_ONE : std_logic_vector(7 downto 0) := "00000001";
-- Burst count = 2
constant C_BRST_CNT_TWO : std_logic_vector(7 downto 0) := "00000010";
-- Read data mux select constants (for signal rddata_mux_sel)
-- '0' selects BRAM
-- '1' selects read skid buffer
constant C_RDDATA_MUX_BRAM : std_logic := '0';
constant C_RDDATA_MUX_SKID_BUF : std_logic := '1';
-- Determine the number of bytes based on the AXI data width.
constant C_AXI_DATA_WIDTH_BYTES : integer := C_AXI_DATA_WIDTH/8;
-- AXI Burst Types
-- AXI Spec 4.4
constant C_AXI_BURST_WRAP : std_logic_vector (1 downto 0) := "10";
constant C_AXI_BURST_INCR : std_logic_vector (1 downto 0) := "01";
constant C_AXI_BURST_FIXED : std_logic_vector (1 downto 0) := "00";
-- AXI Size Constants
-- constant C_AXI_SIZE_1BYTE : std_logic_vector (2 downto 0) := "000"; -- 1 byte
-- constant C_AXI_SIZE_2BYTE : std_logic_vector (2 downto 0) := "001"; -- 2 bytes
-- constant C_AXI_SIZE_4BYTE : std_logic_vector (2 downto 0) := "010"; -- 4 bytes = max size for 32-bit BRAM
-- constant C_AXI_SIZE_8BYTE : std_logic_vector (2 downto 0) := "011"; -- 8 bytes = max size for 64-bit BRAM
-- constant C_AXI_SIZE_16BYTE : std_logic_vector (2 downto 0) := "100"; -- 16 bytes = max size for 128-bit BRAM
-- constant C_AXI_SIZE_32BYTE : std_logic_vector (2 downto 0) := "101"; -- 32 bytes = max size for 256-bit BRAM
-- constant C_AXI_SIZE_64BYTE : std_logic_vector (2 downto 0) := "110"; -- 64 bytes = max size for 512-bit BRAM
-- constant C_AXI_SIZE_128BYTE : std_logic_vector (2 downto 0) := "111"; -- 128 bytes = max size for 1024-bit BRAM
-- Determine max value of ARSIZE based on the AXI data width.
-- Use function in axi_bram_ctrl_funcs package.
constant C_AXI_SIZE_MAX : std_logic_vector (2 downto 0) := Create_Size_Max (C_AXI_DATA_WIDTH);
-- Internal ECC data width size.
constant C_INT_ECC_WIDTH : integer := Int_ECC_Size (C_AXI_DATA_WIDTH);
-- For use with ECC functions (to use LUT6 components or let synthesis infer the optimal implementation).
-- constant C_USE_LUT6 : boolean := Family_To_LUT_Size (String_To_Family (C_FAMILY,false)) = 6;
-- Remove usage of C_FAMILY.
-- All architectures supporting AXI will support a LUT6.
-- Hard code this internal constant used in ECC algorithm.
constant C_USE_LUT6 : boolean := TRUE;
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AXI Read Address Channel Signals
-------------------------------------------------------------------------------
-- State machine type declarations
type RD_ADDR_SM_TYPE is ( IDLE,
LD_ARADDR
);
signal rd_addr_sm_cs, rd_addr_sm_ns : RD_ADDR_SM_TYPE;
signal ar_active_set : std_logic := '0';
signal ar_active_set_i : std_logic := '0';
signal ar_active_clr : std_logic := '0';
signal ar_active : std_logic := '0';
signal ar_active_d1 : std_logic := '0';
signal ar_active_re : std_logic := '0';
signal axi_araddr_pipe : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal curr_araddr_lsb : std_logic_vector (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) := (others => '0');
signal araddr_pipe_ld : std_logic := '0';
signal araddr_pipe_ld_i : std_logic := '0';
signal araddr_pipe_sel : std_logic := '0';
-- '0' indicates mux select from AXI
-- '1' indicates mux select from AR Addr Register
signal axi_araddr_full : std_logic := '0';
signal axi_arready_int : std_logic := '0';
signal axi_early_arready_int : std_logic := '0';
signal axi_aresetn_d1 : std_logic := '0';
signal axi_aresetn_d2 : std_logic := '0';
signal axi_aresetn_re : std_logic := '0';
signal axi_aresetn_re_reg : std_logic := '0';
signal no_ar_ack_cmb : std_logic := '0';
signal no_ar_ack : std_logic := '0';
signal pend_rd_op_cmb : std_logic := '0';
signal pend_rd_op : std_logic := '0';
signal axi_arid_pipe : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal axi_arsize_pipe : std_logic_vector (2 downto 0) := (others => '0');
signal axi_arsize_pipe_4byte : std_logic := '0';
signal axi_arsize_pipe_8byte : std_logic := '0';
signal axi_arsize_pipe_16byte : std_logic := '0';
signal axi_arsize_pipe_32byte : std_logic := '0';
-- v1.03a
signal axi_arsize_pipe_max : std_logic := '0';
signal curr_arsize : std_logic_vector (2 downto 0) := (others => '0');
signal curr_arsize_reg : std_logic_vector (2 downto 0) := (others => '0');
signal axi_arlen_pipe : std_logic_vector(7 downto 0) := (others => '0');
signal axi_arlen_pipe_1_or_2 : std_logic := '0';
signal curr_arlen : std_logic_vector(7 downto 0) := (others => '0');
signal curr_arlen_reg : std_logic_vector(7 downto 0) := (others => '0');
signal axi_arburst_pipe : std_logic_vector(1 downto 0) := (others => '0');
signal axi_arburst_pipe_fixed : std_logic := '0';
signal curr_arburst : std_logic_vector(1 downto 0) := (others => '0');
signal curr_wrap_burst : std_logic := '0';
signal curr_wrap_burst_reg : std_logic := '0';
signal max_wrap_burst : std_logic := '0';
signal curr_incr_burst : std_logic := '0';
signal curr_fixed_burst : std_logic := '0';
signal curr_fixed_burst_reg : std_logic := '0';
-- BRAM Address Counter
signal bram_addr_ld_en : std_logic := '0';
signal bram_addr_ld_en_i : std_logic := '0';
signal bram_addr_ld_en_mod : std_logic := '0';
signal bram_addr_ld : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
signal bram_addr_ld_wrap : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
signal bram_addr_inc : std_logic := '0';
signal bram_addr_inc_mod : std_logic := '0';
signal bram_addr_inc_wrap_mod : std_logic := '0';
-------------------------------------------------------------------------------
-- AXI Read Data Channel Signals
-------------------------------------------------------------------------------
-- State machine type declarations
type RD_DATA_SM_TYPE is ( IDLE,
SNG_ADDR,
SEC_ADDR,
FULL_PIPE,
FULL_THROTTLE,
LAST_ADDR,
LAST_THROTTLE,
LAST_DATA,
LAST_DATA_AR_PEND
);
signal rd_data_sm_cs, rd_data_sm_ns : RD_DATA_SM_TYPE;
signal rd_adv_buf : std_logic := '0';
signal axi_rd_burst : std_logic := '0';
signal axi_rd_burst_two : std_logic := '0';
signal act_rd_burst : std_logic := '0';
signal act_rd_burst_set : std_logic := '0';
signal act_rd_burst_clr : std_logic := '0';
signal act_rd_burst_two : std_logic := '0';
-- Rd Data Buffer/Register
signal rd_skid_buf_ld_cmb : std_logic := '0';
signal rd_skid_buf_ld_reg : std_logic := '0';
signal rd_skid_buf_ld : std_logic := '0';
signal rd_skid_buf_ld_imm : std_logic := '0';
signal rd_skid_buf : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal rddata_mux_sel_cmb : std_logic := '0';
signal rddata_mux_sel : std_logic := '0';
signal axi_rdata_en : std_logic := '0';
signal axi_rdata_mux : std_logic_vector (C_AXI_DATA_WIDTH+8*C_ECC-1 downto 0) := (others => '0');
-- Read Burst Counter
signal brst_cnt_max : std_logic := '0';
signal brst_cnt_max_d1 : std_logic := '0';
signal brst_cnt_max_re : std_logic := '0';
signal end_brst_rd_clr_cmb : std_logic := '0';
signal end_brst_rd_clr : std_logic := '0';
signal end_brst_rd : std_logic := '0';
signal brst_zero : std_logic := '0';
signal brst_one : std_logic := '0';
signal brst_cnt_ld : std_logic_vector (C_BRST_CNT_SIZE-1 downto 0) := (others => '0');
signal brst_cnt_rst : std_logic := '0';
signal brst_cnt_ld_en : std_logic := '0';
signal brst_cnt_ld_en_i : std_logic := '0';
signal brst_cnt_dec : std_logic := '0';
signal brst_cnt : std_logic_vector (C_BRST_CNT_SIZE-1 downto 0) := (others => '0');
-- AXI Read Response Signals
signal axi_rid_temp : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal axi_rid_temp_full : std_logic := '0';
signal axi_rid_temp_full_d1 : std_logic := '0';
signal axi_rid_temp_full_fe : std_logic := '0';
signal axi_rid_temp2 : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal axi_rid_temp2_full : std_logic := '0';
signal axi_b2b_rid_adv : std_logic := '0';
signal axi_rid_int : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal axi_rresp_int : std_logic_vector (1 downto 0) := (others => '0');
signal axi_rvalid_clr_ok : std_logic := '0';
signal axi_rvalid_set_cmb : std_logic := '0';
signal axi_rvalid_set : std_logic := '0';
signal axi_rvalid_int : std_logic := '0';
signal axi_rlast_int : std_logic := '0';
signal axi_rlast_set : std_logic := '0';
-- Internal BRAM Signals
signal bram_en_cmb : std_logic := '0';
signal bram_en_int : std_logic := '0';
signal bram_addr_int : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
-- Narrow Burst Signals
signal curr_narrow_burst_cmb : std_logic := '0';
signal curr_narrow_burst : std_logic := '0';
signal narrow_burst_cnt_ld : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
signal narrow_burst_cnt_ld_reg : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
signal narrow_burst_cnt_ld_mod : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
signal narrow_addr_rst : std_logic := '0';
signal narrow_addr_ld_en : std_logic := '0';
signal narrow_addr_dec : std_logic := '0';
signal narrow_bram_addr_inc : std_logic := '0';
signal narrow_bram_addr_inc_d1 : std_logic := '0';
signal narrow_bram_addr_inc_re : std_logic := '0';
signal narrow_addr_int : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
signal curr_ua_narrow_wrap : std_logic := '0';
signal curr_ua_narrow_incr : std_logic := '0';
signal ua_narrow_load : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
-- State machine type declarations
type RLAST_SM_TYPE is ( IDLE,
W8_THROTTLE,
W8_2ND_LAST_DATA,
W8_LAST_DATA,
-- W8_LAST_DATA_B2,
W8_THROTTLE_B2
);
signal rlast_sm_cs, rlast_sm_ns : RLAST_SM_TYPE;
signal last_bram_addr : std_logic := '0';
signal set_last_bram_addr : std_logic := '0';
signal alast_bram_addr : std_logic := '0';
signal rd_b2b_elgible : std_logic := '0';
signal rd_b2b_elgible_no_thr_check : std_logic := '0';
signal throttle_last_data : std_logic := '0';
signal disable_b2b_brst_cmb : std_logic := '0';
signal disable_b2b_brst : std_logic := '0';
signal axi_b2b_brst_cmb : std_logic := '0';
signal axi_b2b_brst : std_logic := '0';
signal do_cmplt_burst_cmb : std_logic := '0';
signal do_cmplt_burst : std_logic := '0';
signal do_cmplt_burst_clr : std_logic := '0';
-------------------------------------------------------------------------------
-- ECC Signals
-------------------------------------------------------------------------------
signal UnCorrectedRdData : std_logic_vector (0 to C_AXI_DATA_WIDTH-1) := (others => '0');
-- Move vector from core ECC module to use in AXI RDATA register output
signal Syndrome : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width
signal Syndrome_4 : std_logic_vector (0 to 1) := (others => '0'); -- Only used in 32-bit ECC
signal Syndrome_6 : std_logic_vector (0 to 5) := (others => '0'); -- Specific to ECC @ 32-bit data width
signal Syndrome_7 : std_logic_vector (0 to 11) := (others => '0'); -- Specific to ECC @ 64-bit data width
signal syndrome_reg : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width
signal syndrome_reg_i : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width
signal Sl_UE_i : std_logic := '0';
signal UE_Q : std_logic := '0';
-- v1.03a
-- Hsiao ECC
signal syndrome_r : std_logic_vector (C_INT_ECC_WIDTH - 1 downto 0) := (others => '0');
constant CODE_WIDTH : integer := C_AXI_DATA_WIDTH + C_INT_ECC_WIDTH;
constant ECC_WIDTH : integer := C_INT_ECC_WIDTH;
signal h_rows : std_logic_vector (CODE_WIDTH * ECC_WIDTH - 1 downto 0);
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- AXI Read Address Channel Output Signals
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_ARREADY_DUAL
-- Purpose: Generate AXI_ARREADY when in dual port mode.
---------------------------------------------------------------------------
GEN_ARREADY_DUAL: if C_SINGLE_PORT_BRAM = 0 generate
begin
-- Ensure ARREADY only gets asserted early when acknowledge recognized
-- on AXI read data channel.
AXI_ARREADY <= axi_arready_int or (axi_early_arready_int and rd_adv_buf);
end generate GEN_ARREADY_DUAL;
---------------------------------------------------------------------------
-- Generate: GEN_ARREADY_SNG
-- Purpose: Generate AXI_ARREADY when in single port mode.
---------------------------------------------------------------------------
GEN_ARREADY_SNG: if C_SINGLE_PORT_BRAM = 1 generate
begin
-- ARREADY generated by sng_port_arb module
AXI_ARREADY <= '0';
axi_arready_int <= '0';
end generate GEN_ARREADY_SNG;
---------------------------------------------------------------------------
-- AXI Read Data Channel Output Signals
---------------------------------------------------------------------------
-- UE flag is detected is same clock cycle that read data is presented on
-- the AXI bus. Must drive SLVERR combinatorially to align with corrupted
-- detected data word.
AXI_RRESP <= RESP_SLVERR when (C_ECC = 1 and Sl_UE_i = '1') else axi_rresp_int;
AXI_RVALID <= axi_rvalid_int;
AXI_RID <= axi_rid_int;
AXI_RLAST <= axi_rlast_int;
---------------------------------------------------------------------------
--
-- *** AXI Read Address Channel Interface ***
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_AR_PIPE_SNG
-- Purpose: Only generate pipeline registers when in dual port BRAM mode.
---------------------------------------------------------------------------
GEN_AR_PIPE_SNG: if C_SINGLE_PORT_BRAM = 1 generate
begin
-- Unused AW pipeline (set default values)
araddr_pipe_ld <= '0';
axi_araddr_pipe <= AXI_ARADDR;
axi_arid_pipe <= AXI_ARID;
axi_arsize_pipe <= AXI_ARSIZE;
axi_arlen_pipe <= AXI_ARLEN;
axi_arburst_pipe <= AXI_ARBURST;
axi_arlen_pipe_1_or_2 <= '0';
axi_arburst_pipe_fixed <= '0';
axi_araddr_full <= '0';
end generate GEN_AR_PIPE_SNG;
---------------------------------------------------------------------------
-- Generate: GEN_AR_PIPE_DUAL
-- Purpose: Only generate pipeline registers when in dual port BRAM mode.
---------------------------------------------------------------------------
GEN_AR_PIPE_DUAL: if C_SINGLE_PORT_BRAM = 0 generate
begin
-----------------------------------------------------------------------
-- AXI Read Address Buffer/Register
-- (mimic behavior of address pipeline for AXI_ARID)
-----------------------------------------------------------------------
GEN_ARADDR: for i in C_AXI_ADDR_WIDTH-1 downto 0 generate
begin
REG_ARADDR: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- No reset condition to save resources/timing
if (araddr_pipe_ld = '1') then
axi_araddr_pipe (i) <= AXI_ARADDR (i);
else
axi_araddr_pipe (i) <= axi_araddr_pipe (i);
end if;
end if;
end process REG_ARADDR;
end generate GEN_ARADDR;
-------------------------------------------------------------------
-- Register ARID
-- No reset condition to save resources/timing
-------------------------------------------------------------------
REG_ARID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (araddr_pipe_ld = '1') then
axi_arid_pipe <= AXI_ARID;
else
axi_arid_pipe <= axi_arid_pipe;
end if;
end if;
end process REG_ARID;
---------------------------------------------------------------------------
-- In parallel to ARADDR pipeline and ARID
-- Use same control signals to capture AXI_ARSIZE, AXI_ARLEN & AXI_ARBURST.
-- Register AXI_ARSIZE, AXI_ARLEN & AXI_ARBURST
-- No reset condition to save resources/timing
REG_ARCTRL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (araddr_pipe_ld = '1') then
axi_arsize_pipe <= AXI_ARSIZE;
axi_arlen_pipe <= AXI_ARLEN;
axi_arburst_pipe <= AXI_ARBURST;
else
axi_arsize_pipe <= axi_arsize_pipe;
axi_arlen_pipe <= axi_arlen_pipe;
axi_arburst_pipe <= axi_arburst_pipe;
end if;
end if;
end process REG_ARCTRL;
---------------------------------------------------------------------------
-- Create signals that indicate value of AXI_ARLEN in pipeline stage
-- Used to decode length of burst when BRAM address can be loaded early
-- when pipeline is full.
--
-- Add early decode of ARBURST in pipeline.
-- Copy logic from WR_CHNL module (similar logic).
-- Add early decode of ARSIZE = 4 bytes in pipeline.
REG_ARLEN_PIPE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- No reset condition to save resources/timing
if (araddr_pipe_ld = '1') then
-- Create merge to decode ARLEN of ONE or TWO
if (AXI_ARLEN = AXI_ARLEN_ONE) or (AXI_ARLEN = AXI_ARLEN_TWO) then
axi_arlen_pipe_1_or_2 <= '1';
else
axi_arlen_pipe_1_or_2 <= '0';
end if;
-- Early decode on value in pipeline of ARBURST
if (AXI_ARBURST = C_AXI_BURST_FIXED) then
axi_arburst_pipe_fixed <= '1';
else
axi_arburst_pipe_fixed <= '0';
end if;
else
axi_arlen_pipe_1_or_2 <= axi_arlen_pipe_1_or_2;
axi_arburst_pipe_fixed <= axi_arburst_pipe_fixed;
end if;
end if;
end process REG_ARLEN_PIPE;
---------------------------------------------------------------------------
-- Create full flag for ARADDR pipeline
-- Set when read address register is loaded.
-- Cleared when read address stored in register is loaded into BRAM
-- address counter.
REG_RDADDR_FULL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- (bram_addr_ld_en = '1' and araddr_pipe_sel = '1') then
(bram_addr_ld_en = '1' and araddr_pipe_sel = '1' and araddr_pipe_ld = '0') then
axi_araddr_full <= '0';
elsif (araddr_pipe_ld = '1') then
axi_araddr_full <= '1';
else
axi_araddr_full <= axi_araddr_full;
end if;
end if;
end process REG_RDADDR_FULL;
---------------------------------------------------------------------------
end generate GEN_AR_PIPE_DUAL;
---------------------------------------------------------------------------
-- v1.03a
-- Add early decode of ARSIZE = max size in pipeline based on AXI data
-- bus width (use constant, C_AXI_SIZE_MAX)
REG_ARSIZE_PIPE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_arsize_pipe_max <= '0';
elsif (araddr_pipe_ld = '1') then
-- Early decode of ARSIZE in pipeline equal to max # of bytes
-- based on AXI data bus width
if (AXI_ARSIZE = C_AXI_SIZE_MAX) then
axi_arsize_pipe_max <= '1';
else
axi_arsize_pipe_max <= '0';
end if;
else
axi_arsize_pipe_max <= axi_arsize_pipe_max;
end if;
end if;
end process REG_ARSIZE_PIPE;
---------------------------------------------------------------------------
-- Generate: GE_ARREADY
-- Purpose: ARREADY is only created here when in dual port BRAM mode.
---------------------------------------------------------------------------
GEN_ARREADY: if (C_SINGLE_PORT_BRAM = 0) generate
begin
----------------------------------------------------------------------------
-- AXI_ARREADY Output Register
-- Description: Keep AXI_ARREADY output asserted until ARADDR pipeline
-- is full. When a full condition is reached, negate
-- ARREADY as another AR address can not be accepted.
-- Add condition to keep ARReady asserted if loading current
--- ARADDR pipeline value into the BRAM address counter.
-- Indicated by assertion of bram_addr_ld_en & araddr_pipe_sel.
--
----------------------------------------------------------------------------
REG_ARREADY: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_arready_int <= '0';
-- Detect end of S_AXI_AResetn to assert AWREADY and accept
-- new AWADDR values
elsif (axi_aresetn_re_reg = '1') or
-- Add condition for early ARREADY to keep pipeline full
(bram_addr_ld_en = '1' and araddr_pipe_sel = '1' and axi_early_arready_int = '0') then
axi_arready_int <= '1';
-- Add conditional check if ARREADY is asserted (with ARVALID) (one clock cycle later)
-- when the address pipeline is full.
elsif (araddr_pipe_ld = '1') or
(AXI_ARVALID = '1' and axi_arready_int = '1' and axi_araddr_full = '1') then
axi_arready_int <= '0';
else
axi_arready_int <= axi_arready_int;
end if;
end if;
end process REG_ARREADY;
----------------------------------------------------------------------------
REG_EARLY_ARREADY: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_early_arready_int <= '0';
-- Pending ARADDR and ARREADY is not yet asserted to accept
-- operation (due to ARADDR being full)
elsif (AXI_ARVALID = '1' and axi_arready_int = '0' and
axi_araddr_full = '1') and
(alast_bram_addr = '1') and
-- Add check for elgible back-to-back BRAM load
(rd_b2b_elgible = '1') then
axi_early_arready_int <= '1';
else
axi_early_arready_int <= '0';
end if;
end if;
end process REG_EARLY_ARREADY;
---------------------------------------------------------------------------
-- Need to detect end of reset cycle to assert ARREADY on AXI bus
REG_ARESETN: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
axi_aresetn_d1 <= S_AXI_AResetn;
axi_aresetn_d2 <= axi_aresetn_d1;
axi_aresetn_re_reg <= axi_aresetn_re;
end if;
end process REG_ARESETN;
-- Create combinatorial RE detect of S_AXI_AResetn
axi_aresetn_re <= '1' when (S_AXI_AResetn = '1' and axi_aresetn_d1 = '0') else '0';
----------------------------------------------------------------------------
end generate GEN_ARREADY;
---------------------------------------------------------------------------
-- Generate: GEN_DUAL_ADDR_CNT
-- Purpose: Instantiate BRAM address counter unique for wr_chnl logic
-- only when controller configured in dual port mode.
---------------------------------------------------------------------------
GEN_DUAL_ADDR_CNT: if (C_SINGLE_PORT_BRAM = 0) generate
begin
---------------------------------------------------------------------------
-- Replace I_ADDR_CNT module usage of pf_counter in proc_common library.
-- Only need to use lower 12-bits of address due to max AXI burst size
-- Since AXI guarantees bursts do not cross 4KB boundary, the counting part
-- of I_ADDR_CNT can be reduced to max 4KB.
--
-- No reset on bram_addr_int.
-- Increment ONLY.
REG_ADDR_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (bram_addr_ld_en_mod = '1') then
bram_addr_int <= bram_addr_ld;
elsif (bram_addr_inc_mod = '1') then
bram_addr_int (C_AXI_ADDR_WIDTH-1 downto 12) <=
bram_addr_int (C_AXI_ADDR_WIDTH-1 downto 12);
bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR) <=
std_logic_vector (unsigned (bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR)) + 1);
end if;
end if;
end process REG_ADDR_CNT;
---------------------------------------------------------------------------
-- Set defaults to shared address counter
-- Only used in single port configurations
Sng_BRAM_Addr_Ld_En <= '0';
Sng_BRAM_Addr_Ld <= (others => '0');
Sng_BRAM_Addr_Inc <= '0';
end generate GEN_DUAL_ADDR_CNT;
---------------------------------------------------------------------------
-- Generate: GEN_SNG_ADDR_CNT
-- Purpose: When configured in single port BRAM mode, address counter
-- is shared with rd_chnl module. Assign output signals here
-- to counter instantiation at full_axi module level.
---------------------------------------------------------------------------
GEN_SNG_ADDR_CNT: if (C_SINGLE_PORT_BRAM = 1) generate
begin
Sng_BRAM_Addr_Ld_En <= bram_addr_ld_en_mod;
Sng_BRAM_Addr_Ld <= bram_addr_ld;
Sng_BRAM_Addr_Inc <= bram_addr_inc_mod;
bram_addr_int <= Sng_BRAM_Addr;
end generate GEN_SNG_ADDR_CNT;
---------------------------------------------------------------------------
-- BRAM address load mux.
-- Either load BRAM counter directly from AXI bus or from stored registered value
-- Use registered signal to indicate current operation is a WRAP burst
--
-- Match bram_addr_ld to what asserts bram_addr_ld_en_mod
-- Include bram_addr_inc_mod when asserted to use bram_addr_ld_wrap value
-- (otherwise use pipelined or AXI bus value to load BRAM address counter)
bram_addr_ld <= bram_addr_ld_wrap when (max_wrap_burst = '1' and
curr_wrap_burst_reg = '1' and
bram_addr_inc_wrap_mod = '1') else
axi_araddr_pipe (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
when (araddr_pipe_sel = '1') else
AXI_ARADDR (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR);
---------------------------------------------------------------------------
-- On wrap burst max loads (simultaneous BRAM address increment is asserted).
-- Ensure that load has higher priority over increment.
-- Use registered signal to indicate current operation is a WRAP burst
bram_addr_ld_en_mod <= '1' when (bram_addr_ld_en = '1' or
(max_wrap_burst = '1' and
curr_wrap_burst_reg = '1' and
bram_addr_inc_wrap_mod = '1'))
else '0';
-- Create a special bram_addr_inc_mod for use in the bram_addr_ld_en_mod signal
-- logic. No need for the check if the current operation is NOT a fixed AND a wrap
-- burst. The transfer will be one or the other.
-- Found issue when narrow FIXED length burst is incorrectly
-- incrementing BRAM address counter
bram_addr_inc_wrap_mod <= bram_addr_inc when (curr_narrow_burst = '0')
else narrow_bram_addr_inc_re;
----------------------------------------------------------------------------
-- Narrow bursting
--
-- Handle read burst addressing on narrow burst operations
-- Intercept BRAM address increment flag, bram_addr_inc and only
-- increment address when the number of BRAM reads match the width of the
-- AXI data bus.
-- For a 32-bit BRAM, byte burst will increment the BRAM address
-- after four reads from BRAM.
-- For a 256-bit BRAM, a byte burst will increment the BRAM address
-- after 32 reads from BRAM.
-- Based on current operation being a narrow burst, hold off BRAM
-- address increment until narrow burst fits BRAM data width.
-- For non narrow burst operations, use bram_addr_inc from data SM.
--
-- Add in check that burst type is not FIXED, curr_fixed_burst_reg
-- bram_addr_inc_mod <= (bram_addr_inc and not (curr_fixed_burst_reg)) when (curr_narrow_burst = '0') else
-- narrow_bram_addr_inc_re;
--
--
-- Replace w/ below generate statements based on supporting narrow transfers or not.
-- Create generate statement around the signal assignment for bram_addr_inc_mod.
---------------------------------------------------------------------------
-- Generate: GEN_BRAM_INC_MOD_W_NARROW
-- Purpose: Assign signal, bram_addr_inc_mod when narrow transfers
-- are supported in design instantiation.
---------------------------------------------------------------------------
GEN_BRAM_INC_MOD_W_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
-- Found issue when narrow FIXED length burst is incorrectly incrementing BRAM address counter
bram_addr_inc_mod <= (bram_addr_inc and not (curr_fixed_burst_reg)) when (curr_narrow_burst = '0') else
(narrow_bram_addr_inc_re and not (curr_fixed_burst_reg));
end generate GEN_BRAM_INC_MOD_W_NARROW;
---------------------------------------------------------------------------
-- Generate: GEN_WO_NARROW
-- Purpose: Assign signal, bram_addr_inc_mod when narrow transfers
-- are not supported in the design instantiation.
-- Drive default values for narrow counter and logic when
-- narrow operation support is disabled.
---------------------------------------------------------------------------
GEN_WO_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 0) generate
begin
-- Found issue when narrow FIXED length burst is incorrectly incrementing BRAM address counter
bram_addr_inc_mod <= bram_addr_inc and not (curr_fixed_burst_reg);
narrow_addr_rst <= '0';
narrow_burst_cnt_ld_mod <= (others => '0');
narrow_addr_dec <= '0';
narrow_addr_ld_en <= '0';
narrow_bram_addr_inc <= '0';
narrow_bram_addr_inc_d1 <= '0';
narrow_bram_addr_inc_re <= '0';
narrow_addr_int <= (others => '0');
curr_narrow_burst <= '0';
end generate GEN_WO_NARROW;
---------------------------------------------------------------------------
--
-- Only instantiate NARROW_CNT and supporting logic when narrow transfers
-- are supported and utilized by masters in the AXI system.
-- The design parameter, C_S_AXI_SUPPORTS_NARROW will indicate this.
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_NARROW_CNT
-- Purpose: Instantiate narrow counter and logic when narrow
-- operation support is enabled.
---------------------------------------------------------------------------
GEN_NARROW_CNT: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
---------------------------------------------------------------------------
--
-- Generate seperate smaller counter for narrow burst operations
-- Replace I_NARROW_CNT module usage of pf_counter_top from proc_common library.
--
-- Counter size is adjusted based on size of data burst.
--
-- For example, 32-bit data width BRAM, minimum narrow width
-- burst is 8 bits resulting in a count 3 downto 0. So the
-- minimum counter width = 2 bits.
--
-- When C_AXI_DATA_WIDTH = 256, minimum narrow width burst
-- is 8 bits resulting in a count 31 downto 0. So the
-- minimum counter width = 5 bits.
--
-- Size of counter = C_NARROW_BURST_CNT_LEN
--
---------------------------------------------------------------------------
REG_NARROW_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (narrow_addr_rst = '1') then
narrow_addr_int <= (others => '0');
-- Load enable
elsif (narrow_addr_ld_en = '1') then
narrow_addr_int <= narrow_burst_cnt_ld_mod;
-- Decrement ONLY (no increment functionality)
elsif (narrow_addr_dec = '1') then
narrow_addr_int (C_NARROW_BURST_CNT_LEN-1 downto 0) <=
std_logic_vector (unsigned (narrow_addr_int (C_NARROW_BURST_CNT_LEN-1 downto 0)) - 1);
end if;
end if;
end process REG_NARROW_CNT;
---------------------------------------------------------------------------
narrow_addr_rst <= not (S_AXI_AResetn);
-- Modify narrow burst count load value based on
-- unalignment of AXI address value
narrow_burst_cnt_ld_mod <= ua_narrow_load when (curr_ua_narrow_wrap = '1' or curr_ua_narrow_incr = '1') else
narrow_burst_cnt_ld when (bram_addr_ld_en = '1') else
narrow_burst_cnt_ld_reg;
narrow_addr_dec <= bram_addr_inc when (curr_narrow_burst = '1') else '0';
narrow_addr_ld_en <= (curr_narrow_burst_cmb and bram_addr_ld_en) or narrow_bram_addr_inc_re;
narrow_bram_addr_inc <= '1' when (narrow_addr_int = NARROW_CNT_MAX) and
(curr_narrow_burst = '1')
-- Ensure that narrow address counter doesn't
-- flag max or get loaded to
-- reset narrow counter until AXI read data
-- bus has acknowledged current
-- data on the AXI bus. Use rd_adv_buf signal
-- to indicate the non throttle
-- condition on the AXI bus.
and (bram_addr_inc = '1')
else '0';
----------------------------------------------------------------------------
-- Detect rising edge of narrow_bram_addr_inc
REG_NARROW_BRAM_ADDR_INC: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
narrow_bram_addr_inc_d1 <= '0';
else
narrow_bram_addr_inc_d1 <= narrow_bram_addr_inc;
end if;
end if;
end process REG_NARROW_BRAM_ADDR_INC;
narrow_bram_addr_inc_re <= '1' when (narrow_bram_addr_inc = '1') and
(narrow_bram_addr_inc_d1 = '0')
else '0';
---------------------------------------------------------------------------
end generate GEN_NARROW_CNT;
----------------------------------------------------------------------------
-- Specify current ARSIZE signal
-- Address pipeline MUX
curr_arsize <= axi_arsize_pipe when (araddr_pipe_sel = '1') else AXI_ARSIZE;
REG_ARSIZE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
curr_arsize_reg <= (others => '0');
-- Register curr_arsize when bram_addr_ld_en = '1'
elsif (bram_addr_ld_en = '1') then
curr_arsize_reg <= curr_arsize;
else
curr_arsize_reg <= curr_arsize_reg;
end if;
end if;
end process REG_ARSIZE;
---------------------------------------------------------------------------
-- Generate: GEN_NARROW_EN
-- Purpose: Only instantiate logic to determine if current burst
-- is a narrow burst when narrow bursting logic is supported.
---------------------------------------------------------------------------
GEN_NARROW_EN: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
-----------------------------------------------------------------------
-- Determine "narrow" burst transfers
-- Compare the ARSIZE to the BRAM data width
-----------------------------------------------------------------------
-- v1.03a
-- Detect if current burst operation is of size /= to the full
-- AXI data bus width. If not, then the current operation is a
-- "narrow" burst.
curr_narrow_burst_cmb <= '1' when (curr_arsize /= C_AXI_SIZE_MAX) else '0';
---------------------------------------------------------------------------
-- Register flag indicating the current operation
-- is a narrow read burst
NARROW_BURST_REG: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
-- Need to reset this flag at end of narrow burst operation
-- Ensure if curr_narrow_burst got set during previous transaction, axi_rlast_set
-- doesn't clear the flag (add check for pend_rd_op negated).
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_set = '1' and pend_rd_op = '0' and bram_addr_ld_en = '0') then
curr_narrow_burst <= '0';
-- Add check for burst operation using ARLEN value
-- Ensure that narrow burst flag does not get set during FIXED burst types
elsif (bram_addr_ld_en = '1') and (curr_arlen /= AXI_ARLEN_ONE) and
(curr_fixed_burst = '0') then
curr_narrow_burst <= curr_narrow_burst_cmb;
end if;
end if;
end process NARROW_BURST_REG;
end generate GEN_NARROW_EN;
---------------------------------------------------------------------------
-- Generate: GEN_NARROW_CNT_LD
-- Purpose: Only instantiate logic to determine narrow burst counter
-- load value when narrow bursts are enabled.
---------------------------------------------------------------------------
GEN_NARROW_CNT_LD: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
signal curr_arsize_unsigned : unsigned (2 downto 0) := (others => '0');
signal axi_byte_div_curr_arsize : integer := 1;
begin
-- v1.03a
-- Create narrow burst counter load value based on current operation
-- "narrow" data width (indicated by value of AWSIZE).
curr_arsize_unsigned <= unsigned (curr_arsize);
-- XST does not support divisors that are not constants and powers of 2.
-- Create process to create a fixed value for divisor.
-- Replace this statement:
-- narrow_burst_cnt_ld <= std_logic_vector (
-- to_unsigned (
-- (C_AXI_DATA_WIDTH_BYTES / (2**(to_integer (curr_arsize_unsigned))) ) - 1,
-- C_NARROW_BURST_CNT_LEN));
-- -- With this new process and subsequent signal assignment:
-- DIV_AWSIZE: process (curr_arsize_unsigned)
-- begin
--
-- case (to_integer (curr_arsize_unsigned)) is
-- when 0 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 1;
-- when 1 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 2;
-- when 2 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 4;
-- when 3 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 8;
-- when 4 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 16;
-- when 5 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 32;
-- when 6 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 64;
-- when 7 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 128;
-- --coverage off
-- when others => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES;
-- --coverage on
-- end case;
--
-- end process DIV_AWSIZE;
-- w/ CR # 609695
-- With this new process and subsequent signal assignment:
DIV_AWSIZE: process (curr_arsize_unsigned)
begin
case (curr_arsize_unsigned) is
when "000" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 1;
when "001" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 2;
when "010" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 4;
when "011" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 8;
when "100" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 16;
when "101" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 32;
when "110" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 64;
when "111" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 128;
--coverage off
when others => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES;
--coverage on
end case;
end process DIV_AWSIZE;
-- v1.03a
-- Replace with new signal assignment.
-- For synthesis to support only divisors that are constant and powers of two.
-- Updated else clause for simulation warnings w/ CR # 609695
narrow_burst_cnt_ld <= std_logic_vector (
to_unsigned (
(axi_byte_div_curr_arsize) - 1, C_NARROW_BURST_CNT_LEN))
when (axi_byte_div_curr_arsize > 0)
else std_logic_vector (to_unsigned (0, C_NARROW_BURST_CNT_LEN));
---------------------------------------------------------------------------
-- Register narrow burst count load indicator
REG_NAR_BRST_CNT_LD: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
narrow_burst_cnt_ld_reg <= (others => '0');
elsif (bram_addr_ld_en = '1') then
narrow_burst_cnt_ld_reg <= narrow_burst_cnt_ld;
else
narrow_burst_cnt_ld_reg <= narrow_burst_cnt_ld_reg;
end if;
end if;
end process REG_NAR_BRST_CNT_LD;
---------------------------------------------------------------------------
end generate GEN_NARROW_CNT_LD;
----------------------------------------------------------------------------
-- Handling for WRAP burst types
--
-- For WRAP burst types, the counter value will roll over when the burst
-- boundary is reached.
-- Boundary is reached based on ARSIZE and ARLEN.
--
-- Goal is to minimize muxing on initial load of counter value.
-- On WRAP burst types, detect when the max address is reached.
-- When the max address is reached, re-load counter with lower
-- address value set to '0'.
----------------------------------------------------------------------------
-- Detect valid WRAP burst types
curr_wrap_burst <= '1' when (curr_arburst = C_AXI_BURST_WRAP) else '0';
curr_incr_burst <= '1' when (curr_arburst = C_AXI_BURST_INCR) else '0';
curr_fixed_burst <= '1' when (curr_arburst = C_AXI_BURST_FIXED) else '0';
----------------------------------------------------------------------------
-- Register curr_wrap_burst & curr_fixed_burst signals when BRAM
-- address counter is initially loaded
REG_CURR_BRST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
curr_wrap_burst_reg <= '0';
curr_fixed_burst_reg <= '0';
elsif (bram_addr_ld_en = '1') then
curr_wrap_burst_reg <= curr_wrap_burst;
curr_fixed_burst_reg <= curr_fixed_burst;
else
curr_wrap_burst_reg <= curr_wrap_burst_reg;
curr_fixed_burst_reg <= curr_fixed_burst_reg;
end if;
end if;
end process REG_CURR_BRST;
---------------------------------------------------------------------------
-- Instance: I_WRAP_BRST
--
-- Description:
--
-- Instantiate WRAP_BRST module
-- Logic to generate the wrap around value to load into the BRAM address
-- counter on WRAP burst transactions.
-- WRAP value is based on current ARLEN, ARSIZE (for narrows) and
-- data width of BRAM module.
--
---------------------------------------------------------------------------
I_WRAP_BRST : entity work.wrap_brst
generic map (
C_AXI_ADDR_WIDTH => C_AXI_ADDR_WIDTH ,
C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR ,
C_AXI_DATA_WIDTH => C_AXI_DATA_WIDTH
)
port map (
S_AXI_AClk => S_AXI_ACLK ,
S_AXI_AResetn => S_AXI_ARESETN ,
curr_axlen => curr_arlen ,
curr_axsize => curr_arsize ,
curr_narrow_burst => curr_narrow_burst ,
narrow_bram_addr_inc_re => narrow_bram_addr_inc_re ,
bram_addr_ld_en => bram_addr_ld_en ,
bram_addr_ld => bram_addr_ld ,
bram_addr_int => bram_addr_int ,
bram_addr_ld_wrap => bram_addr_ld_wrap ,
max_wrap_burst_mod => max_wrap_burst
);
----------------------------------------------------------------------------
-- Specify current ARBURST signal
-- Input address pipeline MUX
curr_arburst <= axi_arburst_pipe when (araddr_pipe_sel = '1') else AXI_ARBURST;
----------------------------------------------------------------------------
-- Specify current AWBURST signal
-- Input address pipeline MUX
curr_arlen <= axi_arlen_pipe when (araddr_pipe_sel = '1') else AXI_ARLEN;
----------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_UA_NARROW
-- Purpose: Only instantiate logic for burst narrow WRAP operations when
-- AXI bus protocol is not set for AXI-LITE and narrow
-- burst operations are supported.
--
---------------------------------------------------------------------------
GEN_UA_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
---------------------------------------------------------------------------
--
-- New logic to detect unaligned address on a narrow WRAP burst transaction.
-- If this condition is met, then the narrow burst counter will be
-- initially loaded with an offset value corresponding to the unalignment
-- in the ARADDR value.
--
--
-- Create a sub module for all logic to determine the narrow burst counter
-- offset value on unaligned WRAP burst operations.
--
-- Module generates the following signals:
--
-- => curr_ua_narrow_wrap, to indicate the current
-- operation is an unaligned narrow WRAP burst.
--
-- => curr_ua_narrow_incr, to load narrow burst counter
-- for unaligned INCR burst operations.
--
-- => ua_narrow_load, narrow counter load value.
-- Sized, (C_NARROW_BURST_CNT_LEN-1 downto 0)
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Instance: I_UA_NARROW
--
-- Description:
--
-- Creates a narrow burst count load value when an operation
-- is an unaligned narrow WRAP or INCR burst type. Used by
-- I_NARROW_CNT module.
--
-- Logic is customized for each C_AXI_DATA_WIDTH.
--
---------------------------------------------------------------------------
I_UA_NARROW : entity work.ua_narrow
generic map (
C_AXI_DATA_WIDTH => C_AXI_DATA_WIDTH ,
C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR ,
C_NARROW_BURST_CNT_LEN => C_NARROW_BURST_CNT_LEN
)
port map (
curr_wrap_burst => curr_wrap_burst , -- in
curr_incr_burst => curr_incr_burst , -- in
bram_addr_ld_en => bram_addr_ld_en , -- in
curr_axlen => curr_arlen , -- in
curr_axsize => curr_arsize , -- in
curr_axaddr_lsb => curr_araddr_lsb , -- in
curr_ua_narrow_wrap => curr_ua_narrow_wrap , -- out
curr_ua_narrow_incr => curr_ua_narrow_incr , -- out
ua_narrow_load => ua_narrow_load -- out
);
-- Use in all C_AXI_DATA_WIDTH generate statements
-- Only probe least significant BRAM address bits
-- C_BRAM_ADDR_ADJUST_FACTOR offset down to 0.
curr_araddr_lsb <= axi_araddr_pipe (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0)
when (araddr_pipe_sel = '1') else
AXI_ARADDR (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0);
end generate GEN_UA_NARROW;
----------------------------------------------------------------------------
--
-- New logic to detect if pending operation in ARADDR pipeline is
-- elgible for back-to-back no "bubble" performance. And BRAM address
-- counter can be loaded upon last BRAM address presented for the current
-- operation.
-- This condition exists when the ARADDR pipeline is full and the pending
-- operation is a burst >= length of two data beats.
-- And not a FIXED burst type (must be INCR or WRAP type).
-- The DATA SM handles detecting a throttle condition and will void
-- the capability to be a back-to-back in performance transaction.
--
-- Add check if new operation is a narrow burst (to be loaded into BRAM
-- counter)
-- Add check for throttling condition on after last BRAM address is
-- presented
--
----------------------------------------------------------------------------
-- v1.03a
rd_b2b_elgible_no_thr_check <= '1' when (axi_araddr_full = '1') and
(axi_arlen_pipe_1_or_2 /= '1') and
(axi_arburst_pipe_fixed /= '1') and
(disable_b2b_brst = '0') and
(axi_arsize_pipe_max = '1')
else '0';
rd_b2b_elgible <= '1' when (rd_b2b_elgible_no_thr_check = '1') and
(throttle_last_data = '0')
else '0';
-- Check if SM is in LAST_THROTTLE state which also indicates we are throttling at
-- the last data beat in the read burst. Ensures that the bursts are not implemented
-- as back-to-back bursts and RVALID will negate upon recognition of RLAST and RID
-- pipeline will be advanced properly.
-- Fix timing path on araddr_pipe_sel generated in RDADDR SM
-- SM uses rd_b2b_elgible signal which checks throttle condition on
-- last data beat to hold off loading new BRAM address counter for next
-- back-to-back operation.
-- Attempt to modify logic in generation of throttle_last_data signal.
throttle_last_data <= '1' when ((brst_zero = '1') and (rd_adv_buf = '0')) or
(rd_data_sm_cs = LAST_THROTTLE)
else '0';
----------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_AR_SNG
-- Purpose: If single port BRAM configuration, set all AR flags from
-- logic generated in sng_port_arb module.
--
---------------------------------------------------------------------------
GEN_AR_SNG: if (C_SINGLE_PORT_BRAM = 1) generate
begin
araddr_pipe_sel <= '0'; -- Unused in single port configuration
ar_active <= Arb2AR_Active;
bram_addr_ld_en <= ar_active_re;
brst_cnt_ld_en <= ar_active_re;
AR2Arb_Active_Clr <= axi_rlast_int and AXI_RREADY;
-- Rising edge detect of Arb2AR_Active
RE_AR_ACT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
-- Clear ar_active_d1 early w/ ar_active
-- So back to back ar_active assertions see the new transaction
-- and initiate the read transfer.
if (S_AXI_AResetn = C_RESET_ACTIVE) or ((axi_rlast_int and AXI_RREADY) = '1') then
ar_active_d1 <= '0';
else
ar_active_d1 <= ar_active;
end if;
end if;
end process RE_AR_ACT;
ar_active_re <= '1' when (ar_active = '1' and ar_active_d1 = '0') else '0';
end generate GEN_AR_SNG;
---------------------------------------------------------------------------
--
-- Generate: GEN_AW_DUAL
-- Purpose: Generate AW control state machine logic only when AXI4
-- controller is configured for dual port mode. In dual port
-- mode, wr_chnl has full access over AW & port A of BRAM.
--
---------------------------------------------------------------------------
GEN_AR_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate
begin
AR2Arb_Active_Clr <= '0'; -- Only used in single port case
---------------------------------------------------------------------------
-- RD ADDR State Machine
--
-- Description: Central processing unit for AXI write address
-- channel interface handling and handshaking.
--
-- Outputs: araddr_pipe_ld Not Registered
-- araddr_pipe_sel Not Registered
-- bram_addr_ld_en Not Registered
-- brst_cnt_ld_en Not Registered
-- ar_active_set Not Registered
--
-- WR_ADDR_SM_CMB_PROCESS: Combinational process to determine next state.
-- WR_ADDR_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
RD_ADDR_SM_CMB_PROCESS: process ( AXI_ARVALID,
axi_araddr_full,
ar_active,
no_ar_ack,
pend_rd_op,
last_bram_addr,
rd_b2b_elgible,
rd_addr_sm_cs )
begin
-- assign default values for state machine outputs
rd_addr_sm_ns <= rd_addr_sm_cs;
araddr_pipe_ld_i <= '0';
bram_addr_ld_en_i <= '0';
brst_cnt_ld_en_i <= '0';
ar_active_set_i <= '0';
case rd_addr_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- Reload BRAM address counter on last BRAM address of current burst
-- if a new address is pending in the AR pipeline and is elgible to
-- be loaded for subsequent back-to-back performance.
if (last_bram_addr = '1' and rd_b2b_elgible = '1') then
-- Load BRAM address counter from pipelined value
bram_addr_ld_en_i <= '1';
brst_cnt_ld_en_i <= '1';
ar_active_set_i <= '1';
-- If loading BRAM counter for subsequent operation
-- AND ARVALID is pending on the bus, go ahead and respond
-- and fill ARADDR pipeline with next operation.
--
-- Asserting the signal to load the ARADDR pipeline here
-- allows the full bandwidth utilization to BRAM on
-- back to back bursts of two data beats.
if (AXI_ARVALID = '1') then
araddr_pipe_ld_i <= '1';
rd_addr_sm_ns <= LD_ARADDR;
else
rd_addr_sm_ns <= IDLE;
end if;
elsif (AXI_ARVALID = '1') then
-- If address pipeline is full
-- ARReady output is negated
-- Remain in this state
--
-- Add check for already pending read operation
-- in data SM, but waiting on throttle (even though ar_active is
-- already set to '0').
if (ar_active = '0') and (no_ar_ack = '0') and (pend_rd_op = '0') then
rd_addr_sm_ns <= IDLE;
bram_addr_ld_en_i <= '1';
brst_cnt_ld_en_i <= '1';
ar_active_set_i <= '1';
-- Address counter is currently busy
else
-- Check if ARADDR pipeline is not full and can be loaded
if (axi_araddr_full = '0') then
rd_addr_sm_ns <= LD_ARADDR;
araddr_pipe_ld_i <= '1';
end if;
end if; -- ar_active
-- Pending operation in pipeline that is waiting
-- until current operation is complete (ar_active = '0')
elsif (axi_araddr_full = '1') and
(ar_active = '0') and
(no_ar_ack = '0') and
(pend_rd_op = '0') then
rd_addr_sm_ns <= IDLE;
-- Load BRAM address counter from pipelined value
bram_addr_ld_en_i <= '1';
brst_cnt_ld_en_i <= '1';
ar_active_set_i <= '1';
end if; -- ARVALID
---------------------------- LD_ARADDR State ---------------------------
when LD_ARADDR =>
-- Check here for subsequent BRAM address load when ARADDR pipe is loaded
-- in previous clock cycle.
--
-- Reload BRAM address counter on last BRAM address of current burst
-- if a new address is pending in the AR pipeline and is elgible to
-- be loaded for subsequent back-to-back performance.
if (last_bram_addr = '1' and rd_b2b_elgible = '1') then
-- Load BRAM address counter from pipelined value
bram_addr_ld_en_i <= '1';
brst_cnt_ld_en_i <= '1';
ar_active_set_i <= '1';
-- If loading BRAM counter for subsequent operation
-- AND ARVALID is pending on the bus, go ahead and respond
-- and fill ARADDR pipeline with next operation.
--
-- Asserting the signal to load the ARADDR pipeline here
-- allows the full bandwidth utilization to BRAM on
-- back to back bursts of two data beats.
if (AXI_ARVALID = '1') then
araddr_pipe_ld_i <= '1';
rd_addr_sm_ns <= LD_ARADDR;
-- Stay in this state another clock cycle
else
rd_addr_sm_ns <= IDLE;
end if;
else
rd_addr_sm_ns <= IDLE;
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
rd_addr_sm_ns <= IDLE;
--coverage on
end case;
end process RD_ADDR_SM_CMB_PROCESS;
---------------------------------------------------------------------------
-- CR # 582705
-- Ensure combinatorial SM output signals do not get set before
-- the end of the reset (and ARREAADY can be set).
bram_addr_ld_en <= bram_addr_ld_en_i and axi_aresetn_d2;
brst_cnt_ld_en <= brst_cnt_ld_en_i and axi_aresetn_d2;
ar_active_set <= ar_active_set_i and axi_aresetn_d2;
araddr_pipe_ld <= araddr_pipe_ld_i and axi_aresetn_d2;
RD_ADDR_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- if (S_AXI_AResetn = C_RESET_ACTIVE) then
-- CR # 582705
-- Ensure that ar_active does not get asserted (from SM) before
-- the end of reset and the ARREADY flag is set.
if (axi_aresetn_d2 = C_RESET_ACTIVE) then
rd_addr_sm_cs <= IDLE;
else
rd_addr_sm_cs <= rd_addr_sm_ns;
end if;
end if;
end process RD_ADDR_SM_REG_PROCESS;
---------------------------------------------------------------------------
-- Assert araddr_pipe_sel outside of SM logic
-- The BRAM address counter will get loaded with value in ARADDR pipeline
-- when data is stored in the ARADDR pipeline.
araddr_pipe_sel <= '1' when (axi_araddr_full = '1') else '0';
---------------------------------------------------------------------------
-- Register for ar_active
REG_AR_ACT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- if (S_AXI_AResetn = C_RESET_ACTIVE) then
-- CR # 582705
if (axi_aresetn_d2 = C_RESET_ACTIVE) then
ar_active <= '0';
elsif (ar_active_set = '1') then
ar_active <= '1';
-- For code coverage closure, ensure priority encoding in if/else clause
-- to prevent checking ar_active_set in reset clause.
elsif (ar_active_clr = '1') then
ar_active <= '0';
else
ar_active <= ar_active;
end if;
end if;
end process REG_AR_ACT;
end generate GEN_AR_DUAL;
---------------------------------------------------------------------------
--
-- REG_BRST_CNT.
-- Read Burst Counter.
-- No need to decrement burst counter.
-- Able to load with fixed burst length value.
-- Replace usage of proc_common_v4_0 library with direct HDL.
--
-- Size of counter = C_BRST_CNT_SIZE
-- Max size of burst transfer = 256 data beats
--
---------------------------------------------------------------------------
REG_BRST_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (brst_cnt_rst = '1') then
brst_cnt <= (others => '0');
-- Load burst counter
elsif (brst_cnt_ld_en = '1') then
brst_cnt <= brst_cnt_ld;
-- Decrement ONLY (no increment functionality)
elsif (brst_cnt_dec = '1') then
brst_cnt (C_BRST_CNT_SIZE-1 downto 0) <=
std_logic_vector (unsigned (brst_cnt (C_BRST_CNT_SIZE-1 downto 0)) - 1);
end if;
end if;
end process REG_BRST_CNT;
---------------------------------------------------------------------------
brst_cnt_rst <= not (S_AXI_AResetn);
-- Determine burst count load value
-- Either load BRAM counter directly from AXI bus or from stored registered value.
-- Use mux signal for ARLEN
BRST_CNT_LD_PROCESS : process (curr_arlen)
variable brst_cnt_ld_int : integer := 0;
begin
brst_cnt_ld_int := to_integer (unsigned (curr_arlen (7 downto 0)));
brst_cnt_ld <= std_logic_vector (to_unsigned (brst_cnt_ld_int, 8));
end process BRST_CNT_LD_PROCESS;
----------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_BRST_MAX_W_NARROW
-- Purpose: Generate registered logic for brst_cnt_max when the
-- design instantiation supports narrow operations.
--
---------------------------------------------------------------------------
GEN_BRST_MAX_W_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
REG_BRST_MAX: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or (brst_cnt_ld_en = '1')
-- Added with single port (13.1 release)
or (end_brst_rd_clr = '1') then
brst_cnt_max <= '0';
-- Replace usage of brst_cnt in this logic.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
elsif (brst_zero = '1') and (ar_active = '1') and (pend_rd_op = '0') then
-- Hold off assertion of brst_cnt_max on narrow burst transfers
-- Must wait until narrow burst count = 0.
if (curr_narrow_burst = '1') then
if (narrow_bram_addr_inc = '1') then
brst_cnt_max <= '1';
end if;
else
brst_cnt_max <= '1';
end if;
else
brst_cnt_max <= brst_cnt_max;
end if;
end if;
end process REG_BRST_MAX;
end generate GEN_BRST_MAX_W_NARROW;
---------------------------------------------------------------------------
--
-- Generate: GEN_BRST_MAX_WO_NARROW
-- Purpose: Generate registered logic for brst_cnt_max when the
-- design instantiation does not support narrow operations.
--
---------------------------------------------------------------------------
GEN_BRST_MAX_WO_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 0) generate
begin
REG_BRST_MAX: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or (brst_cnt_ld_en = '1') then
brst_cnt_max <= '0';
-- Replace usage of brst_cnt in this logic.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
elsif (brst_zero = '1') and (ar_active = '1') and (pend_rd_op = '0') then
-- When narrow operations are not supported in the core
-- configuration, no check for curr_narrow_burst on assertion.
brst_cnt_max <= '1';
else
brst_cnt_max <= brst_cnt_max;
end if;
end if;
end process REG_BRST_MAX;
end generate GEN_BRST_MAX_WO_NARROW;
---------------------------------------------------------------------------
REG_BRST_MAX_D1: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
brst_cnt_max_d1 <= '0';
else
brst_cnt_max_d1 <= brst_cnt_max;
end if;
end if;
end process REG_BRST_MAX_D1;
brst_cnt_max_re <= '1' when (brst_cnt_max = '1') and (brst_cnt_max_d1 = '0') else '0';
-- Set flag that end of burst is reached
-- Need to capture this condition as the burst
-- counter may get reloaded for a subsequent read burst
REG_END_BURST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- SM may assert clear flag early (in case of narrow bursts)
-- Wait until the end_brst_rd flag is asserted to clear the flag.
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(end_brst_rd_clr = '1' and end_brst_rd = '1') then
end_brst_rd <= '0';
elsif (brst_cnt_max_re = '1') then
end_brst_rd <= '1';
end if;
end if;
end process REG_END_BURST;
---------------------------------------------------------------------------
-- Create flag that indicates burst counter is reaching ZEROs (max of burst
-- length)
REG_BURST_ZERO: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
((brst_cnt_ld_en = '1') and (brst_cnt_ld /= C_BRST_CNT_ZERO)) then
brst_zero <= '0';
elsif (brst_cnt_dec = '1') and (brst_cnt = C_BRST_CNT_ONE) then
brst_zero <= '1';
else
brst_zero <= brst_zero;
end if;
end if;
end process REG_BURST_ZERO;
---------------------------------------------------------------------------
-- Create additional flag that indicates burst counter is reaching ONEs
-- (near end of burst length). Used to disable back-to-back condition in SM.
REG_BURST_ONE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
((brst_cnt_ld_en = '1') and (brst_cnt_ld /= C_BRST_CNT_ONE)) or
((brst_cnt_dec = '1') and (brst_cnt = C_BRST_CNT_ONE)) then
brst_one <= '0';
elsif ((brst_cnt_dec = '1') and (brst_cnt = C_BRST_CNT_TWO)) or
((brst_cnt_ld_en = '1') and (brst_cnt_ld = C_BRST_CNT_ONE)) then
brst_one <= '1';
else
brst_one <= brst_one;
end if;
end if;
end process REG_BURST_ONE;
---------------------------------------------------------------------------
-- Register flags for read burst operation
REG_RD_BURST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- Clear axi_rd_burst flags when burst count gets to zeros (unless the burst
-- counter is getting subsequently loaded for the new burst operation)
--
-- Replace usage of brst_cnt in this logic.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
if (S_AXI_AResetn = C_RESET_ACTIVE) or (brst_zero = '1' and brst_cnt_ld_en = '0') then
axi_rd_burst <= '0';
axi_rd_burst_two <= '0';
elsif (brst_cnt_ld_en = '1') then
if (curr_arlen /= AXI_ARLEN_ONE and curr_arlen /= AXI_ARLEN_TWO) then
axi_rd_burst <= '1';
else
axi_rd_burst <= '0';
end if;
if (curr_arlen = AXI_ARLEN_TWO) then
axi_rd_burst_two <= '1';
else
axi_rd_burst_two <= '0';
end if;
else
axi_rd_burst <= axi_rd_burst;
axi_rd_burst_two <= axi_rd_burst_two;
end if;
end if;
end process REG_RD_BURST;
---------------------------------------------------------------------------
-- Seeing issue with axi_rd_burst getting cleared too soon
-- on subsquent brst_cnt_ld_en early assertion and pend_rd_op is asserted.
-- Create flag for currently active read burst operation
-- Gets asserted when burst counter is loaded, but does not
-- get cleared until the RD_DATA_SM has completed the read
-- burst operation
REG_ACT_RD_BURST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or (act_rd_burst_clr = '1') then
act_rd_burst <= '0';
act_rd_burst_two <= '0';
elsif (act_rd_burst_set = '1') then
-- If not loading the burst counter for a B2B operation
-- Then act_rd_burst follows axi_rd_burst and
-- act_rd_burst_two follows axi_rd_burst_two.
-- Get registered value of axi_* signal.
if (brst_cnt_ld_en = '0') then
act_rd_burst <= axi_rd_burst;
act_rd_burst_two <= axi_rd_burst_two;
else
-- Otherwise, duplicate logic for axi_* signals if burst counter
-- is getting loaded.
-- For improved code coverage here
-- The act_rd_burst_set signal will never get asserted if the burst
-- size is less than two data beats. So, the conditional check
-- for (curr_arlen /= AXI_ARLEN_ONE) is never evaluated. Removed
-- from this if clause.
if (curr_arlen /= AXI_ARLEN_TWO) then
act_rd_burst <= '1';
else
act_rd_burst <= '0';
end if;
if (curr_arlen = AXI_ARLEN_TWO) then
act_rd_burst_two <= '1';
else
act_rd_burst_two <= '0';
end if;
-- Note: re-code this if/else clause.
end if;
else
act_rd_burst <= act_rd_burst;
act_rd_burst_two <= act_rd_burst_two;
end if;
end if;
end process REG_ACT_RD_BURST;
---------------------------------------------------------------------------
rd_adv_buf <= axi_rvalid_int and AXI_RREADY;
---------------------------------------------------------------------------
-- RD DATA State Machine
--
-- Description: Central processing unit for AXI write data
-- channel interface handling and AXI write data response
-- handshaking.
--
-- Outputs: Name Type
--
-- bram_en_int Registered
-- bram_addr_inc Not Registered
-- brst_cnt_dec Not Registered
-- rddata_mux_sel Registered
-- axi_rdata_en Not Registered
-- axi_rvalid_set Registered
--
--
-- RD_DATA_SM_CMB_PROCESS: Combinational process to determine next state.
-- RD_DATA_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
RD_DATA_SM_CMB_PROCESS: process ( bram_addr_ld_en,
rd_adv_buf,
ar_active,
axi_araddr_full,
rd_b2b_elgible_no_thr_check,
disable_b2b_brst,
curr_arlen,
axi_rd_burst,
axi_rd_burst_two,
act_rd_burst,
act_rd_burst_two,
end_brst_rd,
brst_zero,
brst_one,
axi_b2b_brst,
bram_en_int,
rddata_mux_sel,
end_brst_rd_clr,
no_ar_ack,
pend_rd_op,
axi_rlast_int,
rd_data_sm_cs )
begin
-- assign default values for state machine outputs
rd_data_sm_ns <= rd_data_sm_cs;
bram_en_cmb <= bram_en_int;
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
rd_skid_buf_ld_cmb <= '0';
rd_skid_buf_ld_imm <= '0';
rddata_mux_sel_cmb <= rddata_mux_sel;
-- Change axi_rdata_en generated from SM to be a combinatorial signal
-- Can't afford the latency when throttling on the AXI bus.
axi_rdata_en <= '0';
axi_rvalid_set_cmb <= '0';
end_brst_rd_clr_cmb <= end_brst_rd_clr;
no_ar_ack_cmb <= no_ar_ack;
pend_rd_op_cmb <= pend_rd_op;
act_rd_burst_set <= '0';
act_rd_burst_clr <= '0';
set_last_bram_addr <= '0';
alast_bram_addr <= '0';
axi_b2b_brst_cmb <= axi_b2b_brst;
disable_b2b_brst_cmb <= disable_b2b_brst;
ar_active_clr <= '0';
case rd_data_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- Initiate BRAM read when address is available in controller
-- Indicated by load of BRAM address counter
-- Remove use of pend_rd_op signal.
-- Never asserted as we transition back to IDLE
-- Detected in code coverage
if (bram_addr_ld_en = '1') then
-- At start of new read, clear end burst signal
end_brst_rd_clr_cmb <= '0';
-- Initiate BRAM read transfer
bram_en_cmb <= '1';
-- Only count addresses & burst length for read
-- burst operations
-- If currently loading BRAM address counter
-- Must check curr_arlen (mux output from pipe or AXI bus)
-- to determine length of next operation.
-- If ARLEN = 1 data beat, then set last_bram_addr signal
-- Otherwise, increment BRAM address counter.
if (curr_arlen /= AXI_ARLEN_ONE) then
-- Start of new operation, update act_rd_burst and
-- act_rd_burst_two signals
act_rd_burst_set <= '1';
else
-- Set flag for last_bram_addr on transition
-- to SNG_ADDR on single operations.
set_last_bram_addr <= '1';
end if;
-- Go to single active read address state
rd_data_sm_ns <= SNG_ADDR;
end if;
------------------------- SNG_ADDR State --------------------------
when SNG_ADDR =>
-- Clear flag once pending read is recognized
-- Duplicate logic here in case combinatorial flag was getting
-- set as the SM transitioned into this state.
if (pend_rd_op = '1') then
pend_rd_op_cmb <= '0';
end if;
-- At start of new read, clear end burst signal
end_brst_rd_clr_cmb <= '0';
-- Reach this state on first BRAM address & enable assertion
-- For burst operation, create next BRAM address and keep enable
-- asserted
-- Note:
-- No ability to throttle yet as RVALID has not yet been
-- asserted on the AXI bus
-- Reset data mux select between skid buffer and BRAM
-- Ensure read data mux is set for BRAM data
rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM;
-- Assert RVALID on AXI when 1st data beat available
-- from BRAM
axi_rvalid_set_cmb <= '1';
-- Reach this state when BRAM address counter is loaded
-- Use axi_rd_burst and axi_rd_burst_two to indicate if
-- operation is a single data beat burst.
if (axi_rd_burst = '0') and (axi_rd_burst_two = '0') then
-- Proceed directly to get BRAM read data
rd_data_sm_ns <= LAST_ADDR;
-- End of active current read address
ar_active_clr <= '1';
-- Negate BRAM enable
bram_en_cmb <= '0';
-- Load read data skid buffer for BRAM capture
-- in next clock cycle
rd_skid_buf_ld_cmb <= '1';
-- Assert new flag to disable back-to-back bursts
-- due to throttling
disable_b2b_brst_cmb <= '1';
-- Set flag for pending operation if bram_addr_ld_en is asserted (BRAM
-- address is loaded) and we are waiting for the current read burst to complete.
if (bram_addr_ld_en = '1') then
pend_rd_op_cmb <= '1';
end if;
-- Read burst
else
-- Increment BRAM address counter (2nd data beat)
bram_addr_inc <= '1';
-- Decrement BRAM burst counter (2nd data beat)
brst_cnt_dec <= '1';
-- Keep BRAM enable asserted
bram_en_cmb <= '1';
rd_data_sm_ns <= SEC_ADDR;
-- Load read data skid buffer for BRAM capture
-- in next clock cycle
rd_skid_buf_ld_cmb <= '1';
-- Start of new operation, update act_rd_burst and
-- act_rd_burst_two signals
act_rd_burst_set <= '1';
-- If new burst is 2 data beats
-- Then disable capability on back-to-back bursts
if (axi_rd_burst_two = '1') then
-- Assert new flag to disable back-to-back bursts
-- due to throttling
disable_b2b_brst_cmb <= '1';
else
-- Support back-to-back for all other burst lengths
disable_b2b_brst_cmb <= '0';
end if;
end if;
------------------------- SEC_ADDR State --------------------------
when SEC_ADDR =>
-- Reach this state when the 2nd incremented address of the burst
-- is presented to the BRAM.
-- Only reach this state when axi_rd_burst = '1',
-- an active read burst.
-- Note:
-- No ability to throttle yet as RVALID has not yet been
-- asserted on the AXI bus
-- Enable AXI read data register
axi_rdata_en <= '1';
-- Only in dual port mode can the address counter get loaded early
if C_SINGLE_PORT_BRAM = 0 then
-- If we see the next address get loaded into the BRAM counter
-- then set flag for pending operation
if (bram_addr_ld_en = '1') then
pend_rd_op_cmb <= '1';
end if;
end if;
-- Check here for burst length of two data transfers
-- If so, then the SM will NOT hit the condition of a full
-- pipeline:
-- Operation A) 1st BRAM address data on AXI bus
-- Operation B) 2nd BRAm address data read from BRAM
-- Operation C) 3rd BRAM address presented to BRAM
--
-- Full pipeline condition is hit for any read burst
-- length greater than 2 data beats.
if (axi_rd_burst_two = '1') then
-- No increment of BRAM address
-- or decrement of burst counter
-- Burst counter should be = zero
rd_data_sm_ns <= LAST_ADDR;
-- End of active current read address
ar_active_clr <= '1';
-- Ensure read data mux is set for BRAM data
rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM;
-- Negate BRAM enable
bram_en_cmb <= '0';
-- Load read data skid buffer for BRAM capture
-- in next clock cycle.
-- This signal will negate in the next state
-- if the data is not accepted on the AXI bus.
-- So that no new data from BRAM is registered into the
-- read channel controller.
rd_skid_buf_ld_cmb <= '1';
else
-- Burst length will hit full pipeline condition
-- Increment BRAM address counter (3rd data beat)
bram_addr_inc <= '1';
-- Decrement BRAM burst counter (3rd data beat)
brst_cnt_dec <= '1';
-- Keep BRAM enable asserted
bram_en_cmb <= '1';
rd_data_sm_ns <= FULL_PIPE;
-- Assert almost last BRAM address flag
-- so that ARVALID logic output can remain registered
--
-- Replace usage of brst_cnt with signal, brst_one.
if (brst_one = '1') then
alast_bram_addr <= '1';
end if;
-- Load read data skid buffer for BRAM capture
-- in next clock cycle
rd_skid_buf_ld_cmb <= '1';
end if; -- ARLEN = "0000 0001"
------------------------- FULL_PIPE State -------------------------
when FULL_PIPE =>
-- Reach this state when all three data beats in the burst
-- are active
--
-- Operation A) 1st BRAM address data on AXI bus
-- Operation B) 2nd BRAM address data read from BRAM
-- Operation C) 3rd BRAM address presented to BRAM
-- Ensure read data mux is set for BRAM data
rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM;
-- With new pipelining capability BRAM address counter may be
-- loaded in this state. This only occurs on back-to-back
-- bursts (when enabled).
-- No flag set for pending operation.
-- Modify the if clause here to check for back-to-back burst operations
-- If we load the BRAM address in this state for a subsequent burst, then
-- this condition indicates a back-to-back burst and no need to assert
-- the pending read operation flag.
-- Seeing corner case when pend_rd_op needs to be asserted and cleared
-- in this state. If the BRAM address counter is loaded early, but
-- axi_rlast_set is delayed in getting asserted (all while in this state).
-- The signal, curr_narrow_burst can not get cleared.
-- Only in dual port mode can the address counter get loaded early
if C_SINGLE_PORT_BRAM = 0 then
-- Set flag for pending operation if bram_addr_ld_en is asserted (BRAM
-- address is loaded) and we are waiting for the current read burst to complete.
if (bram_addr_ld_en = '1') then
pend_rd_op_cmb <= '1';
-- Clear flag once pending read is recognized and
-- earlier read data phase is complete.
elsif (pend_rd_op = '1') and (axi_rlast_int = '1') then
pend_rd_op_cmb <= '0';
end if;
end if;
-- Check AXI throttling condition
-- If AXI bus advances and accepts read data, SM can
-- proceed with next data beat of burst.
-- If not, then go to FULL_THROTTLE state to wait for
-- AXI_RREADY = '1'.
if (rd_adv_buf = '1') then
-- Assert AXI read data enable for BRAM capture
axi_rdata_en <= '1';
-- Load read data skid buffer for BRAM capture in next clock cycle
rd_skid_buf_ld_cmb <= '1';
-- Assert almost last BRAM address flag
-- so that ARVALID logic output can remain registered
--
-- Replace usage of brst_cnt with signal, brst_one.
if (brst_one = '1') then
alast_bram_addr <= '1';
end if;
-- Check burst counter for max
-- If max burst count is reached, no new addresses
-- presented to BRAM, advance to last capture data states.
--
-- For timing, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
if (brst_zero = '1') or (end_brst_rd = '1' and axi_b2b_brst = '0') then
-- Check for elgible pending read operation to support back-to-back performance.
-- If so, load BRAM address counter.
--
-- Replace rd_b2b_elgible signal check to remove path from
-- arlen_pipe through rd_b2b_elgible
-- (with data throttle check)
if (rd_b2b_elgible_no_thr_check = '1') then
rd_data_sm_ns <= FULL_PIPE;
-- Set flag to indicate back-to-back read burst
-- RVALID will not clear in this case and remain asserted
axi_b2b_brst_cmb <= '1';
-- Set flag to update active read burst or
-- read burst of two flag
act_rd_burst_set <= '1';
-- Otherwise, complete current transaction
else
-- No increment of BRAM address
-- or decrement of burst counter
-- Burst counter should be = zero
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
rd_data_sm_ns <= LAST_ADDR;
-- Negate BRAM enable
bram_en_cmb <= '0';
-- End of active current read address
ar_active_clr <= '1';
end if;
else
-- Remain in this state until burst count reaches zero
-- Increment BRAM address counter (Nth data beat)
bram_addr_inc <= '1';
-- Decrement BRAM burst counter (Nth data beat)
brst_cnt_dec <= '1';
-- Keep BRAM enable asserted
bram_en_cmb <= '1';
-- Skid buffer load will remain asserted
-- AXI read data register is asserted
end if;
else
-- Throttling condition detected
rd_data_sm_ns <= FULL_THROTTLE;
-- Ensure that AXI read data output register is disabled
-- due to throttle condition.
axi_rdata_en <= '0';
-- Skid buffer gets loaded from BRAM read data in next clock
-- cycle ONLY.
-- Only on transition to THROTTLE state does skid buffer get loaded.
-- Negate load of read data skid buffer for BRAM capture
-- in next clock cycle due to detection of Throttle condition
rd_skid_buf_ld_cmb <= '0';
-- BRAM address is NOT getting incremented
-- (same for burst counter)
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
-- If transitioning to throttle state
-- Then next register enable assertion of the AXI read data
-- output register needs to come from the skid buffer
-- Set read data mux select here for SKID_BUFFER data
rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF;
-- Detect if at end of burst read as we transition to FULL_THROTTLE
-- If so, negate the BRAM enable even if prior to throttle condition
-- on AXI bus. Read skid buffer will hold last beat of data in burst.
--
-- For timing purposes, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
if (brst_zero = '1') or (end_brst_rd = '1') then
-- No back to back "non bubble" support when AXI master
-- is throttling on current burst.
-- Seperate signal throttle_last_data will be asserted outside SM.
-- End of burst read, negate BRAM enable
bram_en_cmb <= '0';
-- Assert new flag to disable back-to-back bursts
-- due to throttling
disable_b2b_brst_cmb <= '1';
-- Disable B2B capability if throttling detected when
-- burst count is equal to one.
--
-- For timing purposes, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_one, indicating the
-- brst_cnt to be one when decrement.
elsif (brst_one = '1') then
-- Assert new flag to disable back-to-back bursts
-- due to throttling
disable_b2b_brst_cmb <= '1';
-- Throttle, but not end of burst
else
bram_en_cmb <= '1';
end if;
end if; -- rd_adv_buf (RREADY throttle)
------------------------- FULL_THROTTLE State ---------------------
when FULL_THROTTLE =>
-- Reach this state when the AXI bus throttles on the AXI data
-- beat read from BRAM (when the read pipeline is fully active)
-- Flag disable_b2b_brst_cmb should be asserted as we transition
-- to this state. Flag is asserted near the end of a read burst
-- to prevent the back-to-back performance pipelining in the BRAM
-- address counter.
-- Detect if at end of burst read
-- If so, negate the BRAM enable even if prior to throttle condition
-- on AXI bus. Read skid buffer will hold last beat of data in burst.
--
-- For timing, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
if (brst_zero = '1') or (end_brst_rd = '1') then
bram_en_cmb <= '0';
end if;
-- Set new flag for pending operation if bram_addr_ld_en is asserted (BRAM
-- address is loaded) and we are waiting for the current read burst to complete.
if (bram_addr_ld_en = '1') then
pend_rd_op_cmb <= '1';
-- Clear flag once pending read is recognized and
-- earlier read data phase is complete.
elsif (pend_rd_op = '1') and (axi_rlast_int = '1') then
pend_rd_op_cmb <= '0';
end if;
-- Wait for RREADY to be asserted w/ RVALID on AXI bus
if (rd_adv_buf = '1') then
-- Ensure read data mux is set for skid buffer data
rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF;
-- Ensure that AXI read data output register is enabled
axi_rdata_en <= '1';
-- Must reload skid buffer here from BRAM data
-- so if needed can be presented to AXI bus on the following clock cycle
rd_skid_buf_ld_imm <= '1';
-- When detecting end of throttle condition
-- Check first if burst count is complete
-- Check burst counter for max
-- If max burst count is reached, no new addresses
-- presented to BRAM, advance to last capture data states.
--
-- For timing, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
if (brst_zero = '1') or (end_brst_rd = '1') then
-- No back-to-back performance when AXI master throttles
-- If we reach the end of the burst, proceed to LAST_ADDR state.
-- No increment of BRAM address
-- or decrement of burst counter
-- Burst counter should be = zero
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
rd_data_sm_ns <= LAST_ADDR;
-- Negate BRAM enable
bram_en_cmb <= '0';
-- End of active current read address
ar_active_clr <= '1';
-- Not end of current burst w/ throttle condition
else
-- Go back to FULL_PIPE
rd_data_sm_ns <= FULL_PIPE;
-- Assert almost last BRAM address flag
-- so that ARVALID logic output can remain registered
--
-- For timing purposes, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_one, indicating the
-- brst_cnt to be one when decrement.
if (brst_one = '1') then
alast_bram_addr <= '1';
end if;
-- Increment BRAM address counter (Nth data beat)
bram_addr_inc <= '1';
-- Decrement BRAM burst counter (Nth data beat)
brst_cnt_dec <= '1';
-- Keep BRAM enable asserted
bram_en_cmb <= '1';
end if; -- Burst Max
else
-- Stay in this state
-- Ensure that AXI read data output register is disabled
-- due to throttle condition.
axi_rdata_en <= '0';
-- Ensure that skid buffer is not getting loaded with
-- current read data from BRAM
rd_skid_buf_ld_cmb <= '0';
-- BRAM address is NOT getting incremented
-- (same for burst counter)
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
end if; -- rd_adv_buf (RREADY throttle)
------------------------- LAST_ADDR State -------------------------
when LAST_ADDR =>
-- Reach this state in the clock cycle following the last address
-- presented to the BRAM. Capture the last BRAM data beat in the
-- next clock cycle.
--
-- Data is presented to AXI bus (if no throttling detected) and
-- loaded into the skid buffer.
-- If we reach this state after back to back burst transfers
-- then clear the flag to ensure that RVALID will clear when RLAST
-- is recognized
if (axi_b2b_brst = '1') then
axi_b2b_brst_cmb <= '0';
end if;
-- Clear flag that indicates end of read burst
-- Once we reach this state, we have recognized the burst complete.
--
-- It is getting asserted too early
-- and recognition of the end of the burst is missed when throttling
-- on the last two data beats in the read.
end_brst_rd_clr_cmb <= '1';
-- Set new flag for pending operation if ar_active is asserted (BRAM
-- address has already been loaded) and we are waiting for the current
-- read burst to complete. If those two conditions apply, set this flag.
-- For dual port, support checking for early writes into BRAM address counter
if (C_SINGLE_PORT_BRAM = 0) and ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then
-- Support back-to-backs for single AND dual port modes.
-- if ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then
-- if (ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1') then
pend_rd_op_cmb <= '1';
end if;
-- Load read data skid buffer for BRAM is asserted on transition
-- into this state. Only gets negated if done with operation
-- as detected in below if clause.
-- Check flag for no subsequent operations
-- Clear that now, with current operation completing
if (no_ar_ack = '1') then
no_ar_ack_cmb <= '0';
end if;
-- Check for single AXI read operations
-- If so, wait for RREADY to be asserted
-- Check for burst and bursts of two as seperate signals.
if (act_rd_burst = '0') and (act_rd_burst_two = '0') then
-- Create rvalid_set to only be asserted for a single clock
-- cycle.
-- Will get set as transitioning to LAST_ADDR on single read operations
-- Only assert RVALID here on single operations
-- Enable AXI read data register
axi_rdata_en <= '1';
-- Data will not yet be acknowledged on AXI
-- in this state.
-- Go to wait for last data beat
rd_data_sm_ns <= LAST_DATA;
-- Set read data mux select for SKID BUF
rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF;
else
-- Only check throttling on AXI during read data burst operations
-- Check AXI throttling condition
-- If AXI bus advances and accepts read data, SM can
-- proceed with next data beat.
-- If not, then go to LAST_THROTTLE state to wait for
-- AXI_RREADY = '1'.
if (rd_adv_buf = '1') then
-- Assert AXI read data enable for BRAM capture
-- in next clock cycle
-- Enable AXI read data register
axi_rdata_en <= '1';
-- Ensure read data mux is set for BRAM data
rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM;
-- Burst counter already at zero. Reached this state due to NO
-- pending ARADDR in the read address pipeline. However, check
-- here for any new read addresses.
-- New ARADDR detected and loaded into BRAM address counter
-- Add check here for previously loaded BRAM address
-- ar_active will be asserted (and qualify that with the
-- condition that the read burst is complete, for narrow reads).
if (bram_addr_ld_en = '1') then
-- Initiate BRAM read transfer
bram_en_cmb <= '1';
-- Instead of transitioning to SNG_ADDR
-- go to wait for last data beat.
rd_data_sm_ns <= LAST_DATA_AR_PEND;
else
-- No pending read address to initiate next read burst
-- Go to capture last data beat from BRAM and present on AXI bus.
rd_data_sm_ns <= LAST_DATA;
end if; -- bram_addr_ld_en (New read burst)
else
-- Throttling condition detected
rd_data_sm_ns <= LAST_THROTTLE;
-- Ensure that AXI read data output register is disabled
-- due to throttle condition.
axi_rdata_en <= '0';
-- Skid buffer gets loaded from BRAM read data in next clock
-- cycle ONLY.
-- Only on transition to THROTTLE state does skid buffer get loaded.
-- Set read data mux select for SKID BUF
rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF;
end if; -- rd_adv_buf (RREADY throttle)
end if; -- AXI read burst
------------------------- LAST_THROTTLE State ---------------------
when LAST_THROTTLE =>
-- Reach this state when the AXI bus throttles on the last data
-- beat read from BRAM
-- Data to be sourced from read skid buffer
-- Add check in LAST_THROTTLE as well as LAST_ADDR
-- as we may miss the setting of this flag for a subsequent operation.
-- For dual port, support checking for early writes into BRAM address counter
if (C_SINGLE_PORT_BRAM = 0) and ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then
-- Support back-to-back for single AND dual port modes.
-- if ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then
pend_rd_op_cmb <= '1';
end if;
-- Wait for RREADY to be asserted w/ RVALID on AXI bus
if (rd_adv_buf = '1') then
-- Assert AXI read data enable for BRAM capture
axi_rdata_en <= '1';
-- Set read data mux select for SKID BUF
rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF;
-- No pending read address to initiate next read burst
-- Go to capture last data beat from BRAM and present on AXI bus.
rd_data_sm_ns <= LAST_DATA;
-- Load read data skid buffer for BRAM capture in next clock cycle
-- of last data read
-- Read Skid buffer already loaded with last data beat from BRAM
-- Does not need to be asserted again in this state
else
-- Stay in this state
-- Ensure that AXI read data output register is disabled
axi_rdata_en <= '0';
-- Ensure that skid buffer is not getting loaded with
-- current read data from BRAM
rd_skid_buf_ld_cmb <= '0';
-- BRAM address is NOT getting incremented
-- (same for burst counter)
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
-- Keep RVALID asserted on AXI
-- No need to assert RVALID again
end if; -- rd_adv_buf (RREADY throttle)
------------------------- LAST_DATA State -------------------------
when LAST_DATA =>
-- Reach this state when last BRAM data beat is
-- presented on AXI bus.
-- For a read burst, RLAST is not asserted until SM reaches
-- this state.
-- Ok to accept new operation if throttling detected
-- during current operation (and flag was previously set
-- to disable the back-to-back performance).
disable_b2b_brst_cmb <= '0';
-- Stay in this state until RREADY is asserted on AXI bus
-- Indicated by assertion of rd_adv_buf
if (rd_adv_buf = '1') then
-- Last data beat acknowledged on AXI bus
-- Check for new read burst or proceed back to IDLE
-- New ARADDR detected and loaded into BRAM address counter
-- Note: this condition may occur when C_SINGLE_PORT_BRAM = 0 or 1
if (bram_addr_ld_en = '1') or (pend_rd_op = '1') then
-- Clear flag once pending read is recognized
if (pend_rd_op = '1') then
pend_rd_op_cmb <= '0';
end if;
-- Initiate BRAM read transfer
bram_en_cmb <= '1';
-- Only count addresses & burst length for read
-- burst operations
-- Go to SNG_ADDR state
rd_data_sm_ns <= SNG_ADDR;
-- If current operation was a burst, clear the active
-- burst flag
if (act_rd_burst = '1') or (act_rd_burst_two = '1') then
act_rd_burst_clr <= '1';
end if;
-- If we are loading the BRAM, then we have to view the curr_arlen
-- signal to determine if the next operation is a single transfer.
-- Or if the BRAM address counter is already loaded (and we reach
-- this if clause due to pend_rd_op then the axi_* signals will indicate
-- if the next operation is a burst or not.
-- If the operation is a single transaction, then set the last_bram_addr
-- signal when we reach SNG_ADDR.
if (bram_addr_ld_en = '1') then
if (curr_arlen = AXI_ARLEN_ONE) then
-- Set flag for last_bram_addr on transition
-- to SNG_ADDR on single operations.
set_last_bram_addr <= '1';
end if;
elsif (pend_rd_op = '1') then
if (axi_rd_burst = '0' and axi_rd_burst_two = '0') then
set_last_bram_addr <= '1';
end if;
end if;
else
-- No pending read address to initiate next read burst.
-- Go to IDLE
rd_data_sm_ns <= IDLE;
-- If current operation was a burst, clear the active
-- burst flag
if (act_rd_burst = '1') or (act_rd_burst_two = '1') then
act_rd_burst_clr <= '1';
end if;
end if;
else
-- Throttling condition detected
-- Ensure that AXI read data output register is disabled
-- due to throttle condition.
axi_rdata_en <= '0';
-- If new ARADDR detected and loaded into BRAM address counter
if (bram_addr_ld_en = '1') then
-- Initiate BRAM read transfer
bram_en_cmb <= '1';
-- Only count addresses & burst length for read
-- burst operations
-- Instead of transitioning to SNG_ADDR
-- to wait for last data beat.
rd_data_sm_ns <= LAST_DATA_AR_PEND;
-- For singles, block any subsequent loads into BRAM address
-- counter from AR SM
no_ar_ack_cmb <= '1';
end if;
end if; -- rd_adv_buf (RREADY throttle)
------------------------ LAST_DATA_AR_PEND --------------------
when LAST_DATA_AR_PEND =>
-- Ok to accept new operation if throttling detected
-- during current operation (and flag was previously set
-- to disable the back-to-back performance).
disable_b2b_brst_cmb <= '0';
-- Reach this state when new BRAM address is loaded into
-- BRAM address counter
-- But waiting for last RREADY/RVALID/RLAST to be asserted
-- Once this occurs, continue with pending AR operation
if (rd_adv_buf = '1') then
-- Go to SNG_ADDR state
rd_data_sm_ns <= SNG_ADDR;
-- If current operation was a burst, clear the active
-- burst flag
if (act_rd_burst = '1') or (act_rd_burst_two = '1') then
act_rd_burst_clr <= '1';
end if;
-- In this state, the BRAM address counter is already loaded,
-- the axi_rd_burst and axi_rd_burst_two signals will indicate
-- if the next operation is a burst or not.
-- If the operation is a single transaction, then set the last_bram_addr
-- signal when we reach SNG_ADDR.
if (axi_rd_burst = '0' and axi_rd_burst_two = '0') then
set_last_bram_addr <= '1';
end if;
-- Code coverage tests are reporting that reaching this state
-- always when axi_rd_burst = '0' and axi_rd_burst_two = '0',
-- so no bursting operations.
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
rd_data_sm_ns <= IDLE;
--coverage on
end case;
end process RD_DATA_SM_CMB_PROCESS;
---------------------------------------------------------------------------
RD_DATA_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
rd_data_sm_cs <= IDLE;
bram_en_int <= '0';
rd_skid_buf_ld_reg <= '0';
rddata_mux_sel <= C_RDDATA_MUX_BRAM;
axi_rvalid_set <= '0';
end_brst_rd_clr <= '0';
no_ar_ack <= '0';
pend_rd_op <= '0';
axi_b2b_brst <= '0';
disable_b2b_brst <= '0';
else
rd_data_sm_cs <= rd_data_sm_ns;
bram_en_int <= bram_en_cmb;
rd_skid_buf_ld_reg <= rd_skid_buf_ld_cmb;
rddata_mux_sel <= rddata_mux_sel_cmb;
axi_rvalid_set <= axi_rvalid_set_cmb;
end_brst_rd_clr <= end_brst_rd_clr_cmb;
no_ar_ack <= no_ar_ack_cmb;
pend_rd_op <= pend_rd_op_cmb;
axi_b2b_brst <= axi_b2b_brst_cmb;
disable_b2b_brst <= disable_b2b_brst_cmb;
end if;
end if;
end process RD_DATA_SM_REG_PROCESS;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Create seperate registered process for last_bram_addr signal.
-- Only asserted for a single clock cycle
-- Gets set when the burst counter is loaded with 0's (for a single data beat operation)
-- (indicated by set_last_bram_addr from DATA SM)
-- or when the burst counter is decrement and the current value = 1
REG_LAST_BRAM_ADDR: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
last_bram_addr <= '0';
-- The signal, set_last_bram_addr, is asserted when the DATA SM transitions to SNG_ADDR
-- on a single data beat burst. Can not use condition of loading burst counter
-- with the value of 0's (as the burst counter may be loaded during prior single operation
-- when waiting on last throttle/data beat, ie. rd_adv_buf not yet asserted).
elsif (set_last_bram_addr = '1') or
-- On burst operations at the last BRAM address presented to BRAM
(brst_cnt_dec = '1' and brst_cnt = C_BRST_CNT_ONE) then
last_bram_addr <= '1';
else
last_bram_addr <= '0';
end if;
end if;
end process REG_LAST_BRAM_ADDR;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- *** AXI Read Data Channel Interface ***
--
---------------------------------------------------------------------------
rd_skid_buf_ld <= rd_skid_buf_ld_reg or rd_skid_buf_ld_imm;
---------------------------------------------------------------------------
-- Generate: GEN_RDATA_NO_ECC
-- Purpose: Generation of AXI_RDATA output register without ECC
-- logic (C_ECC = 0 parameterization in design)
---------------------------------------------------------------------------
GEN_RDATA_NO_ECC: if C_ECC = 0 generate
signal axi_rdata_int : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
begin
---------------------------------------------------------------------------
-- AXI RdData Skid Buffer/Register
-- Sized according to size of AXI/BRAM data width
---------------------------------------------------------------------------
REG_RD_BUF: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
rd_skid_buf <= (others => '0');
-- Add immediate load of read skid buffer
-- Occurs in the case when at full throttle and RREADY/RVALID are asserted
elsif (rd_skid_buf_ld = '1') then
rd_skid_buf <= BRAM_RdData (C_AXI_DATA_WIDTH-1 downto 0);
else
rd_skid_buf <= rd_skid_buf;
end if;
end if;
end process REG_RD_BUF;
-- Rd Data Mux (selects between skid buffer and BRAM read data)
-- Select control signal from SM determines register load value
axi_rdata_mux <= BRAM_RdData (C_AXI_DATA_WIDTH-1 downto 0) when (rddata_mux_sel = C_RDDATA_MUX_BRAM) else
rd_skid_buf;
---------------------------------------------------------------------------
-- Generate: GEN_RDATA
-- Purpose: Generate each bit of AXI_RDATA.
---------------------------------------------------------------------------
GEN_RDATA: for i in C_AXI_DATA_WIDTH-1 downto 0 generate
begin
REG_RDATA: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- Clear output after last data beat accepted by requesting AXI master
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- Don't clear RDDATA when a back to back burst is occuring on RLAST & RVALID assertion
-- For improved code coverage, can remove the signal, axi_rvalid_int from this if clause.
-- It will always be asserted in this case.
(axi_rlast_int = '1' and AXI_RREADY = '1' and axi_b2b_brst = '0') then
axi_rdata_int (i) <= '0';
elsif (axi_rdata_en = '1') then
axi_rdata_int (i) <= axi_rdata_mux (i);
else
axi_rdata_int (i) <= axi_rdata_int (i);
end if;
end if;
end process REG_RDATA;
end generate GEN_RDATA;
-- If C_ECC = 0, direct output assignment to AXI_RDATA
AXI_RDATA <= axi_rdata_int;
end generate GEN_RDATA_NO_ECC;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_RDATA_ECC
-- Purpose: Generation of AXI_RDATA output register when ECC
-- logic is enabled (C_ECC = 1 parameterization in design)
---------------------------------------------------------------------------
GEN_RDATA_ECC: if C_ECC = 1 generate
subtype syndrome_bits is std_logic_vector(0 to C_INT_ECC_WIDTH-1);
-- 0:6 for 32-bit ECC
-- 0:7 for 64-bit ECC
type correct_data_table_type is array (natural range 0 to C_AXI_DATA_WIDTH-1) of syndrome_bits;
signal rd_skid_buf_i : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi_rdata_int : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi_rdata_int_corr : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
begin
-- Remove GEN_RD_BUF that was doing bit reversal.
-- Replace with direct register assignments. Sized according to AXI data width.
REG_RD_BUF: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
rd_skid_buf_i <= (others => '0');
-- Add immediate load of read skid buffer
-- Occurs in the case when at full throttle and RREADY/RVALID are asserted
elsif (rd_skid_buf_ld = '1') then
rd_skid_buf_i (C_AXI_DATA_WIDTH-1 downto 0) <= UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1);
else
rd_skid_buf_i <= rd_skid_buf_i;
end if;
end if;
end process REG_RD_BUF;
-- Rd Data Mux (selects between skid buffer and BRAM read data)
-- Select control signal from SM determines register load value
-- axi_rdata_mux holds data + ECC bits.
-- Previous mux on input to checkbit_handler logic.
-- Removed now (mux inserted after checkbit_handler logic before register stage)
--
-- axi_rdata_mux <= BRAM_RdData (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) when (rddata_mux_sel = C_RDDATA_MUX_BRAM) else
-- rd_skid_buf_i;
-- Remove GEN_RDATA that was doing bit reversal.
REG_RDATA: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1' and axi_b2b_brst = '0') then
axi_rdata_int <= (others => '0');
elsif (axi_rdata_en = '1') then
-- Track uncorrected data vector with AXI RDATA output pipeline
-- Mimic mux logic here (from previous post checkbit XOR logic register)
if (rddata_mux_sel = C_RDDATA_MUX_BRAM) then
axi_rdata_int (C_AXI_DATA_WIDTH-1 downto 0) <= UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1);
else
axi_rdata_int <= rd_skid_buf_i;
end if;
else
axi_rdata_int <= axi_rdata_int;
end if;
end if;
end process REG_RDATA;
-- When C_ECC = 1, correct any single bit errors on output read data.
-- Post register stage to improve timing on ECC logic data path.
-- Use registers in AXI Interconnect IP core.
-- Perform bit swapping on output of correct_one_bit
-- module (axi_rdata_int_corr signal).
-- AXI_RDATA (i) <= axi_rdata_int (i) when (Enable_ECC = '0')
-- else axi_rdata_int_corr (C_AXI_DATA_WIDTH-1-i);
-- Found in HW debug
-- axi_rdata_int is reversed to be returned on AXI bus.
-- AXI_RDATA (i) <= axi_rdata_int (C_AXI_DATA_WIDTH-1-i) when (Enable_ECC = '0')
-- else axi_rdata_int_corr (C_AXI_DATA_WIDTH-1-i);
-- Remove bit reversal on AXI_RDATA output.
AXI_RDATA <= axi_rdata_int when (Enable_ECC = '0' or Sl_UE_i = '1') else axi_rdata_int_corr;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HAMMING_ECC_CORR
--
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
-- Generate statements to correct BRAM read data
-- dependent on ECC type.
------------------------------------------------------------------------
GEN_HAMMING_ECC_CORR: if C_ECC_TYPE = 0 generate
begin
------------------------------------------------------------------------
-- Generate: CHK_ECC_32
-- Purpose: Check ECC data unique for 32-bit BRAM.
------------------------------------------------------------------------
CHK_ECC_32: if C_AXI_DATA_WIDTH = 32 generate
constant correct_data_table_32 : correct_data_table_type := (
0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001",
4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001",
8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101",
12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101",
16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101",
20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101",
24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011",
28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011"
);
signal syndrome_4_reg : std_logic_vector (0 to 1) := (others => '0'); -- Only used in 32-bit ECC
signal syndrome_6_reg : std_logic_vector (0 to 5) := (others => '0'); -- Specific for 32-bit ECC
begin
---------------------------------------------------------------------------
-- Register ECC syndrome value to correct any single bit errors
-- post-register on AXI read data.
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
syndrome_reg <= (others => '0');
syndrome_4_reg <= (others => '0');
syndrome_6_reg <= (others => '0');
-- Align register stage of syndrome with AXI read data pipeline
elsif (axi_rdata_en = '1') then
syndrome_reg <= Syndrome;
syndrome_4_reg <= Syndrome_4;
syndrome_6_reg <= Syndrome_6;
else
syndrome_reg <= syndrome_reg;
syndrome_4_reg <= syndrome_4_reg;
syndrome_6_reg <= syndrome_6_reg;
end if;
end if;
end process REG_SYNDROME;
---------------------------------------------------------------------------
-- Do last XOR on specific syndrome bits after pipeline stage before
-- correct_one_bit module.
syndrome_reg_i (0 to 3) <= syndrome_reg (0 to 3);
PARITY_CHK4: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2)
port map (
InA => syndrome_4_reg (0 to 1), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_reg_i (4) ); -- [out std_logic]
syndrome_reg_i (5) <= syndrome_reg (5);
PARITY_CHK6: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => syndrome_6_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_reg_i (6) ); -- [out std_logic]
---------------------------------------------------------------------------
-- Generate: GEN_CORR_32
-- Purpose: Generate corrected read data based on syndrome value.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
GEN_CORR_32: for i in 0 to C_AXI_DATA_WIDTH-1 generate
begin
-----------------------------------------------------------------------
-- Instance: CORR_ONE_BIT_32
-- Description: Correct output read data based on syndrome vector.
-- A single error can be corrected by decoding the
-- syndrome value.
-- Input signal is declared (N:0).
-- Output signal is (N:0).
-- In order to reuse correct_one_bit module,
-- the single data bit correction is done LSB to MSB
-- in generate statement loop.
-----------------------------------------------------------------------
CORR_ONE_BIT_32: entity work.correct_one_bit
generic map (
C_USE_LUT6 => C_USE_LUT6,
Correct_Value => correct_data_table_32 (i))
port map (
DIn => axi_rdata_int (i),
Syndrome => syndrome_reg_i,
DCorr => axi_rdata_int_corr (i));
end generate GEN_CORR_32;
end generate CHK_ECC_32;
------------------------------------------------------------------------
-- Generate: CHK_ECC_64
-- Purpose: Check ECC data unique for 64-bit BRAM.
------------------------------------------------------------------------
CHK_ECC_64: if C_AXI_DATA_WIDTH = 64 generate
constant correct_data_table_64 : correct_data_table_type := (
0 => "11000001", 1 => "10100001", 2 => "01100001", 3 => "11100001",
4 => "10010001", 5 => "01010001", 6 => "11010001", 7 => "00110001",
8 => "10110001", 9 => "01110001", 10 => "11110001", 11 => "10001001",
12 => "01001001", 13 => "11001001", 14 => "00101001", 15 => "10101001",
16 => "01101001", 17 => "11101001", 18 => "00011001", 19 => "10011001",
20 => "01011001", 21 => "11011001", 22 => "00111001", 23 => "10111001",
24 => "01111001", 25 => "11111001", 26 => "10000101", 27 => "01000101",
28 => "11000101", 29 => "00100101", 30 => "10100101", 31 => "01100101",
32 => "11100101", 33 => "00010101", 34 => "10010101", 35 => "01010101",
36 => "11010101", 37 => "00110101", 38 => "10110101", 39 => "01110101",
40 => "11110101", 41 => "00001101", 42 => "10001101", 43 => "01001101",
44 => "11001101", 45 => "00101101", 46 => "10101101", 47 => "01101101",
48 => "11101101", 49 => "00011101", 50 => "10011101", 51 => "01011101",
52 => "11011101", 53 => "00111101", 54 => "10111101", 55 => "01111101",
56 => "11111101", 57 => "10000011", 58 => "01000011", 59 => "11000011",
60 => "00100011", 61 => "10100011", 62 => "01100011", 63 => "11100011"
);
signal syndrome_7_reg : std_logic_vector (0 to 11) := (others => '0'); -- Specific for 64-bit ECC
signal syndrome_7_a : std_logic;
signal syndrome_7_b : std_logic;
begin
---------------------------------------------------------------------------
-- Register ECC syndrome value to correct any single bit errors
-- post-register on AXI read data.
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- Align register stage of syndrome with AXI read data pipeline
if (axi_rdata_en = '1') then
syndrome_reg <= Syndrome;
syndrome_7_reg <= Syndrome_7;
else
syndrome_reg <= syndrome_reg;
syndrome_7_reg <= syndrome_7_reg;
end if;
end if;
end process REG_SYNDROME;
---------------------------------------------------------------------------
-- Do last XOR on select syndrome bits after pipeline stage
-- before correct_one_bit_64 module.
PARITY_CHK7_A: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => syndrome_7_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_7_a ); -- [out std_logic]
PARITY_CHK7_B: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => syndrome_7_reg (6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_7_b ); -- [out std_logic]
-- Do last XOR on Syndrome MSB after pipeline stage before correct_one_bit module
-- PASSES: syndrome_reg_i (7) <= syndrome_reg (7) xor syndrome_7_b_reg;
syndrome_reg_i (7) <= syndrome_7_a xor syndrome_7_b;
syndrome_reg_i (0 to 6) <= syndrome_reg (0 to 6);
---------------------------------------------------------------------------
-- Generate: GEN_CORR_64
-- Purpose: Generate corrected read data based on syndrome value.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
GEN_CORR_64: for i in 0 to C_AXI_DATA_WIDTH-1 generate
begin
-----------------------------------------------------------------------
-- Instance: CORR_ONE_BIT_64
-- Description: Correct output read data based on syndrome vector.
-- A single error can be corrected by decoding the
-- syndrome value.
-----------------------------------------------------------------------
CORR_ONE_BIT_64: entity work.correct_one_bit_64
generic map (
C_USE_LUT6 => C_USE_LUT6,
Correct_Value => correct_data_table_64 (i))
port map (
DIn => axi_rdata_int (i),
Syndrome => syndrome_reg_i,
DCorr => axi_rdata_int_corr (i));
end generate GEN_CORR_64;
end generate CHK_ECC_64;
end generate GEN_HAMMING_ECC_CORR;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HSIAO_ECC_CORR
--
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
-- Derived from MIG v3.7 Hsiao HDL.
-- Generate statements to correct BRAM read data
-- dependent on ECC type.
------------------------------------------------------------------------
GEN_HSIAO_ECC_CORR: if C_ECC_TYPE = 1 generate
type type_int0 is array (C_AXI_DATA_WIDTH - 1 downto 0) of std_logic_vector (ECC_WIDTH - 1 downto 0);
signal h_matrix : type_int0;
signal flip_bits : std_logic_vector(C_AXI_DATA_WIDTH - 1 downto 0);
signal ecc_rddata_r : std_logic_vector(C_AXI_DATA_WIDTH - 1 downto 0);
begin
-- Reconstruct H-matrix
H_COL: for n in 0 to C_AXI_DATA_WIDTH - 1 generate
begin
H_BIT: for p in 0 to ECC_WIDTH - 1 generate
begin
h_matrix (n)(p) <= h_rows (p * CODE_WIDTH + n);
end generate H_BIT;
end generate H_COL;
-- Based on syndrome value, determine bits to flip in BRAM read data.
GEN_FLIP_BIT: for r in 0 to C_AXI_DATA_WIDTH - 1 generate
begin
flip_bits (r) <= BOOLEAN_TO_STD_LOGIC (h_matrix (r) = syndrome_r);
end generate GEN_FLIP_BIT;
ecc_rddata_r <= axi_rdata_int;
axi_rdata_int_corr (C_AXI_DATA_WIDTH-1 downto 0) <= -- UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1) xor
ecc_rddata_r (C_AXI_DATA_WIDTH-1 downto 0) xor
flip_bits (C_AXI_DATA_WIDTH-1 downto 0);
end generate GEN_HSIAO_ECC_CORR;
end generate GEN_RDATA_ECC;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_RID_SNG
-- Purpose: Generate RID output pipeline when the core is configured
-- in a single port mode.
---------------------------------------------------------------------------
GEN_RID_SNG: if (C_SINGLE_PORT_BRAM = 1) generate
begin
REG_RID_TEMP: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rid_temp <= (others => '0');
elsif (bram_addr_ld_en = '1') then
axi_rid_temp <= AXI_ARID;
else
axi_rid_temp <= axi_rid_temp;
end if;
end if;
end process REG_RID_TEMP;
REG_RID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1') then
axi_rid_int <= (others => '0');
elsif (bram_addr_ld_en = '1') then
axi_rid_int <= AXI_ARID;
elsif (axi_rvalid_set = '1') or (axi_b2b_rid_adv = '1') then
axi_rid_int <= axi_rid_temp;
else
axi_rid_int <= axi_rid_int;
end if;
end if;
end process REG_RID;
-- Advance RID pipeline values
axi_b2b_rid_adv <= '1' when (axi_rlast_int = '1' and
AXI_RREADY = '1' and
axi_b2b_brst = '1')
else '0';
end generate GEN_RID_SNG;
---------------------------------------------------------------------------
-- Generate: GEN_RID
-- Purpose: Generate RID in dual port mode (with read address pipeline).
---------------------------------------------------------------------------
GEN_RID: if (C_SINGLE_PORT_BRAM = 0) generate
begin
---------------------------------------------------------------------------
-- RID Output Register
--
-- Output RID value either comes from pipelined value or directly wrapped
-- ARID value. Determined by address pipeline usage.
---------------------------------------------------------------------------
-- Create intermediate temporary RID output register
REG_RID_TEMP: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rid_temp <= (others => '0');
-- When BRAM address counter gets loaded
-- Set output RID value based on address source
elsif (bram_addr_ld_en = '1') and (axi_rid_temp_full = '0') then
-- If BRAM address counter gets loaded directly from
-- AXI bus, then save ARID value for wrapping to RID
if (araddr_pipe_sel = '0') then
axi_rid_temp <= AXI_ARID;
else
-- Use pipelined AWID value
axi_rid_temp <= axi_arid_pipe;
end if;
-- Add condition to check for temp utilized (temp_full now = '0'), but a
-- pending RID is stored in temp2. Must advance the pipeline.
elsif ((axi_rvalid_set = '1' or axi_b2b_rid_adv = '1') and (axi_rid_temp2_full = '1')) or
(axi_rid_temp_full_fe = '1' and axi_rid_temp2_full = '1') then
axi_rid_temp <= axi_rid_temp2;
else
axi_rid_temp <= axi_rid_temp;
end if;
end if;
end process REG_RID_TEMP;
-- Create flag that indicates if axi_rid_temp is full
REG_RID_TEMP_FULL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rid_temp_full = '1' and
(axi_rvalid_set = '1' or axi_b2b_rid_adv = '1') and
axi_rid_temp2_full = '0') then
axi_rid_temp_full <= '0';
elsif (bram_addr_ld_en = '1') or
((axi_rvalid_set = '1' or axi_b2b_rid_adv = '1') and (axi_rid_temp2_full = '1')) or
(axi_rid_temp_full_fe = '1' and axi_rid_temp2_full = '1') then
axi_rid_temp_full <= '1';
else
axi_rid_temp_full <= axi_rid_temp_full;
end if;
end if;
end process REG_RID_TEMP_FULL;
-- Create flag to detect falling edge of axi_rid_temp_full flag
REG_RID_TEMP_FULL_D1: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rid_temp_full_d1 <= '0';
else
axi_rid_temp_full_d1 <= axi_rid_temp_full;
end if;
end if;
end process REG_RID_TEMP_FULL_D1;
axi_rid_temp_full_fe <= '1' when (axi_rid_temp_full = '0' and
axi_rid_temp_full_d1 = '1') else '0';
---------------------------------------------------------------------------
-- Create intermediate temporary RID output register
REG_RID_TEMP2: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rid_temp2 <= (others => '0');
-- When BRAM address counter gets loaded
-- Set output RID value based on address source
elsif (bram_addr_ld_en = '1') and (axi_rid_temp_full = '1') then
-- If BRAM address counter gets loaded directly from
-- AXI bus, then save ARID value for wrapping to RID
if (araddr_pipe_sel = '0') then
axi_rid_temp2 <= AXI_ARID;
else
-- Use pipelined AWID value
axi_rid_temp2 <= axi_arid_pipe;
end if;
else
axi_rid_temp2 <= axi_rid_temp2;
end if;
end if;
end process REG_RID_TEMP2;
-- Create flag that indicates if axi_rid_temp2 is full
REG_RID_TEMP2_FULL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rid_temp2_full = '1' and (axi_rvalid_set = '1' or axi_b2b_rid_adv = '1')) or
(axi_rid_temp_full_fe = '1' and axi_rid_temp2_full = '1') then
axi_rid_temp2_full <= '0';
elsif (bram_addr_ld_en = '1') and (axi_rid_temp_full = '1') then
axi_rid_temp2_full <= '1';
else
axi_rid_temp2_full <= axi_rid_temp2_full;
end if;
end if;
end process REG_RID_TEMP2_FULL;
---------------------------------------------------------------------------
-- Output RID register is enabeld when RVALID is asserted on the AXI bus
-- Clear RID when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
REG_RID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- For improved code coverage, can remove the signal, axi_rvalid_int from statement.
(axi_rlast_int = '1' and AXI_RREADY = '1' and axi_b2b_brst = '0') then
axi_rid_int <= (others => '0');
-- Add back to back case to advance RID
elsif (axi_rvalid_set = '1') or (axi_b2b_rid_adv = '1') then
axi_rid_int <= axi_rid_temp;
else
axi_rid_int <= axi_rid_int;
end if;
end if;
end process REG_RID;
-- Advance RID pipeline values
axi_b2b_rid_adv <= '1' when (axi_rlast_int = '1' and
AXI_RREADY = '1' and
axi_b2b_brst = '1')
else '0';
end generate GEN_RID;
---------------------------------------------------------------------------
-- Generate: GEN_RRESP
-- Purpose: Create register output unique when ECC is disabled.
-- Only possible output value = OKAY response.
---------------------------------------------------------------------------
GEN_RRESP: if C_ECC = 0 generate
begin
-----------------------------------------------------------------------
-- AXI_RRESP Output Register
--
-- Set when RVALID is asserted on AXI bus.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking
-- sequence and recognized by AXI requesting master.
-----------------------------------------------------------------------
REG_RRESP: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- For improved code coverage, remove signal, axi_rvalid_int, it will always be asserted.
(axi_rlast_int = '1' and AXI_RREADY = '1') then
axi_rresp_int <= (others => '0');
elsif (axi_rvalid_set = '1') then
-- AXI BRAM only supports OK response for normal operations
-- Exclusive operations not yet supported
axi_rresp_int <= RESP_OKAY;
else
axi_rresp_int <= axi_rresp_int;
end if;
end if;
end process REG_RRESP;
end generate GEN_RRESP;
---------------------------------------------------------------------------
-- Generate: GEN_RRESP_ECC
-- Purpose: Create register output unique when ECC is disabled.
-- Only possible output value = OKAY response.
---------------------------------------------------------------------------
GEN_RRESP_ECC: if C_ECC = 1 generate
begin
-----------------------------------------------------------------------
-- AXI_RRESP Output Register
--
-- Set when RVALID is asserted on AXI bus.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking
-- sequence and recognized by AXI requesting master.
-----------------------------------------------------------------------
REG_RRESP: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- For improved code coverage, remove signal, axi_rvalid_int, it will always be asserted.
(axi_rlast_int = '1' and AXI_RREADY = '1') then
axi_rresp_int <= (others => '0');
elsif (axi_rvalid_set = '1') then
-- AXI BRAM only supports OK response for normal operations
-- Exclusive operations not yet supported
-- For ECC implementation
-- Check that an uncorrectable error has not occured.
-- If so, then respond with RESP_SLVERR on AXI.
-- Ok to use combinatorial signal here. The Sl_UE_i
-- flag is generated based on the registered syndrome value.
-- if (Sl_UE_i = '1') then
-- axi_rresp_int <= RESP_SLVERR;
-- else
axi_rresp_int <= RESP_OKAY;
-- end if;
else
axi_rresp_int <= axi_rresp_int;
end if;
end if;
end process REG_RRESP;
end generate GEN_RRESP_ECC;
---------------------------------------------------------------------------
-- AXI_RVALID Output Register
--
-- Set AXI_RVALID when read data SM indicates.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
---------------------------------------------------------------------------
REG_RVALID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- Clear AXI_RVALID at the end of tranfer when able to clear
-- (axi_rlast_int = '1' and axi_rvalid_int = '1' and AXI_RREADY = '1' and
-- For improved code coverage, remove signal axi_rvalid_int.
(axi_rlast_int = '1' and AXI_RREADY = '1' and
-- Added axi_rvalid_clr_ok to check if during a back-to-back burst
-- and the back-to-back is elgible for streaming performance
axi_rvalid_clr_ok = '1') then
axi_rvalid_int <= '0';
elsif (axi_rvalid_set = '1') then
axi_rvalid_int <= '1';
else
axi_rvalid_int <= axi_rvalid_int;
end if;
end if;
end process REG_RVALID;
-- Create flag that gets set when we load BRAM address early in a B2B scenario
-- This will prevent the RVALID from getting cleared at the end of the current burst
-- Otherwise, the RVALID gets cleared after RLAST/RREADY dual assertion
REG_RVALID_CLR: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rvalid_clr_ok <= '0';
-- When the new address loaded into the BRAM counter is for a back-to-back operation
-- Do not clear the RVALID
elsif (rd_b2b_elgible = '1' and bram_addr_ld_en = '1') then
axi_rvalid_clr_ok <= '0';
-- Else when we start a new transaction (that is not back-to-back)
-- Then enable the RVALID to get cleared upon RLAST/RREADY
elsif (bram_addr_ld_en = '1') or
(axi_rvalid_clr_ok = '0' and
(disable_b2b_brst = '1' or disable_b2b_brst_cmb = '1') and
last_bram_addr = '1') or
-- Add check for current SM state
-- If LAST_ADDR state reached, no longer performing back-to-back
-- transfers and keeping data streaming on AXI bus.
(rd_data_sm_cs = LAST_ADDR) then
axi_rvalid_clr_ok <= '1';
else
axi_rvalid_clr_ok <= axi_rvalid_clr_ok;
end if;
end if;
end process REG_RVALID_CLR;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- AXI_RLAST Output Register
--
-- Set AXI_RLAST when read data SM indicates.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
---------------------------------------------------------------------------
REG_RLAST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- To improve code coverage, remove
-- use of axi_rvalid_int (it will always be asserted with RLAST).
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1' and axi_rlast_set = '0') then
axi_rlast_int <= '0';
elsif (axi_rlast_set = '1') then
axi_rlast_int <= '1';
else
axi_rlast_int <= axi_rlast_int;
end if;
end if;
end process REG_RLAST;
---------------------------------------------------------------------------
-- Generate complete flag
do_cmplt_burst_cmb <= '1' when (last_bram_addr = '1' and
axi_rd_burst = '1' and
axi_rd_burst_two = '0') else '0';
-- Register complete flags
REG_CMPLT_BURST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or (do_cmplt_burst_clr = '1') then
do_cmplt_burst <= '0';
elsif (do_cmplt_burst_cmb = '1') then
do_cmplt_burst <= '1';
else
do_cmplt_burst <= do_cmplt_burst;
end if;
end if;
end process REG_CMPLT_BURST;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- RLAST State Machine
--
-- Description: SM to generate axi_rlast_set signal.
-- Created based on IR # 555346 to track when RLAST needs
-- to be asserted for back to back transfers
-- Uses the indication when last BRAM address is presented
-- and then counts the handshaking cycles on the AXI bus
-- (RVALID and RREADY both asserted).
-- Uses rd_adv_buf to perform this operation.
--
-- Output: Name Type
-- axi_rlast_set Not Registered
-- do_cmplt_burst_clr Not Registered
--
--
-- RLAST_SM_CMB_PROCESS: Combinational process to determine next state.
-- RLAST_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
RLAST_SM_CMB_PROCESS: process (
do_cmplt_burst,
last_bram_addr,
rd_adv_buf,
act_rd_burst,
axi_rd_burst,
act_rd_burst_two,
axi_rd_burst_two,
axi_rlast_int,
rlast_sm_cs )
begin
-- assign default values for state machine outputs
rlast_sm_ns <= rlast_sm_cs;
axi_rlast_set <= '0';
do_cmplt_burst_clr <= '0';
case rlast_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- If last read address is presented to BRAM
if (last_bram_addr = '1') then
-- If the operation is a single read operation
if (axi_rd_burst = '0') and (axi_rd_burst_two = '0') then
-- Go to wait for last data beat
rlast_sm_ns <= W8_LAST_DATA;
-- Else the transaction is a burst
else
-- Throttle condition on 3rd to last data beat
if (rd_adv_buf = '0') then
-- If AXI read burst = 2 (only two data beats to capture)
if (axi_rd_burst_two = '1' or act_rd_burst_two = '1') then
rlast_sm_ns <= W8_THROTTLE_B2;
else
rlast_sm_ns <= W8_THROTTLE;
end if;
-- No throttle on 3rd to last data beat
else
-- Only back-to-back support when burst size is greater
-- than two data beats. We will never toggle on a burst > 2
-- when last_bram_addr is asserted (as this is no toggle
-- condition)
-- Go to wait for 2nd to last data beat
rlast_sm_ns <= W8_2ND_LAST_DATA;
do_cmplt_burst_clr <= '1';
end if;
end if;
end if;
------------------------- W8_THROTTLE State -----------------------
when W8_THROTTLE =>
if (rd_adv_buf = '1') then
-- Go to wait for 2nd to last data beat
rlast_sm_ns <= W8_2ND_LAST_DATA;
-- If do_cmplt_burst flag is set, then clear it
if (do_cmplt_burst = '1') then
do_cmplt_burst_clr <= '1';
end if;
end if;
---------------------- W8_2ND_LAST_DATA State ---------------------
when W8_2ND_LAST_DATA =>
if (rd_adv_buf = '1') then
-- Assert RLAST on AXI
axi_rlast_set <= '1';
rlast_sm_ns <= W8_LAST_DATA;
end if;
------------------------- W8_LAST_DATA State ----------------------
when W8_LAST_DATA =>
-- If pending single to complete, keep RLAST asserted
-- Added to only assert axi_rlast_set for a single clock cycle
-- when we enter this state and are here waiting for the
-- throttle on the AXI bus.
if (axi_rlast_int = '1') then
axi_rlast_set <= '0';
else
axi_rlast_set <= '1';
end if;
-- Wait for last data beat to transition back to IDLE
if (rd_adv_buf = '1') then
rlast_sm_ns <= IDLE;
end if;
-------------------------- W8_THROTTLE_B2 ------------------------
when W8_THROTTLE_B2 =>
-- Wait for last data beat to transition back to IDLE
-- and set RLAST
if (rd_adv_buf = '1') then
rlast_sm_ns <= IDLE;
axi_rlast_set <= '1';
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
rlast_sm_ns <= IDLE;
--coverage on
end case;
end process RLAST_SM_CMB_PROCESS;
---------------------------------------------------------------------------
RLAST_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
rlast_sm_cs <= IDLE;
else
rlast_sm_cs <= rlast_sm_ns;
end if;
end if;
end process RLAST_SM_REG_PROCESS;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** ECC Logic ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_ECC
-- Purpose: Generate BRAM ECC write data and check ECC on read operations.
-- Create signals to update ECC registers (lite_ecc_reg module interface).
--
---------------------------------------------------------------------------
GEN_ECC: if C_ECC = 1 generate
signal bram_din_a_i : std_logic_vector(0 to C_AXI_DATA_WIDTH+C_ECC_WIDTH-1) := (others => '0'); -- Set for port data width
signal CE_Q : std_logic := '0';
signal Sl_CE_i : std_logic := '0';
signal bram_en_int_d1 : std_logic := '0';
signal bram_en_int_d2 : std_logic := '0';
begin
-- Generate signal to advance BRAM read address pipeline to
-- capture address for ECC error conditions (in lite_ecc_reg module).
-- BRAM_Addr_En <= bram_addr_inc or narrow_bram_addr_inc_re or
-- ((bram_en_int or bram_en_int_reg) and not (axi_rd_burst) and not (axi_rd_burst_two));
BRAM_Addr_En <= bram_addr_inc or narrow_bram_addr_inc_re or rd_adv_buf or
((bram_en_int or bram_en_int_d1 or bram_en_int_d2) and not (axi_rd_burst) and not (axi_rd_burst_two));
-- Enable 2nd & 3rd pipeline stage for BRAM address storage with single read transfers.
BRAM_EN_REG: process(S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
bram_en_int_d1 <= bram_en_int;
bram_en_int_d2 <= bram_en_int_d1;
end if;
end process BRAM_EN_REG;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HAMMING_ECC
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
------------------------------------------------------------------------
GEN_HAMMING_ECC: if C_ECC_TYPE = 0 generate
begin
------------------------------------------------------------------------
-- Generate: GEN_ECC_32
-- Purpose: Check ECC data unique for 32-bit BRAM.
-- Add extra '0' at MSB of ECC vector for data2mem alignment
-- w/ 32-bit BRAM data widths.
-- ECC bits are in upper order bits.
------------------------------------------------------------------------
GEN_ECC_32: if C_AXI_DATA_WIDTH = 32 generate
begin
---------------------------------------------------------------------------
-- Instance: CHK_HANDLER_32
-- Description: Generate ECC bits for checking data read from BRAM.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
CHK_HANDLER_32: entity work.checkbit_handler
generic map (
C_ENCODE => false, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
-- In 32-bit BRAM use case: DataIn (8:39)
-- CheckIn (1:7)
DataIn => bram_din_a_i(C_INT_ECC_WIDTH+1 to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH), -- [in std_logic_vector(0 to 31)]
CheckIn => bram_din_a_i(1 to C_INT_ECC_WIDTH), -- [in std_logic_vector(0 to 6)]
CheckOut => open, -- [out std_logic_vector(0 to 6)]
Syndrome => Syndrome, -- [out std_logic_vector(0 to 6)]
Syndrome_4 => Syndrome_4, -- [out std_logic_vector(0 to 1)]
Syndrome_6 => Syndrome_6, -- [out std_logic_vector(0 to 5)]
Syndrome_Chk => syndrome_reg_i, -- [out std_logic_vector(0 to 6)]
Enable_ECC => Enable_ECC, -- [in std_logic]
UE_Q => UE_Q, -- [in std_logic]
CE_Q => CE_Q, -- [in std_logic]
UE => Sl_UE_i, -- [out std_logic]
CE => Sl_CE_i ); -- [out std_logic]
-- GEN_CORR_32 generate & correct_one_bit instantiation moved to generate
-- of AXI RDATA output register logic.
end generate GEN_ECC_32;
------------------------------------------------------------------------
-- Generate: GEN_ECC_64
-- Purpose: Check ECC data unique for 64-bit BRAM.
-- No extra '0' at MSB of ECC vector for data2mem alignment
-- w/ 64-bit BRAM data widths.
-- ECC bits are in upper order bits.
------------------------------------------------------------------------
GEN_ECC_64: if C_AXI_DATA_WIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Instance: CHK_HANDLER_64
-- Description: Generate ECC bits for checking data read from BRAM.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
CHK_HANDLER_64: entity work.checkbit_handler_64
generic map (
C_ENCODE => false, -- [boolean]
C_REG => false, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
Clk => S_AXI_AClk, -- [in std_logic]
-- In 64-bit BRAM use case: DataIn (8:71)
-- CheckIn (0:7)
DataIn => bram_din_a_i (C_INT_ECC_WIDTH to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH-1), -- [in std_logic_vector(0 to 63)]
CheckIn => bram_din_a_i (0 to C_INT_ECC_WIDTH-1), -- [in std_logic_vector(0 to 7)]
CheckOut => open, -- [out std_logic_vector(0 to 7)]
Syndrome => Syndrome, -- [out std_logic_vector(0 to 7)]
Syndrome_7 => Syndrome_7,
Syndrome_Chk => syndrome_reg_i, -- [in std_logic_vector(0 to 7)]
Enable_ECC => Enable_ECC, -- [in std_logic]
UE_Q => UE_Q, -- [in std_logic]
CE_Q => CE_Q, -- [in std_logic]
UE => Sl_UE_i, -- [out std_logic]
CE => Sl_CE_i ); -- [out std_logic]
-- GEN_CORR_64 generate & correct_one_bit instantiation moved to generate
-- of AXI RDATA output register logic.
end generate GEN_ECC_64;
end generate GEN_HAMMING_ECC;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HSIAO_ECC
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
-- Derived from MIG v3.7 Hsiao HDL.
------------------------------------------------------------------------
GEN_HSIAO_ECC: if C_ECC_TYPE = 1 generate
constant ECC_WIDTH : integer := C_INT_ECC_WIDTH;
signal syndrome_ns : std_logic_vector (ECC_WIDTH - 1 downto 0) := (others => '0');
begin
-- Generate ECC check bits and syndrome values based on
-- BRAM read data.
-- Generate appropriate single or double bit error flags.
-- Instantiate ecc_gen_hsiao module, generated from MIG
I_ECC_GEN_HSIAO: entity work.ecc_gen
generic map (
code_width => CODE_WIDTH,
ecc_width => ECC_WIDTH,
data_width => C_AXI_DATA_WIDTH
)
port map (
-- Output
h_rows => h_rows (CODE_WIDTH * ECC_WIDTH - 1 downto 0)
);
GEN_RD_ECC: for m in 0 to ECC_WIDTH - 1 generate
begin
syndrome_ns (m) <= REDUCTION_XOR ( -- bram_din_a_i (0 to CODE_WIDTH-1)
BRAM_RdData (CODE_WIDTH-1 downto 0)
and h_rows ((m*CODE_WIDTH)+CODE_WIDTH-1 downto (m*CODE_WIDTH)));
end generate GEN_RD_ECC;
-- Insert register stage for syndrome.
-- Same as Hamming ECC code. Syndrome value is registered.
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
syndrome_r <= syndrome_ns;
end if;
end process REG_SYNDROME;
Sl_CE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0)));
Sl_UE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and not(REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0)));
end generate GEN_HSIAO_ECC;
-- Capture correctable/uncorrectable error from BRAM read
CORR_REG: process(S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (Enable_ECC = '1') and
(axi_rvalid_int = '1' and AXI_RREADY = '1') then -- Capture error flags
CE_Q <= Sl_CE_i;
UE_Q <= Sl_UE_i;
else
CE_Q <= '0';
UE_Q <= '0';
end if;
end if;
end process CORR_REG;
-- The signal, axi_rdata_en loads the syndrome_reg.
-- Use the AXI RVALID/READY signals to capture state of UE and CE.
-- Since flag generation uses the registered syndrome value.
-- ECC register block gets registered UE or CE conditions to update
-- ECC registers/interrupt/flag outputs.
Sl_CE <= CE_Q;
Sl_UE <= UE_Q;
-- CE_Failing_We <= Sl_CE_i and Enable_ECC and axi_rvalid_set;
CE_Failing_We <= CE_Q;
---------------------------------------------------------------------------
-- Generate BRAM read data vector assignment to always be from Port A
-- in a single port BRAM configuration.
-- Map BRAM_RdData (Port A) (N:0) to bram_din_a_i (0:N)
-- Including read back ECC bits.
--
-- Port A or Port B sourcing done at full_axi module level
---------------------------------------------------------------------------
-- Original design with mux (BRAM vs. Skid Buffer) on input side of checkbit_handler logic.
-- Move mux to enable on AXI RDATA register.
bram_din_a_i (0 to C_AXI_DATA_WIDTH+C_ECC_WIDTH-1) <= BRAM_RdData (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0);
-- Map data vector from BRAM to use in correct_one_bit module with
-- register syndrome (post AXI RDATA register).
UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1) <= bram_din_a_i (C_ECC_WIDTH to C_ECC_WIDTH+C_AXI_DATA_WIDTH-1);
end generate GEN_ECC;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_NO_ECC
-- Purpose: Drive default output signals when ECC is diabled.
---------------------------------------------------------------------------
GEN_NO_ECC: if C_ECC = 0 generate
begin
BRAM_Addr_En <= '0';
CE_Failing_We <= '0';
Sl_CE <= '0';
Sl_UE <= '0';
end generate GEN_NO_ECC;
---------------------------------------------------------------------------
--
-- *** BRAM Interface Signals ***
--
---------------------------------------------------------------------------
BRAM_En <= bram_en_int;
---------------------------------------------------------------------------
-- BRAM Address Generate
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_L_BRAM_ADDR
-- Purpose: Generate zeros on lower order address bits adjustable
-- based on BRAM data width.
--
---------------------------------------------------------------------------
GEN_L_BRAM_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate
begin
BRAM_Addr (i) <= '0';
end generate GEN_L_BRAM_ADDR;
---------------------------------------------------------------------------
--
-- Generate: GEN_BRAM_ADDR
-- Purpose: Assign BRAM address output from address counter.
--
---------------------------------------------------------------------------
GEN_BRAM_ADDR: for i in C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate
begin
BRAM_Addr (i) <= bram_addr_int (i);
end generate GEN_BRAM_ADDR;
---------------------------------------------------------------------------
end architecture implementation;
| bsd-2-clause | fcab8aeff847f826ed06fe76fd11619b | 0.431815 | 4.770687 | false | false | false | false |
Yarr/Yarr-fw | rtl/spartan6/gn4124-core/spartan6/gn4124_core_pkg.vhd | 2 | 30,618 | --==============================================================================
--! @file gn4124_core_pkg_s6.vhd
--==============================================================================
--! Standard library
library IEEE;
--! Standard packages
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Package for gn4124 core
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--! @brief
--! Package for components declaration and core wide constants.
--! Spartan6 FPGAs version.
--------------------------------------------------------------------------------
--! @version
--! 0.1 | mc | 01.09.2010 | File creation and Doxygen comments
--!
--! @author
--! mc : Matthieu Cattin, CERN (BE-CO-HT)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
--==============================================================================
--! Package declaration
--==============================================================================
package gn4124_core_pkg is
--==============================================================================
--! Constants declaration
--==============================================================================
constant c_RST_ACTIVE : std_logic := '0'; -- Active low reset
--==============================================================================
--! Functions declaration
--==============================================================================
function f_byte_swap (
constant enable : boolean;
signal din : std_logic_vector(31 downto 0);
signal byte_swap : std_logic_vector(1 downto 0))
return std_logic_vector;
function log2_ceil(N : natural) return positive;
--==============================================================================
--! Components declaration
--==============================================================================
-----------------------------------------------------------------------------
component gn4124_core
generic (
g_ACK_TIMEOUT : positive := 100 -- Wishbone ACK timeout (in wishbone clock cycles)
);
port
(
---------------------------------------------------------
-- Control and status
rst_n_a_i : in std_logic; -- Asynchronous reset from GN4124
status_o : out std_logic_vector(31 downto 0); -- Core status output
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data
p2l_dframe_i : in std_logic; -- Receive Frame
p2l_valid_i : in std_logic; -- Receive Data Valid
-- P2L Control
p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
rx_error_o : out std_logic; -- Receive Error
vc_rdy_i : in std_logic_vector(1 downto 0); -- Virtual channel ready
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
l2p_dframe_o : out std_logic; -- Transmit Data Frame
l2p_valid_o : out std_logic; -- Transmit Data Valid
-- L2P Control
l2p_edb_o : out std_logic; -- Packet termination and discard
l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
tx_error_i : in std_logic; -- Transmit Error
---------------------------------------------------------
-- Interrupt interface
dma_irq_o : out std_logic_vector(1 downto 0); -- Interrupts sources to IRQ manager
irq_p_i : in std_logic; -- Interrupt request pulse from IRQ manager
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
---------------------------------------------------------
-- DMA registers wishbone interface (slave classic)
dma_reg_clk_i : in std_logic;
dma_reg_adr_i : in std_logic_vector(31 downto 0);
dma_reg_dat_i : in std_logic_vector(31 downto 0);
dma_reg_sel_i : in std_logic_vector(3 downto 0);
dma_reg_stb_i : in std_logic;
dma_reg_we_i : in std_logic;
dma_reg_cyc_i : in std_logic;
dma_reg_dat_o : out std_logic_vector(31 downto 0);
dma_reg_ack_o : out std_logic;
dma_reg_stall_o : out std_logic;
---------------------------------------------------------
-- CSR wishbone interface (master pipelined)
csr_clk_i : in std_logic;
csr_adr_o : out std_logic_vector(31 downto 0);
csr_dat_o : out std_logic_vector(31 downto 0);
csr_sel_o : out std_logic_vector(3 downto 0);
csr_stb_o : out std_logic;
csr_we_o : out std_logic;
csr_cyc_o : out std_logic;
csr_dat_i : in std_logic_vector(31 downto 0);
csr_ack_i : in std_logic;
csr_stall_i : in std_logic;
csr_err_i : in std_logic;
csr_rty_i : in std_logic;
csr_int_i : in std_logic;
---------------------------------------------------------
-- DMA wishbone interface (master pipelined)
dma_clk_i : in std_logic;
dma_adr_o : out std_logic_vector(31 downto 0);
dma_dat_o : out std_logic_vector(31 downto 0);
dma_sel_o : out std_logic_vector(3 downto 0);
dma_stb_o : out std_logic;
dma_we_o : out std_logic;
dma_cyc_o : out std_logic;
dma_dat_i : in std_logic_vector(31 downto 0);
dma_ack_i : in std_logic;
dma_stall_i : in std_logic;
dma_err_i : in std_logic;
dma_rty_i : in std_logic;
dma_int_i : in std_logic
);
end component gn4124_core;
-----------------------------------------------------------------------------
component p2l_des
port
(
---------------------------------------------------------
-- Reset and clock
rst_n_i : in std_logic;
sys_clk_i : in std_logic;
io_clk_i : in std_logic;
serdes_strobe_i : in std_logic;
---------------------------------------------------------
-- P2L DDR inputs
p2l_valid_i : in std_logic;
p2l_dframe_i : in std_logic;
p2l_data_i : in std_logic_vector(15 downto 0);
---------------------------------------------------------
-- P2L SDR outputs
p2l_valid_o : out std_logic;
p2l_dframe_o : out std_logic;
p2l_data_o : out std_logic_vector(31 downto 0)
);
end component; -- p2l_des
-----------------------------------------------------------------------------
component p2l_decode32
port
(
---------------------------------------------------------
-- Clock/Reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- Input from the Deserializer
des_p2l_valid_i : in std_logic;
des_p2l_dframe_i : in std_logic;
des_p2l_data_i : in std_logic_vector(31 downto 0);
---------------------------------------------------------
-- Decoder Outputs
--
-- Header
p2l_hdr_start_o : out std_logic; -- Indicates Header start cycle
p2l_hdr_length_o : out std_logic_vector(9 downto 0); -- Latched LENGTH value from header
p2l_hdr_cid_o : out std_logic_vector(1 downto 0); -- Completion ID
p2l_hdr_last_o : out std_logic; -- Indicates Last packet in a completion
p2l_hdr_stat_o : out std_logic_vector(1 downto 0); -- Completion Status
p2l_target_mrd_o : out std_logic; -- Target memory read
p2l_target_mwr_o : out std_logic; -- Target memory write
p2l_master_cpld_o : out std_logic; -- Master completion with data
p2l_master_cpln_o : out std_logic; -- Master completion without data
--
-- Address
p2l_addr_start_o : out std_logic; -- Indicates Address Start
p2l_addr_o : out std_logic_vector(31 downto 0); -- Latched Address that will increment with data
--
-- Data
p2l_d_valid_o : out std_logic; -- Indicates Data is valid
p2l_d_last_o : out std_logic; -- Indicates end of the packet
p2l_d_o : out std_logic_vector(31 downto 0); -- Data
p2l_be_o : out std_logic_vector(3 downto 0) -- Byte Enable for data
);
end component; -- p2l_decode32
-----------------------------------------------------------------------------
component l2p_ser
port
(
---------------------------------------------------------
-- Reset and clock
rst_n_i : in std_logic;
sys_clk_i : in std_logic;
io_clk_i : in std_logic;
serdes_strobe_i : in std_logic;
---------------------------------------------------------
-- L2P SDR inputs
l2p_valid_i : in std_logic;
l2p_dframe_i : in std_logic;
l2p_data_i : in std_logic_vector(31 downto 0);
---------------------------------------------------------
-- L2P DDR outputs
l2p_clk_p_o : out std_logic;
l2p_clk_n_o : out std_logic;
l2p_valid_o : out std_logic;
l2p_dframe_o : out std_logic;
l2p_data_o : out std_logic_vector(15 downto 0)
);
end component; -- l2p_ser
-----------------------------------------------------------------------------
component wbmaster32
generic (
g_ACK_TIMEOUT : positive := 100 -- Wishbone ACK timeout (in wb_clk cycles)
);
port
(
---------------------------------------------------------
-- Clock/Reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- From P2L Decoder
--
-- Header
pd_wbm_hdr_start_i : in std_logic; -- Indicates Header start cycle
pd_wbm_hdr_length_i : in std_logic_vector(9 downto 0); -- Latched LENGTH value from header
pd_wbm_hdr_cid_i : in std_logic_vector(1 downto 0); -- Completion ID
pd_wbm_target_mrd_i : in std_logic; -- Target memory read
pd_wbm_target_mwr_i : in std_logic; -- Target memory write
--
-- Address
pd_wbm_addr_start_i : in std_logic; -- Indicates Address Start
pd_wbm_addr_i : in std_logic_vector(31 downto 0); -- Latched Address that will increment with data
--
-- Data
pd_wbm_data_valid_i : in std_logic; -- Indicates Data is valid
pd_wbm_data_last_i : in std_logic; -- Indicates end of the packet
pd_wbm_data_i : in std_logic_vector(31 downto 0); -- Data
pd_wbm_be_i : in std_logic_vector(3 downto 0); -- Byte Enable for data
---------------------------------------------------------
-- P2L Control
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- Ready to accept target write
p2l_rdy_o : out std_logic; -- De-asserted to pause transfer already in progress
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- Asserted when GN4124 ready to accept read completion with data
---------------------------------------------------------
-- To the L2P Interface
wbm_arb_valid_o : out std_logic; -- Read completion signals
wbm_arb_dframe_o : out std_logic; -- Toward the arbiter
wbm_arb_data_o : out std_logic_vector(31 downto 0);
wbm_arb_req_o : out std_logic;
arb_wbm_gnt_i : in std_logic;
---------------------------------------------------------
-- CSR wishbone interface
wb_clk_i : in std_logic; -- Wishbone bus clock
wb_adr_o : out std_logic_vector(30 downto 0); -- Address
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic; -- Strobe
wb_we_o : out std_logic; -- Write
wb_cyc_o : out std_logic; -- Cycle
wb_dat_i : in std_logic_vector(31 downto 0); -- Data in
wb_ack_i : in std_logic; -- Acknowledge
wb_stall_i : in std_logic; -- Stall
wb_err_i : in std_logic; -- Error
wb_rty_i : in std_logic; -- Retry
wb_int_i : in std_logic -- Interrupt
);
end component; -- wbmaster32
-----------------------------------------------------------------------------
component dma_controller
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- Interrupt request
dma_ctrl_irq_o : out std_logic_vector(1 downto 0);
---------------------------------------------------------
-- To the L2P DMA master and P2L DMA master
dma_ctrl_carrier_addr_o : out std_logic_vector(31 downto 0);
dma_ctrl_host_addr_h_o : out std_logic_vector(31 downto 0);
dma_ctrl_host_addr_l_o : out std_logic_vector(31 downto 0);
dma_ctrl_len_o : out std_logic_vector(31 downto 0);
dma_ctrl_start_l2p_o : out std_logic; -- To the L2P DMA master
dma_ctrl_start_p2l_o : out std_logic; -- To the P2L DMA master
dma_ctrl_start_next_o : out std_logic; -- To the P2L DMA master
dma_ctrl_done_i : in std_logic;
dma_ctrl_error_i : in std_logic;
dma_ctrl_byte_swap_o : out std_logic_vector(1 downto 0);
dma_ctrl_abort_o : out std_logic;
---------------------------------------------------------
-- From P2L DMA MASTER
next_item_carrier_addr_i : in std_logic_vector(31 downto 0);
next_item_host_addr_h_i : in std_logic_vector(31 downto 0);
next_item_host_addr_l_i : in std_logic_vector(31 downto 0);
next_item_len_i : in std_logic_vector(31 downto 0);
next_item_next_l_i : in std_logic_vector(31 downto 0);
next_item_next_h_i : in std_logic_vector(31 downto 0);
next_item_attrib_i : in std_logic_vector(31 downto 0);
next_item_valid_i : in std_logic;
---------------------------------------------------------
-- Wishbone Slave Interface
wb_clk_i : in std_logic; -- Bus clock
wb_adr_i : in std_logic_vector(3 downto 0); -- Adress
wb_dat_o : out std_logic_vector(31 downto 0); -- Data in
wb_dat_i : in std_logic_vector(31 downto 0); -- Data out
wb_sel_i : in std_logic_vector(3 downto 0); -- Byte select
wb_cyc_i : in std_logic; -- Read or write cycle
wb_stb_i : in std_logic; -- Read or write strobe
wb_we_i : in std_logic; -- Write
wb_ack_o : out std_logic -- Acknowledge
);
end component; -- dma_controller
-----------------------------------------------------------------------------
component l2p_dma_master
generic (
-- Enable byte swap module (if false, no swap)
g_BYTE_SWAP : boolean := false
);
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- From the DMA controller
dma_ctrl_target_addr_i : in std_logic_vector(31 downto 0);
dma_ctrl_host_addr_h_i : in std_logic_vector(31 downto 0);
dma_ctrl_host_addr_l_i : in std_logic_vector(31 downto 0);
dma_ctrl_len_i : in std_logic_vector(31 downto 0);
dma_ctrl_start_l2p_i : in std_logic;
dma_ctrl_done_o : out std_logic;
dma_ctrl_error_o : out std_logic;
dma_ctrl_byte_swap_i : in std_logic_vector(1 downto 0);
dma_ctrl_abort_i : in std_logic;
---------------------------------------------------------
-- To the L2P Interface (send the DMA data)
ldm_arb_valid_o : out std_logic; -- Read completion signals
ldm_arb_dframe_o : out std_logic; -- Toward the arbiter
ldm_arb_data_o : out std_logic_vector(31 downto 0);
ldm_arb_req_o : out std_logic;
arb_ldm_gnt_i : in std_logic;
---------------------------------------------------------
-- L2P channel control
l2p_edb_o : out std_logic; -- Asserted when transfer is aborted
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Asserted when GN4124 is ready to receive master write
l2p_rdy_i : in std_logic; -- De-asserted to pause transfer already in progress
tx_error_i : in std_logic; -- Transmit Error
---------------------------------------------------------
-- DMA Interface (Pipelined Wishbone)
l2p_dma_clk_i : in std_logic; -- Bus clock
l2p_dma_adr_o : out std_logic_vector(31 downto 0); -- Adress
l2p_dma_dat_i : in std_logic_vector(31 downto 0); -- Data in
l2p_dma_dat_o : out std_logic_vector(31 downto 0); -- Data out
l2p_dma_sel_o : out std_logic_vector(3 downto 0); -- Byte select
l2p_dma_cyc_o : out std_logic; -- Read or write cycle
l2p_dma_stb_o : out std_logic; -- Read or write strobe
l2p_dma_we_o : out std_logic; -- Write
l2p_dma_ack_i : in std_logic; -- Acknowledge
l2p_dma_stall_i : in std_logic; -- for pipelined Wishbone
p2l_dma_cyc_i : in std_logic -- P2L dma wb cycle (for bus arbitration)
);
end component; -- l2p_dma_master
-----------------------------------------------------------------------------
component p2l_dma_master
generic (
-- Enable byte swap module (if false, no swap)
g_BYTE_SWAP : boolean := false
);
port
(
---------------------------------------------------------
-- Clock/Reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- From the DMA controller
dma_ctrl_carrier_addr_i : in std_logic_vector(31 downto 0);
dma_ctrl_host_addr_h_i : in std_logic_vector(31 downto 0);
dma_ctrl_host_addr_l_i : in std_logic_vector(31 downto 0);
dma_ctrl_len_i : in std_logic_vector(31 downto 0);
dma_ctrl_start_p2l_i : in std_logic;
dma_ctrl_start_next_i : in std_logic;
dma_ctrl_done_o : out std_logic;
dma_ctrl_error_o : out std_logic;
dma_ctrl_byte_swap_i : in std_logic_vector(1 downto 0);
dma_ctrl_abort_i : in std_logic;
---------------------------------------------------------
-- From P2L Decoder (receive the read completion)
--
-- Header
pd_pdm_hdr_start_i : in std_logic; -- Indicates Header start cycle
pd_pdm_hdr_length_i : in std_logic_vector(9 downto 0); -- Latched LENGTH value from header
pd_pdm_hdr_cid_i : in std_logic_vector(1 downto 0); -- Completion ID
pd_pdm_master_cpld_i : in std_logic; -- Master read completion with data
pd_pdm_master_cpln_i : in std_logic; -- Master read completion without data
--
-- Data
pd_pdm_data_valid_i : in std_logic; -- Indicates Data is valid
pd_pdm_data_last_i : in std_logic; -- Indicates end of the packet
pd_pdm_data_i : in std_logic_vector(31 downto 0); -- Data
pd_pdm_be_i : in std_logic_vector(3 downto 0); -- Byte Enable for data
---------------------------------------------------------
-- P2L control
p2l_rdy_o : out std_logic; -- De-asserted to pause transfer already in progress
rx_error_o : out std_logic; -- Asserted when transfer is aborted
---------------------------------------------------------
-- To the L2P Interface (send the DMA Master Read request)
pdm_arb_valid_o : out std_logic; -- Read completion signals
pdm_arb_dframe_o : out std_logic; -- Toward the arbiter
pdm_arb_data_o : out std_logic_vector(31 downto 0);
pdm_arb_req_o : out std_logic;
arb_pdm_gnt_i : in std_logic;
---------------------------------------------------------
-- DMA Interface (Pipelined Wishbone)
p2l_dma_clk_i : in std_logic; -- Bus clock
p2l_dma_adr_o : out std_logic_vector(31 downto 0); -- Adress
p2l_dma_dat_i : in std_logic_vector(31 downto 0); -- Data in
p2l_dma_dat_o : out std_logic_vector(31 downto 0); -- Data out
p2l_dma_sel_o : out std_logic_vector(3 downto 0); -- Byte select
p2l_dma_cyc_o : out std_logic; -- Read or write cycle
p2l_dma_stb_o : out std_logic; -- Read or write strobe
p2l_dma_we_o : out std_logic; -- Write
p2l_dma_ack_i : in std_logic; -- Acknowledge
p2l_dma_stall_i : in std_logic; -- for pipelined Wishbone
l2p_dma_cyc_i : in std_logic; -- L2P dma wb cycle (for bus arbitration)
---------------------------------------------------------
-- From P2L DMA MASTER
next_item_carrier_addr_o : out std_logic_vector(31 downto 0);
next_item_host_addr_h_o : out std_logic_vector(31 downto 0);
next_item_host_addr_l_o : out std_logic_vector(31 downto 0);
next_item_len_o : out std_logic_vector(31 downto 0);
next_item_next_l_o : out std_logic_vector(31 downto 0);
next_item_next_h_o : out std_logic_vector(31 downto 0);
next_item_attrib_o : out std_logic_vector(31 downto 0);
next_item_valid_o : out std_logic
);
end component; -- p2l_dma_master
-----------------------------------------------------------------------------
component l2p_arbiter
port (
---------------------------------------------------------
-- Clock/Reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- From Wishbone master (wbm) to arbiter (arb)
wbm_arb_valid_i : in std_logic;
wbm_arb_dframe_i : in std_logic;
wbm_arb_data_i : in std_logic_vector(31 downto 0);
wbm_arb_req_i : in std_logic;
arb_wbm_gnt_o : out std_logic;
---------------------------------------------------------
-- From DMA controller (pdm) to arbiter (arb)
pdm_arb_valid_i : in std_logic;
pdm_arb_dframe_i : in std_logic;
pdm_arb_data_i : in std_logic_vector(31 downto 0);
pdm_arb_req_i : in std_logic;
arb_pdm_gnt_o : out std_logic;
---------------------------------------------------------
-- From P2L DMA master (ldm) to arbiter (arb)
ldm_arb_valid_i : in std_logic;
ldm_arb_dframe_i : in std_logic;
ldm_arb_data_i : in std_logic_vector(31 downto 0);
ldm_arb_req_i : in std_logic;
arb_ldm_gnt_o : out std_logic;
---------------------------------------------------------
-- From arbiter (arb) to serializer (ser)
arb_ser_valid_o : out std_logic;
arb_ser_dframe_o : out std_logic;
arb_ser_data_o : out std_logic_vector(31 downto 0)
);
end component; -- l2p_arbiter
-----------------------------------------------------------------------------
component fifo_32x512
port (
rst : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(31 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
prog_full_thresh_assert : in std_logic_vector(8 downto 0);
prog_full_thresh_negate : in std_logic_vector(8 downto 0);
dout : out std_logic_vector(31 downto 0);
full : out std_logic;
empty : out std_logic;
valid : out std_logic;
prog_full : out std_logic);
end component;
-----------------------------------------------------------------------------
component fifo_64x512
port (
rst : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(63 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
prog_full_thresh_assert : in std_logic_vector(8 downto 0);
prog_full_thresh_negate : in std_logic_vector(8 downto 0);
dout : out std_logic_vector(63 downto 0);
full : out std_logic;
empty : out std_logic;
valid : out std_logic;
prog_full : out std_logic);
end component;
end gn4124_core_pkg;
package body gn4124_core_pkg is
-----------------------------------------------------------------------------
-- Byte swap function
--
-- enable | byte_swap | din | dout
-- false | XX | ABCD | ABCD
-- true | 00 | ABCD | ABCD
-- true | 01 | ABCD | BADC
-- true | 10 | ABCD | CDAB
-- true | 11 | ABCD | DCBA
-----------------------------------------------------------------------------
function f_byte_swap (
constant enable : boolean;
signal din : std_logic_vector(31 downto 0);
signal byte_swap : std_logic_vector(1 downto 0))
return std_logic_vector is
variable dout : std_logic_vector(31 downto 0) := din;
begin
if (enable = true) then
case byte_swap is
when "00" =>
dout := din;
when "01" =>
dout := din(23 downto 16)
& din(31 downto 24)
& din(7 downto 0)
& din(15 downto 8);
when "10" =>
dout := din(15 downto 0)
& din(31 downto 16);
when "11" =>
dout := din(7 downto 0)
& din(15 downto 8)
& din(23 downto 16)
& din(31 downto 24);
when others =>
dout := din;
end case;
else
dout := din;
end if;
return dout;
end function f_byte_swap;
-----------------------------------------------------------------------------
-- Returns log of 2 of a natural number
-----------------------------------------------------------------------------
function log2_ceil(N : natural) return positive is
begin
if N <= 2 then
return 1;
elsif N mod 2 = 0 then
return 1 + log2_ceil(N/2);
else
return 1 + log2_ceil((N+1)/2);
end if;
end;
end gn4124_core_pkg;
| gpl-3.0 | 43aa5eb3851ddac6a6d31728c2096179 | 0.434222 | 4.126971 | false | false | false | false |
rjarzmik/mips_processor | DI/Decode.vhd | 1 | 19,714 | -------------------------------------------------------------------------------
-- Title : Decode and Issue instruction
-- Project :
-------------------------------------------------------------------------------
-- File : Decode.vhd
-- Author : Robert Jarzmik <[email protected]>
-- Company :
-- Created : 2016-11-12
-- Last update: 2017-01-04
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Decode and Issue a MIPS instruction
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-11-12 1.0 rj Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cpu_defs.all;
use work.instruction_defs.all;
-------------------------------------------------------------------------------
entity Decode is
generic (
ADDR_WIDTH : integer := 32;
DATA_WIDTH : integer := 32;
NB_REGISTERS : positive := 34;
NB_REGISTERS_SPECIAL : positive := 2;
REG_IDX_MFLO : natural := 32;
REG_IDX_MFHI : natural := 33
);
port (
clk : in std_logic;
rst : in std_logic;
stall_req : in std_logic; -- stall current instruction
kill_req : in std_logic; -- kill current instruction
i_instruction : in std_logic_vector(DATA_WIDTH - 1 downto 0);
i_pc : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
i_instr_tag : in instr_tag_t;
--- Writeback input
i_rwb_reg1 : in register_port_type;
i_rwb_reg2 : in register_port_type;
--- Bypass input
i_bp_reg1 : in register_port_type;
i_bp_reg2 : in register_port_type;
--- Outputs
o_alu_op : out alu_op_type;
o_reg1 : out register_port_type;
o_reg2 : out register_port_type;
o_jump_target : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
o_jump_op : out jump_type;
o_mem_data : out std_logic_vector(DATA_WIDTH - 1 downto 0);
o_mem_op : out memory_op_type;
o_divide_0 : out std_logic; -- if set, a division attempt will be a X/0
o_instr_tag : out instr_tag_t;
--- Control and bypass outputs
o_src_reg1_idx : out natural range 0 to NB_REGISTERS - 1;
o_src_reg2_idx : out natural range 0 to NB_REGISTERS - 1;
-- Debug signal
i_dbg_di_pc : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
o_dbg_di_pc : out std_logic_vector(ADDR_WIDTH - 1 downto 0)
);
constant op_rtype : std_logic_vector(5 downto 0) := "000000";
constant op_addi : std_logic_vector(5 downto 0) := "001000";
constant op_addiu : std_logic_vector(5 downto 0) := "001001";
constant op_slti : std_logic_vector(5 downto 0) := "001010";
constant op_sltiu : std_logic_vector(5 downto 0) := "001011";
constant op_andi : std_logic_vector(5 downto 0) := "001100";
constant op_ori : std_logic_vector(5 downto 0) := "001101";
constant op_xori : std_logic_vector(5 downto 0) := "001110";
constant op_lui : std_logic_vector(5 downto 0) := "001111";
constant op_lb : std_logic_vector(5 downto 0) := "100000";
constant op_lw : std_logic_vector(5 downto 0) := "100011";
constant op_lbu : std_logic_vector(5 downto 0) := "100100";
constant op_sb : std_logic_vector(5 downto 0) := "101000";
constant op_sw : std_logic_vector(5 downto 0) := "101011";
constant op_beq : std_logic_vector(5 downto 0) := "000100";
constant op_bne : std_logic_vector(5 downto 0) := "000101";
constant op_blez : std_logic_vector(5 downto 0) := "000110";
constant op_bgtz : std_logic_vector(5 downto 0) := "000111";
constant op_bltz : std_logic_vector(5 downto 0) := "000001";
constant op_j : std_logic_vector(5 downto 0) := "000010";
constant op_jalr : std_logic_vector(5 downto 0) := "000011";
constant func_nop : std_logic_vector(5 downto 0) := "000000";
constant func_mul : std_logic_vector(5 downto 0) := "011000";
constant func_mulu : std_logic_vector(5 downto 0) := "011001";
constant func_div : std_logic_vector(5 downto 0) := "011010";
constant func_divu : std_logic_vector(5 downto 0) := "011011";
constant func_add : std_logic_vector(5 downto 0) := "100000";
constant func_addu : std_logic_vector(5 downto 0) := "100001";
constant func_sub : std_logic_vector(5 downto 0) := "100010";
constant func_subu : std_logic_vector(5 downto 0) := "100011";
constant func_slt : std_logic_vector(5 downto 0) := "101010";
constant func_sltu : std_logic_vector(5 downto 0) := "101011";
constant func_and : std_logic_vector(5 downto 0) := "100100";
constant func_or : std_logic_vector(5 downto 0) := "100101";
constant func_nor : std_logic_vector(5 downto 0) := "100111";
constant func_xor : std_logic_vector(5 downto 0) := "101000";
constant func_jr : std_logic_vector(5 downto 0) := "001000";
constant func_jalr : std_logic_vector(5 downto 0) := "001001";
constant func_mfhi : std_logic_vector(5 downto 0) := "010000";
constant func_mflo : std_logic_vector(5 downto 0) := "010010";
end entity Decode;
-------------------------------------------------------------------------------
architecture rtl of Decode is
subtype addr_t is std_logic_vector(ADDR_WIDTH - 1 downto 0);
subtype data_t is std_logic_vector(DATA_WIDTH - 1 downto 0);
alias ra : std_logic_vector(DATA_WIDTH - 1 downto 0) is o_reg1.data;
alias rb : std_logic_vector(DATA_WIDTH - 1 downto 0) is o_reg2.data;
signal alu_op : alu_op_type;
component RegisterFile is
generic (
DATA_WIDTH : positive;
NB_REGISTERS : positive;
NB_REGISTERS_SPECIAL : positive);
port (
clk : in std_logic;
rst : in std_logic;
stall_req : in std_logic;
a_idx : in natural range 0 to NB_REGISTERS + NB_REGISTERS_SPECIAL - 1;
b_idx : in natural range 0 to NB_REGISTERS + NB_REGISTERS_SPECIAL - 1;
rwb_reg1_we : in std_logic;
rwb_reg1_idx : in natural range 0 to NB_REGISTERS + NB_REGISTERS_SPECIAL - 1;
rwb_reg1_data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
rwb_reg2_we : in std_logic;
rwb_reg2_idx : in natural range 0 to NB_REGISTERS + NB_REGISTERS_SPECIAL - 1;
rwb_reg2_data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
a : out std_logic_vector(DATA_WIDTH - 1 downto 0);
b : out std_logic_vector(DATA_WIDTH - 1 downto 0));
end component RegisterFile;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal op_code : std_logic_vector(5 downto 0);
signal func : std_logic_vector(5 downto 0);
signal rsi : natural range 0 to NB_REGISTERS - 1;
signal rti : natural range 0 to NB_REGISTERS - 1;
signal rdi : natural range 0 to NB_REGISTERS - 1;
signal rfile_rs : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal rfile_rt : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal immediate : signed(DATA_WIDTH / 2 - 1 downto 0);
signal next_pc : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal pc_displace : std_logic_vector(25 downto 0);
signal decode_error : std_logic;
-- Enable writeback of register file if not stalled
signal rwb_reg1_we : std_logic;
signal rwb_reg2_we : std_logic;
type reg_src is (bypassed_regfile, zero, immediate_unsigned, immediate_signextend);
signal ra_src : reg_src;
signal rb_src : reg_src;
signal bp_rs : register_port_type;
signal bp_rt : register_port_type;
constant r0 : data_t := (others => '0');
signal rimmediate : std_logic_vector(DATA_WIDTH / 2 - 1 downto 0);
signal rimmediate_unsigned : data_t;
signal rimmediate_signextend : data_t;
type jt_t is (jt_rs, jt_rt, jt_absolute, jt_pcrelative);
signal jt_src : jt_t;
signal jt_addr_absolute : addr_t;
signal jt_addr_pcrelative : addr_t;
signal jt_mux_addr : addr_t;
signal jt_mux_reg : addr_t;
begin -- architecture rtl
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
rfile : RegisterFile
generic map (
DATA_WIDTH => DATA_WIDTH,
NB_REGISTERS => NB_REGISTERS - NB_REGISTERS_SPECIAL,
NB_REGISTERS_SPECIAL => NB_REGISTERS_SPECIAL)
port map (
clk => clk,
rst => rst,
stall_req => stall_req,
a_idx => rsi,
b_idx => rti,
a => rfile_rs,
b => rfile_rt,
rwb_reg1_we => rwb_reg1_we,
rwb_reg1_idx => i_rwb_reg1.idx,
rwb_reg1_data => i_rwb_reg1.data,
rwb_reg2_we => rwb_reg2_we,
rwb_reg2_idx => i_rwb_reg2.idx,
rwb_reg2_data => i_rwb_reg2.data
);
next_pc <= std_logic_vector(unsigned(i_pc) + 4);
op_code <= i_instruction(31 downto 26);
func <= i_instruction(5 downto 0);
immediate <= (others => '0') when rst = '1' else signed(i_instruction(15 downto 0));
instr_tag_p : process(clk, rst, kill_req, stall_req, op_code, func,
i_instr_tag)
variable is_br : boolean;
variable is_jr : boolean;
variable is_jump : boolean;
variable itag : instr_tag_t;
begin
itag := i_instr_tag;
is_br := (op_code = op_beq) or (op_code = op_bne) or (op_code = op_blez) or
(op_code = op_bgtz) or (op_code = op_bltz);
is_jr := (op_code = op_rtype) and (func = func_jr);
is_jump := (op_code = op_j or op_code = op_jalr);
itag := get_instr_change_is_branch(
get_instr_change_is_ja(
get_instr_change_is_jr(itag, is_jr), is_jump), is_br);
if rst = '1' then
o_instr_tag <= INSTR_TAG_NONE;
elsif rising_edge(clk) then
if kill_req = '1' then
o_instr_tag <= INSTR_TAG_NONE;
elsif stall_req = '1' then
else
o_instr_tag <= itag;
end if;
end if;
end process instr_tag_p;
alu : process(clk, rst, kill_req, stall_req, op_code, func, alu_op)
begin
if rst = '1' then
alu_op <= all_zero;
elsif rising_edge(clk) then
if kill_req = '1' then
alu_op <= all_zero;
elsif stall_req = '1' then
else
case op_code is
when op_beq | op_bne | op_blez | op_bgtz | op_bltz =>
alu_op <= substract;
when op_lw | op_lbu | op_lb | op_sw | op_sb =>
alu_op <= add;
when op_lui =>
alu_op <= add;
when op_addi | op_addiu => alu_op <= add;
when op_slti | op_sltiu => alu_op <= slt;
when op_andi => alu_op <= log_and;
when op_ori => alu_op <= log_or;
when op_xori => alu_op <= log_xor;
when op_rtype =>
case func is
when func_mul | func_mulu => alu_op <= multiply;
when func_div | func_divu => alu_op <= divide;
when func_add | func_addu => alu_op <= add;
when func_sub | func_subu => alu_op <= substract;
when func_slt | func_sltu => alu_op <= slt;
when func_and => alu_op <= log_and;
when func_or => alu_op <= log_or;
when func_nor => alu_op <= log_nor;
when func_xor => alu_op <= log_xor;
when others => alu_op <= all_zero;
end case;
when others => alu_op <= all_zero;
end case;
end if;
end if;
o_alu_op <= alu_op;
end process alu;
registers : process(clk, stall_req, op_code, func, i_instruction, rimmediate,
ra_src, rb_src, bp_rs, bp_rt, rfile_rs, rfile_rt,
rimmediate_unsigned, rimmediate_signextend)
variable asrc, bsrc : reg_src;
begin
rsi <= to_integer(unsigned(i_instruction(25 downto 21)));
rti <= to_integer(unsigned(i_instruction(20 downto 16)));
rdi <= to_integer(unsigned(i_instruction(15 downto 11)));
rimmediate_signextend(immediate'length - 1 downto 0) <= rimmediate;
rimmediate_signextend(rimmediate_signextend'length - 1 downto rimmediate'length)
<= (others => rimmediate(rimmediate'length - 1));
rimmediate_unsigned(rimmediate'length - 1 downto 0) <= rimmediate;
rimmediate_unsigned(rimmediate_unsigned'length - 1 downto rimmediate'length)
<= (others => '0');
if rising_edge(clk) and stall_req = '0' then
rimmediate <= i_instruction(rimmediate'length - 1 downto 0);
bp_rs <= i_bp_reg1;
bp_rt <= i_bp_reg2;
case op_code is
when op_rtype =>
asrc := bypassed_regfile;
bsrc := bypassed_regfile;
when op_addi | op_addiu | op_slti | op_sltiu |
op_andi | op_ori | op_xori =>
asrc := bypassed_regfile;
bsrc := immediate_signextend;
when op_lw | op_lbu | op_lb | op_sw | op_sb =>
asrc := bypassed_regfile;
bsrc := immediate_unsigned;
when op_lui =>
asrc := zero;
bsrc := immediate_unsigned;
when others =>
asrc := bypassed_regfile;
bsrc := bypassed_regfile;
end case;
ra_src <= asrc;
rb_src <= bsrc;
end if;
if ra_src = bypassed_regfile or ra_src = zero then
if ra_src = bypassed_regfile then
if bp_rs.we = '1' then
ra <= bp_rs.data;
else
ra <= rfile_rs;
end if;
else
ra <= r0;
end if;
else
ra <= r0;
end if;
if rb_src = bypassed_regfile or rb_src = zero then
if rb_src = bypassed_regfile then
if bp_rt.we = '1' then
rb <= bp_rt.data;
else
rb <= rfile_rt;
end if;
else
rb <= r0;
end if;
else
if rb_src = immediate_unsigned then
rb <= rimmediate_unsigned;
else
rb <= rimmediate_signextend;
end if;
end if;
end process registers;
rwb_reg1_we <= i_rwb_reg1.we;
rwb_reg2_we <= i_rwb_reg2.we;
rtargets : process(rst, clk, kill_req, stall_req, op_code, func, rsi, rti, rdi)
variable reg1_we : std_ulogic;
variable reg1_idx : natural range 0 to NB_REGISTERS - 1;
variable reg2_we : std_ulogic;
variable reg2_idx : natural range 0 to NB_REGISTERS - 1;
begin
reg1_we := '0';
reg2_we := '0';
reg1_idx := 0;
reg2_idx := 0;
case op_code is
when op_rtype =>
case func is
when func_mul | func_mulu | func_div | func_divu =>
reg1_we := '1';
reg1_idx := REG_IDX_MFLO;
reg2_we := '1';
reg2_idx := REG_IDX_MFHI;
when func_nop =>
when others =>
reg1_we := '1';
reg1_idx := rdi;
end case;
when op_addi | op_addiu | op_slti | op_sltiu |
op_andi | op_ori | op_xori =>
reg1_we := '1';
reg1_idx := rti;
when op_lw | op_lbu | op_lb =>
reg1_we := '1';
reg1_idx := rti;
when op_lui =>
reg1_we := '1';
reg1_idx := rti;
when op_jalr =>
reg1_we := '1';
reg1_idx := NB_REGISTERS - NB_REGISTERS_SPECIAL - 1;
when others =>
end case;
if rst = '1' then
o_reg1.we <= '0';
o_reg2.we <= '0';
o_reg1.idx <= 0;
o_reg2.idx <= 0;
else
if rising_edge(clk) then
if kill_req = '1' then
o_reg1.we <= '0';
o_reg2.we <= '0';
o_reg1.idx <= 0;
o_reg2.idx <= 0;
o_src_reg1_idx <= 0;
o_src_reg2_idx <= 0;
elsif stall_req = '1' then
else
o_reg1.we <= reg1_we;
o_reg2.we <= reg2_we;
o_reg1.idx <= reg1_idx;
o_reg2.idx <= reg2_idx;
end if;
end if;
end if;
o_src_reg1_idx <= rsi;
o_src_reg2_idx <= rti;
end process rtargets;
memory_p : process(rst, clk, kill_req, stall_req, op_code, rimmediate_signextend)
variable mo : memory_op_type;
begin
case op_code is
when op_lw => mo := loadw;
when op_lbu => mo := load8;
when op_lb => mo := load8_signextend32;
when op_sw => mo := storew;
when op_sb => mo := store8;
when others => mo := none;
end case;
if rst = '1' then
o_mem_op <= none;
elsif rising_edge(clk) then
if kill_req = '1' then
o_mem_op <= none;
elsif stall_req = '1' then
else
o_mem_op <= mo;
end if;
end if;
o_mem_data <= rimmediate_signextend;
end process memory_p;
jumper_op : process(rst, clk, stall_req, kill_req, op_code, func)
variable jump_op : jump_type;
begin
case op_code is
when op_rtype =>
if func = func_jr or func = func_jalr then
jump_op := always;
else
jump_op := none;
end if;
when op_beq =>
jump_op := zero;
when op_bne =>
jump_op := non_zero;
when op_blez =>
jump_op := lesser_or_zero;
when op_bgtz =>
jump_op := greater;
when op_bltz =>
jump_op := lesser;
when others =>
jump_op := none;
end case;
if rst = '1' then
o_jump_op <= none;
elsif rising_edge(clk) then
if kill_req = '1' then
o_jump_op <= none;
elsif stall_req = '1' then
else
o_jump_op <= jump_op;
end if;
end if;
end process jumper_op;
jumper_target : process(clk, stall_req, op_code, func, i_instruction,
next_pc, jt_mux_reg, jt_src,
jt_addr_pcrelative, jt_addr_absolute)
variable src : jt_t;
begin
pc_displace <= i_instruction(23 downto 0) & b"00";
case op_code is
when op_rtype =>
if func = func_jr then
src := jt_rs;
else
src := jt_absolute;
end if;
when op_beq | op_bne | op_blez | op_bgtz | op_bltz =>
src := jt_pcrelative;
when others =>
src := jt_absolute;
end case;
if rising_edge(clk) and stall_req = '0' then
jt_src <= src;
jt_addr_absolute <= next_pc(ADDR_WIDTH - 1 downto pc_displace'length) & pc_displace;
jt_addr_pcrelative <= std_logic_vector(unsigned(next_pc) +
unsigned(resize(immediate * 4, ADDR_WIDTH)));
end if;
if jt_src = jt_absolute then
jt_mux_reg <= jt_addr_absolute;
else
jt_mux_reg <= jt_addr_pcrelative;
end if;
if jt_src = jt_rs then
o_jump_target <= ra;
else
o_jump_target <= jt_mux_reg;
end if;
end process jumper_target;
debug : process(rst, clk, stall_req, kill_req)
begin
if rst = '1' then
o_dbg_di_pc <= (others => 'X');
elsif rising_edge(clk) and kill_req = '1' then
o_dbg_di_pc <= (others => 'X');
elsif rising_edge(clk) and stall_req = '1' then
elsif rising_edge(clk) then
o_dbg_di_pc <= i_dbg_di_pc;
end if;
end process debug;
end architecture rtl;
| gpl-3.0 | fc7803f16750331f78b9935101f388d1 | 0.526225 | 3.383797 | false | false | false | false |
okaxaki/vm2413 | vm2413.vhd | 2 | 10,377 | --
-- VM2413.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
package VM2413 is
constant MAXCH : integer := 9;
constant MAXSLOT : integer := MAXCH * 2;
subtype CH_TYPE is integer range 0 to MAXCH-1;
subtype SLOT_TYPE is integer range 0 to MAXSLOT-1;
subtype STAGE_TYPE is integer range 0 to 3;
subtype REGS_VECTOR_TYPE is std_logic_vector(23 downto 0);
type REGS_TYPE is record
INST : std_logic_vector(3 downto 0);
VOL : std_logic_vector(3 downto 0);
SUS : std_logic;
KEY : std_logic;
BLK : std_logic_vector(2 downto 0);
FNUM : std_logic_vector(8 downto 0);
end record;
function CONV_REGS_VECTOR ( regs : REGS_TYPE ) return REGS_VECTOR_TYPE;
function CONV_REGS ( vec : REGS_VECTOR_TYPE ) return REGS_TYPE;
subtype VOICE_ID_TYPE is integer range 0 to 37;
subtype VOICE_VECTOR_TYPE is std_logic_vector(35 downto 0);
type VOICE_TYPE is record
AM, PM, EG, KR : std_logic;
ML : std_logic_vector(3 downto 0);
KL : std_logic_vector(1 downto 0);
TL : std_logic_vector(5 downto 0);
WF : std_logic;
FB : std_logic_vector(2 downto 0);
AR, DR, SL, RR : std_logic_vector(3 downto 0);
end record;
function CONV_VOICE_VECTOR ( inst : VOICE_TYPE ) return VOICE_VECTOR_TYPE;
function CONV_VOICE ( inst_vec : VOICE_VECTOR_TYPE ) return VOICE_TYPE;
-- Voice Parameter Types
subtype AM_TYPE is std_logic; -- AM switch - '0':off '1':3.70Hz
subtype PM_TYPE is std_logic; -- PM switch - '0':stop '1':6.06Hz
subtype EG_TYPE is std_logic; -- Envelope type - '0':release '1':sustine
subtype KR_TYPE is std_logic; -- Keyscale Rate
subtype ML_TYPE is std_logic_vector(3 downto 0); -- Multiple
subtype WF_TYPE is std_logic; -- WaveForm - '0':sine '1':half-sine
subtype FB_TYPE is std_logic_vector(2 downto 0); -- Feedback
subtype AR_TYPE is std_logic_vector(3 downto 0); -- Attack Rate
subtype DR_TYPE is std_logic_vector(3 downto 0); -- Decay Rate
subtype SL_TYPE is std_logic_vector(3 downto 0); -- Sustine Level
subtype RR_TYPE is std_logic_vector(3 downto 0); -- Release Rate
-- F-Number, Block and Rks(Rate and key-scale) types
subtype BLK_TYPE is std_logic_vector(2 downto 0); -- Block
subtype FNUM_TYPE is std_logic_vector(8 downto 0); -- F-Number
subtype RKS_TYPE is std_logic_vector(3 downto 0); -- Rate-KeyScale
-- 18 bits phase counter
subtype PHASE_TYPE is std_logic_vector (17 downto 0);
-- Phage generator's output
subtype PGOUT_TYPE is std_logic_vector (8 downto 0);
-- Final linear output of opll
subtype LI_TYPE is std_logic_vector (8 downto 0); -- Wave in Linear
-- Total Level and Envelope output
subtype DB_TYPE is std_logic_vector(6 downto 0); -- Wave in dB, Reso: 0.375dB
subtype SIGNED_LI_VECTOR_TYPE is std_logic_vector(LI_TYPE'high + 1 downto 0);
type SIGNED_LI_TYPE is record
sign : std_logic;
value : LI_TYPE;
end record;
function CONV_SIGNED_LI_VECTOR( li : SIGNED_LI_TYPE ) return SIGNED_LI_VECTOR_TYPE;
function CONV_SIGNED_LI( vec : SIGNED_LI_VECTOR_TYPE ) return SIGNED_LI_TYPE;
subtype SIGNED_DB_VECTOR_TYPE is std_logic_vector(DB_TYPE'high + 1 downto 0);
type SIGNED_DB_TYPE is record
sign : std_logic;
value : DB_TYPE;
end record;
function CONV_SIGNED_DB_VECTOR( db : SIGNED_DB_TYPE ) return SIGNED_DB_VECTOR_TYPE;
function CONV_SIGNED_DB( vec : SIGNED_DB_VECTOR_TYPE ) return SIGNED_DB_TYPE;
-- Envelope generator states
subtype EGSTATE_TYPE is std_logic_vector(1 downto 0);
constant Attack : EGSTATE_TYPE := "01";
constant Decay : EGSTATE_TYPE := "10";
constant Release : EGSTATE_TYPE := "11";
constant Finish : EGSTATE_TYPE := "00";
-- Envelope generator phase
subtype EGPHASE_TYPE is std_logic_vector(22 downto 0);
-- Envelope data (state and phase)
type EGDATA_TYPE is record
state : EGSTATE_TYPE;
phase : EGPHASE_TYPE;
end record;
subtype EGDATA_VECTOR_TYPE is std_logic_vector(EGSTATE_TYPE'high + EGPHASE_TYPE'high + 1 downto 0);
function CONV_EGDATA_VECTOR( data : EGDATA_TYPE ) return EGDATA_VECTOR_TYPE;
function CONV_EGDATA( vec : EGDATA_VECTOR_TYPE ) return EGDATA_TYPE;
component Opll port(
XIN : in std_logic;
XOUT : out std_logic;
XENA : in std_logic;
D : in std_logic_vector(7 downto 0);
A : in std_logic;
CS_n : in std_logic;
WE_n : in std_logic;
IC_n : in std_logic;
MO : out std_logic_vector(9 downto 0);
RO : out std_logic_vector(9 downto 0)
);
end component;
component Controller port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
wr : in std_logic;
addr : in std_logic_vector(7 downto 0);
data : in std_logic_vector(7 downto 0);
am : out AM_TYPE;
pm : out PM_TYPE;
wf : out WF_TYPE;
ml : out ML_TYPE;
tl : out DB_TYPE;
fb : out FB_TYPE;
ar : out AR_TYPE;
dr : out DR_TYPE;
sl : out SL_TYPE;
rr : out RR_TYPE;
blk : out BLK_TYPE;
fnum : out FNUM_TYPE;
rks : out RKS_TYPE;
key : out std_logic;
rhythm : out std_logic
);
end component;
-- Slot and stage counter
component SlotCounter
generic (
DELAY : integer range 0 to MAXSLOT*4-1
);
port(
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : out SLOT_TYPE;
stage : out STAGE_TYPE
);
end component;
component EnvelopeGenerator
port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
rhythm : in std_logic;
am : in AM_TYPE;
tl : in DB_TYPE;
ar : in AR_TYPE;
dr : in DR_TYPE;
sl : in SL_TYPE;
rr : in RR_TYPE;
rks : in RKS_TYPE;
key : in std_logic;
egout : out DB_TYPE
);
end component;
component PhaseGenerator port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
rhythm : in std_logic;
pm : in PM_TYPE;
ml : in ML_TYPE;
blk : in BLK_TYPE;
fnum : in FNUM_TYPE;
key : in std_logic;
noise : out std_logic;
pgout : out PGOUT_TYPE
);
end component;
component Operator port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
rhythm : in std_logic;
WF : in WF_TYPE;
FB : in FB_TYPE;
noise : in std_logic;
pgout : in PGOUT_TYPE;
egout : in DB_TYPE;
faddr : out CH_TYPE;
fdata : in SIGNED_LI_TYPE;
opout : out SIGNED_DB_TYPE
);
end component;
component OutputGenerator port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
rhythm : in std_logic;
opout : in SIGNED_DB_TYPE;
faddr : in CH_TYPE;
fdata : out SIGNED_LI_TYPE;
maddr : in SLOT_TYPE;
mdata : out SIGNED_LI_TYPE
);
end component;
component TemporalMixer port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
rhythm : in std_logic;
maddr : out SLOT_TYPE;
mdata : in SIGNED_LI_TYPE;
mo : out std_logic_vector(9 downto 0);
ro : out std_logic_vector(9 downto 0)
);
end component;
end VM2413;
package body VM2413 is
function CONV_REGS_VECTOR ( regs : REGS_TYPE ) return REGS_VECTOR_TYPE is
begin
return regs.INST & regs.VOL & "00" & regs.SUS & regs.KEY & regs.BLK & regs.FNUM;
end CONV_REGS_VECTOR;
function CONV_REGS ( vec : REGS_VECTOR_TYPE ) return REGS_TYPE is
begin
return (
INST=>vec(23 downto 20), VOL=>vec(19 downto 16),
SUS=>vec(13), KEY=>vec(12), BLK=>vec(11 downto 9), FNUM=>vec(8 downto 0)
);
end CONV_REGS;
function CONV_VOICE_VECTOR ( inst : VOICE_TYPE ) return VOICE_VECTOR_TYPE is
begin
return inst.AM & inst.PM & inst.EG & inst.KR &
inst.ML & inst.KL & inst.TL & inst.WF & inst.FB &
inst.AR & inst.DR & inst.SL & inst.RR;
end CONV_VOICE_VECTOR;
function CONV_VOICE ( inst_vec : VOICE_VECTOR_TYPE ) return VOICE_TYPE is
begin
return (
AM=>inst_vec(35), PM=>inst_vec(34), EG=>inst_vec(33), KR=>inst_vec(32),
ML=>inst_vec(31 downto 28), KL=>inst_vec(27 downto 26), TL=>inst_vec(25 downto 20),
WF=>inst_vec(19), FB=>inst_vec(18 downto 16),
AR=>inst_vec(15 downto 12), DR=>inst_vec(11 downto 8), SL=>inst_vec(7 downto 4), RR=>inst_vec(3 downto 0)
);
end CONV_VOICE;
function CONV_SIGNED_LI_VECTOR( li : SIGNED_LI_TYPE ) return SIGNED_LI_VECTOR_TYPE is
begin
return li.sign & li.value;
end;
function CONV_SIGNED_LI( vec : SIGNED_LI_VECTOR_TYPE ) return SIGNED_LI_TYPE is
begin
return ( sign => vec(vec'high), value=>vec(vec'high-1 downto 0) );
end;
function CONV_SIGNED_DB_VECTOR( db : SIGNED_DB_TYPE ) return SIGNED_DB_VECTOR_TYPE is
begin
return db.sign & db.value;
end;
function CONV_SIGNED_DB( vec : SIGNED_DB_VECTOR_TYPE ) return SIGNED_DB_TYPE is
begin
return ( sign => vec(vec'high), value=>vec(vec'high-1 downto 0) );
end;
function CONV_EGDATA_VECTOR( data : EGDATA_TYPE ) return EGDATA_VECTOR_TYPE is
begin
return data.state & data.phase;
end;
function CONV_EGDATA( vec : EGDATA_VECTOR_TYPE ) return EGDATA_TYPE is
begin
return ( state => vec(vec'high downto EGPHASE_TYPE'high + 1),
phase => vec(EGPHASE_TYPE'range) );
end;
end VM2413;
| mit | cc0b6d55c381e335905e4b63f0653082 | 0.590248 | 3.402295 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/blk_mem_gen_v8_0/blk_mem_gen_ecc_encoder.vhd | 2 | 20,893 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
TK94jT5BKUsHhZCc49J1z77fTRMf0luLtVCnashKi4Rz3dFAmYJ2qG51l8uUbtXOS4b9cXY0VgPn
joh0A6Wddg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
TiyULDtPByOksXKQKz0hpqm5Nr9Xm4owCVfWTEDzLSEPVlXniJf5mfFU0uWG/9J+AZ4FqwXJDD72
0nLdzfpc1SwqLzvv2KZZCrFhsChYKUgiMCoKsvpo5jLPkcdAa5be7qN//0Mx4/G2pfxb/6KM6lW8
h32JSOSgM31kMMyBJwI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
BonvIDRaePQNE/NO6Pu9LB37N86NEAbhrY/NcmEedGg0ihI67xCH8KXqgmN9gSjkUf5O9bohvMw1
wAdKDaxbtGZvJxGlxRSLo8eg10EVLicVrZPs/ibqHe0yQO66dPXwvnvxbO6CL6+VFRCOLVZLzyKn
iCWqtIYHEdpeiPQPscDUcQD/bCgXzaDl7nT80pS5OkUOp86uydeF6gTI8qpsnbEMdW7VHZTFDb9l
Y66fZObxVcQFp8SGqnJ6CMGT0y4TCstJ/Q7jS6MDYbYmsMVEKCfYyqi1tQqupqlOyTRZXGmhtBkB
COLdJ0n/+wz9b9nK+EhbYET0OLys2KukAB/X1Q==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
AwMZbgYHPqC74HT+q0xxJkthYysQrmjIazB2Ie12VyFTlKlAxTOlY/8snSB+8rIUNSam8gmLIyh2
qWYAIwfJ7k7vNXAwsLC4pVj1fV4ZIqOqrV5o3AU9GMkXULQnfOUsUgy13xkikQ2AxwMbscpZmuLC
tzj3OZjNk5lBoUIj62c=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
B/2v1PW4LQeaxBYbvbTvdvfeZQajgHIa1P0hfg5s+/H58FhYbPgwx8VidNJSo9SGQqJTfYlJdfj9
0N7WjwfUpzZmpR3+7JWKlnWXrCRrRj8jvNG6a3d0cnW414kB80Jh99soPINjvQKyeA5YQCPYjgFR
U60RP1yHmOvyfEMLznVKfpRkaf6VExO7GHDW7coLU3K5Xu8GzzO0JjFHMDDigzsr9SD46t0syFto
eIRoAKn7MYpoBUU3MJefJyVXADLvQVrPfC9DBysuP5K6tscCTKaa9pvRZxNeNcfWnupgpxjsOFsP
KccONyh4bhcoPtStQsAEaVGUD5XJ0xGIYx59gA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13728)
`protect data_block
QGAAsv5d9IRKTJOiA8tUia0U8nx2Q4wGstNvKoNoeXFVOv/DIP6kAYT3L8wBfoYEJs1WIAtI5w3v
57tHtvxmoRIE4HB5k3Ups4aVBrK+eSoSw6urUegE/gnuew+XGn4hKPFtN/GsrVKFNWcg3yPiYevd
5J+ayZ1FTCnmtrQ37ZjAIFUUVPtsZKzj8XowLxTVCGVyPKZTN7G1YE0fLJ3W64EIqwjwP2PbuUiy
xInjiEWY2vpnPDH8h8DhzVFzd6I/i/xG0XUbb2nwqx4PWa+6KCOO0kQ2DlRDc1qeSVie+/+3Kxv9
BV+EDh+A0h7L/F1BAmjQNQAs/smsEOXYfXed277BwAz1n7tFi8McCQLr5sT3J6NW582btx1EeSU+
2Q/s+Z3rnR+RKEe1JdPhjnTnB/l0MK0LRIZp4f5Uy5cPqA9fsNaeI62Fiz3uW8CeZabjYwxe6f4C
nAu1ZGG0fYr4fPtyIXMxnbDwqE4u81jDTZy+jczvC75iiHqWMELNzWQeLFT+r2O/DXvTiJNBYZ6F
wTjDIU5r9Jgv0TtGGEcuMXfWSlAC8C/WbpIS7cRt1UuxgaivEt9Pam/hutrNULUbDtEwFearB4Lc
L2qUhjGsDj8S5eZS6gpRv5VvOi/+0INMQXozyVLnesNqE76eOBQIEwQr6GnLeYLSFMORz7piQ9Ex
xPKe+X4QrWhhPDU2ZkarBFrh8k9mlzZ+Ot8puY6xrXJhPdwQakKzQXg3OAY/q17oqI41eo5MI+zm
Mhxlz+6MSQjhkHV3/dXmr56mr74DJ+DGbpD8sIbp8fYVWMDIn5zh2rrd4YsYnQbp1br8r9sP+BQu
lftUdwGXZCURWppDO9xZlKUS7vsbZZVSjSwxaSOcXs8XMb6Y4JJoeXYfEeydrdUJeXFoGTEDnAw1
F8fyVeq6/y72dZS/YaPSCPLGSZCgzLh8H58q6s3GIaDnouf6TfpUIxAQnUBpLwhUAA03XeatJ9Ea
BdAeUlwrbBcYsQ5TWgRlnW8F86ZR9zA5qIro9oZvsFLAshLZ8rWXjJv776exKp3QZhSiom10xqOs
NtrM7P07xSn55Rz2dvRlz4R6thP9hZe9lw0u5Ap35ikfmpg4HWARxlyh0MAGu7d5wk/ewsrVl6p/
rsnbeD3kCi8Zb7OLAUV6Q9QMhMRO6FisFJp1m1L5vve/33yFEwyzdD3tAmus0jS2mhc8q94jUzBz
nULltwI8nDqLqxoQ8YHIqFf9ESkI7V5GwezuBoa7+oOY8gMzocid6AVbNKa0UMc8anG18w9b4wam
5Cdgt0YW7IFdbXqwiep6zbgjVUxj4xBNkrgIWIKj1Q/eSWY+p11xvXFRY7lBOkn7IRRtrzF+HNiW
XN9OSxYpn8M9uKN62ym1FHgtPv7G8apf7MR0LVsg7hdsYycFk/rs2nqk92DG1RuJMQWubE4dsKrj
/ciF5QrQvZbmMVt1m/e9wgcaLxXlaINIJcS+tGei98dcHdPOUKjxdHhBX3cuf8PklleilGWBdr/3
yvePWlu1wzEtKBSBpBRv95O8djUnxG4pEHZCJOBUCvNVzAoUuLgXOPgGPTcYKSXTp3WNSOhF6Cq5
HJAkiw5qztbJfOFRAqvfUmV2TjxVHKYanDw4j0D79Jk8/uFbdykbP2yaG9SeC8wfNDfQqSpb94MA
PMmXQ9I/nOWT4fxhfxdGFn6kZmmVmq1ZWbZYMSxqSpVLRBTTeEln+YnLYTxFIzSsJwBRDDJE/CHX
drxH4ZeLaebwAaMeAHKqliK82iNfwbBI5/U4w1jFvN0/B80JgkodfGMxMWTXiFrsQWx7acG7XdnM
qXpUOH6DkUTPZEkhNSJWeSfaRM4AT38DO6BNz7rUk9AulLdpb9WxsFdjAv9R+YbXiYgftrF2MUrD
tjivNj6fVQ5YJRtkT7omk8pPXgn0M7l5vnRqQS8StXNR5Hcz9zD9oHk+CgrS4RFRmKHs+ZODt5Vk
yFyPTw6tKvhXdkojUuirpcCrdNHNIVAbvJLR8TBvhJT11q/YLc5rGipoi7VTs3kgnwiLLO41fR2i
gf17v+2QXu+Hm3zCfMI11xyQjssz0UxRlEeDGzhhXOXsMaEqoJVz/9jnK1WN6eYGfdKB6HYkuEvU
tvvvBF1Ppv0XL13hrIzlT6IsFY77edIBttZTs6iMX75viXccpCsZiabLGI/BSQ6C8hbfHVJpZ/qP
F6a8fXrLoS9DPtS21cgf7iYSBEGg9GA/y+Y6wIYVZ2dkqr8iQUNN5u0ehyHFL/ve94yuMqEEzw4G
9r9dwHzCLGmzI+MuRqvoIxh//PufHYHt8gyO7XCR0mn+eWQWdsD/+E/sEINzQ2lbOIvnqk2V9G4/
Uiv5Gb+oDcP2PvxNB3hQcbRp2jYQ5OAPROqsvPAKbU3BVXCX3YtaDOPj5NlT2av/ajVjKc/IWonP
B4taL6hQ/i9cRfilEF675MSmiHlc0aFuDUSXKEEcq8Eia7odMTwpI1XXu7OJhu3TNFcSu8k+wikn
K0njEm6HLOxCAH2Et0ThW59stt6ngFOx6Ox99qOjPVYa3UYqRb1Tdhr6Jch9bj0ZJbHLAZC/PC37
k9OGtOSycKtJbBk0k2zLnW01n9RbhHJe7tYNmeOa7QgUnlZ0qEXWUKHSQUNwODE3KNGqAhqXTgdA
q/HNzQdBnQ56OehtnCvTA+WWjNrwk2ye0UplPGS4Tw6umsDJ1DOxEucpPzU144UiLHS1u8HQEEy3
XRwm+nhXnUQNElb0ZMDwpsrYxGsXN44GrOvjvZoXoozYRBPsoziPQ8/hFNLESlmXzHDp0XPfwdyx
6x0NHHkyD6i7nttWY9NnoRmXc5wpOMAw2YYE5+TeVzc/qSA8SMkxlb3KpYN9I6wbloniNrlMwqkC
4gOGfH9IKD5iiNZ0nTmCLTBFzLKRND+ow8ySiqGKgZoQmUOUOSzkhzqh1hsDFhBOpmbnwOuwD5UJ
WNBe3RUgAbyhWEcyWstMoE+Jsjv+GH3Sh9PmsmQyyszsrwWTHzYsltNjyXA2Rz7B1CdX4cxmB+8P
oyiu5L/0vaKDdX1ZXJsRtEqOR8Tvizw66XBhEeA1sWGo8vshUcDnPtTTCYVOQ4tUZtJPfY3bCxX6
5beDf30rKy70rVBo3127yhNOJFTzxRhczmm0LW/LHaFhz2TG/dFMENfBIyVH3YWBuipxYrzq7gqH
e0CPZeyMLjZv5hZh/OKlRR59L+XyxIgpTqtpzCBqJvrke6ylJysL2/vooxzV68Xe4lcfT97ynwo6
pZboBEetyXJI3SxvV0EaP+z5yhyAYkRY6AG14LyGwUI75xrBfYjFNcPTjvZD3EcIpBMVgA6CPTIq
w3FNmFyGFkOszfXfthjWdsbgT4aSd+PNbt8/Mg3YnruQjgkoVviQ2CBzoofe1BrNML+k95f+VZ4O
UmrUJQXvB5VexZlfPOTN1enEUCfKJq/e6cwOuj9HgepKPPrPw8Oj/rg3S+nCv+WwoMBGzR5vmwIN
vc3v5ioU1SOeDfuiE5mj2Q0TxvFGi//+v6Mg4KjeJtAidi53xh7GIKNEmxuQUSodJAti6lGalE5C
9Ofpzi5OmEXvooMI6jlbPVEa6kG/ANbVku1zFkFJz5+4mCy21lyBMP9KxECfhKwPHlcmwExgGE2C
eeg9locP+heLl8oWxoRiDIpGPZuvVpbooLqQQs0QLH4Ftbp3yAsG+j2fdTh3S/UFfhihOnXbQjBE
GH2yuGgE9mv39ZmPPCDHGurRZ5JEm+QgMVMaK0IvjhHjVmdOYEsWUYp0WETd48d6tJjZYXgYbjEz
x9IfRLebNgOSQyh0eITUszuzeUD9yYpliymxX6bLviZHR7jq7o7KW6cIxgdicOh5y4hrDFLbiai1
Vqf6dSXVwYtqxQY8HA81dYjsEulik74HRgFtvbZg/qdieOAcuJpxWACJvWCJX7DSRvdkJDc5LD7w
i6bD6FnGKfMNGvwYMQ5vfJTFlLUHNKvTeeNCMCn2aK6S4pQd0Tw2Nc2tgp903jmAN/z06DcPf8hv
1xni6RTAPCcNJKhzmISPtb7ksZJO4Ci8uWuX8pJ05+/NV0GQ0a8FuBZ3SYgJ1xkFrAPNkp17a4cn
0SyqKD99HfOxnw0xlThLa/BoEVNMa/CbtQ44GzF5TIKZzHzJQjMhdfLsmaHZ+iYtX492esu2cSXk
hijTnjHqMbK430m+lfG/KyYPbjpoSRbVGFD5Ccgyv/S8sxn7llSqC4+tBviiYa+1MfHP5/hZeL6I
a0xLV+CWh/4GzxGFn2u/DKXMugQNLfAxwV8Fbc8RhcU9opCZXF/tD5rB7uMYbnbY3a43KDDtsh/7
fxz7b/Wdj6lnUtAhfTlG+3RBXk//6PKm+GONhOFnHCbOBOwXvmWfhz+sdAdjrzMtv162KseHD20z
mL1wQSYTTw3GBV5suoEk1ihCYRAl5MMArLkwVG6cgl0TcxYwTBYLKJfFMLhgqgsBdXurEFi7GKG7
BDa1woilu2WMtcNYmZaui2czvz/EdFBHypQ3jsIrYXV5XP+Afjn3GnlIIpabnsX3kMOxiCnYmuKN
ZbPaNU5i2YTE5W/ErpVEglCjdS7oAaXKBBYPJWJuM/50Z2l6TaT/AxOB/2a3JmNTAoKud/2oBA68
RiUn+nAobHi4T0tzUK5sgWIvl//50Xjr9o695nCXTg/5aGq5BS/vI9NX8rb80vyFv9TE4+I4Pk2S
do4Kgv9t7+QC5cRLNOGBw9+YaQ9u4LnXsMPM6foFeq3ExKbVkWpoio2O6DMpkRQVFQqSGMX8Y6eF
Mg4RQa6GcjVgKfVKCgRwP1QdQvhVkPgcOe2zNWvePet6XQ8nZq7nYYY4HFN20k8pPsNJjVdU+6N4
8/cMOuOovS4rzro/ifV79+NPINDbx9TdYrikJ0bxMXxIQ9p/gw8V9/EUYAL49CmEINYZyWf2WBNR
LAj1HO6lQlg2nmNztJ0UzrfaYpsoDjWza3Lzwk/4ndXA2k1b03SfDIAKe3hSTRYLdINpyNBWnlil
Xeoud4hugo+1Ag6khBrY0f9u0VAJqgeT1iRUcmK0m9tVhdpFaFBcMFcgkJvIx+PiBHJ5G818Nlbz
3OA7L8crrT7otzvbaBLcoS4heZSsiNZNN79lezEiGmdm6VvF9o8pLuHUvhk8c3DIKG4BmeXLh2wV
I2ELZjP71n4l46yjy9F6jtI3tQEm3Ihn64aEMR0Kgr/8mffEoQ0FtceT5lJn+2Kg3Qt5NjyuzT6+
ORr+trZm38W1HepxYtkzrGyH28EtRyZ3AN8gxoZtO1cyEb3dDAT8bVWfGw5FS4/wAp0+aWt/5kCc
IQ4O429Q0IaynKFm4ygEiokoRt1e3/HMnPLcIkUfvDaLUw4DtBq/ZzJPQhvnfAjeYjUQvEeS1jAb
Etk5H7O9Yu7PiUsIupnKGXRbKjlTjouFERnUQEVfdQbzpk4Ta5V4yxtOh9cfyD1KYpnUR9DviAMX
b8zciGpY8Bzw31esrstd5pgu7y0VD1R+pftwX3H0ndlMFSraEOWGuPC+uvbHQLHV5sLOtZIsJP/0
fkTUXMDnWGKl24KzlZXiKt8evVa7tb9DWg7d8BH2GQroT6q7kcP1EycMboFGgZQKvHa8gOmkIUUo
EvTc97dMC4XnTNFcpFgOsIbcvnBQSG00GAxw5dhQFJPFSXGfhCoCsCFBmaiYVwJUr8Go8Y8aWyat
p89yHfvttDEO7kCeyS5aUgqCDDwYVGrPSaDtsAeC+IxsIW4zCstjNjxr9kIUjz7pQwbuq/Ef86cO
J8nt4PwwT4reEt4Y7A59chdcaclhree48gLpwE1siovP59Vy9pYa4KpGCW5ESoeoQ7MA+Wb9V+G8
Odz6/1o/ZsuvFdjUTIfhpWAY75U3WwTJrYwT1N4val943jz+I9+ZVVfGfUsAWJ8Fc42y5UMr5F2b
/0z+yvBrl/wqfngzLiUMj7gUI7OBiBAXJ3qQYKo8dA+AVU8gZqav3nlpYyijDKyei6ewRXa0twjV
W7PGtjl7rERwdwcnqljHXeBIYgSjStDLeIEFcAPShzCesmHi2/YJaFD5pEtjySUvQcr7D5ogSd1X
J7RakQoNU++IaAB1Wx8uOhfxqJFdG8MEDcrv7gHj9yGNdw4wlEMK4o7F6wX4+QzZTW09IpqWtkDU
uFnWHMocuvuHcQIWXjCBTndxD4/cLwXTEzTfxkqNdA8wHCepric2fyqbGtgu9mzfE8p65FR7gRoQ
+s8LqY/UFm5z//sFQBG5u7xESNuJ9TBF3INCmth4CkAk3JEuWrTEKPZeDXkSNfzTXvFGo9Q2tT1r
fyFItw9/06HYt6KUsKAaU4m8gaUrmCdeeIsl7Ha31HnH0+u69qNHt+AodNv1Qei5MV770vUiQFNh
jEAM8NvBNqH6qiucY2DH1UhVw72SHpr6IwcepMKhCRilOO4djRH1fVDqatY1dpaVIOvl4fOGCh8P
iMoT2yt7B8LUfo+jhkIchWmePuoTR6+9kJZTMMWxPTyoYHFF41z2ZitfkwJH3p2sZ1qi8J4dH9Ke
M2jv/RCsMHZ855QWevbxscvgV9w8SMqjt+9Mum3YnGV3+FgpzcsFuP9ALxDLkpBriYyMvKPU2nda
6fGJMH4Z//iPAmJUz9xCjnv4FHHockpjkmuZU4mcnsQnvxZ2Nb8UmKXbTqmKjSgiCDXyhjPGLca8
KqcMTcOtBeTHXHp6coyapbmjZqQTeVIhZU3KIHnoSuOAUPtS9/RjSzd17S3rMJYSGuf8JjnrUb+D
OiXyO7pxLjEg37YAZAY90MHxnYZGDLVgnOmstxI7PFyfp1mnyU/M3AJ1opI7DFe0pueH+8bkDwQ6
yYM9HqEH9GTX1sth7XIP2Ip+S9EyWQygDH5RrtTQyirp+PPRKh8e5q0u/uGYkPocKvq0BR6Qvq/d
HEcUuz43P0mywgar6h5+m3ovHlmzW0VMwGSTM0aU7CHsbzw2m/gWfdpAEr/i8j+/y+ja5ZZa6MYp
1Yb0eNhPiJPdNqmNozhLl/gOv0Kzl/NaOWaQsOeRivJX64CH6wjdlp0k8OIXzvVy3C2HCY8V0SAX
49aufgRX+f9BY/kjkcfBMbMRvwi2VjOfuqojkKGmIFVa9Thnk6Sbk6wvlS3SiDJP9554YRpxs80q
wf41vVShwqqKL5NYCBsNcFsvIi+tHEpYtEEe3UcGGtTLgpOSEpzftGPdARqOYGitjM7ZJCXnOB7/
U1Vs59Kfgs4i1WVtTKsoiydTopdP/ZIRpSMOvcjCE+HyKT78vXGCAFOvXLFAwXMvFfjpV3qJ6VBP
MbIA6V4VPTtkv/dCLOBEhn1DWyEBrYN1ADoRTKVf09W3dxVwpj0dZj6br4tytE7WopLE5WabTGc3
a6cJHQfQqvo6Pc5RS4mTKlB2NgmSoqCLOoER5MlbamAgj/ijtqLk7NXdJDtckSqVkSwXf3hRXYPF
txrrkScE+gDd9mgHFe3ZCzCMMUdV1IeSJHh297nFQ/cklfDumIvf1nCWa+6f1eCmuHpEAYQpoeg+
7lMp9730WEY6kj9bFTWESymsThiSLBjxUKwCwVEHYbv14BWlQO6hIF9jwzcvLGOiWyn/VutThzu+
TmVpSMit/YUX7niE8goTZpjPQYYE3tJ29KOhxJQQAUVZ0NW3XdVR8Hl4V5N9lnAmGcjpQMwMqQsc
YA+lPHX7VuBf/2dz9n49ZSeBu06lz3N/Lf0qxRgeY1wEUxDZIcPHu8oxZa71TJWfJbE8r6+LaJaa
+xki7SPDwyk79qzFMW9PLAAkxQmRGw/2rDoKIHipA+uOD5fuukjpVRbBBjggE7ro3RifrmzeoHhC
EwrMf6idE5WiYAiYD0QdmHWj17dt19M5l6knknj+RW+DG9doxdd9K0rBxc2kuZFpgOjOl8vN4VmR
jtvdtDuB4zhc5NhGmGBrFMZ1znMVTo0pZSpVpy6IU8qW8gnhPCfE7LzFxu2oDJWNA5Y6pkAHF7tr
ZfKKmRZJNQYK1lN24k0GkJ0480y7pEWIk54S3XG1RpQ0yty/9kpQV+4CMWJvOUFupghvolJ/vCna
HUz13mxg9Ddkoj+ELFw6ZGiykhRC4Y7THdUrZ38d73beNEHBG3l61NHicHB4kJH+HbFoXmBc6kO7
A/mmvV17NO2zUPMGVb358Cico7sMuvpgZy0/z+Am8MH4BwkINHjPzj9K7ggxbn/IbYW/AmjMuQyN
qxfdmq2Ohx366cmh0G5+wj2ZLaj79GmNy9FfEyndxzE2wLuvfDBeh4i8aR5ZvrTddyzNReSEA66v
ceeJBh9ZU/vYipWSdO+SZGHO2yXFwKBnX7g3YElsUdBSqI6JMYGer666Gl1EUYVezkvHp7gZmWQI
tLMs40QPPANs316Qk11CUwCQdpptx5oXLSUu6fkf4DL6Sw3gGhfGKNaw1Zq9C3ob/SlwnQYRlP/2
WtAMfwaepbTP13+TPuXZqt59p9boz9IWm6MSGo4u1Ke2P1rnPyE7RZbTPHxBQcEp9ciH01Q4N7Xs
qGvU8WIfChrOuMq3QlZFhXu0nfkowL0VxL6gwedAxwlOXd2c9JhimuCRHSUAS0m0FZ2OP6FTXiRm
ijFEhMkx+vry8uofT8ieE75R+7a1XE4ujnRdzdf/Ecq+A2HcE/fW/ER0clBoEvH50Rx9qVXeKZ0r
omfgn4BMMQFJi6cDcL4dcz+pWaEymNPyCB70w7gr5Lw4mQJp69IQfbJWc+0nQe2RKPoYLWu+ZhNB
eH4bWw5SEiAdhz0lycIcRAg8K5pZ6H4fp4Ye2BotaNUYr6/clY+xPVha9EDOdMa7ZvIjdrC4EHHx
Zd9E3jj9wFqSX7N28K73d4JRHeHU0XRcibO1sGIlPiqIZ0KSmrQCLLTY03I+m4e5eYHLEiM0Voxv
lOQZuXq5493oGs92AjabPas5j6xEhwJKkl83eGK6sUglFaJNpVvfzVg4AfLrzdaqetlsNBG928lP
6Vw5wiZ9hAfOHloVOE5Uo4sDn5kOiBBxmpKiyeCEcMANFfAGdqD6V/DS2/Q5EDFvhKGb0ZpArlak
YznMfUnRcz24iNag++RKZW/R4NvwYmnKUJdIPMMsKs9r3C7ScN1V2phd10Yge8LniSPxhbNQGk2W
2uXzzbHjRIY0ybLtRHpHsHVTfLtE1ShTZVRqjz4ZmaFIS1GsJ7VYDz67P4e/3Xun0pYfVGHkybtQ
MfH76ac6I4WHwZrrmStRPVHAhDCrgFXqEmD+M0xZih1SOaKIDnRjmBFRaCMWFS/K7K+fEDPzIFXQ
RbMztjIoETbBIi+rX9hTDwQAHf05LmNqHJQsLbLxklOdM+JsBwute1AWI5K+iqIjTonTHRjX19sk
ov0xJhs8gb2zqJpsWCDY7erV1wh4RTDVR3GM7tnp2e5I2mcjbobpx1nGgaZt38KC6WS4uYzNoniw
hWxGprESma9PLsAQLImra31V3RVo5CrA/u96ITcaPD5sTKbrGrjK+h/g44mLYbvtqsg7vfL9Dqt9
gTCV9fMupylNXh36+7hwg6cdE+5U98RIY5gprVnUhhBMAhL844zFbpAYjwwLkrW5y5DvwamVB3Ke
0DbWhYLX2A4Rq5n57od7oP3EG9xG5SSbuRqnJuCrpfHSjBElPbxLlxGah9PM9bcIXG0DJC5cVA14
FJjPnd+SIamgROsteEDPZQAUvScQZJ4g15MFqGV3Y57A0GX2kjWfb967p4j28KPFotI5a+uFuSKO
nnEWqXauSxM0TZPu/smDC/gyV4T7Zsdd72famUVQNyfeVEz6nCZt1PIfauCN9S7wAxc0+Aeq4xJ0
dKahwtatFuvfIdhg8xkhU1YR/fIHPiH4lVhKhfu8XNeCBU1RwnaCuGCgP8vCR9yJEDFaeR3awMPC
QuUnEWCUOokMTw0jsgYkX9ttP/Xj0Rp1LH1Ihn5zNcCv49sjgIaGOZBxeNkfg+4cxyr/gW0rHYQU
7UIi2g3iIdFjDCuKsd2bOmkS7wzFuWH23+Dzi0R/msCOc2OqzrRCypPqBONeVbvOzzRalswRJox+
Kx/owJsVaJqdSCrDn3LHok/38UL9ge3igoEySXGzeplFs9rKnk4xtkL6WVOXWpkpBZGd11t7fw5d
fCjnYoQxyyuniyTtfdk/X38vHtBuiA5T7ammUddwLRaqjnuQ+DvmVlDYj+NZlZXZ7CgJh5zJWP2v
oDrU9NhxlEijBkeX6R+Yc+LN07xrwg2E5bPgdu+EX1rFUOI2lq/NkcTRSbVbcugbatFUxmBXdMc+
Mmbr8GOX4SYgSFTCrx3GKVU3bzjw55hBiwkfRZVZ3fnom6ZWTiVv2NwhrTzDdjH0Ssflh63O2iBK
UQAR3TnhYqFMH18pC9pHeEjFS926FUHkewV0FdKpLl1rSp82dQKZKH6iKwsNbJBWlX0UyVD/mE58
kQuEbZEbcgMesbrTgY26MWwYJ1Ga02piQy9dmhSr4hjxQwQpXhEgdDRsIspygBJOu9JA+K3Z8jy8
kqzMUlq8X8RyzNkH8B1NaEoY7b4eHtKNWGugpHQiT8GzmSLp6sikQMeblhxuSAEqLpY8C2nR83t1
xrQZCSuz84GqO0qmBGIMv9T9/A99eJmiIKgqzQNvy6Oyuft3kB5fPWUOHo8mi8Mx6cIH+6v6Wemp
2JBnjPV61jL5LqdxiNc8fctOl7UTiCZ8l5eKHWL7oe4M4ax7yI3cvg0F5HZehBDGoWudqi1sIrQ+
lwq48ssGg9iB59rUAMeNTM9own3ot+qCvsUlL3wVUdf/N43Fm+wj/6oOm7r559sdZY34tdCAaPi9
dMgJNJJCqNjy7geT7R2DAyaAGQPGcc0kEUQSNLbYPSrSfVC0fQHLERJm7WWPYeI80ah1ZDiinVY5
tCNSmRrvlhVTdKXEpZAqHYi02QaiyCHIqmVQLT5UHyhZP4P2JqUnlUwrpQ1scONky7WIGKVRS+LL
isZ8w5KgprKmTGX6+oFazZTGBQVzrCjvExRxNdHe1nM5n1Ir7BO9G4ofHu5e8AoS0/vWzDbbRfMp
UxDa43n2hV7TbX5+KLSIhp2lroEG+3Iv5R3KgYjWAHc8zVXmv3hlDAkI/v7S8Km2BxwdGH1wGNxf
FL8S3+AMn9RszRD1XiItVMCMCl8hNgxaYDS72SadwSLs+02sJQX9hjv7UqhrFwb3xlXIOu9u1R4S
8GBFjUd0ojufsCrVXcvEjsfUWvMVG2+M5Ke/e2FgUy/AZLKV8x14zNqH3rBadYbuvLfY+9uzQbci
oA2ZQ3O2nch/VW4yJOU8lLH4+Y38T5JwQ0AUH2OGIlf92jwN3ro4BbmVg2UfF9adFvwRdFYXks5S
ac9EP5Z/XyGKrzDsZBF0LHIC6VGeBc5700SFKmju9YOs8NCfLoS+qrt5n1gpQbNQRdICik0bKwHt
+9g49GOWMfUOmpGWBCfeVdJqDm1v5qRRggcu+CZYP8z0C0O6ZRO4ObFfcn2+vby3vusOY1W3wd6t
rdW/eEzkCNQvdVzK27MBvRJATcOQtbhjUp+MxqT8RDaBe8twywsiKzcaQ7PW6Drt5eV034k/tOH0
Ixxm4a3d3KVjRkkpzBSdb2VKkj30FxzTZQymKPr+rB4SUKAqWMIaWVyfswXDDpB9MVennGcKSWa3
NXg3NZt0V6mUA/v3XoXr7TRbmybHxRN76sCqK4onz+OEBVysi4UGWNqb68ltCC/DFT+xyeveefJ2
65algXK2XhBhR31eKhLBVJ7YDb92Y5kZ3zhDhC6DHB4Zc3jJn4D1wVnc2gPdJT1DiY5EVt5R7sjS
f6MZ+VVXrIwowgJzm73ay60+1sqgpfjVn91erlwBmhBuvHv1bMC0wBrBckGgEp5gbYJWUPjRqqB4
4qxhtqok+REgTGiLuFRls1QEKsb7C7JAylIwoYu0J1ZxTgQ29auJfHqnl+HrECM6BMUWBA7jscxM
edYk8LBbKS1VJKnLSNQ+gBRtVGK3fDVsaNjZnPVb9+u8WNZMGGFm0/fImEekFERlZ3VZLFnExbWn
/o8FGwDGXHRMfP65IcYZgawHWjlKtJ5Y/v++3MkyiiA2BYR+5bL3dL0oxHMueC2jc6tHXMQpf6Rl
2lznxWtPw24TDXs130+TsYsYB/FkhinO94OH/nk7vrnBNyhjKb9Duan0U0X0Vvj+pvj7z5qL3ucL
8Y/KqE9Sdzym+MjuX0memwMN2iu2khWuXsvDsniU8/qzgHdIUgY7JLd0i84YiY38DuCnj2/Fknok
FWN8OvnHQMEYNvSqicyi69pcc4LVO5YtVXrpsqcq6jEm3WtV5oJgdVhkEATnQjucDzn8ybD6O4A5
Q2dwemCaESiaYxfH95XGmlVR/i1BXSvkMlfe2CISOoyINGcZlmxOej0WrQt0QrpGX6/76aqx2wbO
rWIWmdPG9XjdelPr7IZF1rugT3wa/KTJE/2SwFuzhRA7E77W1LqGb83XzQcoD+14eMScVi/GvoBY
v67DAYCa3KC/HSgm+8CEFCETJTtuRWTbcrhkpgulqSMBLUUhXzSREIn9d+GYcWQkM45tX2Nmq4Qn
ktD27FB/3L/ndlqtIWQ7eN15IOauN4KRYXY/khoD+QDpWOlph0BCxQ/WDM/zHO7N1IBcL5FTz1/8
bmykUnylZDoWH5VDbdtZYaWGfLaIpTrHit+F2EXCEzTinKQCDU3k9cCisGSPC6YwoM+1Q4jBTnaE
6ZUhD0ZgX0z/uda6yRXNdUGYg7dU2ZHf4v0OXlULzK474dPeGURxaiOiODwALR7HyzHmad+jBg2B
MRsFTJOCE6qx5B6QeigRITFQJVoWf2CVoO5OjR3nTjjxGUAWGsXWizcXI61iyP6+10L/DrtvXvMm
DbwoEMo5298bSti7fNzBP6GV0fPGPHy3m8XbxGJv2acrJ8IGBCq+g/Woq2aBKeDO8qZGr2+aiOQj
p/y9cSm+1a1y0TcGIDNs7yQKDycO3QOMe3tEgvijB3y0if4+/Q5ba2o5nR1HKQUCsrG9jjp620ed
/WR6mOa04HVvN+m7Cu8yrU/udnl0PhS/t3x2JmpWawIVmC1hqqVAtOSUPTCwVHgxfFveoZLksVEV
6uA7sZTfznIxDF9Tou3pnsuJr7kYTZc4YuI2nnvgv/jOorCiS69WmugSW5dGcfCXaN4XcIiCm/Hs
6M3HxlcKrHSs7gtjF5xRO1oAq+zifUN2FD+qVMtQI9q4S7d+G+NRkrNOfPVQvEiSO4/Wt7oHwZFB
ypZ+nyeMMywilKIXhSSv+8eVU+TJT5ZFj1IHrYR3DDWetpcoH+Q9nhlGpCeOCPzVr7hgJ0DlmWoR
WI/BAXyLmsuKpqXjz19UmfQ0pyuN6E95w0f5caEri3Wr6V01bGxeggl+PxqIzL1dlRmHIbEz+2bb
jt+e1GS2+iFcObG9WE8sEI+O8u8w1ab5W+68iNj2nnSGGN+/scljK3He25fcPToDc4O4PW5XlSO6
tYMZuK3R9wsqKa1pWH/QiAfpo8Iso1WxDim2jgRdTAVmJfAaQ0Lm9OqQCeYhS6nmcZULCDVAwx+L
t3CDRNA76m031CJhVsXqHtitj8e9M0DiJHwZ5r1OvP/HFBtPriBbzbnjviP2X/gBA4j+Mx08YrcM
yfrhK3pRI6VHyyylNQ4TZpms/C4JbOJBOOfSMI1XlRQCtgCEfxxr1fJ+a/T2fw+pCL7ZvIIbJbjk
QA259jF0tPaDiP7Pqg5zu0z3mvc+z6fSvTerrEfm4djCrMdZ8K6lnSOs6l0gJSEZERpbtF545naq
BxjISAAGhRzonTOUo1NYw74nifea6vdiNIdExzbn/9W/IR6vhVRuc2ExrsRAwvamPZhsXE5Sn1OI
0eTQBGYH2O0pRX+XnfhkzQm8d5oHyTbnfut4zywhko7+7cneVUddaMPlf3X0/p7LTtNziuit9IFR
mvoMYJ2kM89vBX3B1oCpo3pOkQx/D8p5gOUDupgKjW3uhJ8UvTiQI6GVdqRIoWdGc2fGe3B2YaqL
442446++OV69TwjWr0VWsOX4jdrbcN847K/EFlgXeafv/0KeGituw72XgBdUXBh4Vo/lm58i8XYA
MzoRIh3YypOrUPLi9WQZka/C7IMsh8V4i6NoRQDPzvUbp2iHBKGoAVkzc82qxjsWP5l9Xe9rnh23
uyFOZoAR091X4mpoNZLqi8GquKD0Jr812OBJ1kUnqorCiQXcKGZY6IFAorRf7CxSThXqOJUPArG2
U385Yvk0KY8AEL63ENmVlVp81XlSXjpKI9s+ArrSdXRGKIvidW/bYR5ts9CRIT5/BciWYK4Cewkj
Sun+MXHBXY6c+FpZtXGeBVshuehOoBDybggtv2WTvzR9/cDyik5a8tFBXZZtAlLAtXij7rv22fes
xanK5R5Z8D7QBPix2yF2ym7leG2Ge9pla34RiNbMLtraRyxW4A5kc62FHGIRwEmnxuixbkp22lle
6uO6UxkeYPMGiDCUDE1UjQwlmDwwZ0fsYsf0lJyya1TYgvNFdPoEIkNy/jAwq94pi5iL83C764iH
dza7Ql/Wu2npcziCde8sJhq67yj//vCk41bUzllwxyc7eqPqG//fnRKY5LlH+GJ2Pzd7tmouolMQ
uh4LDxPPJPZtaGijy541fFAnzyFFhclK7CtNw3RZK0Q2uvNPlc0guYR47Oc9jOBtyYOuZALGYtCC
M8F3eAKfW59qZbsA+HM6wZTfaXk5f7Y5KzIr0N5gatvLOPnfEMUKEM4WwXRswEv+mXet6yF2E85k
/qzNsslmL2iaD+fim2r4CEJ/lz0HPHDgUrcJnDDVdoFqHJGt+TxbBuRj+vKjRZ8S+/aUfFyMyHfi
Bw2gx2TsdpiRaK/ZKKpfSOfhsPQKS8c0Rh0E089W4daNt0hgSm3OE2ytcfWk8SiFCp7QUTM+BiNh
2eadYARu0srgBJwPPaX0fBEU6Q42pYqsQH6KD73ldMcwPplOa51Uo5TAyIED+j6U/UoA1LD/ev7w
NdzDeRqvalo76RhoS9jwK4Ydun/01kaaihB+R2o++GdWzCdTW7a8BEHdVJWaWGct7Hi2LlPLDmiA
U/FNcO0CZsApydbNZmfz9mDIlYtfqKjPx+2SIcJmC0NBax0TAH26F2TI0IV35N1GARiJWlwmSg/m
UZVW7F7EaexAx7ysrEwImMwglxXAwt7wds6eL6dXNQcP8YA588vwe59FWVcVhGJ6ErWk6PY8duBY
grD3I4OTGL0uofSdHy/WOXCNm5hHYv0cgLs9bubhKCmWraU/yMcENeGPf4H8zWVqEgpxjT8zzuOl
liFyXO83vTZnEIO8lG8FbmiYufBBl0uc8bTMji5gTz+cOcD4gaMCcvDl9lU6GGPpI6G1ztlYQlKS
mwdGRBXuz1RBf+j75JELQwkfqukZMaQ4V4ouanj/3Ohp57JHC80ce5ntEVZTw6p+RuTqZTm1JnMV
gJlVoUrFOarAKiDp1VbuccttXyTXDXkbnPDSE7CGImAwnD5S3Vv13BjSxjinKsCMPiRanUC2RoQE
XjZhFW1Ft3RQsxA/FVB+Zs+k25D4ZoKAIxbwd2y0V0TasoydStBh8T7cwQEuojqiQpQqvv9k784X
GUCuWwzfP1HUvYDlfCXB1PTNvDlKLiJC1iQQFjfC2KadAjxJ8HBjSA3sph6f++CNDxGbTQm9T8Rw
1n3mWdltIEO1ZUBHUqIQOGo8c4Jxi9hrnYpp8yVjBkYjGe0ljYvBX+a5qQqH7l9ysYb5a6/yJfIi
JzTeHyTHAlT553v6u/Y5I/qznZGwQOlYYF5EkVxVTsjg4wSVLFcIXocizI1nr6sZ11PvcIVLJKSA
H3RA4QzqcoPoZJ7+a5JEdXlhRH/RbV6tmc+5mMnmE0ZjYnW9/tqg7FPl0MzZ/k+Afm7ov/HMPvIx
VBCF6mpPxCr9xJICGnEQl+PTN1u0c6vIqUxFHqwR50IM1AfPKtC1Ou0Jk7x1X/3QmsK/8RwgKr6L
Wy64vyQVATaPQ27IZMv+N6vkh/GOBHYCmtfYh9mZAMNQ6UaLVMG8j1gf/ekR3t6MX1Rr3Px313ni
aWhuioNZvPSCeNH1PrT9fMH9XKpSxgKivR1AwDOWDKyIuhvmVz5lxhKcLvU3ALGU//6zregK2n2A
rAFDDtxxctvt7sN9XnId2HGRkaVvWGMOYIVyKncyTrzz/gish6Hb1xlK/iRHLAq12sqCUZZm5W+E
FA1yFIFg1CaWktW16LYczGH9XT4Rv7v1An9tyAqDJL+HdTVvbbIcGYjuukjZiAgoD+Mpap6qf3NN
G4VzlxuQdEG3yPhiKXekLHKdGfmSm3BVpiEjFBWzCJgmlnlMzNy/yF+KUK3J+pgs0pc3/D8hLr67
ek1Kfi3I6+z7zxHJI38kz2w7OIVH67but8I/Qv2kXIRy8IxwpzYqCEwmtE+07fQOK4dWmxcbtqcb
iea0r2TAu4hDdO6a2X6IGbLy4B4hM2f66NitfXqx1wmPTe1fpa05K/aPXfRSULRAY6m13gLk3o/1
TWw7YmT7Ok0Sk0lOJqqudClBzC9mhSDLkqJRMOgKUFATG11Dn1k/AwtR4l3+B2HZBb2t1vCGDVU5
T+OKRVY9U80dstUuadmibROcJ20GEJ0Ts0r420HDiLwpWD0C0V9J1EIi9emo3WK98cXonYA9bAly
oK6Z8xWirzTDt4S+EFPrNdHbpqRDbuHkv1V/HxjLR8H1Q5EvtTWdvZGhg8MB4Fvcip6tQCOtUrBz
4+OBbpO6O6wzgrTaDoWpPv0+eoDB4EQh6Nz5L7Nwh0lgIJgs6MBSJjbJU1Un3Z5drpjSpQP3fMaa
5Nz1OhaNs3BuecTcQ5Uvwn2T/X/RQXTHG9e4uZqBdDAVHw7HhfbNTiY8myS7CSxFSRtnY0yqwzkU
Qc9zkADr60cvJefF/BnxeZSvEC0vg/OB4pdbyyZ94/Thsn08wVeerR7tXiyhTXjcU8a8R/ilYn2k
OgmiZzFrlWf7VSkR6RJER+kiajytNi+l0d2pY0DHc69UV7DgRGyhXyo/iBSgQ8bnM4T9eq1w8H0M
PLeIMoL244bjn/61q9/L4bHmoijG1t0ADLcNDSE7tBSW+uvHmuGX9wvuoTmYRTpWvOVHxmK1IzAI
rHr4IfWOG9akFajZKoN4gZXtyytCaHrpI0rmjJ2nIG2Pdv/OCW+SAjQV0CF4ttyIE1k8lYEMwGLk
k/EX7da7KRulx14UegP97zsIWLy/P6ywEKWajaNu/C9j1DpoRYyRDKAkfTUs8ElKAWS6uq/i3vaU
PHXnZzHg8W3qH9nuC5boXAd3UPtdhz8wVVd2VT5W+/gGt3j7SNCI+gW5IethaK4y/8oIvbHrQ9LH
Iuy2YoDNyKJv5+jOEXPRtjP7tdgkTP93EwtZnjI86rcKCbMWBoXbHOYOgnQJZhon3fMLXGKE6UPU
6Rum+JXLlgtQOTAFluYWOazn2PHudk5XXpTjy+phkIi0mLT+1XaVb2C2x/ZW3VZzv5O5tm7SaZar
d/0VwHQo/JN76lIDKrPGEIpXxZV2VEt9qVJynC9mghxv8YOuj4X/HR6dZhXDdfjxBtQqj7I0ZXIB
txlr4y3QJId4tJzkkPiM0zVrqP6SHLG0hIslUYYSFIULGxuW5O7GWvQtQXTCkIK/dv0ggxwWyK9h
lNlsS/aNm7xAerBmhTWpVOWDyRRyAtglHVauoI1Be0PpDB2cmzm/rS57o99nDF/ruOQhXsDH2nNK
KBUuIRbESwWeAwQhcrR3LJvkTbe+FjIz6Jf9snxWW/8CSN8r9vra3VmshzKEgXSTwR78lqVvTDZe
WiPTVLDQDBywFxATCFwPgVvOJCS+OzhMRContcWPxMGREIfTbru1u//luY379iM4eDcn/SluKU9c
jB71uEEjdo0gBVMgWOXWXV3w5hwloV+7LQ8IMdD2qTxZ2flqdw0ALMMNKFfXKQip7jOwd4bhkgDT
KSFdmEaNzuLBP2bJne0BmCfw86P48FK072JlsBQR0aJjD2xmXk67neX1+OgGMWWSjElySjCj7rqp
1RoazwMIQGjztXyUXet0+MWhgoNgOYnaGkOZOYib4odjq1lGbWr6JvufxlSWnqzaYOaRR9NxMKrw
WU+LXJyw5sCThcji6glsunb8OSMnWdnDomz6jxcbcH1ZJLS59H+vQNz1teS+M5KnUjwsslG64rBi
7ebWwMaOJaYVulTo5nGFAfZUEaBwDU12aQ1Iu2QizcDoGWHtNoenyJPuHxWoKRfx6Uc5DpDTy7Vq
XwrppjlEG+ALszyhuIPAeasXZBjTZ16gtNF4IXvN7sK6pqRTEz0cZSoyT+zuVutN
`protect end_protected
| bsd-2-clause | 9bd56fee39aac1d4be23cf047f113f56 | 0.941416 | 1.849102 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/if_statement/rule_027_test_input.vhd | 1 | 566 |
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
ELSE
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
ELSE
z <= 'Z';
end if;
end if;
end process;
end architecture RTL;
| gpl-3.0 | 62385e4fec3cd4ce6aaa215f1ec4a670 | 0.379859 | 3.19774 | false | false | false | false |
Yarr/Yarr-fw | rtl/spartan6/rx-core/decode_8b10b/decode_8b10b_lut_base.vhd | 2 | 31,488 | ---------------------------------------------------------------------------
--
-- Module : decode_8b10b_lut_base.vhd
--
-- Version : 1.1
--
-- Last Update : 2008-10-31
--
-- Project : 8b/10b Decoder Reference Design
--
-- Description : LUT-based Single-port Base Decoder for decoding 8b/10b
-- encoded symbols
--
-- Company : Xilinx, Inc.
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
--
-- History
--
-- Date Version Description
--
-- 10/31/2008 1.1 Initial release
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
library work;
USE work.decode_8b10b_pkg.ALL;
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
ENTITY decode_8b10b_lut_base IS
GENERIC (
C_HAS_CODE_ERR : INTEGER := 0;
C_HAS_DISP_ERR : INTEGER := 0;
C_HAS_DISP_IN : INTEGER := 0;
C_HAS_ND : INTEGER := 0;
C_HAS_SYM_DISP : INTEGER := 0;
C_HAS_RUN_DISP : INTEGER := 0;
C_SINIT_DOUT : STRING := "00000000";
C_SINIT_KOUT : INTEGER := 0;
C_SINIT_RUN_DISP : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC := '0';
DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;
KOUT : OUT STD_LOGIC ;
CE : IN STD_LOGIC := '0';
DISP_IN : IN STD_LOGIC := '0';
SINIT : IN STD_LOGIC := '0';
CODE_ERR : OUT STD_LOGIC := '0';
DISP_ERR : OUT STD_LOGIC := '0';
ND : OUT STD_LOGIC := '0';
RUN_DISP : OUT STD_LOGIC ;
SYM_DISP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END decode_8b10b_lut_base;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
ARCHITECTURE xilinx OF decode_8b10b_lut_base IS
-----------------------------------------------------------------------------
-- Type Declarations
-----------------------------------------------------------------------------
TYPE disparity IS (neg, pos, zero, invalid, specneg, specpos) ;
-----------------------------------------------------------------------------
-- Constant Declarations
-----------------------------------------------------------------------------
-- set the default decoder output for invalid codes
CONSTANT DEFAULTB5 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "11111" ;
CONSTANT DEFAULTB3 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "111" ;
-----------------------------------------------------------------------------
-- Signal Declarations
-----------------------------------------------------------------------------
SIGNAL dout_i : STD_LOGIC_VECTOR(7 DOWNTO 0) :=
str_to_slv(C_SINIT_DOUT,8);
SIGNAL kout_i : STD_LOGIC :=
bint_2_sl(C_SINIT_KOUT);
SIGNAL run_disp_i : STD_LOGIC :=
bint_2_sl(C_SINIT_RUN_DISP);
SIGNAL sym_disp_i : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
conv_std_logic_vector(C_SINIT_RUN_DISP,2);
SIGNAL code_err_i : STD_LOGIC := '0';
SIGNAL symrd : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL b6_disp : disparity := zero;
SIGNAL b4_disp : disparity := zero;
SIGNAL b5 : STD_LOGIC_VECTOR(4 DOWNTO 0) := DEFAULTB5;
SIGNAL b3 : STD_LOGIC_VECTOR(7 DOWNTO 5) := DEFAULTB3;
SIGNAL k : STD_LOGIC := '0';
SIGNAL k28 : STD_LOGIC := '0';
ALIAS b6 : STD_LOGIC_VECTOR(5 DOWNTO 0) IS DIN(5 DOWNTO 0) ; --iedcba
ALIAS b4 : STD_LOGIC_VECTOR(3 DOWNTO 0) IS DIN(9 DOWNTO 6) ; --jhgf
ALIAS a : STD_LOGIC IS DIN(0) ;
ALIAS b : STD_LOGIC IS DIN(1) ;
ALIAS c : STD_LOGIC IS DIN(2) ;
ALIAS d : STD_LOGIC IS DIN(3) ;
ALIAS e : STD_LOGIC IS DIN(4) ;
ALIAS i : STD_LOGIC IS DIN(5) ;
ALIAS f : STD_LOGIC IS DIN(6) ;
ALIAS g : STD_LOGIC IS DIN(7) ;
ALIAS h : STD_LOGIC IS DIN(8) ;
ALIAS j : STD_LOGIC IS DIN(9) ;
--Signals for calculating code_error
SIGNAL p04 : STD_LOGIC := '0';
SIGNAL p13 : STD_LOGIC := '0';
SIGNAL p22 : STD_LOGIC := '0';
SIGNAL p31 : STD_LOGIC := '0';
SIGNAL p40 : STD_LOGIC := '0';
SIGNAL fghj : STD_LOGIC := '0';
SIGNAL eifgh : STD_LOGIC := '0';
SIGNAL sK28 : STD_LOGIC := '0';
SIGNAL e_i : STD_LOGIC := '0';
SIGNAL ighj : STD_LOGIC := '0';
SIGNAL i_ghj : STD_LOGIC := '0';
SIGNAL kx7 : STD_LOGIC := '0';
SIGNAL invr6 : STD_LOGIC := '0';
SIGNAL pdbr6 : STD_LOGIC := '0';
SIGNAL ndbr6 : STD_LOGIC := '0';
SIGNAL pdur6 : STD_LOGIC := '0';
SIGNAL pdbr4 : STD_LOGIC := '0';
SIGNAL ndrr4 : STD_LOGIC := '0';
SIGNAL ndur6 : STD_LOGIC := '0';
SIGNAL ndbr4 : STD_LOGIC := '0';
SIGNAL pdrr4 : STD_LOGIC := '0';
SIGNAL fgh : STD_LOGIC := '0';
SIGNAL invby_a : STD_LOGIC := '0';
SIGNAL invby_b : STD_LOGIC := '0';
SIGNAL invby_c : STD_LOGIC := '0';
SIGNAL invby_d : STD_LOGIC := '0';
SIGNAL invby_e : STD_LOGIC := '0';
SIGNAL invby_f : STD_LOGIC := '0';
SIGNAL invby_g : STD_LOGIC := '0';
SIGNAL invby_h : STD_LOGIC := '0';
-------------------------------------------------------------------------------
-- Begin Architecture
-------------------------------------------------------------------------------
BEGIN
-----------------------------------------------------------------------------
-- Conditionally tie optional ports to internal signals
-----------------------------------------------------------------------------
----New Data-----------------------------------------------------------------
gnd : IF (C_HAS_ND = 1) GENERATE
----Update the New Data output-------------------------------
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF ((CE = '1') AND (SINIT = '1')) THEN
ND <= '0' AFTER TFF;
ELSE
ND <= CE AFTER TFF;
END IF ;
END IF ;
END PROCESS ;
END GENERATE gnd ;
----Code Error---------------------------------------------------------------
gcerr : IF (C_HAS_CODE_ERR = 1) GENERATE
----Update CODE_ERR output-------------------
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
CODE_ERR <= '0' AFTER TFF;
ELSE
CODE_ERR <= code_err_i AFTER TFF;
END IF;
END IF ;
END IF ;
END PROCESS ;
END GENERATE gcerr ;
-- The following code uses notation and logic from the 8b/10b specification
-------------------------------------------------------------------------------
-- Set the value of k28 signal
-------------------------------------------------------------------------------
k28 <= NOT((c OR d OR e OR i) OR NOT(h XOR j)) ;
-------------------------------------------------------------------------------
-- Do the 6B/5B conversion
-------------------------------------------------------------------------------
PROCESS (b6)
BEGIN
CASE b6 IS
WHEN "000110" => b5 <= "00000" ; --D.0
WHEN "111001" => b5 <= "00000" ; --D.0
WHEN "010001" => b5 <= "00001" ; --D.1
WHEN "101110" => b5 <= "00001" ; --D.1
WHEN "010010" => b5 <= "00010" ; --D.2
WHEN "101101" => b5 <= "00010" ; --D.2
WHEN "100011" => b5 <= "00011" ; --D.3
WHEN "010100" => b5 <= "00100" ; --D.4
WHEN "101011" => b5 <= "00100" ; --D.4
WHEN "100101" => b5 <= "00101" ; --D.5
WHEN "100110" => b5 <= "00110" ; --D.6
WHEN "000111" => b5 <= "00111" ; --D.7
WHEN "111000" => b5 <= "00111" ; --D.7
WHEN "011000" => b5 <= "01000" ; --D.8
WHEN "100111" => b5 <= "01000" ; --D.8
WHEN "101001" => b5 <= "01001" ; --D.9
WHEN "101010" => b5 <= "01010" ; --D.10
WHEN "001011" => b5 <= "01011" ; --D.11
WHEN "101100" => b5 <= "01100" ; --D.12
WHEN "001101" => b5 <= "01101" ; --D.13
WHEN "001110" => b5 <= "01110" ; --D.14
WHEN "000101" => b5 <= "01111" ; --D.15
WHEN "111010" => b5 <= "01111" ; --D.15
WHEN "110110" => b5 <= "10000" ; --D.16
WHEN "001001" => b5 <= "10000" ; --D.16
WHEN "110001" => b5 <= "10001" ; --D.17
WHEN "110010" => b5 <= "10010" ; --D.18
WHEN "010011" => b5 <= "10011" ; --D.19
WHEN "110100" => b5 <= "10100" ; --D.20
WHEN "010101" => b5 <= "10101" ; --D.21
WHEN "010110" => b5 <= "10110" ; --D.22
WHEN "010111" => b5 <= "10111" ; --D/K.23
WHEN "101000" => b5 <= "10111" ; --D/K.23
WHEN "001100" => b5 <= "11000" ; --D.24
WHEN "110011" => b5 <= "11000" ; --D.24
WHEN "011001" => b5 <= "11001" ; --D.25
WHEN "011010" => b5 <= "11010" ; --D.26
WHEN "011011" => b5 <= "11011" ; --D/K.27
WHEN "100100" => b5 <= "11011" ; --D/K.27
WHEN "011100" => b5 <= "11100" ; --D.28
WHEN "111100" => b5 <= "11100" ; --K.28
WHEN "000011" => b5 <= "11100" ; --K.28
WHEN "011101" => b5 <= "11101" ; --D/K.29
WHEN "100010" => b5 <= "11101" ; --D/K.29
WHEN "011110" => b5 <= "11110" ; --D.30
WHEN "100001" => b5 <= "11110" ; --D.30
WHEN "110101" => b5 <= "11111" ; --D.31
WHEN "001010" => b5 <= "11111" ; --D.31
WHEN OTHERS => b5 <= DEFAULTB5 ; --CODE VIOLATION!
END CASE ;
END PROCESS ;
-------------------------------------------------------------------------------
-- Disparity for the 6B block
-------------------------------------------------------------------------------
PROCESS (b6)
BEGIN
CASE b6 IS
WHEN "000000" => b6_disp <= neg ; --invalid ;
WHEN "000001" => b6_disp <= neg ; --invalid ;
WHEN "000010" => b6_disp <= neg ; --invalid ;
WHEN "000011" => b6_disp <= neg ; --K.28
WHEN "000100" => b6_disp <= neg ; --invalid ;
WHEN "000101" => b6_disp <= neg ; --D.15
WHEN "000110" => b6_disp <= neg ; --D.0
WHEN "000111" => b6_disp <= specneg; --D.7
WHEN "001000" => b6_disp <= neg ; --invalid ;
WHEN "001001" => b6_disp <= neg ; --D.16
WHEN "001010" => b6_disp <= neg ; --D.31
WHEN "001011" => b6_disp <= zero ; --D.11
WHEN "001100" => b6_disp <= neg ; --D.24
WHEN "001101" => b6_disp <= zero ; --D.13
WHEN "001110" => b6_disp <= zero ; --D.14
WHEN "001111" => b6_disp <= pos ; --invalid ;
WHEN "010000" => b6_disp <= neg ; --invalid ;
WHEN "010001" => b6_disp <= neg ; --D.1
WHEN "010010" => b6_disp <= neg ; --D.2
WHEN "010011" => b6_disp <= zero ; --D.19
WHEN "010100" => b6_disp <= neg ; --D.4
WHEN "010101" => b6_disp <= zero ; --D.21
WHEN "010110" => b6_disp <= zero ; --D.22
WHEN "010111" => b6_disp <= pos ; --D.23
WHEN "011000" => b6_disp <= neg ; --D.8
WHEN "011001" => b6_disp <= zero ; --D.25
WHEN "011010" => b6_disp <= zero ; --D.26
WHEN "011011" => b6_disp <= pos ; --D.27
WHEN "011100" => b6_disp <= zero ; --D.28
WHEN "011101" => b6_disp <= pos ; --D.29
WHEN "011110" => b6_disp <= pos ; --D.30
WHEN "011111" => b6_disp <= pos ; --invalid ;
WHEN "100000" => b6_disp <= neg ; --invalid ;
WHEN "100001" => b6_disp <= neg ; --D.30 ;
WHEN "100010" => b6_disp <= neg ; --D.29 ;
WHEN "100011" => b6_disp <= zero ; --D.3
WHEN "100100" => b6_disp <= neg ; --D.27
WHEN "100101" => b6_disp <= zero ; --D.5
WHEN "100110" => b6_disp <= zero ; --D.6
WHEN "100111" => b6_disp <= pos ; --D.8
WHEN "101000" => b6_disp <= neg ; --D.23
WHEN "101001" => b6_disp <= zero ; --D.9
WHEN "101010" => b6_disp <= zero ; --D.10
WHEN "101011" => b6_disp <= pos ; --D.4
WHEN "101100" => b6_disp <= zero ; --D.12
WHEN "101101" => b6_disp <= pos ; --D.2
WHEN "101110" => b6_disp <= pos ; --D.1
WHEN "101111" => b6_disp <= pos ; --invalid ;
WHEN "110000" => b6_disp <= neg ; --invalid ;
WHEN "110001" => b6_disp <= zero ; --D.17
WHEN "110010" => b6_disp <= zero ; --D.18
WHEN "110011" => b6_disp <= pos ; --D.24
WHEN "110100" => b6_disp <= zero ; --D.20
WHEN "110101" => b6_disp <= pos ; --D.31
WHEN "110110" => b6_disp <= pos ; --D.16
WHEN "110111" => b6_disp <= pos ; --invalid ;
WHEN "111000" => b6_disp <= specpos; --D.7
WHEN "111001" => b6_disp <= pos ; --D.0
WHEN "111010" => b6_disp <= pos ; --D.15
WHEN "111011" => b6_disp <= pos ; --invalid ;
WHEN "111100" => b6_disp <= pos ; --K.28
WHEN "111101" => b6_disp <= pos ; --invalid ;
WHEN "111110" => b6_disp <= pos ; --invalid ;
WHEN "111111" => b6_disp <= pos ; --invalid ;
WHEN OTHERS => b6_disp <= zero ;
END CASE ;
END PROCESS ;
-------------------------------------------------------------------------------
-- Do the 3B/4B conversion
-------------------------------------------------------------------------------
PROCESS (b4, k28)
BEGIN
CASE b4 IS
WHEN "0010" => b3 <= "000" ; --D/K.x.0
WHEN "1101" => b3 <= "000" ; --D/K.x.0
WHEN "1001" =>
IF (k28 = '0')
THEN b3 <= "001" ; --D/K.x.1
ELSE b3 <= "110" ; --K28.6
END IF ;
WHEN "0110" =>
IF (k28 = '1')
THEN b3 <= "001" ; --K.28.1
ELSE b3 <= "110" ; --D/K.x.6
END IF ;
WHEN "1010" =>
IF (k28 = '0')
THEN b3 <= "010" ; --D/K.x.2
ELSE b3 <= "101" ; --K28.5
END IF ;
WHEN "0101" =>
IF (k28 = '1')
THEN b3 <= "010" ; --K28.2
ELSE b3 <= "101" ; --D/K.x.5
END IF ;
WHEN "0011" => b3 <= "011" ; --D/K.x.3
WHEN "1100" => b3 <= "011" ; --D/K.x.3
WHEN "0100" => b3 <= "100" ; --D/K.x.4
WHEN "1011" => b3 <= "100" ; --D/K.x.4
WHEN "0111" => b3 <= "111" ; --D.x.7
WHEN "1000" => b3 <= "111" ; --D.x.7
WHEN "1110" => b3 <= "111" ; --D/K.x.7
WHEN "0001" => b3 <= "111" ; --D/K.x.7
WHEN OTHERS => b3 <= DEFAULTB3 ; --CODE VIOLATION!
END CASE ;
END PROCESS ;
-------------------------------------------------------------------------------
-- Disparity for the 4B block
-------------------------------------------------------------------------------
PROCESS (b4)
BEGIN
CASE b4 IS
WHEN "0000" => b4_disp <= neg ;
WHEN "0001" => b4_disp <= neg ;
WHEN "0010" => b4_disp <= neg ;
WHEN "0011" => b4_disp <= specneg;
WHEN "0100" => b4_disp <= neg ;
WHEN "0101" => b4_disp <= zero ;
WHEN "0110" => b4_disp <= zero ;
WHEN "0111" => b4_disp <= pos ;
WHEN "1000" => b4_disp <= neg ;
WHEN "1001" => b4_disp <= zero ;
WHEN "1010" => b4_disp <= zero ;
WHEN "1011" => b4_disp <= pos ;
WHEN "1100" => b4_disp <= specpos;
WHEN "1101" => b4_disp <= pos ;
WHEN "1110" => b4_disp <= pos ;
WHEN "1111" => b4_disp <= pos ;
WHEN OTHERS => b4_disp <= zero ;
END CASE ;
END PROCESS ;
-------------------------------------------------------------------------------
-- Special Code for calculating symrd[3:0]
--
-- +---------+---------+-------+------------+-------+------------+
-- | | | symrd |
-- | | | + Start Disp | - Start Disp |
-- | b6_disp | b4_disp | Error | NewRunDisp | Error | NewRunDisp |
-- +---------+---------+-------+------------+-------+------------+
-- | + | + | 1 | 1 | 1 | 1 |
-- | + | - | 1 | 0 | 0 | 0 |
-- | + | 0 | 1 | 1 | 0 | 1 |
-- | - | + | 0 | 1 | 1 | 1 |
-- | - | - | 1 | 0 | 1 | 0 |
-- | - | 0 | 0 | 0 | 1 | 0 |
-- | 0 | + | 1 | 1 | 0 | 1 |
-- | 0 | - | 0 | 0 | 1 | 0 |
-- | 0 | 0 | 0 | 1 | 0 | 0 |
-- +---------+---------+-------+------------+-------+------------+
--
-------------------------------------------------------------------------------
PROCESS (b4_disp, b6_disp)
BEGIN
CASE b6_disp IS
WHEN pos =>
CASE b4_disp IS
WHEN pos => symrd(3 DOWNTO 0) <= "1111";
WHEN neg => symrd(3 DOWNTO 0) <= "1000";
WHEN specpos=> symrd(3 DOWNTO 0) <= "1101"; --Ex: D1.3-
WHEN specneg=> symrd(3 DOWNTO 0) <= "1000";
WHEN zero => symrd(3 DOWNTO 0) <= "1101";
WHEN OTHERS => symrd(3 DOWNTO 0) <= "XXXX";
END CASE;
WHEN neg =>
CASE b4_disp IS
WHEN pos => symrd(3 DOWNTO 0) <= "0111";
WHEN neg => symrd(3 DOWNTO 0) <= "1010";
WHEN specpos=> symrd(3 DOWNTO 0) <= "0111";
WHEN specneg=> symrd(3 DOWNTO 0) <= "0010"; --Ex: D1.3+
WHEN zero => symrd(3 DOWNTO 0) <= "0010";
WHEN OTHERS => symrd(3 DOWNTO 0) <= "XXXX";
END CASE;
WHEN zero =>
CASE b4_disp IS
WHEN pos => symrd(3 DOWNTO 0) <= "1101";
WHEN neg => symrd(3 DOWNTO 0) <= "0010";
WHEN specpos=> symrd(3 DOWNTO 0) <= "0111"; --Ex: D11.3+
WHEN specneg=> symrd(3 DOWNTO 0) <= "1000"; --Ex: D11.3-
WHEN zero => symrd(3 DOWNTO 0) <= "0100";
WHEN OTHERS => symrd(3 DOWNTO 0) <= "XXXX";
END CASE;
WHEN specpos =>
CASE b4_disp IS
WHEN pos => symrd(3 DOWNTO 0) <= "1111";
WHEN neg => symrd(3 DOWNTO 0) <= "0010"; --Ex: D7.0+
WHEN specpos=> symrd(3 DOWNTO 0) <= "0111"; --Ex: D7.3+
WHEN specneg=> symrd(3 DOWNTO 0) <= "1010";
WHEN zero => symrd(3 DOWNTO 0) <= "0111"; --Ex: D7.5+
WHEN OTHERS => symrd(3 DOWNTO 0) <= "XXXX";
END CASE;
WHEN specneg =>
CASE b4_disp IS
WHEN pos => symrd(3 DOWNTO 0) <= "1101"; --Ex: D7.0-
WHEN neg => symrd(3 DOWNTO 0) <= "1010";
WHEN specpos=> symrd(3 DOWNTO 0) <= "1111";
WHEN specneg=> symrd(3 DOWNTO 0) <= "1000"; --Ex: D7.3-
WHEN zero => symrd(3 DOWNTO 0) <= "1000"; --Ex: D7.5-
WHEN OTHERS => symrd(3 DOWNTO 0) <= "XXXX";
END CASE;
WHEN OTHERS => symrd(3 DOWNTO 0) <= "XXXX";
END CASE;
END PROCESS;
-- the new running disparity is calculated from the input disparity
-- and the disparity of the 10-bit word
grdi : IF (C_HAS_DISP_IN = 1 AND C_HAS_RUN_DISP=1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'event and CLK='1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
run_disp_i <= bint_2_sl(C_SINIT_RUN_DISP) AFTER TFF;
ELSIF (DISP_IN = '1') THEN
run_disp_i <= symrd(2) AFTER TFF;
ELSE
run_disp_i <= symrd(0) AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE grdi;
-- the new running disparity is calculated from the old running disparity
-- and the disparity of the 10-bit word. run_disp is also used to
-- calculate disp_err and sym_disp when disp_in is not present
grdni : IF (C_HAS_DISP_IN /= 1 AND (C_HAS_RUN_DISP=1 OR
C_HAS_DISP_ERR=1 OR
C_HAS_SYM_DISP=1)) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'event and CLK='1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
run_disp_i <= bint_2_sl(C_SINIT_RUN_DISP) AFTER TFF;
ELSIF (run_disp_i = '1') THEN
run_disp_i <= symrd(2) AFTER TFF;
ELSE
run_disp_i <= symrd(0) AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE grdni;
gde : IF (C_HAS_DISP_ERR = 1) GENERATE
-- the new disparity error is calculated from the old running disparity
-- and the error information from the 10-bit word
gdei : IF (C_HAS_DISP_IN = 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK='1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
disp_err <= '0' AFTER TFF;
ELSIF (DISP_IN='1') THEN
disp_err <= symrd(3) AFTER TFF;
ELSE
disp_err <= symrd(1) AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE gdei;
gdeni : IF (C_HAS_DISP_IN /= 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK='1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
disp_err <= '0' AFTER TFF;
ELSIF (run_disp_i='1') THEN
disp_err <= symrd(3) AFTER TFF;
ELSE
disp_err <= symrd(1) AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE gdeni;
END GENERATE gde;
gsd : IF (C_HAS_SYM_DISP = 1) GENERATE
gsdi : IF (C_HAS_DISP_IN = 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK='1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
sym_disp_i <= conv_std_logic_vector(C_SINIT_RUN_DISP,2) AFTER TFF;
ELSIF (DISP_IN='1') THEN
sym_disp_i <= symrd(3 DOWNTO 2) AFTER TFF;
ELSE
sym_disp_i <= symrd(1 DOWNTO 0) AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE gsdi;
gsdni : IF (C_HAS_DISP_IN /= 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK='1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
sym_disp_i <= conv_std_logic_vector(C_SINIT_RUN_DISP,2) AFTER TFF;
ELSIF (run_disp_i='1') THEN
sym_disp_i <= symrd(3 DOWNTO 2) AFTER TFF;
ELSE
sym_disp_i <= symrd(1 DOWNTO 0) AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE gsdni;
END GENERATE gsd;
-- map internal signals to outputs
run_disp <= run_disp_i;
sym_disp <= sym_disp_i;
-------------------------------------------------------------------------------
-- Decode the K codes
-------------------------------------------------------------------------------
PROCESS (c, d, e, i, g, h, j)
BEGIN
k <= (c AND d AND e AND i) OR NOT(c OR d OR e OR i) OR
((e XOR i) AND ((i AND g AND h AND j) OR
NOT(i OR g OR h OR j))) ;
END PROCESS ;
-------------------------------------------------------------------------------
-- Update the outputs on the clock
-------------------------------------------------------------------------------
----Update DOUT output-------------------
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
dout_i <= str_to_slv(C_SINIT_DOUT, 8) AFTER TFF ;
ELSE
dout_i <= (b3 & b5) AFTER TFF;
END IF;
END IF ;
END IF ;
END PROCESS ;
DOUT <= dout_i;
----Update KOUT output-------------------
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
kout_i <= bint_2_sl(C_SINIT_KOUT) AFTER TFF;
ELSE
kout_i <= k AFTER TFF;
END IF;
END IF ;
END IF ;
END PROCESS ;
KOUT <= kout_i;
-------------------------------------------------------------------------------
-- Calculate code_error (uses notation from IBM spec)
-------------------------------------------------------------------------------
bitcount: PROCESS (DIN)
BEGIN
CASE DIN(3 DOWNTO 0) IS
WHEN "0000" => p04 <= '1';
p13 <= '0';
p22 <= '0';
p31 <= '0';
p40 <= '0';
WHEN "0001" => p04 <= '0';
p13 <= '1';
p22 <= '0';
p31 <= '0';
p40 <= '0';
WHEN "0010" => p04 <= '0';
p13 <= '1';
p22 <= '0';
p31 <= '0';
p40 <= '0';
WHEN "0011" => p04 <= '0';
p13 <= '0';
p22 <= '1';
p31 <= '0';
p40 <= '0';
WHEN "0100" => p04 <= '0';
p13 <= '1';
p22 <= '0';
p31 <= '0';
p40 <= '0';
WHEN "0101" => p04 <= '0';
p13 <= '0';
p22 <= '1';
p31 <= '0';
p40 <= '0';
WHEN "0110" => p04 <= '0';
p13 <= '0';
p22 <= '1';
p31 <= '0';
p40 <= '0';
WHEN "0111" => p04 <= '0';
p13 <= '0';
p22 <= '0';
p31 <= '1';
p40 <= '0';
WHEN "1000" => p04 <= '0';
p13 <= '1';
p22 <= '0';
p31 <= '0';
p40 <= '0';
WHEN "1001" => p04 <= '0';
p13 <= '0';
p22 <= '1';
p31 <= '0';
p40 <= '0';
WHEN "1010" => p04 <= '0';
p13 <= '0';
p22 <= '1';
p31 <= '0';
p40 <= '0';
WHEN "1011" => p04 <= '0';
p13 <= '0';
p22 <= '0';
p31 <= '1';
p40 <= '0';
WHEN "1100" => p04 <= '0';
p13 <= '0';
p22 <= '1';
p31 <= '0';
p40 <= '0';
WHEN "1101" => p04 <= '0';
p13 <= '0';
p22 <= '0';
p31 <= '1';
p40 <= '0';
WHEN "1110" => p04 <= '0';
p13 <= '0';
p22 <= '0';
p31 <= '1';
p40 <= '0';
WHEN "1111" => p04 <= '0';
p13 <= '0';
p22 <= '0';
p31 <= '0';
p40 <= '1';
WHEN OTHERS => NULL;
END CASE;
END PROCESS bitcount;
fghj <= (f AND g AND h AND j) OR (NOT f AND NOT g AND NOT h AND NOT j);
eifgh <= (e AND i AND f AND g AND h) OR (NOT e AND NOT i AND NOT f AND NOT g
AND NOT h);
sk28 <= (c AND d AND e AND i) OR (NOT c AND NOT d AND NOT e AND NOT i);
e_i <= (e AND NOT i) OR (NOT e AND i);
ighj <= (i AND g AND h AND j) OR (NOT i AND NOT g AND NOT h AND NOT j);
i_ghj <= (NOT i AND g AND h AND j) OR (i AND NOT g AND NOT h AND NOT j);
kx7 <= e_i AND ighj;
invr6 <= p40 OR p04 OR (p31 AND e AND i) OR (p13 AND NOT e AND NOT i);
pdbr6 <= (p31 AND (e OR i)) OR (p22 AND e AND i) OR p40;
ndbr6 <= (p13 AND (NOT e OR NOT i)) OR (p22 AND NOT e AND NOT i) OR p04;
pdur6 <= pdbr6 OR (d AND e AND i);
pdbr4 <= (f AND g AND (h OR j)) OR ((f OR g) AND h AND j);
ndrr4 <= pdbr4 OR (f AND g);
ndur6 <= ndbr6 OR (NOT d AND NOT e AND NOT i);
fgh <= (f AND g AND h) OR (NOT f AND NOT g AND NOT h);
ndbr4 <= (NOT f AND NOT g AND (NOT h OR NOT j)) OR ((NOT f OR NOT g) AND
NOT h AND NOT j);
pdrr4 <= ndbr4 OR (NOT f AND NOT g);
invby_a <= invr6;
invby_b <= fghj;
invby_c <= eifgh;
invby_d <= (NOT sk28 AND i_ghj);
invby_e <= (sk28 AND fgh);
invby_f <= (kx7 AND NOT pdbr6 AND NOT ndbr6);
invby_g <= (pdur6 AND ndrr4);
invby_h <= (ndur6 AND pdrr4);
--Update internal code error signal
code_err_i <= invby_a OR invby_b OR invby_c OR invby_d OR invby_e OR invby_f OR
invby_g OR invby_h;
END xilinx ;
| gpl-3.0 | 4031aa537b66a645c3cb59d7973cce31 | 0.404694 | 3.619726 | false | false | false | false |
Yarr/Yarr-fw | rtl/spartan6/gn4124-core/p2l_dma_master.vhd | 2 | 26,505 | --------------------------------------------------------------------------------
-- --
-- CERN BE-CO-HT GN4124 core for PCIe FMC carrier --
-- http://www.ohwr.org/projects/gn4124-core --
--------------------------------------------------------------------------------
--
-- unit name: 32 bit P2L DMA master (p2l_dma_master.vhd)
--
-- authors: Simon Deprez ([email protected])
-- Matthieu Cattin ([email protected])
--
-- date: 31-08-2010
--
-- version: 0.1
--
-- description: Provides a pipelined Wishbone interface to performs DMA
-- transfers from PCI express host to local application.
-- This entity is also used to catch the next item in chained DMA.
--
-- dependencies: general-cores library (genrams package)
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: 11-07-2011 (mcattin) Replaced Xilinx Coregen FIFOs with genrams
-- library cores from ohwr.org
--------------------------------------------------------------------------------
-- TODO: - byte enable support.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
use work.common_pkg.all;
entity p2l_dma_master is
generic (
-- Enable byte swap module (if false, no swap)
g_BYTE_SWAP : boolean := false
);
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- From the DMA controller
dma_ctrl_carrier_addr_i : in std_logic_vector(31 downto 0);
dma_ctrl_host_addr_h_i : in std_logic_vector(31 downto 0);
dma_ctrl_host_addr_l_i : in std_logic_vector(31 downto 0);
dma_ctrl_len_i : in std_logic_vector(31 downto 0);
dma_ctrl_start_p2l_i : in std_logic;
dma_ctrl_start_next_i : in std_logic;
dma_ctrl_done_o : out std_logic;
dma_ctrl_error_o : out std_logic;
dma_ctrl_byte_swap_i : in std_logic_vector(1 downto 0);
dma_ctrl_abort_i : in std_logic;
---------------------------------------------------------
-- From P2L Decoder (receive the read completion)
--
-- Header
pd_pdm_hdr_start_i : in std_logic; -- Header strobe
pd_pdm_hdr_length_i : in std_logic_vector(9 downto 0); -- Packet length in 32-bit words multiples
pd_pdm_hdr_cid_i : in std_logic_vector(1 downto 0); -- Completion ID
pd_pdm_master_cpld_i : in std_logic; -- Master read completion with data
pd_pdm_master_cpln_i : in std_logic; -- Master read completion without data
--
-- Data
pd_pdm_data_valid_i : in std_logic; -- Indicates Data is valid
pd_pdm_data_last_i : in std_logic; -- Indicates end of the packet
pd_pdm_data_i : in std_logic_vector(31 downto 0); -- Data
pd_pdm_be_i : in std_logic_vector(3 downto 0); -- Byte Enable for data
---------------------------------------------------------
-- P2L control
p2l_rdy_o : out std_logic; -- De-asserted to pause transfer already in progress
rx_error_o : out std_logic; -- Asserted when transfer is aborted
---------------------------------------------------------
-- To the P2L Interface (send the DMA Master Read request)
pdm_arb_valid_o : out std_logic; -- Read completion signals
pdm_arb_dframe_o : out std_logic; -- Toward the arbiter
pdm_arb_data_o : out std_logic_vector(31 downto 0);
pdm_arb_req_o : out std_logic;
arb_pdm_gnt_i : in std_logic;
---------------------------------------------------------
-- DMA Interface (Pipelined Wishbone)
p2l_dma_clk_i : in std_logic; -- Bus clock
p2l_dma_adr_o : out std_logic_vector(31 downto 0); -- Adress
p2l_dma_dat_i : in std_logic_vector(31 downto 0); -- Data in
p2l_dma_dat_o : out std_logic_vector(31 downto 0); -- Data out
p2l_dma_sel_o : out std_logic_vector(3 downto 0); -- Byte select
p2l_dma_cyc_o : out std_logic; -- Read or write cycle
p2l_dma_stb_o : out std_logic; -- Read or write strobe
p2l_dma_we_o : out std_logic; -- Write
p2l_dma_ack_i : in std_logic; -- Acknowledge
p2l_dma_stall_i : in std_logic; -- for pipelined Wishbone
l2p_dma_cyc_i : in std_logic; -- L2P dma wb cycle (for bus arbitration)
---------------------------------------------------------
-- To the DMA controller
next_item_carrier_addr_o : out std_logic_vector(31 downto 0);
next_item_host_addr_h_o : out std_logic_vector(31 downto 0);
next_item_host_addr_l_o : out std_logic_vector(31 downto 0);
next_item_len_o : out std_logic_vector(31 downto 0);
next_item_next_l_o : out std_logic_vector(31 downto 0);
next_item_next_h_o : out std_logic_vector(31 downto 0);
next_item_attrib_o : out std_logic_vector(31 downto 0);
next_item_valid_o : out std_logic
);
end p2l_dma_master;
architecture behaviour of p2l_dma_master is
-----------------------------------------------------------------------------
-- Constants declaration
-----------------------------------------------------------------------------
-- c_MAX_READ_REQ_SIZE is the maximum size (in 32-bit words) of the payload of a packet.
-- Allowed c_MAX_READ_REQ_SIZE values are: 32, 64, 128, 256, 512, 1024.
-- This constant must be set according to the GN4124 and motherboard chipset capabilities.
constant c_MAX_READ_REQ_SIZE : unsigned(10 downto 0) := to_unsigned(1024, 11);
constant c_TO_WB_FIFO_FULL_THRES : integer := 500;
-----------------------------------------------------------------------------
-- Signals declaration
-----------------------------------------------------------------------------
-- control signals
signal is_next_item : std_logic;
signal completion_error : std_logic;
signal dma_busy_error : std_logic;
signal dma_length_error : std_logic;
signal dma_ctrl_done_t : std_logic;
signal rx_error_t : std_logic;
-- L2P packet generator
signal l2p_address_h : std_logic_vector(31 downto 0);
signal l2p_address_l : std_logic_vector(31 downto 0);
signal l2p_len_cnt : unsigned(29 downto 0);
signal l2p_len_header : unsigned(9 downto 0);
signal l2p_64b_address : std_logic;
signal s_l2p_header : std_logic_vector(31 downto 0);
signal l2p_last_packet : std_logic;
signal l2p_lbe_header : std_logic_vector(3 downto 0);
-- Target address counter
signal target_addr_cnt : unsigned(29 downto 0);
-- sync fifo
signal fifo_rst_n : std_logic;
signal to_wb_fifo_empty : std_logic;
signal to_wb_fifo_full : std_logic;
signal to_wb_fifo_rd : std_logic;
signal to_wb_fifo_wr : std_logic;
signal to_wb_fifo_din : std_logic_vector(63 downto 0);
signal to_wb_fifo_dout : std_logic_vector(63 downto 0);
signal to_wb_fifo_valid : std_logic;
signal to_wb_fifo_byte_swap : std_logic_vector(1 downto 0);
-- wishbone
signal wb_write_cnt : unsigned(31 downto 0);
signal wb_ack_cnt : unsigned(31 downto 0);
signal p2l_dma_cyc_t : std_logic;
signal p2l_dma_stb_t : std_logic;
signal p2l_dma_stall_d : std_logic_vector(1 downto 0);
-- P2L DMA read request FSM
type p2l_dma_state_type is (P2L_IDLE, P2L_HEADER, P2L_ADDR_H, P2L_ADDR_L, P2L_WAIT_READ_COMPLETION);
signal p2l_dma_current_state : p2l_dma_state_type;
signal p2l_data_cnt : unsigned(10 downto 0);
begin
------------------------------------------------------------------------------
-- Active high reset for fifo
------------------------------------------------------------------------------
-- Creates an active high reset for fifos regardless of c_RST_ACTIVE value
gen_fifo_rst_n : if c_RST_ACTIVE = '0' generate
fifo_rst_n <= rst_n_i;
end generate;
gen_fifo_rst : if c_RST_ACTIVE = '1' generate
fifo_rst_n <= not(rst_n_i);
end generate;
-- Errors to DMA controller
dma_ctrl_error_o <= dma_busy_error or completion_error;
------------------------------------------------------------------------------
-- PCIe read request
------------------------------------------------------------------------------
-- Stores infofmation for read request packet
-- Can be a P2L DMA transfer or catching the next item of a chained DMA
p_read_req : process (clk_i, rst_n_i)
begin
if (rst_n_i = c_RST_ACTIVE) then
l2p_address_h <= (others => '0');
l2p_address_l <= (others => '0');
l2p_len_cnt <= (others => '0');
l2p_len_header <= (others => '0');
l2p_64b_address <= '0';
is_next_item <= '0';
l2p_last_packet <= '0';
elsif rising_edge(clk_i) then
if (p2l_dma_current_state = P2L_IDLE) then
if (dma_ctrl_start_p2l_i = '1' or dma_ctrl_start_next_i = '1') then
-- Stores DMA info locally
l2p_address_h <= dma_ctrl_host_addr_h_i;
l2p_address_l <= dma_ctrl_host_addr_l_i;
l2p_len_cnt <= unsigned(dma_ctrl_len_i(31 downto 2)); -- dma_ctrl_len_i is in byte
if (dma_ctrl_start_next_i = '1') then
-- Catching next DMA item
is_next_item <= '1'; -- flag for data retrieve block
else
-- P2L DMA transfer
is_next_item <= '0';
end if;
if (dma_ctrl_host_addr_h_i = X"00000000") then
l2p_64b_address <= '0';
else
l2p_64b_address <= '1';
end if;
end if;
elsif (p2l_dma_current_state = P2L_HEADER) then
-- if DMA length is bigger than the max PCIe payload size,
-- we have to generate several read request
if (l2p_len_cnt > c_MAX_READ_REQ_SIZE) then
-- when max payload length is 1024, the header length field = 0
l2p_len_header <= c_MAX_READ_REQ_SIZE(9 downto 0);
l2p_last_packet <= '0';
elsif (l2p_len_cnt = c_MAX_READ_REQ_SIZE) then
-- when max payload length is 1024, the header length field = 0
l2p_len_header <= c_MAX_READ_REQ_SIZE(9 downto 0);
l2p_last_packet <= '1';
else
l2p_len_header <= l2p_len_cnt(9 downto 0);
l2p_last_packet <= '1';
end if;
elsif (p2l_dma_current_state = P2L_ADDR_L) then
-- Subtract the number of word requested to generate a new read request if needed
if (l2p_last_packet = '0') then
l2p_len_cnt <= l2p_len_cnt - c_MAX_READ_REQ_SIZE;
else
l2p_len_cnt <= (others => '0');
end if;
end if;
end if;
end process p_read_req;
-- Last Byte Enable must be "0000" when length = 1
l2p_lbe_header <= "0000" when l2p_len_header = 1 else "1111";
s_l2p_header <= "000" --> Traffic Class
& '0' --> Snoop
& "000" & l2p_64b_address --> Packet type = read request (32 or 64 bits)
& l2p_lbe_header --> LBE (Last Byte Enable)
& "1111" --> FBE (First Byte Enable)
& "000" --> Reserved
& '0' --> VC (Virtual Channel)
& "01" --> CID
& std_logic_vector(l2p_len_header); --> Length (in 32-bit words)
-- 0x000 => 1024 words (4096 bytes)
-----------------------------------------------------------------------------
-- PCIe read request FSM
-----------------------------------------------------------------------------
p_read_req_fsm : process (clk_i, rst_n_i)
begin
if(rst_n_i = c_RST_ACTIVE) then
p2l_dma_current_state <= P2L_IDLE;
pdm_arb_req_o <= '0';
pdm_arb_data_o <= (others => '0');
pdm_arb_valid_o <= '0';
pdm_arb_dframe_o <= '0';
dma_ctrl_done_t <= '0';
next_item_valid_o <= '0';
completion_error <= '0';
rx_error_t <= '0';
elsif rising_edge(clk_i) then
case p2l_dma_current_state is
when P2L_IDLE =>
-- Clear status bits
dma_ctrl_done_t <= '0';
next_item_valid_o <= '0';
completion_error <= '0';
rx_error_t <= '0';
-- Start a read request when a P2L DMA is initated or when the DMA
-- controller asks for the next DMA info (in a chained DMA).
if (dma_ctrl_start_p2l_i = '1' or dma_ctrl_start_next_i = '1') then
-- request access to PCIe bus
pdm_arb_req_o <= '1';
-- prepare a packet, first the header
p2l_dma_current_state <= P2L_HEADER;
end if;
when P2L_HEADER =>
if(arb_pdm_gnt_i = '1') then
-- clear access request to the arbiter
-- access is granted until dframe is cleared
pdm_arb_req_o <= '0';
-- send header
pdm_arb_data_o <= s_l2p_header;
pdm_arb_valid_o <= '1';
pdm_arb_dframe_o <= '1';
if(l2p_64b_address = '1') then
-- if host address is 64-bit, we have to send an additionnal
-- 32-word containing highest bits of the host address
p2l_dma_current_state <= P2L_ADDR_H;
else
-- for 32-bit host address, we only have to send lowest bits
p2l_dma_current_state <= P2L_ADDR_L;
end if;
end if;
when P2L_ADDR_H =>
-- send host address 32 highest bits
pdm_arb_data_o <= l2p_address_h;
p2l_dma_current_state <= P2L_ADDR_L;
when P2L_ADDR_L =>
-- send host address 32 lowest bits
pdm_arb_data_o <= l2p_address_l;
-- clear dframe signal to indicate the end of packet
pdm_arb_dframe_o <= '0';
p2l_dma_current_state <= P2L_WAIT_READ_COMPLETION;
when P2L_WAIT_READ_COMPLETION =>
-- End of the read request packet
pdm_arb_valid_o <= '0';
if (dma_ctrl_abort_i = '1') then
rx_error_t <= '1';
p2l_dma_current_state <= P2L_IDLE;
elsif (pd_pdm_master_cpld_i = '1' and pd_pdm_data_last_i = '1'
and p2l_data_cnt <= 1) then
-- last word of read completion has been received
if (l2p_last_packet = '0') then
-- A new read request is needed, DMA size > max payload
p2l_dma_current_state <= P2L_HEADER;
-- As the end of packet is used to delimit arbitration phases
-- we have to ask again for permission
pdm_arb_req_o <= '1';
else
-- indicate end of DMA transfer
if (is_next_item = '1') then
next_item_valid_o <= '1';
else
dma_ctrl_done_t <= '1';
end if;
p2l_dma_current_state <= P2L_IDLE;
end if;
elsif (pd_pdm_master_cpln_i = '1') then
-- should not return a read completion without data
completion_error <= '1';
p2l_dma_current_state <= P2L_IDLE;
end if;
when others =>
p2l_dma_current_state <= P2L_IDLE;
pdm_arb_req_o <= '0';
pdm_arb_data_o <= (others => '0');
pdm_arb_valid_o <= '0';
pdm_arb_dframe_o <= '0';
dma_ctrl_done_t <= '0';
next_item_valid_o <= '0';
completion_error <= '0';
rx_error_t <= '0';
end case;
end if;
end process p_read_req_fsm;
------------------------------------------------------------------------------
-- Pipeline control signals
------------------------------------------------------------------------------
p_ctrl_pipe : process (clk_i, rst_n_i)
begin
if (rst_n_i = c_RST_ACTIVE) then
rx_error_o <= '0';
dma_ctrl_done_o <= '0';
elsif rising_edge(clk_i) then
rx_error_o <= rx_error_t;
dma_ctrl_done_o <= dma_ctrl_done_t;
end if;
end process p_ctrl_pipe;
------------------------------------------------------------------------------
-- Received data counter
------------------------------------------------------------------------------
p_recv_data_cnt : process (clk_i, rst_n_i)
begin
if (rst_n_i = c_RST_ACTIVE) then
p2l_data_cnt <= (others => '0');
elsif rising_edge(clk_i) then
if (p2l_dma_current_state = P2L_ADDR_L) then
-- Store number of 32-bit data words to be received for the current read request
if l2p_len_header = 0 then
p2l_data_cnt <= to_unsigned(1024, p2l_data_cnt'length);
else
p2l_data_cnt <= '0' & l2p_len_header;
end if;
elsif (p2l_dma_current_state = P2L_WAIT_READ_COMPLETION
and pd_pdm_data_valid_i = '1'
and pd_pdm_master_cpld_i = '1') then
-- decrement number of data to be received
p2l_data_cnt <= p2l_data_cnt - 1;
end if;
end if;
end process p_recv_data_cnt;
------------------------------------------------------------------------------
-- Next DMA item retrieve
------------------------------------------------------------------------------
p_next_item : process (clk_i, rst_n_i)
begin
if (rst_n_i = c_RST_ACTIVE) then
next_item_carrier_addr_o <= (others => '0');
next_item_host_addr_h_o <= (others => '0');
next_item_host_addr_l_o <= (others => '0');
next_item_len_o <= (others => '0');
next_item_next_l_o <= (others => '0');
next_item_next_h_o <= (others => '0');
next_item_attrib_o <= (others => '0');
elsif rising_edge(clk_i) then
if (p2l_dma_current_state = P2L_WAIT_READ_COMPLETION
and is_next_item = '1' and pd_pdm_data_valid_i = '1') then
-- next item data are supposed to be received in the rigth order !!
case p2l_data_cnt(2 downto 0) is
when "111" =>
next_item_carrier_addr_o <= pd_pdm_data_i;
when "110" =>
next_item_host_addr_l_o <= pd_pdm_data_i;
when "101" =>
next_item_host_addr_h_o <= pd_pdm_data_i;
when "100" =>
next_item_len_o <= pd_pdm_data_i;
when "011" =>
next_item_next_l_o <= pd_pdm_data_i;
when "010" =>
next_item_next_h_o <= pd_pdm_data_i;
when "001" =>
next_item_attrib_o <= pd_pdm_data_i;
when others =>
null;
end case;
end if;
end if;
end process p_next_item;
------------------------------------------------------------------------------
-- Target address counter
------------------------------------------------------------------------------
p_addr_cnt : process (clk_i, rst_n_i)
begin
if (rst_n_i = c_RST_ACTIVE) then
target_addr_cnt <= (others => '0');
dma_busy_error <= '0';
to_wb_fifo_din <= (others => '0');
to_wb_fifo_wr <= '0';
to_wb_fifo_byte_swap <= (others => '0');
elsif rising_edge(clk_i) then
if (dma_ctrl_start_p2l_i = '1') then
if (p2l_dma_current_state = P2L_IDLE) then
-- dma_ctrl_target_addr_i is a byte address and target_addr_cnt is a
-- 32-bit word address
target_addr_cnt <= unsigned(dma_ctrl_carrier_addr_i(31 downto 2));
-- stores byte swap info for the current DMA transfer
to_wb_fifo_byte_swap <= dma_ctrl_byte_swap_i;
else
dma_busy_error <= '1';
end if;
elsif (p2l_dma_current_state = P2L_WAIT_READ_COMPLETION
and is_next_item = '0' and pd_pdm_data_valid_i = '1') then
-- increment target address counter
target_addr_cnt <= target_addr_cnt + 1;
-- write target address and data to the sync fifo
to_wb_fifo_wr <= '1';
to_wb_fifo_din(31 downto 0) <= f_byte_swap(g_BYTE_SWAP, pd_pdm_data_i, to_wb_fifo_byte_swap);
to_wb_fifo_din(61 downto 32) <= std_logic_vector(target_addr_cnt);
else
dma_busy_error <= '0';
to_wb_fifo_wr <= '0';
end if;
end if;
end process p_addr_cnt;
------------------------------------------------------------------------------
-- FIFOs for transition between GN4124 core and wishbone clock domain
------------------------------------------------------------------------------
cmp_to_wb_fifo : generic_async_fifo
generic map (
g_data_width => 64,
g_size => 512,
g_show_ahead => false,
g_with_rd_empty => true,
g_with_rd_full => false,
g_with_rd_almost_empty => false,
g_with_rd_almost_full => false,
g_with_rd_count => false,
g_with_wr_empty => false,
g_with_wr_full => false,
g_with_wr_almost_empty => false,
g_with_wr_almost_full => true,
g_with_wr_count => false,
g_almost_empty_threshold => 0,
g_almost_full_threshold => c_TO_WB_FIFO_FULL_THRES)
port map (
rst_n_i => fifo_rst_n,
clk_wr_i => clk_i,
d_i => to_wb_fifo_din,
we_i => to_wb_fifo_wr,
wr_empty_o => open,
wr_full_o => open,
wr_almost_empty_o => open,
wr_almost_full_o => to_wb_fifo_full,
wr_count_o => open,
clk_rd_i => p2l_dma_clk_i,
q_o => to_wb_fifo_dout,
rd_i => to_wb_fifo_rd,
rd_empty_o => to_wb_fifo_empty,
rd_full_o => open,
rd_almost_empty_o => open,
rd_almost_full_o => open,
rd_count_o => open);
p_gen_fifo_valid : process(p2l_dma_clk_i)
begin
if rising_edge(p2l_dma_clk_i) then
to_wb_fifo_valid <= to_wb_fifo_rd and (not to_wb_fifo_empty);
end if;
end process;
-- pause transfer from GN4124 if fifo is (almost) full
p2l_rdy_o <= not(to_wb_fifo_full);
------------------------------------------------------------------------------
-- Wishbone master (write only)
------------------------------------------------------------------------------
-- fifo read
to_wb_fifo_rd <= not(to_wb_fifo_empty)
and not(p2l_dma_stall_i)
and not(l2p_dma_cyc_i);
-- write only
p2l_dma_we_o <= '1';
-- Wishbone master process
p_wb_master : process (rst_n_i, p2l_dma_clk_i)
begin
if (rst_n_i = c_RST_ACTIVE) then
p2l_dma_cyc_t <= '0';
p2l_dma_stb_t <= '0';
p2l_dma_sel_o <= "0000";
p2l_dma_adr_o <= (others => '0');
p2l_dma_dat_o <= (others => '0');
p2l_dma_stall_d <= (others => '0');
elsif rising_edge(p2l_dma_clk_i) then
p2l_dma_stall_d(0) <= p2l_dma_stall_i;
p2l_dma_stall_d(1) <= p2l_dma_stall_d(0);
-- data and address
if (to_wb_fifo_valid = '1') then
p2l_dma_adr_o(31 downto 30) <= "00";
p2l_dma_adr_o(29 downto 0) <= to_wb_fifo_dout(61 downto 32);
p2l_dma_dat_o <= to_wb_fifo_dout(31 downto 0);
end if;
-- stb and sel signals management
if (to_wb_fifo_valid = '1') then --or (p2l_dma_stall_i = '1' and p2l_dma_stb_t = '1') then
p2l_dma_stb_t <= '1';
p2l_dma_sel_o <= (others => '1');
else
p2l_dma_stb_t <= '0';
p2l_dma_sel_o <= (others => '0');
end if;
-- cyc signal management
if (to_wb_fifo_valid = '1') then
p2l_dma_cyc_t <= '1';
elsif (wb_ack_cnt >= wb_write_cnt and p2l_dma_stall_d(1) = '0') then
-- last ack received -> end of the transaction
p2l_dma_cyc_t <= '0';
end if;
end if;
end process p_wb_master;
-- for read back
p2l_dma_cyc_o <= p2l_dma_cyc_t;
p2l_dma_stb_o <= p2l_dma_stb_t;
-- Wishbone write cycle counter
p_wb_write_cnt : process (p2l_dma_clk_i, rst_n_i)
begin
if (rst_n_i = c_RST_ACTIVE) then
wb_write_cnt <= (others => '0');
elsif rising_edge(p2l_dma_clk_i) then
if (to_wb_fifo_valid = '1') then
wb_write_cnt <= wb_write_cnt + 1;
end if;
end if;
end process p_wb_write_cnt;
-- Wishbone ack counter
p_wb_ack_cnt : process (p2l_dma_clk_i, rst_n_i)
begin
if (rst_n_i = c_RST_ACTIVE) then
wb_ack_cnt <= (others => '0');
elsif rising_edge(p2l_dma_clk_i) then
if (p2l_dma_ack_i = '1' and p2l_dma_cyc_t = '1') then
wb_ack_cnt <= wb_ack_cnt + 1;
end if;
end if;
end process p_wb_ack_cnt;
end behaviour;
| gpl-3.0 | 1a808662c21cdafd73e18bf97ec8c60e | 0.483418 | 3.526008 | false | false | false | false |
Nibble-Knowledge/peripheral-ethernet | vhdl-serial/clock_divider.vhd | 1 | 1,345 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:58:11 02/06/2016
-- Design Name:
-- Module Name: clock_divider - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity clock_divider is
Generic ( TICK : integer := 3333 );
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
clk_uart : out STD_LOGIC);
end clock_divider;
architecture Behavioral of clock_divider is
signal counter : integer;
begin
process(clk, reset)
begin
if reset = '1' then
counter <= 0;
elsif rising_edge(clk) then
if counter = TICK then
clk_uart <= '1';
counter <= 0;
else
clk_uart <= '0';
counter <= counter + 1;
end if;
end if;
end process;
end Behavioral;
| unlicense | 13c18a1aada52ae59f94eced00945401 | 0.576952 | 3.810198 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/checkbit_handler.vhd | 1 | 26,249 | -------------------------------------------------------------------------------
-- checkbit_handler.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: checkbit_handler.vhd
--
-- Description: Generates the ECC checkbits for the input vector of data bits.
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/1/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity checkbit_handler is
generic (
C_ENCODE : boolean := true;
C_USE_LUT6 : boolean := true
);
port (
DataIn : in std_logic_vector (31 downto 0);
CheckIn : in std_logic_vector (6 downto 0);
CheckOut : out std_logic_vector (6 downto 0);
Syndrome : out std_logic_vector (6 downto 0);
Syndrome_4 : out std_logic_vector (1 downto 0);
Syndrome_6 : out std_logic_vector (5 downto 0);
Syndrome_Chk : in std_logic_vector (0 to 6);
Enable_ECC : in std_logic;
UE_Q : in std_logic;
CE_Q : in std_logic;
UE : out std_logic;
CE : out std_logic
);
end entity checkbit_handler;
library unisim;
use unisim.vcomponents.all;
-- library axi_bram_ctrl_v1_02_a;
-- use axi_bram_ctrl_v1_02_a.all;
architecture IMP of checkbit_handler is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
component XOR18 is
generic (
C_USE_LUT6 : boolean);
port (
InA : in std_logic_vector(0 to 17);
res : out std_logic);
end component XOR18;
component Parity is
generic (
C_USE_LUT6 : boolean;
C_SIZE : integer);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic);
end component Parity;
signal data_chk0 : std_logic_vector(0 to 17);
signal data_chk1 : std_logic_vector(0 to 17);
signal data_chk2 : std_logic_vector(0 to 17);
signal data_chk3 : std_logic_vector(0 to 14);
signal data_chk4 : std_logic_vector(0 to 14);
signal data_chk5 : std_logic_vector(0 to 5);
begin -- architecture IMP
data_chk0 <= DataIn(0) & DataIn(1) & DataIn(3) & DataIn(4) & DataIn(6) & DataIn(8) & DataIn(10) &
DataIn(11) & DataIn(13) & DataIn(15) & DataIn(17) & DataIn(19) & DataIn(21) &
DataIn(23) & DataIn(25) & DataIn(26) & DataIn(28) & DataIn(30);
data_chk1 <= DataIn(0) & DataIn(2) & DataIn(3) & DataIn(5) & DataIn(6) & DataIn(9) & DataIn(10) &
DataIn(12) & DataIn(13) & DataIn(16) & DataIn(17) & DataIn(20) & DataIn(21) &
DataIn(24) & DataIn(25) & DataIn(27) & DataIn(28) & DataIn(31);
data_chk2 <= DataIn(1) & DataIn(2) & DataIn(3) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) &
DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25) & DataIn(29) & DataIn(30) & DataIn(31);
data_chk3 <= DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) &
DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25);
data_chk4 <= DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) &
DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25);
data_chk5 <= DataIn(26) & DataIn(27) & DataIn(28) & DataIn(29) & DataIn(30) & DataIn(31);
-- Encode bits for writing data
Encode_Bits : if (C_ENCODE) generate
signal data_chk3_i : std_logic_vector(0 to 17);
signal data_chk4_i : std_logic_vector(0 to 17);
signal data_chk6 : std_logic_vector(0 to 17);
begin
------------------------------------------------------------------------------------------------
-- Checkbit 0 built up using XOR18
------------------------------------------------------------------------------------------------
XOR18_I0 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk0, -- [in std_logic_vector(0 to 17)]
res => CheckOut(0)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 1 built up using XOR18
------------------------------------------------------------------------------------------------
XOR18_I1 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk1, -- [in std_logic_vector(0 to 17)]
res => CheckOut(1)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 2 built up using XOR18
------------------------------------------------------------------------------------------------
XOR18_I2 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk2, -- [in std_logic_vector(0 to 17)]
res => CheckOut(2)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 3 built up using XOR18
------------------------------------------------------------------------------------------------
data_chk3_i <= data_chk3 & "000";
XOR18_I3 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk3_i, -- [in std_logic_vector(0 to 17)]
res => CheckOut(3)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 4 built up using XOR18
------------------------------------------------------------------------------------------------
data_chk4_i <= data_chk4 & "000";
XOR18_I4 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk4_i, -- [in std_logic_vector(0 to 17)]
res => CheckOut(4)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 5 built up from 1 LUT6
------------------------------------------------------------------------------------------------
Parity_chk5_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk5, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => CheckOut(5)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 6 built up from 3 LUT7 and 4 LUT6
------------------------------------------------------------------------------------------------
data_chk6 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(4) & DataIn(5) & DataIn(7) & DataIn(10) &
DataIn(11) & DataIn(12) & DataIn(14) & DataIn(17) & DataIn(18) & DataIn(21) &
DataIn(23) & DataIn(24) & DataIn(26) & DataIn(27) & DataIn(29);
XOR18_I6 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk6, -- [in std_logic_vector(0 to 17)]
res => CheckOut(6)); -- [out std_logic]
end generate Encode_Bits;
--------------------------------------------------------------------------------------------------
-- Decode bits to get syndrome and UE/CE signals
--------------------------------------------------------------------------------------------------
Decode_Bits : if (not C_ENCODE) generate
signal syndrome_i : std_logic_vector(0 to 6) := (others => '0');
signal chk0_1 : std_logic_vector(0 to 3);
signal chk1_1 : std_logic_vector(0 to 3);
signal chk2_1 : std_logic_vector(0 to 3);
signal data_chk3_i : std_logic_vector(0 to 15);
signal chk3_1 : std_logic_vector(0 to 1);
signal data_chk4_i : std_logic_vector(0 to 15);
signal chk4_1 : std_logic_vector(0 to 1);
signal data_chk5_i : std_logic_vector(0 to 6);
signal data_chk6 : std_logic_vector(0 to 38);
signal chk6_1 : std_logic_vector(0 to 5);
signal syndrome_0_to_2 : std_logic_vector (0 to 2);
signal syndrome_3_to_5 : std_logic_vector (3 to 5);
signal syndrome_3_to_5_multi : std_logic;
signal syndrome_3_to_5_zero : std_logic;
signal ue_i_0 : std_logic;
signal ue_i_1 : std_logic;
begin
------------------------------------------------------------------------------------------------
-- Syndrome bit 0 built up from 3 LUT6 and 1 LUT4
------------------------------------------------------------------------------------------------
chk0_1(3) <= CheckIn(0);
Parity_chk0_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(0)); -- [out std_logic]
Parity_chk0_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(1)); -- [out std_logic]
Parity_chk0_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(2)); -- [out std_logic]
Parity_chk0_4 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4)
port map (
InA => chk0_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(0)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 1 built up from 3 LUT6 and 1 LUT4
------------------------------------------------------------------------------------------------
chk1_1(3) <= CheckIn(1);
Parity_chk1_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(0)); -- [out std_logic]
Parity_chk1_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(1)); -- [out std_logic]
Parity_chk1_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(2)); -- [out std_logic]
Parity_chk1_4 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4)
port map (
InA => chk1_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(1)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 2 built up from 3 LUT6 and 1 LUT4
------------------------------------------------------------------------------------------------
chk2_1(3) <= CheckIn(2);
Parity_chk2_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(0)); -- [out std_logic]
Parity_chk2_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(1)); -- [out std_logic]
Parity_chk2_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(2)); -- [out std_logic]
Parity_chk2_4 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4)
port map (
InA => chk2_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(2)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 3 built up from 2 LUT8 and 1 LUT2
------------------------------------------------------------------------------------------------
data_chk3_i <= data_chk3 & CheckIn(3);
Parity_chk3_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk3_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk3_1(0)); -- [out std_logic]
Parity_chk3_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk3_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk3_1(1)); -- [out std_logic]
-- For improved timing, remove Enable_ECC signal in this LUT level
Parity_chk3_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2)
port map (
InA => chk3_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(3)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 4 built up from 2 LUT8 and 1 LUT2
------------------------------------------------------------------------------------------------
data_chk4_i <= data_chk4 & CheckIn(4);
Parity_chk4_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk4_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk4_1(0)); -- [out std_logic]
Parity_chk4_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk4_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk4_1(1)); -- [out std_logic]
-- Parity_chk4_3 : Parity
-- generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2)
-- port map (
-- InA => chk4_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
-- Res => syndrome_i(4)); -- [out std_logic]
-- Set bit 4 output with default. Real ECC XOR value will be determined post register
-- stage.
syndrome_i (4) <= '0';
-- For improved timing, move last LUT level XOR to next side of pipeline
-- stage in read path.
Syndrome_4 <= chk4_1;
------------------------------------------------------------------------------------------------
-- Syndrome bit 5 built up from 1 LUT7
------------------------------------------------------------------------------------------------
data_chk5_i <= data_chk5 & CheckIn(5);
Parity_chk5_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk5_i, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(5)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 6 built up from 3 LUT7 and 4 LUT6
------------------------------------------------------------------------------------------------
data_chk6 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(3) & DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) &
DataIn(8) & DataIn(9) & DataIn(10) & DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) &
DataIn(15) & DataIn(16) & DataIn(17) & DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) &
DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25) & DataIn(26) & DataIn(27) & DataIn(28) &
DataIn(29) & DataIn(30) & DataIn(31) & CheckIn(5) & CheckIn(4) & CheckIn(3) & CheckIn(2) &
CheckIn(1) & CheckIn(0) & CheckIn(6);
Parity_chk6_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk6(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(0)); -- [out std_logic]
Parity_chk6_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk6(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(1)); -- [out std_logic]
Parity_chk6_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk6(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(2)); -- [out std_logic]
Parity_chk6_4 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk6(18 to 24), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(3)); -- [out std_logic]
Parity_chk6_5 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk6(25 to 31), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(4)); -- [out std_logic]
Parity_chk6_6 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk6(32 to 38), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(5)); -- [out std_logic]
-- Parity_chk6_7 : Parity
-- generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
-- port map (
-- InA => chk6_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
-- Res => syndrome_i(6)); -- [out std_logic]
-- No internal use for MSB of syndrome (it is created after the
-- register stage, outside of this block)
syndrome_i(6) <= '0';
Syndrome <= syndrome_i;
-- (N:0) <= (0:N)
-- Bring out seperate output to do final XOR stage on Syndrome (6) after
-- the pipeline stage.
Syndrome_6 <= chk6_1 (0 to 5);
---------------------------------------------------------------------------
-- With final syndrome registered outside this module for pipeline balancing
-- Use registered syndrome to generate any error flags.
-- Use input signal, Syndrome_Chk which is the registered Syndrome used to
-- correct any single bit errors.
syndrome_0_to_2 <= Syndrome_Chk(0) & Syndrome_Chk(1) & Syndrome_Chk(2);
syndrome_3_to_5 <= Syndrome_Chk(3) & Syndrome_Chk(4) & Syndrome_Chk(5);
syndrome_3_to_5_zero <= '1' when syndrome_3_to_5 = "000" else '0';
syndrome_3_to_5_multi <= '1' when (syndrome_3_to_5 = "111" or
syndrome_3_to_5 = "011" or
syndrome_3_to_5 = "101")
else '0';
-- Ensure that CE flag is only asserted for a single clock cycle (and does not keep
-- registered output value)
CE <= (Enable_ECC and Syndrome_Chk(6)) when (syndrome_3_to_5_multi = '0') else '0';
-- Similar edit from CE flag. Ensure that UE flags are only asserted for a single
-- clock cycle. The flags are registered outside this module for detection in
-- register module.
ue_i_0 <= Enable_ECC when (syndrome_3_to_5_zero = '0') or (syndrome_0_to_2 /= "000") else '0';
ue_i_1 <= Enable_ECC and (syndrome_3_to_5_multi);
Use_LUT6: if (C_USE_LUT6) generate
begin
UE_MUXF7 : MUXF7
port map (
I0 => ue_i_0,
I1 => ue_i_1,
S => Syndrome_Chk(6),
O => UE);
end generate Use_LUT6;
Use_RTL: if (not C_USE_LUT6) generate
begin
UE <= ue_i_1 when Syndrome_Chk(6) = '1' else ue_i_0;
end generate Use_RTL;
end generate Decode_Bits;
end architecture IMP;
| bsd-2-clause | 5e4acc8edc08650a3cbe2558444fb90e | 0.442912 | 3.853347 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/signal/rule_014_test_input.vhd | 1 | 1,217 |
architecture RTL of ENTITY1 is
signal sig1, sig2 : std_logic;
signal sig9 : std_logic;
signal sig3 : std_logic;
signal sig4 : std_logic;
signal sig5 : std_logic;
signal sig6 : std_logic;
signal sig7 : std_logic;
component COMP1 is
port (
SIG1 : in std_logic;
SIG2 : out std_logic;
SIG3 : in std_logic
);
end component COMP1;
begin
PROC_NAME : process (siG2) is
begin
siG1 <= '0';
if (SIG2 = '0') then
sIg1 <= '1';
elsif (SiG2 = '1') then
SIg1 <= '0';
end if;
end process PROC_NAME;
-- This is a component that is brought in by a component declaration in the same file
U_COMP1 : COMP1
port map (
SIG1 => Sig1,
SIG2 => SIg2,
SIG3 => sig3
);
-- This is a component that is brought in by a package
U_COMP2 : COMP2
port map (
SIG3 => Sig3,
SIG4 => sig4,
SIG5 => siG5
);
-- This is a component that is directly instantiated
U_COMP3 : entity library.COMP3
port map (
SIG6 => siG6,
SIG7 => sig7
);
Sig1 <= '0';
sig1 <= sig2 and sig3;
sig1 <= Sig2 and sig3;
sig1 <= sig2 and
Sig3;
SIG1 <= SIG2 and SIG3;
SIG1 <= SIG1 or SIG1;
end architecture RTL;
| gpl-3.0 | 63fc1c45b543b34cc74ba5d97dfbe4de | 0.581758 | 3.057789 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/generic_map/rule_601_test_input.vhd | 1 | 492 |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : INST1
generic map (
W_GEN_1 => 3,
GEN_2 => 4,
WR_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
end architecture ARCH;
| gpl-3.0 | 2331a410c7c2b0135c959b2ede2894dc | 0.455285 | 2.779661 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/blk_mem_gen_v8_0/blk_mem_gen_prim_width.vhd | 2 | 70,607 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
jil4IvgVMvTDCe1v/NxeuERnTlA5p6U4lkoNWlRM4I12XciN7RcaSd9VzFqHU5CnflWAVtHLTlV6
twEOya3ffQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Woa5fw7+m9/rT3WFrKFNyQp3CEh9JxVTrjZbvODWT2xbBagiFOs9QW/CgGMOaKbySUTQ17kpANvr
TwZPJ4/11EttPhMOZ3gsQhcC91dD/qP57l8rQFZ726PNhFn/65bRSHD1rxIxnt9WXAVqtbPsAGVb
ydrXHHIEzRWEiGD+yOM=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
wg8Jjuv0R2oQs1z+NYspS7XiYNezKmfCLxe4vYoGi/vHIDF4uXL//COI4Z5XoNBZMqz0N4FICVhT
pcMxyJD7i2kavDcKF1INsx1AHTGEn2+ABcXkQJGyzxd0E2xHQdBer0qYKNYUSxhRgg6XWpPaQQxx
NSU4HgKDSoX71xxYQ3tdeJVqYm+63x9hCO1RqDdHeqHqltgLHv8am/Io7q+Y5hVDwSAP52iAFMe9
Ol9/0mT2+YdFiDEPmFjtlhwnOcYus0EPX7rcdlU2jVeFW9sF0HNdD4mfTSXiIpsW6h3CAJyO3in1
xLn7WMs7XqPDP6bhwoD45r8/rkmt9rh1fzZriw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
27GtccqyyI5l4ofoWmNKOGbLIi8U1C8bBaJ36rGKl43ATXYvQcIu/TZlQsc5ZibMv4yrFONC0i18
7qj5cMNMBYNF84+7f37tNbrwpPSKGY9KEG7PNbd0sINuOIVRWm779eracT1bZUzkRBYZqMnoJhXf
ku/X8ElSB0Q1rsO1HLE=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
kTNJfMX8qQuvaXgF4YOtU6jO3ft+J8zyTI5slGt5t08gFPZ23+eoKzJcau/6P4U3rqjtLsjLp/dQ
DikuuJrEp5K1Oy02tC5/cIybS8fDgu+4vGFKWXzLxixBmI/DPTYB+6NxuUyl2F70KAzsfuLQqSZF
/1vRQlZuyCjqZDsJYQIoZHUpkGSV0wOl6kBgDfblZNyvO1o3B5hjReG4qJK1zffXqRw5l4kO30l6
evjHTB97+I8jRrDCwROg3Oo286/bSJpnXs6ICVmn8EEcFUmZ4BzPK1I9XFJJW57KwHpnDLKlHvGG
Rj8NGO9D57xOL65c600oQ8AUHItrH6V4MC5oww==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 50528)
`protect data_block
eHiboXlGUu/atNexXjeLBxPPSld8oUWJPo+lchA03vv4gMbp4tO/GdtD8Wn7OLNGNzPcrFuKF24B
R8Kt4shpew47FNWUOjI0cnWG2wGGeG0MIz1QiK7YRaiAPEdReK82zDy7ZroJgIRaiFkv3ftLOhfd
J+oyevIcqMIHQt4rKvE2oF5+XyO1sP0Q2MT49vFgfK7AdxtLYk7OlM1V8pVAYiI8dEW2umLScB0E
fY7Dp6KhPnF/lnnujp/2c8uWZ2LzU68RB27yX3v4cNjYrajyARlQjj249krWnu3G/FiPkTf3qvzv
Tm8k7lf+boiwwLIMhKwx0x4kkzvk//JXP7df/jbo3lUDTQhlkTzd408cGYJ1iZmEf5GbQc0AanF7
EXgtiEGZPVatDn1I/K+gTtqBgY1BcLmQBZywBtreHhW6QDkys92wpAprutXok4SqbZoRQJV81ct9
kplchL5waPTKqix+WdeWXC8Rt9Lkir5f/u/keUuh2nEszP986/2LCi1NGyFiSZlF+QK7oD+NdwvB
Ydyw8y7WxPQEOwamKCdXg3YLPY3fffryuObwU3HLPPkTrznSY1+sSDZCgrkjYtlYL7hQqoA0Xayq
zR95aaILN0+jH2Tq1/Iol48q7Eb7w6Gou7sMXl5RCyqEBDUHFtJN6PMnYrarxUzzIBFnGp7vwxP5
cR3uxRTQEPvFNk+YA0MgM4l2oL9l2h/DoxF4MaxYeVJ4ScDoGsETz8FciQYX1CLhiW39ORIRt/5R
zLK4vtnHAeQ2eKGSpcVK2riIpj7TFtvHImh7tB65j+62OtQ/oiJReQDoLzRRZDThuGOWHCX0+okS
7CKpoZQcHdeKuWQS/R2R+7+yjZ0FBb8Pfs+ggkYP/VMpTc6r7cLoII5x5H+il2lRqmLcgn2J1jJO
1rPqJypRYggZ+jIvCHWmyUsr4z2ZhpRnghh+PN1fd+mbzld/86wqCwY7rKF1zpqpN+C1xIMSuQHE
2qhBtHHSCpOL10SE/gVVCROnZxu1iQtGBs5w80nXFi1vC2lX+ZFIs1zKAsQmJW2AXQMp3ATDfl8D
ZVLwaiO90D5jvvC7yqbja8Um81hd01DyKaWtj5MGKFCsw8Zy74WSLi97lvZnk2oCFxV3fX6Netis
64FyD8mtmGXml2vUkaPnEgBrIQ26JXM6gf51C9nnfd7YW6XFSclqU5QInPdQawW/nu9PS90+RA9X
FgAZYJbcXd0jzic4jP7GDZURM17eYqkc6H2ObBYhjFur2sZpzPZ8B3bDWoBxZB5g+y5Fci0ag8bO
TLLoiW1INdRbwbffGPLjLtVUuRsC4VHrKSEKuntY9viWNtATvUOLIVsMFrAsYsiOc7TLlcFg+jfu
Hw4QuOphSedSQdb8etU+hQFll5/K7DzlJxkqOSM2MUraxYa/dw9t8N8t5X++zsteAy3db2jTYFq7
FljLskSq2vq/mfkW16AatSzfuuKUnbRY2aJwfsauYoZ6qcdLp2aiS7s/eQ8QRIk1DoyiNR4xGnNB
6UBgErJr6Wnc/pQtRqgy+i+Jg0wI6ia6UddcSROgq4Db+fkXZ54jsxnzV8OM9yt9XZgSvoQZyRYX
e/rb4MEMn6jgokLvg72JVUBnxC0SCL6TytpUEPn/zcVZBS5IPltSrOCtYLfpeAKdZxhyTX4SQ1pq
8ykxw2D6rp+02/aykpu9Kmc2+aqUAXtqmYA7+YGf2BulTxXulh487pgZlTskzvQj07msjCzckjmL
76UpZo86nV8Q9SjoA0n7cTBm5NM5iGK45mp3ul25DzOraISZe2tzyVvsm/P0E/P3uxeWocSLGX56
xdry7DzQrGwl6IU0LoalPJv6ehk8CKuSlQ63cLQmjilnNaapXfHE99rS0qbMppoxa7Co90Ciq7gP
cf5Ozx5XQ79O3R4i375407PP8OczoT68iMv9Hr57Om9RzljDtsXJ/FNZ8DP7WUw1V0LzGYbJHUN+
/pjrrjHRk8DKpvOO+uhJW1p9WLhJTfX518zbsP5Nb+qiztLKhp5wSIhvTL9zoSrD83FxnCpQ1dj6
AwFmnMKntcxBjtCRMmMrca3cdFfWnaprpWm7gtjEBzgkhfVehLIIV1fm6fstgRZ6tqJO3iSBPZff
M9C8gO2bjybSX5vshxX0J01/U5NJEtzV8BsoCrNfQ9buWQYnwYzZZvxd07KLj3SzgiaenOcKyKvv
IGUALrXFMqOez5BvDFj+1v1o7WPzcUAr87pb+xxOGfJ29chPuXKa0l7pwYWaHOrPZRhW1APZ+yf+
o1DIUPAjr3nyg/0QJ8yCeZqwTQCDzzsh5fGB7cLz+MH+LnOpakG3aZUI9Ej2LGma9SWZhlEMqZ6z
Fc29mxDaO8HEXFg9L8etU5fpP4fweR5gkVV2UNThiy1grKH02aHt1lEycRoSjO8kdnKjm96WT8EB
slbZAtYy3opIk81jEydiAuDAmmWLIU5Vv7zJSds+MhbkknSTcI5LAEigSnLvkv/4qDgsWdq/dLQM
OOZUPDGJSPH96UP7TLiT5Fqq1p4z14O1OnXugXUkgrDQF7s/L4ZIX9X5PkNnXz9uRAizmv5fbsnH
fD+sZplmnMxJOQBc5/osCPjEU+cxGiMBk9SlCnqvBXIKewSdlL/qs99gihhlw9g+VBcfApbhHyvj
ge3lsiRf+ddnDjxKdmWFPduPAx/kEYJfT5zFHrcf6Fb3id2zG9YIyG5scBLkeKw72tzuI0Gc62WT
V+VqoWIgtud4ri9SUfrcD2+yrte0hXAAGF/lFlHj1we5yVgGjT7lJVGBV/PqQDB+mZG1NoEx5IRc
z2rC6wB7267QHCngKK0KxXQ7fepRmnVXQxBw0uqYWj8DOBGJbJ6cN1cPsOe2lKI9P7BI26feW9PF
TfnSpZ4vJxwkMFR4UZmjk6/fsm/h7l055IhMPbdaUg1UDvEwsBliS+f0SlHwsXDTj3a7/q+4hfmH
+0JGWlj7HWxlfiPwSjA6myNUb90gGRbyNYMLtWyElEcmQ2Yvf2+mGx8SjZxOKRDh8gAPoqaeMPe9
Pwc8w8buGijN3nfF/jzc0L5b0T/HDBn0RgMGMC96RujJiG1WmFJCoBfXzgJMZRu7LvsnZQUhut4t
ROZiLPCd18JS43rJfci3Mw/xrMSsBtlOpbwjc0PfkZba/cvWO+LrV1zQqhBJ1xyszvNgVsIfC+lM
Dpf3VQ55c63gWYVAShttU4yVqoHhRd7e95iNxyQNNTWea2M2zyKwRyTBX+2XCT6dZNrbC1tXpefo
tlbeili+0VqPPKztIz1RmfJAX0HwMfU0BEjh0PPjwp82Yan+dL5fey31bwLQ51GXggcujJYLPTDV
BX2ZoqxrtGZWg2XgMVeLEU371II48rNuGaaXKeSjPmNVjJmevX2IT5CkzwcxoJiKU15q8T+WfYNj
XLSuA2cN/C/tfqWiDMrdRuwpzZjHcAimt6F529U3BpGwBufvw+RaANeLRifkEWd3nF6PHh4V6Joo
99yTdOc4k2VBC1qsnAcMhqRrhPI/ubLOsYgqYdw11Uqj1Y+Da1Fz38c4MMjsE/AVAuiepTJ8BVIq
1P0oR6NpLWYktmBFlVWCv4h98mgfFqcmRo8raDn///bcguTcA3TL9cUm6eswxwD4z6FK5LE1TX59
uNn/2bNCAT81d+3MjK5VstUb1kyPMsxuscTRfp2zB0HuV44qIQeHviSfOF5zMDPg05Tj4A7yRCyf
Qd78V3CK2cI3Rfb4KhFRcKLoMyKcQ5sbBYqR5Xi4iRqdUNcqCkuZ3DUS1wSutKTKovlmUpKAM15x
e8/9dSoK+rvjDTK1rqJsan51kvb7JuYYXs5DF+HbIRCoVwq8MPdwpyIq3V5Cz0YSnwEenWPp4Lrd
EZWvyqzMjdRff4SxkU6anAsXckOh7kA+4naSg0fsBy1/z4Vn0dUxcskzguNtu0HdlFC5vHkX+dNa
VbHce8Iy06CvO0CVykrsbMM0rFCHJ4M2921PgyZVcdYGoPy+1Jt6BLzJ+Y548y6VcIK/NFIytIYm
QX+H0cNfXpDqQdWVBL70oA4ycYooAnfyTxFluWMZ+ieLUsm7j4JMgC0RhDiHkZA2sF+Pl5qoVIF0
3JTM7L9wVB29ejdskIGTUZwn5ko5dXfYntHCcLF1ddApdtnV3Hp/YaYEDvrzsBDF63cdDR/anvJ6
AwPp0qH5HKvmMhx/nZzvxFGoliPgQnpkF3mPF4MJOpkZvHljdJPyB2fbh2hWhMAaUREo3udYbWO0
8jFRWB4jr5yQZE5p018jvYanrdw1UHaNW6yJyCo3gzzWNCZnKKJubEXqAM4WG4HdaZbRJXKl27nF
qUNDdBFCAHX+K9yCGpQTritfpqoKb/iGRUVvuWKWXgtake+LOuTSJTuf7B3tCjf7V2Mzd2WfJJ3H
9c1wjmdk1QUyGEyWJcLe87p7wfaSzQvO4wHqZDMQ1LyNM5hfb3VpNltdc30s8OrU8LnHMPN5xRXK
JAVeGiVpEfBfk8eXjTeK5JowM2a2QPXqyHPRCzozL4GnFHZBYCL0N5IeaHMKRkCfrkH3m2GkGwjM
vdpQewxWx8Byu9P+U31SpyBctb8sVVE1SNr0Nh5aprrdqTOCPn3u9zyYYMfrWocUFdTDff35dZvz
XIsDrmzi5SD2evXLA6ekxOkpLNVMN/+rtJfpNZT7/CtGVymhhM1+Xu6Jn18Xz8l/kKuOBUeB4JQ9
xioUgxANMbeOPzUNqVk4OGnPbDmhCmApdkC7ygQ5Qff70UUFNi+BM/vfcdscxKCSl4m4u1fH8wwJ
GkG27U/vHApDqKWSuTprAEt9dpmPpPlQCWS1ij89TlYH0P7eWJ0fKFkyzkR1w6d6Ocm6W0pWmDeZ
EEDwkjqKtPoKxPZVoWwRDvIYBhY/0ffOvSg/tknJjfzzQSGGLA+K31/hOty78FUuZ8EZeuHtNcD0
lGZjyip5ucCiyYRsALg1jaAoh+dYsA18cnZe/aCGtjX7Q++Vkd5OKXgJb9cqJt0YzTqGVn3sD+5u
ckTuY52zNSLlIDWBVVh51lIbPQh9LtWWAbdvdEjrPaU4GuKd4L09yMOD7sJSVvH9B3weuJpQethI
bJtZkmNilwjM7rsGi3GoC6uCyFbp81EMoo+RejWNhRhah1juIXPn6jyy4nKKQIipQweSHdeB6NoB
KqfCgP5/O0blQENCyaKBdQpKlZze2Jt2rh+QrCUbJbCii/rmgVUHuWZaIQWBjWQBxAy3gRMhEQQx
5hGC7MzIMy6Y8XN+OktVetmAA1zFwQyxvJeTgHRiyZJk0pjroKHz59bcFkTqWk/itMFyg1xbnuMm
x4UmXnDOFNfdwOIal3T6HfJRaR2IccIU9kfGzUUBYFzNCIadq2YLDqWGY6mbIJtdSTBKcZR8pPw4
LdY6mOCaYvIBvfvuwCgz+oDsoMr82AD8O5ZKLK7vNtViDFHwgJWhXFt2wF3daHF3uWUQ7U5LVd9Z
ZraAIHBWSNvIaeeyLwKKUNcuj4SMRxBzQjy+izgOedXhQEWRzrmlfvjsWegC1ZEgLmbZHakrTYpN
oaAdhHZ12na9zpoLXXX/XT/qCKwyMXC1l+wtP50qw0ZsN4eaAcGxDt5zOeO+VSSDw3SAWRdP2sQ6
94gA8wNkLHV4l3XcTXE2rrkIf+AvecgQ/UQSUk+xub4C7yCDMXfRR79g/CSzp1O8x6RA48Y8RfDG
kS8iHPhUiiPt4kZ4lzv1oHKhFHaOULp1in6HShw+hRd1+UBAIvRoVAyMCOWPFSBLu6PfLCUOVJsL
397O0K7tlxEjJEQJyTDtsvIdmJNxM1lgHcKLxXVi9jE3qRdc/AgsO9m8T+HNngtojiOyIG8CGdmO
G1bYjJH/WrYiz1tbZThyOd4wQoakryqAjLbYRFIU2n3Ej8Gib8B5mAOLCMTpIPnBscJmZm9Dm/CB
e9WcbdeVQSTv8/OFhcLXAHrbLfc96FwzTp28HUnusOtWesCmT7nSB2XdDNnXIEpWMKFXhod2Nta1
DIOkM4eU0Vtl7czp1JSOFiNdjT1q4F8XMUKI9EEBlX32Y8lHKdLmkXCckmZK+/hsGyrZMe9Jumor
ETTDdCtocD//LpJvicdVRQ/QCcmAI9ODV4NubNbDU+Iv8wz9ImZCB8lOPWKSWCHhc0su6U9329EO
M7PCbIG1lKkQ11h8ayC9RO+ms4tGWoCLL9QFfsykLuOKeYsEuB+b0DaYqxaKxs+md9kVgmHhAe6h
GFwHZFkPTMKFJKwlY70X1WOKWlna6QoKOg91TeZpglfRoxP2eMQ5d6RGDepAMBi3PQKo79x3r1bW
cnNxE+Y7iJzWgTorNkrsUTsdyGBiKg0FfYZrf2EOZtqvkJ8okHhsWMDweD7QNoo/WQFiPUba+0OF
qxzv+DPj247bnm9myMxuLqjrFrrUUy4MUz4Ie/0lwJ25vlzIb0N2W0+kmqopHG1EK3kpRnuHw/La
VqnMwaojjLM6FftTvE6AxU/7pnasYOt5vooty0jKE1D5xf5E53J+TTJUGS//OBhgzc7X/fntaCRt
CFlrM0I9bJ9JArNMuOAGWIZdN0oIaQotBILKuTysiu2LUQyw0SdwI2sfZ4Y+TqU7N3ePenpfb8x9
v1phELhRSUrGEZft+PhgBYwoILEGA++Fz5eruq/6HFiY80XvPSa7lHDsBm4obLjLKYfnshDeAxOl
uHxdM6PPNXxBflDShUVPoF04JBDeAsSQogU6Mjciiud/Mt+YYnZYnbC8aHcIbp3IJXml8nFON7eg
PC058FVaNFnOIMQr8iausfHRjWYvdElXXEUDxQmjESnO0N/j4Ud+9fTNGpVZDONNr8APgpw97Aay
WIgcYqtk1uAncHwzjrMzA6rlUAfoNETOmIxLSsaMqqpDMQTUiZhr2ijUkCOudb8Mr1W7eqx4ZnNf
B++s3pkVMPa8hlSJkfzdMH7r1SQr27u96KLkH4YOJ3WNpGDdU+XmFq+oSLZAnGW+Q5tPohpW9jbN
qYzU6Yk6vhYMDhCKCX+YfBnvQg8SE8pA0nE5JTWzQPMlAWcaMVdh7Lh2tdBBLlkgDl1Fky/KhDSv
4LyktbeeRCK3qk0ZsWuQu+Vk9vaIpL8yMfFYatjaHJg6T26fZzyoBuCfEO3Dopt1mrY9AVWiW5hj
nDpy0gy9gUK9Po085+yLSFuBPCAC9cfJyEsHBGzlGBgwrUMwXxXJNvwsB+qI+Lw0qOcCwS6RDSsN
oV7A1q6XcLR/XerP3PPb2/ky0EqX1Jpa5hR1FXcnkO5Uev/PDVPIaZ32tEfRV9TGqwpfLyxgEXiP
DqBecAiPvNiGjFwKF1bTAamxFwqXRcBrwfVMkBgTNTnxpxGdhoozrcf/VZZDA7a+moTZbC3c/hv+
M5aIb+fJBPo7c16BCc4dgNVOS55QPXatNyP3nqtpZyZWGj1qfonzmd2znTFUn/IsjR7nHQtnXXnx
+JYWgOPJoau9yrCqGbzNNItEUVPe7fpRrrnZNNbnV4kyszAQ30BLuRUOQ1g4Srbv1ZlistuNKTPY
pTlFC4jgr4QKB+FyECiwMD5WdA6aQ0COOiYNo2J+v+3in2Mc3tNS+Hrc5ZndiNIp+SnxO4r2Nvvg
5Ok3EDz2hj5j084BTLnNUKTpxIvVLp7Ndbahi5z2FZLS52GOpYUefUgI31bik6pMySLgJP2pP1Iw
eHzM1as2QRK3RCTXSIPiv/ENbfK5d4lxhl8awKHX+nLZID/GL0DJRdxWmrcjyx+z2IEhHmZ75l8c
Yytu42fJvGJXhZiv0Znk8rnBoWaSMUETibIla35U21YJxM5jifm8MN5N+htwYSeX7RnU3g+w3k+v
JnZ0VAyX8wffEocTo9sONdz5fQLWxH9ZIOp6tPxdsqpa+Tiq0Gvr6BWolidKZy5LQnD+VSmCPSas
L2FTLYKI4eBm+JnccZ2blYns/k9a8DTPEb0lXzGeUQ5+SmzNW2RFjBEXJyfEputz6tnw2k0fH2gG
FARw6sRrFohViMX/ao0NYaA8kBDa7YJYC9Sq8H4J7rXTceq8YZpB9DJkB4rNy2TMYUC12fdgKH8s
0qwdPRSwdPXxo+SWEZ4RIoPnk3q3t+5p5EVL1I1etPtlngKUHBDfKXb95bcp4kXiVfexLfRQ8X+N
yxTeNWYI5k3TW36S4VrqVZl77t88M4j5wPJpdO+d98Xf+LNzcrUDZr3MzopdSPVhApvJ9GJ4qpIj
aH/DPGMCHzf1l4i7NJ0FXfzsL9CURU4qrHqVKbVr8GzC0fqKByc9aa35vGiIamm7eC9REDaML+DR
2dRD3FvYrujeGhPUdvEwpgpETU1lOFRNYD8oEfcNnCKy2jHt/qkxDM9EF9V/Rq/aPrphdwlyYt6G
yztL9UY0TjzvP+s7s304NHlPd36dVlnw2mXBfQZrqeMszP1Xjq/+yuftCPwi/PGEPvVi5uuSmeaB
+0R+KmEDKaILxriYM77ezF66OVMIc2UzcS/k94RMTOLGctRJpcLRAejbEQDvycCwNh5wPctu37yG
GbZstVf3R26RiwFv7M61B9mjButLBPE5hgZ9JliQ7iZvwme/48DV/WfgPIKrHiAiSaKpgH9FyrV8
GENKePs+V8u1u83aGjemBHJ/47zrm+mst0CEGZB9XzzoxYTFH0a3n4q++tlzDYrNKX8fsmWea+n2
NyemlouyYzKy2IWCwe1Rdk8DUoXWlI5qMQ7kKrnoY8g/iSSnvzAPk4FXFMo0TAdPPBGMVN2xQCmq
eqFTLRcjD102pML/8TQknC3gnmt9gqvFQGIzSml23PpW27ZujzwE5s4eQz9lzmDDHIEGO7LsM0XB
TeW1GJSv3ZFavodW3YEJjpt/ibZvuO09JK2DCw/6V6OTRF7z6EQ3NWawdfBTB0n4ji3+0z6Cx4yC
5vdCtJz2MZDCbLcJIxtovaiqecKchYroRlsB3630Bm/ogxdxkjc52uqfY5McueRGv7ctyejWE7Kd
uSam2u03UOrHog4BfaN2FsfWSUHwdTbHRbZANFUYmCZOLMLn3A9PFHdC9V5RZnoi7node4FxhgAR
6isbHzcdj2E0zAmrzt0qhA9sDdZ79jp4PgY4CDo6yhHC4y2xVbHOLKuOwLvQ+8qxFTYy64I6lXbt
0bkfUv5c7g3DyBOBz2WoFA3j6NnwCnyx/20H9qNdQz4w64ux0g8JjELM0YO7DmP+0AR30WhTTMT8
1FtDD93nMigKveT3X7B6m9tEmNlPtyy5WDrU+vxZSca8NkhTe4izpW9mLRnP0+auQ4zaMpgkK+BU
s3gi3UULZmCvJsFSx+NWnLgguRJM+XX8RHeRE/dxbRYOXHMP9WCEixyvkuFUfVed7YCrN5JRDQ8U
LCq10QPOUsxign7NgFeKFzjVffKVERa/DuPEIjmoW2DR895vKrmpbqgPfYOEnkNPRhGfpzGJNThu
OUUcpRXYj4z7GAS3HBUKwQICXdMucXAVB0VyMHe9Llwlna7iJWyrOVH4qlzVQrFQ+8Rw/AisZ8AC
f+ZeMNfoeTDzqHcWjOFkJPPZ3iaVMj7Vb92EELkftCGH671UATNanqHyRZJJCU0a3hFZovyAlzJj
5i90VK50mnqLwc1wfqfpc+pOPt6CbcFZFIyzjaG8qASS9itHkcg0/3CAwspXdxDRtsHl4BucEwMu
7tX15yWV1LXoYeIW1CrpAUeVuhbkki8diJ4j3ae26JUgNKDTV7B0VtkTJRwzplNtDIcQt7NsjgGT
yjU8unz9ltpVTmDm1hLwFNknk+iiyboQotGQICXPzT5GbvbBdKYctVKuQP/ybipBFwU2msUqk4BL
6nOtzdIKTgNN8TEtuqOSpnG6EmSBfPMvm+KTavSckIWVXTCJbWyRQGQBJYKnNyAbUVBz9yFMtLGd
aXWfQ5v5YBLLDJCEI5jiQrcFlM5yTuplptLSLrvbIinthTaB1a6wNXwKQiOeK31GLpccfhDlqXJL
USJwkNaj58fFn0D/Rf8j3f89+Ni7ZwmxbLgrUaHXrZ98hocJyytGV2WN1rWIXpsaapCsGYe28Yay
sUJW6q45iy+kWsfF+FXTftYbJt2MNZqhWsGpP+WdiYY0QJWeHMpnS3p0c4ylg5uA+IAW7TDkb/yT
iduBir/BSzdDQgecpRidCXUKIoauhtsvPLHZiKu+w3qtvJGam3WQxPhDKxF/fX868tKrl6PWhkSZ
3RQgtZqnQ9e+WF5niMcM55dqfh4co3HnC+nY09cdEBQhqBtbSfL6kOa5mDIEFa62eZRboNE4Cdxu
J+vv6Y5xYj6LOxeY6+Bz361061QIIRV1EiDAV7tFyW9SZUgIcXNuVxUVW5GzvvAbMzdJ5BefaLk0
M5VtZfYo1RKbsESmjWWWJjpQTczHWh9JpJYSl2i0G7ZIyt/v4mpT5paeli0vI3zt9vltNBuEyZy2
qBdDC9Ky3ZeWGGamEm/VLYCoM2agKgc1VNc6l3BiWCnjCNhCmucWMnbZh+M38vz5c4IeJIOzeKuZ
QUFLRDnRg3J62y3sxgrJI9Agysx1b6bx85ggsA+Ul0LD/skRq1m2nxYmNnfIdomJD6Va/v+F469D
NqMscu7YBSjLp9ZdqeYXdtf6Y9qoGM2mSoYpYmDZfIkECXjmSDRfXbW3Zr6Yx8t9ifteM2/fF/Jx
yXN182VeGMzJGhBCexAuUEjX6SY1Mf0HHoqLhQlnerlIMjTRwW7qssbVfsEtyunf/YFMrdCzCCis
93fXAJolkjQooMgjaTRS6Y3D+s3gK0xvZOwZBRdcuPfqymt3O+DdzFGutauDeviF77JzUYzyPrg3
a4hlRwBjI6KCcvN6x6x+Ic5JIrP65wOjCwDRqfbGfSsSvQ0g1EdSfMbKkpQ3qrXnRorUKLChWaYk
cZ8LjldGaGskBU76Ihg+fYcqGj+GGBOshf9IOI1AHQghpGvWQrRtbUrsBYOmbjnYUq7xctLv2sWx
iopNZXuTnYREiR11+UJoti5CRt9ZUzE0NW4M2mUa/bDoJQseJaCgvQ2F3pV5jcYHgJA3r/Osd+6D
H3nozF855hW4qL6sT/eQur8xjg7czTy9Ulj4VUdB/7DnL5BQTkZLnYPR3iq3l3kI8Nric5xKESC8
eALIv8CSL8s6jX/P6nO7qfkMJiVL6HwCc36fpwVbcJolmzLmUQKawNqKKsr53DOcXPr7dIbTZu16
7mFiwQX470ppyJMlfoQRsJ4HQQiNwp/Dqi8zsT/lckTrZNRdsDF9Y8dReTLRU4dRumdXQrJaqog9
w+atZ09e2p1xmXrf/zCcBhUqNSDXvsDPyKQOZ8lpDFEejBublwQ1q64BC/ekgQWuBNWLVVmHBhM7
SKDQX4PweDEpjWzRK8IPzEznfRKwJBfvPvqJ3JQf4blrVq+30it2EKcvaRpIGDPjBCKNvO+vC4l8
v9qUfc1+AK31/8X0UsG9Q0JhfK2McDmvDgeTsnxAMSVZr7HaU/yV7AxCDReWA3mwzB8HG5VZllVb
RSJGrNKOMn7qg9usanacG80FFzE30PySWZJgZABkvsrMUe+PzvhFXhH8J7qn7B15y8IrZJ/VATAD
1i/G7oSQ9X4vIsMijcuZNtElWrouxmw0qAU5qJyov859Tr5wE2sp1ZaDoE4tZAW/25vC6ybRuR8+
jPoIstYNzITQhpAhFnf2CwHWuNNpkCCpYndMTxTl4R8OrFAW5w8Zwkdrf89jHq9bKJnRPeVmWp0S
Q16wrtWEJjxOYDYd9ZY1bJV9j6rbG3ofMBOIJ1JzPYgKFATaVnMd6z6aX1T8jcuffhvBnWNvBYkr
zIaw3hxhJ3kSkyGOsCvdBrphSfzpKWdcLNNVN6CR/7wqQMAzVDraLOJo0C/h/iMxK41mMInh+ohH
LmlfJXHo0MN66I4mxuglPBUS823BhprY8t6i4cIj94hSncc8pvUGmq8UBwkPmZWX0I+zwOxTmlM9
54hK0emu0LxvTunZpq13luqUs8rrlV5Lx2+XI+4iIGbQK126I8UHSPK2DySy4ya72dvSiJMYX8Fx
qvwRl60KUcbva1DRHw+myctSJtdBBgJjJ0HN6XobGRXIXXXQTPCrRD340973TUnRwLvRdNx9EX7Q
lC8DxEno4/6i/KfLMTcP7tNg9m1fYeWXxrW9xpkMCrAiMT/YXWstAOlIOVvyzqgS5M6vHAZOtCYy
iQCBLzKhwGc9tdN6iR+BCctAqUxJPETvuyDC/E4WLs3Y6PcQSmMrv5iLrhLPHEBFIlTXxKfy1PJH
mtzYbBAYEIUls4gLCB4JnoX2N09LcXS35x/wv1ZocYtT50dUZ0enLAG+ca2hLbLzUW9sV+Ih3xz9
eA85DpIO8MKVr2EOO49FM+jg/OV7JeAYOxj93jD6Fp2x/qZ+korsS2g6AeMVzn80ZocyTMJvbxv7
NGwtEgDNr8JTods46jHjl/2/lRXuBoYzEFKQwPfUnAhO/1vuzVFUK7I/elisrXliLpt345nJ0B+m
qV84Gjr7UPHCDgRwGKVH/by2ztpRIbaUSpMmZcSdRTkH/i5clOt4FoWrXCe6DUw56aXzwef38IgL
E5RYkiiPaHAfOzDfbzwo7BkPTynqoYj8ofVpgiB1sy0BoSnz2XrzxHxNb8eJNiM+zGBy29jFfF14
jBy1S8ptthVEVIX5Wqe/0X+035CkcRP+asB4xQxa6l4L9iZLNgMQEIzJujazd/F0Qi+iUQaKN+GT
OaOvjDtsuFdV0CaGl6x2HtpoXByNWyVCXHxHXQZj+hSK32KBrMD+JH7u0GQ0aS3lv8Q0EOwDsSPM
BOrxDC3fZS16lvnyCcaeexGeOKPhAYhUltr/5NxNdA77EohD/Oqjf49xEVO4BtBUUSAGvfkhDcBU
wBTkhHQGjTRYG1OKs1Mx8zyLDRXatpc68kA5OeoI5eZ3u/ptA+jWoEEk7vs8entsUeEovz6fkw6T
nsGKluxA2iR9Fhg6+uxNThlO/RwBidaxl+2LLV3m8icYwESSaJ/rU1w0Wj2hAi65c+e34cEUoTTG
96t0CaIeNEPTTuLOObM4chgeGfxfRStx4heyn9OjsUQOcrDw8FjNlJ/DWcymouQsTrq+PiUDCruB
qYxR99kCFDxGIqWqMNbhMcKj7EldMo32ybtXHP+qoNJ3Cqe94rmx2yls0zcFXAFVrVjgaGoStxnw
5ylRg3qfAyGahG76ZTOQOvL64dZMIJ8I0qga2LkBrsvNAF0104Wh5MOD4mFnQIl7G9GZvKL+LXx5
M7Xrj6oWGc0VoXtopdrKRXYhAziUHM5ivbrekYubdryqjnUjNbVyse7xcXEpfEqFiOuiaRr9TlSi
RiUFgrK36wyJA/NaAU1RPA40bgB0oS5p9KUn5LVT09c4Rt5JJzPJHTElXMA+N8mj4//L3BNa0COl
wgZp2ZYE+KONbsnBAhqHtyimSsIO4ZAi9T+HuFADRTwAYSctCwnQO/8Z/qtvPht2rC7q0L8DhCxs
+211fbWLsAHkblq0AyusP7Vetz0/yrniaRQj3hQoSY2AW57iapUBPwyBcK+BIrkFiHxj1tHMOptv
3T1tt4GqgBAYg+OFYQ+mepDe5lTbRRiyU/wPIgFambC8U29EJ7DDjCzmY6kJmKK9sQtONKsBhm8E
bjwh9EahZXFyO++IJvDhY6IE+0969B4XA3LA8xmrbZhK5/oWnMf9Oi11LXNerjfLDcBLFEBX+UQq
V62QM4rohUXgnlYl5iIyrYTq1Wpjon6YHIKIZj2ItjS7BqGkA5wlF0wLvax+44M4lkwOxhOOR5Hl
jpTNEDuV/zy2lUFlILwO8ioYuouvV5hdxr9xkFm9xyxTucM7X+6usnEVUi4c2Q6YyZgGo+Jhjwyd
HxwN1hwdfKkSAsHDXX+X4LvhNaouLbsfaEhEpBs2pQYeXF6tIcRMGzuBeAgucLWKqnFdALteOJ+f
IG+JEJv1kEpzjkW6dSaGRizPZq6pd0WycvmiLkpjleX8wrGDnuB1l/LkMXG+yvMwtRZ+rnZ+uSBo
H5Y8CktzY1ZwHbvoPlX5O9SpI4e6Pu7n4OnBtN9WOTLHtc+yJJijcnaCPief5Y1o8Vwk4qXyaY8G
uJ1r95RpApcGLQmY03hn+ZumEIji2ZlGgBQ3nNg223Kv7iz2/fMz4dY77pwkWAI9PBp6uA1dIcR9
Ovr9rolOjUaJH58fjXBLlEuafb2w3N1RJJwsCIMIWtZVC5R5NQZvluP3joD3JNYg4/KAaYPhGuve
7MQAJGi0Ld+lvV53z19yM+xlYzPNJX7O1kh3qV9ue3lMBU2BWmmwJp5gptuPtq6y0bTGeaWv7cha
yzh0a6Uu6qWMow7jY3st2ONpnU1SkdBFeU43lhR7m05IBgNA0I/i8YQKIkPnCqzidrKuZhDiEuwv
TRWLnwn/Y1EUMTkZmRp8Eq02BYmk7vsDRrCUdZDofssi7pTGEI+/LHvPzdR40kNik2jiPR9RILyn
v+EL2w149JVQba4IpJz2/pWxW3Gs+7UzvC42qxdaFOLRPzVNh8vf6N564gR92ODHW9Vnef3Ms00W
B0bm2d15YtqXPs4AhTZ0Z4AshI46KfhMoypgsQePwkWhxT8AAQiJR3561hMgNQzmX9nTh/lsa+aI
eB3vd2K7TokcISLwYZhOya8cSTCaM1/hcypz5e5RHKKGCOZ5/72AeU6GyJIOBE1gmrFvqZJ+hppV
T/0oJdNarLbN8RukfPt9mFEUk+5eTCYLsBGfej17ePqhJfZClqCVnHRt5/HTJv8Ji3KHh3P3/VCG
TYVjYwTCtkFTovbjT2xlxWteeafJfrfeGc7/hIzgFUwhtHh77FfqN/5GIYiE3RrD+n+ZdL8lsBY/
MQBEwdpUsBiHOhe/f3nFDvD/FN+SHmEzfOnUbGQ5ejSsuolAMzAjHCrb0YkkzR7a9gsf9U0bL8Vs
2A3Y3joDw3Zl6OOmauKKktebL/aJpSeWqintaG4CI0alJZ1Yb7CC8I43oBny8lqfDHIcXtfYR+RB
6oGxV92+PQZy8mbbh0jTcKq0jtsVxvm3PXcJ4MUiokf6cSVx+/yMSua7PsuFnxORUuxIl/gpJ2Du
sckLvPHTleIMl8snnx2ZDCMJ6HHQ78/zj5mTZpEdIrDrYDRHgdCrA+Rc6L+1i98XlsgD2W09UMII
79XXkECwPxU8EKMLOXvbB/HQ0bSufM4cU3OCvbKX+Zn8lzR5OiYpeJtuDoOIvDgO7cFbASczgUCb
gcLczNQhei7dfFQKeXM3ClzYHfoDzbfYvJIBD6x9NsgqaJib8IBi1XrG12fDSQRgyN0xPJAL+RE9
0xjVDXn+CNMgYmnAZ3T6wyugynidmpN8BNByklXIqQ2w83bsB75VrK4C4CgWu8lUl3gIkMW2swvH
Orouc+E9vWFJtH/isH/lI/cyOBch8K+EhrHO6aQLj1PcUACfQ6j9dOInQm85I198Jwf/moSwTuR3
pv4wrxe+wAhcfZOOivY8hVT2pp+8Tb87DdNM9isgAOWL/4Abo72CwwQZKL1pbHE9RpI3+lTRAu+K
THsAZ+fA85qtd6ETw4lsIXa8kj2N1NqyyyfLMAnT3aodVBSWzb9v7KR0dlQkicev7cMjL47ev556
LFymSDCNiA6gbkGnrJhC6DisYVnQ/cz6uph1L5Ft7X7+xjVK+3hphP5cZGJV/keG33DwhCo3cc8H
4xcxABuXTocRYh/r2ujGaO9MxNKF+1HI6MBKekm4iipDzhuUXxTWdQJmoS2bB2E2UjrfY2B0loME
jPvyRS86zLYYIOzAqshPWvyaugdsEYNEfwRX6g8DSf18qFFG05vWtcrenCrbNlYKaDllJYdUw8fA
M8cBNuFCVSLGYb2sMKejjlu7Zxl76CvU/WM3fgFlPZEHp1Gqwxh0fxPaCxwFGwsGjcPIIGvGMsWa
1LX3oQuLxMeB10y3QQI6m7EizwlbgLxzxKgKtUsd4intmrj6SI4LK3CLmTY62LwOi2rQKUGGJDnT
lvKfF/lmvPDGhlCcdAYKICn7wOwY2yQ8xY4zMiafhQ+QwZg876ySDRymw2KTNQO13/pIWtqo8ezv
X2Iv8DZZR7S/PvZoZ09zlTKUVqW7/6u8GaR/Lu8+D2GS8L8oT2fJu20qRTiAMuISGHkp3tqbGm+0
ZsnDyKuWgGslea8MrFUg2n7Nrq27tL73lrRBbZKBm8YtpNLBbRD14RTad8dwrCHYlpcAkIYw2GXs
aZYhw+RQGTA/xSVlr0BvlGb4Bw4o4MWMEL6OP+KBIavFcu1FtxV+XlLiw8yuOpd/Ak1y+Hl6ZOZj
a84TD7Yjk9SDP22NqhKIIb1lJkv0hL33qqqWWFi0cb+r/q1zjIBJ8HA85zsN4Mf3DxkeKMSJFYWm
bON97mSFiR41wud8Ri/CYOJNVm8RpnUbRonDUkH/hriWHGBEZRjhmxacYv9DE3+28orK4cFCaS7n
BuJOoyqp1sY/y7ClJDp4fT3Mqu0nw1BI31m1RlUMgKzncmYvGeVH3n2YsaQfBpQghjxQCuaNNmew
dCgCUZdYyo5GW0HALScPl2RLQqcnG7A/laryZt4sfi3YMaK2BR89CKJ1Ky/u0Okrr7lD98Wfxiw2
raWslZ+z5XdBV0egJFYx+Iiupp/V0QgDEeSJMBwnkba/Q/gQO7JnnD5+Qgicr3pPRVwDHlU+AD6f
WFSx7WC3ImCpO373E6h98Z+aeyxtm132bG29fg7pQO6XGgFLe8sUlx8Ylmes+pRLbp/As5g3hnsX
a78CdEBy2AUT/SS3Sf2aWIKo8ivcEqShpEHVaOmRfGeDosV4VrRqDA7dCQW/lcdD1dk6juf6pOp0
ninwCsHZ0apKOUrXE4rgF2Odg/3rc46YQUOeq3h+OHmQZL9yWHO0pwSeYAXfslG2TnLU9JV3z7VQ
Y6vbcjsj7QVmhrHx/GFq4A5Xp8Uth3lvv26Vs84Jj0aK+MXnXXY9NrZHcwjB48baK7NSscbW8qgQ
ne8ev99DhhLR5xS+kxJ/q9BgO9hoBGvgAPJjPVz/fBL6PEXuhaPzfM8ejYxdeqpG98D9aV3ASgn4
DKy9ZA3Ezs+4VhhBVmmnMjIKYJDnW9Pp7HRrUK8H+HdEXEgELtrcji2J/GHYq6zZWH7/Jj6d0WRt
Tsc7AipLRsv5+r0ux/jpQ94D8b0eK1rinruqEKIbIcfiiTPP1mhaylszE77eV7u13rgVFU13azQM
Z0T+zHfy3J/ZjE38Q+IdRgFMJI3dmfPj+N7vKU3C4U8WyhPxgz8ILtGJRNqiZAW0V9ajtDcBijoX
qPmR0vPiMhRv0hkPDihadRuYioS2oRrbSuJnFBUjrwFU9v784aWtNTd3VKYKTKrtztbdPQ0YUEiU
4p7+B9VnmxpDxr1EHLJLHkARidaA3gadR7a9hADH++v68z/YQEl1sO2yRgLokPUZBybPn9qxIC0A
6rCnjVjjkDEAC1ZoraqKY7QbKNcdLAhY7ecEcWDtZrWORa8aCC4a5GBMHhgQzYWsuJRyg5J43VD1
cozuSaI+czngFugVMGSbXTagKG0mlZ6bu/SQO8/Wxg7TkmBjcv4bSpipCyhzqK6YyuOdD0HOR9kV
f8Yh7tL1L0fol1tMIhxlnvoyCWge7VbixsjpE4ycdzK9GeYaYClf1X02LWjJydO9KEk7/hfx09Dv
G1JH43mVzF4TXQr5Xq43VVkTW0j4UIrCExqsLwoGIK0W0xqpP32nBMXFM58/kqzfSt0KuQDfTPQz
t5BywKZZH8NeC6+YQrqaGDvFhZs+skO+AVx7tPd0vnWvW0do5gSOiaNcPmROTxzTQiw8JJ7ahROk
f78pWWoPS3+Kt1zuaHWhcTcSE9+/rQbLGiq/VOCKkVVlLcqLQxfMdDHCnlom9CJqfAU9C+IJHBdQ
JOZKyNvNm8k8T+7DiVCNLx5c1WMRcQEvQN5P8cJSVX+3Zj5e7KVOHgkUJXr8RnpdT4Dp6w2z7yDe
HqhXE1jvXIyc5QxQhKFLl/z/Kzw0iXnQr6H8Auh2I6P04ZRUryOoNV++eDVAO2927WWmgZsR9OHR
cglZdJEYU/qrMe9NduGUBfvBqXdrI5zl9CoqLW7prtpcWNAF3ZNQ51NR7cub+WTvlB24A0rxUUxh
O/w3RxxgpxOQAfrl7QRiaWnSOwcgHhcuX5E1ifeaFh8B3HmEwYN/hpOKgMmNazE+gZD3Wa6IyR/8
CR2VdLxxPHMCQlZjU7+psOa8d5NV4CrEJV0FdqRHOSpQj+u3JvkgGVGWI1gflzyb2WBtOTVwN4E6
ocGSx0SGeMFlPoFdr+uCRVw6keJkkWGLf7y8lf3DNzstwLsrJ1yxWV2MrjCGdCTDBEcyOE6WuP0t
KGYjXQRtSTYJ+0wSPLLTQIPW6owrBYp1n9wgl5D1wE+2sU5eSH1BmO/+0Mn09X3d+4nhVJrQzq4O
Bh21hESFS19LG5QNK1wvKY4EHV1CCe2X8RrHz4ZdqTmpIKjli1rEarOWpZTovsVFKPcmd/IgKSGG
Xvhd9XXD83qpVr1pRot+kjuzt9BBO8aiHMqoAVZ+ug495mKQk5ZGJD8gBt4VzQqNfBWuzsouXR9+
ECEpFQ9JMHF/l2Nsvdl7IMze6hQKXnZ3mfTU7KiTAePDm2JSNeyHR2bR2FJeQg99b09odWzIVuT8
Xbez+gE303uxg98SCmupiqJqCxK9Ve7qRHe2WxYGaCDtNPsVw9BBkCTz5bj13LfoxUMKyv4bG+Dj
gQc7u6M7yzRxdYOJNDNnTjO36HjqjmuUe8uHunx5COrRJRT0fwru3N2aqZ2r4fhYu4++QLRtp9oH
akoUSmtbutPBfKcL3YHKft2i4WJvNjva7ik0ZlVnJuCwcuEoSxqDIfvZ4JN50XHdVYdlYpIbs2sq
9GPf2xZxSOx/pLXuFnlypordTp3trBddhzzv9+Ommex3CdMJ4Z5ZoBCHdXS7Ur6bJcxISGjcMFgP
ibxkt+wZk4d+2SkZE7+vosjYLQmamOteau7Detxh/ifc1aYQu9nXcSdZDmiwKt+T/DHtSNCV2Fte
1yd5UQ+3faHzO3TbOZew8cZA+Xobetcu5fsY53SPlrsA2B7et2Sxbzmi7BDpiUqEGRJmemj1Lnx+
yMxf6ACOl5l0W8YGjShrmyFW4DC51CTfCcFqE5LQz3Io2v8zXZSdwY2I1MFbyss3695zBBrDnQUV
DEHCp6mmrF10iB+74NYVGLWrWLTmUcGK5rolWL3zcKs6g3g7ToCOzkPGIzirvAGvYfISynxbL7Kw
80O8lPRYPXgrXapuTVavJ3Dy2j3PdKsijDbZRWiLMOc4vFJV8027VYBNUCIRpZygLZjOnuu6yRjj
ccqb5whAx2TZcMeGmYcaLoczjd0sWlDs5mTL99zaImqOZMx5YSS5aNMR8ekhqU+ryeWYtYXcKAsn
EqSAjRK365FlKxgHaehyH6eGFTtCTjdQboNQgsTBOE0PWDSLsKQaXqzCuS7tWfqLSfUCSkAdwTj4
EhAvguHltDFpI7CEa5wV+mk3gf0HoC6RNtJs3P8FUhf3cwI92iPwHJ5KHMNM2aiHZXjl4ZG++2NU
0qHbeU3lVSb6iSwjatO0pZcAaKVmoD0uVmsvORyVdmQJbJ6sViXAPTnPYmCUBFPDECTJOlNaic0u
vJ9M+3aTZY43tcmzfa89ROge1GIfPgQ04kP5L8lmvZlTUpouiv0hOdKgzYRDCFOiQEeYlBJmCCyZ
u+/CnQvuP2qhFCd1SZlq2+KnUUlMS/2GShbh79C2D2X6MXKt05tHsJsdaRImK1WgXcaniSLAxrfN
WXmdL91B+vXaQoDD469oElqLrrXFaqvC6qzzQNbNI1Jg8W5Oe/kAyF2KtbpEbPG5k78G+x/rHfNB
CSXaSSB4BMoHlxRsJqQHREPd5mAoz956BsVEJI12AbVrRyjVlVYlzwnVgIbRpvL6Z4jRKri3xTrp
RyTc3fg7E9+wcgP++SQPR0t4bkqi6pQgEtWAoBhzupeX9Cvk67P37XmTJBADvQSGopCb08Wnr2LS
FUUw1rtgFtO6E1kJsAmZFn3XsuMl5lIqw4KbrUnI1/spv3K1I3pAZKtJKSw1/V85NQe05LIqO+xe
3isxIUPS9a50jkV2wer0+dVIa1y9G5l3/qgaM5myRzHq23o7lRK/uCFGi/v2zXwfUQDCCZ31W9yC
6tY/aLPtXSzmVQFNPO6aeAFE7sBAeXLroee0uRcCcpn2LiDCS7Wg8AYc9vp9l8t1hpH59x4ODBvG
yZjKcFqilPYYJDZiIlf58ox6/TiRKh0ZPw++SrcLqbWxtPhdnksuhBbDcYeNrThpTvhLbzJCsSBF
AFOOxOLm/rF+dOXEayMMzuDl3wiT+WHRIZPMYzEMMNEzKjMFvBSZeiFj7J11VlgI0X3x8WP3hPEk
l9sjYGNEY+9bI/Ldr+u9//e5fYBenv/MC9s0rCqmQvVv2nxSt97UXcxDNZprMQOwIrmGkbHFf8ue
vKn9lFN97MqI/9stTUsp1wHz0J6zRnDCWDJPAZCa2LexmZJKSVGKsZL6P/VrI9uE8tPjF/yAd2W+
3loZ2zvYJeNrFofVDUX2DlfXeZM45+K4TzypC261Fyzsvd9wkM6avCc6c/742mK7WOGbx4k6478z
Nph7WPaL52ooCWK+DCeVO6xlxuSbY0h6knVwZfsHKyvuau69Voc8Kt1ptgkQRaCDUIwStLb3TGzT
EomF6Rxj576SP+joP1aB3RKqLyc+d5f2cXLM2fl0+b+syeLAuY4RXm41D+41rrpuTZSA5X18bzMa
k3c3zP1UbGzYgYerPNo8HeD8C5q/528YrNeJAsRj2DcQAmnug1L+1dqCkyGXoSQyrWBdwEL05FBP
vyABYTKaLjFPMcskmTLJ1PjCzU6HmEULunnBHGjZrDYfDmby5nF+pdHZozZhQXI1sMOulbUrGqHm
8jtiFE9bg0wnR+yWkJZNzZO9MUV7xWcKwTvnUOdZO+99G5qJmWJokCDKjSLQPUNkLgolOkw93VsU
gijp+JVSOyOlvkf7VUx47+9wSBNVEj01P9sjoZZvesNTYTc9ZaQ160xf2TJkWKyyojWVDJqgY05r
0lwhwTO/7HF3DsHZ0FUTF5RJyzNgUn64hKVYaUjwU9BCEx3Ly9O0ov+nQdQMUrxwGghI+QzsKLm0
EMWX9gAHzABVV7vzqAYEt40x4NOoFeA33yS5Y1d2KfngZJ9opiT95eFLv0sxfpUx7KnBASOIWtlx
yUnB0EP1Pj5XCg5Zpnn+k+JVEbzqrIhbjd4WXvKsxXMlmyLwV0qVlSFeSzOIl3wTkspfF5TfdcMF
g75KYTIN5orDon95XUmq2Jv7ENbdLwFIy+2/vNlLdvGBy/wwRCEzrqkUDfqaljTIahox7hsS4OjT
++4T56BRX58BxI9l7rjmrC3dVr62FJ5GebTJDHsPDFL/CryseGp7+zF2JIqcL0kkT9d9bCpLa/cf
r0LbFV4WS7QYU2H/qFQNmazfitXq1tziTJNvWWOeiRrBC1DeJZYCaT8OSXPtEsyPiJqbcqdFxL0X
5EJtqLPTduqacap/eU1J9B6FJnvNu4KY43Cd05sr7rDCtchooVOjB6eXd4tadVzRxrFanZ2Ow0WE
xRSGeAXOvBwWXsb1Ep4WDki5QzV3qnqNaldkqzEc6I5zAqo0Cw9d9DjL8btiDSmWq0dmed1iJI+M
sw7kOfyZWbwP5K8tMCYIQ86qATsTT7+V/zIdHHuk9Jm3pdI3p8r3iJgzCwgIc6HyrtYe0gWgTqv2
zMTYt9I84g6Qd4tyI8KK6s7M9cFHRxupSo3NEKppctDNoIFvotF2FlRPXivXWO6sUrPLNrwZMXDi
M5ElFZgx9/BE5yD2m8sII1pn6tAIxr+c3UirN3v9QvgFKzt1EziYn6GCSJjgWeazv3ih5msu1+4D
h5VAlQLSUqpjouqTTzpqHrnU8CfrUAqD2m96QCFyUFTTq7MPIRLawLib4S6xZcMwsQb+5ReQTryl
wfk72HHgjwmR/dYJWvHPsRkRlk4jcbHnERuQoZD6ODHlThmbjenDiOqItqWvKJig/SI2XDyqgMP8
LaqIWHb71brYMm4N2UsJRPRCQbqD5KxhVxiWKjTncIfWCI26YqflwMUmlgU0k4eK9IhcBCHPItvP
ZNJEGt/1IJw9iIpbIZLmjAQn0ynomfHD3rH8D3uVsbhc6XQj/h0p/UqbbbzgeeF8Hl/wuno+btOI
qoOOtfwtVjErrhxhNYibssM3YROL2WSHftW4tfrQ8pwZUEbVtIF1+JyKVmFm7d/d9zaa8uWj9Th9
LZCXlz6D8co/hvB/MA5VN8JMtgjUpY/KmQ5DQHLk3CVG3JQhTnNMbLCCcJyB4SCEHDSmgDhGt95u
+V+8cWQVnHBfTG39V4qRsrq17fmR1xvWbFLUe9wcPbT80UdRQFwIwCq7CwUvqgev90vIh9aHkAGI
Tk8PG0inQCSsXWG7ovveJuufxJG7KbrnI6B9CzcqVNXU3cQVXE2FQFMsNXrIGtDssfSV5pEAH4BO
dwFRZYdCdRAruMuBolZZpitt9DbrNtJUh7M0EoKKfhtw1HcFETt9OFUOi+rkRUCeENmncTuuRgIb
FCdn+CTxDI36dVwEC70sEkTSZUCUbDY1zdYirlY2MdfjahMph+c46b5Ukuku8BTkiUrIDhd7UcI8
lJ+zcsWrDYSB1HClfvNXECQjyfKW0Qb8xR4ZOacMuRfRAcQ/oxaH8NRHXdMlPSIIfduqs7HJg4tS
TSAdKGKp1JIg6uDAUzuwWXsKZmXybA7MuSoEc+InmCoPdxlxXjtgHsyU19iwVQq3uDPMewKx+bX4
eulRBgLxYq0Emyc3CKuL83R1GKmQ0f/JaPCDLTxYT2axqUh8Hi79gsS3+x6f91o5ZPldYdTC3Asc
x2rBAu0hIhCdVtTlghrWD2Kzx5k5P+D5nlLRYFDLSmRIG397u7jjaSpjerqmO4zdInFBFA+ps38/
Xfdb6c0Qnk65iTpEkA9A3suKet0T6CAigcW2aIbPEwjYpWG2Yu9M/KPhWdBGUd3sFeT6znDWV8My
9p8kYciqPA5s40cobfvuVZg4kgXXQlfCJmnm0CmBECg8pME8aRxfQSDfM4YTxAOSfHzGcL4o+3Ux
5kuUHOafMpPFEAfMa+aM4eHbFdPcfr5Sye+W37qM2KU+CC/Xjvlvuo5gT96bipxxlkPQ8cnyE1X5
WDfjNJzrACBU+9L2T5dsGnlF6VCrUF2tiJmXlPg9bmgZcnax/CTRONwN724DSquTxrT30SsKHNc4
X7GVBq0U1kO+yryyj90f5di79PGh5fOnRg4QaJnQ7NBBDm53cESMq9iaSLLyilCULnRrURaSsN2q
CdwV5gAkDb7UeGuth1yFNsDUvNzbztksyE/8OsTh+yxEZ2YSJ/+6bzmZiH1ux86RRIOfKAaPrJNu
M2az2Co6RrpQsZ0Jwmck1GMguVhnaUDtf+/jX40Z3huPwaRDG2ahagIhonOTwBgeK9nZPTrCwBDi
yMgn7EU9w3sPsLtoeBqVuK2QOBio2MH03iwIka2nlfHS15nbCOQ8tYv8INr+4G6tSU1yO4jv/U80
Rbt5dWPwspCr8EQ1xQVV3T24I+SKGAjIqKZs/6I01rvD4rsy2Hr9cLdcQeBcmvoSPkZ9rgWC6E0a
nNBwte2AWwB8oRDavgiZ26FWG49nhC8CM6UO8UjV34HVqRetoAR0UARqF0sE4CGDumtMmtUomQIR
w5Oa6yp9q97xoXIa874gIrwIwdVgIlu5zmBE9hJLlmeMlzJ+u0PFmlt4LDgJDH3FGVbhYozxEyrY
SQsutqeBc6dzmIfBymh+/gOCwL/N8KafBXarLhfjhSxyYuPJIFfi7Cf1u6IEVf1qbch7aujRPANK
oSOCFNQi/k0r7iJ5maZfCBpOkGGhD+p7Na/mDTCO+u7kTsEyj/Gj0tBJ2xxtHciiyxhqqTbivNzs
GFBlvHHx7QfiGyhE5I6OxSo7fgjwO0K+SMMy4bJzcjdxTvW8z+oiKEt9b7t4XMnmFDQDC2P6tQmx
1ALuZhQ1eMG9FNdjokxI28/V2xYt6y4bLt4ShqhMH2bVxJ0g7atc63jf+0RtNDvFxHWW2WFlofxJ
7S+OJfvz0QH9b7ttH0L0+sZxEOwUbqdmFGuRZE/askGkMUKr/MKtCoD7LKeuEke8tsea9MixEZh2
il1Np88vlwKDSuPVSk4/VRVLUaYHV1SGdf0HMnm/bEa0gPgUpevwbIjj9RNtmaFQr6Xs/xVfwT9S
Nt6K+syavDe3f3WisSi8OoKcIc8vGmLVme1vDN89zoUJo5fNzVUP1T7WRVVM15X1VwuJYXygR8gh
W5gg/HKI5PBXPhyLuQ9lj4NCMgUmBfdzSdJvjT8TWPdeEwMOeN0CJbLg+Qwt7blwXGW6ebPam/U3
M1L/XmfcKVCywR4T3y9UPN2sgsa9PDqUyac6lRLZKQAJHnvt1/igsa/L+ZCugoytqT8YWfjbCebz
Ke5u0ka4FDfIBTczzXPPct7e87Wq/FcOqyMHjJVwz+z6cU3WQxm1B2pGuSvtnTYda49x9yF27m+U
p/hoLVt9aUDaBpRZY6TVHpU8rUsardbUvJaPxSHG4ZHwZPL3NoAjAz/b79ZzdttRT0lMlouPfWzi
coWiz5Hdv32+P1d4T4DHj5fEnPZjAxkNMGsYv4INbX7uJ8E0XV6MUTrkkOEux89lf83D5flTOyd8
AyVaGhxeellScz6JwvBkhvwVQbUWaLBRowlK1I7NN9wx/NFUr6N+6q5ryhv3n/U8D06NgurTxZff
0tbCi02mGwlToyi+wrbvpeocMN1WLmqelTflzS30asuVmj2fCnrGNqxyQgnUzHrcMSvTQUuvPEFP
UhirlOoQ0NH6GIZI4CUbLj782b1x+/5lW6BiewkvXO/38YPPq9lRF+dWYYKr2YWZV934tHqCsM2A
Rt3m29VnAtyEQjitDTTbrHFPgjcemr1MUHXTspJFKt20nozVX/9wq3NZEQ2WI8nOqKBQz2Vke/gA
uSPzbpsxobEFSBWE2NCMcM7dFVon9+1lJ6OmblEaFO4CR7ENtPZ00MRuUKJrAHLwYU/IP9vFsuH9
L4Iw7U3bKYz0w66izpIPwgEY9zuoc1sauNJ09IHnO/x7yb4hgVP5s0DP2RygHUmQH0IT12qF6akC
7M0rnWlgRmDOLfPq9KwbqfY5/ORtk8PzUp6XLkkbThIGAF4EmRFvKNRKYynaxPlfRAxn26jHyc6Z
6FKO08avM/xsbvtFMCYo9nwP5/RK7e1+Z+wC+NWmpZWWNdM/dswKQDSstokYeSVg3PkXslN6uq8w
JZsJnD1cfNwt/0IVrqqloSuwOpcxfl0Tf2Ajr8azsO6waAGf5Unl/BD5Oi/7CeiY98ozg1DCnd2n
DQ6Exqy+LPAHi3b9xP1KdJoDO80QKH+JgqEM3sQVNoEPOeLMdA4EE7IOwTfDAInmtOJUlL/xhisp
ikQwO53O64YlNsZB3KSTl5oCBRad9c3Hvy+2beazjNI12igaE6LrX3tpN8iaDNfjOldEYdI3u5Bp
kvLUTumLwif2tUrnpU2Q8vmJdHPJ2eE6d3CnDA7Jju1evZU8ZArziFxVmxSm5/OmwdIxfydd+/Y3
y4yJBXoYkcYoriOUJ4+onJ5A4N5ddLM3lPefJ24iYBPf2BuIUHofotMBjsK9TkdftsYpIeacksdN
+h6KCdegR2r1VZREOZrghFRU8Ren+tHnkiUW9qoCyimLI0rLTffUIm5qmp+yy1Qd3UFaXqXLu7XQ
eOG2aajPYwQyA7+EE7FZPTR6aVxQVtUxyTj2idYTumo+TmEwlaOk3jiGMqx1iJVOg6Os7iM9sQhl
xoP0GZQJaXbmF2wg6P4tbt7wlavVYrQWL8Ykxczd/xfyRFH+oXJJ41/WII9d+x4px48JEGMRfkTX
b1n7wBBHQCoJoL3prX3MyiV4KkanR+9f9dY5/gPtYbpvWPO04EG/prL6UHBE0cxpbjkXsfSTkNGG
dN4eQMSFa0k5eLFggmjN3HEgPKfl2d9cofx8f3CqXfzZmpo8DslazESBKw7jgTK+4AIamTd/Ccgw
t/yW1tLn4nVw2WvXRX5cEZ9nj85SRyQBVfpoCmMwu5gkc5PbcOEPOgxbTvulGE1qtuhbEDcI97JY
QdngFeCfVXH6WCcenPLlj+0315FWHY3Rpc86NhX6rmUMDTsz/ijTu+W1QusM9MrPzMjVbAaQrVcJ
WaV5WIacFQkiCDtcAfODcLkLziCPPbIXqxDaSTZKB05lK07x0Rifks/dkLiBmtdMVQxTwG4vCyCL
csd77/vOY0pyf/33qUIy9rt1wSAuAWvUXxbsFh5cxLFvYQa1q1Ey5863XlI7XJdwCtG7/CQE7cbU
7grpEHeeOB2Wxg7+LkoUQvRda9l2BXn57Imp6uAShpS2H+ZjQRGeMxA0fsDEMknO1f7GQofFckeW
uWPkFlrMSnSedKBMEHhOSik1RCDPE/g6pMnksS37yet3wdLn6M1t+YxuSOKASqpYIt48d+Qbwj/0
VZrGd+ahe1Ud8H5DDynN+ctCBQlRuj5RmyD9m35JAuhhNO/fw2W9o8vrvyDjpjZqfPdRgH9mg7qU
GQGUwNLwa8tObb+1ZMScJDeDP47usg6rkUQHdOBrol7AAghvMLBd8wmquhEpr8bKyCWAMhkK1CM7
r8/cG/JXZVfNkbpICOMeEmBXepWuT+bV/SSc7qughlpiVGaKd/Ok6HEHI6Rj7sd3uvuxonioLUzI
FaCr0+cqNvilO92GqePw+4IsXgT63TXWdSFN1w4SBEd30apnnouavVl51sLhRamBAyvIoyi+HyYc
BmDdSKyKM956hav3YYuCuO6ckFpUhhDYd252hp94SK0kQfjjXFYmJdJCV8NqS7ibnvLvVAs/vbJQ
pqHEXLUPSOqVOWEmeL+2QSvrZsDHnJjYRXsAGfPpMgiJr2KS66F5i2c+ZoaYXq3KIUukHdSXyFUi
BUxyrM9x65/viQkO7lkHAdn7+8ftPWOIrbRD0WeyAU2U8ZCv1c2XgdXHy+Kdy+FhxEqxApbq/96E
QAn7D41nEvFjreM5CY4HJYtX3uBRAIqt1G/S5Jgl+8FxCrU+TqjOIvRB2pPGgpoy8b8tnBNmP5ga
dOywyw1Z10gQ4AiS2xcKhbYJVre7agE5v7wzLkwkQ0WqkVBNoT3puBrtAvTn3Lh62Zv6iTcvRRKr
8n5zhoflIT0ayE3oCKkYtH8fuJT4OtbRauTh6k8vwwmTXE7hCItd0c1JAERJMbWgxhl2cK0LCy14
KAe9bmQ8S5f/J6RfXd0lwBVVedDzx7D/lZUg2nDAFnIiXIJF9VFDvjip8e4kcpAY1GkLzhyqjFxD
YW0VdhKk4KMug+VEnhvFbFZbeXfSSImdKs+k+qamjZD2D7ziJAPzsVCP3xjPDwY7QALrVe3MZoFz
qlIRPByDSKUTAmP2INih3ySumUcgAVkjvRaRfasxm1ZBbahcRuioyfsWWj9vLHqlA/w2W9ib7/VC
suHTB5pJPtFwuknT1IaATAs3idoe6/cQEDCqAQPX9WF84m72x0t6oZ00D5O4xqxbt0MetcDlTfAv
scBxBzGD3hsYdofKpUXgCNvKtpYZHuCQUVRTULjzJ8759/T0rCKvY+rInvrdqhqn3/2T3y2Jtak4
dAgfMzjkPo3WRvKvhI8HNZpjjREDnAkXh+m3RaFzSjacTTp9chfjCuSyAK/D+djWFRzesQyUUtSc
AE8PNMsgD0hwWdfgepi/7K13ZHnuh98+d15fBV7yyOhgeSwkFkanCKlmDivuUk2bSaeG3yHlLLcC
eWJlOoYIpDrmTk+sxfhL6oOCQDb7VFtgLhTxAMMvFyr/XoteiF9xHcv6PcHNRJrj/Dc5oYaH1m/L
MxQ3KG7aDAcPfgDfT8rpUkU0Znj5sFYF8kmnGZ2V/0WviEI6cdV8nenpEDsQk7jJo7cIp3tfYdyi
kfdNyEfNRSDNEjapI5UREJwytJxHZe2j8UrjqeDyFME/MqBzxUQNWD0K/uVADSGHDx1kzCY2ohR6
wNaBRVMShtet63cwxxMPXU7ngRBrACqOTR9/A+4Db2HvkdMGSOrgCVYZYJOL234CCju+l/UWMbgW
8WwwFMLloYsbP34hK4QMjeEeNgukHMFcjueHJgJJuKNgNY80sccsC7MjWMk9NltHMcZV5UJudN7U
TWVuHMb0Yw/NYLoFh0WlV56gHcM2Dq7myqM8oSRje/PbtRjmuPnt4O3xIzVPGzuJ2Fq65K+RJead
e2+7Q6pAXHVLZr6PsFqPrVERqgJLpknqYsIc1AGPXnO8vtd78BnL0Yi5T7o8F9pa76hDTwGHf/Za
L0NeCSkCJ1StOKMD5IouUKIdRFpoJq3N5LwKfYkflz4q6ZGmKBlOmonBxGaGBWFUMcetTkjYMjj+
uRgZK45hU+UcoWRmd4q7UsicFt4AXzVjKIUu7YBTYJZbeHugbi0qAa/YyJkpG6poVFSfi9wzemGG
A26qVPUQWNMvE6JtGjxP86qKrMVAWM2BExLseGzLazJkEqP8DTextcA8pYI1o53zL5QKQLkZBO5T
e//eVmnfTbFBs1tj2i5ebP6ItW14KwKU7DMykCl4DwtdJRpEVcvEMby6UeF5ulSuv2yrBs2Z4oez
FLqgG3vrtf9h6Qq7TJ4FNHwGL7Quf9QTgofnKulPVHSL7+OWcE/JkAb8mymIjo1zYrCGX+J8UdI2
iNctHwSuK9VLcrcV3/XPfNY1uh4uG1DgdKHr4+swuY7Nhy8/GP8qX53p2tSD1yyCn2/+vPxh9j/a
2wLQl/7MBSRi91Ieu3aolqiuQr9ht+lEBTQvJymc9XC40BTelo26x1NXxm2hepQyJfxNrkkM/ddP
McoXHL0sEt0jF851+MEewuLs6IKPocmFu4dmsmVkitItFVe1vShD14jTYc0vuee5Z2EW0KIj4brh
/d5YoS5rbbapGfIumn0rpMZeVD+K2BkG5G4HsuplG26pqjwl6Hu2C3U1x3gJBQ8q4xStW9M68bpW
LkxkT6oSdU9EaECoVPRTmEo7sI9ANSV3JsKkia89QiyZCYnah0VgME/Hk2liYCvF5p0XTPhQeUcX
la6OxS2sosiwkoCafiJ7l+rauEveLuOuk+tZNI2BGGY/IfSwD2MwfV4yYH0O8pAZtHvmRe16lu8r
g1l6TBhEnPTVS8bHl1ikCkm/VWnk+Ib8ZrBKXHrMdwyl48aRs0lL5IKK3FIrFJyqBGppumc+cXlY
vwt8LvtcFnEUwW2kGVDtYe+mo14ZdyNqb9fzna68kivf17oc6hnSH+NQqI2XnpojwSzDmtJZFJSQ
7FAzTl5Nj0Gxakxdt9CYsCHTCWJ83Rxe1mXs1RnKuEs989LAlYvrPubSNhyNgEdrA/geyKGKvOMe
P8km1Tjoey984ZNwT2yb641vWP9ELTiSG4htD67GEztK4M2NanHv3W9ccRxNK4ZY+VmCMNNShJTP
88dCaP30rE34FLWfkGkTxNB7nZUuysMkaiQLEzL2sFc9LvsY6kzlHqfB7yApUJD0sBwFOlKu/YYX
AfQhlySfHPQFL1HZprLrHAzVAauu+Y1QbvECdRkm+RVHeAI/ScVKHwWAZGzlrhb8axv+lhyOzPKb
+QL4TIZZBoFbeQ5vjE0SWSk0My7w9FCLVT+xAix6VnQhAV/QTPumDP+KAJuxU8zXaWAAQ7zM7Uat
uQEdOdJgsql4ELUXLcD2G7FIj4hV1K1tBuQ1lRuHGjMLDYhKTMgvMA6kGnDPsFFPoTk1UyEyZ54P
iWfkoZHnnJPAykiYwfFxzBYpBow/eYNThho5eWM8QL7KtL1qWT/xtDVLpiB8s+hPAIUjHe4yaasv
SAbksI0HwT6IrxV5MEabLDy8XM1sjLwBis1mV6fwpNemyYzpeE0skX+Tr0hv4UHXS7wbLgXeePh/
s75LjMHrunRZd54fIWZeIUc59lX6H6/B3CjtnC3raZramFB50LCuDmN3N6TdGrxZbrT4uocO5ozo
3J2/zt4Qz83oJzZv8CDkxtL7Klnd5Ed2JaZJGnwLP6WawRnxf9eW5hIlPMFxgAFpSBiiTYBvv9im
5K3oqFBRdyC5iZfUtMNv0RTpHXeWzigwSc8tvQiS29uMjrrzFGpT7K1NcAma0E0feA43GZtlky5a
hWRzg8NqchC5RTyEdy+7g6hu9pHSEtqTos6gvVOAW+Fz5K01/yYdle6Q1oKQvJ/+sdnxZyHXdzdB
IQSlm5QhOQoJfArQKMdEJqQd02ZOZK+/LgcFi0jZOUewjl5uJObsPY37094EsETQPEHTXlSqU52O
yO2Wu9tnzEIhg2G0VWHDtN5/h6hmoX3gigQmfuYnXod7yJ0F+eUyHt8/gxwHKSV4Gq2KoCGS9w1Z
dtlXb1kxAHL7UiehwA4m0SYYWFP6MWu4MeC3UnBvWDSS5nDReFYShQ38/WYI5+VvufSB9+dYPSEu
RNxRxlhjt2nwvWAJG+UH8REsSHMJAjsguHyt/IwFrF+B4qvOhwrw0wrFkCkRZfiHyuYzOic5T/ur
Vz+mzV5ZcMZYE9AP7HXPnPkWT/3m8UBommgdJYhNMnNzQdBFsOuiWYZG6cULi94+yF9Bkx9CvNGU
P91cW8ZIkkpWm24+Wckk3VeWfgwSfMGZ1nltGg3bL99N5sCYivip4mQPEhZuAxaEvap3XiCjlEnn
hyiIBhwMM/ZRrv41f/oHSsMkDKzCFSKt+D8xZPVfMcByn5keAURiQUG4PKExOZr8qbjWUnbDejIi
ANTomN+3nFUx2wRDOeu23dVwEDt34EXuonC0jdP0FoamdzSAr+I0hW4j7ilWOnCNA+L15/t4/ziI
lLNFtp6sdDdOo/FEAT0ziatB/Vnj3tDis2BaEYlsooD5M4gweYFPdRk7UTG7FFTWrCUGa6l+hagL
sHMd6P5O4LsGUoeMJvgpqa8rOvZwrZ07DxZzhPrPbgxElAt8NNJcU7xUDLcTPjsJzFyiLocUGZRj
/ZfiZkr+SkNufrj4vLrE6bKkLY7BRXVr0vIU6TjiaanMMhRJ5Fka5XlbVoJMJY8Sk/zVv+XUjUUp
V0W7aH0KPOmr6B5XWrIIf1VqfIqU9qJB7oy2FAlfLCbYK85dgueCX59Shbe/vqfg8RjKM09WZzYD
UGLOEqiW7DLVJBq04+4RVDa5KjVRs1OisyWCkkta0O2PNY+H4hdztMjDRFIAVvbOsSnFl/cEoetB
nRRTHZdEhDfX9IpaKs8B16Kc80RKH6A5SkXoI3xBYj6b6HuN3j8Bqq9DHMZVA118iOvrBWIfOtRA
3d7LM3oY/TWN6AKByTfFZaO07GW+g5/wHlkb+T64Vcb+aOAqHX3YL0/kHhJVKN3/CYFjBw2+axjV
gW2lMAcK+xan/wqBIl+9eCOZ6KySUKbGxP5iRCmKdwD/ooz9T34EjSh5QohDHaOgGfUf7pimENmT
grN7QaRlusK4/wnZ8TXw34INJdUTNtvUBJOmk356PnKdwfA4f7rFaxvf8mewDfLz/ONSCb+ONf3i
haUidttLMQSpmbaqgHgrmx/aiNkbdd8Z5nAWfQAfQWm/4mAAkQ75r3OdPyJjS8Nj75goRodV2rlR
FLhImVnTdPgU6LZfZwAHz0wlxh3/xwiTvJU542Ae46NhMkGddjGGc6P/qg4CzDwVFFpdlHPnIlCB
kaqbFsDO9ENVAN0fbz5IrNGu7FtyaCqE/FdZpXFYkV2je6nPaVs5X1+rrFwzDec8CnlXtUimYUta
ULkdSe4KkldIC6BiqrNvpnbjO1XvyiRvOJmuDacRPhRdNHaD2IGpXjRb84Zc2K9/WFtrKa2Lg9jw
SnBQXRakuPcGw77rP6/LD/5ivtpKBSq8MCSXzoH59JrtkWxPud3DAZMAORxt6JCTs8ar4ja5sE+m
S1FxA6EhENTV0fOE6ZR7LipzyjvR4dTap6M//8a6TUsgw9SYGpLSQds2m0O+VzAlIDU3J4LGLVmx
vDyCjrkfLvHsYFzZOOMsGfcT104Hftt2VVbry3LKdxOjfrNwMLCsoi8nJoDaGcCcstvCh0K2QmCg
dbMSRwovpNfSpawYPax+riPdlxS75rqZyQljcQa5K8rREQaZAqOiqObpuyeFVqt3khZFdMwjSo5B
WKYf5TXTQ7Y9uNk/Q79jQ+eH6Jm7HKT1Q9y3K/eHToHRWXKQLF0goddcst7IGnArOMzQavbU2E9F
qNzQYn3pg02MvMwN4camAkqtNxGuqSx7XJ67V3F0ui081PbMjoDt2YCfsQFSC7o4/31MXpdzb2bU
kwNo/nG+kL1/bGCFY4H1dkpEKiTNgGCXW0pY3dERcOu4X801VR5Nf4Py6eT4BGLrkn0xmBFadhuv
ao/W1I9a6inCS6tLyICWZyAWk6J9CS2elMCa9RROLRsI7H1OqSdMJtQC256LSXjHZVZ4aOwHiBRC
eQReKNVrAdcXNiAXhJ2Q+ar1wrrAt537/aGML451eqeJ1M8MkR+7axvOORuwWLkVzKt8eNv802TT
HHyhsKS6cwZSCgI/BHt/0Sxastj5vsLpKfpPPxBSdRoQ8LpdM1Jv43drxTx9ICjMULYDsxni0iTk
oupVHLeG4AEerzuY/femZAIfNwtE5GrgtXhhxDIWsQnQunIHDAYJzrNkhK+/s2mzav40vO0Nkzeu
mUtss3emrbH+MF0rJixcKisGxR6U9JaC8L0RW8eSNd4jXgzpPGEOCjm5flCUxsKARP5GTxWl3RO4
zBmVpUJri0FLjbWKLjgzD001rSToHpdb+EFi3+mKbrZp6fM8jnwBbMcKNZQTyxX6z32OGjyS7yoy
5uR4KGPZ8EtjAhLlTd2O89JwSpgPg4bx21IG0qNcKKg3X1NDUJa23idp9u3ofBzmjo7SSDgGdMX4
qAV0EL+QubvZwH3zzilhLtl6IEhEynjPR3I2b+ZiM8dqx6NMwMbcm32TSyhs5CKkCzU3MaLXY1A1
AJqstryPxXmQGIxLsDSB0Hc3TfkONLOv/AKi4+r8/N29XiuzjOBeTNW7K4Tj2+bkA/91kPkXm5SI
kf2HA1f+wCUjn9a9S+Crq6kM5rIvxk3ql/5e08iR8X3RlBicGDec+nu2cfPJHa+IHxs8gNEZnXkg
WF0vc97jo6Dqmf9vpCyfwSEz7vTmW0EG91MZTK4T8IbZ558fpJumTptHkI/BswO0/u2j6OT+WMat
fVXVoEBSTtGi8VRhZPIKrs7a1YxhD6w+iNvzLFw/77vkx/tAzO5aVHvwgbMkG6+h4jSODxnS3PG9
c0/F3oEkgV01brySJLNWIfuLtdyaMfNU6rZs+uYNiJo5EOJdi1Bknzd7KQv+Lm5YBT/TXbKc77wQ
gqdiL6doMpBu2uGhy5Qs8huaQZGkuMW7cAMnu7QWEN3WYxy0364NRc+p44G4yKVgClHqD9Czcdko
56ofDSBqoBlPwYT9HpvcxqNzbxgPdRUiR4QNQw19T27FJqnYmbdbEav07TECCRaQfhdKviCc5VhI
vMyk1k5Bka0yATgU/M0RiA9THHaGsx/O2BXgtbPqPm4nlV4hQoQPpM7WZyb6b35hUhCY5kYNc8DN
t+c8Ysdfh6tkVrCqsPSsr/y51GuVSTfXAlPtivPf19SNbWxAh7wRzBhdcjGG+MoxZ/pZTINBroci
R75cOW9q+ds0uVUdw+q2qn482gTn0D9YkmEAbAVUJFoRI/rTjiUw+7xU7uF1kzRRVpAYM18w/Uct
y3hM+K+fMsuVMzEOhm45HtcKNaew2akcY5XCcVGfSdE/e2S4j21PP4M71uODgMpWgPeGpjLfvG1k
KfbzjZDgZFDHFgLhoZx63zdeA5wdHP50EYCvTQgNnQgB9NnBNNmqv4ptI0EcUY7hYgYSAOWSjuWp
zEiq2cDEi6v48HjAPZnN1wbZ4v2+2USQfBAjFec24KzdZQo6tLROxakV65BWoVVoA463H6JNcZWY
4KEF5tADng4BI23IusGVIfDKCH4xbL5cnEhk6ev2Ohyplfn9kWhIutUb4OU+nHGhfDGCF7pSQ4XV
BB1UQooiYQ7zH3tiUyhWGqvc4YXPxG8EECShhL+PkcLhyoNAJwV4FdeawbO/581cqHa8Q/hR6dSG
qRCxD3Lu/OB2Zzqxk88/n3n5rnGQcgKjbyo31IFJ8y+Fn9mt6mj1q+nNp6RSV3PJgx9k91UAqE5R
79NlfmXDuKEB0WA2WLl+KLS+SX65KRQbK/3xpUYv4u3JqTS4EJxTpLa/mqdfz6+kSx189sIBbSL8
R3tRAZSboqjCG7LBdDbMjIigkqPE+uK7Lld/NNnb0uEb0p7oe1qieaq3RsF1Nv7X2ii3gq6XscmD
anaoaI+Lv7JZxTwrQBUBFzazvHSbgTNl+pNIon78PA3dXkAOjqvX/8f3+25BUmEQcs2ZcDeM0oY4
Nw+NzHxX4yoL9WxoEugPR7MawrTFuKQ/PRzTs8KF5hxxGt7rrnVBADDVJIwnQnvBp/AKQxVpCZQQ
/4NTIr1pr9Mde3TMOQAX28EZyAsUDtkspwCrQAPmSlxw/VMkz42ynJetFy5jcEcv+Do18Iw2GUc5
/LMvm5SMhDm4OK6ckU/IQnisl9OqJxKQ9ES9KqLuPnE3CA6i1N/2EmJLbpY+UwiZXkUqY/OxHBFF
GdvL8Hqpdb+JbfWlIZa6omFOPHbCKtxxmXm79VCs2qJRoKl4h2vMG/YJGC6psJMLRXmrpdqQEjZa
WtWEcS6tDTSRGyG86CphFCLeX5SzqVHQ36GWCtOcCPZglQH8vo8Jx6Z2GBT7PWX7AMssveLFcjEx
pAFlzW7KKae8wBrH0ZgD7CpTNWDucpq3C9egCpRRqU02hynSjczsas99/ENHwY/K6HyGuyDScyEd
ZwxwnBVb6q1gN/orDkN+adjG4kOyx0//uq/0WC/U7Oo9YyJYK6/pGCOvuLM1mWBumVlOsRKX0Oss
/N5lPWfcovgLvgiCTARbeE55r+IyhAap93DUwKc/wTSnfFst2D2J9TznRsLnpdbG0neC4wy7YTxj
NsNm02DLTyq/AkNuRqgR5hqzx3XraSKWlDTfa2Z3Fx9N4YB7NLjiXtyKk8Ptp7RbYMc23D8m+rVm
tJ4PbvA91mkw3tiqKCVdhAGrN6YuxGdYfXBY0kIYlAluLZHfiJIqyXGziuD3HhvRol+A0U5pPHdo
g2E8BUZctoeQ0/f2P0p7A6VZUtPZzd8XplJOC/yo8cjmmt/JtKvkaRFcUHx+tKZLoCHvFS0swh7o
VgsA79Mnzwyj5dj1x/e05e9y5g4RoVQhz5JfQHBCFR244PoBHWRh3CzKW28soV9u7pSAIPl52for
8d1TwlO066gi3gU4Euyxvtt3zTrTMuR82lIXZPy5HN+oZwhsXhvPqbs0WmaNr3oC+H226dBYGZzw
BD1/mEVqnXK9yW3jRaT2B3v/0qJKPICiooh1oF+9z7l6vV1cogWToEKQoFESQoBbDlMtnMyYmScP
Ss51ces+gtia64LlaDAuCXXu8TyiI19TGCmPE2nbjKrUa2evN4be31djNVVvfIsE8fU6c2cD9iLL
a0AgH+fWODll7Jy7hQP4jI+DUa1AGBsBb+qcfo6eY+c+0yHo38B7PokldhlXyLcAjAMYdjP5UaSV
BGNeZIBZw1trbraYZl7uPtiFg7OasMmo+ew/ZekXA489bZ/LV2y7xlXU10k1vICpGv1R+go15fAf
PK9VNepTTUK1jpjKWbaQWumTbwBJXoxYvEVwQofCDefNP26dpmeSMKAh2bLD+8MY9v7HarI+jRB7
go4r5LukBH1n69lHWvZ1uHT8MWi14j5d4zzZuBFlpz7pbwrBVK5Uz82fM7eDsJYFB3a7FRvTbymB
fAoOuNHnoiAZ60MWfyMf/rpIu2wLNrq39fQj+X3568cr4SRCumXGA5dcUfceRI0jNEbsZM21TL5c
q0cMk6kFLcEl9HDtUrHPn0Va58Y5rqBE6rJavQDjoNJqJ6aA9S2xmnW0uDlBiXbFPDdtLSSGTHME
Di1/Qd36Ut9GVZDUDZUJzqtC/n/TOLkLC5ghYQDQRFS3Ai3qcudB7ci/RkIRNj+jXFg+vfzKy8pp
6FWDw/FkFWYHwZ+5xHYge5S+jkritCKYs4s6bgvKq022veLKEHRCBK9zOFzjY/At9LFkvg2b37hb
DWSOKzTqRAlPQR1KUCuYxBeNPqxKMTSgNtPhaANjZjPuvH8Gv+9g5HFamyAnseUt+JmS/+sBdPCj
fB4YJKbi6enqlNnnuTEDrniSyA7UoEidoYEbSSSViKZdAB4JJrVT9GGxVPzfEBFUH+J4hCiTy2eg
MaDQqqQURZAIQs56DvkrkAibs/goU5UCC7s6mBPs6mGSRbQAEfaLebG2G4DQgZepGSUa205scHJH
SkZQvHYsrw4es8WOB2auUnseLCo25ASVuEqTlp6a4hX2DYSUru6kKz+BahT91RpbSiOQQ1J13LYc
dwDzQ+pPfNi8oqubX9gU7O3QULf9O2rMnaAjfX/gtsS3O9KUy4zr0op06NIGgZ3ZSYdRZZMIvwku
x1g05uGs2tRuH1T1mDOIJ/2NWZi69UixTyEkYz7nhrOPb19n2hocT3M5JNzqmcE16n38EiD8IFkg
xaVCrDahxvm9nDsJ+qKrOwgbhjESQWWm+BxgRciycUHtXDGvteqJ8RxP/pb05vSwkigzqfzqGcef
0TuQ18Ztj6OGcXQeIBP+g9f6RlN6+5FxD8ZaNNjH77eSXIgZxQzDMyN2g4Fi4ccwlZXNdAKDgFKE
ilJuyJj1/8NE9zNHS8DUFhvdK62oxfl3iGo1wVTgDJW9/Sd21hhth/1m1KwGoEuH6SdWsOwDtYhi
lOXlYi24qd+QY7bl90+fd9KTqEHFySnk7nWg/KykD1ei5f9RcYLIMEEGmg8AMMoebuDOQKuEGhs1
74DkGOJx2DGlLe/wLXcqc2ysjeN6QhHUaygE7oySvvH71mp8FpCOqtTv5cfdgOr5GGwZO8iQCOKQ
nQv/XHDbcC5VQOscdF8cne0B/JliJ0xptwe8c/EibCInLYZQ+zlz/neMrOD5gim40kgE8J59lNrF
oAbQoCALoUJjyGgm5xKNAhy/xgGEQcF1wavaBF2e76bfIkrtX1r8YFw6MvLgeOp1CTpu6OmnBtQh
yTKxCX45R+Ps8hqkBUil0KA5NnPLuUYE2Y56Ny+aQExRpQa1VSwe0WzDBJvYsSp2/Yzp3mE2BUjB
bNcWsCLn+Pk2hCZbyOis02BNXfuzHbS0AcJstpv97bAGNszkNNqiWDuGK8ZA3pYBqTTBdcbVE9EY
5ZM4F7NxuU8vhlu/GGUyWnfOKqjMSTj04Llm9axWecVUMe9/5Hv2eZXMSAsyIADbzPkBpxiqgQIj
DkEmCly0xZNjtccLseOJw3qxeM/JsH/kIOIBAksJkGZfsFTvc6ynpMLkBlb8lmok3llEisJ2rr3a
xywNaQuTxuJNNp7KpkbUpFRNMdJMVqDNHgaGZ/z9EXBzWER4/U2/YitNapunsFqmD2vMVpPksMZp
+wadcjHvV5U4JHPboV9K477ZGYMJWE2BHcLyaW3msIUgmg8QVbA3N/G+FW+viGWSOM6FPB4owyBO
gyF+MINIj75c3ixqc2LXPp7rwE2M2thYbEcpV6+QkSmulQrijva8vj4xSMVA/5CeyKTwHCdV73g3
jWUwYfYfZEwIMutRk7PjOtZi0XAAMgVnmlds00YAjGUbfltnTSVCXqjh04eXfpsQrwRFV68r/f7F
lVRkbvvpj4DI2KNnYGZ1wRWCJQUmktlSiYaK9Ar//Q6a+H68zgGvwIC6JENEBrbvZrcgMJXQVWul
tELvynyFUw+3jn6EaYpVINogf40rUhoWd+DhEv0eJQC7N+TBjT1ZWwtj7N7nubV28YBqqjjutaEH
6vmei8c9Zx89SwFabN4iOKtiaou2bQkdOrjYE9v4gCEC6Us8/vcsxPXqNZodCxpuIkj3dyReFsEB
6Wm3bIzRkrQRs6OXRc7Nk3yTe3Fn4DKSugLNdzID2pHp0IOqNJcTXjYOkvusVyYkRUnH1jUQBIfQ
E4TG0WYlZJs96jDgtZ8uaMdTm3q6nCW/ynkele3ustrBYeh3Ovu/rQY+6pzX55xEg1uaxBUzJRFA
Xypr2nWLnPtnKzkdgGyVG4zfpokFXgbg9PPQHH7F9TXKOs8vMUxi5eK3vG+jWfy5WEn6AeiGAEWP
XIdtHHXRAxXCR1Z2uX6BVaYkLcCczOpkYDquvYNGGRk/8X61F0bh9RxVeRkCxBqx4cVNSKjvP0tA
FI7lo3Cv1LBsc36aH/K2VDpEIGApZGOK57qRv+K7LOqjCPYLdeJolH9d6SmMsJaWOaeMEH08pFKx
vpryvjN/aguorS9pqmXhmvRdYUwyHVoV98GQnnawWft2ZVPdlUJOR14BeF9WCHPRXNjDxFFRoqWr
pvjDVcgSprLwBVRhG+FdtazWKBISZgwvxbnQhnHuAXR5BI8feuhwyITU4H9LhZm5V549CHn1RDwj
BYZY08CMlQamQfxP1wFxspdwatmqtjVWdS2YJiobmjg1sBvjmMWUhi64LHCkiWEC4+jAi+0bPks8
282U+D1jL35nggZ4/nYeDfae1T9wSIBROUD4YHyzdFhcdQzTkbzRNXdafDcumcGOzaHLewN9OTv2
545KMgNgS0A5FCeNelMdgNNdxPA/p2RE0H8iZg/xf+rGnOkUufChJKtcIf1hnbiaQJ/pLRd989fK
YNkf98R1rj9QxFVbMEFsObZVd/J94mOUM50zszNlzxKaHR5sdmhdzTkdxe9x7OThSErTurMjDlNi
FHHSamr7pCrs6L60Wp2Esf0BAC9Xv6Mg2GduwcE8DMFps9V2m9HwDxqdPfkkx5XkJx2b5m1p8zdK
FW/HBzMjbnp1MLJ7n5EDvnsTMLcV1v8IE6l9ootESZR/AM5LQRl722Gk6ZlCKlaLb/Le91Bk2jy5
HqC2tqbp91+HoNGcTj8qGxcVJfPGpYYp7Lx6G/JGWCbzSb92e9gZN7XKpVqw7S1HH524I65x/pID
ArNMNBRPOW0FCCgxVE38MslvjxKrdrODHw6ItxyYvND4KGphAKaa3Qazj8BKfQrkb1mO9s3pkeJR
3D2wjIPJgI4g+X6vMtr2I0Qx0rpqGmPDse0IlREAk5Q2NnkmhQaxTvoJk0XZI4SPu8xn/DHpveLa
UKXj55PioZ9F4BgKdqcC6zgg+qoTBrAgNrBP8k7AT0qowwCtJJBoNDV9PTi0voplbdQNwIL3WHiZ
vPA/i4SKG03vNThEA4T20w2qBDWxSxo86zLLhagzsdsHMjoqBMtP3SIZxA/y0BdPDfRP4egP5aGa
jl2lF/P6UNZZscxSe3zG7mf5wNRpvtF46fdMoOcXvrgISFc9dn44Y1r3IqyMknrttOsKvDZUg+4m
KOwkLV4i0jFMP/AfQ2KwQyzcrGM5h38yV1wuQvZJVaPfjycqVNusswCR6ddDu2aK/ig12iu9ixHc
u1rBX8W+u4RKVn+33tfhg/fl2817ihuPNLW4lG3DnYm6/xmegVAF5/j7OGhzsQKI9iKvtTn3M9ys
k4fFmXLSKg1t7c/U0XritJu7wOcnGt8OtzaeyQFmrLEJ7g5EdLNQvic0rjZ1Qb3GoIy3mbjmXOoJ
/9uYq1qW323Dv+p/11OrjosXMPcIL1FjXfMai+ljCY+plPgYo69LKpscFIEtA8U0QtEV8/AmlJtR
R2Z4DKuSCj/t+nC0sLlhWsJzQShzbjBes3nfXXTv8xYHkIKMndhs30dwP1oRrFVHUV5gp+9fqjXl
VUmsZvGbmrJeAma34tOgCvyCwbcwFV/raHwbEyQ0JXv0lbDaaI2CmjttiLSTk6y7wcDBXHK1QY/n
eC5nfFqoDLsW21HdDBqskVyFgMcRl/M16wI4vacljMw2o9jzw6msq1WCjuO2cBlJK0vpIXIZPIU6
+kzYm/kc+RNqSLT6vvSs8Z2J9RjLM116BWcTEoxr0FzAPed0frAXBsJuuAZZChspREuZKmoNSLCj
07Ks16H7+9frPspeB3dBMgctfdv6fN0XycM3sV2AOxV9B4otUh9/3n1jfuyy00caML+fMPbYZoZz
6VxhVttrbJSARaGbMIiRqOgATG7TueHY4NAjwZ0YqnTuhdv9F4xTvnrqBBOexvG3YuNv8q1VaF+9
8qb4SXjBvo3SCz7ZBXhKxOWFbUyyIwgshcUsC1KPjPYK20aTGZ3BEggzir+58cHUa9rYrMXaB2ml
u4QZ4TI0vNp6sPgJ3Cx36DgddSPAemNk461WLtjm3jJMI3P+G/Px6nRY6nW5CKVTXTDSVL3ckJhG
4dcI1iydQPXL0vUiOMY7TLWKvKuY2EaQ3hKQsAQKD8XamNJw/LgftolFWw/peiePQLHR20QstImr
hqqw5COaO67u2TWaEzdoJ3Hlpi0p3JThjM/5+9NFJfpNxFkThoqRUq1NMqq+sNwElwfjyA9sRapc
fVFzPBphpQ4rJTBRw198Bl9Ff8wOG7mP2vSTwpxYrtYMsjotxWMjwMtWxkdfqoBNiSOFcEg2FOC+
eYrpmdXqRzhNqUVz/cDKVPsNFd1B1I8B6yqI09wnxVg3b5OEHMPCEH2TGFj1URMc9zE7eaXqHUZX
EPmbQyIsQaSjxN+dEdRDUlWco6abA9k9wRm8mDsFpGVdWowmQ9ldSMQwSVSmMjzI80S0BUa58Vce
isg2DJOSJtviNFwLk9uiCmaRtprddMmxIGFOlYGRe+G00fkOFvyjX+rpBwszAgTKhHgF1zYYtSYp
otsQF3E5OvxGFG5ffSdw+rH2EZbDqT9uS3QJFCSHqbf13LlMvePiUel5eHPA92uKsuUjRiLHDG3A
skiZOO0kbLFad2uvHdAnvrikIeyuMybULbu0FyX+r9GbHE2oIA7lI+tsTdpSsCbi5/eJPEe+7rZo
rp99mjnxJJpOdy5NTooz4V5y/tZfSSxjt3h1NiACtrMkFUvLfDJHWK5GEHXmHNl0Cymx7CtYWA0Z
nzYsdDZl/LW7ETkbFf8PH3kOB8UfqPoWWUKb57Ik42pTLbq1bZj6h9UyUzGLFe8Ks1bEPs+y1yFW
5Lsvfs7pJERKDdYusAh/fHIFJVtIE7Z5oL6NV2dJxkJU4gOZVs8qyYrUWVCy9yRcxwg71Ct0Hapc
wO33cEsBozsmtugzvKbWQsMkfqYHlbEGsSnz5fnjk2jNaJDv0t/295LR0QS04bGl71EQ6cGB2K4R
2fLBRBLpPCvFaslb2hPvPg74UvC/0psQGl9ctBuvTP/I3xYBMQu+22OV1jWAjpTPsNyemYkHjCcD
q7TMOmASMZ51S/TVZJBB7BaLYfH/UCQhHEWaUQo8bBFTBrao16+RhWxpcVyIU5kIwuKYUUHku7WS
3bTB2QtG46n1c/AXjEADgLOVbYgeVtVy9nRsAEgVC6e5Rhdla1xelJpYZEJiwgM5OOkrDO1U5abd
sJuWjMCXfGvS+lLOcLeMpwKB+vH5uJI78JyqsS2EwnODkd8D5L9JVYEz2kVpoqzIIL4H9hJ6nuuo
2BBluBKe37/FvQJ5vFvGOo5JINv7h9YF3eyxYgppJ2yPW748ahGsXzIOx4GQDMPwTvSqv/NTO693
Gl4BvmOV/5NUWgUqSevSCFEAXBFgIRSUwtiGhKKCyJXVlxDjCj6Fn50PlW6uUyMIjpeRqY8zx6o7
3upEE/Fvw/Bbb8NBCUM9UrTygZuYJGVk5h3suMVSrmDJQFbkgjwq100g51VwNIF1PwdYgUS2Zzh2
k3xCW02ik5u+BBSCOn5IYqwebtDna7lDRYzEXNddT4f7HlnkQWgeDzOT2ZjwBt47p4KLVoeYtkT7
FJmmaVMMlmSp7vQc/tAN3PmTPov5eg7IQTZkf2hH+ZpIChG6C7XneSi6H4FUAWLbqZKs+hwkyVHP
1oLwk7cD0wk+Z7KvtmPFXILnJZyK2oAfbl86Z7PPnOfHkygutZoreOQl1S6psJNm7289dwh+xjgJ
yT8jDs2J0YZmWuWuyriq2W/D+Wu8rGdkJOHaU9vUpoJDfpD1SuKEDHhwNZwn9IJ7aYhhkwGAygeL
KQ3QvYXvvjns6kxbaTK/AxectGBcleTVJZ9+C6V0Q6RUgq3cWLEMMTFCR/RP7JXjvULF5FsVR1E3
PvBLufvwL5KBmA7FSerAPnWMyeaG06tgJ+xGxLB85pTuGy4rZI2vwrpcmCOvkJeqlyIPE0cHBdRC
PM6sxrEoqjEgaVH8Kiyl7etL70c2rm+V9k5AlXLwZXQhu9sSpPQnLV8+j0wXAVqxOPV0qpjr5FBk
LxEZHyWoY5Agq0u3yorBsT9mD8O7SxfMOStFWYhNXLAGehP85sW95POyI+Ett6a0Upj5Tlf82BI+
6D/xQc1SySNK4ofho2VSMJj5LZ3vPZCHptQbW+8YHGifIV9BoFgAMNsv36UoXY9apQZmgengKSBV
Qp05assM64xOGwuQ2bZm5llbhWzl+OYHj0T+5Dehm5S3RpJzkM+vXYFKuqU8w44KurXqC6gy7WU9
T6fXRZ98ogzfPTx2LNSOSw82coQ1Aw8aH/bAQOFeU6qJybZkJhja3v5UEPUX2lraTEZ98SqooC8Q
Lt7mqWLu/jluUTIcX+kbK1puj+yZgYUp/K8OCJfzbE06aHxhuawtf2lyAWnk0Rh+qr0PanluwxRL
XlWDj6Y7DLa7B2XV0uOYQiEjBoTcbCm+NK3A17IVX8kSH4wnXj09LlhB31iiVUM/N52CpcdV2GEZ
fnXyKGlGqlew7qJQ94IZcMhLK8llToI8nuyPNf/Bpg5pfdOni11u3eWv0ndbI2anpqb6hrgjINYc
m/POMghZSjBYm8swNKKS3a6f93b08cFGR0jEO3dPWjKbw9IfTUbiDV27BcYjbxKuMw0UJMo2G2bE
XQsQhIn8hZtNQb3DVv6YHjFmgI561tWErsytfVOZCHDtpAQ6nsRPClZ4bogm+SLhEtZ9usU7+JhD
0qro7G8P7P10SCrnl+VJOCRS86Xmtc+W90w65W3OdRqwfCLTCr2WOORki1c0PaGrvQxu/G6C1k+b
fpt8RUPHZfOpfE5a+ICdAIvgbE7CXZUdlpxcdWI0YzbDgTW9CPqjn80vTI1nOt4Sf/Cde/PnDTiX
x0q/+wnajvcuuHiV7lEJVnOnpAL9p/CBdNxejgZgPO/yIgLNtRHAGFo78fy182un6gEkK/PybqMF
ddyuD58qQa4DexxhhgZD8hg2zG2FxoZH9drW/kfqmLdzJXGctgBjlx5qTkaL1rlFh+HCRorjQft5
4hwj+bHtlKy8HQDmV8BeUHAhOW/gytfGR5PLiBzKPyJRcL8Ybf9iLC+T1v7IedF/4ktRXnpTQK9R
oDST9UnPFnZLbJkZR18ImmwP7iOtKFoPel0lgvbJJCFt6asdeGhQucOcOum1E01Ve0TvuGoyn53A
2qi0aqfBv2BOhFNtU3ZEt00jNjX6PmG3KYeePUvB+WfTViUG6ZxcowENNy4yRYHJplRrIosBTGOy
nevV8ESDpAomMlfElZMST02jt4yqWavOtsvAXOl+Xj5Fvsp1LW6Wp0OSjafVuU48ZMWJB0I5zqSR
/LMzMTfbaC5gTKzqPQXpfJu3CYH2YBfTujHWnmRk4LA40F8lSVVG7DdXGJTX5f/i0aFdDdA3U2i/
sY7466CI13OSycLYD7HbxW7pXMBe3aHMaRA1yHFMnF1cZ1dm8jA0mEI2xBrjkjFzrYvkYGE3OHRb
jnvbJH3n01KBJUWPdGtAXrn8VKmHJ+P1JtrTibGGqLGi09YiFrdjVoTbiwKqgZ8IOoc4kmaiUftu
Zvj1sVHq1HO5QJ/Uzsbr9IEsAv02yAQRuygQkiSdu9izI33ByxL+WL/kZBc/3PrjRYU2Icg6n5N5
MY918QorBRUWYQGrxJFXQ76NKOG4jt5r+pbM461Tfznp0y7yaVxf689fDDKMMj/PwloHb+jxyKW8
qtCPpVOCvqHV7atMlSgUFdc7f9K5GwfHsQVe1bpytVIwTCERlFziy+58yK1hMrzJZ0JKkv03zosJ
9ENK6xhyh37t7n0mvlQ50hR0cgQaO9vfbcSNAW5IXJWWbj461R6sRaV1/wOS+0PjJlNn+8RKoCF0
NzOJtX38s1naSJMKvFZvJRpcItHd/HU5JQPhyDS0WV0R7f+TU//wRuJF6fFl5ZHq1AoZgv72p865
rfgFpKkVeVSx8rRHPCIUZxqqaS8AQduKb4iGACIG9rhckbA8AnuvtJSc/y9HKRMYSURjT2esbjE5
ZYMVTlz40HMFLAu3yO+XVpiE5itEtGuyFaFoZ0/hQBk13Vt7XECWUu1kFfQkKqqnn+z/grbDuJmd
hH677ros7zSmUSfmLVPACPyGWg6WeQbk0QnSmByvQuyVjFIC5rChkEx1Fg03ZqXEGt7x1xRvhkmY
uTzUVuwGeoWbTUbTDr+P2UUB9GCktOaAmjgkW9wA7tfRcyPCZLfELHtgfusUn9+b7WWreTQXXyyi
JyCQ0uX1q1wzgY/lJyQ67lelUdyn+CSw0dRf0mNOCUvjFN/hK4cJX0bIUqXQeUjF1xv2thrvRock
bBRxw63QUF6u5R1MFNGI9qbE6BFuHkGcxQ1Sbwce7SbwMY3JdjpDEXrLc48ZTNwuqkOq9cCql9nu
YRz2ebvKKSTY16X+50coCYs1OqZOlbmXxy+pTtbCp9qJk5CseP0DYawsinQDsEh4OYcdPGlP7C4q
QA5EYmUlpyVKr3ZYSOzX6qo0fIMbeLxhohdj64PMptAsyyW8B7go5WoDN5iwFGTVI53ABqgsyUA9
B2lAt00CnppXa7bwjGPbH+HrNQ/faUlzp+IBJxrYekfTQ0iSGrDOMgxORc6aYFMHPsXFR4gCNiTY
8wOQPGCJqnuMASJEyyjUGBF3LwsvLBFtkH7FM9U9BupgibccTV/Jikm3UCIqfw2C5ga6SLYak8Hy
6Gsx22djpf0hfMIpDXWjBE04ENmwvo9DZtxPL5XBORi3HwJ7SyElalE4SMZRpP8WSiKVd7xSVY4R
iVTLY7Fw4CF62IYqf4mjcLY2ux7XPzrC2YjnkOi2W8ZTbq9KQbzOBBrNo7KqXY4QC0ttWO5YcykD
f4sS63t+VojKcL6zSqnAt2rerA39CGC4SojfCUv4V7+yqHcfkcwnxAo6t4UiDex8TyW+FfDbs7+X
BNQXEffvB8Rve5oX09AcBqs0gikM1gDwwtGLIWklCGTm1DEv+bmc6G/mgbm4xgiaeQjcSGmc/Zub
tfzB23hcK4P2d1Qqn6t5FjidZa+uzPSVysZdTgyf4WG7PfkgeHLrGJeIpvncyQQdIi2RIyC93n5a
NP1tIxNXeB5cetM6oWlAIwBdtsav3NDozeRL15EGak+InyNCSA5jwC2u+HoYyto01D0IhKBa4Xo1
0IG6mldV1Me7x+jLiUmDzoboyVyiWfeo6RpuDLez8+5sjlhejKUT/74hJyASyh9iqt25R0fCfb5c
/oebjTzXTiQq2JXqwgh4+fWL+CwtKCSVZxiWkizOvysBkAFODFiRZVkT/BIZQtlLBK2m0ofgCV67
x6lkDhiOuTY49HpHrvFYz15XgDVOrlE8ZoXdeR1QcK1p+5XAWi4RVrY98S8z3m6LbAHXJ1G0wb+y
hX/OBSWNwhrLkP7mCD27rxnnwUkBCBvd8KM/TWZ1MoM4EoL6ZrWvwtMcN7a7+PAZIWb4mau645Ex
Tr9rsdlVspEp1cw17bovR9m6ZUKju+4ey3LlCFaeubKVwGkxM/Gtaik0Kqi2uePp8Aece4KBKFtc
46PTfeMZJpG5RoiJT25SY1jw6vYI9XPjmVvuqxGKkcA428kmvifMbvG5xNDJU2174TT3wsDw6xsE
B1J3SCxyzQVT0vmyQk5UV26DjEJVYO8vH7RXUL8pAHSOY2JYlzdB258gcVHGTQniuv3xoVONRYvz
s6L3miwF/x+7xIavkfyG29H/8QM/Nsin4f8PIJMP4qgmAVtYNiSJ3hq5ADxEWmG86fJIXL1b1gqp
fPO3yl46v/OVFo42+BzQhilAEmaecsAXiWVFvviuFhyc+CgiUlcE/cK8eXZyyc/GKYmLYCrZGOia
9JNm6Kg4xNdB5s/cJmUku22Gwamnq5eIyIH/xpX2HsGRO3tOkwfAW6pUafOS/EUKwoc4dtvqzdvd
2vMDdO9T9X4iTClp4n99Yx3xb9TCgH1Keb8i+HqX17+JtJoIuq65zCGwB3Us6OAPdhMLjHsfJMZm
UNY0LoPQ38jq/A8SrgoCfsMt0cuoqt2uVIdYvdbGDNj7Q9SBkTezuWnFSdZe3B07tZ+T+nKepAsq
UCmSc1o1pMKxZxrrX7JY3imjQuYzuRBQdbJcQ+sLyd5Aqe5MeCsLu9BAWwZealLPGrfjeBCV85si
BkgT1fuSvwYHHL95RFypzNJ30diiN2Np6a8PKaGsbYombZjvkhS/Vzrg6I4zPnUxAearU9fdbbJC
TRv7uwLaEJW1hPB0VVtD/O2UFi3gp8KXzfDdCQSw2B6x2KRm2pyrky6l9JNt2JH0oPKwn3KvQ1cp
tnddBgDsLnDHlagTAauaGD9qrLBH/eo0kOHkWPN2nyLaFFCqXIt8jwdrHibndcu6YU2A8cXxK22a
vUOQmHa80e+R+PL8hEQzsUXygWGy3dcMBpvYyn9T241oZ3AK7Onk4RpDnbxoTOrOJ145xVN7O3pt
UNVOfjr7uqtYPq9CFcdqrltsW5/9jpMkgJNIm/iKEiCP0Kja+iFYcXSnEjFGd2eYrSyX0UpylFBu
x5wf0xu7ynSfBwddTicMqnk4TzNsfExClRTfjW/1Mosk4/ZaDxMBplcCZQB6xcTN0jzSBywjFKU/
KlOmQTWWMzuJ32bh8yloqA3xU0TSwwiX3FqLuub9jQD84BqNMpExIdnFQXzCmL+65xv3AMTGoQJb
irReLDuPwh2GyWWximzzoBDxsl7vmWwVu7vMxdvuW5Q83axOYlV0Ls1mS0lig0uEjrf0rYplb6Qh
d26BjlLkWt31wI3iPdUZKX5u6Mc9WFv3AcS0h3pjEBIgY2QuCt+iAi10bPZa4PddMGummHEYeCaP
kVin7UqUBotowq13Cr36oQn32H2TbvzgWIyVxtTNc/Qh6Rl8EhQvtr5Cdj3r01WCInCFQS+LwIHK
NaptlXQ1by6SJoOTC7us6wzEIZzih61SSLLzGfdELovCqz8Snah6gtR0jgjs4E9KqSOhzj1S4tPC
/rZH85wsLERehBV6gAwcZFocVhicV3C3w3nDnhN0ZMt55lRxZfY5xjoLvawZzythKEu34BpEmFKe
0uPX4UYIC8FoyI/UKMK3wHINh6++Nc/k8ivvzlXxB5RBCSD5fzSJgvbynNmUW7wtUMPYtLpmtHP8
LO7owkPMBATRYqmyna7ScgONZEeG5APwWWr37gAbQ9t3j+Ta7MsiN+F9ugfpCOkUNsljSlfh/Wps
oAZkAJaPSvZwvVNobnEB8fn3FXLY1hdxxZie/L3+AWK4IyxbmEhIwBpjaCmnqBXe63SHtvbxldIq
4gxMdiFQtbfrgv2/dLclzbWRUrG9WIcwwvzSiH/3BpO76c+zIv3iAW9l9UbMiHCUJIVIQvG7bitS
NFn7ql7ZSPoqlGiDjn0LS+rfk4v/eFdk64z3NvWzlpuBMinuTUNCb8FQm4yJOM5nvwcU/nt3biHi
Foq1OwGqk56ODqLTxESeWYaSqrHblnHTPeRdMfWR0NTobzBVnqmHc8q9GM2V+Bgi1YfTadHawQ1a
nFNCmHB+O5+lDsJK1SJE9XWdxRE/75qqVmAf9YtJk8gm3vnWYaF6q9qoIJlDlWSTFUn6dbT2PjTv
kpvYz5RevxM+Za4YXFp8KMZqew2rXzGdOcD72bKRu9P9HR2YRuFyrSb9XFOLEAQY84ib0FG7xh1M
oyumDEPAZX0WlvRLmdTAagmiGARF3l/+O7xTFowK9VDr+dkcXpv+7MZMbgGUiOj589CXBB0WUuuU
cFnyltxRg4srr7pbFJOqKrTPxlKijbu51zvrxsqfC7zreAGTgQtYB4jGhynLzGcx/mTDpNC8D6Ql
a/m+XsC4uPntc65Du5ZYuAbbWkYuS2wK+R3SnKDqSZiDEJ1HTw1e2+anCztQA9lIa3bHSD+zWOdd
KudPPievV3c+sCqju9D5n+KDBpeqI5juExshjPis6g+gLn8o/rod5MBcFxph4/r4KsoI2RxyDPkp
b2O8SQo6g8SvDJMv5jwB427vnJNHljCF4pV7TwN2NECP5BPMp7zL4xf+QlIQerxNIvLavyAvU7eM
g+mIpqUJCShXDCgc5OEdosXdd3xr5Jvu+MGLxiKkAjlXL0bUgorSNvnRfFb6n284/aPjWouHdlVv
wQv+haICgnLXYUd8y+sd89p73WSU8QcGzyLs8eGHcGbLqP7A/QJI1NlzvfgWTSm/WWSBhzx3K/3K
/n0EVT29TVZ0Ynpr+FT/dSmCRYJ9xK2TOiMC4IQNXrRfNOQ3aav+DO3rjPj+nBxGM/z+88ikMfZP
TRkJMMGi09ky+NqquxW3RKoUE0XbQFhITmLmH5yaMZd0v0bDm19/9sQkg0Qav16Vf/sJiTpMzUgE
UTNJck05SHIyAyVwM+fbzmxsMReLltHkrWRW8yMemu68aFuJhgsOJrv7xYNtDAcPw8u1JZZqFtQo
37J/omgzjV+KxBpAGMUDK2gTNc9S6ju9YoRWd7yp9SOyTkBsVfhH9/NNLnS7H+9p/f01/yUBh9fv
l/5ADuRDfiRJCmM++KtT+qNRzsMLBjkyh+qBETXElgsM5GwbiT0q+GX7XxvviCI9WcPsi2tFswG0
g0iUbEB/FNvY52x/X29RJIRkEh2MhTqJnYDF5SYnbX+9n3QzQhBTKqyNGnDYseh1QTbQru+21p4I
P74DbaU5jCM8pObykLWqQFk1+TNyV2o2Zqb23wJ9QY6CeHSnuUZ9po6f+PDdl0EeV7LyXJJFUxv/
8tNrN8aPebZfJKVwBFWAX0pUjl2Xvv4zo1gEaFv5o3tq1bpKWfPXElEqMM5dvHWOVtbjVYPB5bqY
YMDuOb0PSpoTd492SkCwzT3XPBBr34ZaR/4vO9QleStyf/4yAVhEREQf9UzILj0jXesZyU3wYHX+
BWMACMPea2z2S+Wc+feQ5kv9ualyr9YuYlPkSMcYvGKpojuL5D4vn4SqFYAmoMAbOKoR5PePHGPx
XY3GRNf4rTdxy941qVXaaDDfSL4hj7YZiyaPaxKQr8vpeRc8qw4W0JY3WGt5bnIcFgsICm93RDin
NH9lqSe8ZWHoeA/V9mvFTtM3VENYkwpn3vGg2lAwUJCwDmmrTu5PzN4qAXbQujh3P02nL5WB3jON
8ynQ9C1vNb0iG01tnKbqKyyoaSFSIj/71sJTqrejy73k+iugzjWYBs+S+sXJATd2EUiuCir0FhDX
K7TnVYE0N2P0EeUCSmG9H7zWe90E6pu8O+Efp2myv5xLE2KN8n2OM5PqEKuXn37BcFbapnfcfT76
gijpGByJc+gZlgDxz6BO4N4IeOXaH7SLPw9a+kDvJlKsEeCuci/z00Vu7aDYAbCab9biEquERNdV
/fLqz05PLs76jyBrunYWGEvjYmdaQxrFuB23VFSP/ic/FOWptvmTaruvOiDqzPC3vcIh/dZy1ln+
h8YFEC2dCVdnEYIjcmZDvMgtwYW7cJJpqlHVLgA28R0Wtu+NyIXHV1xXfGK2TMy+7gIEmGQbzH4e
UvoRkWgfzzECwRsVCDEPRcm/Tz5HBglw2IZcyq8NOI3YHh84Rg1hLI8xp0Kx7zHAOm65KxTbToUL
F8RMTyGWx8kxaYpnC3KAzMEzGebRKBNmSBpXwTvVktX9fDs69J+YMuOEc4Y4IiQe6KiI5CB4GWDy
YmMRDMUc5eTBbvZ6x0oToVH4IMjcMduNs7UsSwItGawY9FmNo+W0f/Kup0ijMe8OwwLdIx3DN/dr
Y0CCaoenks0c+OuzwLnGt6ZCMr9978HtONSHjmWUjye5LRfsOZ/oU/MduH5K0263s978jD3KvZbr
vV7pzeN7jkrKY8isT+2rt0bOASguPyymL30Rwqh1UWIgyf4hbwAYqxc8tF9Xzyw8nIhnNnulwS89
8HqVi65AFpEB6nx/HeWSEFpXQIkEqxtNbamBP+XnUwjUHR9fdVX6PigNe4Slq/kA7xTR+L0kaz6o
15xdyk7lt1fWQar7hbgU1QaoGe7EVgUrTzZciPcfXOjPtCp7N2xqJsnOMu57ea/7OLIzMn3bCeqM
5EReJxfRY2I7BwWKbLEWT2knl+LLlopzhGO2HYhrMA8eJ+qwitlLTbllVzAcQxqkHPusgQbZIra1
Bu2Xv5KHOwnO8Rt2U22yGNCSz3gtLHXqnEKEGq1RD8KQ5EaIhCt9XMwLU3WNI+AWcJ77zTdGfaI7
j0NMFDOJni6zDVd2QyXJGOtiPY+r2EOyB/vcE0MWAMNkTvZQSqD7XPaazB7Zm0DUcN/7/GjZB0hT
IQyBlx/Zjt21ys0sPbsIyQ586ghyci+FdX5W49cvWM4mbyJoubnnkhFEj+rUEoS37GbtiXOjJDcX
rQP5H8zw/R7rog4butuCimr8zgdITs+AgC6eD/KjK8pAwk6K25VsLtf2L3J2+CpHRh3MEeo43jso
OVdWBc1lKcmo2v6U6xJX+seWAxEFjs91oW1soY7OEn9G7FbxAP/3v7XxupfrpbW6UfD+J1sioiLa
9/mWXnY78LNLgmBDt7Mss3rWHmL73jiejw6Rop7il5T2D/+/6wtldFFAxq5WAAt86N9ZY5daCiTH
FmP414dWD56s0nWSuPgxuCrVL9uVtHuV7+guTvLUQ4x2rXtG2AbmRjd2JZMcTeqIVqDDrsSHLBfO
q8jt5YVG66BrWkrxYY4UJQoOQPHFU2MAVxLSRzirdMGQDONHeJ2TcDVCzH3i76RwhGMBURDT4SAt
moOWGzzH4AFKy85Wv/NIX4iiIaxdxFp6B/q5SppNBUUSXPZT6UOjqgkQ5f+SBZ4EdFlSsLPEiu9t
YtMV0PWnJoDMdQKBtBtOHX+lBwt39leKjhl6ZFSDsMP8YmK5eJQixpTpIQu66lEVwfuskAeyrefp
uvlCFkJFYMmIYyHVUzrcSyAQ/Be6ianHR+mva+lSp/SxQidF8O5F2cfybRi2oCjPXeNgndoEQ7Jh
8AfrwlaadCu3SkArZ/wnnLBCeondicOJXqPN0j7g9836GotF8H4OkyiCi6VxCeUJXk3+uCU3Yepg
dgNOlgf6x02Xs4j65BuWSBJ5cxS0HmGa3iw5I0zSlS4DGvs0tqB3wmXhi76CAxbd7ZlwdlckkbYW
aNIJWeMSGEuf/7xkR2TAohIIr3kwcHEKxi5fCDuz3uZK3b+rRsd0ubIdOdIg1Z3TqdS5q7J1oAsj
FHXWnl95ObSEeuhu/DF8qxHySoDso1G8POoXAq5cV1u88owzSr4lRpzbOI436wcH9NvBLiYn1/c9
j8P9gOLo8HaiBjsljyG6cD5emSot/WYlQWs2LKWAOPDP6dz/KISb5UukME0vNJ9lX0q+dRJYzOYj
S844RxTWGO+TpBhFP8wk4OxW0jQUFNKkhSg5JKXxTa9Fm9bEUoC+odlGIgkvgxzRdaiYxNJALsW6
weACW4SF5OYvFEI4Q9i9gpBTQZLfrQX2SgW0LUJ2818kjzmPHSyEjqYCz9FE+51QE2xnI/xlt50c
OjT7TUlb8YcT8xh4eHC5aGOISD2ghTwgN+2gEDqKJBmnpZW1AzDtxu05yf2vctReICTmLfXVcX+F
G4xL/piGGTyXcxWoUvY5Ph7juUKSE8sBlJ3c7jYQeXd7WOcTphesYt4TUNVGKBoNb8BVbIqvAe58
MKqN36FwQRjHHNu2+v2vrg28peoO1OCLLsChFra1BhtkTuZZxcuyVlzJQlndNqkgBb2IyEt6xEXx
AHSXZncD1xkSe5zZ+HnF1ZfzFsECLZomoSAkvCS26mgc8abZ3PsgVIofJdd9HTO4RhM2O0vehBfK
lHw1tbxf7VqAQ2IIlUr0Cpj5g/mOJC+6IZUDzmozBuO0Udp1HLqKU3KbAKs83kxGme6a2+/2M0NK
ovYqw3Og9r4xiA3xsDDgZYtcjBRtYURS0Uix0k+WC3nVs1yJzWhyt0CMxqx+TrPfpcl3bt14XQUA
Hxe1idxxourtcsCHo9XFFxF+85kx4noscRSMtchBz5+f7jyFTtsfeKDRWaQ85orVsZQNIN43yX4C
+zk2/KWkwOtHRLPkjV0RqlhMc/T+nEsz3CfY2RK85iMQS59Ownz6JOaZebgBPUPEHtUAz+pXAPil
eiBPb1bmdjLBuuiqnVumoQ0Sr2PZCgS9MzCn6IWDTHOkIus0NQLOeaXgnhaCO1TB5D4doYN8bKVK
vLefALmE2UE4m4DGWrcUicIJBnRkV7VQIzoMRFGeynLtYsZIaw1Ddyt4MFqAfO6wj+7RasY2oz1E
Vo5CGYdy559rD0wUglTS5Kr14yG2CNHDMDymwu8EpIWVqoTqjj6wYTHNIWjos6t10RY6uRCFuOpH
m7JwT+6lQr+CubUEaD+eGFpaR2DdN5HhUwoox/f1igrmZbLL8U0OdUAAMUjkbTtExEOcHRskSvtM
FcNZq/aPTIZ1l6CkasrZz+/hxSV1fNvGXz1ysyy3GolV4a9LzmyLQ9bd51zsyNmTw/u0bWofZU6D
ZTteOWGXW3W5rmIytkPqON2QWEnzIZohJjBBjE08hHZdXb4klkbJ32siCobox2m5tTS5ERqlz/NK
J2Dhs58TRiiJMpwfS9r0mwhkaiQTDhV6D8U7UBexwn5GOqWZUiVCPZWuApacttavHBu14+iwlaAg
Pd6QYCD4xQECkIcVWiXZr163pwxLNQBCZCR8Ikztk2FI0BQD1GXqh4lO+yZqxeFSbZ6B9XmBQlwT
uShUFoPJxwFF/J5VHydsMA+x7K1bbfpCkoh0XMyM9BYwJOM2ch7r5xZ2Qse9Lzuaob1h9fc8vjun
kMV6GYLRDOw93gQTNgqbBxWSkYd4FKQNdXFtnVF3SOYeoxkFDGf53K/71xcyB2dMEGgY5l7g5oYl
C2ZwlsG3IDixGH5t5eN7dmoRWGfSJgEwmK70Mm1DPgyW1/V63axmoAC6gwk1Z5GZh6GChTb8QIjl
/oEhfeqYwDBA9kjSecLlGmWDS/+Y/KoyNvIyiUQAxIayEBWwvl5HwxD9zHMQVq1VHz2aDQR6yCBq
4lo0g+6S/J9/NlMjxmrgNnrgKmG2x4mx/2raMtUjKAZgf3zJXLJZVbSa9MTfZoxT1EJkPUraeIY8
tKvNr4ZBgHleKifLCETWadNdafUgekC8ajS2iRSnnfWf4KornK6s5oeIM0MkWUiIS1nw426kqEeP
jiM1kwGvUpPfx7pUlb7AIN+bzdFw8yqv92rfW6UIOL7LMB2SkrLZTFIbb6n+20cLzPZ+L92QHK0f
uynFboTdNpBys1ka8LZj+8YqVJlTOl4y58XJeYLWOdl018mENMSea+QyRyHn3fhAsj+d/jsgtHJ+
nSN23I9/Pkbxu0B4GlCyptzeOWPttA0j6TlugmGbpPhTOB5mkOhP8QG3gUBqLG2sQkeOnE8tQyxF
PjDnDlLgm3gg8GLD0dInGlqszB21pNAE+QG2gHxdb3qOIBaXfGgfz86fSUzACcmWClC9jRDx/xLy
yNmcFl6T5IjsAFItZhOpmTJJa9Zkr7h+Pp6z4MYUT5qBpSm3HtXJsCkRcz5OsiYXBs1GN+Z5XB5K
wvB8nvAwKPbzJEXPpaFNfPNMsYGWJHu4iKyYsm/JXq4fkOqsvldNHcFI+wP0pTyqdmIdbvuz1X/G
0ZA44mCNYaP+E8gF2WLTNZ567yoWABXdba5yBwK3oT8PqHXQ63aV5gZhVZl/RpXMh/MNlPiEwD+P
eNcZD/B2GmBIw58foUR+/jiucBqwoeFjF6J5r2AU5Iqdz4aQzlkpQZGDsh8mjFf9FumOQIuZkMES
PJ+0+KO9Saav44FP6Zf4KpJ8cYiFq4ZhMZFn9K9Mx/yIgaCeFJ0Ynh8GeUamxEMvgGg5bcB2KT3U
BIEk7EHY2o8RqtH5mUbBQBYfFBw+G8uHyWYsrsfwbJQyuc3d1/hF1fq25Ljq8a5MAz6NeKolpXQ9
lZkgJSxhVIK5H7jsIkYDWuxbtBFudob+tkuHew42TpktfKFMCweNNsqnTyIICaPMKT848sjN+Hxj
WT23wJnqxloLaFnDyuamffP9N0eS8uVvpQdqVv47jGt9wsmUOk/xTXTARDaDQlkVznUlMJgVtP5m
/lKdH5NGOjo6MiXQj8nYVpOrli98azhUrydsgsP2nmnY27rDvUS35alNCCqcDl4F/8Sv8tizax+u
a/GMuJwN8afCkZz9oPIXxF7ywOPvXbZCXGs/9zqKLlh8bQUslbb6uWgTgRTand+LLFlGmuiUVVzb
Ft+jzSDaV+ChMBe6wVA8HyeEmV0eDzOluQACIe3mVXVZG0sAPd9x4qEhgvsOEGNYjsg/HaB/qib/
QNzLj8lg0n06KsYke3tzWB8suwdzQwrCsCbaPdvPvb+KuHrq0a74xqojueGVXFPOaVMDW8a0+Aq4
eFob9R+7QtAW8cQQ8GjCEPRIxkunq3DbEOOIgv6VND1gRiF7bJ4g3rRxBeVl9cRLv6JQXpyHJqkC
4vJhQYOTpvaCpSMsrY5s1GabDd16mvReSOSi4l7MtrApN1Tmj0dULAJ4FrqZaC+tCgIBPAFbFmYS
/3ZXNr4CUPX5Scu4K0IxuSM3Jm2exHU/zpl0Ce2bPF1VTuj+dXdwiYy1n42Xto4LfP6oSe3OrqAw
AzGauwE5K6Z6jbcTtiF79Rf24pXfvfkEBgRPTtKqOxMQ4KZHsLw0KY3Ca0ufqiEFOJqdxRCBrA1Q
E6Spy9gcCNZKnd8edIwcoz+qwERm1IX7BuA+ZkXtZBN9PQuodOydkFepPmSU8M1Kw3ReS1uxEDvL
/177o+tBbXs106aghHt8bDvTOaHd4UzTQm/WX1AcMh8HmU+m65kiVc6qC4wCTWNP9xKWAgmnjVKd
tvTV2ZZaBVQCDBSJuwZKEZjcrQOQYD7tltKeXQbkraJaYFPk6859Abrs+GNz+6m6SWknjtJ4j2I9
qQPyiihdnSl7LCocZ0UMlysvFFrea58z7fn0JWaIoiGVt4ZQCGLIn6lqfn86NpVCZIh3ho1trEIl
Fcl7DLvOma3tQ5SWJFYGvMeeYYiu10Y8VNJfe3uBPn8AWjxx2iG192mgxjgHLtQ4hm2JmlBTNWdU
Yekb0I7TSd2YpvgxvVfNEx1CZ052LOWgs2NwnUmYTBp5zcPDluD/7o1annVWARTyMFHPlaBcPNj9
oivShFZ3KNjm4KYUZoUBZcqWT5sdM2Oumw23FRWCrMwN2kVAi8rdw3Vf2jrPAMdKEytlfcBaF1fM
AqvKjdbHGt2pHvfozzc7NOKSyCuVJ565gYTbsWP4rwnj8EXFbhJ3fQTVMBZUzc18eJ0YKjauELE+
oD1ldExEH5eDyYEeY+rFTzVxj3ugIJeWWEmqdhtSeM7EqHrcHHrMpGN8hlAvkTFrhzzh9zKrNqaF
RerKKgqV4DhGaqBphV4/eG+3WMjXw9yN6dHKKVjRmQ9eeTe0lZ5lmNSFEcUwACpPfyEtBdXYiPnU
lWXAXzyrigCxYoyf6YJ+fyj/sPNcRO9Cxj1QiyFZfgHgkWqf3rEWbXzf/HYrU1SxtuNb20fack7A
5lktMsWX1is7QEJfZasr9GJ0hwBi0fHbM+XxzB8kBR9oaSPPmmDr6O6SVt2NwPboXlKK8ZXd4pUV
c9bK/DSHwzVFPUPjv7TDdhoyro6ljdI57xpX6RcB2G6BV7Xn21pHzk7TEYsLzN536LgpyaXeD/4+
CG8/u/0NiXO/y7hTs7iGCaavLsq0d8oKquxPHgacOoHt0a5rLHQdbpKQzi+6t6cE9tf0VyXymUlO
EMEo0MIf4m8wI1/RRufhSgev5I4kJmRzkGoNneAaAk2dfyw8S/so22QXinonXt4eqzrND6lt5aha
33SEO80w/y5P3+2cMrmPakK712baYBWlraPbIzaLNjiana/6Lm4PjvjmoWiZ/cF70oQ573weUMqB
7WmcN0Mc9X4OTa8GE2vQtK9kSEl2m66nbvQu5SW0izGQj/eLngFrnhGxWD82v4nlPFCfdUE4FuUD
mXF/ss48G72xjrobqJwh+CkS4ZcL9Y9JnLv1B794x0R4MkYrz2MWeMSqok5Kje3AV+6XHZa6D6Uf
66wiVL4pOAiLE7xhIIBj3I05SBD8SAu3+16bjlxIn6+8xXi1hmHRugMuQJi38Zg0Qn+sbeNSMEOB
nEQClmFDs93dIWdLZxbviG8nxS4zuq3+BcyOgyYtsfNoFz4u5lDz3ZeovI5+qbIBK3mBFdovqwPN
mU7nAVUeykrwFRZAt4qwawLFK7SZKeyNlTDC8lyO6cCk3ZQiBvdkdRISW9i1xRFUg+q6yFjmIeHD
1jGTm+SSmkgfn8d69Zqm1XTa4DThN3AIR5EYSfYBXvnA/5nm/W0iwnFhVKMG4sLjKHkktKEB3rXD
5ort/wsvO4Jc0X99zmclB2pP0Gzjf+PP0qBhn9VDpSYuwlqWi22svChoIOnRTp3AZ4Oeouwd9IXt
xc54gYKmgvBH1WXcY1Zz1gS00v0W1KrB58/c10k7NxWfuELiMN2XB3OdJH//hsFyEG8XF8sr34mG
aLKDLXmx3TGzwgczuAsVX52Xax21qZYe6tAF4mV169ZXOQkLQqrxwiGo4KtBf8kYvQ3xGWNIGqC/
ROFqdmGImeUaOhXQTErnAi5GiX5Gf3Uah5PKBu/1LM8mTeczQw99HqP+IqQuSHR7w51KjIHAiwsp
29TEjAISMqq5Q4crD/Sd0bXWYC4UxudZblvmNUkiZX1XkuTp3Z8FjiVvijIp+wzlXqO3wk7HGNHj
1L7LNudiiMWjQuBLe37T6+eoUZ9DsdGEyCNSYIewQk3NFV8GEf6MvcmekL/YBf5oABbMvjK5mLI3
u6kQ5M9R/T3vHIA/8g57cTxrPjxrUxsRs579/WLC+oHh3aBlGmENmB7gvo/WBnM+ILO1qauS4bsL
jE9uw73vVsI8SwubqK/OjvGTgAwdTr1jLl6pIySkA+hEd+HwN92aWmi57FyF3TU8m3/wXd8RjkyG
//HO/aBtEh65UkO1v0CyWuJbHUXBwbtStiyjSgH8McDP4STGkNBBbvEKOc5q0p7t+XH7hfW07gvL
p8S/kxoffosbcksquR5+HRfDF5YFgiIbXTt4Y1vBK+fyC2VHyCBPmZusVNrXvH6V8vHl+XjDCcmU
mSMHHP6yhhGOqWI7k12LLtueIt/NrMeIz8KnAlwh4QGUz+UJhRWoIza+kjugJaGS1pyJlm1E1IpS
E17o1K7+7FBTEq3m+yDsfNLHoK/1dtoixjJex/ep2mte42zcxnsqQ3xBfjzcEwNKSlbUFryrlYs+
gnpZHJa3hCzcCdrq/0yeZALI60yckTIgeoXGcyntKz5B7bqac5duNP5Y8UgBEeoYKTNCmEKCiLbs
hBnegpK36IfBiUVNnAMDRLcE6N/9Egk66bzq0cWo6EHbT40fihH1w3IVHDnfMCEYzoSEZ/6xEAjx
Zu+ZKqor18xjNXtFIlGYmK8vscSXDxr/b2ceGTO0/yRJhdIqPtFe0P9mch4XqfJPbRIhQZ+Gquud
WUsLs66b3/yg3CvG7Ld2gf6cNBpDo6A/PEanPF53om9nY5vWSUnH94n/8ovhPefGvPJ/JCLzXaKj
GDOQb5lz/O8jMg4vyMR5n03MMRgouZUFKjzhUuVTuAdQsPo/ax9uNj1671x3EFAFbArpZxjkH9/y
dixPcapLRjs74hXjcd8LLZDBVx1KVVeWbQ+8Qe34cH/jyZAlXcwJvdMKVLAY+aBXC/N8AyJxlPEU
BcJPx7QS5hQyX5LJcM8BjZmNO/bpHIkjpyO99FLwd8I2pc4ACV85l1ep7Yc1Vho+6H2skYpOUpR0
O+94ohJg3Y13/1kCDmO870X7YLSKhbtb4dtC/hqHW82aZ7T7ONj6IdC9L+2wg8C/iJtFbKOyOJDM
fyre7YHKVbIrI3S/2VEkcLIu7DMfjnlv1sa/ojAcBdvYI7KxF6LzqmjlO/x8W0k3hGAHGtMEJCJC
dx1CGIAR+1OimZnp6TkAiN3aQORwiOy9fO5W3wLAWp8r/FkfECVvbS/m6mvxsC02XcfUPpceHvXm
+zBGS8PNx5oCMGpnTCq1eZPmwTLMzowWiN9sZdPEfT6zLfkHfbkYO0W7SmH3Lwshz4RefD+FC74T
BwqirIJszewcG9QgXiCbqTdgi/qw6QeGjqDEjhJtBlNUyzSrcVVdkWBUhEBSFG/vQoO+pz4QZ7Or
yV+umElnFr1LJ4FTXdwi+GnU+8lHvs/0bqNlx5EQWj3n/mftGI38L3Ya2wJy/2/iF/h4+oSsVdA3
qKVhPwinRDCaMBBTFPrsfUNM3oI9XbBydjugwmMiCRS30BqAAsEwkPKuYxyWIwOqxIo5Ta6RkluQ
XofkMRN/sq4b3cylFsTKytoBRKj/2vqjXvYifKKY0kvBmFY9Us7Ema9n8xTRGzvPq9gXl/cklh/j
AODMMDvJS/GlIRQX/0dyTFzOsVa99SJ1oN3FZgIWm8WaJuD0780cODYk+vxWCC75VDs2TI31AW1N
DyVi4JgVmYVuFY8j79XCkYZmxg8WTOcpjfjCnDHnB5Y9LfUVMyedr3kNcTcZuXMgyXvvm/bL63yQ
v4ZAFc2klfU9phwnBvvn2fsXy4+Jk/RnNus9zCjVuKh44JIk/ADswK48dAqcUPlXJDXcavKwqxB1
zR2+lTCVhKoos+TQICONq2qcJj70SbjJGCZx/ekj/yMJ8VnoBfOeUFdEG1ofQsrfNDgKjMyH/zqj
/I5h1mruwVcwOmGQG9/NI2S5t+8OiCO3/bC3N9Xiz7l8LCaspjonQA7yNlAiHAaygGAkXCDrH441
QV2Krt4pwDmvDqhbuHUuTD3h0s3KOuf+zH3us2L1lzXNzdtyqsE1a1v7aVLKLTrgB5y7NqVzWKCY
A4Q1wTtooefOqdWoJKcgnj9caHDTiEbKs4SPuJVWDVTouoeZzvU4wquGznpXVHySBD39GyfkQEbz
5hB4DGWdveUuoIfmtZC7UPzKoSTw3mPwBRAvTaCV5S6xIB/P89a6AKLgd4TRnBHgzeTveoSD31wQ
tXpdlN5pCi/uoX/tztfs2LcvfDI8qTSP1YQ/ChXvWn9h4jpnIoFgE5SdS4Q9TMyIkYA4hAI4Edd3
DYHugnUYeVFQUmCGZ7HslSI5AllY9Gy6OerRwi0m8bznlFSh2hxbOZf5Dh/nS5mzcf9eQ3aVhX92
Dbqm01U93lCMmBqgqjbEVLz5FWDqMXY1hO66bLEKG1/ynJU+SBkDPbtlzDAQ29gh8eEVHQ55P1Xe
TH2vfKn2p1U8Jc8STI8qp3q+p6sG/wc9hAKuqs7Hx678HrxpFynWoLE/OiRkfY3HxzaBpkAESsy/
OhLIuhFsAhWiKkGvyhfaBhSQHqQUT4SRS2+30cNg+IejPBovccZc8tMe1CxWrC9OfzSMNLD5NFNK
BBL2XofY11HxI+AtjegdlfbXbhcpziyKN6kc+2eKhwm58T6r0BkClL2gruTlOo1OYhi8JIjEHSe8
8ON82Qdeeews94xAndGmMgCjAA3yFBb8owkiXr8zU15BuiCWsmrEaMjKQsi2rmW9IZu+Vq0+Jw+/
EoItv+85Pwrb+Se+xt8w7BBdlSIQeStYvkIiwj0RI9zV+8p6VFkASqN671bJyKHMQL6t9sR/bsnE
y1a/fmVK05Pc1xdZ5qmQKAZhgos8d9avYygcDD5J0TWs0W+GS9HJfZYqf5uYyujZgom7xQJEp1cA
2JQKpQeUP8Aub04BRbKZ+0iHsAlT1E48q9o1DiWZ8gZbw++zwtxD0Xd8VmIw0+Z0u0TbJJnZVu17
WqDs7cTvL/g2Sw1n/LVCw0GCKV8s4n3isG3gsY4mP1hyhRGCcLqAwOUpmTVMi7/vbiZC8m/kJKnO
l808zPtym8dUQfsPDpavaYssmqJ/qP6MbcS/getWjGenxrlp4Cj8qPavpBAx++fa8PfHQQf1Uay3
DNBuM1GAT+tEfW0QAFCv1/D4MOWnf9kNtCv2IS4EtHfnGK2YxVpcSVCPJAE2F9VPfqC5kFSO0eja
k3051sLc15nnCJG3w9OvJhVZn3dNTk2kiS6iR0v/L7q+3khDyd2IngDxPTgCkrKRH8z4g6aVWKQJ
NiggcOQ3IeTDz1kw99I1rJ22apA4gLcqr1itFLp+prhXANNR2Y84GdVjSia1unwPDBfZUWLv7XuU
9CzRjoHueiyC7fjtM9d5MEKygcwH7MoEgvZ5F2g72H2uRkSgcIJEyhtaTB3chI6OWTZ3uPQ9RUen
uLVR/IhX+jt34t6AkbNtVfBovgcDeQSXMDmJ3AeTa3F+FTEqosjMpX41TvlpHlANhAxfoAvVGiFS
4svmTJIWmSTvCDMdZmWeRsDMqfgYSB7jjGuIbEizoFWdbBCYOpeN0zjJf12bx6MunZzvpUV3dtdt
Z839gHRZ4uVjwsOJDVR2Nnse3msjSSeJGsTEdVCwWTgDsVXJrBrW4vq16cmmH3XbOcIaY2TsntQ6
ncMSaf5IT2RsKOP3mY2aKTvHCPxlfszKgs2O8v3MmnBiM/cMXWz/vkovfsJHsZ0g87FhpmSeJELK
Cew4jqKb5I4TnkmcL6fhgr7Fu23kV5SKJpxMJXz9Sf8xhfkKuAhoPZMHcbeUb99kMuwr2X6QjmBJ
J0rkbz2a60Xooe6UR2uzMjr/uDn7LAiubm1bDqdnll9KxMVtYY9MIePP2gwfh9v6YMDtzFaDxQY7
F2re9oRZ1IlSudTBoPUqq/OUF9AbHBgrTDykF64pz56oJRZolgKRB4/KUCf7FfGk86HmC8V5d3RY
QHA4LxARi1LT6TFp5yLOe2svmQeXtKwvcCsVxySEws/QBfE66A0Ygd04UesQQzP2g7dO8qU7AA4V
3vKtrXmEaDUwKdxTzwwfelnSFsd56ySbRV5eGekZgRTGj0MyamM5d4WXwjvHs7LDq4inPDLOqXRT
Oq6jpBMpcGt8tsNMj/9gTRZK0DDx3YHQaZ0PzVTYQS3UMeknjSG/omglDuoZS7Bdf7tNh+EauDll
xQM2EImehUIl9quQwpbPeRY0rI9QGxz+JwktSiPnF0NTjl+3ZJCeHXsEhBfQp9pxsPeTV2looLS3
xyO/UtNFxaposjjwHb3A5K57zEGWKqNUqDfIEFvWQxQvtMNy2Aq1JKllFqNYM3MEB+ZTC6dBR6Gm
uI/upuwUErHzpI4GNtAMuAuUfOsBW6ARs+gKyXOw/KeNNPvEqUBnMz1kJIWH7FCOr0Qyr/9P+PN1
qRTAN2pPH7zaosd+31VQ+3l9UPdsCnhzVjr+xetU3U++qpfmhywht1kfHKPMLNSWIUL8NMli3aPl
QVK1e0x5paSzsSlPXbsbh8l0uEyz0tuLr1nzC4u+0Yi2ih0mbkh8i5l7bBwfAR8IWbtJ1i82igM/
QSbKRcHq+Q1rTfbp7L0iOEqeBeehtyNAbM6GGi55+mmezemdGRY/4dsFdutYNMKwMk6qOpgLrI4i
dqrxGoulIcwPRVzalMaOvDkuOUS+qObs44LUwtDpYgxP2p8roY0Unb3xRL4gyLqfBlcJtEV8OzNT
sGbR+A+Jep+Mf4V9MEqtoOk3XrZf5zURgRHZadaGu5JSyea5Ur7ENkyHPnMggxZp4xO71YlV8MQM
Jt01dINUWyBOQXyOY5NPTjDU6yUS7JuU6iUfLremRYAKZW9TcLe/5+jQgsQHVkS82HG9ZpF4Tw9t
fVB0nvrWvPPCqLwZJXrXX9N06udrJFFERnpc4FC3DOocctijkBMKaC5nT4Yd+wH+ao4eRCcmUCPZ
SGCKLfdqFrgaDecD+Dd0V2KJCLJlQUl+bTdRWoaXtciQ0fialx6yF8Eni57tAvoq+6Gr+h7pJTFe
axYnE8GNHs7Xlx2cNrmibkVMPS6LxTqZYwL20nYg0Mbj2An3j95w8pOvNqhfoVLeNMKfWFa+0DBt
6t29kVWma0JRqznazp0aYgJkBZGjzIhj+UM9U1vGF7r8vcjOW6x7VMoF+0+hfGqLGSpAKxE3mwRr
quP92cu2gUIsrJQt1HTsIf3n+aMr1cp1YEFS+5VjiqDxpw8okUt6mI9fiBm50LDialw6EdnIdYdJ
z9YHUxyh+XTac3tKRdoBzWkLJ1qIBFQYZVUPiPlige6OCohhOUY114CtqSTXA7YQgkY43qt6GjR6
gQmo9FNxdYdz/D04irbwK1lPIL2DaLesJnlMYymjZ8oELyJ5iZTeYUa5hjIKtHxJcTZu2Ty+jxs6
mG94bMHvTcmE6WbRmq5pweOwndKRM7kssEc/Dj4F7XhdT2BYc/sZYhLoexv+sFO4C1USPnMDx6Zb
rF805h+u3Te7wvQGDN6YPGm2f1UrQDQ0bUDhLz43VJTKb4NP46RHfKPiMDGKJF8vCY8+C94WjAeX
yKYQDj6EMYihZwGyRY+RTzuWYUBaez9dwOO5UisZ5soGQYppWsWBkjrrrGdJpc4WZ3uE+GP0IfYE
X93kAIiNtgV+WK0v06IBQMua9gK1vgCXOiU1iLhH/TjKAJchf2fnj93K27I+1AN8GYHxu4j2FlNy
F94Tcx0UwwHcztdbmQv0MXxG34L/gBSKBuBKT1inVSNd4f37xpHy72xq/wd0kLOM5uDBZCiGxcYH
UksOgKXmMPGxo57ClGpabEeLsabDD+5gN0M/eDwHlPVFY0bGvozSqsexNp89zDSAxJ2nXlN3c6vL
OmURzeD2b0WbhCUzASwEySRk0sImvGHUAhJvmofpU4YrPRrtrHcisIWu27+SzvAQeMu7fJNiJhzF
BaUa2/eTHSMMe9+1W/1NRGM1DUJy8wDnv0J4pLOh/Oe/g3WRaGW5MxlqOH8Mh4Dh6e966Qoj5Sa2
Ojvi5VYfTGSxv829WkfLY+mahvD5sZ1jyJApBFRc404PmYEfRVYCadkDPHKeB/YvQn7uIS1+n3TB
rBcUG6cLHYx2KH5RlncMjFenvauWmcfBt7aeceoRAsUJniFUvwmSQI12fegdyeu2t0sUR4CeYe13
NRU5BwoDWZ4tgYt9jc3LAXP/iAlzA/jQYH8nsbNUpnbicmaqmYyUsQlWoFFJbVo0U30jyw98Bt4N
km5Gif6oLfXbJ6zhn2KK1W1mYaf7Tr0go9xIvtL5oTDpWr6+wsFZFX6DLpKLb9ABHZZCb+qLIs2P
VS9s/bCKpJlmK0C5yzX9/EYQnFbL7Zi2iPZdwUYZy01NndH4/vXaki2Fq+WShMGF3IeCF2+2vRcQ
S7W6YPjQ5Lmu5MnA8jXqEdNDLaSnKG5djEdfZLhfo3m0dhWiwkjPfaQuPxmZsp14O9bQ0Lj6aykq
eGf+rublxHkEonzfND3oO4VRm4+H23pMEX0QQntRAbkJpnk+Q5dGufVjkrB9LbKmrLkDOYq7UZzK
I1uGEtiPIv1+ZlBLJWHgX5cI5LQV6460OF5IJdMYgalEj7W2JQBgjjwOdq2DMi02pWFFjljYO0m+
r7RnLA53rOH/TFYOm7NS5E7tq/DX4uxp36K7BTGdrMQSgCOUVi1QQRpBRdGEhSRCQk8brZsgYsvm
fOKvvcnPImSkDCKbqVv4EiTz0GFyS3e9XEFBMcK1KrsGBESbAaUBrA//qNVJgyhD//LFJ5Rae3tU
5QAtVOJ3ysJdjow8gyZOLKpfshsb5LmEuij3lFcoszk8J0ASgrnoCoKR13E61N+AmPJgNRgGuuAL
K2XReDIoStSu9uy4lvpfhfZfJiQupSuzylR25l/A5rnqkZ0BA5sMYKGyz+RVA2u9AXSagdXzeuK+
lArkr5HX8MHC34WUDTfUV3wfRxfUVSSbD9Vk1Wn/sliy/a1f+u4pEzXhDeo9Rzzy8UxXMguuF1Ae
sX2XgFZKxJm+mvPnv6NYy2GOBe6TYLHgeDeJnuB72FPUnTDUpj6YVstdjAnyQAYqqBL/B59Tzi9Z
V4LGBrK+uAVwnk64pgDpEQz97PefkdE0O375aFJQZIn3m0qh5fbi0w14+HazcBQkW2ww5HlzPvhH
IK1EbA412NOLHMw70xSKbXvv+w6+MxL84Mn2rLMoAYfB00PceELLXDIQduTHIlEC8JIEyVjN50EP
EBqDROTzBAvgQNH0MMqswxx30dCer/s1tANJd05Ry7YXdZFJ27V9WFJksy3yjJGWiUemKfboQixC
xJm063QOiXKBNwahYK/8r+SOCDOu4XQ05CJMmBk2gMCqiPQD4oLpriEf3e2e4JOt9qHuzkkW3wE4
OFRasrKw8AWT0R6gfSi7oNC4wtJNiY+a8IA4nb1XQ3bmlI6DeXY86nzBY5WjdvSAAFA2aPR8qVh/
8fj/bC+4/mNiaWRyBG4BlMSMWLc2SmVe9m/E7Af24QNhduZ9gFavqQSn47Ngm3DPW57HWwq6RcK2
z7kt19HK+9/umGD7E6oAiSNBgL26UYlTC+1Df8FjWt78SjEs44qggeZLt//WyurOcJdFMt5ZHLEN
sQos1TTVc/hPvFqvSvd5sE37qvcVgN4YqjwA9nrLIdqnXYrDPPI/msMrZHf+7FWK0QV6pHo0ppY6
0UASa7NIX4e8coCNqoKFXL4PSaHZVd3AsAvPUDcfPiSnJxyq7MhGlDrAgD2KDwVxVrg4HsggAB+V
NSIosZwHZDk4eqOpitAdfeq2mQuCYQ4eCT/nizTpe6SxIiHzZGq9tyb2PATIO17+geu1iitXiJWK
fpTMn2Zuo1SBAT4dqeN4SPENahhfauFa1Ylx6izuVGea3jxl67U4RQA0vbdl+380g7/VZI9llo19
Vy5iNvuoUHwocTkvd2DevB+O7nQM0mgPfYe9a9wQhFN3LbQsT4WgvKt3Of1ALWVp6C0m1sKY+LU1
RqhsLBj+aHlkOcUzsu5buWarOrxwNPizdMC/4PjerQcRQtb0MdQ0xX+Cwk7Xq+PT0zra5Rfnrklo
52B0/GtG2DMgezrIk12uTPyb284ha+A+lVxc+p31uB7Wq+VCWVUPLQANxsrv/6xN0oDUlXBAWRV3
E+25ENTzosF+bfyVaWTFF0SJZrILJSqBex3YFGJolXI0g/xZ2Oi5VJFF83eItNf2I9rJrcWTcpVX
tRkDMbk5TVswDgDrme+LS84rnfwIzK01i13/SZk9EL93TRmfleIvJYrh1KNokFyB5954fTWP6xY/
aJ4T1yOZnFldDqe7z0q5bmkSaATjZYktQ+4iekuLzS2BLjLBzQTtP181ajVI2n8euIidxZkttWBL
n+FafgFfB9rA6slDHZiJtRVW69mmFjGHFEvkPFmk5NJ539ldKpd2JTNafaM1ON6dBzBtCTy66qpr
E2VPFfEKwiSd41iitgyiuXk4+ls+BuEnjWFdvWwEnZHQG9FuzB/c4yGDFE9Dmznc0MSq9ObKx7LP
e9guKM2yYaccXl4GL3p8JB6BE7ieDxqeIL4cmA753w4o/zRqigA1KYA5MMnkUpPx/o/77lijZS1g
bGCwbuwqgncS2UksjfNFEkh8jyYroZns80en0+apogbyTQVgl1/ZkKERn7qtK88lohXjIm90tpJY
Vrl4nNjmh22WWqtTHPJq/LFAb6N7pNFgq46l9NMpvGQi40tTUVUmFBFhVARZk4mZlZNH/TxU4wsH
uMBrXyqOmjHpOyTSu+d1GFFUpNMjqG5LjW4i/K73nBJg4jw7iZEm+rLJRGtM/1oaU4Ao4AjN4KtH
TX4mQT+zVJlyOtO8IPSgA21+qj5SKWwYwlWR6w4i3U+ml/aAee9BvyoAU8dYqAQCCxmva5lDfHNG
DT6etMIyJycDOGtusmA4JE6Y+ld3sRg4huBvlmO6bQgdEkMhHrTEHbNw7Z1wbewvTnoQ6zX527M1
kYHybFH9AG4zYXrKxjvIuszLgGx+sAHkp7C+dp+TRVoEgyUo+NYn0MgYLVi8um3LHhOrp1QSmpSw
PaKlnm+UwoOGGJ2QXmwdFhd96h9LYGb+kUfj0QJKB94ojy3cij0siGph9gAv9KxGKJlOAwQCldyG
u5TDE44Ts67COL8hykWOoTdgOcZOnWLyY8n2WmPABUmJeZGBi7C1D+z4rXFIbtfudxj9tMiKg/lf
e7cNYRK4OYdf4GHuRLGN4FFO2T21UGQSZHcCMrwL+C6DNFD+l4N4vpz8eZKyFjIBCQD4e8L8zxC2
yUYzfxuczyj/2C2tOe5iqwkDhm5jNIToO8GJvKg2KAvwbdt8v2RniFJ731zN3tWz6pC7bBxz1eyZ
mKl+LasV71q5YdQylvVZ2Ci2h7taa6AsC3PBOT4aEWRrmxkZcjr0fKNIuAU/VJuRO16I2cAU9dIO
lwe1+C7d1j+LTHIPO2n6t0vLc63C+PSFj/raN2oSbZeAiMp+87cHEGx5Alxna0OuykZKDsd6VEPz
btqEbn7hypk5CVnbIAJYUMhKqENOYxiAFFlP4Z5kOKZEHdkBX/8TmU/NjDzBXg02yuSlilT/ZxNS
jegwfcSTQlCz+pbuqMNBz81uIh1JVhokeHjy34g7SaBedfOqH5ikWGZyWc72t5epDlurdSS7Ktd7
KvLo8gVQ4xtyFp5d4zh0XfugRmQCRcqlhJCA+WzVFTIgiurZzKUl/RSen/VllA11SX5o6pL5wpxI
gnbQeZk+uKSHOMnm+shr7ZqmWbpzcNE5Z88k6aXwFHJhxqZNIYelSYF81VY3edz7Z9YXiElDTomA
SLQljEPv8WXojFYFw8mRWs7827HTeC5MTwOHO729GJLucC8dqlH4bLBxlIekAyTeHUIhEhKp0kEO
dWicOfEWJblWu3a1Le2+MX1FJ+vOaUXB6+lIbJUmn0nesix21AN0XuzgHi70a1Kw1bhreLAYLx13
S1CgPAxn8iEiNJlDvCVC069PGzbobu6GFbSQNvMalCeG+mLX2WoKcJgG7VQn4wErxg0fhg7Fzaeg
3XewsIWfVLrEQohp4+feMrdEbIWpGOhfWiYiA7OsCJAxoBxml+7qeNYPLztVbKieX2IWNpDc5J/4
uaRjwg8ONcAb7ADato7rlcwDWKpr4nQ3cjAwNXe0jA/YM4XdYcUC6QlC25Ju5iM5dyoNpInNPfIB
UdeAFYil94+21nTRqfHPma8LYHOjMAwRRNAgsSrgVwXHcTR0HU43VQqditcek3y3IW3/xy4gpkmF
M+htwF7CaJ4kJlCHJXGfvWpxqYxVc9b6PpA=
`protect end_protected
| bsd-2-clause | bc348478e0a456899066a0af003ca7f7 | 0.95237 | 1.824612 | false | false | false | false |
Yarr/Yarr-fw | rtl/kintex7/ddr3k7-core/ddr3_read_core.vhd | 1 | 18,277 | ----------------------------------------------------------------------------------
-- Company: LBNL
-- Engineer: Arnaud Sautaux
--
-- Create Date: 07/27/2017 10:50:41 AM
-- Design Name: ddr3k7-core
-- Module Name: ddr3_read_core - Behavioral
-- Project Name: YARR
-- Target Devices: xc7k160t
-- Tool Versions: Vivado v2016.2 (64 bit)
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ddr3_read_core is
generic (
g_BYTE_ADDR_WIDTH : integer := 29;
g_MASK_SIZE : integer := 8;
g_DATA_PORT_SIZE : integer := 64;
g_NOT_CONSECUTIVE_DETECTION : boolean := false
);
Port (
----------------------------------------------------------------------------
-- Reset input (active low)
----------------------------------------------------------------------------
rst_n_i : in std_logic;
wb_clk_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (g_MASK_SIZE - 1 downto 0);
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_adr_i : in STD_LOGIC_VECTOR (32 - 1 downto 0);
wb_dat_i : in STD_LOGIC_VECTOR (g_DATA_PORT_SIZE - 1 downto 0);
wb_dat_o : out STD_LOGIC_VECTOR (g_DATA_PORT_SIZE - 1 downto 0);
wb_ack_o : out STD_LOGIC;
wb_stall_o : out STD_LOGIC;
ddr_addr_o : out std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
ddr_cmd_o : out std_logic_vector(2 downto 0);
ddr_cmd_en_o : out std_logic;
ddr_rd_data_i : in std_logic_vector(511 downto 0);
ddr_rd_data_end_i : in std_logic;
ddr_rd_data_valid_i : in std_logic;
ddr_rdy_i : in std_logic;
ddr_ui_clk_i : in std_logic;
ddr_req_o : out std_logic;
ddr_gnt_i : in std_logic
);
end ddr3_read_core;
architecture Behavioral of ddr3_read_core is
--------------------------------------
-- Components
--------------------------------------
COMPONENT fifo_29x32
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(28 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fifo_8x32
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT fifo_256x16
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(511 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(511 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
--------------------------------------
-- Constants
--------------------------------------
constant c_read_wait_time : unsigned(7 downto 0) := TO_UNSIGNED(15, 8);
constant c_register_shift_size : integer := 8;
--------------------------------------
-- Types
--------------------------------------
type data_array is array (0 to c_register_shift_size-1) of std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
type mask_array is array (0 to c_register_shift_size-1) of std_logic_vector(g_MASK_SIZE - 1 downto 0);
type addr_array is array (0 to c_register_shift_size-1) of std_logic_vector(g_BYTE_ADDR_WIDTH - 1 downto 0);
type row_array is array (0 to c_register_shift_size-1) of std_logic_vector(c_register_shift_size-1 downto 0);
--------------------------------------
-- Signals
--------------------------------------
signal rst_s : std_logic;
signal wb_sel_s : std_logic_vector(g_MASK_SIZE - 1 downto 0);
signal wb_cyc_s : std_logic;
signal wb_stb_s : std_logic;
signal wb_we_s : std_logic;
signal wb_adr_s : std_logic_vector(32 - 1 downto 0);
signal wb_dat_s : std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
signal wb_ack_s : std_logic;
signal wb_stall_s : std_logic;
signal wb_rd_valid_shift_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_valid_shift_next_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_data_shift_a : data_array;
signal wb_ack_shift_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_addr_shift_a : addr_array;
signal wb_rd_addr_shift_next_a : addr_array;
signal wb_rd_addr_ref_a : addr_array;
signal wb_rd_shifting_s : std_logic;
signal wb_rd_aligned_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_row_a : row_array;
signal wb_rd_global_row_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_first_row_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_several_row_s : std_logic;
signal wb_rd_flush_v_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_shift_flush_s : std_logic;
signal wb_rd_shift_flush_1_s : std_logic;
signal fifo_wb_rd_addr_s : std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
signal fifo_wb_rd_addr_din_s : std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
signal fifo_wb_rd_addr_wr_s : std_logic;
signal fifo_wb_rd_addr_rd_s : std_logic;
signal fifo_wb_rd_addr_dout_s : std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
signal fifo_wb_rd_addr_full_s : std_logic;
signal fifo_wb_rd_addr_almost_full_s : std_logic;
signal fifo_wb_rd_addr_empty_s : std_logic;
signal fifo_wb_rd_mask_s : std_logic_vector(g_BYTE_ADDR_WIDTH + c_register_shift_size-1 downto 0);
signal fifo_wb_rd_mask_din_s : std_logic_vector(g_BYTE_ADDR_WIDTH + c_register_shift_size-1 downto 0);
signal fifo_wb_rd_mask_wr_s : std_logic;
signal fifo_wb_rd_mask_rd_s : std_logic;
signal fifo_wb_rd_mask_dout_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal fifo_wb_rd_mask_full_s : std_logic;
signal fifo_wb_rd_mask_almost_full_s : std_logic;
signal fifo_wb_rd_mask_empty_s : std_logic;
signal fifo_wb_rd_mask_rd_data_count_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
signal fifo_wb_rd_data_din_s : std_logic_vector(511 downto 0);
signal fifo_wb_rd_data_wr_s : std_logic;
signal fifo_wb_rd_data_rd_s : std_logic;
signal fifo_wb_rd_data_dout_s : std_logic_vector(511 downto 0);
signal fifo_wb_rd_data_dout_a : data_array;
signal fifo_wb_rd_data_full_s : std_logic;
signal fifo_wb_rd_data_almost_full_s : std_logic;
signal fifo_wb_rd_data_empty_s : std_logic;
signal fifo_wb_rd_data_rd_data_count_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
--------------------------------------
-- Counter
--------------------------------------
signal wb_read_wait_cnt : unsigned(7 downto 0);
begin
rst_s <= not rst_n_i;
--------------------------------------
-- Wishbone input delay
--------------------------------------
p_wb_in : process (wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
wb_sel_s <= (others =>'0');
wb_cyc_s <= '0';
wb_stb_s <= '0';
wb_we_s <= '0';
wb_adr_s <= (others =>'0');
wb_dat_s <= (others =>'0');
elsif rising_edge(wb_clk_i) then
wb_sel_s <= wb_sel_i;
wb_cyc_s <= wb_cyc_i;
wb_stb_s <= wb_stb_i;
wb_we_s <= wb_we_i;
wb_adr_s <= wb_adr_i;
wb_dat_s <= wb_dat_i;
end if;
end process p_wb_in;
--------------------------------------
-- Wishbone ouput
--------------------------------------
wb_ack_o <= wb_ack_s;
detection_gen : if (g_NOT_CONSECUTIVE_DETECTION = true) generate
wb_stall_s <= fifo_wb_rd_addr_almost_full_s or fifo_wb_rd_mask_almost_full_s or wb_rd_several_row_s;
end generate;
no_dectection_gen : if (g_NOT_CONSECUTIVE_DETECTION = false) generate
wb_stall_s <= fifo_wb_rd_addr_almost_full_s or fifo_wb_rd_mask_almost_full_s;
end generate;
wb_stall_o <= wb_stall_s;
--------------------------------------
-- Wishbone read
--------------------------------------
p_wb_read : process (wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
wb_rd_shift_flush_1_s <= wb_rd_shift_flush_s;
wb_read_wait_cnt <= c_read_wait_time;
wb_rd_valid_shift_s <= (others => '0');
for i in 0 to c_register_shift_size-1 loop
wb_rd_addr_shift_a(i) <= (others => '0');
end loop;
elsif rising_edge(wb_clk_i) then
wb_rd_shift_flush_1_s <= wb_rd_shift_flush_s;
if (wb_cyc_s = '1' and wb_stb_s = '1' and wb_we_s = '0') then
wb_read_wait_cnt <= c_read_wait_time;
else
if(wb_rd_valid_shift_s /= (wb_rd_valid_shift_s'range => '0')) then
if (wb_read_wait_cnt /= 0) then
wb_read_wait_cnt <= wb_read_wait_cnt - 1;
end if;
end if;
end if;
if(wb_rd_shift_flush_s = '1') then
wb_read_wait_cnt <= c_read_wait_time;
end if;
wb_rd_addr_shift_a <= wb_rd_addr_shift_next_a;
wb_rd_valid_shift_s <= wb_rd_valid_shift_next_s;
end if;
end process p_wb_read;
p_wb_read_rtl : process (wb_read_wait_cnt,wb_rd_addr_shift_a,wb_rd_addr_ref_a,wb_rd_valid_shift_s,wb_rd_shift_flush_s,wb_rd_global_row_s,wb_rd_addr_shift_a,wb_rd_row_a,wb_rd_first_row_s)
begin
fifo_wb_rd_addr_s <= (others => '0');
wb_rd_first_row_s <= (others => '0');
for i in (c_register_shift_size-1) downto 0 loop
if wb_rd_global_row_s(i) = '1' then
fifo_wb_rd_addr_s <= wb_rd_addr_shift_a(i)(g_BYTE_ADDR_WIDTH-1 downto 3) & "000" ;
wb_rd_first_row_s <= wb_rd_row_a(i);
end if;
end loop;
if((wb_rd_global_row_s /= wb_rd_first_row_s) and (wb_rd_global_row_s /= (wb_rd_global_row_s'range => '0'))) then
wb_rd_several_row_s <= '1';
else
wb_rd_several_row_s <= '0';
end if;
end process p_wb_read_rtl;
wb_rd_shifting_s <= --'0' when wb_rd_several_row_s = '1' else
'1' when wb_cyc_s = '1' and wb_stb_s = '1' and wb_we_s = '0' else--and wb_stall_s = '0' else
'1' when wb_read_wait_cnt = 0 else
'0';
wb_rd_global_row_s <= wb_rd_aligned_s and wb_rd_valid_shift_s;
wb_rd_flush_v_s <= wb_rd_first_row_s;
rd_match_g:for i in 0 to c_register_shift_size-1 generate
wb_rd_aligned_s(i) <= '1' when wb_rd_addr_shift_a(i)(2 downto 0) = std_logic_vector(to_unsigned(i,3)) else
'0';
rd_row_g:for j in 0 to c_register_shift_size-1 generate
wb_rd_row_a(i)(j) <= '1' when wb_rd_addr_shift_a(i)(g_BYTE_ADDR_WIDTH-1 downto 3) = wb_rd_addr_shift_a(j)(g_BYTE_ADDR_WIDTH-1 downto 3) and wb_rd_aligned_s(i) = '1' and wb_rd_aligned_s(j) = '1' and wb_rd_valid_shift_s(i) = '1' and wb_rd_valid_shift_s(j) = '1' else
'0';
end generate;
end generate;
p_wb_read_shift: process (wb_rd_shifting_s,wb_rd_addr_shift_a,wb_rd_valid_shift_s,wb_adr_s,wb_dat_s,wb_sel_s,wb_rd_flush_v_s)
begin
if(wb_rd_shifting_s = '1') then
wb_rd_addr_shift_next_a(c_register_shift_size-1) <= wb_adr_s(g_BYTE_ADDR_WIDTH-1 downto 0);
wb_rd_valid_shift_next_s(c_register_shift_size-1) <= wb_cyc_s and wb_stb_s and not wb_we_s;
for i in 1 to c_register_shift_size-1 loop
wb_rd_addr_shift_next_a(i-1) <= wb_rd_addr_shift_a(i);
if wb_rd_flush_v_s(i) = '0' then
wb_rd_valid_shift_next_s(i-1) <= wb_rd_valid_shift_s(i);
else
wb_rd_valid_shift_next_s(i-1) <= '0';
end if;
end loop;
else
for i in 0 to c_register_shift_size-1 loop
wb_rd_addr_shift_next_a(i) <= wb_rd_addr_shift_a(i);
if wb_rd_flush_v_s(i) = '0' then
wb_rd_valid_shift_next_s(i) <= wb_rd_valid_shift_s(i);
else
wb_rd_valid_shift_next_s(i) <= '0';
end if;
end loop;
end if;
end process p_wb_read_shift;
p_wb_read_data : process(wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
for i in 0 to c_register_shift_size-1 loop
wb_rd_data_shift_a(i) <= (others => '0');
wb_ack_shift_s(i) <= '0';
end loop;
elsif rising_edge(wb_clk_i) then
if(fifo_wb_rd_data_rd_s = '1') then
for i in 0 to c_register_shift_size-1 loop
wb_rd_data_shift_a(i) <= fifo_wb_rd_data_dout_s(63+(i*64) downto 0+(i*64));
wb_ack_shift_s(i) <= fifo_wb_rd_mask_dout_s(i); -- The data are reversed
end loop;
else
wb_rd_data_shift_a(c_register_shift_size-1) <= (others => '0');
wb_ack_shift_s(c_register_shift_size-1) <= '0';
for i in 0 to c_register_shift_size-2 loop
wb_rd_data_shift_a(i) <= wb_rd_data_shift_a(i+1);
wb_ack_shift_s(i) <= wb_ack_shift_s(i+1);
end loop;
end if;
end if;
end process p_wb_read_data;
fifo_rd_data_in : process (wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fifo_wb_rd_addr_din_s <= (others => '0');
fifo_wb_rd_mask_din_s <= (others => '0');
fifo_wb_rd_addr_wr_s <= '0';
fifo_wb_rd_mask_wr_s <= '0';
elsif rising_edge(wb_clk_i) then
fifo_wb_rd_addr_wr_s <= wb_rd_shift_flush_s;
fifo_wb_rd_mask_wr_s <= wb_rd_shift_flush_s;
fifo_wb_rd_addr_din_s <= fifo_wb_rd_addr_s;
fifo_wb_rd_mask_din_s <= fifo_wb_rd_addr_s & wb_rd_valid_shift_s;
end if;
end process;
fifo_wb_rd_data_rd_s <= '1' when wb_ack_shift_s(c_register_shift_size-1 downto 1) = "0000000" and fifo_wb_rd_mask_empty_s = '0' and fifo_wb_rd_data_empty_s = '0' else
'0';
fifo_wb_rd_mask_rd_s <= fifo_wb_rd_data_rd_s;
wb_dat_o <= wb_rd_data_shift_a(0);
wb_ack_s <= wb_ack_shift_s(0);
wb_rd_shift_flush_s <= '1' when wb_rd_flush_v_s /= (wb_rd_flush_v_s'range => '0') else
'0';
fifo_wb_read_addr : fifo_29x32
PORT MAP (
rst => rst_s,
wr_clk => wb_clk_i,
rd_clk => ddr_ui_clk_i,
din => fifo_wb_rd_addr_din_s,
wr_en => fifo_wb_rd_addr_wr_s,
rd_en => fifo_wb_rd_addr_rd_s,
dout => fifo_wb_rd_addr_dout_s,
full => fifo_wb_rd_addr_full_s,
almost_full => fifo_wb_rd_addr_almost_full_s,
empty => fifo_wb_rd_addr_empty_s
);
fifo_wb_read_mask : fifo_8x32
PORT MAP (
rst => rst_s,
wr_clk => wb_clk_i,
rd_clk => wb_clk_i,
din => fifo_wb_rd_mask_din_s(7 downto 0),
wr_en => fifo_wb_rd_mask_wr_s,
rd_en => fifo_wb_rd_mask_rd_s,
dout => fifo_wb_rd_mask_dout_s,
--dout(7 downto 0) => fifo_wb_rd_mask_dout_s,
--dout(36 downto 8) => open,--ddr_wb_rd_mask_addr_dout_do,
full => fifo_wb_rd_mask_full_s,
almost_full => fifo_wb_rd_mask_almost_full_s,
empty => fifo_wb_rd_mask_empty_s,
rd_data_count => fifo_wb_rd_mask_rd_data_count_s
);
fifo_wb_read_data : fifo_256x16
PORT MAP (
rst => rst_s,
wr_clk => ddr_ui_clk_i,
rd_clk => wb_clk_i,
din => fifo_wb_rd_data_din_s,
wr_en => fifo_wb_rd_data_wr_s,
rd_en => fifo_wb_rd_data_rd_s,
dout => fifo_wb_rd_data_dout_s,
full => fifo_wb_rd_data_full_s,
almost_full => fifo_wb_rd_data_almost_full_s,
empty => fifo_wb_rd_data_empty_s,
rd_data_count => fifo_wb_rd_data_rd_data_count_s
);
--------------------------------------
-- DDR CMD
--------------------------------------
ddr_addr_o <= fifo_wb_rd_addr_dout_s;
ddr_cmd_o <= "001";
ddr_cmd_en_o<= fifo_wb_rd_addr_rd_s;
ddr_req_o <= not fifo_wb_rd_addr_empty_s;
--------------------------------------
-- DDR Data in
--------------------------------------
fifo_wb_rd_addr_rd_s <= ddr_rdy_i and (not fifo_wb_rd_addr_empty_s) and (not fifo_wb_rd_data_almost_full_s) and ddr_gnt_i; -- and (not fifo_wb_rd_mask_full_s);
fifo_wb_rd_data_wr_s <= ddr_rd_data_valid_i and ddr_rd_data_end_i;
fifo_wb_rd_data_din_s <= ddr_rd_data_i;
end Behavioral;
| gpl-3.0 | 187f967a5d17259d3742c23d56624440 | 0.49379 | 3.096747 | false | false | false | false |
Yarr/Yarr-fw | rtl/spartan6/ddr3-core/ddr3_ctrl_pkg.vhd | 2 | 11,365 | --==============================================================================
--! @file ddr3_ctrl_pkg.vhd
--==============================================================================
--! Standard library
library IEEE;
--! Standard packages
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--! Specific packages
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- DDR3 Controller Package
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--! @brief
--! DDR3 controller package
--------------------------------------------------------------------------------
--! @details
--! Contains DDR3 controller core top level component declaration.
--------------------------------------------------------------------------------
--! @version
--! 0.1 | mc | 12.08.2011 | File creation and Doxygen comments
--!
--! @author
--! mc : Matthieu Cattin, CERN (BE-CO-HT)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
--==============================================================================
--! Entity declaration for ddr3_ctrl_pkg
--==============================================================================
package ddr3_ctrl_pkg is
--==============================================================================
--! Functions declaration
--==============================================================================
function log2_ceil(N : natural) return positive;
--==============================================================================
--! Components declaration
--==============================================================================
component ddr3_ctrl
generic(
--! Bank and port size selection
g_BANK_PORT_SELECT : string := "BANK3_32B_32B";
--! Core's clock period in ps
g_MEMCLK_PERIOD : integer := 3000;
--! If TRUE, uses Xilinx calibration core (Input term, DQS centering)
g_CALIB_SOFT_IP : string := "TRUE";
--! User ports addresses maping (BANK_ROW_COLUMN or ROW_BANK_COLUMN)
g_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
--! Simulation mode
g_SIMULATION : string := "FALSE";
--! DDR3 data port width
g_NUM_DQ_PINS : integer := 16;
--! DDR3 address port width
g_MEM_ADDR_WIDTH : integer := 14;
--! DDR3 bank address width
g_MEM_BANKADDR_WIDTH : integer := 3;
--! Wishbone port 0 data mask size (8-bit granularity)
g_P0_MASK_SIZE : integer := 4;
--! Wishbone port 0 data width
g_P0_DATA_PORT_SIZE : integer := 32;
--! Port 0 byte address width
g_P0_BYTE_ADDR_WIDTH : integer := 30;
--! Wishbone port 1 data mask size (8-bit granularity)
g_P1_MASK_SIZE : integer := 4;
--! Wishbone port 1 data width
g_P1_DATA_PORT_SIZE : integer := 32;
--! Port 1 byte address width
g_P1_BYTE_ADDR_WIDTH : integer := 30
);
port(
----------------------------------------------------------------------------
-- Clock, control and status
----------------------------------------------------------------------------
--! Clock input
clk_i : in std_logic;
--! Reset input (active low)
rst_n_i : in std_logic;
--! Status output
status_o : out std_logic_vector(31 downto 0);
----------------------------------------------------------------------------
-- DDR3 interface
----------------------------------------------------------------------------
--! DDR3 data bus
ddr3_dq_b : inout std_logic_vector(g_NUM_DQ_PINS-1 downto 0);
--! DDR3 address bus
ddr3_a_o : out std_logic_vector(g_MEM_ADDR_WIDTH-1 downto 0);
--! DDR3 bank address
ddr3_ba_o : out std_logic_vector(g_MEM_BANKADDR_WIDTH-1 downto 0);
--! DDR3 row address strobe
ddr3_ras_n_o : out std_logic;
--! DDR3 column address strobe
ddr3_cas_n_o : out std_logic;
--! DDR3 write enable
ddr3_we_n_o : out std_logic;
--! DDR3 on-die termination
ddr3_odt_o : out std_logic;
--! DDR3 reset
ddr3_rst_n_o : out std_logic;
--! DDR3 clock enable
ddr3_cke_o : out std_logic;
--! DDR3 lower byte data mask
ddr3_dm_o : out std_logic;
--! DDR3 upper byte data mask
ddr3_udm_o : out std_logic;
--! DDR3 lower byte data strobe (pos)
ddr3_dqs_p_b : inout std_logic;
--! DDR3 lower byte data strobe (neg)
ddr3_dqs_n_b : inout std_logic;
--! DDR3 upper byte data strobe (pos)
ddr3_udqs_p_b : inout std_logic;
--! DDR3 upper byte data strobe (pos)
ddr3_udqs_n_b : inout std_logic;
--! DDR3 clock (pos)
ddr3_clk_p_o : out std_logic;
--! DDR3 clock (neg)
ddr3_clk_n_o : out std_logic;
--! MCB internal termination calibration resistor
ddr3_rzq_b : inout std_logic;
--! MCB internal termination calibration
ddr3_zio_b : inout std_logic;
----------------------------------------------------------------------------
-- Wishbone bus - Port 0
----------------------------------------------------------------------------
--! Wishbone bus clock
wb0_clk_i : in std_logic;
--! Wishbone bus byte select
wb0_sel_i : in std_logic_vector(g_P0_MASK_SIZE - 1 downto 0);
--! Wishbone bus cycle select
wb0_cyc_i : in std_logic;
--! Wishbone bus cycle strobe
wb0_stb_i : in std_logic;
--! Wishbone bus write enable
wb0_we_i : in std_logic;
--! Wishbone bus address
wb0_addr_i : in std_logic_vector(31 downto 0);
--! Wishbone bus data input
wb0_data_i : in std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
--! Wishbone bus data output
wb0_data_o : out std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
--! Wishbone bus acknowledge
wb0_ack_o : out std_logic;
--! Wishbone bus stall (for pipelined mode)
wb0_stall_o : out std_logic;
----------------------------------------------------------------------------
-- Status - Port 0
----------------------------------------------------------------------------
--! Command FIFO empty
p0_cmd_empty_o : out std_logic;
--! Command FIFO full
p0_cmd_full_o : out std_logic;
--! Read FIFO full
p0_rd_full_o : out std_logic;
--! Read FIFO empty
p0_rd_empty_o : out std_logic;
--! Read FIFO count
p0_rd_count_o : out std_logic_vector(6 downto 0);
--! Read FIFO overflow
p0_rd_overflow_o : out std_logic;
--! Read FIFO error (pointers unsynchronized, reset required)
p0_rd_error_o : out std_logic;
--! Write FIFO full
p0_wr_full_o : out std_logic;
--! Write FIFO empty
p0_wr_empty_o : out std_logic;
--! Write FIFO count
p0_wr_count_o : out std_logic_vector(6 downto 0);
--! Write FIFO underrun
p0_wr_underrun_o : out std_logic;
--! Write FIFO error (pointers unsynchronized, reset required)
p0_wr_error_o : out std_logic;
----------------------------------------------------------------------------
-- Wishbone bus - Port 1
----------------------------------------------------------------------------
--! Wishbone bus clock
wb1_clk_i : in std_logic;
--! Wishbone bus byte select
wb1_sel_i : in std_logic_vector(g_P1_MASK_SIZE - 1 downto 0);
--! Wishbone bus cycle select
wb1_cyc_i : in std_logic;
--! Wishbone bus cycle strobe
wb1_stb_i : in std_logic;
--! Wishbone bus write enable
wb1_we_i : in std_logic;
--! Wishbone bus address
wb1_addr_i : in std_logic_vector(31 downto 0);
--! Wishbone bus data input
wb1_data_i : in std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0);
--! Wishbone bus data output
wb1_data_o : out std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0);
--! Wishbone bus acknowledge
wb1_ack_o : out std_logic;
--! Wishbone bus stall (for pipelined mode)
wb1_stall_o : out std_logic;
----------------------------------------------------------------------------
-- Status - Port 1
----------------------------------------------------------------------------
--! Command FIFO empty
p1_cmd_empty_o : out std_logic;
--! Command FIFO full
p1_cmd_full_o : out std_logic;
--! Read FIFO full
p1_rd_full_o : out std_logic;
--! Read FIFO empty
p1_rd_empty_o : out std_logic;
--! Read FIFO count
p1_rd_count_o : out std_logic_vector(6 downto 0);
--! Read FIFO overflow
p1_rd_overflow_o : out std_logic;
--! Read FIFO error (pointers unsynchronized, reset required)
p1_rd_error_o : out std_logic;
--! Write FIFO full
p1_wr_full_o : out std_logic;
--! Write FIFO empty
p1_wr_empty_o : out std_logic;
--! Write FIFO count
p1_wr_count_o : out std_logic_vector(6 downto 0);
--! Write FIFO underrun
p1_wr_underrun_o : out std_logic;
--! Write FIFO error (pointers unsynchronized, reset required)
p1_wr_error_o : out std_logic
);
end component ddr3_ctrl;
end ddr3_ctrl_pkg;
package body ddr3_ctrl_pkg is
-----------------------------------------------------------------------------
-- Returns log of 2 of a natural number
-----------------------------------------------------------------------------
function log2_ceil(N : natural) return positive is
begin
if N <= 2 then
return 1;
elsif N mod 2 = 0 then
return 1 + log2_ceil(N/2);
else
return 1 + log2_ceil((N+1)/2);
end if;
end;
end ddr3_ctrl_pkg;
| gpl-3.0 | 286e2bec210e772bdd35b3fdf36243f6 | 0.443027 | 4.406747 | false | false | false | false |
Yarr/Yarr-fw | syn/kintex7/bram_yarr_trenz.vhd | 1 | 24,774 | ----------------------------------------------------------------------------------
-- Company: LBNL
-- Engineer: Arnaud Sautaux
--
-- Create Date: 09/27/2016 04:46:45 PM
-- Design Name: YARR Top Level BRAM version
-- Module Name: top_level - Behavioral
-- Project Name: YARR
-- Target Devices: XC7k160T
-- Tool Versions: Vivado v2016.2 (64-bit)
-- Description: The YARR top level for the BRAM version
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
library work;
use work.app_pkg.all;
use work.board_pkg.all;
entity top_level is
Port ( ---------------------------------------------------------------------------
-- Xilinx Hard IP Interface
-- . Clock and Resets
pcie_clk_p : in std_logic;
pcie_clk_n : in std_logic;
clk200_n : in STD_LOGIC;
clk200_p : in STD_LOGIC;
--rst_n_i : in STD_LOGIC;
sys_rst_n_i : in STD_LOGIC;
-- . Serial I/F
pci_exp_txn : out std_logic_vector(4-1 downto 0);--output wire [4 -1:0] pci_exp_txn ,
pci_exp_txp : out std_logic_vector(4-1 downto 0);--output wire [4 -1:0] pci_exp_txp ,
pci_exp_rxn : in std_logic_vector(4-1 downto 0);--input wire [4 -1:0] pci_exp_rxn ,
pci_exp_rxp : in std_logic_vector(4-1 downto 0);
-- . IO
--usr_sw_i : in STD_LOGIC_VECTOR (2 downto 0);
usr_led_o : out STD_LOGIC_VECTOR (0 downto 0);
--front_led_o : out STD_LOGIC_VECTOR (3 downto 0);
---------------------------------------------------------
-- FMC
---------------------------------------------------------
-- Trigger input
--ext_trig_i_p : in std_logic_vector(0 downto 0);
--ext_trig_i_n : in std_logic_vector(0 downto 0);
--ext_busy_o_p : out std_logic;
--ext_busy_o_n : out std_logic;
-- LVDS buffer
--pwdn_l : out std_logic_vector(2 downto 0);
-- GPIO
--io : inout std_logic_vector(2 downto 0);
-- FE-I4
fe_clk_p : out std_logic_vector(c_TX_CHANNELS-1 downto 0);
fe_clk_n : out std_logic_vector(c_TX_CHANNELS-1 downto 0);
fe_cmd_p : out std_logic_vector(c_TX_CHANNELS-1 downto 0);
fe_cmd_n : out std_logic_vector(c_TX_CHANNELS-1 downto 0);
fe_data_p : in std_logic_vector((c_RX_CHANNELS*c_RX_NUM_LANES)-1 downto 0);
fe_data_n : in std_logic_vector((c_RX_CHANNELS*c_RX_NUM_LANES)-1 downto 0);
-- I2c
--sda_io : inout std_logic;
--scl_io : inout std_logic;
-- EUDET TLU
--eudet_trig_p : in std_logic;
--eudet_trig_n : in std_logic;
--eudet_busy_p : out std_logic;
--eudet_busy_n : out std_logic;
--eudet_rst_p : in std_logic;
--eudet_rst_n : in std_logic;
--eudet_clk_p : out std_logic;
--eudet_clk_n : out std_logic;
-- SPI
scl_o : out std_logic;
sda_o : out std_logic;
sdi_i : in std_logic;
latch_o : out std_logic
-- . DDR3
-- ddr3_dq : inout std_logic_vector(63 downto 0);
-- ddr3_dqs_p : inout std_logic_vector(7 downto 0);
-- ddr3_dqs_n : inout std_logic_vector(7 downto 0);
-- ddr3_addr : out std_logic_vector(14 downto 0);
-- ddr3_ba : out std_logic_vector(2 downto 0);
-- ddr3_ras_n : out std_logic;
-- ddr3_cas_n : out std_logic;
-- ddr3_we_n : out std_logic;
-- ddr3_reset_n : out std_logic;
-- ddr3_ck_p : out std_logic_vector(0 downto 0);
-- ddr3_ck_n : out std_logic_vector(0 downto 0);
-- ddr3_cke : out std_logic_vector(0 downto 0);
-- ddr3_cs_n : out std_logic_vector(0 downto 0);
-- ddr3_dm : out std_logic_vector(7 downto 0);
-- ddr3_odt : out std_logic_vector(0 downto 0)
);
end top_level;
architecture Behavioral of top_level is
constant AXI_BUS_WIDTH : integer := 64;
COMPONENT pcie_7x_0
PORT (
pci_exp_txp : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
pci_exp_txn : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
pci_exp_rxp : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
pci_exp_rxn : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
user_clk_out : OUT STD_LOGIC;
user_reset_out : OUT STD_LOGIC;
user_lnk_up : OUT STD_LOGIC;
user_app_rdy : OUT STD_LOGIC;
tx_buf_av : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
tx_cfg_req : OUT STD_LOGIC;
tx_err_drop : OUT STD_LOGIC;
s_axis_tx_tready : OUT STD_LOGIC;
s_axis_tx_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_tx_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tx_tlast : IN STD_LOGIC;
s_axis_tx_tvalid : IN STD_LOGIC;
s_axis_tx_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_rx_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_rx_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_rx_tlast : OUT STD_LOGIC;
m_axis_rx_tvalid : OUT STD_LOGIC;
m_axis_rx_tready : IN STD_LOGIC;
m_axis_rx_tuser : OUT STD_LOGIC_VECTOR(21 DOWNTO 0);
cfg_status : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_command : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_dstatus : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_dcommand : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_lstatus : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_lcommand : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_dcommand2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_pcie_link_state : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_pmcsr_pme_en : OUT STD_LOGIC;
cfg_pmcsr_powerstate : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
cfg_pmcsr_pme_status : OUT STD_LOGIC;
cfg_received_func_lvl_rst : OUT STD_LOGIC;
cfg_interrupt : IN STD_LOGIC;
cfg_interrupt_rdy : OUT STD_LOGIC;
cfg_interrupt_assert : IN STD_LOGIC;
cfg_interrupt_di : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_interrupt_do : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_interrupt_mmenable : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_interrupt_msienable : OUT STD_LOGIC;
cfg_interrupt_msixenable : OUT STD_LOGIC;
cfg_interrupt_msixfm : OUT STD_LOGIC;
cfg_interrupt_stat : IN STD_LOGIC;
cfg_pciecap_interrupt_msgnum : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
cfg_to_turnoff : OUT STD_LOGIC;
cfg_bus_number : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_device_number : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
cfg_function_number : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_msg_received : OUT STD_LOGIC;
cfg_msg_data : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_bridge_serr_en : OUT STD_LOGIC;
cfg_slot_control_electromech_il_ctl_pulse : OUT STD_LOGIC;
cfg_root_control_syserr_corr_err_en : OUT STD_LOGIC;
cfg_root_control_syserr_non_fatal_err_en : OUT STD_LOGIC;
cfg_root_control_syserr_fatal_err_en : OUT STD_LOGIC;
cfg_root_control_pme_int_en : OUT STD_LOGIC;
cfg_aer_rooterr_corr_err_reporting_en : OUT STD_LOGIC;
cfg_aer_rooterr_non_fatal_err_reporting_en : OUT STD_LOGIC;
cfg_aer_rooterr_fatal_err_reporting_en : OUT STD_LOGIC;
cfg_aer_rooterr_corr_err_received : OUT STD_LOGIC;
cfg_aer_rooterr_non_fatal_err_received : OUT STD_LOGIC;
cfg_aer_rooterr_fatal_err_received : OUT STD_LOGIC;
cfg_msg_received_err_cor : OUT STD_LOGIC;
cfg_msg_received_err_non_fatal : OUT STD_LOGIC;
cfg_msg_received_err_fatal : OUT STD_LOGIC;
cfg_msg_received_pm_as_nak : OUT STD_LOGIC;
cfg_msg_received_pm_pme : OUT STD_LOGIC;
cfg_msg_received_pme_to_ack : OUT STD_LOGIC;
cfg_msg_received_assert_int_a : OUT STD_LOGIC;
cfg_msg_received_assert_int_b : OUT STD_LOGIC;
cfg_msg_received_assert_int_c : OUT STD_LOGIC;
cfg_msg_received_assert_int_d : OUT STD_LOGIC;
cfg_msg_received_deassert_int_a : OUT STD_LOGIC;
cfg_msg_received_deassert_int_b : OUT STD_LOGIC;
cfg_msg_received_deassert_int_c : OUT STD_LOGIC;
cfg_msg_received_deassert_int_d : OUT STD_LOGIC;
cfg_msg_received_setslotpowerlimit : OUT STD_LOGIC;
cfg_vc_tcvc_map : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
sys_clk : IN STD_LOGIC;
sys_rst_n : IN STD_LOGIC
);
END COMPONENT;
component app is
Generic(
DEBUG_C : std_logic_vector(3 downto 0) := "0000";
address_mask_c : STD_LOGIC_VECTOR(32-1 downto 0) := X"000FFFFF";
DMA_MEMORY_SELECTED : string := "BRAM" -- DDR3, BRAM, DEMUX
);
Port ( clk_i : in STD_LOGIC;
sys_clk_n_i : IN STD_LOGIC;
sys_clk_p_i : IN STD_LOGIC;
rst_i : in STD_LOGIC;
user_lnk_up_i : in STD_LOGIC;
user_app_rdy_i : in STD_LOGIC;
-- AXI-Stream bus
m_axis_tx_tready_i : in STD_LOGIC;
m_axis_tx_tdata_o : out STD_LOGIC_VECTOR(AXI_BUS_WIDTH-1 DOWNTO 0);
m_axis_tx_tkeep_o : out STD_LOGIC_VECTOR(AXI_BUS_WIDTH/8-1 DOWNTO 0);
m_axis_tx_tlast_o : out STD_LOGIC;
m_axis_tx_tvalid_o : out STD_LOGIC;
m_axis_tx_tuser_o : out STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_rx_tdata_i : in STD_LOGIC_VECTOR(AXI_BUS_WIDTH-1 DOWNTO 0);
s_axis_rx_tkeep_i : in STD_LOGIC_VECTOR(AXI_BUS_WIDTH/8-1 DOWNTO 0);
s_axis_rx_tlast_i : in STD_LOGIC;
s_axis_rx_tvalid_i : in STD_LOGIC;
s_axis_rx_tready_o : out STD_LOGIC;
s_axis_rx_tuser_i : in STD_LOGIC_VECTOR(21 DOWNTO 0);
-- PCIe interrupt config
cfg_interrupt_o : out STD_LOGIC;
cfg_interrupt_rdy_i : in STD_LOGIC;
cfg_interrupt_assert_o : out STD_LOGIC;
cfg_interrupt_di_o : out STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_interrupt_do_i : in STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_interrupt_mmenable_i : in STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_interrupt_msienable_i : in STD_LOGIC;
cfg_interrupt_msixenable_i : in STD_LOGIC;
cfg_interrupt_msixfm_i : in STD_LOGIC;
cfg_interrupt_stat_o : out STD_LOGIC;
cfg_pciecap_interrupt_msgnum_o : out STD_LOGIC_VECTOR(4 DOWNTO 0);
-- PCIe ID
cfg_bus_number_i : in STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_device_number_i : in STD_LOGIC_VECTOR(4 DOWNTO 0);
cfg_function_number_i : in STD_LOGIC_VECTOR(2 DOWNTO 0);
-- PCIe debug
tx_err_drop_i : in STD_LOGIC;
cfg_dstatus_i : in STD_LOGIC_VECTOR(15 DOWNTO 0);
--DDR3
ddr3_dq_io : inout std_logic_vector(63 downto 0);
ddr3_dqs_p_io : inout std_logic_vector(7 downto 0);
ddr3_dqs_n_io : inout std_logic_vector(7 downto 0);
--init_calib_complete_o : out std_logic;
ddr3_addr_o : out std_logic_vector(14 downto 0);
ddr3_ba_o : out std_logic_vector(2 downto 0);
ddr3_ras_n_o : out std_logic;
ddr3_cas_n_o : out std_logic;
ddr3_we_n_o : out std_logic;
ddr3_reset_n_o : out std_logic;
ddr3_ck_p_o : out std_logic_vector(0 downto 0);
ddr3_ck_n_o : out std_logic_vector(0 downto 0);
ddr3_cke_o : out std_logic_vector(0 downto 0);
ddr3_cs_n_o : out std_logic_vector(0 downto 0);
ddr3_dm_o : out std_logic_vector(7 downto 0);
ddr3_odt_o : out std_logic_vector(0 downto 0);
---------------------------------------------------------
-- FMC
---------------------------------------------------------
-- Trigger input
ext_trig_i : in std_logic_vector(3 downto 0);
--ext_busy_o : out std_logic;
-- LVDS buffer
pwdn_l : out std_logic_vector(2 downto 0);
-- GPIO
--io : inout std_logic_vector(2 downto 0);
-- FE-I4
fe_clk_p : out std_logic_vector(c_TX_CHANNELS-1 downto 0);
fe_clk_n : out std_logic_vector(c_TX_CHANNELS-1 downto 0);
fe_cmd_p : out std_logic_vector(c_TX_CHANNELS-1 downto 0);
fe_cmd_n : out std_logic_vector(c_TX_CHANNELS-1 downto 0);
fe_data_p : in std_logic_vector((c_RX_CHANNELS*c_RX_NUM_LANES)-1 downto 0);
fe_data_n : in std_logic_vector((c_RX_CHANNELS*c_RX_NUM_LANES)-1 downto 0);
-- I2c
sda_io : inout std_logic;
scl_io : inout std_logic;
-- EUDET
eudet_clk_o : out std_logic;
eudet_trig_i : in std_logic;
eudet_rst_i : in std_logic;
eudet_busy_o : out std_logic;
-- SPI
scl_o : out std_logic;
sda_o : out std_logic;
sdi_i : in std_logic;
latch_o : out std_logic;
--I/O
usr_sw_i : in STD_LOGIC_VECTOR (2 downto 0);
usr_led_o : out STD_LOGIC_VECTOR (3 downto 0);
front_led_o : out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
--Clocks
signal sys_clk : STD_LOGIC;
--signal clk200 : STD_LOGIC;
signal aclk : STD_LOGIC;
signal arstn_s : STD_LOGIC;
signal rst_s : STD_LOGIC;
--Wishbone bus
signal usr_led_s : std_logic_vector(3 downto 0);
--signal count_s : STD_LOGIC_VECTOR (28 downto 0);
-- AXI-stream bus to PCIE
signal s_axis_tx_tready_s : STD_LOGIC;
signal s_axis_tx_tdata_s : STD_LOGIC_VECTOR(AXI_BUS_WIDTH-1 DOWNTO 0);
signal s_axis_tx_tkeep_s : STD_LOGIC_VECTOR(AXI_BUS_WIDTH/8-1 DOWNTO 0);
signal s_axis_tx_tlast_s : STD_LOGIC;
signal s_axis_tx_tvalid_s : STD_LOGIC;
signal s_axis_tx_tuser_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal m_axis_rx_tdata_s : STD_LOGIC_VECTOR(AXI_BUS_WIDTH-1 DOWNTO 0);
signal m_axis_rx_tkeep_s : STD_LOGIC_VECTOR(AXI_BUS_WIDTH/8-1 DOWNTO 0);
signal m_axis_rx_tlast_s : STD_LOGIC;
signal m_axis_rx_tvalid_s : STD_LOGIC;
signal m_axis_rx_tready_s : STD_LOGIC;
signal m_axis_rx_tuser_s : STD_LOGIC_VECTOR(21 DOWNTO 0);
-- PCIE signals
signal user_lnk_up_s : STD_LOGIC;
signal user_app_rdy_s : STD_LOGIC;
signal tx_err_drop_s : STD_LOGIC;
signal cfg_interrupt_s : STD_LOGIC;
signal cfg_interrupt_rdy_s : STD_LOGIC;
signal cfg_interrupt_assert_s : STD_LOGIC;
signal cfg_interrupt_di_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal cfg_interrupt_do_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal cfg_interrupt_mmenable_s : STD_LOGIC_VECTOR(2 DOWNTO 0);
signal cfg_interrupt_msienable_s : STD_LOGIC;
signal cfg_interrupt_msixenable_s : STD_LOGIC;
signal cfg_interrupt_msixfm_s : STD_LOGIC;
signal cfg_interrupt_stat_s : STD_LOGIC;
signal cfg_pciecap_interrupt_msgnum_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
-- PCIE ID
signal cfg_bus_number_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal cfg_device_number_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
signal cfg_function_number_s : STD_LOGIC_VECTOR(2 DOWNTO 0);
--PCIE debug
signal cfg_dstatus_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
-- EUDET
signal eudet_clk_s : std_logic;
signal eudet_trig_s : std_logic;
signal eudet_busy_s : std_logic;
signal eudet_rst_s : std_logic;
signal ext_trig_i : std_logic_vector(3 downto 0);
signal ext_busy_o : std_logic;
begin
-- LVDS input to internal single
-- CLK_IBUFDS : IBUFDS
-- generic map(
-- IOSTANDARD => "DEFAULT"
-- )
-- port map(
-- I => clk200_p,
-- IB => clk200_n,
-- O => clk200
-- );
-- design_1_0: component design_1
-- port map (
-- CLK_IN_D_clk_n(0) => pcie_clk_n,
-- CLK_IN_D_clk_p(0) => pcie_clk_p,
-- IBUF_OUT(0) => sys_clk
-- );
-- EUDET buffer
--eudet_clk_buf : OBUFDS port map (O => eudet_clk_p, OB => eudet_clk_n, I => eudet_clk_s);
--eudet_busy_buf : OBUFDS port map (O => eudet_busy_p, OB => eudet_busy_n, I => eudet_busy_s);
--eudet_rst_buf : IBUFDS generic map(DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => eudet_rst_s, I => eudet_rst_p, IB => eudet_rst_n);
--eudet_trig_buf : IBUFDS generic map(DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => eudet_trig_s, I => eudet_trig_p, IB => eudet_trig_n);
-- HitOr
--ext_trig_buf_0 : IBUFDS generic map (DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => ext_trig_i(0), I => ext_trig_i_p(0), IB => ext_trig_i_n(0));
--ext_trig_buf_1 : IBUFDS generic map (DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => ext_trig_i(1), I => ext_trig_i_p(1), IB => ext_trig_i_n(1));
--ext_trig_buf_2 : IBUFDS generic map (DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => ext_trig_i(2), I => ext_trig_i_p(2), IB => ext_trig_i_n(2));
--ext_trig_buf_3 : IBUFDS generic map (DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => ext_trig_i(3), I => ext_trig_i_p(3), IB => ext_trig_i_n(3));
--ext_busy_buf : OBUFDS port map (O => ext_busy_o_p, OB => ext_busy_o_n, I => ext_busy_o);
refclk_ibuf : IBUFDS_GTE2
port map(
O => sys_clk,
ODIV2 => open,
I => pcie_clk_p,
IB => pcie_clk_n,
CEB => '0');
rst_s <= not sys_rst_n_i;
arstn_s <= sys_rst_n_i;-- or rst_n_i;
pcie_0 : pcie_7x_0
PORT MAP (
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
user_clk_out => aclk,
user_reset_out => open, -- TODO
user_lnk_up => user_lnk_up_s,
user_app_rdy => user_app_rdy_s,
tx_err_drop => tx_err_drop_s,
s_axis_tx_tready => s_axis_tx_tready_s,
s_axis_tx_tdata => s_axis_tx_tdata_s,
s_axis_tx_tkeep => s_axis_tx_tkeep_s,
s_axis_tx_tlast => s_axis_tx_tlast_s,
s_axis_tx_tvalid => s_axis_tx_tvalid_s,
s_axis_tx_tuser => s_axis_tx_tuser_s,
m_axis_rx_tdata => m_axis_rx_tdata_s,
m_axis_rx_tkeep => m_axis_rx_tkeep_s,
m_axis_rx_tlast => m_axis_rx_tlast_s,
m_axis_rx_tvalid => m_axis_rx_tvalid_s,
m_axis_rx_tready => m_axis_rx_tready_s,
m_axis_rx_tuser => m_axis_rx_tuser_s,
cfg_interrupt => cfg_interrupt_s,
cfg_interrupt_rdy => cfg_interrupt_rdy_s,
cfg_interrupt_assert => cfg_interrupt_assert_s,
cfg_interrupt_di => cfg_interrupt_di_s,
cfg_interrupt_do => cfg_interrupt_do_s,
cfg_interrupt_mmenable => cfg_interrupt_mmenable_s,
cfg_interrupt_msienable => cfg_interrupt_msienable_s,
cfg_interrupt_msixenable => cfg_interrupt_msixenable_s,
cfg_interrupt_msixfm => cfg_interrupt_msixfm_s,
cfg_interrupt_stat => cfg_interrupt_stat_s,
cfg_pciecap_interrupt_msgnum => cfg_pciecap_interrupt_msgnum_s,
cfg_dstatus => cfg_dstatus_s,
cfg_bus_number => cfg_bus_number_s,
cfg_device_number => cfg_device_number_s,
cfg_function_number => cfg_function_number_s,
sys_clk => sys_clk,
sys_rst_n => sys_rst_n_i
);
app_0:app
Generic map(
DEBUG_C => "0000",
address_mask_c => X"000FFFFF",
DMA_MEMORY_SELECTED => "BRAM" -- DDR3, BRAM
)
port map(
clk_i => aclk,
sys_clk_n_i => clk200_n,
sys_clk_p_i => clk200_p,
rst_i => rst_s,
user_lnk_up_i => user_lnk_up_s,
user_app_rdy_i => user_app_rdy_s,
-- AXI-Stream bus
m_axis_tx_tready_i => s_axis_tx_tready_s,
m_axis_tx_tdata_o => s_axis_tx_tdata_s,
m_axis_tx_tkeep_o => s_axis_tx_tkeep_s,
m_axis_tx_tlast_o => s_axis_tx_tlast_s,
m_axis_tx_tvalid_o => s_axis_tx_tvalid_s,
m_axis_tx_tuser_o => s_axis_tx_tuser_s,
s_axis_rx_tdata_i => m_axis_rx_tdata_s,
s_axis_rx_tkeep_i => m_axis_rx_tkeep_s,
s_axis_rx_tlast_i => m_axis_rx_tlast_s,
s_axis_rx_tvalid_i => m_axis_rx_tvalid_s,
s_axis_rx_tready_o => m_axis_rx_tready_s,
s_axis_rx_tuser_i => m_axis_rx_tuser_s,
-- PCIe interrupt config
cfg_interrupt_o => cfg_interrupt_s,
cfg_interrupt_rdy_i => cfg_interrupt_rdy_s,
cfg_interrupt_assert_o => cfg_interrupt_assert_s,
cfg_interrupt_di_o => cfg_interrupt_di_s,
cfg_interrupt_do_i => cfg_interrupt_do_s,
cfg_interrupt_mmenable_i => cfg_interrupt_mmenable_s,
cfg_interrupt_msienable_i => cfg_interrupt_msienable_s,
cfg_interrupt_msixenable_i => cfg_interrupt_msixenable_s,
cfg_interrupt_msixfm_i => cfg_interrupt_msixfm_s,
cfg_interrupt_stat_o => cfg_interrupt_stat_s,
cfg_pciecap_interrupt_msgnum_o => cfg_pciecap_interrupt_msgnum_s,
-- PCIe ID
cfg_bus_number_i => cfg_bus_number_s,
cfg_device_number_i => cfg_device_number_s,
cfg_function_number_i => cfg_function_number_s,
-- PCIe debug
tx_err_drop_i => tx_err_drop_s,
cfg_dstatus_i => cfg_dstatus_s,
--DDR3
--ddr3_dq_io => ddr3_dq,
--ddr3_dqs_p_io => ddr3_dqs_p,
--ddr3_dqs_n_io => ddr3_dqs_n,
--init_calib_complete_o => init_calib_complete,
--ddr3_addr_o => ddr3_addr,
--ddr3_ba_o => ddr3_ba,
--ddr3_ras_n_o => ddr3_ras_n,
--ddr3_cas_n_o => ddr3_cas_n,
--ddr3_we_n_o => ddr3_we_n,
--ddr3_reset_n_o => ddr3_reset_n,
--ddr3_ck_p_o => ddr3_ck_p,
--ddr3_ck_n_o => ddr3_ck_n,
--ddr3_cke_o => ddr3_cke,
--ddr3_cs_n_o => ddr3_cs_n,
--ddr3_dm_o => ddr3_dm,
--ddr3_odt_o => ddr3_odt,
---------------------------------------------------------
-- FMC
---------------------------------------------------------
-- Trigger input
ext_trig_i => ext_trig_i,
--ext_busy_o => ext_busy_o,
-- LVDS buffer
pwdn_l => open,
-- GPIO
--io => io,
-- FE-I4
fe_clk_p => fe_clk_p,
fe_clk_n => fe_clk_n,
fe_cmd_p => fe_cmd_p,
fe_cmd_n => fe_cmd_n,
fe_data_p => fe_data_p,
fe_data_n => fe_data_n,
-- I2c
--sda_io => sda_io,
--scl_io => scl_io,
--EUDET
eudet_clk_o => eudet_clk_s,
eudet_trig_i => eudet_trig_s,
eudet_rst_i => not eudet_rst_s,
eudet_busy_o => eudet_busy_s,
--SPI
scl_o => scl_o,
sda_o => sda_o,
sdi_i => sdi_i,
latch_o => latch_o,
--I/O
usr_sw_i => "000",
usr_led_o => usr_led_s,
front_led_o => open--front_led_o
);
usr_led_o <= usr_led_s(0 downto 0);
end Behavioral;
| gpl-3.0 | a62c04b4bc0175b8b80af6a22e7e3fb1 | 0.510979 | 3.285676 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/conditional_waveforms/rule_501_test_input.fixed_upper.vhd | 1 | 400 |
architecture rtl of fifo is
begin
process
begin
var1 := '0' when rd_en = '1' ELSE '1';
var2 := '0' when rd_en = '1' else '1';
wr_en_a <= force '0' when rd_en = '1' ELSE '1';
wr_en_b <= force '0' when rd_en = '1' else '1';
end process;
concurrent_wr_en_a <= '0' when rd_en = '1' ELSE '1';
concurrent_wr_en_b <= '0' when rd_en = '1' ELSE '1';
end architecture rtl;
| gpl-3.0 | d39e6cd1281ac6f4b88ed06b5925212e | 0.54 | 2.564103 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/proc_common_v4_0/hdl/src/vhdl/basic_sfifo_fg.vhd | 2 | 46,121 | -------------------------------------------------------------------------------
-- basic_sfifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: basic_sfifo_fg.vhd
--
-- Description:
-- This HDL file implements a basic synchronous (single clock) fifo using the
-- FIFO Generator tool. It is intended to offer a simple interface to the user
-- with the complexity of the FIFO Generator interface hidden from the user.
--
-- Note that in normal op mode (not First Word Fall Through FWFT) the data count
-- output goes to zero when the FIFO goes full. This the way FIFO Generator works.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- basic_sfifo_fg.vhd
-- |
-- |-- fifo_generator_v8_2
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.0 $
-- Date: $3/07/2011$
--
-- History:
-- DET 3/07/2011 Initial Version
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.proc_common_pkg.log2;
use proc_common_v4_0.coregen_comp_defs.all;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
-------------------------------------------------------------------------------
entity basic_sfifo_fg is
generic (
C_DWIDTH : Integer := 32 ;
-- FIFO data Width (Read and write data ports are symetric)
C_DEPTH : Integer := 512 ;
-- FIFO Depth (set to power of 2)
C_HAS_DATA_COUNT : integer := 1 ;
-- 0 = Data Count output not needed
-- 1 = Data Count output needed
C_DATA_COUNT_WIDTH : integer := 10 ;
-- Data Count bit width (Max value is log2(C_DEPTH))
C_IMPLEMENTATION_TYPE : integer range 0 to 1 := 0;
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
C_MEMORY_TYPE : integer := 1;
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
C_PRELOAD_REGS : integer := 1;
-- 0 = normal
-- 1 = FWFT
C_PRELOAD_LATENCY : integer := 0;
-- 0 = FWFT
-- 1 = normal
C_USE_FWFT_DATA_COUNT : integer := 0;
-- 0 = normal
-- 1 for FWFT
C_SYNCHRONIZER_STAGE : integer := 2; -- valid values are 0 to 8;
C_FAMILY : string := "virtex6"
);
port (
CLK : IN std_logic := '0';
DIN : IN std_logic_vector(C_DWIDTH-1 DOWNTO 0) := (OTHERS => '0');
RD_EN : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_EN : IN std_logic := '0';
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
DOUT : OUT std_logic_vector(C_DWIDTH-1 DOWNTO 0);
EMPTY : OUT std_logic;
FULL : OUT std_logic
);
end entity basic_sfifo_fg;
architecture implementation of basic_sfifo_fg is
-- Constant Declarations ----------------------------------------------
Constant POINTER_WIDTH : integer := log2(C_DEPTH);
-- Constant zeros for programmable threshold inputs
Constant PROG_RDTHRESH_ZEROS : std_logic_vector(POINTER_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
Constant PROG_WRTHRESH_ZEROS : std_logic_vector(POINTER_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
begin --(architecture implementation)
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a basic Sync FIFO
--
-------------------------------------------------------------------------------
I_BASIC_SFIFO : fifo_generator_v11_0
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => C_DWIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0, -- n0
C_FAMILY => C_FAMILY,
C_HAS_ALMOST_EMPTY => 0, -- n0
C_HAS_ALMOST_FULL => 0, -- n0
C_HAS_BACKUP => 0, -- n0
C_HAS_DATA_COUNT => C_HAS_DATA_COUNT,
C_HAS_MEMINIT_FILE => 0, -- n0
C_HAS_OVERFLOW => 0, -- n0
C_HAS_RD_DATA_COUNT => 0, -- n0
C_HAS_RD_RST => 0, -- n0
C_HAS_RST => 0, -- n0
C_HAS_SRST => 1, -- yes
C_HAS_UNDERFLOW => 0, -- n0
C_HAS_VALID => 0, -- n0
C_HAS_WR_ACK => 0, -- n0
C_HAS_WR_DATA_COUNT => 0, -- n0
C_HAS_WR_RST => 0, -- n0
C_IMPLEMENTATION_TYPE => 0, -- Common clock BRAM
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => C_MEMORY_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY,
C_PRELOAD_REGS => C_PRELOAD_REGS,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 0,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 0,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 0,
C_PROG_FULL_THRESH_NEGATE_VAL => 0,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH,
C_RD_DEPTH => C_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => POINTER_WIDTH,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH,
C_WR_DEPTH => C_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => POINTER_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_USE_ECC => 0,
C_FULL_FLAGS_RST_VAL => 0,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_HAS_INT_CLK => 0,
C_MSGON_VAL => 1,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
BACKUP => '0',
BACKUP_MARKER => '0',
CLK => CLK,
RST => '0',
SRST => SRST,
WR_CLK => '0',
WR_RST => '0',
RD_CLK => '0',
RD_RST => '0',
DIN => DIN, -- uses this one
WR_EN => WR_EN, -- uses this one
RD_EN => RD_EN, -- uses this one
PROG_EMPTY_THRESH => PROG_RDTHRESH_ZEROS,
PROG_EMPTY_THRESH_ASSERT => PROG_RDTHRESH_ZEROS,
PROG_EMPTY_THRESH_NEGATE => PROG_RDTHRESH_ZEROS,
PROG_FULL_THRESH => PROG_WRTHRESH_ZEROS,
PROG_FULL_THRESH_ASSERT => PROG_WRTHRESH_ZEROS,
PROG_FULL_THRESH_NEGATE => PROG_WRTHRESH_ZEROS,
INT_CLK => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
DOUT => DOUT, -- uses this one
FULL => FULL, -- uses this one
ALMOST_FULL => open,
WR_ACK => open,
OVERFLOW => open,
EMPTY => EMPTY, -- uses this one
ALMOST_EMPTY => open,
VALID => open,
UNDERFLOW => open,
DATA_COUNT => DATA_COUNT, -- uses this one
RD_DATA_COUNT => open,
WR_DATA_COUNT => open,
PROG_FULL => open,
PROG_EMPTY => open,
SBITERR => open,
DBITERR => open,
-- AXI Global Signal
M_ACLK => '0', -- : IN std_logic := '0';
S_ACLK => '0', -- : IN std_logic := '0';
S_ARESETN => '0', -- : IN std_logic := '0';
M_ACLK_EN => '0', -- : IN std_logic := '0';
S_ACLK_EN => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR => (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN => (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE => (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLOCK => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWCACHE => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWPROT => (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWQOS => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWREGION => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID => '0', -- : IN std_logic := '0';
S_AXI_AWREADY => open, -- : OUT std_logic;
S_AXI_WID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WDATA => (others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB => (others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST => '0', -- : IN std_logic := '0';
S_AXI_WUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WVALID => '0', -- : IN std_logic := '0';
S_AXI_WREADY => open, -- : OUT std_logic;
S_AXI_BID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER => open, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
S_AXI_BVALID => open, -- : OUT std_logic;
S_AXI_BREADY => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_AWADDR => open, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
M_AXI_AWLEN => open, -- : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE => open, -- : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT => open, -- : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER => open, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
M_AXI_AWVALID => open, -- : OUT std_logic;
M_AXI_AWREADY => '0', -- : IN std_logic := '0';
M_AXI_WID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_WDATA => open, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
M_AXI_WSTRB => open, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
M_AXI_WLAST => open, -- : OUT std_logic;
M_AXI_WUSER => open, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
M_AXI_WVALID => open, -- : OUT std_logic;
M_AXI_WREADY => '0', -- : IN std_logic := '0';
M_AXI_BID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BRESP => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BVALID => '0', -- : IN std_logic := '0';
M_AXI_BREADY => open, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR => (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN => (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE => (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLOCK => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARCACHE => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARPROT => (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARQOS => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARREGION => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID => '0', -- : IN std_logic := '0';
S_AXI_ARREADY => open, -- : OUT std_logic;
S_AXI_RID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
S_AXI_RDATA => open, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
S_AXI_RRESP => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST => open, -- : OUT std_logic;
S_AXI_RUSER => open, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
S_AXI_RVALID => open, -- : OUT std_logic;
S_AXI_RREADY => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_ARADDR => open, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
M_AXI_ARLEN => open, -- : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE => open, -- : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT => open, -- : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER => open, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
M_AXI_ARVALID => open, -- : OUT std_logic;
M_AXI_ARREADY => '0', -- : IN std_logic := '0';
M_AXI_RID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RDATA => (others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RRESP => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RLAST => '0', -- : IN std_logic := '0';
M_AXI_RUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RVALID => '0', -- : IN std_logic := '0';
M_AXI_RREADY => open, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID => '0', -- : IN std_logic := '0';
S_AXIS_TREADY => open, -- : OUT std_logic;
S_AXIS_TDATA => (others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TSTRB => (others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TKEEP => (others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TLAST => '0', -- : IN std_logic := '0';
S_AXIS_TID => (others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TDEST => (others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TUSER => (others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID => open, -- : OUT std_logic;
M_AXIS_TREADY => '0', -- : IN std_logic := '0';
M_AXIS_TDATA => open, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
M_AXIS_TSTRB => open, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
M_AXIS_TKEEP => open, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
M_AXIS_TLAST => open, -- : OUT std_logic;
M_AXIS_TID => open, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
M_AXIS_TDEST => open, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
M_AXIS_TUSER => open, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_AW_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_AW_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_SBITERR => open, -- : OUT std_logic;
AXI_AW_DBITERR => open, -- : OUT std_logic;
AXI_AW_OVERFLOW => open, -- : OUT std_logic;
AXI_AW_UNDERFLOW => open, -- : OUT std_logic;
AXI_AW_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_AW_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_W_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_W_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_SBITERR => open, -- : OUT std_logic;
AXI_W_DBITERR => open, -- : OUT std_logic;
AXI_W_OVERFLOW => open, -- : OUT std_logic;
AXI_W_UNDERFLOW => open, -- : OUT std_logic;
AXI_W_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_W_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_B_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_B_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_SBITERR => open, -- : OUT std_logic;
AXI_B_DBITERR => open, -- : OUT std_logic;
AXI_B_OVERFLOW => open, -- : OUT std_logic;
AXI_B_UNDERFLOW => open, -- : OUT std_logic;
AXI_B_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_B_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_AR_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_AR_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_SBITERR => open, -- : OUT std_logic;
AXI_AR_DBITERR => open, -- : OUT std_logic;
AXI_AR_OVERFLOW => open, -- : OUT std_logic;
AXI_AR_UNDERFLOW => open, -- : OUT std_logic;
AXI_AR_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_AR_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_R_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_R_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_SBITERR => open, -- : OUT std_logic;
AXI_R_DBITERR => open, -- : OUT std_logic;
AXI_R_OVERFLOW => open, -- : OUT std_logic;
AXI_R_UNDERFLOW => open, -- : OUT std_logic;
AXI_R_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_R_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXIS_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXIS_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_SBITERR => open, -- : OUT std_logic;
AXIS_DBITERR => open, -- : OUT std_logic;
AXIS_OVERFLOW => open, -- : OUT std_logic;
AXIS_UNDERFLOW => open, -- : OUT std_logic
AXIS_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXIS_PROG_EMPTY => open -- : OUT STD_LOGIC := '1';
);
end implementation;
| bsd-2-clause | ee621a10e45986971efc2c9a87260767 | 0.396631 | 3.77237 | false | false | false | false |
okaxaki/vm2413 | RegisterMemory.vhd | 2 | 1,131 | --
-- RegisterMemory.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity RegisterMemory is port (
clk : in std_logic;
reset : in std_logic;
addr : in CH_TYPE;
wr : in std_logic;
idata : in REGS_TYPE;
odata : out REGS_TYPE
);
end RegisterMemory;
architecture RTL of RegisterMemory is
-- **SKBLK<FNUMBER><AT><VO>
--"000000000000000000000000"
type REGS_ARRAY_TYPE is array (CH_TYPE'range) of REGS_VECTOR_TYPE;
signal rarray : REGS_ARRAY_TYPE;
begin
process (clk, reset)
variable init_ch : integer range 0 to CH_TYPE'high + 1;
begin
if reset = '1' then
init_ch := 0;
elsif clk'event and clk ='1' then
if init_ch /= CH_TYPE'high + 1 then
rarray(init_ch) <= (others =>'0');
init_ch := init_ch + 1;
elsif wr = '1' then
rarray(addr) <= CONV_REGS_VECTOR(idata);
end if;
odata <= CONV_REGS(rarray(addr));
end if;
end process;
end RTL; | mit | 3711b2e2ac1251c7c460c31c849af3e8 | 0.548187 | 3.416918 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/sng_port_arb.vhd | 1 | 17,789 | -------------------------------------------------------------------------------
-- sng_port_arb.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: sng_port_arb.vhd
--
-- Description: This file is the top level arbiter for full AXI4 mode
-- when configured in a single port mode to BRAM.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 4/11/2011 v1.03a
-- ~~~~~~
-- Add input signal, AW2Arb_BVALID_Cnt, from wr_chnl. For configurations
-- when WREADY is to be a registered output. With a seperate FIFO for BID,
-- ensure arbitration does not get more than 8 ahead of BID responses. A
-- value of 8 is the max of the BVALID counter.
-- ^^^^^^
--
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
------------------------------------------------------------------------------
entity sng_port_arb is
generic (
C_S_AXI_ADDR_WIDTH : integer := 32
-- Width of AXI address bus (in bits)
);
port (
-- *** AXI Clock and Reset ***
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
-- *** AXI Write Address Channel Signals (AW) ***
AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
AXI_AWVALID : in std_logic;
AXI_AWREADY : out std_logic := '0';
-- *** AXI Read Address Channel Signals (AR) ***
AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
AXI_ARVALID : in std_logic;
AXI_ARREADY : out std_logic := '0';
-- *** Write Channel Interface Signals ***
Arb2AW_Active : out std_logic := '0';
AW2Arb_Busy : in std_logic;
AW2Arb_Active_Clr : in std_logic;
AW2Arb_BVALID_Cnt : in std_logic_vector (2 downto 0);
-- *** Read Channel Interface Signals ***
Arb2AR_Active : out std_logic := '0';
AR2Arb_Active_Clr : in std_logic
);
end entity sng_port_arb;
-------------------------------------------------------------------------------
architecture implementation of sng_port_arb is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant C_RESET_ACTIVE : std_logic := '0';
constant ARB_WR : std_logic := '0';
constant ARB_RD : std_logic := '1';
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AXI Write & Read Address Channel Signals
-------------------------------------------------------------------------------
-- State machine type declarations
type ARB_SM_TYPE is ( IDLE,
RD_DATA,
WR_DATA
);
signal arb_sm_cs, arb_sm_ns : ARB_SM_TYPE;
signal axi_awready_cmb : std_logic := '0';
signal axi_awready_int : std_logic := '0';
signal axi_arready_cmb : std_logic := '0';
signal axi_arready_int : std_logic := '0';
signal last_arb_won_cmb : std_logic := '0';
signal last_arb_won : std_logic := '0';
signal aw_active_cmb : std_logic := '0';
signal aw_active : std_logic := '0';
signal ar_active_cmb : std_logic := '0';
signal ar_active : std_logic := '0';
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- *** AXI Output Signals ***
---------------------------------------------------------------------------
-- AXI Write Address Channel Output Signals
AXI_AWREADY <= axi_awready_int;
-- AXI Read Address Channel Output Signals
AXI_ARREADY <= axi_arready_int;
---------------------------------------------------------------------------
-- *** AXI Write Address Channel Interface ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** AXI Read Address Channel Interface ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** Internal Arbitration Interface ***
---------------------------------------------------------------------------
Arb2AW_Active <= aw_active;
Arb2AR_Active <= ar_active;
---------------------------------------------------------------------------
-- Main Arb State Machine
--
-- Description: Main arbitration logic when AXI BRAM controller
-- configured in a single port BRAM mode.
-- Module is instantiated when C_SINGLE_PORT_BRAM = 1.
--
-- Outputs: last_arb_won Registered
-- aw_active Registered
-- ar_active Registered
-- axi_awready_int Registered
-- axi_arready_int Registered
--
--
-- ARB_SM_CMB_PROCESS: Combinational process to determine next state.
-- ARB_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
ARB_SM_CMB_PROCESS: process ( AXI_AWVALID,
AXI_ARVALID,
AW2Arb_BVALID_Cnt,
AW2Arb_Busy,
AW2Arb_Active_Clr,
AR2Arb_Active_Clr,
last_arb_won,
aw_active,
ar_active,
arb_sm_cs )
begin
-- assign default values for state machine outputs
arb_sm_ns <= arb_sm_cs;
axi_awready_cmb <= '0';
axi_arready_cmb <= '0';
last_arb_won_cmb <= last_arb_won;
aw_active_cmb <= aw_active;
ar_active_cmb <= ar_active;
case arb_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- Check for valid read operation
-- Reads take priority over AW traffic (if both asserted)
-- 4/11
-- if ((AXI_ARVALID = '1') and (AXI_AWVALID = '1') and (last_arb_won = ARB_WR)) or
-- ((AXI_ARVALID = '1') and (AXI_AWVALID = '0')) then
-- 4/11
-- Add BVALID counter to AW arbitration.
-- Since this is arbitration to read, no need for BVALID counter.
if ((AXI_ARVALID = '1') and (AXI_AWVALID = '1') and (last_arb_won = ARB_WR)) or -- and
--(AW2Arb_BVALID_Cnt /= "111")) or
((AXI_ARVALID = '1') and (AXI_AWVALID = '0')) then
-- Read wins arbitration
arb_sm_ns <= RD_DATA;
axi_arready_cmb <= '1';
last_arb_won_cmb <= ARB_RD;
ar_active_cmb <= '1';
-- Write operations are lower priority than reads
-- when an AXI master asserted both operations simultaneously.
-- 4/11 elsif (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') then
elsif (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') and
(AW2Arb_BVALID_Cnt /= "111") then
-- Write wins arbitration
arb_sm_ns <= WR_DATA;
axi_awready_cmb <= '1';
last_arb_won_cmb <= ARB_WR;
aw_active_cmb <= '1';
end if;
------------------------- WR_DATA State -------------------------
when WR_DATA =>
-- Wait for write operation to complete
if (AW2Arb_Active_Clr = '1') then
aw_active_cmb <= '0';
-- Check early for pending read (to save clock cycle
-- in transitioning back to IDLE)
if (AXI_ARVALID = '1') then
-- Read wins arbitration
arb_sm_ns <= RD_DATA;
axi_arready_cmb <= '1';
last_arb_won_cmb <= ARB_RD;
ar_active_cmb <= '1';
-- Note: if timing paths occur b/w wr_chnl data SM
-- and here, remove this clause to check for early
-- arbitration on a read operation.
else
arb_sm_ns <= IDLE;
end if;
end if;
---------------------------- RD_DATA State ---------------------------
when RD_DATA =>
-- Wait for read operation to complete
if (AR2Arb_Active_Clr = '1') then
ar_active_cmb <= '0';
-- Check early for pending write operation (to save clock cycle
-- in transitioning back to IDLE)
-- 4/11 if (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') then
if (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') and
(AW2Arb_BVALID_Cnt /= "111") then
-- Write wins arbitration
arb_sm_ns <= WR_DATA;
axi_awready_cmb <= '1';
last_arb_won_cmb <= ARB_WR;
aw_active_cmb <= '1';
-- Note: if timing paths occur b/w rd_chnl data SM
-- and here, remove this clause to check for early
-- arbitration on a write operation.
-- Check early for a pending back-to-back read operation
elsif (AXI_AWVALID = '0') and (AXI_ARVALID = '1') then
-- Read wins arbitration
arb_sm_ns <= RD_DATA;
axi_arready_cmb <= '1';
last_arb_won_cmb <= ARB_RD;
ar_active_cmb <= '1';
else
arb_sm_ns <= IDLE;
end if;
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
arb_sm_ns <= IDLE;
--coverage on
end case;
end process ARB_SM_CMB_PROCESS;
---------------------------------------------------------------------------
ARB_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
arb_sm_cs <= IDLE;
last_arb_won <= ARB_WR;
aw_active <= '0';
ar_active <= '0';
axi_awready_int <='0';
axi_arready_int <='0';
else
arb_sm_cs <= arb_sm_ns;
last_arb_won <= last_arb_won_cmb;
aw_active <= aw_active_cmb;
ar_active <= ar_active_cmb;
axi_awready_int <= axi_awready_cmb;
axi_arready_int <= axi_arready_cmb;
end if;
end if;
end process ARB_SM_REG_PROCESS;
---------------------------------------------------------------------------
end architecture implementation;
| bsd-2-clause | fce358af3cc89efbf6d76023e278d89f | 0.394795 | 5.150261 | false | false | false | false |
NicoLedwith/Dr.AluOpysel | RAT_MCU/MCU.vhd | 1 | 12,806 | ----------------------------------------------------------------------------------
-- Company: Ratner Engineering
-- Engineer: James Ratner
--
-- Create Date: 20:59:29 02/04/2013
-- Design Name:
-- Module Name: RAT_MCU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Starter MCU file for RAT MCU.
--
-- Dependencies:
--
-- Revision: 3.00
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RAT_MCU is
Port ( IN_PORT : in STD_LOGIC_VECTOR (7 downto 0);
RESET : in STD_LOGIC;
CLK : in STD_LOGIC;
INT : in STD_LOGIC;
OUT_PORT : out STD_LOGIC_VECTOR (7 downto 0);
PORT_ID : out STD_LOGIC_VECTOR (7 downto 0);
IO_STRB : out STD_LOGIC);
end RAT_MCU;
architecture Behavioral of RAT_MCU is
component prog_rom
port ( ADDRESS : in std_logic_vector(9 downto 0);
INSTRUCTION : out std_logic_vector(17 downto 0);
CLK : in std_logic);
end component;
component ALU
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
Cin : in STD_LOGIC;
SEL : in STD_LOGIC_VECTOR(3 downto 0);
C : out STD_LOGIC;
Z : out STD_LOGIC;
RESULT : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component MUX
Port ( TO_ALU : out std_logic_vector(7 downto 0);
FROM_Y : in std_logic_vector(7 downto 0);
FROM_IR : in std_logic_vector(7 downto 0);
SEL : in std_logic );
end component;
component MUX_4in
Port ( TO_REG : out std_logic_vector(7 downto 0);
FROM_IN : in std_logic_vector(7 downto 0);
FROM_BUS : in std_logic_vector(7 downto 0);
FROM_ALU : in std_logic_vector(7 downto 0);
SEL : in std_logic_vector(1 downto 0));
end component;
component FLAGS
Port ( FLG_C_SET : in STD_LOGIC;
FLG_C_CLR : in STD_LOGIC;
FLG_C_LD : in STD_LOGIC;
FLG_Z_LD : in STD_LOGIC;
FLG_LD_SEL : in STD_LOGIC;
FLG_SHAD_LD : in STD_LOGIC;
C : in STD_LOGIC;
Z : in STD_LOGIC;
CLK : in STD_LOGIC;
C_FLAG : out STD_LOGIC;
Z_FLAG : out STD_LOGIC);
end component;
component CONTROL_UNIT
Port ( CLK : in STD_LOGIC;
C : in STD_LOGIC;
Z : in STD_LOGIC;
INT : in STD_LOGIC;
RESET : in STD_LOGIC;
OPCODE_HI_5 : in STD_LOGIC_VECTOR (4 downto 0);
OPCODE_LO_2 : in STD_LOGIC_VECTOR (1 downto 0);
PC_LD : out STD_LOGIC;
PC_INC : out STD_LOGIC;
PC_MUX_SEL : out STD_LOGIC_VECTOR (1 downto 0);
PC_OE : out STD_LOGIC;
SP_LD : out STD_LOGIC;
SP_INCR : out STD_LOGIC;
SP_DECR : out STD_LOGIC;
RF_WR : out STD_LOGIC;
RF_WR_SEL : out STD_LOGIC_VECTOR (1 downto 0);
RF_OE : out STD_LOGIC;
ALU_OPY_SEL : out STD_LOGIC;
ALU_SEL : out STD_LOGIC_VECTOR (3 downto 0);
SCR_WR : out STD_LOGIC;
SCR_ADDR_SEL : out STD_LOGIC_VECTOR (1 downto 0);
SCR_OE : out STD_LOGIC;
FLG_C_LD : out STD_LOGIC;
FLG_C_SET : out STD_LOGIC;
FLG_C_CLR : out STD_LOGIC;
FLG_SHAD_LD : out STD_LOGIC;
FLG_LD_SEL : out STD_LOGIC;
FLG_Z_LD : out STD_LOGIC;
I_FLAG_SET : out STD_LOGIC;
I_FLAG_CLR : out STD_LOGIC;
RST : out STD_LOGIC;
IO_STRB : out STD_LOGIC);
end component;
component RegisterFile
Port ( DIN : in STD_LOGIC_VECTOR (7 downto 0);
DX_OUT : out STD_LOGIC_VECTOR (7 downto 0);
DY_OUT : out STD_LOGIC_VECTOR (7 downto 0);
ADRX : in STD_LOGIC_VECTOR (4 downto 0);
ADRY : in STD_LOGIC_VECTOR (4 downto 0);
RF_OE : in STD_LOGIC;
RF_WR : in STD_LOGIC;
CLK : in STD_LOGIC);
end component;
component PC
port ( RST,CLK,PC_LD,PC_OE,PC_INC : in std_logic;
FROM_IMMED : in std_logic_vector (9 downto 0);
FROM_STACK : in std_logic_vector (9 downto 0);
FROM_INTRR : in std_logic_vector (9 downto 0);
PC_MUX_SEL : in std_logic_vector (1 downto 0);
PC_COUNT : out std_logic_vector (9 downto 0);
PC_TRI : out std_logic_vector(9 downto 0));
end component;
component SCR
Port ( DATA : inout STD_LOGIC_VECTOR (9 downto 0);
ADDR : in STD_LOGIC_VECTOR (7 downto 0);
OE : in STD_LOGIC;
WE : in STD_LOGIC;
CLK : in STD_LOGIC);
end component;
component SP
port ( RST,CLK,LD,INCR,DECR: in std_logic;
DATA_IN : in std_logic_vector (7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0));
end component;
component FourRealMux
port ( TO_SCR : out std_logic_vector(7 downto 0);
FROM_Reg : in std_logic_vector(7 downto 0);
FROM_Insta : in std_logic_vector(7 downto 0);
FROM_SP : in std_logic_vector(7 downto 0);
FROM_Subraptor : in std_logic_vector(7 downto 0);
SEL : in std_logic_vector(1 downto 0));
end component;
component Subraptor
port ( Food : in std_logic_vector(7 downto 0);
Feces : out std_logic_vector(7 downto 0));
end component;
component AND_GATE
Port ( INT : in STD_LOGIC;
MASK : in STD_LOGIC;
CU_INT : out STD_LOGIC);
end component;
component IMask
Port ( i_SET : in STD_LOGIC;
I_CLR : in STD_LOGIC;
clk : in STD_LOGIC;
oot : out STD_LOGIC);
end component;
component ret_db_1shot
Port ( CLK: in std_logic;
SIG: in std_logic;
pulse: out std_logic;
level: out std_logic);
end component;
-- intermediate signals ----------------------------------
signal s_pc_ld : std_logic := '0';
signal s_pc_inc : std_logic := '0';
signal s_pc_oe : std_logic := '0';
signal s_rst : std_logic := '0';
--flag sigs
signal s_cu_flags_cset,s_cu_flags_cclr,s_cu_flags_cld,s_cu_flags_zld,s_cu_flags_ldsel : std_logic := '0';
signal s_cu_flags_shadld, s_flags_alu : std_logic := '0';
signal s_flags_cu_z, s_alu_flags_c, s_alu_flags_z : std_logic := '0';
--cu sigs
signal s_cu_reg_wr, s_cu_reg_oe, s_cu_alu_mux_sel, s_scr_we, s_scr_oe : std_logic := '0';
signal s_pc_mux_sel, s_cu_reg_mux, s_scr_addr_sel: std_logic_vector(1 downto 0) := "00";
signal s_pc_count : std_logic_vector(9 downto 0) := (others => '0');
signal s_inst_reg : std_logic_vector(17 downto 0) := (others => '0');
signal s_reg_alu_mux, s_alu_mux_alu, s_alu_reg_mux, s_reg_mux_reg : std_logic_vector(7 downto 0) := (others => '0');
signal s_cu_alu_sel : std_logic_vector(3 downto 0) := (others => '0');
signal s_scr_mux_scr : std_logic_vector(7 downto 0) := "00000000";
-- sp signals
signal s_sp_ld, s_sp_incr, s_sp_decr: std_logic := '0';
signal s_SP_SCR_MUX, S_sp_SCR_MUX_MINUS : std_logic_vector(7 downto 0) := "00000000";
signal s_multi_bus : std_logic_vector(9 downto 0) := (others => '0');
-- INT_MASKING
signal s_MASK_AND, s_AND_CU_INT, s_i_set, s_i_clr: std_logic;
-- debounce
signal s_debounce_and : std_logic;
-- helpful aliases ------------------------------------------------------------------
alias s_ir_immed_bits : std_logic_vector(9 downto 0) is s_inst_reg(12 downto 3);
begin
OUT_PORT <= s_multi_bus (7 downto 0);
PORT_ID <= s_inst_reg (7 downto 0);
my_prog_rom: prog_rom
port map( ADDRESS => s_pc_count,
INSTRUCTION => s_inst_reg,
CLK => CLK);
my_alu: ALU
port map ( A => s_multi_bus(7 downto 0),
B => s_alu_mux_alu,
Cin => s_flags_alu,
SEL => s_cu_alu_sel,
C => s_alu_flags_c,
Z => s_alu_flags_z,
RESULT => s_alu_reg_mux);
alu_mux: MUX
port map ( TO_ALU => s_alu_mux_alu,
FROM_Y => s_reg_alu_mux,
FROM_IR => s_inst_reg(7 downto 0),
SEL => s_cu_alu_mux_sel
);
reg_mux: MUX_4in
port map (TO_REG => s_reg_mux_reg,
FROM_BUS => s_multi_bus(7 downto 0),
FROM_IN => IN_PORT,
FROM_ALU => s_alu_reg_mux,
SEL => s_cu_reg_mux);
my_flags: FLAGS
port map ( FLG_C_SET => s_cu_flags_cset,
FLG_C_CLR => s_cu_flags_cclr,
FLG_C_LD => s_cu_flags_cld,
FLG_Z_LD => s_cu_flags_zld,
FLG_LD_SEL => s_cu_flags_ldsel,
FLG_SHAD_LD => s_cu_flags_shadld,
C_FLAG => s_flags_alu,
Z_FLAG => s_flags_cu_z,
C => s_alu_flags_c,
Z => s_alu_flags_z,
CLK => CLK);
my_cu: CONTROL_UNIT
port map ( CLK => CLK,
C => s_flags_alu,
Z => s_flags_cu_z,
INT => s_and_cu_int,
RESET => RESET,
OPCODE_HI_5 => s_inst_reg(17 downto 13),
OPCODE_LO_2 => s_inst_reg(1 downto 0),
PC_LD => s_pc_ld,
PC_INC => s_pc_inc,
PC_OE => s_pc_oe,
PC_MUX_SEL => s_pc_mux_sel,
SP_LD => s_sp_ld,
SP_INCR => s_sp_incr,
SP_DECR => s_sp_decr,
RF_WR => s_cu_reg_wr,
RF_WR_SEL => s_cu_reg_mux,
RF_OE => s_cu_reg_oe,
ALU_OPY_SEL => s_cu_alu_mux_sel,
ALU_SEL => s_cu_alu_sel,
SCR_WR => s_scr_wE,
SCR_OE => s_scr_oe,
SCR_ADDR_SEL => s_scr_addr_sel ,
FLG_C_LD => s_cu_flags_cld,
FLG_C_SET => s_cu_flags_cset,
FLG_C_CLR => s_cu_flags_cclr,
FLG_SHAD_LD => s_cu_flags_shadld,
FLG_LD_SEL => s_cu_flags_ldsel,
FLG_Z_LD => s_cu_flags_zld,
I_FLAG_SET => s_i_set,
I_FLAG_CLR => s_i_clr,
RST => s_rst,
IO_STRB => IO_STRB);
my_regfile: RegisterFile
port map ( DIN => s_reg_mux_reg,
DX_OUT => s_multi_bus(7 downto 0),
DY_OUT => s_reg_alu_mux,
ADRX => s_inst_reg(12 downto 8),
ADRY => s_inst_reg(7 downto 3),
RF_OE => s_cu_reg_oe,
RF_WR => s_cu_reg_wr,
CLK => CLK);
my_PC: PC
port map ( RST => s_rst,
CLK => CLK,
PC_LD => s_pc_ld,
PC_OE => s_pc_oe,
PC_INC => s_pc_inc,
FROM_IMMED => s_inst_reg(12 downto 3),
FROM_STACK => s_multi_bus,
FROM_INTRR => "1111111111",
PC_MUX_SEL => s_pc_mux_sel,
PC_COUNT => s_pc_count,
PC_TRI => s_multi_bus);
my_SP: SP
port map ( RST => s_RST,
LD => s_sp_ld,
INCR => s_sp_incr,
DECR => s_sp_decr,
DATA_IN => s_multi_bus(7 downto 0),
CLK => CLK,
DATA_OUT => s_sp_SCR_mux);
SCR_MUX: FourRealMux
port map ( FROM_REG => S_REG_ALU_MUX,
From_Insta => S_INST_REG(7 downto 0),
From_SP => s_sp_scr_mux,
From_SUBRAPTOR => s_sp_scr_mux_minus,
SEL => s_scr_addr_sel,
TO_SCR => s_scr_mux_scr);
my_SCR: SCR
port map ( DATA => s_multi_bus,
ADDR => s_scr_mux_scr,
OE => s_scr_oe,
WE => s_scr_we,
CLK => CLK);
my_raptor: Subraptor
port map ( Food => s_sp_SCR_mux,
Feces => s_sp_scr_mux_minus);
JimCarry: IMASK
port map ( i_SET => s_i_set,
I_CLR => s_i_clr,
clk => clk,
oot => s_Mask_and);
AND_Gator: AND_GATE
port map ( int => INT,
mask => s_mask_and,
cu_int => s_and_cu_int);
-- Debounce: ret_db_1shot
-- port map ( clk => clk,
-- sig => INT,
-- pulse => s_debounce_and,
-- level => open);
end Behavioral;
| mit | af95320ca226f92eb9cb9158809ceb7f | 0.473762 | 3.130286 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/vhdlFile/concurrent_conditional_signal_assignment/classification_test_input.vhd | 1 | 1,004 |
architecture RTL of FIFO is
begin
-- Simple form
a <= b when 'a' else
c when 'b' else
d;
-- with guarded
a <= guarded b when 'a' else
c when 'b' else
d;
-- with transport delay mechanism
a <= transport b when 'a' else
c when 'b' else
d;
-- with inertial delay machanism
a <= inertial b when 'a' else
c when 'b' else
d;
-- with reject delay mechanism
a <= reject 10 ns inertial b when 'a' else
c when 'b' else
d;
-- with guarded and transport delay mechanism
a <= guarded transport b when 'a' else
c when 'b' else
d;
-- with guarded and inertial delay machanism
a <= guarded inertial b when 'a' else
c when 'b' else
d;
-- with guarded and reject delay mechanism
a <= guarded reject 10 ns inertial b when 'a' else
c when 'b' else
d;
-- Variations on else's
a <= b when 'a' else c;
a <= b when 'a' else c when 'b' else d;
end architecture RTL;
| gpl-3.0 | 4408dcede3ba546536344678930f5423 | 0.573705 | 3.677656 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/generic/rule_008_test_input.fixed.vhd | 1 | 827 |
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
-- Violation below
entity FIFO is
generic(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32
);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
entity FIFO is
generic(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32
);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
entity FIFO is
generic(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1');
end entity FIFO;
| gpl-3.0 | d4ae896966fa016e7c514ca53f58c5e4 | 0.558646 | 2.996377 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/blk_mem_gen_v8_0/blk_mem_gen_mux.vhd | 2 | 91,985 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
dkahayCYqd+IN1ynrpiAawhApGkbRzkAoSRCTbdudNr613vDedV/sXDi4HfrK2UNGQUEwTAUekds
x3EDMqmkrQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
WJ2GpXVWOumM7PSkskdGIaHGp+trqchuHYOmxLQtMzjzbjBh5Dtfmw3eX9nZMwQDqvlUdkI4ymLg
in2ZHA8VIwRRm/VCG1YyamxLxvEFgPwCOi4o8HZIo/biO9JgXdYQoxMhPDmYJvl1njAtIVgQtfnv
wYv4vPMmlP3IWsic6Jc=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bDgtqkvJT2kgMrIvHxJydVEsv6eAfSIRygTmZ5ZSiZ83xBoCwSR77PlIot51gU4UiOVAKKrNH4bD
z+pqKlVF4dWPPRp7nIj8Vi6GTb3SK57Dos4KDWgzfI3UyGQQljrvUD3lO3bvIDSJ1UC+irU/rgIq
ejxA8in8aYzX+rkFeirBBCHnoSV9IPMfws4g3AS1n7na7YHXxinoaHLxJLWSo2Gkh99JLJXNWFLe
PaZxuQaxCx+Q/uqBdi7/R6IjFP2JLcQKuGs8EE6Hh1uH2i7UNzd4Kv+pH+d9SQGW2+8rzhbflRlk
fC62SMgfydBz4uL5zhKNslko3Wa8av/8/VLAfA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
0E4Vgc8exwEdGz1IVS4sBw2GCZBJMj1LUDKd9/kQc53O/1jd2Nx9eCho99HcWnEL2hLJaM/fzZH0
gAEUWAdIAVxeBBdDaA/HJX954xPtPK/OIUA9hZo3t2/DXh+NyWyUWeP6grGmsx84XSdh6jevopgQ
T2XWcpWcGOaMjtQLen0=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ioWzirej46wj/Ulk1KwDz1Ni0CnjYCU2T8EDx4vz99q3k1XRJLviGTSKfaFJZ13K40eY+4vYI8DQ
MzmwjrcW+5zup/72KgrkQ0bd72JGGaqwdwdw/C2Uq7eJeF7elWqJh0NE69DrhqzzbxU6ssIJ1dB/
4dVb6GcewsZnHNvOYyoQ+v1nnugVqBYFeYnyNgI3xvtlsClGSdBynn6sw9mMJ5oRW5jhKEQ4m4/k
33ONzcx0exM8hBY4B2gL6DiXByk6DS9HA8cVqDMvkshlxO3Ie82glSV8OSzr3UKqaq1jQ71c1iV/
kfrGxN0avm5huwXB9RBOIqWD/t78xzRvyUHmLQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 66352)
`protect data_block
jnhx6SBMs6lPLHukA0kQLb8HoaSvs3P3JD9kIf0rrC3OqGdUoWm8HvXmEhgVzbDjSlnRakI2YITH
8eQ7lYOMHIgnC0AbGwCZtIAhiQaozcCKws/nJ+j+bi9ZgwvdxXQV+/HX5OHldvq8OW6mC+suxj+0
ZkLvQacUFaINhXBXjjtDgyBjZg8i9NcdXPtyPEhnOXkULWH1r2ZSXsfVF4IlqHogP6VvOTY+ZoRw
jHuzNriIBJ2i4io+hvRkfDuY2rJ7FPkK3MRM6utblESkVuoL/CwBuJz2yW1aw72g98lJctj98J6P
y5coBsUt+or7635Wi0+HOKRooPAVA6RjH8jIt/J91bscGW9U5K0haw5p8Ysr2umcDsUat9wZ7weJ
7Ol1p9Tiuuk4PWxpiKmcaj5c2XcP7W59D2rIJFNrKUsJoJ4mBVokEfmfgvMaKnNueeYUJQfsYPbI
ygfUMjPMB2W3YbMIBbHUz1Cqr8cA4QA+y780jjJ+rvCx8cKrDVcx+79JH8kjTfc6h2c57Gh+DYA8
M2XjFj20ZtDfn4MxnwJ6DlVHFJXIPaOAa7PHQfD1EarsD7GGwdFSXgf/4S/fL1/Q0KirTjBEOFT0
t0HoGoxnZdaOKSNcw6gBQxRbNDNJqzxJLxCdzZRDcm85XX4INqeoXcKdCackDpdxtKs0zKDoM/bi
QGVg34cTzJSBB4PZEdgHKe0HuEQcWfLXq5W23ata7v/iC5ZZfSYs8+r4uiJ5MKkBrIPqdfPq4Fc8
Z2sSqTqb5+ZQfjgqTetp9j1Y1ANA0qzMzk+I41nODaE5njBKlegSJ3PlsF/q1NHDsGR0jtJI0mco
NO687/0Kk6p9bjqOA2x9oSym/xpEoaVLZew8SVcQpROzwO7ogCwmhgo0DeEjvtSt+CgeMXWnYr0H
HhfrFYPCP/CxEB420a2mmQwe7YBqt92HJhDBC4XmgKC1qf4YZqCicrbQA4PNFp9w21/P9M5D3pjF
b6Dxewp19IsbNXF0KwLPgqTdSGs+bPOjzNz9lo9g4+fVNqyOcwpcfFR6idwUOIRW73doBrJi61Hu
1KCZboZ9xspA3W4ahptjuPEQ10FFKbxLSHVLmg1xh6/26xUjR8R9KXwjPtY4RPcj/eQphPJSxL4o
mCG3QEfl2f6oAQtCvc8OU3NUrysRBt7Xd/jZS0Rfext2wtQOCCskB3uQt0OXPw9Z+u21PSRKw5O1
raaPzeRIM8vIl5S9v0cRj3J4uVi8t3ans+qiSj/RFjp/TWmwP7ynjE7P3RtYXnPzHKISPg+ER+NG
PwypghohscRc8n9bgdtCNZPIZdTHSygqq5MSDInIqXINLhlbPkMzkv31EZvaaBidq8fdJs90Ilau
PNQP1JEPLx/9lEe/rtD1k5kM3Bsj4wVoyrDZv/eZBwYvFdQGVRkm3YOlLYd6W7JthJ2NuSyK2xob
j+jLpNoA2aO3KNVCa9OEyszxIJG9PVHqnFrTa18W+J82ocpJ9FkVZtZ7CgspXGlV95NcKscceI8L
OOHk9O3ygCxrpVT8did/sxUhdJ/4vs3nHAVgqoFclCN65661PhiuLN4yf2pTvI7gEX10+Lrzo0cc
A4Jtypcy01v7Ut4d1Mr+iNWyLTESld6JExBQEU4gpSUrkShiR5BUkszCkVMJ9uUeOeAIYNPH4GTG
pdnYcVb6K3UutvohfdKdHEH+kF4tHOV+EcHrorvnb40VvD/JEHfSzjk9J8UUGEwF9pYtd9plodjT
2DtRn5Ohp9UU1bpyXINjr9glBRUvslikCKuiEFLMcW4VmuzEdIBSmPNSvsjcWk7PE2Na2+x2hxB2
4Bnk6U4LNqMOgXkxBrrhnSXCwmx3Oztu+Yv8CP9pRmOyYCBmgeIGfGdr0rKTomm/XsKEhUJ8KNuR
UtNMGIk33DR7BADcOcjdox+4MN+V2cWInFiVkHG1NaZmWo9PnnWnvyjNMbKb8keKgeVrWXf6ok+i
5xKvlxU4ooPeBv8qAtBMlVO48/qqaf3CqDZAA//KhEgyxVqQDfUWQ2310hPAy8VUtEPf7DMhMdc0
pcENeQGrGKNF3jF5hPAfY6Eh9rn0kPsCAESf1jqeNCI52h+BjaNfoQEv4/sik27/CKp9ZstwdAkZ
FF9dtzARp4F/ZZ6T8jqXnY75Ol095njPkNIRK4TF2h2/ULadHIRMFv+9u2p7uU/5PCBqgjabEvZ/
VeFvhaVlbDWOIQFqbjNnZxlqtCm/nKzZVpAWk/9on+x4hffjSC7YNiqyp9yozUZsxjIb/wxnNqNt
v9K1kKy+pCy2LHRaQgBlwl5ncMnwgt8mgE6YVishL9YgQhjSAaBP2NlJwooz1XcfVulJVGyr9Fl6
+04RzNWBwIsGVYPquCA5P7+soejMHyL9wvcx8kCXqw8XYwAJ8qxrFBjnkRPPKZZfleUQKN2m6UHk
+EkCBoOOlNSje553VDSkNW9y5SHKbGCjy0NsjhDsDmEIWvmKlnjA59q8gEfJuJOH3ZE8EXgnHajx
dX/dB95zwecCUKturUD/uZDlUsyUofqKFr09GlKqnR4tT+M0BoaNpIQwJzTBellPwXy13lOI9L/f
/31m2FzYj3lBKsZq53IfvKl9hTPoOeFc1hgabFbgqXDoWvnGkB7pMoT34HfuTJ0smfOPPq88Y9p6
riA6Ed3J9Waa8Y8Atjvy+OdF9LA1SC4LFxTceBdcNY1FGP+/jtDcT1gRgMZeKUfx2l3E6q1E+6WH
N0wDFtokjhushyZtCHbEs1/HnVqIkszSqMwyFfbVsgMTt8rmsxBg0pHHo2oeR3tTuo6LH38ahNky
X1BMausLcDkvAiAe7re4E6Y2xyqtMGU3vRgB0NpkB5xEMmKXwnVlKvPXHFoxoJEKqgYtU+T7NfdL
z3pfts6VaunTDzdQPRw2ERZnnf9sc6pfot92/EGd4zzx5pCfManXPQoK1EotOuLNJzrdTP8qJefS
aH2AfVVx+h/Jl7ydRK8Rq2DHB9ttz4he4mArTGjXx9ZP1ULE/aehaaKZxlyiJxXzr2JgTM0v3gdu
D0Hzovy/G9nt5JpSAiFsBavPSUAL7+dGXPDHo4cbcSn//8XR9PO43frZUjan1UWWLdqa12qcW5Be
YckBIULO1w51ZqcX74vIOpR4W+l4B3h0/Ms0zI+/C2zvR8Qcf0Mgu7qnUyAD5dE6M7DgmPlFS9Y4
qaHtdNPzN5iNISTMa74kxWXe+yp4FnWVRJYI3d+UaIMEMx2NVs5Ej2XtGDyQbzzVu7jylpNG12c/
NmfGdaku+NNkpPy5VRIvP+g6tZjyW5yOsiUyLbr4JCFk3crGbZiGM6tsHSSdUEQG/3itLL619QdX
qNBtsAhRuDI5jzjuy5QUA3AiqKK4RkC+MvE6F7DNq3tOritsHhzA0jOHh4zq7MOfOYkmIYaF2Vqj
rHewRF1R9Shul8WD/v7vUqAWupDmKVxSoAgxFn4mxhLCBA/I9wn3jBTXCGURGZmZ4D2iTXsTh/NN
iimgu/aMf7+nBRU1SYjSPlZuIiO60xL9AN+J8Ghoa6Q1Cd5yV08YaKgytMUiYzAWxSaxnK5xa94D
LpJZJgozH7Z0wc1YuY4B9LtfQvvrsJmrIqdRvsChhvo5mPXELUG3QM7KIYeLX1qavqXQxYPeWfOH
IuBmONwklpD7RjAKZXwa5xQ09nxHuM79BBjiuZBaCWYLuzALMR5qNh530j20MVtZFpDPnvqfxtNp
q5Ts5w3qu38IjNBiVyiTt+vhY5gLi1QGRFRxIcMlbCOgQY6uHARYCJ58yUgwDZkV2942KFT7V1St
kNPfpTsYyZxfvP13THstd+yQxYtW2c9PRXaYMpKrEa+BR4CvYG9pV90WkAAZJDiK6qUs7EG7tUr+
oQtDxsHz0dQmtUyMPIEydM+E1DdmQPV4w6fjDOyZd0syD1/YoSKH88xIJ7gTDuggcbmoRcHPzM0d
e+wLtD/WLCt33ZW5sG/+mLnZhWtFY7MqEkN3/Tvd+PIlqBb2xH4YVdWv8P1SSXiZmacxdBkqVwof
fkxXqDIpMKhr8fo30akqFEmNnjdNxQO1cjcbaX4G9XEAyrVHZ78o5T0dZ9Wb4C4Tf/CaBfPuyxd0
5gOsQ2xwFu8r2h753YUuwIUTnrFZMtUddET2TkCLOLoYnlImZGZG/FeJWYrhtB6kgdQjFVAUaXlm
6bzsqQcdh1UhjQDq2eFq3K/CsXfKVcm0m+U4Pxzs/bsjKTaDB+WkASB3JdhCg5OtNWXhgPYIui30
/vEg2sscoaBGxBBJvCzv/lk+MNt8bbon6dbU/NYnClksYP369GN2sMxpbxCxrIemY8M1jNyYo4BI
Tkg2pX16Zx+mUB+Ez1gvXQsR1GgCWaxSRIqPmruLBltZ/k3e/g+Rc367Cam1P+uoUd8yQWY9ML/9
6MK6OU08eCY1mh9XGpZ7k5iVxvBpW3VNusKavUcqNstPsKUeAqQrLlw9+kJNKHSw5I3G8Fqd2SyH
2I+rt1sWwJloDajUShb2bBcVXbI9MT2iCt8FRdAfGZ5Wex9J4sag16a8uWBEZ7ENVKqco7dDZppF
TzpPUPtnf5HD9hMfjOS/aS37rdN8MKcbhU7UYEg9FxBQojkEZZscx5f4ZpLV8GCaCErRM9QlzoY1
PkWfFO4XJCL6PST9wqzGBzKw9372uHqBhd/49YceNESKgarf3+9qEEzfOElN4sm6OB/VNKDAkQ6p
NoJSvcf4yBrboipgde68UPvgXAdzb+j/w9UD8RcO9Muo4NjruPR1H4Lt4YKgVshx/Aqh2+f4FRtB
ETAL6EvTn8qQvuUouvPUjbWBOX8K8Whi1E8rHAtqo+kS7dp4/XMeisgi+gTvaq25ZuqGLkgrNnAy
Qx2kI8i5crnRMckupmVecNfyume/jTKcHwoQ+v7GITpMXTKlKG4jqiq1IJ7oS7/2DxYHnJzJAMq5
HPDlEP+CLeZFh6OQQhnitujXLH6mt/v8+YEKYLhh2PkaltIv+4joqDGckkradI6MH6I2WLbywycZ
PZDxS7KNAWgjmCEoWf/rzM3/yngHzt+ywtVJScrV9rflezyZmmjzVfOFeQDNza1j+lHwnvxsdgps
eT3wNjnMsFZENuUPyyqhnuJmn4aYfekTHoVON824Agv8hRZpefWj3PhW7xdV2d/Yj7/A+QeVrUcu
4mKG02Zgns8oiCL2mzP86WLbfoOwnUUbRHqHXN+cBU9TrFZ2qCBdnvR69mRuvnbedWl38bBCEw1X
iRdQLgDURUW1VgyfVckjM1XOTINXA7jcypp86hRsUmYFSfwkwavvTvTro5nH5/fc5CPNc308PJjj
3oZL3j+LlhfH6ofzoi8QqRjSFC16mxNSjTMQ1IBN5VjN/GeL0XEXaK5UIwaip27ywVmSJb+/Gqy7
R2taK1/DWJVlYB2V8+lHWuKg0aGavofRmd5Vb3VS2eEXnno0o/C1M6851FMBDkiPf8yz6+Tub3Py
mblDm2ERLzuToqQYnG9CgNrJ/m1UWmybWxdj4ZHV8BGfB8eseuh/Vq13b415PkG6UXuisEMPOaM3
W+clsW9LeE4UA90PyxcHfJqJfKsFUVyYu60vCoK7Bs+XJ552wd0vRfzCVq2llRvaVBhG8y/ZUIvd
3f+RblNKHPUfkxSCiqyQO1w+GgkH621Xt3n4XmlbQIXDpY1Q8eI3C27sPAqxxa0GX0PuasjXs8yV
RmPyRVbaGpUBsDrpibHFgqAPRyZS27uxuq40ar2NOxqDTiWyPBP7er6cS8Dz1kv+aenLST1hh8Mh
OO5LUpe8D5jkhyq7GWTJOTEb3d03xOh9SnhLw2wLfE9aVButGEwO2go2Nv9Qy1Y1P8NcxbL21S9u
QQ120QJCP0/2Xao0yUWWtSqi3hYT5j4DSdOxEuX2xnw7oRisW/clImlddVaaF32JpcFYEqhojKMs
J5Pf6ZzUYf4eyMqw8a2t9zuqG+PmbmC3kX8jrbIgJupNWIMhI12R5NVWD0c89a5GCwQ04XVH/AMO
DoxhWRA/hNJlSnlpNRew/e5hH6rZq0vwQNnKw75BFYHVn+zetsi3acdWMO+hOeRMCok/JXhyUCwX
8hZZEgNorwt22OVzmq33hul6rXsLNdYSZOmu9wurI4rKozLM2fJwKGfBwILdrBM6rbyBe8du8qNJ
bwqfhYqEDuIIJudNRP9VyDcuvW2CFuOieGXMr3trjjHRHIv87j7rvxx4JAsgjoZ7kOowYijRKUPK
uO1DU3oGNP5EydMPdGx9ILaEs4GjOvSnlGmMUsvl+F6nVaH6wE7DvQH/bOO7+q0dqMAr/21TZGA/
nlNLVvV5MODn88+3g2v8vYAAx5Q+LxWWqpj1I8TdkLdfyjghdYTI0FgZoAjyGYhK5AZShKmdX+DY
gI9ki/VUmrSQZOItrdN2TIaJs4VrwFPA1Kk74zyCOrdFyRZAtzPcqF5n16otFkN+vF0oelesKipb
KYeKuN2zOI+Z7Fpynv5H3Lie9UCKbIg2aiADqQCnHYcmfjwwp6sONgUU27G+efbor8djjUoxG4FP
DVk+b1W4zLZXeVZ/sd8bfOdoDH2dLICpTyxcQczWZ6aluydEBigdV6Xug98goe5zMSogaZR5lqWn
seT/Sda6a3wsXpOme6r8NxN3vMIKEWntno1uQNGm2brfDFWx1DOe5BLQ9zr/Vads/1TvLM03STwI
OiFpg3mmEH9UMpzaGjyUI4X2jfSN1VTvtiKgW+PdYmTwW91NlJiFk5TGPfrOu2T+LnsLdpJy02YU
lADOkW8GgJwDN2otj5McqrQm9TFjVKzE/0gmKvkboDJL91HCdXWGcDsCom9A8kSa2/VF7N6rG2SJ
wuX4z/u1aAKRhEK0gcTXg177ru0tYpYtzTgHw4PDk/Bem2BPxtnJIITQefE7ZIwCyS7tO4hIXY+j
B8I+wLRQUEDfd1oEs7PsRdBFjQFUp1I6fwAS9mDxVgVUn2YK9FsvFQMSXoOzWGYot8GSm0bvQfk9
Uw5WhXLMBWLmspIQeb2F6jOh+xZYtc3AC60XMPK4sjAgouZK7xBTVk+kk4DddS+nxZ5RJW0EYmmU
KRGZUqwpwgjWpVUsd1ChPiVor+yWn57XnvrEV/62RCtFO+2SpUR6EbmdmDoX1JcHKMb9BbNIILET
OnASl1DnnCO9j3Zg6QQ8eL7gdZJvbYB3zBxFuGBzzPe6fThN+p+gVhN23Nf2r/mi0186Ucp/9+0j
ZArD3jJO1syKKKZATwVc+1Ic6ryPcJGAVXIVjVOfTuH5thiQ0bRq37/cdvCOVa6D5C1COy6KaVB7
TaWx8tuiFcS8abxjtam9WRXgtByHTzAP2kQNUC88znHP3L2FOpJFoD2VTi1oAJqoT5775Ewwpr5e
2K5koP3aGwLgOU6dSA03ViYDL6p78myh/WvJLw6z/WZbF5tuytKUjhUGP7UX/IA6omV6tL2+GwSL
Lkxo7+PEAYLF3CPvmKzftQtzK6mlvN7LelOKDqwCSkbJZpJL8JmXAdssURL+ozYQcRY7saJy4wNf
9HyN6SdZXXmxcGQl7ovZJG+Ck4bfFYaVD0ii00mmE6JH1SMtErthjzaBIvPQnzMCVFXE4wilo92P
atafIIZsScs0Xb9GXgtUKqhN9yvy98uNN+1NXcUIrKrzd6gUhNwyB+TC0fsw9vcyKbmIgTWXLImq
/xc+b4IKLSqmVRUI0qwTiYHik+txw1UH4dVxQVeMCoGAbcrlNE5zSiuuxPrqWrvOfsf2yTc0U9TJ
pkZT3PMbGB1woefhj3/NcqAaVodtjVpormb61sQne1JE5xEK0TLVY2q3US+ArMds3VN9oWHZH1Tv
tcbYLhb8IFnR4nAU5gDqPZb3dnGUBUtDUzkZrwyxXON90mGV4nUNSTQohnqVXwZ5G4Bp6FWiiVm1
lZkJQbf2hmbOZlwPT79zO0l9vILDMEqeLVg/QmCyfsjiDvGu4phTCC14Zqd1R1QQl0iqACsl2N20
paGvmKAtPIaepAMSIpDHzo05N4Jbsd/xC0UGoUQUwhhSstmRgOu/HeFkbu3Epi/aRQcgtjOsFib0
4S699pTKdY/6CmwZ68UX8D/2KHEujHVGnNFThNH7GpfAtO0MO6f/ApcsWM7LdaBqv5A/yDCCR1kv
XWmQv+ieCi/2iclCcl/VUEervHA60ZuOYDfYY/+kQJhvI1eEYVMDr23Z9PsH+HEmBTv7N1mMF+Zu
tRJ+VjWl/96SrB6jp+R1QwcnkD9mxjfE0pYkNSRcWriFs7LIWmFsDlGT1WgoOwPnOlxi1iP2AQ/j
F/QSnA3k/ZnV7cMs8A8EUyL0wObmwY15rFj8Tl/+ELdTZteYMk6qHW2neHWDAwxmBsJ08IAzYxx0
UH7WpvBAxRgwmdzzvlf1u6hz1E1zPj2kDEw1PWWkW/n/Y0U51UqTSenc8nAR5h7bsmEgCtWAGwN9
ek4tPCBtQqeLWD+0MM4miVRiS31VhHTRRbwVjWMsDGz/LrMDO/l15LU1zmdsMbxF3odtJaK7kmIQ
CuFjzGrgDCI1Zm4Iz5VFHaJ5aBG7XmXcz9jU1JG88+FLJ6XGvjIM2MLJwYbAJZN+Y09oXK3tjA0v
TElAcoKyY083r7fHaifQEM657VsorLm4NrHj50Cz1EzOLMj1+ZZe3qQzCgBCFW0cx9HDKRVp+Epu
jFRjHs62+RLg7g0uTl4LM9yZg3lWJgi3EZ0mFJ6d76YULNrJt0dgU0Aq5UWyqPSKXJLV/c7SBtIH
f5ZC2pfYV4KaDVmQXHLhGGHlHTzAIABEAV+2TgWPQpn1hwM7YaySPZPGP1/6q+zpbU+mrxjxLCh0
kS05uuLqeveOIx++SDqz67ACpNTMEHZqXv/kPfE2FqoTFG93Lc25TndUoq8X6Cq4iYrEmmfMhDEm
tHlGYgDEDZsBLJmbz6yR8VYq4qMEYjvpd8k+FTXVNJaoHsEBbP8z5eXa7KGJ82JK0MPHEIOFkl7m
Gju1h04iX7y2dd+J7QrIRPFOAtfP/jnln7omSvBaWScvSsfTbYxAR80wjn3+8iWtIG42yS8XOphp
Ot+T9lOXwoIE3fi7kLFqk+CyQkd05a2q/a65ro35nCjngFz6JAA5ik7dwbnskxrPmj4h+4nDzhSJ
xO3iG3CHS/tj+wAGCgM1Tfb8LfmE/Vec7nWs5JgRQ5ZDAzHsLtRWlLrsXC6uDz5yhGWklLEr5XBE
mZFzQ327U0TTyqmjzKP53nzQ93c+B/AImFYDt2LLSzSvQoOn0m7SA6PKFb/YYwzGMZEujJ6DVR51
QYLbu0A2sdZlb41v/Ue6qFXc/cIrysGSXWMrhTpQAr1Vu+JIJzoeIWkZuFzCsznp4pVN0W9dlHi4
8waWJS1312tXk0wpwvMP9iEPNPBSKM1m/pk5Cd0kkWbOXPiQR7FJG4AFCR7b5UdjnXTo2kE3HV0k
HhIulO4HzujBB/xTda4oTNjK+k5+WerXTiUpAHJu8j6uBOpgkn8fLYUrVj86GwBGAojyL3OQw5Z6
bqGC9ldV+DezT0Y/OkY/m0njm/42V92f7ysjmwTxMLltjdEtLXBw90K944ddhsGCLkvLqrLlVyW8
tkjRmf5lJf4S1HvF0nh+rmFEFRrHCRtV6HFhFYngjJQJCdL0QpJpZglM2jmftazcusrcVcSoDD7P
k1d7ok5tQM7VtKeMXTv0IvVLzfHoEj5MdoR94FK4JaPzoDcSf2SLIWaAfhlfjKmZWw+6N8gJjD6v
rgh785Abh15qfrAk5FOUjYS28mwkzZaNCc7U2ZBIrKdHW/HhoF77jPoPF2IbzYbmrdlUwyryb0VW
7vSGSDCRTsQieUXbdnGl/lD35nXfIqAJGAPqmcqQ9AcDBnPVtY13SX8GOrAeyMpvNZBNzJwJiHYj
1RfdHzIrs9qAPebocvW6KfWJfHOMhu6wjBrIkHighW72OaeZhKtW5eW41Kpcek/tZG2ITXuTxG4k
fv0ub2zpEozDIq4wKogkBpmbZfdh1U6E+GnZKB2InSt7/TZRxCMJ5iUDu0YjPl9YUFMam48zPR+6
hmNJobTPBHYLuhpky8NGcCV5GZw/ov0kyR5dDz2supbADbZSEVhB1w4nv4j3zdWKU1T/XS15JFFx
E9sX2aTZx+3JzsipT2UiY/ViL+xLwvgTc3dElPPc53ajP5OSfLKJhzfM3t7Sd5AMmIfPc3a/2tjc
AfE3uPgNTL+8cNSuIMxtEx+U96Wb3/06UZxn1q2RL+GEatt8X3EPfWcroyn7O17LK1nQdbbHKgNp
T9qSNEcuPfyncnPIgOGOyfnfv98nGPxoQcV9/A27/IDBRIyCMqGutwca58qo1h0S2gPgwQ2vsOdm
yVYmoQkGYfFIzwiocsNZ9MghRke0xHm2PEnnh6DfiETcEDLecNRExFGv4Qm0DRnWwR/eCWdTtU+R
r1pnr/Oi25rsv7ADj00+gJerJ5nYygjcvcb2eIrGRM+QQkTp4GJwEYkuiVDRvUFPIB9qB9YTc0s1
qPgYu8sifMnOK2VTTP07VRTmFi8TJdrZuBk6UHGko0yznx+YrlvUEkwea9qxIuzYV1Kd74tm0VRb
kCY5dMdu2lxFCjpVe5//PDuGxdxVbHleWJfmaYXN4CGQyqSztdCJYoxethDeIa9/SoUddA4FAHWd
IOV0TmLHz2SKCuDWXil5r3Ecsx9N2ptXA8pNt6azR5yA8rFnA0hw/rqkYSYjQ1VdOwcsyoRkl/lx
jyEOe+6kyCGRrGhGBxbHu/1T10v0Fkzs86bicrAa3zh4+NVcc4DlV/yvW+OtPaOKza3PCoVnmqav
NCvPOYWioUfc9VFhq2Vjdy+JvuRw/qGJqest8NWIKcU0PgZDaEfuAP6ny+ipLeZ+1tB7fUa3Nrcq
1RCdz6l/X10cM4iiVcUPY1qhpaD45nUcEYFkHaedfq8cJwO552UgBYUbfIy0gXFgPhdgIP9vu4hY
jmKFrt5JM7BYym+ZE3/M6doaZVhRoOBWBNM582zHcLfYKCNg4R1aIOWFy4Pri0PF0pFAra5If2dv
3zmnGbQL2CYGi0sDraDRhvqwPFO1FPiMkAr66Sgb1rfyma6NNREX9JbF9RNgLagDGGSUj9ijCxst
tvbLj+EVh8W7b8pHvR1Zx5U5HbLeisO21ulaSIF0tbDTCoM/YV3//J5p5/r5XYA+eYzCKDlYaOxW
UdZ/B9NyIwg31URY7gllDd/upVkepIewDgL37Ptu6aJtU9B8HW1eaosOSa8N7r4TyizcRARrJxrV
79sLewmPmEJqUzGZsUhi2xjoT6SbymtFm04/cLrehmervRFQhSYOGV6Suv5jh0Xyk/ZGsfnl5ZfA
YP7IdNwZozzN1BYFxDT1jhHXQjhZyBOUjlCVotl60uzzxEzwEHi8fRFE5hroUrGoeH2I9RnqIcVY
oQm218AuAgYl3MPHn4bRhnAFSiMZOP2LWa+f/U1If7K17aLT+FbWdJPqBaKjMC/gkoAuWtPZxZdD
vl8msEedEivBCdJUHZ/kTmVZ8PDVlciFR5EfHoV71ds22Pifg2Gol2YC1SqZLA7P8FtLsOYHGnMm
XagDyN/s72UiVr62Ws425mlsOIbG0beAKfK8jhWDmiuOHd5Uuygun7sRjEVSTMa/w8nm5xQcwYXL
EpIOZfzCMEo++10WDVdYKdS9IBevvzqiHaug+AhcNQ7zZ6THvcx4uO3uy0TP/VI3LkvQFqkURcXe
8dMc+l/Wu7mUBA9P8JXImxQwLFq2aGuIK7gr1AiODcqvLI1Q/RJJGycidENuC+q0E/XVbs7XTWmO
Rmsxir2wloSJoCzIN99DNOkoO4ofouufFGBynHyN4HeIw2CNHVFMv2dupFCiYRDE9cGLAmBsfMbh
krw47VhL6nBJUbity/tajSq/kwWNp5C5sH48Gu8ltaH1ladjNiqx2zsfcwGurGH4q9WwBI6a+5km
667chlN59gSbk8fzlhPU1F5rSYFfdIDuF/BBpqdUNwxNX0EgnjI3xM48+ICkwwXFUgPud/1WHCFH
VbOJORL8cgckF7J3IUxbtZWcrNzn+5LYeg9tMEZxfvbhUJ59uQnwJzYx5sWU4/R4ZWBrjM/7dwBf
shp7FgIFkTmT0vfYlAGSf+Vnjf2IC+JNvC64WqCxF6mo+gRpFodnIpFEZAH0Xve1XMzadOBFqd9u
DvfmRlRI+ErGbQ4uaolb/hy23cf7bO9N84o95iwVXvSFuTpjutqnKFnfTaA3aPgEuT2AhUH8TiRn
6Wfnq2sTR5f69zphbJWQ5t8rtnhyWdmYjI2xxzXvuSAVDbVN76CxBkwl0/ImPWJtJ9rDkGib4Q68
KpRE79d8051LONkVNaeQbnM7d+19DLVdcIg/sbZ88Qpm6/SdYzlpNnR5r0p9/55gd+VH7jTi2QD0
YhXHwZfgKtBDcN2HP1lHuNFLEKHEN3cpWxRgDJwRCEBCq9Tw6845vfgvtREQvLE8ElorGyqgL/s8
0hnLvAB9Ad0x0rGNLYuZblqL3/K91/Ia0OpOfYfccB35n9fWoPaSBpVvXdmpm55DHVHftYZguqnt
Xms3soG4ZaUwdnJAFsmiixhX9JHfFQ2MOk50rMJ0MZmzLzqQq5Me7uY+DK8Bk+NJg+UwIbLBFdDN
OkDbiZZIH3TbPgu4hpPo2yL6/fIQc/s37bcba0v9cccxs09Z+peFtUgrxwXDlFGgdlmOZWvv+Uz8
jF9+iHcg6xP9DkRotDaa9nRSBE1kK18CcS8oV3jkYqGztggkFsXrTWhN4Wllht7j1Nepmy3B4MvU
vHUiwwZ8SR5OpKa+qFZM7K9kID8ObZfqvN/yjrw0zNGrnBKChmRQZGPFwNkjuhavL4kZ/R7b3UXa
teCYbhSD44/MvU5TlTmzFaB+exnirHvJS0m2by/9ccDid+6Rq7jCGmZVOgzl2VDMcOnbLE281abD
B6bQPUSzqASHp1U9o1jXUgi94Drfo1HddX2fdv+rTS3o07rGFBf/1pr+a3OgwbI6AoqYU6/pmwq1
EQXPVJZ6a5O+ZqEu0CB4R4y0RBsex6lJamQ/hFgRvD6yh8lv+Pv7S95FtdLLcOpQMIbezLp6I7tt
G2INy/iVFBP0JbLNdZfbEo7LlDxZPzxRLVpxnbSSPltZ9WH1fAA6rGK1Se1gbAuccYHw55aU7iC7
rsaJ7At5ICBrxrkAi9ouf1oFfSiBLx0eAm14NShs6LPP6qCCu8Y0MzzCMAiBX3rf75iS6cBWR2+2
/Gr8KFHCy1Yjm/GpXRtWv5H0oakDJH640E6HDEDi9KRqExNP9+nwQwl3jiw1aTRo+a9zZCxzqzC1
h2iEJ77qzY0AXkkV4HuN+ieBO5eyCbbbbs/V8vFfIw2/uCFPXGob3LHdKxF1jWeD9v/s+Z0jZSti
tSTCREQnVVchZB55m5L6yZ68k9xZ0n+/FXZVCkJpP6A0PrmQ/rks33xqjLXmngcsXMNYm/DfGlKC
c+IsvmQI5diOq3kSfzYo0M59kQ9hkMyLZwokbaHvJDNuCH0eMD/cnRrOY810+3Atl1QTnvIAHXXC
IpdSZLqQ+0Bad1203ljB2SeIbR0jRrxqUZzOfCovkVqagPSRPq3OdDNCNk965OeslTSbo6nGHer7
OSfXltJW0t7znA7CFWGRWXVFAVzVNALXQ8aj4Sd0IcmY8/kge73yGMD8PO6YeuQmbXmVvV+no2TO
dgWxQMBYfq5mjFzlIEosLypntaDqXHbFcgmGpJHfKKL/1nmoLdfDnvAN/lgE/FyDXCUheew7c72c
tKLspYwLLKkqSb6CsWWIRJy5IBUx8+48hv0fgAWXCEoqyY40lUdO98zQcjvOQa+/p2WwhpGz/AfW
o9lonTXfIwvjQhQkaKwfEk864zJPWS3kIC8MSlmB0v7nqwJ1FBKLGghodskTfGRq3N74aCbXEpNM
4T+9/iPSGZ2D66tUCjmew34udOCYGFSO7OM37FHd6uSJG24U8a+eOY5HxnCJLXRyNDkqH6lONp+d
YhhX4E9oDmx7Nv8tXgVhilIDzFBXJES0AVTg/yDAkHn+aXMPc9vBiuRzlL9OJcym0JF2DbxFaQMy
kZhaESQhHzAA6iqIb1rRpCZeHWl9/M1O6xXlf5vnjh+h1etBqLVNXNaQ9a4WZ963TVfGJdfaUj8i
h1UCxKbRbXCuKtXudzzMFGjPFKmr17A3WZ124QQzRc6DKM8bqv8pUKzPKAvgdcPXjqqAhrGBxtmJ
zsfts13mTks5RLC4f/6GsMppPGLINrhaDoRjtizyV3Gz+UVWfRqeCbLZnYfNtRrLwEJVKGBve/ny
Q0ry+4bRAnvKFmltFJRjgybao4En9AR9p0e2U420RHxdVh1qzZ4lZ21wF8LeLan3tg7ggd1ijPyx
IJCIIi8gr8ZxF7ZaUi7nnRUZoBt9pRHRDVlHwGWPt+vop3y1mNBFbpaNX2eOtyf29obu4M+xjUgX
J68eaVn5Pj0w1M8LB4B/xaDMu1Mh+fex26mwZnVGqPZSoQEQ2EpgvUjICuVAS+80q8NLPVAHFlMZ
+s51BXWl/JRlBh1Wcuzz8stYKPsnmpeFqiNVH+kQHNtnTkEa549HuLVj+ILJNU6FKGSLzGTfFs2u
XbvjUnrJm3L9mWP2YhnhKIct0YfCgT8NvDmsuwo/IVjbEj5K6MhaliEwH0MfLN1PaNIZtEcSdAq6
4qUhASmEAI+NnSlnHnOzBD+jZR01SoLQJUJBdlAirNhB8XtM5XvF5aP66HuZ+TnmD51pklyLLZo6
L2KKjvMoCflEo/HzuaGb8uTRKggVXe532ifVhYXam9TLb60EVq5UDZRzf1Zqv9LHvF3A93NHLqMh
X1FoaGqldru2dNR69IegjDwFWr0NlA5aBEQa1ty4+7jykkrrlPaIeVWF4r1t6/DGYNKqhVY7bxg5
VyQvOz9avy01BQ2dsKfek9aGVAeIzKu7J8YmPWXNDLy//nATDDlpGIK3zoWOA8rUwcJX73Q++f3q
mpZH4nCJado7RzM9XSRHomy8rOIldgBu1EgD/N6UU7DvCQr6PbkiECiAF2eMk+M0LV18v4bZ442n
/D9TULd/b7nDOGllraN0WPVaYFuCg5gsw9ejjOaQZQyKIifOxjcsXy2g1Amoiis6WjclQaKrDsUD
+UQBS90Xd6NUi0exAAJD3TZdTxd9cYuCTetMym6ZG0R5CpGwuJSVfjUr2f6KjevGv0sJEkE/79gs
NAU13oG4kHZi2JhOxNDK0XrbzT9kZ6kBhVZHhp66J5MT7wGJ/IoxOYl/Fs2Usfc1j8v7F+uehi2B
f7/03W4JxMGFkov/tLGPTmQWacaTFexntUb860ZI04TerIQ5Ey5ICUebgAmhSJe5W3vUwJ/KZeVi
GUOuaxKdwgY8VOptOI6yQQSqoRcwzLrbnC1EUXm0tf5P/pSgol/Tqk8ywIUWAIEZnhKmOIEPR0N5
MRfg2fgVkI6PTYMFz/xIMkL23gcLG+M6v3S6X6RI2jRUDc6UiWXB8T03p1sy56Anq3BzZzF5fz00
/NsJeKWp0LR4MJzwAEbMj6Th4lMWJ819ai6vnjIzl5v/A84Rdn0AfrbMOkJy/nv9Vv64gu/iENUi
GIK9YCq6SoKiYcThbj48YindgNww0SeIYCkClHORAeYcr++no+2BsZL/GjlLDmT/0Jzq/CwHpnFY
kDnT5mbWepn15dTWDHIOt/sHjDbcJPAOThaG6Lstyj3QfVM58nMELcz/MUmsMsuoGIfRRMb86kYD
vfR6OPzCZ+hjBQq5RgcDfyUk3Zt5Yuhp5UpeGy7EF2ktvD2NO2kaJ6NlO9kBhPsA1uBscW/4ScaE
ine3LQ2ez78AWlwDM4755FvsaN3Y3ChjzfTcG0LBflW+2nl+wHDzPh4DodJtiQAyB0bMGtctBXA8
44+zlB9yyyYlnOaWolOp+ar6Oap+I/LK4MlDDjzzffXAq9o+Tct9palLzpU8O3zCo9w0fT/vLW1X
JtEQ7AsUmTS14aVpuik0V23bPxdWrKl1xELnnbfmkM9sAnG573gfPwy8dn2gxzckdwbGFTGa/bdy
rZXK7f2iakZ2vGqMt40Yh2Ga9vyQXd7FiyEiUEVf8wKQZNqxZ0qs/rkhRgK1EHHVEVqasVVb4RoI
WiHRvuZY/SMLEKsUvFoxjNG36303DWzrvf7dPBzb8M5pogTi8C4xV82YmvmYf7sb9Mfkd8PklRsN
WN33jpIw3z8Sz4/hoGlQ+kp1p2KiMRwuB06u/2XxnBKJcQN3owsqc3f7+W1w8YjaqxPN/+Wp2rPe
lrPhzVHnsnxZ9+V0dm3f574DBa+LXwYzUVFap0owuWchDc8xmuJLDp1UO4P+P2IntJ7jXzKCrRgm
I7VrrfS8Jr+HPxvSJXiqaZQ7HBChGal92VKOZJEEEyiLXHsOwGoijREsnj9gGb+zjwe0aeTJew/1
+nuDcJSIauhb9IpjIQ4BC4zH3iKkpy+I+RbfjdUNbNPZpYMnPs07u/yk+gWy7s2yDJe4COKaPVJt
hfnS6HPgBlp/haWcqJhKv03NL+cnINco7/KA+UnEGNdzZCJ3r+1gT5FCOzKhybegq2OUd6llWgUo
5jq167tXluzZdbkp8fJDc+75JUUCzpDjqTk1Nk2A30KqMRyKkg2HEZie9pIjAervwAjwB6diVEMW
3eeNPPw3tJ88HLnItoQqJj60ggVFPWZmJoMBqwD+pcOlhdU4tP4h2C/QP3c0ZXzREMuzTF/7MYAC
LodPuDmnQs3LL9SO5vW0Z4bNVer1uTlCZnFVOMwG7uPan6jG2jT7bFZjT+0tz25inDh3pCBq90mE
VwNqTPpGPRZAJNRX8e+TqNBbl3Duq3j4PNJGIpP5qOFLfQ39KN6k5hDK+OjG581/Zzgq8L1FkzTn
SPz+jRwS2D8dQ6BSM6JeH0U0eMSNUpMn3OFO3N994FkxFS8j6oN0U6JDT9ZXeS4xAU+FeAlDd07d
mOynQy8dg34/LI9RoGebG5VFYmW4bM/EtYPg1NOiYeimJV9FWXvmEHhC23MD++giToqpk4iuBqcm
nW68RJaxx2PrjcuPjo2iUHn0M4NDKn/3Xd2rfjcHaCHefe8WYLsODq6o6zUkRtRQj1EhQFERPRrb
hgCLeSLHre11qAvF4Zidw4C1wQja9UqSFvMndZFsbAGOhsoAOdzLsayOvLr4a1Jtx2+RzBovZU/M
xW154sUDVS8hGwAynpqfRH+yLHhulVtd05XfZg5kQqxgjf42s2nJl6XQUpTmsre7a2wEfEhB3c+8
TOX+UkfOpbPmLs8c7U5WxaOr7WXFycK7nga9V1HO95hcAxn+RNbEH5TjLFk9+WbQaKfy7bXZdVmh
ALV6kMZzac72dTOUnqzHRdeA99Ieo01KkqXYlvTcGD2sOkGGdSWzVLy7tMONiHR3S4GHEIRLmxPN
cOox1avC99tTCF7BLN7YSO6nH0RwdDsXjutEi9YN31kpHDJj3gqFA3iEDbk30q3tGvu8ZtgOYFkn
V/mCaqGDkmreVTS6+Pv5o5k9hj5clqtQQKHWmzmB7MG60wAahRkNLDcZDEnxB47PDzWIzJ29MMuf
TVdoOTuJFDefUBXhyX5UyriklqOZqumgQcTAMolqcBRPBrOpFYPXhW/qDhzDBI0Zz6ATbRaKZA2G
+OnJMd/vHzPN1JzGkdIC20tHik2Ja1lMY1p6TYMPuzlq4AaPjp0XKxkz/l1IiPpTMTs/NGCYPp0x
kcsmM1h0kQi9QOL2FPv8+2LE71yo8VaFhGhnn6/vRGDXxItOL9EOV08YNS7NU2zjMFzG6QXk0gZw
WgTuFEA+1Kpz9NR7eb/dvBT8+Ybz1cnRASVSZx5FuDr0pMLkaeJOF9rGLXUQiozCVb42h6+zmBrt
YYydjUpwb83Je7jfdX6mWy8qdz8l2rLWZJc1c+LUMK0Rw7HUUV4Gb/oR+Gh53SGpAbwLvJ0zt3f7
7AaJKA0MfSTNWcvCMRwiIdRmx0fJdgYKhPWEDrMUleYnXCgHbn+i1DxJBY5sOLJ/iV9Sk9eRk+yi
dKl7i2xEMuEGB2j8YkUKyuH2X9az1eIQQ1HtWTg+5ObfvkcwwK5va3dOKCMyl5cydLm3J0ElVXsd
4kmgAojqZumHVdJPkEvzvENH3fdOEKXSd2LPGNfyDllJW3cyLVLUWYahXKb4vzo4nsfnhQvKRIHc
2RXiseKk4TzaaGEu4uqzHPgGABcG81s8y0MwV65/mz4CiPgTsAG9uDTZnFxDBH96J0lzmDtrl3//
sJhXapx6w05Ajmnfd66Q9YftdNQk4PVnTJsQeMLIg7orjYTR4uKu2aGZPKaKRpVDZLSwYExHS7RQ
Othg4mlEaLUoHnBkVkcj7jLWFRkbfYZMVPD+IvwpaaxeCwWcFgWhIiMqJ87qpTGrZCMi5de1AkfH
ECQVaj8XsNE+WnzUeXt3SIwH+Q12fJ6aMhX6JdW5clZ19AwAalU1dWcfZHfwC/jEdNg+mXZaiVt1
EVNhKyrYzMe9XQFVCRYdTpTmTp5fJJXXJQujw1KRCgoeqy8pByXO/Bkwh9/aG3XWttOwD22qnlMJ
h2h+2vxsiT7jracXVP9FEoccMSg7w8tZmVdvQJIczrxpcBl4Yb9Ah5kIZ7EmV+z8bWAnOFZwiqBz
cvUNsGjN/QfB0qZlzafeOvKwrB6yqdZ7X4Wth3LM2qopZEB/IEQ1LwnBwmIFmUULdo7kz+/gr+jk
bZERFX2KeiaIcm7URuZGULMrml7EipaL9Rk3Zi/4w7739HndRBSIyTIKwAkH08s/zGKKW6YZnxS4
tmOR1bFHdnRje6bJrk40QYTfJvvJWGHvbLXO8XC3F02i86TroEdXk31oAIIOLNSwhZiZ1BSoM0/w
ddebfiTJvp6l6QC+xBMuVpK4+jqSXh5cEGT3LyFdMQIL3eY7mthURcbwwAG9OzmaH2IxWqRtF2EV
xMCPepkqj5w6DcUjJ2o1BDVnP7AImTZdUjotwd0+AVFwgyIyanq1JecQ8M5mT7PQrrq50SUBhDHH
eBwzHFF2Gb2RJhzB46GPNnyQZ+6JeAMmkT4atIrIsZTzBAwR39SZatx2Dw7bKVw4NVxaFqmf3aCM
t8QICEyuK34Ap0sUsKJqUaZlIqUsM5XW+3oKzlWBDXiaD0gbEtFTTDyhIvXBuJSSbfbXUedavWmH
dkAE3JtPlEJzyOItKkB4eMMza6sUWM/1xaQnj30a9sGC5sd9i1gfIPKLA90kW+JsegpG/wH8VPLX
VnvLMS6OhdXyLUxd95DgwIHxoJgITBSXmW0kgslEKLj++CmoaFVBtyGdzGspQ8e4u1WrRgJvu3e9
fqmqysgRls9hEOeWQOcgZhcuA6/ron9hTaorFRPrcSTMdqLQL32OcMb38Ti6kkgVCfwIJr4Eod66
tft2WfMO+9rpFuCnMvFBmCFV4DbfG54qwy9OL/ewyQTF/yNOgStaCl+Zo5TGsT993RmcFhSiyW7r
6/HSQ71l4PMwx4fP8Qk9i4ZxItCft1qP3hmLOOyF+UeOev+WaXIfQ7F0Et3andZJVHUr5DgiNAg6
n9XdkrF96MSKr17KzYkG3Ac4lL8O9gpHekLZiCkdzjgsr8eEWL3xaUAuahpVyQbIZfcnK3bYqq8d
S1f1T6gMKoHwjTXdw7wh0INcSPgT2AhizTKH+x3CZo578uGevLILpus42QfLZ3yRVpicwLX2mqsK
FnlilNWFV8iWZZLzHz/0kqoPf4+XUoVa4WGEo0hkRaYPyzMi8FwPcIExMwV1B/Bg/KtdPrfHE5j7
BFopu5LFTQi3BkAgZfCg8CqFbY8N2Fh9oCavVNGQ+Vg6bZCRV8oXNJrlWTmH0ST61mlOkrfaEkjL
I+lW2z3sd38vPVzCjC6k0OAI6LYBz9U7geX+iYoRqK0jt6nmOMpq51wfd+gkF1GNGfg9PgnyiX0Z
7esE1TO8zGx4WdKtV25bZccy4xTOqz8T5SFNqIQGtGT/5F/ipXyCAyAMU7t+WD+XMlIyS55eRa/A
9EJY9PHFIMEWoUVzJRELgbSrd8/g5dTIhrWPBQqMs7tgYz0S94kZ30oe5Sn22DsJwTYCl9ko8xvp
zHEIRBkyFAxWDv9CDrO7eHadn8UrICmC0Hpq9/u6iQ1I2F/wlV/AqCaA8KP+idiavysTV2Ea6glE
AysXvTP5N5iNV0GuFq+t00dN7000fDPORug/DnplF7b8052XuSsDq/l6ovc/61OszC5LV9ZbU4e7
FMWwchEG9AG/5Uc9roQkGsp/CDzuhMh1qSGjOwmDU/3yu9w7WmXO5xkjs9UujG9IpZVrjKLnMW0K
Bc8LmMe6p3qnUnvx3IlYF8Io3qb1T55RTO+N/A5/OID9myUrATh5uN7xVeNQex3mbZjB4y9f3JK/
pLR2fufSfRtBGFIww+E7sHwpexNpFh63QvH5dNtilPCDhtoe55+GZcBgyzMf+trCaiQimi8AVkgb
TwZtr/DAvEa1dJRgvqyVsKousRQweKtwAdI9GlUa/dUAb5KdRltxBs+WL9AdGy2Pty1SjucS1n2x
Ulhda5q5mJO4qL0SFb9IDUjP1gIbQUSa/LL98hxryHkcX/4myd5IppuUjTbpnKBZcDuHKnaYjdvn
wrXcO4UG3tjYICPleCx5u70P/OYfr+sqtOI2NOcs2YIdREl6uBfEkL+cw8Shf7NcHkvMC+cBrP6W
qFXx7sX75Q3/hlDAU6WNxg5J9jNp03VW1uP/Dk63k3ccVa/WtwpOVxOwqaFMMuTjIK8SdoTBEl3N
vmsmlCgfMwW/Rbw00wU09FfRr299fxqYowOjhcSczaqAK5Q+T1yBUKPrZUcG32Dg1EbewiSqnzn/
lebwQoUlts3e8DX7ThIRkqGyoy3NoZkhiJTLXN5+/WsW9CU5WkMGWwaGkSOZXND8am63dN8L2G7M
579XDUhR2obm9nujxvV4aVFZZaCtF4r6K9aTo6F9yP+bq8oRSWr3gBwPGbl9+jyIrRwV02tJplbU
9E/d47tdCOoK+T/NvA0v37gc/4b3+LduwP5Z9H+4CUDGUkGN9KhfTA/QOgIqN8Ctigj0iy8bOgvm
JYTmbrXtGt25qe6HqSt1kXh7Cbo238mT6BR58ozUrOeZ46a02f6xtD25Pu9ml+0iRivghATOpA5z
rnxQqhvbxslpKGJ9rUHDGxQp2ZLELULiBv6D0wuvsW93JVGsu5hPlZviS67pobR1SvTxJWwBDAbY
//EUdHG7Let/pI0ESEGQqWeb6uc8fRQ2BKmegF3m1z4FVKgInGbKh8RRjeDunq/68Mn+gczZuRX7
3ahe3nMmd6xc4HLp65RfuTCezfyxMeJDJYhi2nUGXG1MKT7VHNL/HJcqCtY+V9MrTL+EcaTITRs4
SjMR+yf9tnACT3BXjRa38tU3mT4vS6cS+slfhXnPQxMZtmbQOz+X/yQH9V8VD+eyv85YgwWJXBVi
Mu1afbKM3EhL8RP81AiEsaYr55pIrq1LnJVT/sXm7uwkKSFCU9rFrh8RWsC+vqjoS1/Ifb868X5K
G8TnsQztJGLvNKwMDTuUKfzqyDOr9eypbVpIwPPhnfNG7euhGWgepy0sewYlk5vrtnzjnxN/3lVf
/HKmLumkbKY+Wpx8zNjopgSWDdjPetXbxYP2/JECmAoqRf2a1vsJp5oW1HP+H8CqTF2JMAbxsSjv
3O70DhsNpxCYOusQuyIhQIr4TbXgW8Edzv46rGyy/TO9PtG42McD9w3oKSVzteL6/VJTpLcWCNG8
bn3q3YoiWS0xoonGA39g8tg+zyLdwQB9pIvxiI00+Xbjx7UEjjeKP55ctvlCQRtxSTOh9beVT2vL
8ch4veBepWf3nsI7hjczb8RFYlM4Vj60ueTnEuLzEu/0zTXFtvU4Fh9azPAQ2rMOLg7NEgB5qUcD
j1dVetnPx4ktf5avPozipbGidPo2Zek2YqAR0boQYvz3F23wOmkoZ7nmJNOWwfFE0fz5cjuDwTKW
URbkCkUksV40MnQwdgMFz4CfY65i2ZEmgjEquaVOrUTK+sepJqbScHreDnqfXGlEuES/3DroqJbA
RTpOqDjg7abzQeMuckX8B/jPvcQMpiVwhiRkD+TwPD333yDrsA/LBGd9J4KLDGwgFMQULkNvs2ek
rIuGE1Zk1JeFy8Nf5c9gqbzkj434rEeSNHpXfJ5m206iOrF69LatUq/9FvWCgSJdIq1sp4SsqIlG
3p0s2NQZUDVnVdatM2ygPI8wOhKJQBeqMpl3pOZ5s+l+G8fRTgRcK7h2xfzvZGETqxUJmznyECB8
Gt2eI465R3btdifaYJAt9nz+kb4EtcDZNZErP/OHjrAHsuvG2TW69u1zfgGV4PleDh1YAjHZ8H+G
1pZ4v96k0vECpRS9BP8tjAD9htPff0J9Qb7Ofs5BdreO9fLGdjOWnbV4PmBtDVLCRSFJYGmHO+Nl
ha/ALYGRPRN4nk6Ae03BNF6xBwKUwsg1Cb+egoRXCbih1rFgceYtHdmb6SfcoQGjXxJxbA6KwfTC
DXhBxb7ZVsA6O7IIY+mt5jmcYERNNEsVta1GO2lupdZuOFjszbO2UZB4BBcM11yjA109UCFQij+w
AJ9ulMLSHFV6GTBm2qCVC5IULIhlx0ztneMGcpv0w2sbNcC+T7PGZhJIw7AixqF6N7YmszGj939U
r0zQONxkXuPGdzRjFkZLH1mb3HCVX/tvHBZSWudG8i8a5CgBjSZxbiddL9/Sxcji61hDzFh9fgAF
jhUxkcOxQljBk5FfVeB7EvRV6UvZr9R26i6fwEqokpWv5YL+X/wCBNd97IqmL+c5cqcC7MYOt0Zy
S+j1uYdyyJcIgmCfOW5kvT5MTtL8TZk0hIqUbM64+1iIHr074PJgK6mBvn6Vwy17yBIEYrglQ3qd
S3maMbvsn/5EZE2J5CROtHepfgDloL9b+1+zzPBd1u6uRLnxlJqtb/fA3d86KV03HQJqjSkwEIkw
vraO0AMi6p5kJbWymUJr5rcgt5/45AQcsqkRQdV1x3gFz9CIXw4Tizl2qOPcfz74d4UPCFWEbi6R
Z6herKDW1LRwjQ2B/SxDdzcnerSII/c6tkEUFwqjoY1PP8dLIiTNak9wytR+AjSDia66vfxj3tD3
UXjWgN2qV6Qav90pyZDQyTd6AslXv/BxPDdCNCDtZj82DsxYWajN7SlmwWJCjBuPdnf2TngyhkXs
64OXKGdYDpSIgbS/YYeHyHBEQs+bKnysEtq6xVxdqF93YeZHZzkW7SOzGeQkp/aB0D4yePMzaeeC
SYtg3bW9JJ4Kg7sbsdFJGtI8iAB2Ab+2BbRn0D3NdWqG3X2Zy80QmJzWmHOiwy4U+Vp1Toxdvgrz
4+Ga1IQWBWS73cFL0OoCE5NGRCR0StD9/e1aOkxL+Emqr2+IleZA4hNRYiCaRiasLg2HM6YkUSFk
Oaflu++oPUDgIHJ7kiCGes25CXPT5KzwR1XHXwxUVjol0XUW46QHwG2I7Yg6rG89xq2JPdTwVawD
FHPtTbBZqMWbRXpDCmWGeFxG3KN2PNbGfNnCykSWu4D4Y/os4onZ5JQKtk1NrVpDuK/ziFG4oVD/
O1vuvZ8vrBUhbmz6v+R1nmvpV4wvbimfaaBHuRU3vgUwbUbrem4lP9zKtcQDwVzZCLg0Qh6Gof6L
XQsxyIitFxRwUBzM6L1TP+bUhfa8J+b8swp9ej1aGMXdhCyCKVFWnNi5FlMjAa7UK+FX7idt+LGH
1Y9PtwvN9so2nAkiACTxEZJsf2llUNWnlls9XJ3kyAkdzfw/u7bjK3zhONpyOdeFrBUk4xJ7Yrmz
iUS4Zfiqc9XyOx0Qlu/2RbOhToX7cBRJzDotcL4f3FGQMZaCRVzeO7xF9VgPzv8XaitpzzxRbhsb
RSYsaCNzt9/d/VknqqOKelZvko7YAaMa6qpbTo3J+VX+7zc11efgq8P1Ssr1z7qKKj+MAlpyDN2k
KdmoAZeom0uMnv7taTAOpbsHZXe+f0VSmZKHZ+UMSk+s25HlnGqKsPgp7yix1yWW8wfh4OMc80oU
/wS3lUXsSXMDBqgcYcamIeltj7aZKV0dkBj7OF/nYar3lrs+CXoXngoRkRwejT77ix1YUDtaVEMZ
FVKjqt4fW/p67TdOllDDP6Jp8RvJxfeoqHKaAQBUScd7tmITq2IwyzisI9R4B7jrizwrcU1p51jT
hPMyckL5sSlTCZb4R4K48r/IXOfFcbeWMa10hhUl0VOfjY44R7hSeyBORrCvR22ldu3CsPYx8u/i
Xsd1I3Z/+7RWy9ntHQO38hQ2nCGvTD9UiDqTqWZAzsh9MsDAG/Kkk9H3p0mfDxiQ5MR3EQsNW8/V
XIofw1i1OmcnAYVipKj08udURXkz8NCfA1KdtYBBC0hehgjyYdk0gj70d65VrX7vs1gNrTGXKtD2
m0ZrISwJUMZVKyGR6CMTZYZLanUwhYk3AxYJF2ltOxTTsT2OpsvJZqHZe3pYCXW+sS4qFfguVnYT
Uw7lU7CBEl9s7DWwDykIboubCwtukNwE0aM/nmvcqwetik/vvtB0oxYHisnnF7G1Yy9G8oRrx2kU
lQmPzFDFFOxX66hvjXfQJbvxWdxcshuqgoMPu+f+WC+Dpb2u4q7NxkspwN3ZGogv3VqIU9WCQsCu
/s6CeEUWMaChB/nRXSmygl38zNEybWRqOHxb0o2fpJSA1Qha0YO4IY/UMUuh6Mozy1c0qLKfuO9/
cAE+jQFGrWtRB4unLm9cla1N908cs9LfjEwrcsphDcNRCqzBhNPvgxjLKwMHORAdMrhx9OkBrmWS
nX8vydrl2An5aiFuQWIOh5pQIiTeAyf2OIfkQW0wMTPiZgpydyyWEZEeCkGzdAoTeThGJh2og0eb
vUNV71DIFsleQSaG1A2Nd0ES0hsxfBuGTy2N0tU35gejIcZ8tYdaORO1p/uRO6uO8Amm8O/UbHsg
We5CPZY9Qd26szaoE0FtPTPtb/lvcCYF2RfVfsBoEoo9AvdnPGzyT4ORfL/qOQMA6LWocM9rjuRJ
5Kg9uctjReC1uZocQ/lD36stwvEEEqt1uUZXnq7HSxmZmVmdoyAPaPPWzmmRNZ0wxtRz2UevU7bM
AMrXO8IMWrnvT4PmrOJ+B3En4g+zw1m9XWkjwvj6lHd8U1rTTucaT1HaauSHP6DyBZLYquVWOrTl
46MsVHndESTPFRyevfzJyE1dKCSiUDHnm+aczeTeoRVGs1BW6G/qFyF/O7bLbbd0g5A1/4MAEwRG
UdFIeLm1UMNr4Q7cbSR1/fpS/6dPX9Ji5yOdL2crLZs9Wu3JRhWTukDqVH4KvcNWgj1LqPQzJa15
d3utXQ3m75O1msx7d7ViinCrlCOLluDfLrcGXASk0Ugktcp3+/BiY7LSACRCrKmvD67QjKnXbl0o
qYEoSP5N777wvEgNHOqmkRwxg9PfwplmJUfqKPl0ARKXnZyyYygXRXSwTJAhFglrrLzAGu4ZmUfn
vrcRrOVP1ovZs89pPRCnm9yYhTOkRgkfGyUHty+NF6msX0jZ427e3FsYjX+IettkCsHeUkaGkFOI
g3A/iPnPlKvtIpi1aUl4jwuLjkXG18fJmka8AHKOek16bKKbDB7AS6ErGDvd3L6vyU4YiXNejJQr
HgLNfpvCoB4VP86BN0cPc5rOzclOyL03cmQF8P2zHVqUiOXIMe5gl4KxNObsMFEBIuVTqqy/dwP6
T67Dc4Ohf6PCMxeA6Gun0VeQ6Or0FNb2oH/9fJ1QkbeIEpljYDr1pSNZceQ5sGP7+3/7d3d9iufg
A/gwB5NM2xn5vmE60yMpuwXWOsvLN34kEZzoa+X5P6f3fZtWgf38j8VDAZZ/wbv5OLJcz9eTsKjl
W5EZTsfCPJtOIzZ2rwACihbnZ7d4n7VbZdC5FF9C/NPS891OalCAMVbrLJMj6QFAmPqCOVZ0zv5Y
r8MBq+OU3hMlYN1U7t7OONbpiqXf8F9JKLh62sI7WXnZnblDI3LaMIZMBaX0sKTMR2XzemafgguE
1KIHHHaNBoGHvsjdIzR+n2tlUS4EmmBR2VPxkgn6R3jsnvplnajN/pZ2Exd6FFwbtS3Y0e0nIeGi
R5LRSMixiVo+Ug17lFaCobIYHxvGII0nWWg/zeknbw3MwXaslGMTMJGTcPzCxAGo85md4ViND/CH
R1BhdL9bg93xASHhuHVpWQeW/Kj6tWQpa0rjTwvAP8gxZI55yji6JgSpq+pnNOmLi6AR1lvUudYX
8K61RULmV6x3IM61iHl4cMajPFsi7tgu6CodeycuJEzJybBfDTbo0mvY+6DAmNl8MrOSD/7iWZme
94B0dhwTpetvY9DP+BxIlBu/Z2Oux4Fm0MWBM3vd1WzK9b5dlbUf8/hsN3IAA9AyO+H4kNBJXPgT
OBywobp2kcyZMGpoEwcpQaNRHxUNcMYZG+G3lmCO2FD6Q7cPHHPb48Ch+6DVvFEVBjZ5Z7d6w6Cj
Gnu/PAIBJvH+ZuLHQQKdATCmL9nnBwUCnmRZWbq/6ysFyvyGiu/QGrlRk421kWn3PuYk6ObM+NCi
rALNYGAlE5li6YtzfNC0fwfja7NZ1kV2XOb5R559DHcgRN1lZ7qMz+/QUV4yK7WsybvTvFiLyeDm
7IY/kaA1ZY5ULuCqHdNXegDDGMxJUUO2HRDJJwMhCUf7oGs3ld31YLiW1caw31It+pZD7iq3MAKU
6ZQl7zc2AZvTlKXbsKzNd4487u7zNPOM/gkCRFiFKN0ghL603gH5NRnB0G84GL4c6jvJGxwOkhL6
hmSWaTcxbFcgXoJipK++J4DTfr3XV7My/dCH34O6vdt4KcpwZnoqS7duAjFGGnrQMbUEeKokSLnA
bg3KSvuRTHEdxt0MTMTl3L+eUFIBvLim978S90jRihJgsCs7dRAr2VIxisl2WRfojWPaGAQ/vT23
ye7gq69HPv7miPmn0BS0aopi0P9uC/8iBKW+Y9vnfL/0wcxHyJuaxZEcL1VCOLeELq8b+IRs1O6s
73B0oA5kJTCj4yQuY5+KIOYLj3MaEci37CGk6m7Ajg0cO2d8yEZ3PTGXWE7YHGtHADbTr4CyGPBO
V6o9Tup4xSvbPeBoiey8nF8yO6x3tPYwSlPr/97BBeq9gWcxLndPnOrAJAfCThVC96nIiV8dLURq
gyw+ie2ziyd9G2RPBw28UtNnzSEHKJrOTyQGfzWUpP/d3liJe+R+1c6i1ikBOb8TZNaoDORrigUm
UsbiXFFDmFehHP0aGnoV/TF2vVxrhtecPPKk9bhTSSaSEtkw0i4QTKDd2A3P3QAwzTuBfgeGLDvs
06qmYMqLX9No1SsmjMt4esPc9wtn7KqBDxvc73KL1tBaqmBDMQUIFp+Z8C6cydQVXYj8gFOWJKl3
kkL69Z/uvw+KER/NP5prJD6CPoIZSCeNsYhuRb6dQlA73MI2hOenP0OgyuzJD5qvAwHegoFzGYWh
DLWLyKp9GuYj32gAKNYiOasnNlZjh590X2f0Ze+a6YcYE9640cJS3apqIbdzFY2HyYjYNluJGoQZ
BumgOUzHy2iNX8jcZPB2cry+GBk2pg6iHAmX2n3NoPvC9NfrktK6OTg4fInZdLuXRrJ59xRJTpHs
UmU8VgsCKmTR1cBtdfomTzIaeZ7d6Mln3kNbz+EHTUG7A7G9CqXPaW6AXvPrv74OO0j38kclQgrE
Ykp8P7uoS/PEpPsLLyLCy2LLsN2/7oVxcMF35nK3kcK3ba+Me9Syv2j5HZk2ALLGGiQcZquqwDBE
uwlcy1ACmrwUnREVSNqudqOq2PgrkrwabEU8mwmqFrRATVm7l1DulOF8YRHpGkoaxXKk8HlkhONe
OrNLkbLn3g0QJO8NkVH7paYxleDkfm0TnsxPUaGqNG1EcZWBSsZj7Sris72fZlmRhoLq2VYfHm3B
bq/UeF2DKFPylw4aLN2QX01Y/XVRfx6tTdZPt3qk2S9RnMvGeRtg+1k9KV4uwCA6DjY5W9pt7kcK
dl7Nlzk/ZavDtxZ8qyGH0KJ9ZFtEv79MjksvGDd8jwK78/mDmtzBZdimQOFgijVe1+KejMTqnfss
5ExuWzUCR9zEX8qglhkNcZuevX2D1YN2Nh0wcguRbwhcGdM1+CcLN+/TqJfIx1eY2+63FFWqsuNF
7q2Uh89sVmodNsI0iJYoGU4JriGtT8w01NFmSbFu7L2I9SQsjhIDJQgSLSGtJHTPDHW3l0dhCsZ7
PFPnzh5TaatBK2d7KXTFlczxYZrCVrDS+wdiQTPPlHwjgkBfnqgSn2NwCDGAxiOFaeRyKmpR8DYi
ekLRhtTCbE5t6WcN1bnZ/VoqnhjcSqL/pnoArNeWuLB8Gwig0Ub7xkFoH9xok5TthhhWLtwYe6Cv
aXaBLDBAnF3R2aw1sHKsRBeHKtzrgSzxnowzeMyY59pDGfaSxg5pDYnRGOgnxWEAPrKt+I7fEkWz
EcY/yoZQ4pAJBmsO2CnoaCnKxz++fY6U2m8o5ki4n7Nuls3xSeqmFfEGgfcLZefqF5Jyrf2tbFnl
3cB2Ds/q9FGy3AacQjQ3s7vPvsK2opRaakYWKxWLZbUSHj7zAvW4rkwXPVCgLzzTnERAASdUZhHX
eHrYFAs9G8BTz7PRqflfaNzeccuAySuD2cNnqx1Pi+U5BvDHydrJOxH31IHtQXmZDfdC6A91ilsq
lVSuZmiw0sQTNUnWeDL1+GSAPpvca1MOKrulKnYecPK0v/MB0lDNHF5tQ0SkE1hLGUk05Nu1X6Tc
+9r4Sd+Yp2kmWL5kcizPvIPoO7b/RacnNnf78XVg8YDU2XvLdJEPnipcBDMcIxkS1q6MROH0YEqn
gth7DWIgVwAm47fSZNUah9iKRUbz/lnjno91Onq1zYDxclSX5jXmiAYq/YO7aq8UKR7FMP2Roz97
N4j1ngZa7z4cSY02p7xCtPKwtpfimY9ZUNznysJwH0E/K/57xMalwPX1Il1+8guHTNTMi5dOgegd
QQRBnLsladKFwRR858KDhiZf4sOl4BXAwSD1p41DZBbPOw9R5BoyWEGh2E6FB6dAEHjgzuN4bYfH
cJgu3Za/FdlO1a6bdg9UuimjeHt7B9OUv1g0A3gvbYUC0925Dqpzexzbh0cfW8lUVHASeeKbkVNE
/ON+s7foIGKM7dAXXLdfGxP14JbRUbmVhF28pDgXagmbM7z7ymvmQKOS/DCu8HCGzG7Il4WO+/2O
BaAXnDMb9nBt8sa6sQiKmr25m5RmJVDeSzLcr29dPDVFsv01n3aaI+RUHJFJRvUTV9WV7PelHTac
iLbaa1Y8uJvLpUDDpicQ5TmnLbmqaFrSUMZ4a5/sGyj9ZQHfu+v9TnEVVO17e9w9UgUfxtcsBax3
01iVQR8Y4hNXzeYZtkmpC3UBCP1YrluH2RayyGQUcR79qFYVTiLURRiY88fDYC2Cq3U8QHqciotP
VPmq17cYjHFt601p1z/Ne1eGqyHAmvByURSuWDrxSa0Dgwz/QAsz1DGdVT29UL7HHGmhj40bZBB4
9/QwZ5fBGGBouxM7vkyNwVButlgcrhh3+yPOmbuZPRsxvKNlbRTOBv5E2Zyedal593BqNhVC0ag0
BvG4BWDlt93YtIZ1SK5w0KOH1xJiazkinZ2XCJqk7tvjxtgxMeNHgdgxdXmmGhpgBHyeYMxzjrUo
ueG1psyhTDvpNZZvRlHgy9cNSxwXZMd2r4sG1P+MvXT7/q0DWTZaLXJ79p48OHb5X9JESZu4ytHQ
8Ukd67fjruRSRx9zp7UR61WnIOHQO+02IduIH7+o1NiNFDyrTAabfxE40YzHzD2yQgS41NqP3W6h
VPPNRNrLXEsDBsxvS+99yeVkbX1V40yT613G7MVmsytHCUKHA5VW373d4pfGNrl3xQtrXT8a5tZN
tpX7uXwn/P8uDyWsWOqVLoW6sA2Hi/JMQCotQB5chcR292nH+T0vQW8BwWr3wcp9epNhPgmkiOwu
feqyXaa3YGW7nEFNpCeIZan0PEGMwP/sP+lWmCgiuiiMLqgUhDV2hanGTIJILaJLrJp6otKaQyyI
V5eSgSqGQgnZhMtiIFwiProWLr1Xy8PJJ5JCJM0m00ox054VgvC+Q96Kca0eq2edqeovRH34VvDj
mx1Jjam3tu630kBBRRhgvzLN9LLkMv00x75xZjbjTijcdluu/QdDc7wM9yb0g92LcEQhMoYeLIyH
r1+jtBYcLed5i6TggHC9UN/tbuLrWGALnc9v5tRsYILhc5xN1jwpl1QIxdjIABnSE7YcilVSQXhv
uonvxDRtmoRSWN0HFnE4NRLDjOyfiAGTZG+0UKik7/m3/xMQrMyly1v36Kf4jajc5spfZdLKBGHL
cof8YSA/eB58sB4PUKs3dh97MqgUQmw11FiRCFb3P2j9LQN+SeFfB5U21Lw4zrqaNnGf0qRSsRo5
U4zs/w4H8kh+nRh0TBWCG9HjIgnS5SCHGki42hKtREUsGNP4hJUg/Uny4Zqum61qr2SCqY2kNCcQ
AhNsQ/tqMzoqFvqXmPC5YxQxzuRCI0xzLTGSyOgB8MxNrGlLgQG4MP2Pom1DAWSDneZLARIDjKG1
XSH22/x135uDikpSOsATfqLMuOLhMaMLiGbDlc6osRWNpoyXzvHjglolLIp6QKYRJ6Qf5f8raj/A
3w95gx6vbAddMeLDrkvAaORWblJxVaBUe8fR2JeMAsJTz3s3qMZqlv7dCCYv/nWKzblnxptvw69A
o+pxdGnUVWRD7KP5mPaAb1dxquKsurgojQeS1xqOkfXJcy2TnaUN6hQzXXzKsZzfBhP1DtnsjEIk
sK0WgNNeYtgurNqD2KQiJQfX+vR9RfqC3dkW0BYps3K2F4oNrRapkHXWkUnze8rga/3t11qsoA1X
wmpwHMTo+5zVprWpZ1Vw5uuF4Sr5n1YfZSTvUKQpYQQMqJkvKsSJyxVxeB2EAHWejCC95bR+gWiM
wpV/CtyWzrzW2rXXLyC9IpALoogM2Ab7lTO5eAQuf68JFl6hSnqoQJQ869VyUEVB3LbMtywzsWeI
Vs45XQM4tW6GDNM51ZvmhP9vppDo2hdkbNf6+kEpMAmZfBfnD3GpTH/wTPrUhhja6LP0yOtpQwhU
Uo80FLUwnwOzbUMaAIgRvXL3idNkkucVaNWdd7NwMWBP611CzKhbJjzQnSUItbVVm4NS/jB7Svdf
PfoQ9MB2B/1BU+kp0ySqNulbca7TVEJ/3JS5FrfJU9xHklrp3LREBUTGBFA9xs5koaLUHiEiTQ/g
jEVfM788lHIJ3WIqQH8Qbdd45BKgAVJQmG8B5uNgWQbF5UrHoEzbmJtSiiXVshqbPFn8Hmw9Ttoc
fX344YRsfEIOBNKmvEx7pyCxRprDQ4gu7qxW6VBuB8QuMLBRKBxPtLH9BGu7m50G2saFVGjXOkJd
vByHwAoQ3IGY26SwKEq0Rh5KK7VHGPIbuBzNSEczKpBf6xJMq9HHjQdrHgNysUCzpitGN3evayAp
tx5Pp/1FcE2lZP7zq88/GeTS6ipF0MytIalINT4D6ur9sNiIXtaNpZxeQBMkT+mw0ROC6kO/dpkR
9MWRCyk447fMT6HAq79JFVrxPodd9+xzI4IdUKmTVvdaKMBIjKC9L2olXwca605lgWGbWrhxaSgg
J8+1YG63DsTqp8U3twf62DCdHaotO96jfEZYXAakii63hYwn8emNe6HfzbUjferiK3+axz+onBPY
IJqTJ7i5PnUo4YuEfjLhYPP+GNdja9dXoT5Yi/O1xoiHOTeCWWNeK52KyawMx17A7r0hjlgT99yH
XL923wF+pE6gg36pRjSQxvAjWQma4wdZ3fRGIKmPpfxBLyNVfhro2nLtGYdxUra5MpMA3d7YGiph
pPPafjldLNcdmMwJxJIgYwZx2Z7Jwv8x4l6qRtjHHHYz9T25hW0Z7QwLevg9QLVZpU+Y20pmOF05
eZ4avh/5de+zJ0RKQbJTpBRTUk01qrBWwFXyg8cBsbMF0r/c7KHcg3S8QQwTUVTgIbhMufpFdQIF
LYVrhhi2jAkABmu2IozJJnunsCkfc4O8vj0HxRVaF8rernq0KGMQNKU6PJSWp7GXeMssGjcUCCB6
EitWCwGlOKep5TMNTVqh0yWl3Umy4Ksf3iGdyI8BhaHx+k6VUu37rVrGav8eDVfkFHsKLAVm7+lH
M0HM7ZQBbjgEBlqfDU0vSrcW9pubtcHu7JLIBB3NQfnPhkA9uDL6zT5oqlRiVjQ+Zj5cWkmXItiL
+xMNzpJMuzvXtw8YuUONZH11t76Y/06/b8YHwexsS/8NYUJ5zlPlCiXWKx2Lig09R3V8M6HSc2nl
37dQlOU3/blBE6TKazVDFPbg5nQzcHMgly8XFJUcGCaWe1e1EcWv8zbbjLH2eaOGV21fQZaww9ev
YQ2891IxS68kndawAqfJoI7xtxzrSl01pZb4UO0xsciuZthvNB/V1ZmMZSN1Fuww6dW4UyyRmgd/
uDUZSHky3P3QjcTz4k0Hzof10uuyHhANhgXgDEWV1n5E8qq2bc7Za10lP1fkQoTO05v71Z650TUZ
zp6EogwcMMu0+Ms0zdhspLmfiSdd85Go2GE1jhTT6LrzLmRYtzF8Am2Pv/gHhn+5FT7o8ky1mqgR
s6LjcStIJL4k29KRQTTs4d915jt1FXV2Zg5N+VTwAD5xMf/usDNzdUKQ2cRsZMWI9/GVlmgAXXO4
vbmmBOP8eOV9VAAaB0WIJKWTA5/I2uDrxVqzufqvBznSs4A1Ki3Vx0FwwPY50Vu+bzM8B8LuRqCx
zyu20s0Q+3vC3nz5n8D6kc3o1zlj57eLhcvxciCSdRC2SwaaBSs7LlSqqgTWN076CJg3QtTs2xZh
plcPf+di0PG8lDe/frI5aSO4FQ1AFcW/n9l+oZ9QzNp2CrOceZznHEhMg7f2zKhY2ED7mtgORGEE
DN0lO6IYh0+jPwdWoJfIQU4pCVdnRMrNB+Ev172iB2dSm8JegYYUJf2IjNdCgP5dz7llb/fAFY3w
znOstyzSN7bWJkSNXEWvcKbj/Q/9FSoDkPj3xRDgVX5lEOQJKdlaF74Jj1tJN6CsoULvk173YyMk
iWuNOnaga6mx2r92uTBLMXVm/S8iIYnBoQjhPFlq+QEqHie+8oUfMQbYl2p0AMMEx+u15fSQVMYu
kEZAsbA5X/e3rrHpMAM8+qQ5Bqlkq/67ntiYR0AFXh9wBmi/piyVfiTPUQx8qfAnTyjTD93gPN05
EWvTIiJuHQ9lH5uiyuDITXb0q7U6hsFyWNLBj5yuQeQ8JOjzUx9w3E5IwYRgBWLRnG4YuoSWlJMW
RLSm0z9p5jBgq7dT8/5IY1TmhPyoH7voyFTWU3Y6lPLb7k0W1hWX6APuebkihFk0Tbvpj/rikDoJ
3t1CyXt+V4qGtwXHtFJ/aLkbzIj4VZwO2L9fVEG0HUzfhG7ewJX0TLzZD4/i4jQ0DDtkhQ+ZorLA
Qn6u9Iwr9eIPRnvk6kBgbJUOJTDnBbgk7H04jwCi6WKZnj5EvSTqegx47ZALyFNdrd/ChXV8G7bp
8LEVcl0STYom7qiJQusK5Uh4nJV82AQU1/ZLN3AntALl/ZehfOcRvgZ63c4m2GYVefs7UUeQeX3c
aaqVpYbujb+7LQ57yij7q0jDwEDGYbRlhXlhakB/vg7i20TRAjDQw7YgXxSAEpIMM60ztgVCoGI7
czPFiwwI++keyuF2oECn9/dawhs6WqHwihn39mcTspP3QFYFWjRAwIInoykK/6eiB51ZJiFca2yQ
br13/x91FizneIVBQFAZ2EXmx4zkNLtJOzmwigsvZWgysE/f1dXz3JmO7VeMB+3/ZskXsIUG3orc
sILmsVxolTqR2y1On4mcbW0V0ZPqD3+pqX3lbAbtRVuoCs+iwi8h0ulzyhu/W67wrl3LlDu0V67c
4mbC9S31r5DZXSJvVtwZ3cujgz1aApJfNT3fRmtt77y+s+iYCcdKPFAlvXvxI93SkpLQl8EAMm9X
UUd26DeSBcgRhcZ2b9k7/yVb1ZbIoIdwtM1Ml799y/N9lAq0ynSlDv5i8iSjApedVmmZ6dxvrjIA
ccugKGomo0b+7Gha+ogdkaJbXC8i7QuQQ3GSdC6c2FN1Cvptbr+d26VQyXz/oe5J54D4DuEpbB6l
RLPp1zSFmqbZL8ceRi22MquXkRu3xoLEW2UzUojZ9en+k7drEssHiA5XuOCOi0CpNtm9/mlg8sqP
a76BeBZJRniUu2jDak9Z/ZJNWs5Tyq4Ql15v2JFvjX/q6NsnpGQ2mdbdaOvJ/BRmx/coAbQ+2feN
PgZYE/6fNzFNosozIN5YDu631iQ9lABMy5km0YsgI8kTSYDoIDfe5/OtQao4/FBQInJsASerr/MA
YBz90Zp//X1DoISwUhuqk57otYW3UVqLerp6IDi7Q14jVBBO17Ajrif/mxJLODk/wTIkFks2pusL
YqboSR+uVNbqxrUTrzMC/Xgg3v+9zTmv4IPVfBj23YhAjBFEW/2zahUEkAqaEDxc2jyIVVKqKSL0
TwfMjyEZy1xc4B6f4+em2mRzOag91/MzMgmZrMN5dHbsykaFPezc2KIg5p/dEM2X97b2DItxI9Oy
HHVT3kuho5h4N9/H+oVLWlWrgyOf5fjx8tznFfNBZzN6mdJVmezGlPxU2UjC6rWiv9OTQd3pDD3E
QOb7F4/Xi1Cc0xPuq3Tt/xjYURGtAyPS+pe4/9DrTK7ZPj4PrYwr1eRE3yVWVdrRJx7vNuFEe54W
jMI0YqOwv3kzgnG/JRRAuHWstgjH+p1Jq55qaDgpxEBXnhqqoYB64qaM3HrbPIfgx3F1OStp0mFQ
QdVRhykM/d5HPATqpT0Nf/ZneF7tDoB1ZkT7gAKz+VcKcJH4ZPjd0KYfdKFl8m0lzvcIlf6b5XSi
fVFyukIDYpo8Xl+T8NvEtt6h9OfCc/scKkEOg2msuzXHCuEn92PmM3vsTJrwU8+0VYBFScJ6dJdO
qkHzKdQKa967Z3tsGaChTLOBxQvbGzXP02kql2rYVi0g0NUhTHeOLMO6usPiYS9YdZo5oZWKdeeR
9f2EcnziZe3jXg2CxGpUwlyIWOceTkOr9IiiipRRpVosLhFrF6PyMqBQMrtaWHQIV0m7fMsp2dQg
yr7jTA4aYLTvsL1ek38mjaA/wY/4A4kQfyzledaqtZBr1ebLnQujvq4z5aJCH60uSK9qXANk8M8m
g20Z2tD+5eJByWwIDTpQQI5t/xSgBMFLL9HkWEwZ19NLPOR88zqJ2sbmd3g3BvGoKPIMS8jq5t1g
J19emSfov3wEr0fzEuk71EoD94RO6r4V0hbvm1PgUi6bDgnDdhZg9r58hD95MNajP9XP6Av9zAA7
293LO1kUyzxA9o7RO/nM3VD1Z/p4NJ8eflmg/Ssp0q0HWNvEYRE6SmAVBZa7RqKM4yVp8elnnslx
4s+M+yJhaalGUwotL9BvIJBu2s4en7xyyMppF9j5jcOgkEVyOTDo2JZpPcgWMXHsmiWtDZ2lCzR+
zXSE5Q3QLE2K6rAKzxkQ9I5JkAEsceppOzb8f87aHKpyitX8N6h2oSRkhOsuMcoVc/Dt/iVBQHVd
Um1pbPFRItdnVUoqIoQJL/R9v7cVDhtlP8ZFIAYH6Rc8J0eVgFR/TROTtSLt2k3vCw0Kh9Z/P1yt
8+7cleV4BU/vPIYTVXrfVyRpPFTpB5OHHt6y4NpZNtGWjdFe3QTXSoknr8ALQ0dDwb/4kem1JMkk
JdvVaUWCBtoW2oDNYSVqHxSCEeROMthgC2I+eUk8TOZO5oHE90wk5Yh5haE8Fu0cQsYYO3dNe8+O
vvqQN6ELqy3m7HbnB2qN/BlEVx3JPl4Het4AQOaWWOkFSjPdOxhGEdL1VwY52Qu0z4Rs6W3MwmP4
vzyiKf2U8E5k3RNF/1bdAA+FXF9h+ihQODkX9TQwTTcAzwtd6t+4ne7NL+D/a7i8t0HP2rQCaG0d
pavcMQcVYQCOQZ+u9c+lIhlxpr8qUamvi8LhqE60rghs0y2pBMmat1BrxikNQHcCCUnCAi6tTI7k
/44WpIc0lMEzJ9v3h30cMs1/AjBU7T87/AB36EbNMhkhV6L/MxxugByYCYMJq5toy5fqMDZOblpO
7QywO9uE9TwKHoFG7ju5WB3J1ltKySDUlwcBiaw5RMq+uzLl0fSHvF0jJKHde9sKa7nrYLbJ9sKN
h7BEIMWhrS4BtGfp5wfJItRjj7sIF4kzCDoYJA+n9H6IIwUQA7/ZvzQPwvTnHxN7l/9+l4gXH0xk
bSLQzkXI61tarolpMlGrzkp2MJWlGtbQj9SshgMuLjH62m+lf6B8x9248+0qhy4jRt5uHFha+hzZ
sCTFAlzxYWv1FUa85Ai6C2rqe5q6emcFU4BMiZI4q4FLGfXfQi0CXhKh7TJ7sVuyAgZmXwQHPthv
lAKVk1UeHV7GAxRKklI1PShCSCs7uMFMZC04+vhuRSPdyvKX+b++QcniV9goyEKVx29xIx3NrljA
D0mlKkJhPQljniLWXiW8VdZhmeaMDUE+P+6tybczeVYjZJIhemL0KfkDm/ssIms1GRPgwSWvfkAm
HddwDQB9Ml7LIO2X6fmbAOThce5ov3JpEakPqeD/eBlLnQA7nZ3UGBmx0EHtd5HBTbjRz7VK24/n
8fbLnq26AVDXwAM8NH4H3XbJd+WGTCLTSRcH9rEPJmXXAmfOcubEtDlmJIfxB00a2NsAIfI4NCr9
0s13zm7wdHHF6IJNrp8SDSgzuwMlk0uZ6FgKYYWtddTTTykrpnSbaWInS387zFFO0/HSv0478GKq
No412jDXun94dd6dQ7X26l8v9dO7musFBQqRMX/F+3ztBY1vPijcDKwWoGBR/L8qhgDMC606u3Q/
hopXJ7YlJa9oe/F2R9ufiBk6jHM7hmF0+y5dFtEP0qQC+IcKQdFssP1D2EFS/606pgcnGb98YIvO
9+SrSZ3Z+pm51QKrwEU4tFoFwoYvuohuLvAUTukUtOehIfvcZt9FR9DGr7oVMumLSln5biRMYAeL
4+EeEPtuNKXeag3RyaCsUY9jcA5fmYHAEshW78a5MCYCmJzixbkPjOxa7t0DVer6FIY+TQHmQ7d1
csUxJ0IjBduZwSplpAs/nYzL8MdGb6IZQ6HM5pNjOjBpTqrebVltgu/Vw3F1oAYegkaFfUfVsGU2
G82SMivNti+suDCX8wvBPJi80OshXzehtoDB5XorOBGOL/jY1tsEgWL+4olxaRr+RGTmadoWInCU
A/OEoMJf6Rtq+8KHFY8jJcqfczK5ylNZjwUUVh4HFz57bjOQVtodLaSS0bHEsh6OKfW7RcBWvjKl
gxpG852+iSLPOLHwvxklXtoyNYfrGKNZwKW3ot008lsxdhbQXCiWlviOJ/NGBVaMIUY7MN1h8n1t
zAW2hveAUM24xfA0vYR+9FyNRHrwlnjb5UDNKiPTGVLe6X6Irib6AgA38KimEGt0eOJbBCpPEAPj
yNNl8qYJIcwe1B80p5yfYtaaY0llBjOc/KukS+qxKbxenriI8d28gM9El9Du6/tuXD0cc/F2kK8K
mbQTOJfgaVf8uVoSlFWMrD2mQfPW44ADCzjuqdPr/pE3q8Ygj0n128ajUtiRTojjIqDHQTMaCdDV
2R3+wQOD2GxqvNXVSxvWosQ790Rzdr01M9dKw4WfetFZOlyDNk5arHeq4DoKZul2JQuUY2nScS3A
zlKFBX/DToM8IIZALJ58mb/1AZmhd9NNrUyoxWHgUvVgIks8mz6e7lqWqyGUdEQF034Wk7E16IId
TUMXWdjkkzUixp4HDx0g9Aw6m6/MHSyRz66WRz3MVz7CRpb/8E4v8/OJLauBQ005DLTYW+517aik
RAWYec34KqqbOjMSlCdYJwyy+KoY2yjEDrLpQ3kyKW7FhmHFm93Q6lWfkRnYg9WltT4NXpvHnbv+
z1roOeom80KNZ71BunQNGJz2Q2Hw4mCjdGaqkZUb5RgsY/W8OODX1RWf53fhLGuyI0y+XhkD01A7
UneTUxf6SrBXhcnjzGvv7i92I62M7Z7s96BdzRdGwVWnRBP1fq4czX7FguqTFwg1HLzy4r82rhsy
sPSbNTf3nacxU0hjAx9Bx3vLto3BEaycXtePY/lvNzvEuu/qhptMI/TD1gIgcZZObfhgsogmEZHM
9/bTRyMrMdf9w3GGtPCNVrU9mwbqy6egESCnY4OwQHNUB3Dr0La1KTfUX/4CvDVO2sCXu8/kUz+F
CD3qoHY+GWHSG8TaoZY7TWaFU6Vfyc7diVDKPxWp75/BbkKUZKv8kK/Y11TOUk9WcqmlOMFVv9aU
cAUaVi2B91DPS5J0J1C6lFiu46tELGCNufTaFDVKZOFvM/VRF1Bqb4k6/hPxWO0tn+Gr0s4Ro+oE
VJeadDXOkwjle70fpQdcOP4pDFlfzXKmTlSLIVGTnO2lsjGuodC3KltXa1LzTJX2RRjqYOkzjXRE
1SUZdVUPdELQBxEgxQcV3U5MQE648/1MMl86icYg7Ga3XQz/OYVKbJ5SYRHAenpmF4sV4zmrJySh
crXMsCZRAg8BDUc/hDkRZyfCvGca9kBoL0sRjK27vLawL4xy0x1TK9Aoo52iCJPksAMRlDpRB7jR
WhbGdk2197KYvqmvwkxaQOdodJ06ZIDm6CbqQbCXWOTC84YbSFrqlrEPxdEVbR+MyxXslFfRYVgb
LCNSAtAe2+J5jIqDpCOx9mWrokteXGR8k+jffgtX5OtEQc6145HAJ0GG5L110SmEmhwHjiUJXm88
e61VsTAUietNyPRO6wk0l7IjQSZbrlXgWb8h7jrnQBmV8zwk84WDjLzwkj1fJ0RSYwDRr9wQz8qo
IDURiFVKc9A96rWaF9BrMxk8nb2KXyNH2HfuE0rYD4EyyVsk8eBPsXkKVdxeoD3XuW++Nl+g8VwT
DCEiZ0x0kgr7Bs68ZIQ0seHcqZz6i0d1yQgfSuMWLnr3dh//cfiZtOP3rNreFZq500A6/nqw+LF5
q0RrDocS6sPWOmAOjtvc7iaMNUDyqfLJ0m50VzDVTvPvLPQIm0USYqVOw5RTu4DvLOxPZjkXCycv
aBQdDwpt3azimN1zWEgQyhygghlK8EnvU2gs6vZyQC7jqR3W9gigaf08ASxBxSXJMNdc/SGrQ9xu
yXswuwEiquAYvSpJAcPr/fLoqH6gDlFuQopHYLtR2EILncW6PAlJKPZntAtVmzJNXWiEwDuHhrew
8zabqy0QpHlvUULJ0LlWRINwGNJEDwFOk/Wq0wcKFMjYT4byEQUPWPXXXzszpFLwRj534oW2Usni
ijXp5kQEFDQL1HV+o68y2LjLwlphcH57QejTgk1z9yZIROrF+pOxKBSQf5L36u7JEymzHjPM1J5S
IviaYZaoQmorkHGOtJmzmVXAmkoUJ11lwLbkwaXKdnLCNC2W5r6fT6qUu3Vjy5/wrGz42mzttr9x
pR2MuwbbHPqUg8sQ8MYSLCJiJ2O1bKjrZy8/zg2aXDwMJCHh/N+X0KkSvD1dG+FmbJTk3fXcofqd
NCVW1n8+00ZUax+yEBnGzewIQbGspLwUudpbwwy1zcI80KbQc+yfTvyVTWMP3K3+uwne4uM3TqD5
/BHAYPLOQiVR4Sv1brXu4gWJ7gQOVUti9I/X6q7zHrsmu8TpotcNCAuZOzFXfxXV56juyhm72MTD
JO+j3Yh+TIVBENdnn5i3tnDkAisj8vp0+rU2CY49Zr9sZbMJgyCxkXCZOEj2pvNMMKQw+C3Pefnk
Z138y5f0cy6I6HGW3U+b5gg7i8kSo51FZ79Tb+Zz+qz0QUJ8kWt16uoRDMnsBO/fYB8rOkFPVuVW
hrNmi7Xg+bTRyVBHGHYxy9Lmi3nUdp3zs23TWldF4z2Rbf6j0Y81fI/vkguuooUGtKftKg3Gco1Y
20w/tZ9i6+Jn4gmzIDIOsrwbOPcwzfhRtEUoUPei9+g03zfnW96ywCxroI++EF5AmHHiXyHkXYWV
b3XM5u5gUVsWe5MV72nZfm08AEUhfqS3vEw5/je+bc3Q0h2Ub2h1nmVNBc1gydwm8jjwZAbl4LAG
FNmPjKyzKajFXMOMgSRUM8M9jIgz69fK6VZOaLdPmSyZ8xeYsvHy4BUREs3+10eY09NKi8qyZtkK
n0lnckVv41z6EVZZ3htnwdJD835Mibr3NKwnj1DsGEobP+IEWkWJPjdb5znyul2lPBssk8Fo4x/g
mhzoa05iyLvaV3kX55k9RH/D8GfSEjI3Exi+oVJdgsp6S3vWye4Gdd4MofUCHS8VGcI8KiW6P5Z9
1NTJuwt0+jMOCHkVa7i/aVWq2mhY8WDnelHXKc7gvt72imcLkvMOROUQab3uK70TrBbS44tPsomW
AAG2l+iZE5eemTdWEh8ncY5u1MwKD28YnlVGt5y7QyVYI1SyaRI5lkJdxH8SF9vyLmCLGBX7/Z9q
SoBtk7py06cZyUwQRVMA0LC9IGBjHnScfClGPOxnqtXrM6r03K7eNIAXHXeMvJ6CaRTKd/D+S/cw
fOfrDeNFG7oP3R5ihT2g6Y0fy1iN1XVGHLR1f9tlkXBT27I17WNz0GxygfjRpxf4ZDbl1OLNH+Ww
6G2UikDCEna6DRKf3yTqLHq7dqREIpeK/KUzYw+jp5HOpG4Nd1xw6DGTETCgw3w3f7t1+tjHWjP+
bKycPQAuBic+3mNRnAP7yZo7ocKiDe1JTlpKgOsjfhsTxLPm8uzlT1xP9GuWQeSQo2V6L5LRSWu7
PejwjWxVdmMNVUPOrK2Tnhp1Q84AnUeC3e9VFJIUgv3hWxtgoxw6KRbwo5wzTbzDosdlHTvkERHW
+BMykm3aPzcpPuhDgTELhqiF80ElDtwIHXHidUlvmaXQNsmsUO10ittPowwN6UAIuDI525gWm34m
elcdOC/kdfQCAw8GiKCiXq6pqIvlVRkNc68PwNf1MFKlDuIRM8RNh6152mrQCVRSdkEBf3q6iV8H
IPvJVJ9uW2243EPW/iSfU4Xo5gXqmn9XZLUe4o6Oj67s+kqJOYytP9ZKLV88NpUnXPS05mP1Ls0i
ma7WVhD6i3lf/dVTA3xbP1vK1fYGDAflKlMLH2ssxULIX1oav4saSKrTy3MmDqyQ6ol5EsSL1WaH
C7slsqEs55FL6Hgts9jvC1wGFfM8TIoXj7fPu5H5XLplRNmkD81UPl9d7RD9kT4cDTmN/E4n4Gol
ecoucUPB7eLWGApdVvDXVjkiqYqC3Npe50n/Tn44vKjPIaRxt2uKK0IDOPDVKYxuyPtmzOkWXt2l
9zsdZTjjSrnctnRJBRWo1qBGoMaKzz9f5cSEeFRoihHETBADCUmM5LYLY1Hyze9dSaP73CE5K6O3
zKJ3UkcKtqH/b4uKPO0riFtcBsbZwCHYI0oZ25Y5gfgFXVn+Spkz+6PRY8e7J7XPUWm36q4xALh8
olpXW6x6w5GUJsTlKwM4F+I7my9LEPyv4eg7aQ/9bvzDlr2P5NusKpIR/tySgYAVcBa+KyRPC2ig
8gzKeUy9IFm7O/uykHjKN66Jj+79v3xDguTdeSy/nOB5V6UzEmLr8jXU4M0wvewP810POaj2/GhY
FpPBG5Aj2jhGNXFaIHPatd6GvqAtoEGaCOFOryfY/+0sBLe8/xwgKDOlAhODkNJ+OssUbNAxe3mW
8U+Owv8TMf93qz5C+cD0G5fX15wKVf5opPepbSB4NOn1BCgU8IxVTIsOtu98ToJ3nStNM6L29Uhr
g21v31pPKKl6HX1VmHrHFSGMH7c6HQbfO3qj5YAzSKcPuiB5kSFStsoFCCi8YKSDBufT/aTIQBwI
oGta7jm5SD6RC+GMgmsx534gze1kyz6AxuIdnrLdsYLTosSZSZGPemv+xQZ+kMQ8dTdtSKMVoqcs
xUNC4GDpuaBIUurWTMpkoBJveuFUmC5rGMXNuQcA3Jxkme843A2p1M26MnCVyuz1O17hwyUyjAto
AMfmKy8dNqUvDwhlRoRXqWbETJA06s1MuwwaInN4C8gUOPGedkK709EdTC8GnFBYne7pJzwb1huf
j0wdfXNlduD6orcI5lI5/LvdyFlXjLm1Q4Q9DtpTYLSWldGAGNxlGvLJq4TmkhjqRqMLTUrPDeSJ
PDTwT3N500yz6vgjYV7BGUooHWggSZ/dqQcasuk53KTirSVUhw5/0eQTtlEHT7x7R5RVYKdVnRTj
/PUoBYKNg+AhkvnjvpO4vynBchOIUnLq7/glMmZEmyTklXdnwq8UATPTFQL0xdE5WwQPoxOqEGY9
Vl3n2P5HcfQYi/VqDkQo0YfPdaMWH6mG6GxXrHLNueoc/0J1100tGUrZFcMAZsIfPMjsC+Ha3Lvs
mwzhXAqn+muQ4YA57igfsJTS5iGpnNyzAn1QEq74bTMIOV1aJRl66yXl6to2E6MapvlaH6Q7dnxr
TgwzXhrDl3N+1xec+1gBnQSSAK9N6hfcnQqTdDkobNHVaVI4xCFfM/hE5RAz0ZVbm36W/rWAF2xW
tFhMDdCSF8oRycFq5TskkyvTNafPTFa+Y5xcykxqXl2hkVc1sBx80KTTWYvKfHUl040PaONKpWoh
OBJz5I/kyvFk32VJ89eU5EnTmbxl1KKKTOxF1DBevGJY4Dz2uORaPvow2QCx74Bo/JAEh6ODqSYk
y7ZQADZCxd7hTCU0wtC29pKPST0n0UwB4ggNshjT2XCaecbviiZMsWSPqVNSWjemSc+U8v2/uzdS
1AGNhhesAPhp0qAic0rq09u9sAzlPm+KiDFgy+LzQAm3WGQDyIwtQnHlBFEvg4uVaKUGFkZv52MM
It5vBrZx9B++Q1VcFkF8XZJ/KuasNfOvVCpzBtM3otiPaLB6Tt9x4dItviw2bVlcrKwBKxOBMrjC
VGpQJ75KL5UoZ5RpUTpuzREfYRWg8gH/PM5ZtYrE1xogObBAtOSK/l7rPJsmDAtkEaN6P5fiTfGY
4FU2dlvxA7kmsKmNyt7eREImY97hcQ/Vc56GBIRMBUcqHNmgMVgjBvGZWZByQEEgyIaUXsPDT3FF
37PS2vHO4SIkQC5t+ZoEeR5BQXs+tluMFI6zlp45k2u7lm+8B0+3aJbkCJQBLDUcCyFycrcFfpyp
ykeehgjeEd9YEKR6huaBJEl+Xffj13ApN6PWDSSNE9v3D2W50laf+JzO3rCFnddya3COaY41wfDS
VbxBlog0kvqWpPsVFBsv6KPx6qagzi78E/szWpPQbJ2O3Ho+Z8F4g7Cq6PNxTJVJ21NTgB3mw/fD
XXwLh2jU+bdTfhdgkhGd53kKuIOYDgQTSv/By31GdPD+LVaSU30C4DHIFiOWwScUZTyEOyHQIPY/
I5CVipS6SMr2qXvlzB3VmUqzzh1OZrmG+Q9BQ4SzI7O0Gd72X5aFxbJ0cSG3T8cU+eEGqH+9sCXh
W+J+FtxT4peKUjz3ZTGEZSLDEjqBuNqNjQPXx4lyBfN+Y92fQKopZbzbB8u+Gy369/Ac2B1t5K59
OtU+4xF4Bqvp/4OJcZqVu0AuW0OVgDVS9FOhHEr+kWjKR0qfhTT+VGOXAUvRjijBexbifMf99+iF
a7hn/JNKZH+hzQH+xOWKFr+j7jWHP2LwLKv2YlQEV3cBzWbb6lIczu9SPYu1PdD8zfLpvilupgAJ
k5coMqmik5VzbrZCjKmR+PvGNscvzw0MaFXAvtXvC3BS7OcWHcQ075W0VPVOnB0wJEF/quxgC8BY
ttPjp4UNmeAizy43pksjNDGcYefNRHA0pPoKYDycPkrbv5vp4L4a23IS/K7zaQBl4sgA/cgFwKd8
TGStDr+zTOfB2b8/LRWyjWrIZz0Em4nKHxL2TqDj+ZZHA+V2Qg8E19mYNxyScuHKgvb3WTZr48Xd
fmUjhibrWpn1seHa7oRO6sTgqp5mNpOp4acSlKZeef64CQH9U90IAK7/n3zpj8ZB2z7uTn0tks4W
Qsw6o8aIbJDotF4ABsBkErJzeUHF0nDJKHiBIbTn5hDawISZWf4nXQ6N2/r1IQJiJH/RWRwe+EZu
OOerrvVCGXNy6lHvZuT0RtKHQVQZbmwvbWU7zQI8Nd1CYeQc+cvnL5D+d0gTnd0E9JCfyz0ASNE4
XOJWnSLH3Mo/MY2qhxG7nYUDAefoF+UWg+V9SiY2zSjsZhPGmVoh4aUowcoyl9mL9phiMK55Qfs+
UxmdKYb1HmKI6dQ/6iEF12Jm1dGrbs5d+5Fg2j2V8MG/tuB30bmWLKjX2zgfI75EeFxMBkeRuIJ4
wo0ICJ63taX2w9QejEnKntp1nwU8knwFI+VBhGBT3AOrt/mOvEKiyWqXG0UZ6oCSUqtXeaYj0V1M
mhjZddnlYC/oBZMETLAHBKUxg02OQfXncf1gUm5ai/27cWOrh55Q6+N3xC4AMxL7GHkzv9pcXbIr
aLyZjebgSnqIUNWclXr/EHIBVk9c3bXJAQiIEuDi/vdrXQvXGI0n1A6O1lkcNUo6DWch63nPMeIX
nLCXmGyBHV/B3cfevwvGOdTvQ3vI3hncVdF+4yEfx2mAm4FiSjEye/Y2LLomdejJcASdJhzVQQZR
1rZme46R2TEjxH/i6plJxY5DnzGdhftBGomG9CaIXZptIzRoxxQaWIr3DT8l3KW7tdRkeoqFRNsv
sHV8fE0GsIxFiG3ha2UmT8dhpyUgyCNEoqKsPnU6AxpOoMZnfr0cVMG89R4iKKSfqLfcqMUZMqqr
w1GBbSB4G8sGxvvNs0zQW3jrNZE9s6zxLbhtpuaGaOP8yrSPwpl9jqx9R6CyMVYlrJw5LTnpZWzW
h4/ofiyHMP5aaBJdI6GdqTRFpSSyOCb/TdvkzQaTAs0cuWGz4EbbMPVGjz1aAkfeGJbfcbo2klH2
7Bq4+jb5IJg7/5ELP/IK7ZaIUSiaqBlrKYmjsCSPEes49YuVVxnQleWDQd9Bn4PH6YnfA9wllNGA
tiH7XThw6EHFBseYNM1Pp2W55v2ZRvxZpTSa+hmt+Ver+iISBi5VnP88ILwjihzi82tifLAM6ZNT
iwOoxSVjQ23JE0OIQPkGFVQVRpFG6pqIgmtrB6fBaZpDKNWO/cH/GdDDNZucA9gYVdt/agDkhamg
saNzn6awUxsHynziCProTaS8cy+iGfE2dpJwQlFPxk3PMPsqxr3VUp0gOR2FP9Vg7CS/4tJ+t/6U
t16Lg14cS2DfF0/AWOQi/q2wEtEWI91OBb3AFzcasYzERSkZ/cwGsRyIZRbY9/VZaQcFXKP/KV/i
tZhBxuHjgh4iYM+biYmhO4Rh6YfQ5TBNhutcykOM6ksjV6V9MQ+VozoXA5GAYeNm5XfTdLgVx8pz
y2pc63K+tTqU6dWM0WIgxNdLqi5lek8iI9QGnSzx/wKEFB7JTtfD3xUOVXMLb9F3aLJ7p4SK+xtD
7wQokYTiR/MWbOA31R7d8q0IW9nn+hiJFo6Hm+dr1X9GhfIdHDl8uYoYesOZ/qgzRoUx6/rYtkAW
eN5Sa1ZtolCeJ3iQWMSGEdX5DrCjcrZ6WfOyax5XkJ/W5zdOI5EQnFINCDBALDF3nK/GB1tAfy71
jaZOnXhJZaV5F8fBiY/2dlQqaV4ZbUVm+/e5JACw/3rjegwLSoH/C6RXOb5vr1Q1F2DFfP6WhIkJ
gh5DrulNPKef0N5Suzr4qzzz9IqK3Op/SBqbp4MrG8ViSmeeiouhcryrPe11pvqybPqJydf7JFiX
GuwwwuhSAqlS7xAK0qWF9rHN2pOFpAtpiNgBU12oBy7KFml0kWsxUIH3z7HzOV+f4tcE4v5j6eB9
bbjXKT+IRDL0mzpxDNZ6Kjt7fwM5Skx61lQ/ICdvwsmdX1AAY8wLRJRYud0/dOTnRQYs54/qfQlE
cl6BkViRy9X/mHavEdAvgYhbyVyffgIIgpeUMR5RYZh8vk6J625Erl5r2/ytmAmxQKlJgCRiOi02
szZqX+WIsOQD1sSBjJ1Zwgh0p5hIWwei1p+xYaNiTR2t+wTo1jrmaKereOYMwlKsHbJQeODwl6W8
Qs6nefX6H/BaDuB89SR6AG487eissF5BJpPeb/CcKs5hEkFfAem/KVjZXJaB8Z4pne0ybhJdtq2W
Oadh4KZLBoLBQ1hzJXbzUTDc2+2gbfZxMnjZ2+AV3h9bKe+UxYbQgjgIWqKJ76Hz7fH/awztkzSW
gLcwW0d0/3f61tel75iEOWfhk2E3HEIsGGLwdJ9vltM1QSdK43WUJ3cRFJI3iWYC0qrcY94DISe9
LX3KQaVtY1Rids2ussfIijU5pKz0g3sd+A4CWovYZmDjg0q2H6gUD4+nDK7NquVomKEZogQOzz52
xhnuBkwb0xhW+Eq1aXh2FuNZm8X+7dG4vcX2nGP6izeIXI9x7ZjgcEs+3RdwgVRUEZez61PlE0Bq
r95N0Wl7Qa+wLatD1WjF2cf0ZsE+R2bZYT8U10fIK+2J9/92mPn8/RhTb6k68kIzNf7SBmgPtiwd
jsJLDV2m0uEhQDKj0QIy0RlQh5DmNUF76KwBgNjFvfVSQYYtOvchS/6+yO6VAJeiIpon5L2Su8vE
XRvuScl8bcmjBvvMDntqEsnYQGaP6al8kELv/P8BoZPC5g6iiZqjI3grmqXCXDGwYwcj3qODy3od
ExVoH0KzRMKSMGEJugTRNRqvQNwVIDj1tRpvj48BsUtS3UJyHyTwZf4Cn3QJiJwJY0PiX6DIYVWd
rVrlEE7FPqSkmJeugC7JApOFl3F7MbBj/qM05ufgq8A9PeZ1SlVDi11jtSPZf0LKBrobd9+LFik3
EvYBLKE/6w3C8yd1kFjax1Qie4SmVCUOpijWEgp3SDkjK2XfBLtP4fcOIX9U1M4omHnisCP7wgeI
Mp33v7rzzFO/ZR6KivGxDZmRRZhTcsF8Gx7vvxir+Cqet1RojQkqlXc5MtRYoRLJxWLTzahPa5Mh
EO2Fw+wI/3axpht82/vkgW+6Lv4tJkmlT+pBE5z2IAtmCXDWW9AT3XEoZAooMEoCojVnTAxEz9ON
mca0Q1o7JCsWBoH7fWaeckugFiySmMjIdbX5tzDa5dlYJ6w/78u2rnO7HdItI8Lu+kJmGaDl6xwC
IbkiavOjYSowrJjNG7dCk9F9Jr9Tf3W90Eg8g6fn0mdWHFNIzWKP1gE9M0p75pnxFdRBVa3GfCdB
sUNK4bVBfEgznSQmqzGk26Q1n0Z0hiHrGuF8hgHD8k4lmvjLiqqN3yd1tOqbtMLy8we+kmZCcIV4
3Ql5VhunhF2c7kTgKx3dDT+ZOdFk8RfuHi0e+OjwkNJAM31STVPSe3atrkZk6kHpWIb72t+M1gvp
oMkZNsP4tgG00Pq2fCvKEiD1/kRrC29T/2tCB74tchP3deQuJ3uNT9tuiZBa0MLFoJ24+mMNeDUH
075R+ms21HKZTPcNi6knCgNfJhoL7DA3ymr8hUH24WZanrK59M390E9KyB7DUCfqOgYHJkx7UqOO
1CWIuGI3syzOpalSUAz0ME2ks+qrh5DXvjeW9+DDpQ+x2w8Tfcrk3fPs/UUrKIrY87MpZ2Upsfnu
GmONoODlUzgtfnVbJkqT/QG968YatZJXvMYPCd0QhQAxXdoROjrzAovevx/sMBJJ0b+mc5xk7F+F
GF3Q4/mMv2YGOUXw6A8dbwzr7NSwBVUBMVdvS+9TiZlz1w/wyHbGcNcwHqjwE70oQzSTxMPnHZIW
odwDLgUBpVJrngFDLbpt27R7DbbsFNAzj+HbW6oJBh6PXPvWhrakjwJgjcHNweVIGKR4dJRiGsKr
+uLTcdEW1syl7FEHu82bWDQL8v0pQGvqwwSQK4/wcC1bXM9N+DviAR72IS+nsDRMO0bwo3EI4YhD
djtGdLuQfhe1BnZ4tvhPRuNjMtPzy5oYKcbiYjYG8685RoD31FbOPSVhBkRgthzMnK4Pn1rge+Zy
wQhv9yboc+8hB05xmwM6RR/upfqrgO9BokC7QzDZy71kTM2xhgbRrn6X8pvx+IA5hKUW3VwLJtZe
QR/d4oqvRwUQ4WyLQT/ucKeyv0pLubhA2KIxSkxLoVeq/c4NWg2/Vz5i45n+BgG8Q/q0uKxeDaRm
zECbH7kUOjLphjftD5LH9K7xTWGiaJ51kjm+IbEjVBFHbaFppLjSZnC8Bw/GxmBTYirrBpikFYfJ
ATck+nhAcCozV6n7jtjX2uYV4UyW9DN7QWoiubhr9h8FkdTp20Zq3z1+B0oiaXo4Hy2FaI/Ne/Rf
m6TtWkAiPQOCc5UHgUlNo44ycclLgSOuF1vcyPH4EeP6CWqY3SZ3jBMBXsbRM4GmzlHWAhX6IiUZ
k+oFt1qenGb2SidJfju+En0OarXcYJ8qMaXszpT8Rk8LYBAkkCFyoIBhemxH9Zw+uP543v9dr1B5
q+sADAIroSmYz1oBAFufmobLw50igl7fYQRGtuXMMoZg7LFCLqSJ3E66x1yaZR2sD0DqOnDw3bf8
Qr1ubgQ6DFUQQTTpeG7jk9/OiK4riYnZ63rgICTy8DXuFusv9ODgLdZcDZ7YtUV//7T4QKwq344I
CVumOmxJNiQJUaxw0M8gPhXtnOPX6uUfEe8LxaEKY5TtocmP/Opmm/diJhJ8WBBAG0uc+VLcaoMc
meT5gd7b20mUCh/JFyyHnzu5QiZE/oG7kMI4VQmLJvViDin51xVApJ3iw+k+GfNTSl2cI3NoyMJ/
iXV8qEn59wt7ASgwdEor+5SWlr2skkX2lmZfsM5ZSZagycjoJplHavLRIdzn+Zg/6ogUgpPv41W2
ON3DV1a/rbSTzK3e4VUhPUImfxGTb1emTUSz32FYjcNSstuDR3/JaDJ+oIGckueibtmqilksWbhE
ScPhjLtx0mYQs/cIj9lcmbWq/xIIsnGpYtAM3Gzt1K6BAQEKP/8pa2gnYMLO7bZaXSjRmyyMbYTI
zxaOWgn4jE/EERh+E2R9QvuXLE9OnSSkvQA9Q+XLhQNND0yyYncl2cNLmIzk6pkVhhRg1jYfiNQP
FDSAkjmgsu4jLZV3F6zzSGAzok5aGmUmSv8t/B/UKJB/nCnYI6i4XnxbT/Xoanzw5PfZkV18JP6B
DAv+1ceIqenyxCahpPWP2Fu5Vk5e5gHxT2q4BtiZd9H4F2R/GWGsCr6oU5kwmd2H+yn0OR67GKdv
J3iZhQgHWuDLFKy+JJNqzmT9XQ/iyUewHJ5JaiSY/PWirLM+/5Kcu7h/tqzFhJ4yx/7g7NwsC1xl
RgV55wOtyTOny5xisbGwl7p0eWw7W5hnzRsxBuufxHzKsTQ31cAYPb1ZYRJBKC4RMM6zp25CFWZb
XMkC3AEVY5T70nVi9dQPaomhLQrClKEO7XnDQDaNS0WtQDRquHmX/Td44Tg+gMOXk9ybbQ3NelYW
t6egyTqElb6Sz01Epne+X8yTpV7zjFWAQvFYSlzUMOPnZG/+PLaU4H9pWUtLcTmfbaqsDIMoIi/J
Qk1NBBWcsN07vsE6FVscTXYSB5Cu5UpfctEha5Xxb6XFJbPLGK8JN9wQPAn16l+JHE0BSh2g9JvJ
nCQLN0ele2MN56ZOm4sQmZsN2h3o1I92RVucJWykFg8jsMTC6rq0jMoZUwNy1mCpuuyMUFGR9may
Iecme/JeNbdKH8dRzMDla62YX+Ikbk2quxsi3ZcbuEnfHCBTpPX3DARr22xvTaP2iP6dbuiRKMEV
KluY7A83za+sOia3r1asb7eqjrvNAZmxuzsENL0qOX82/XvxZBqraIdMNpUv4LGSvAKQxFM/2CYW
8nq7h+URVEEs31YXBIDgSOjSbcJmDwhTutTGx7H/PCQcU/6unpLKTGzcW1QdFwdulZsYHe14o+SS
D3DGbRYqnaCC9GatgnZlBdQq6XRMc7VEH0MFjg+bzesgBKTgkpq3b/1PuJEWelY+yH1zA23NrNPT
cYyPUFLOjTBYk8DeEUo7KLgibl2+UaMjzpKBPF+3TGhZxj0cCQu1xQKxO2oEhcFb9f8SLARvRwhF
8ivZDJU0QVTfwMSqyxqcDFHknlGWIcdq4FpV4sDK0BB4Hz6BRS09sS5+nkCfOYa/eDGHGK0Uk51l
050YKA9/RcPO+0ttn+oqj5qC+aqel8wSGiOGMeK2XZwQ8xb0b149P36HA0r4rgrtdPGxvi+Oju2J
YJmsLBbE5EKDWjxlE6UWCRxBPGO1mNWrj1A+Fa7i34ESkLgv0J5eC+v11+RC4uTVvtlk0VdNhTaV
RbZdU7avvmugdt1hV8NPGDsHEuOBwHVNeYMlSef49aEKu8PTCbthXZEY1Vb6d18EcifRomGMUkI8
ENjiHlKKhA7D3Hr0J2IKuEnQAF9Rc1uCuQhEd5K9DfJADRrxBQRdFmweeml231/qtmsxZktSYU3F
22IcMyDZv6Nvk6iLum9Q/qrzW6snPrO6sMUelH6xt/7riN4NUGSGuVkIB2MK9tLzR46ikf/Nl6ol
y0DFfpMWs58IfMI2ysDHW952lMhyjC9uu/AvwCm6aKLqaE9aTW7xvqyLCPJuYqR1PPrBL28Rlxiw
xTwJb2kfwSyMdbRZRPJzHhUTDCdBXTepdv0JBWSisK0QEILvT6i/2PFFi4F+lDxQL+BJjjCn/t1w
xhlllCAnAGf/dEgkMF0zoZBz/9+C05mNaXpFL4ai4+wUUWffxPYcRMgPmcCXJIgMqXU87s+zW5sL
qVf+378nyYzWu69Z225z75gbuoPoEQYpqT4uVlu3+/3iTHBTA1VKlGEHtvizmNxSX5d/3rbxgKYk
36RwQFFTjRWbtdYu3Y9X7Jv29PHRaya3wLQjNaoEYJR7pzZ8XyGWrvEYqDT1yHxFUMXD8iZUYnKg
o7zAlldZCKz6z23LfMxQubfarjFB1QHpRXRZjfpaZ7YYzM9lzeuMprToOelXgwdPhgMDbrPXsXwf
ijo9bIinvyHupUjDcnVYaDeBFypFqQ7cOfAS+gbK2yuM9wYIps4PSkfSToIv7uegcA1/mIRl1pkD
B0tK87aQie0dGWIFHfDBXKSIv+6XF4Ybzf7GvxwLl9J366lR53/ZS3GocQ39K3zSYBG0gocdRCrG
n/Ql8VXdS4LxFz99N6G8ZItPf4G+gbWOyyO1wIVDvFOo1R0i/iiXtni59PdXbDO6qray2XDowKwI
qyo8ep8MbohhhfPYCin/JjHfAe3Ar2lGOU93VH2UV0k0E+w6h+yHPLZP8Gq/EelIMP1JbQTFX3bn
2ZP1I1l2de5FLatxcDsRoe2fFDot6AZk8vCpjpj7zF+GX/R2ptYVAXuauRznhLvjOuueaQDX03to
mzsGt8AI/yI8H93CjvitZi3TXUyORIWd5KRP0stXzCIR4e0mhPbCwgG28paGNQgMFY0U1i9NNkoU
lAhfdc3c/3Aw/UG3Zfv+r+vcMD5yd4pg0zGVNs3dvOyLUqubiBSUyCe0/0ujUvAkDFlDC3RsK2kD
ObH1fruvLUbjrHTPp5XKTTRzKSXLls4EdVsggNSLh+tPlKSn3uvR1IdeZyr9++aAXnf5Jj5Rhwqv
fZnwcyc55x39QGb04dUFonTTqVkd9ZcE4obuZ15F/EBBSyPuBCyIFGXL/qRawrbbHyeonQrjgv+H
g4cuwYK6NL5RTYrJIYE5PuulndfDnBsyt6PNJQnu4On1YuqczBg/BM7scwI3ENXytWaDcuxiztXQ
ikgXKBwUPvHdLhSxnW3zDaySwl1tqGyBYtLjXFaGICuEO5mgOxL3XPTdqnRyGIDlSeIwol0THDmC
vHsfcQyTY0s44t64GlK1ERtnBxswL1yflE6CpyRZNWebRMFULi3F9BIgqR+nikfk02q6ahbIKxVU
1PLyNHdx33S+RZFwSuljnyg09ik95kcnsKc9ET6iEyehRyA979bt/8OzWQRamZKSdZ2zXOoyjfs6
1bij1DqXJnvmAfzyN8Saz3rcEoqQOS02kUr7Z41nFVvA2jpskNmDfFm/hCZhY6X4fMHa5FMxg43X
wLsyPvIUn/OfPZugxcPwvvxZaB8XTY2n80jHqQYsWq63ARrMyLZlAgAgnsWfngLVOK/01D6avNG8
VQi4MtWIl8ey4KavG/A9AcPWv+jB7kuxf8z5XsBS/cXMyoBPQ1rBDEdms6+dIlUpB5CQpsUzdQDU
h8Hx4Igl3PAhA77ORm4GnRilDl/eobsP9HDBzZP2rWu/q8sPg/hAL5xiwB2j08xj5aQw/vHVe2m7
DrPIehijRFzCJJtnbanSq5QybkvcBrY9+/n8eaVqbrppqu60lIVy845uNsDWJF72x2SmKWUbA6xk
VoVA4lec4QIVPTUDxFmJc+xNgVZwe9WsgibeFkYzdvMwOuADAbkRaQFqe1Oy+lswJg9naTN2DsFy
flwZa1xnspkAcPEiu1e9xtfZnNNYTNbdHZunEWZ2BeitdBu7+VY04ZP1YJe+Xq2kW8p0L1rrvWXw
NA5SdhYHd17RxtnZosRIKiE6HgCFMfUB/SA2sPwWUJbMk92BzGNH+IFIVnvgQn6dbTHqUPZRbYBt
q1JKwCrS9bqsa+SH2QylwmEIbqt284n57/jKLp0h+JznNEmFYRCQuDYW3IUlrhpykyVFKz01j4Hp
B1AuWUsMaNdAKa6Yw6FdEYDpLBch1iX3Mq8ySUxKP74VA6FmVSn+fVDchj0gFRwTde8WEnqM19uu
IK7wIOIE92Vmra2LSB1qqOA8ksRnLxeMwcTBLDVHWkxxTpoWIrgLVsbrfrCAupxvVj6PXrwnIW7Z
7f4o9zLBg/G9pS6S5lO3R3vihcN5+We1aRibllKoVBiapUqDMwkL9axTlVyWurzxMny8PRbnseAF
Bg6ShaCgzDsze+DE5oLR1AztkamjkgL/yY/vkC2ysIcuVxFRdppjSCG6sV5DZZb1AGHI+kjuCbrQ
S2BjOMkhhoJJT+HYu1l4LGn92Qd8GsB1R1RizgG/88bEirxNUO2DO9i06PEzyfXAwn/ac3JV6VkL
raLlKdMZZF8+uTttRIAOryvZDI/fUGEhxNJ65jkEArCVjQtc4x6l2qcRqgkU5VBdaS8Ezibmymqk
D6VooR1cuhrumQn2I6F906Oeo76oI/y+EwFWxyl+s4757E09T1SyGeZdZWzzZv7udFtYHJ+Aaa2R
XS/oF2qWshogA23MEZJTwO/jIOpZ3UE0Cq3H9Sr9AllPryYj3WP+lO7zA2An6H0shEUUDYCFXVJp
+OTJD2EAfFDfw/99gAFwZoodWlrQjlp0W82ANtTYCil3Z8ZZVUhu1Kx/ggd1v4U7EEMdI9spBSCG
OLULBNJ1C7iv7iYc4m5WrWmiHqp0ahsE61v3yektnkdf1L5G6FPUBfAsjbXqpJJ7PJmH6Ew0Q6qd
dm0RjHT2zZZBHZu+EsPMISOCuvPvvfC0F1i6xdrTEg0NQYCBQurYca3owoI4YhWeP3EhfQRaIyIv
S3A8RkOi4nJjnp6mbRM/5B9GMu7OsYGyQbApxIKKtw75npexnZz7T3L68rTi+Qtcz+T3qAg43PBv
8sIb7Sgqb2wzfnoKwyN66arnrmCm6hKyt0/u47TkwicjrpZdlGgagj2PcHDp14WvvgWc+e05h+SB
uCTXBacaBknT4apwyuHKB+PdVrm2giyFshRJdm/aQay193JVU8Q2EgHMHv2WDwCwY7DP0+c4yHWC
XzB/JLCwKC385y0wu03n5eFiSMzozg5LpDjydTcOTlDhpEjRNP5FPtj62awYn9kc+uYnsMrg39zY
QlX/aBQ2NImRdaA3/Nn/fuuSKeRXRckyG5o+5CXz2xvV983mZvvWnGHpdYzCmQfJQldpYOwQKGUx
7Q9xj69ITJU3htH6lJle/X3Uqo9lI++lkHfnW+mLnBzTXbVUiI7SXUJecvJHQttsa9BUeS1RLAvA
85YFYlAQoD0r7hf9A/qOCWxLDGz7Z7bfLsnhv7Ekg9XEAYI249/M5IobgaCI2udAEp66/v/wWPt6
7U+XOJXUbqPkX1HcvrK+tzzr61LhsARoBds2buqlEaCZh9sZlNUI3StaXu1B1FJOlUHm2V3tYKCk
pUIPKFJwT4YSAJV6cKAg390bqKLl9V/ww6li3K5k0Nmfgy5WkBkaB82EO81UEgYO/2STjDRL5Zom
QxQ/4twZ03tZG+9EH8fsW4TJhUuNGSotsIsfruM1M86LmmzT0blBrXT0F45+9rdW7ujNIegOGdxX
rhiMHDx9wAdU/xpP3KHSG6zAb8zbthvgmQ1fjH34A79pIr0yktgNan39UrYTj87PU6Ixk+YGssBi
C2sntbSW5Y2HtNW8ICHvRwDM1iYJrM39R9AmpfoxIAKaHfq28vj1ylu9z/yw0xgv53Jf83CmXeNt
cToNLmhTQjT1HOwSeOXLMWaWG/IlBRkibTlL3X4ze642Ndf9H5ji1zvXmiPEytWquLRVxkwp2rNj
aITb7cLMnwikJpOMIW2WYLHybCte2uV2ZO9nuFy8x5TqMRVpoujW8ZVenarbSghLHzSi5HvWIg+4
XE/kazX8ISvYyJuPMH5fBsgDlTZxgFigBtz9Vdm6Cv/m9xSQT8CZVS13YYZgYf69K6domSwYxqU8
f/O5Nj5ft5pIfhp4S9XcW+uEyB0pPkbeGnMdx0zUbCcI9PwGhvrIIANhpTsSY6uY7QSKcMTtyX1K
IXNg5LKQtY10Oph9XKM9wPEkMvKhqsAs8FqEF0QUbAkqv9mN7TLJUGJ8fOG43MrWTLrxq6Ka1Ogw
IIjNl/vmXForc5ZDPuE2eS2Lz98oSkgyk0C1wxMnxvQXrvRJMCc+86j++7OHsi5kFJGfIEpI2Eqd
1fR2HPxzCK1DGHMQny+wc6DGjLzM7B+TOu6CUlxba3Sdiy8mAcae1sIhuxijq9nL3UzUKwxbLSAp
WxQ40OYOMBSvRfNeIlfiSDiVuvoy6aULEB/0tqGxq+iuC/ppSFdV8Yi1KFb9+bON2ddDc0/E1k9Y
sdS4pU4eun0ZsZeN5vwpdd4qd9STMzI6TGTodk50O09SnAdnt73BJ/ffK+05LhnGu/WOXM0ko7kR
80hWf7wcVZMLoWYloCk1heNrSk8xw+Rj22O0FtQ/UFNxCD8QmHTJtsaxIscKKw41SftVk+6wxfJT
g/qmvuy6yAxfmTIw4nEL3CdYfl6QsNwqq8HkuUz/aEIKQKiI6NOeWauuOkbhmzGkSMSiurN2uVQ8
yBX4aPa/3FnMsBMXCoK1WPFyGBXFwcL6mR3+oMPx3budRFM+Xl54zJB9f1H20idJLd/H62+0Q4Hy
OYFjjdSKt7GY4UUKO6bpZIG54QA1Wd9STlPXTyvrj6jnKttcZ9ktx3dYlQmodW1AGSadq0MBGJz8
zO9i1TIQJiJrvxJFml04e8O6MMXLeyFpqUY/UjpWWaWnD/aI+Jwm69qDBdb3C7ruXYmQ6lEWRMZq
KLPokuHWQX46fTAFt1qFY3LxJMc8fGLRDM70mNU7hfBrs77crhqh4L8BS/hL6rjyQIctCLSM+u4h
50l0eMKnosw/eB8S7FQzn/W19Tm8PSPVLyp9IRjwvmBmn0Vuvqfwp5/OzyhuJVgxNMSQYLPLxNoZ
AEnUSl0zhGU7cDMDVhw+6UzvqU0PvkT5Lz7j/Ipa2kd0wYRYGLvi68saJx77ETuJiDT5kz88yElU
Fk1NYiIQYRbWtXtV88MJQka77p8Ikqvz8FEipGSudchA5gp9gplm5nlGDT/YFRuhwrsZYX8LkStk
It42PFLJUREdAJ/w170VDfaFnwz+TKysb+2DvXupZ+geNNl0hxfKg1r/9zrPmVGtWeTkH6Gs1iau
oHTXHTLE68HxPc6fGh9k7Ha9ifZfYf4kZ+CJNa62GvWf72sDC3CUSeBm6AJYDeTFtGlte5enaFh3
wGWPHbUyImN9gdBAMKzdzjcT25i5pfzqKhgryIX9QHDcTJhklWJF2j16flBC8B3oewHBffCjqIJ+
6AhOBg5qz7nmN8OdqWYfdqqVYbV0147yn1NiI2G+DVZQbUQrWeshrjh4ZgWyMQQY4qExsWyB9NVy
YOkMDhRTUgJa7JNDAfd45j6LHZ864sZrJpDRfEdvcTKSDss4PGOsbrIZrLk2Z/IqfwKHZc5gmEzE
5B3gqrPDeVcBgjMxmGxiWOR0x5dw9cUgj1RWbM+N0YqaWtvQIusjp3XPCvwPzrhQBIMai2swwfJx
NZ1TQ23ImyVweqJb+0RDFFzIfOw1LRPAoSIBrscZYqKPDG+zrOyHWOyqH5VbX1k6u1o3CeHd+coQ
C83NpyCBXaT5+6AMw7CMGKIYRWtNqSV9ufhhdvtyjsRj0c2mdVTYemnO2SN5aTovBbcpLL9tPnC2
FuVhxrhgIQb1Nr2AqyjUQHmUhFQ4qbey0+NCQbpvJIsz/qCgvLPPT3+QDyO1q9fO+Tx+Zg/GIisW
xAx+Bb68yLNO8RAXm7ssNieg8t0uxACIodbn5N3UTlzl8Bhb4tmcUslctJNNZBpqQyZ/EpsvdOed
d+cPCary+zMh0vwtySExbbt419uxtt5PIqzNzuuAoYsQ2PAeu45xPPKdCapuKSHPNyeXVAg76E5H
eR3nlpAZATFV9Mg0OX1gi6gLi2HkHMuyA3k6TEKcQvHIfPU0hQNaN7ovZ1VrT3OPwFOrpiQIMDEs
lpTyw5bp0wCUcrq9z5p2ADFfAL1uyMptVflkNc7d8w2Y+f1UeURi1ZbcVEb9pxmXZOkaZYj7oNND
I+AVle3z6eNO33oH5nP3a/Yqkj3Y9GOYNmc0rEIWe597oqqedbpo12UxCqfDx2ncf3ojsSGaCg+N
EBfkCftJhOQrxJV/7O9f/fz2WK3++b6DMVLJVXDID9vkIWJ3ghEM8xP6B6o9PKuZhw4j3hM+9WCA
da2e1WCwBv0E6eQjfQqT4MBls7/1kG78/y7yHvW+d6lAIwLeOwWqQ+rDJbcuIpENW/kRCBCsYTRr
0V7C/OpTHT0wdQBQusKEvJr9v/rhVbWaoWs/gb9ldt2s5Wgd3ZAZye2d86JHxW4XNasq5jZ+VdO8
tdtb8RAdB73T3/9wzSJvQCORhf8Lfc8qnZScUU88WEQVo+MIL91gV/yvJ1TMb597QmX6N2W/eWVM
OFLbGdifl6/BIrL0JSf6WaskL7PgC9L5hMgrC3lFKWu2ayc5lWvN55VegB8d8KDVGeX/3k4yZ6G0
dqJ3eihHU/ThmnBFrXu6eH1wertMY2t3mgP5apaTlm79rX7BdtYo9jIn9buZlRwnUdVZhXcilcti
DzKSURqKtPM2oyp1W88bO4LJkWH6nGb3z/qEQFtIxXnln+vKrwPzUHLIcbXPzTtUNeunYDqyTc5K
BGLwWOEZJdJip9Wn1HgndeeqIesVcWznt89tJhcuuqXXiLP3yld5DocCrROzXixv+P6XRsAcMp1h
ep7MbG1/p9ALVOihsjqNbvA8VrU7dEHvvmXwnlk7QmhniZbDFwV57r1XfteWo86REid8gx0TnLLl
FzaJo6jMsh/9XQDj1cxiYEc53f3dfznQxDyiZnh0bWGRhYFX8+PYj/jNargKSrrT6NQ71ge51OW4
7SauopNwsDJ7ztuJn9kw6Ay+7OXxqT8/d/v6hnOfmQ0oVXFfQnINaT4f/sRpmcIaGOMsOItXEqrT
mQo21v6bgVbIiT0el6pZP6NSvlaULRIlWbty/AdKwy4okAkF5aifOB4ThSS/x3LzY1HBfypaVSrS
9YFePwNi9GvAoy0NOYeMgcGN2tP3SyGy1fSEWFt1lo46R2snXJiErJPCds0EvpzKlNaeHNBtgZFB
X/pd+hT3Udtpyn53/s5EUUmhmF10QjAnHdN0AouyPytJAeqZKUmM3HT/Ew1wTyHyZP9TF+quHvdv
jDny0RhZJW+EMz3gb7KaPL45SutkezmWVPJsAAhgqOAAAj7GbAGszTNa+xEgY/jCTiZfxqj24RlS
8XQr6rRhI3Txx+8q3hJb9Eq9w0o7aM3lRdA86jswza0M3ylWeY0vh9i5EML1ybQSfJ3qXmkBx+O7
UW6zvwkM9+Uidpr8O4ByxBbpO9ITcuCLjJLaa1Henmb4SjNUR1qAyetNSaM1BdRJzOMdFSAaXP1X
zm7tUJDIQbQk+hRN/olm3XrJf9hl6XcV6xUGz6KN/BHs/3ylYfb5KIGUtbXHU3I8GAR5tJQHQnLT
bPTvYVzZMDUmGFNOu7+9j077OuCmu6vj1j4AMSU8ljx/vRDEIDYCWJNxUF3QirD+Fey8V09/TAx+
OqsTaMCm6tCwsyD/HLBaMhvQy/d9DXOoBttR8iagWejzGhdR62CxIX0CI1qRf7NYKkAIRkMOSeYl
knSNV9JeKklMH4PVPU0YkMmxV67wJ7DlCci9Kn1IQo9/vOMBXF1u71FfNWA+KjHjHU0iwwJlLs3t
uL0xcKLiT5Rumw1svjzKZZqoc1/zXwe2q6P4A8tSh8/CAYm3F16n6qxY1SjGqB0wrzypzWRwpXvK
lgcjpSbRNBqlVZ9TbvUBlp0oqsF96AFECOcyDOliuo1w56vgfh+pGx7AW8EHhwdZVDRnjqgA3xQv
xGfaTL9XjT8a8zGIp+wAqVrxvvVW3t5VLy2N2CjC+BLSVr4L5diWZ4wSkbJl3bJC003gHLR297t2
LxATh8MghKWZ/5NMS40fwIOu+5o5snoz2FYN9GHx8JTGCwJvTP/Y3vmhwmQ6aCIoCvmmMYPwaMZS
OKJzNyueyNHanxuH4O8aFDwtgq+sdIYDD/n0+gsjcBeUzImcm+KFkXONYq+/TMCRWVEw9HQzA4/w
xkTJ6d8OOKXSkufovu9tFmrEQqEn8MST90xZvDw7zQxRf7qDm3+u/dLYuRuzp/wPr/jJBUjpLIQa
r6xZY4v49EofyxUsLJBHy69GR4Z/stZ30S8ECckHDyQDuZLBEH+FOQi/lFn2A1kfAvSGFTTk5Iwy
SF3pO9V/YAhdGUAuigK/NEZ8li9epZxmrM85wcHQvXmJh5uHRvt/uJMCkwtE+vtKEm4rqB1L0W+f
z7dOK6DQhlZoUJwL3yvLiLbkgyclAya9z0B/PBEcy+Ydgg17m13Um7wqRRkEIENsCB4U4SJPYUXl
jkHjM6J1fI2dt7K7GXI80PNvdF887e+WM4vJvgp330eJOsuCJD+1M5Vium3QcZZlgET8LFwtme85
Chx6Ilb6Tup1ElEXGqKGKrH+smGCCz9K6yLzYYCytwCUdFsfC+dLak82fsQYJwYFeeGnvuj2mKou
8SjJ/twmvuvhs0twzkCKLu3r2Da9og8nM11NhxIX135CKPOHV5rfWqxifO8eXZtjRnOFFA5/r7U2
kuXHAUjL/S473ugd3ZFonLesxU+vgxploeGDwsIgRkXx3NM8a2ocEXDUDYljb9o4koDA+pon/UsR
rdRDJXTM/u/IaJS4EeOwmge2Ayi6n3TdZj9eRsUAv1MntapDgeIc3pUiByYKWqTsFYqfnOtog5Ey
6RynRX8S9q/RFy9sypeDuuRgwqE0jpyUYz9K9Cz3SCwrSZTF/0j0vIcXPRwnTUUu+9VJAEcg1Qsa
/ZY0U/GrBC1ZDwYpTOoR359TLdZwz5NhvBtvsx3S5XdNRCwr2jbqzfMRkU6PWWr6RBu7H0SV25JV
s8GvaMy6flMYCv0Pe8awInV2Qe8j4fopoRd0mev0TNfYgSoyKYVgfgqFkE4TSDu5NkhiI+G03mSV
8KP6dlC8czqmOMbc/LUckKP6QF0HvnD14176jQsIhcCIIxcqvoAM7Cm5dct+15ylO6Q1viL0BJ6w
vUNFCaW7y9lok8s1TkDicxSI+WZkxmztgz+3tVyaDkbOUV9O7bs3+uKlMZ3cHqQ/Zz56DsJlwI9B
vFnEUDFDIKBClw1jEv6tWdAR0s0xK18pb30VGW/WoJvU5rFR/hy2Q5eYI388ruTR0zKbQ1WLBnAt
OKs2ELtzgCLgQAk0J5FfOX8QRBMbGcOX/9n4pnjlSU0P1KFxe5hTPjAe8NB+uU8q25q7XW1E2mC8
DxEboIkM3HMraGCaIETqtgc7yM2FrgB8pvaqaGpgHCtJXS5gR1W9YUzvsgR6uho+lTni9pva2gek
RX6qe1XpqvhgUiDdCEQ9rPmoy4pswCnqN8Kgxq1ZTKIataYidOTCi0dAeWg9pa8nRH4KtI5qa6Hk
YJMwgZw8xHs+jnaIhkVqhNqLE+OJQvNVEQ2F2UaDm0YUhcKZYFgQV9WLhMYuZzhEH6g30nGPutX5
Pc8daKyQFZQWfTCW/bcTGWgIJ7XFb9lSgVqv4eZglpRgWMo67EF5p9JLcn9klO7poH7X07AHN7DB
iqVpEscO3OVtenaNzgVc/gOveiZsMvlWaR98LUn7nzHih5+a5ciTYU9AfNFXEESrkH3nTM4vKtrr
Bb2icGKkKS6PAI+46dD8OpdHJe0K+3SyqAGaFCNdUX0/uYV7gL1vefaq4A2qTdxP/dFMGw76v7u8
D9Pcjoev3oGOZT5jkzuH/T5kmOQLVeylExRvcL9ZPmdgtzXzPKVuAqr21BwvIDseQwk3GMHGUzax
Vk6/25jXNkgbyWBKLtgtu/cE2gxHUQVQ9nJPvgD86dhpT+YhUFzEFip/5Qrg64L1vBZ0tz0i+caG
6rY4Ji9nCIB7UOefqLiK8qU7K61qA6mqTIRKx0CLg5qV4ZJf1nKQDKgBClZmH/+fs5/bT07gyJXB
PuWLI1U3ICfLhHv3DlZWXREa7eRXs5OPrtsTTXhtCa/lwubJHVFyoEvHYYYySMNxOHI8Ew1EjLE1
BLzL5nhohiX8LWhDzPiDC16QkLRhN3BpVoXC/4kcDqba4LkDXqbtAkK9waaAmzw7YYgprTHzFDxj
hGqN9xFaZtaeQe3LRmXWhGCq0Z8NO+teguicMVEFqD3RA/8nDSW/aR1uy1kj0NHSdBSDVU+DD9RV
U/l6QcnfdgVokhM8+mUIjHbG2NA2w9+eYQr+GsmHwe3qMIcDE79j1+/OD/TWbSDQwTxVBEuPrFwU
8RNhHRohNxLN8XneLYfseZrx95crs5o7omwWaeEtmyRDgPp26TKeTy/9g90jLAKfe85GTDAwZ7Wy
OgCJ/BMWITjJ3kauuKPL2droWzzDLG5sA1x+n0C9adblWGHPjhob1t1XqrXD+Ov/p1JlM3zJmL+l
0k5gz/Y+kUIjxm2SZMdjcEbTxAdRP5ozW0vS2lOmBAEKIN3CG18qKuU5enpnjmlb5HAe7vWWpENd
YCkK4eKF1paXIJb2vDt/mcpXDXB1KTbE/zdpSsSteSe6rbxzvQgZ9Vpi1rKd7P9fStgdwVLWsMmG
stPz9LpxBme1GGd5hrdpA8Fmvzx0GmZFucHoOzNcC1QACtJtvpCdA0c+EZYHwS2e6Qj+UYuouXBl
mhMz3H344FOo7qVxIam01FDrzZodyEAHJs0ryCbD9OSeuG49pdfahy1lKbcqZLwoVEs0hJSYsRHD
tKn6jEkDrS78yIGZYmuiYn1pOoZ/NyAFNmIEeDNDIgMTSlL/VmPDQygayn4m0IG6JPI6qdBaDvbB
A8/9aIgWns0ey1c8J7sV75Wycvz7CG1WgRef8lSiOiwxaQhqZ6TunRXGvfoXIXicsQ0YMLF0pQqg
eEmQD57olUt70TZl0k8FskYkI+sXyQleZ5gr+1OPIPgmG08VUW8y1s3/ZoVGnRTKcLofYHQtKoap
ZHsgOoimx3O0sXtLG7E7LW14CzfqYdBCvKCH+NChgiKjAZHDexfhyJtd19UnxruVqLY7tc5xjzak
0Uii49BsoNZ9TV5ag5EYUx8GbuYQ28AJpIt4p0PXgclQntpL4rKCiaYhN9U7fzw3xH+12M09gc5z
1fdMP2v0jKx9tHvb0g5T5gF3AeEdGnEpPoJLzhEW/OoCKQEbkq6rO1R/5LJjHSbeAak1vaj3BZiV
dCZZTCxk05Cu9fDeg8qIw26M2ZsSJSkspNpmFFXOKjtftjwsNBEherdULdqCikrZ0H9EJeBt6jKv
Dm4D5g2CNPA1R7K/cVssrZ1qm7OBfdWGpOi4tLYKcsoE290p/lKEayoM7MuJ24CSDGVB0dXNdu1c
9fvqqHJ9q+7DNo7B8Z0d6ouyI4fTJdgiBRBkwxs+IMrnBCPvsy3OhBdJhMsrJ6pcJVhj2rCwXn6C
otI8Mjy8M/W9WQKaVCnF/GwQ4Pwggjr+0MzS/+BuTPFwx9OmFd6DSe1UMVMJLHWyqMqh8eQvPgaf
impKMVhsfpgxvjy6MwD21pOlrC+vY+lYkQPdPzEULk0gADOLjOG7Uc0KjJVaCkqjItu9N4iseCn1
GnnHAjszDiNCghOdyswyLCmD+2+LgYJf+DLoBE5FUIqu+/BQus23Dl8cGTrMx0rYTEGhYzcwm8Xw
s0uzfvm86xkscwaf2jp1O2bO+gDY2EoEH3GN0gajqd8RO/JILLWRPLnVtaAXVN56T61m4+hixOiL
jhPsIGNDwLSdBd3sREi8jASxp+4ogolR7GA+l9984OxREdCHYInj7k+xEjoVGvEO3LLOID/KH8MR
AANYiLLCrhiqfTrFXuEnXGHvjZuhCfF0VqSwgQpnAn25zFDSki7CNVxoqxVda/n43g3+D3AmLoaI
78sZ58ihTEuNEVaJtQ8XHv2tJVCEgLwydTIGdsKtivgWOG7cHoXPOco82jpGVrytvBPCLcuKDCxo
/dGMUn5cKXYC7JEkfjSNAts24KP0+USxjQzbgmW5RcCIA3s+I/xoKW8//es/wwBOcDA6oryi5o2u
jZyNCnF9cwduhtAGbS7aJ/CVmfivbzvHhXta/mwvjMNu1iTg+FteeGgyjfIshIAHJ2IbJmlG+2uG
BvM0QOycdyprwp3euBLhaRZKJMHqwEqkBP8gNdGYBbLu0NQ8QAIXtphUVotIMOb8B9MEI+T5TEGK
WzLPpwR6ywcUtQL7eVumarkXYRG7yjgeIBBFYqET/nisAsv+/JOQFs6yX9taCTFi4WBCMAqPxMpx
+xbu7aJ+jsHhYxGVMJMXjRAWuCfp+CmGlDrAIfFFpXwKHdTohCvi1NSjUEJdZZk4do89poq6yKCH
FHG5KlmESA26ucTjTeGBcrOz0ZyWpL3DYrDKKeF/KaNwPEsoKTGUSlAjaZxH+g0LHy0ighDWd7Lg
PTvuWDqacReO+VrBo8zPkzuuJtH2WAQ7KvfNytFcuDE8V7IOBfim1ScgDLqO0l116ercyDvdCHrH
zyFnCOy4WDATSK36E6PbhOfGvbqPrquL51kMTFbjroZ2zlElVT4knduPdb1C/393RvtoYc80z2d/
1kMNs/bCxetwDB8wryGYF1D7TgaMKFjcA1RAm9HrnvPFy+xqsVNUsnbs4X8XP4edyeTASlGxiMtY
zj2Ru8V0U9s9ChIPbxeDjuw3yyoXWlaQCLxXJryO0OJKaIyynoyDKTSbeTvCy57O5UPFHX1bUk++
4UUPm8dVtKJMd8xqkKGO+Aac0DDPb6QwqMkdKHf3FEmG+mU5WloObxOE+sj9yeUB4Zrk1SKj4VFI
IDEGD3Kt4yumPOTaWz2t5gevxcGSMkz/zMLqktDWahQQ9mtbiWHcFtOrHPrN56nCciYYUSefhOvO
Ie/6YHH2ZiKO2XRxp9ZUc2CNUWtUGu0hN60RwBrALECEn1CJQzsZmDl/I8XVQ1nGIIsFaYXyA7gA
MzRSYop6gcnvdm+HOuKeAc1djU2Oj0Y2osYgHNVHCkWMjTQI8gUpctocBFzeL8bU71QXylGqPS8j
ViqrjTPTt7NfKBA8DSzQmyGAv5uFGKB1fTSpaq7TMel9r6pLdWWkU8mFbIYgG3D4mQgjVjYL8W1+
o8abiylmH4LJ+xMe/CP+r3Vx6shzZM4wkc/IUew/gwDv0FnEZwmiBZghkUnRkNjhLf/h0lCepTuj
6cWDenYjrr4jONjXtq3vcRtvQ3K2lCSJrn+AjOdvv2Tfjux2uXgHTz5d0TfP98DlGSc+hxHbRtwJ
ntZH8RzTqQxqnN317rkD6GPDoHJ1+PgI287lOXbd+FRy/JYSaFvCglI8PN50qiNVc8O9tgmpOdv4
PJ9qsxJJcpGf5ciLO5gD87NOoc1KWC8h/mC6PhlhBcH407UQfeEPDcnuZb1Sb6AzGVmx3H+VHBFD
+OusYwCZHJA8VBHQqRYRMo1yXjdaL94X/XT1fCJnnmhZDmf85acNRuN70QzHPjxYozoUFRrLJ/BB
Vx3uA1f07WTyfwLfMGCzQEckIamojSN2WOieYhuKUXbp+x1lw01wQm/nGWejHvu//eb/sWFE8uBI
lACrxXaWgBx1g1bshM6wafvz2XhRHU8vMgwoLdfnxVL2yfKf3Z47LkPyGESA6YMMJrg+7JTYghJF
3HDF4+qE8zRYGlJyOwYJzeNUVqLNyKXiyLiE65kjEiWjPO1W/Q1LTQLl2e5QK1dAKky9XtQxMpo9
iT8WFYdOQ6X8ieEOxKeFSZRPdpDK3Hmnb2mH7OgUktrxVEp8fYRVsl07dnfEz11OccXuZkVfbix+
tn/lbsXbBThkGDPZLW2tCf4m6vnxt/sLM7XqYNtQoe0zCHRVnbB5VoC7h+mFwVqZYEdTvvTh5giU
8XAiPCS46Iqlz4hDHucJt/vC6BmP0CoW+RfsMSlu0EPaEmfUaXfneIqjbp+AOyzkBZiFfiuiSGqs
rYF+qVxcW6Yb223rMaZ6SoQcbVjMgsyG72X69gbvuUZvEAFkO/xDvHCkU2uQJSqdcX75WMUngvSk
yDQqhc4nPaGSCJ3B5T69+SdpPpMDdc5XDskigBTejdGV96sfVW8MeC4YGG005UmT9Gnev2SEtqYN
wQWP/UqgHvnZojbGFSPxovQ6km4RSnu+RRvNdkS4URkoSZ3yzggC6AyXBMJjib6VUJgPW8BaqAyG
UUrbR5y3DIGohVQQk63DxqzaFYKLpogXNZ7bnWCcIxh/eFZiUEbU8LXr34W3vgePMoZ3w3nEbBy4
QciA31K59+Chl0l3nHdwT+e86vI3FNskiHwCdi1Wang2QPueH+FrnikQkjLM1ZW9iHagqfBvhubA
qFHl7bNK1TYrucqgItauZY6n6Q22QYLQ0tH2xkdS9KdmYEmIM0gYxIdjL3TESatn6sYtsiOGPVS6
nHM/RVhap0UF2iC7X/A5+XxxDt0hPpu+iQKcuOQ2tS/lo87IGXg1CzpteLOb38WZrFvJKUtngSj5
8SfQsb1smA6RS3n7x1t7G6WgitWEnnVCcoAEzpc0Kd8RuAeUvrDTrWVkouVfS2NkB1GYEo7bjyQg
p9nP2K3kyDkUK2QL+p4HG4585hpfHFY+mxc213n8/wN/UTeUs8sk+yICNUPKHGRBCuj1FJLw4sN8
PUEVrtdB9FLOhmGq82nXKfqc/EdQTwOV4yJRH52PF4vOM9OWxfYjnjGJr+rxTCuZYswYRjXCm96J
fRXFGhEiU6gL8ugCDREMQC3GIIHTcGsLua+m8cLyYiEPx3vAHpwXqI3/Hg8KPyUjatYn074hoEDJ
FQVJ3mzCpz/ClDY27ZJMJ8HFaOmoMRTTjJtEMNXKJbp4N766DN7dMxszx2dXjOFYhJ7Rq+D6ljdg
9vZ3vd9UbOCajagtluVTLrnJhhbL3ZhaDVL00dPWaIF9e0w1FuQAYZhyNidWkVGlUIJzTEQeA/TF
pZqe58Fsjg2x8kTOL6kJJwq9cssKx45Sw9QXWU8K/VPWkBiobxIRmFZwM6fAZP9OTr+7Mi0GP6Xd
LPeAJQTyaqBEbwcIBB0iRU7XSzso79QVpfRVPo9mv07z6kz+Dj7r36HF89Xvdpoy6zKhux0kYdX4
QKZ59McQlXP7FDRBpHmRtBey/yWPZ4+2d/kumzph4qY0QC57Ga7DPZgrnSZS04yHRftYHEn5R1Ip
tP7hopb98PLUIYsfANvrY+LzUPmoWzUVZtwjZljZiML6fYR/IP6y47lOc6Q2yPeA2ZnmcBc+3dcX
SjvysqvbHOh9GF9Etaw1p/bWEIjUEChsAO8dlBgX7O8DMJYIsMgIevVOlTk/kpYnIKnBeDU8sRRu
EmzJsQddZXFOAS2aTiJ8FZDc/6yzU/psJiOXjr66pC/bER+1Z0z3V2sru1VRZZNcK1wy0xVdmZDN
VpDvSJVw2ZQBzJjahBEQhKONpEbWM7q0ebfbRYrtNwykAPaMrECuEUAa7Kj+vUxZlZeozln6nSte
18UVtQziKfscBghqDO5ww6O6YeP//ZRlMXfDhXCqA0x0BWSOOtRqS1bHa4pqvMoBccGWc9T+O0i3
qjmKQt3Lp4qvuTrNIq8U9mszRuC8AUccUTP2Akowqw3hQ6H8eidAJwQDequFFqjDxdnT87nlz3k8
fHpGGyuZoNjUpXNETEzyeuuBeR0/oLr3t6gtpg7aIpNT/gmeQ/RycyhINLd0ieqTCsK4eQmz3UBn
1AVcSYnEAHVi2QZM+PN9bPCMk0aBfJk7f7F1UQ4GXOF9DJSCbd7WUTE/N+veNJc4mvSaB/980ptX
+IUmoCsIVws6TZ7KAVunzrdzNy3mO0gGLIWxej2zd5yE0TJ3iQrta66iQWCpLlWLUT6ngbmiZ79Z
hafnMr3LbB9FA4znl9QVcKGX03NmQDnBi39YaH2CuNTcYg+oDbbAsT2ytKvSCLASxHcoJ2ZrEMBr
SFX6aSwr49WkByYZ5AHwrGmB5py2j3zpua/fY5iAYNXDVKqVNwpAK5LPqi4acpLISrBdB5TzcxcE
umZ3siN6GUtnkfDyIAqsT6o9FqBhis5NxasK//VBfp/D0qYTW9x7YqeeWKfkOOaZVbgyN6aVSk6d
ywpn5CyleFa6N65gENCADQreGJVVSEgnfOM13A/30pOyCjgghQTjxHLomdrSr1wZOqarhySVgikC
7q5qBTmPNxfcMS2Df14pWbCUYO0Cs0UatEcq8roPOtSrZ55CMO+hziyKCQoTqyQlBHBt+IObpBWr
9Xc5AWYf65nJ2NmPBG43ZxZAoYH016N91zsZejTyS6TzXWJGJLqBmJ4kIyvhyXI+XYAPwDgc4vrp
WXKeudAoTLbJq+7AFzLedeyXstibhFLwnELPwueB9qEBMwTuJ5EwzGndNRbNOsaBBhM6rdG06e0b
rnDo2/U67SJ7j0wywW6y47HmAaDMO0lkJfFFVGYDZGoA3Bo5gq26iU5eFbnpISwfBL25RquiEPGU
afArdu1NJHuAyhCJ3ZAsTC//A+vntKuDyBi4maH7lrRVlCXEdhk/MM8z4jk5+lVrw73zWsLZm12T
yncHLhE2GYC4lfXIdwwJpoS6M67hfp7xMTdVrmLeYKXpBt8/gkRMjb6PCKvtyY0bRo7LeROZNS5u
XpuGv1FAFrfr9PkHaLFMOOVTlW+jzNjAaEZPzy4xZFpAdkpGgOcqFNXV4PcXiEiLU+BoHk3+ZhIB
mbdwV42Vcza/Xcan8pgPU39Xy+gmQkB7GUprqmSCsAuJ7F5Bnn1raz47nvbRd2zsYMgIe+rRDRWq
sharc0CqtNYUy9r1PAvDuWtiwLiJ2jkX98ta5E8rV6aj3gRbbZt5L0BushYooHM12yIhWfUoRpNb
ytIomtx8Env+7XJklQgxDzL5LdmCDUKP2/835YFmUrvwhGUtQICKOANWXvK3mcvEa8z6MIeBqf5c
jdphs0xbJgyzT7kZ1+YKVa8aReabrEKFp7Fkxm7rA3qID0R4XVxWsgnSwwM+Kl2LpPI9HFCY2sZy
46nGpQgN3gXxTghxD2g33mrw/er0Nf6eLWJ7T28jhers0rGw3C2SyOHfWBDATgelc2NDETiix/Uk
gCoVwO5xV72RY65/UGhGUee6YsM36ZzwTwiDymV8TleOtcE2Y7WJy10GJsA1gAdpkHO4L17Gfbvm
/OK0zX79vnoxCkS0KZKR+w6quMssiwFADT5Hd2nnhBY03fHdIm01qjm7vgv2pPxI9E88iDRr8l7s
G+v3+JWMhnPIJTeG4EY/sK8ogUupLueW49kheVtwPz+rtbDU/S3lAbRmc/GfMCEDkU5NVo5L57QY
ggMmcTDYukcYrCfOispZv5oamfWUGvdNmzFKHkbM2QADuhyvyZQpCyQBhPZzdDt5DCbHz/7UO+sq
8UKkIJjysp0eszxze/FJvLZZepZ7pkwDpGsQbiXJzyf2WbKLXHfU+TwKj7VQYiFgyZPgMurnoMod
XccpFhM2b/exDaJer/n1b65bLHC2pqeH1/RAgNxcg4bQf/3mNLZMpEKzQQxFDtI6WZLxLw9dPDoO
lOseDgtlRuizFgeOlYtY3EC+EDoY6hrLl7nzD8NiJPszH1LNrU4Q01da97l0Znx58vhApV3yuaom
/j6qdUGO7Wcu6ZTkVuNWvv/dUL0N6G1rASC25qpgISG+jqbcgvggxE5oVIbzlJmBSr51klFCeOJS
33kq0IJBN/S36MlpFez7OckAdijtenqyvvTzDkcNtD1uZ7NKGC4vNOZnqhTCtEtAgMk5cphuw7NP
MZD6I5nNELav+/iTOCCc5paHHmw2kx0y5WGMKIlWCaTRH5JkmgrwpySWnl7vHXzrAZLRSNC0DLGt
xQjk0CZ81n7eqbDQsTJHv8xNXHJbHMCHcTqyOoh75agsDDNARdUr88lMwzwp6m7RGKYdBY0fHATD
cuHvS5Y+btJCymKLOo3BmCU5ytX+1O+cmSO7kKT6fxRAoM6hMdBlwfBQDVE4xBr97a08YNRLdHbX
8yV0/lEG7cDAoTDIbfTVa6JCw+rM7iD4a1s2xDWaLWjGPPJYeGN9IesiItx32IjZi2+ukIql7PsT
TGMc7WejlpitbnU35G+17hRPQe7SLbR3bHv14idEiMqU9LoEuekCQDv3NEl8/wi02SJT2prhI4Up
J13o8AjIHdslB7zyPS/Ah1FLOqgwKkcJKQ+xdvAqdZp8eOdyePAqaCCcbr0+S4lOJ32tQnhz7nTh
GoYy7hXYT/hZY5DXezY5b2x2Zaww2PaTH2UMEMm/hQapVcXyPvjikfirwTKmVcvJHH98lcOav0xe
i1Q3FuBOyX+tJc3dBJVlP6qgR7/IjGkAOquczgVEtPVy6yiia/EFVx1kjL2qr15AluJxuVG832xe
16v+WD/TumRuiE+nvLtn9SuYCsEM1dqVKLfVxdnggChc5jNlwstumT3gfvfzblSOMOcpDbkHh1o8
t9oxfs+ZqmoLTCDXxX9l5ZAqMlYeZKGTA9e9ARdsr5GmC01/d2yapW6JFvoPqOBjyzy39YuRvPVv
LaHGwyp8uVOHBPNxvkpiNJYcai6jBqIuQBImg3f2Tma0EE+eIvIo+nGUpCdzi0UrulDTQJYdq/rj
M8iOKPheNQ0fgKF1IspSJ3qLcowm0ICJdcCPqx3Lby8Xdiizo2IlbdYHlNJBSCgRgn0Dx/0uTv+f
4fUKLsk7f85ijIu7ayuf0VDb7nDU+NAieod6XqbvOx+j2ELqjYspoLZCr0wNVZJOHLcMr727US6v
YlvANBygsoFFQ9kYMX2JNeV9DpioAkpL1NaKZQ1WTM9xNr8hXPua2SmbPcmB7fn19u28+UYHFNov
hVLtMgFv1Te1Z0uuzLqDbppIfXdzJsndtT8FIRHPVFnhoOPnKdjnCb6eMEwqqLWeF/CQpf3dyt/i
eM6wHysFlXi8hEniJ6XDrDsD16LHIlvJK0F5l/cCJJyekIkDoJybioL7q2dzcLByp8Xed8ne6BM6
3PvlEHzsbd/wy3xXQ8RtMxgS8vXJmXVT6fn/RYqoEZNfZ7+Qp5qq0aq0gxyLNpKjPzOHNrbt30Z8
KPy+equqxKXJGM2CDKiCQg69IqCTu3ioRLTiD62Ei2/IWLO6ZkncN58wrdyknlKMb3iNdCYd+1OL
IwxZkyJ22lfXXlfraPx3y95BG+TQg7DdrzNgDq8L8bObtowxuavO9G0sfG+z975fOFW/nmabcDdA
Z3dhGjgdRIaxN/NVAB4H22F1PGdjHE4sfRG33S6wu5rZv4x8Au9f0eTCR+saS5xSMf6egA+nPmdK
208yAdxv1iOPF7IAl0vPT+uKXFdtuVNsjJDHkSUq9V+s5aZ/CH/J6y0zv/+2spSIT0gQI81xRINS
yDg76tobCElzam0j7GBkvPmSmtDfhI1qYd6aiftk2wjX9aTSq4BCglu1J3zyxg6HpP1d0yWazDic
5ez7WaiZ8gDQIEYTSekF0ZreQQt+x+TmNQNz6cnsV+29k/HauKDDUCmXRZbThWXYORiE89jc/+Jj
mR7HI9MO7tKu9b0WcALhKVBVxXhYYakHQNxIHbJCjvmpG8gg/gEk1ChFMANt43EvjWVdPtt64hkW
Zo2vd3FzGkprOvnuVosw75qYkohUrbpSXWNN0nFtRaptP+VYghezWB2VpU6i17PfVgULrKuLdi7N
mqlOeR/dh0F5EH6m4lbGcEz0f27L4muL33TxH28Inud8wIAfhYUAnQd6IDDc6pUlsxYeEWbNAOB7
MtHWIftPXse0exzU+IRPeTD1tpVPMtpyxxivMM2cf4A1ezJZmWenneKKDLnHiVVNZSm+iVkJuWyo
jpPEkLGgzof9bUPPgpQWrxpuRDvw+I9pr120wz7PCK2/Iw9Hq78JAPfX+PQI1k/Z895tVP4sahUp
CN93LRuETiOR4zOvdciIzsNX17jskggVWQelfln2nO1Cx6TXVXFkEtkHNlX5DHmEZ04RXwGQ+80C
nBh5LK5UR09N73NuDsMraie7DaQJgk4u/oRBJemfbOsrVT4b5qzGrWGS7Ug4uxOtCHPZiaFkFFnV
V5nimnu5q1stRz/wmE6qUuV6CKaYFGhZG9zqNf7zWNCJCECAfIh5YqHyx5cfIe6jQ4I5byuuHP7d
uYeiVXNX6JhHdwt8lVJK7UN5cDEbNZ6uR42YZtgAldxTsXtD2fzD7/9JXeIdZz/YEbdo420OD9EF
AJ1x1kh56OY7QCRpFTSUorudegTTRHWddaO1pu0QcpuKRRgqF6z0fLSL6342XXkWZ/U7oqc1DTDF
5+OncK38IP5PPfu4KmTInIEWChEwLowcPXc4HHzLSFhKNw2e+sFNaiTyF6yU32GSNMnR07NbY5rR
zRZ6YYzQfDaPhHfT8hSAPSptQ8wiHLvFIIDr00O6pPFn7Fq2pAxqtMe8NmP/h/azoNboIG4HdFUH
XgcdANebPKnbSbh2JSK9cFyrwE3J7IkSQ9ZZpFI9dJm5pLa+cpIRKmWRCX0EpxL5GI1HuhUB9aDK
CRoev4oNeXKboRoXc9GKj8cyF+dUm7cDkOpOlqere03h7bnusprHV2RBMVIVir8CjviddFsMGxoD
7kuIFTH2/3QbO/alFre936BEWDXNgGdZcRkphTbSYuf8FcNXM9H8MADLjUHNP8rJ6VkcRgvScxVj
Y5A+iEi4M2PR0cxoNKXbgaAL89F+o1tkT2t5daWgYdPw+bquH12f5dRxpQ/aOYAW9SCq2rdob30e
0g1o8OWoAf1KB7rfy6rK+I4fnkZN4rO+XW5yc1h4qlV2iUFtSKxsNIl1WhcSGC3SBtc/clOUYPa1
HluwYOnn6LwanRo4vEEBB7F9pAGTe+UxvKeLy58LzJjCIEZq0PSUxoW/prPbf7bJa/7Mpj7zQBZT
ytRrkzhHtJU7UBBgCaotuiopU65sXtV0LH8mBWUVX8/2djdroxMuV3PSxhEAR8wH/tDQmmooWKTr
2bJQYjF2jstYftoA+lr4HuhGOngokwZDJCLUD0+Zq44oCHPpUvdXx+VhN5+WkbjfUn499XlkUX5n
3okTRS/COXlTON6Nfjnr8hYQFCZNzqVWeRPyHnYQX+Sx7/UzgrHvaRQWP2QJv3V8vcyX1Uny319w
ka++p/RWO/2X8Zrpe9ldYoE/z8a1dTqUUjIA54Yjn8/Xb0Cgf0PV2bQWomJUZpwPmEQCF1ARhi5m
G2qDAN01AbcfXQfXR8TVL2TfRIrWyfNluxapkyewAqVd+yVyPu78E9XSSzGRTWGGGp+isp7U0H5q
OeUaHbyiQ/5bOBuupHEe8Z3NuKuZk1q31RzRY6fG5Tv7pITTbLdrjVcD+ISrVqvPDWTqSOU8S0tL
MFQwqiqa4BkHuw+loV65i8EZa29eanf7bHgIMIj5qEdoPJEmgZu/AHkfwHeh5PAw4d2Z2OVXbujL
6SUjumeZYQBWFLEMDcbNp4L+egdk+HRsrXO8PBu/LsKgtXQn3aLNG8l4vU3K+PTgsRUwr+VQb1UO
pCScL19REcd1YBaIWo+MdR6GBQYh0mkS/+tPlW/l5kfMtSAUSMHA85zpILeysQ//EPq4eZGe6Xy+
fF395yV8DLQPqjgcUxhrq4NPMDB02LuPfiktWAvDJzp2oVyP3UKfKg2+ohGxbPeNrLQIsWAnRs4A
Vj/27It5lEx8HBh8g2pZ/AegyC022FYD2a0SHFezQgbKbaCGIyy1ztN1cV1hx0iqJhcH5uXeVHBF
jObI1lh9wA6eaud3CO1RDjLirt0fvU+l97E/gmWVeis6uP6aFWJ7YIfz6YBr27XE0tSTDzVkTdlA
84eeNTlj9RW7wI8/mxoayY109br95KZ5RnUHmyjrJOZq00+HJsOMgF79z0VypsXHU500iX7Pgcn4
orkBYfw7u9to/aGCifW2TJM1fgO97/Qiw/50+KV580dV7oUUT5Yr4fYg/7fOLUELG3tQe7mkhqM2
QQEpFGY9Sx/h9njyGUxAxx/EUfooBkSBDkoSTkKMiX9CqEcr0MSPatES2v/nRhVCm+fbcwDmrcqD
+/1RqynYIlbrN0F2Ip4EPXelqjqZqcHYqEHs385u1bbh+BZbyxkcRLGhvlvDPLJhMLze983+sVMO
9+Qz08KbWJYci0d3LCHodjQBV7ITOcKNT3u8x/2EoBeqShso0E4i/hzuqeW0P2Vc+TPLe3gXjKQT
N9wamLciNeurMR4QXKStxuiM0maLs2BGmTLetU9Os0sT7l3k7zIyZDUEc1a5vw2u9DCcUUyfhADO
pphOuEnLhX5c737qyJtr4jxq05gi161KBqgY82k2lVa3VKKKmrHb52xLNAVpw95xYxkZSvAC/ZyT
Yv+CbRv+kLC/vB1TIm0YkK9QQp6hlX9HFbzRSChnStm7MM8X/J7cWfG/l3ZhN1PdrT+IOJOtIcPN
PZuAzy4/k27UclTxRMKHDPMRytsQOBIHn2qooHGJokjLpIIFvL2/g8AZ/HZu5lOTQZ+VZ2/twc8/
zDhAJ/q71XK39gIon9RYDJLbBpJTj4za0tWlmcJHLVrcsvMipWHlG9TB+sc1YNKEmC/QdteatKtl
0dDAktmY0Di78trRCWLrIW23nHYckX1FCoy4oxvgH7Kc7vCBVSemN6VWYWQc8HPX155aSbHwymnr
gr+35mqqkVI9VA/qUoz1RjncMzGmewSC9hM9LVdpff5c6EfTix3zM3rK5jDeNb8/WljeMmzchYK7
J3JLUwwSgmDvyZ2P7MvnO1XAcNU19G1CNjnmeUEReBWyg1czoBY0cSdtQoMxElAURfpxqRywwTb9
IvF9nanEReHiTwZDReQbSXwGhHbWdWJV0yrGTQzGeeTyI4sWcJ+OO3k8jg3ZmQy3mcZDt1DOhlqM
J3XucUmouwK1ENok5C7cW6/IAtLXEZl+fuxi41cJk0UUn1bXc6an5ivuX/OnXHmKob/meR1SQ7bb
H6sYRW9bd+wAdDJx1npAC4x+GmNAE4o8Cp8quX87RbhG/tfPCEZubfp7XSes0lWwEMDrVFdBcJUb
8oaX4b2F7greidaLvQe3di64wqjffaWlQSm/nOmDKcFUQJLJpudcxhFo0fEsfqDsu/Hevw895ZeR
PL/5Vn7b1qw3HQoOcH86+5WWFvKnNUUGfJpjExKaWkvuhFZeYG1rQYnpFTEPRgsPrLWnbLabOd0W
TALTsC0rxe1QWWgX9yb+nyD+aqAsCUA8lftkRjKVfY2BH61qrTwhn66ziw3E3julamQ30ZZJlUEu
F0EvVW21pEzp/6nnaMXvagsxoQFv9aUCTac9RYws1Wucu+GS0dHRgLV9PCcRKP8xvVL8VxNyVyB6
THa/5Nas5lgQ6SN0dmO0qEesEd+1Om+QjubyTEcafNOO0VkgsGq28BDmNzmIXOrw196lsiy9rQ62
lSvdFB3WhkYkO/jZvKccADJ41t+/3NJcrGWZR83TM3sUfDOisVAVvpSkJ8aK40KTLzLvxuCEl0PW
/FDL//b1lSOuzdCyrsY3QwQxzxKGtDn5pIwl6u+9xibBgIV+V0F9QhBnX7+ds63Opm7+xvwR8H30
M1w/avGhUO//ZoQHL6+fEjy75injRn75/WR4GL5lCeWORPWl1f4lvuIGURH5ayQ368L+DK6iSH5s
u5cdz2a/WbniJL3ar64SESVLI5lPuXh6cZRcde2/dIivYIkhSIBJyFbF3KT1lsIZh9L8sTIQf+TX
tI3olrSLmhzGvzCwS/qMEgBJ9vMmV2WYGDEnE8dIpAS8T/AawPepVdhQbiDcswzWb304kFW2Zxae
OT73itSCbiTJJFSz2/19QyWO75mEdKnQC+0DItLD/o6DWl+BsnDqpQAVZgjSyjPQTaAo6xrwrPFQ
i5q8wMdQ8xTP0fkZg4qesLu5qUG/AXLL7AX/vkp+LVjdG6IGRnI66uG6XejgegTAHIw3KP6b897x
pEhEUQxFhBWxLnxZTzc+rhUb1uZP+B6keyuFgAm8Za7RPo3+jRU+MFiWPpZhIwEvzsHJm+yEmvBV
dr6gwPA4KmZVBGrdxh8MU26uh58IJq8u61wORJ75WMDWC1FBkerjh8K3czTyw/l2LlvUkjQozJ83
oYVDvHkD4WQsRFMV4xRKIZBGlp4Z7ZA+1w4N+Hlz3Uk5DcE+vP9ZQQ+vs36/iFeI0fTY+YTHe3MJ
pgKLxPsH5p5H4YQoeQyJwYzJwmVxcIeMLqNnYESWEyKHJ9ENyNSX2U3/I00oPBFrsqktTjYmid0v
fuhDpXcZT6pymappXz22AwP66V6e/anI/YHfJFPTldVoTSdUYnJogiCut+qEpWyRv4l/4zTfkwLe
8SOgnViAtf48VZhSMpMd78UwjMS5rOHmP0BtHumq9y85+6JLCyrJJ/ACZLdNMeU7G9+1wxumruB3
2cuE5++QOxvHw9JtK0inPd/glCEjCWl+CTv0Vv+DdJg7Pj5ayK2CBbf8GLXQaw7+a7n6SAY7pEZR
Kck9NfQFU7KKolxBEP6FkoSsSCKOdCqWwRk1niy9KzJIKCoKyepg0fmL99QhKa5eyfx8HvrwFF5v
Nd6E+7B5pp1dUaQq3huKKSoYIGqnJtaRRFtoMkcCaSQlyi/8CJHX6+rwRHU8Gdv2ZEIO3FqboR4H
ddK+aK2Ovdb8MOidZuugEIdz96wctds+LjO6NTyD9jG8SqKjdv/0Xe9ePlSfTMPJ0jDkwoyM+LdY
1bIZL2unuG7dXhjl08oSWaDWikfwx/MH2yA1IISkUVM020nJ0CUV7dskoeN8FrPiLQpV0ncCDsr+
76H9MzetF+e/fkgn6Z6HqIF7bXQE3RL6YA9w5itr+0QjQljDOQ0O0ykW2p0wfCA4vfQe6yJbIhh2
ZiUV2X+jOe88KX0A6p8dAyZsgc8c2Gv6a+G0MX1GgXMietGG+lSw/O/I2JpL4hws8EVs/MZCw6AB
qFtsCXpgbE9UWaOzbStXc4vReodTpDxxe/Y1mQcXx7III7f57EeqDO0O9P+loeeZU2egbVqGZsRm
hgjkXudFno4Yntb/BzueYnqWXd0Ov39ThouZ55aEwsQpef4/VtcfsoBZDoG9HXw4+5j0B7MvQaqJ
OMjewLwPg0FFYYry0DtzAWqiYFhc2473e0nSz0PpMNqmL+DtSURlBi5SmM7wMEb4htLa0AwHTNAM
WBnNEKyyqvWQIh0sdM0ImsKZ6YPHb35TnvVS1LRdj42LbTvlm8AHUFyD+m6M+hrDW37b52t2jf28
n4v05Y9NlH2kaELaqsjxrAyqEqXDNNv4mhtBVq3ZjchTafbEXgjuGkmyFftYZ/ei4pBELRSIrhtR
NOWxWwDbBpZttxBQwtl3XFlsUrTLweQDrrB+6KcoJyM2PI7WGMaPWgLRqRcMw3Jz2sHJEUoxxVw9
MqzaLuJM7mL46WBX6lHmd7Vi2CmaRpVRk/8a5z0clqVOyGYz7/E1u7ayVMqDeodAMkqkLGbOjhbD
S+nk4O00Uk+BE8T9PInP6lsnKxBX5UHImCuM0F0t0A+C+95pd5LkVfWAuQH/JjkMGYxgk51PcvjU
22e5+Vei1T+aydFZECG9zQMSYFPo9WbRpIbJbl5zdzkIEVdQXypgLJ3C4omcxqsZbuEzO/NQZQp2
HsS7rIFhmCVfGVYMIrdlWeM62dUqvZ0jHNALkIw2xnMNPns0Pmq6rcmiztUAkyGvAwfzjtpKGBDc
MMC1b0k/RGz9EzDFsbzsQkb765lPiZ0cCzW+I4cG5nl4JCZOO48+V7StZ8R3T+VyV5dJketw9RQu
+ZnffM8Jm728PWbVf7jWCilcVfM3Ho2tVP93wboJ+Tg6yafejRM54VA3S/L3guoNJMXiIwefNG12
dSKO/euZoiMDXjQ6xsWS1cVTdZAVewt1+ngRlrayE4VMXu634XS/exFGat9nJyVsMmXrzrtzA7Sl
mWFOV1sbiclzINqes98pIDMUqly1IDCGgR1nvcpIs6pyWTdYeD7A6SE9HHc2vNllznnugnSb+Xom
iY2uwBnsCMizfgsuiUTEr7xtHjcz4SYvUc4QWkHJ9DIv87btj8XZ/S6oi49IZEG/Q7JFDLrfuueS
A6u2tgAvcnlHmkBfMzWoosILZNtQ3+zABKdXBf08DZxUgQ9qPlBJxZFLeN97S328ZzNBf5+B3lvz
AxdCzYOhSC5dfgSYZGc8SZjuDEv0FBD9eAhTcDSyFZbgNAf0qWaGjSpvwQTHgja2fdBkDblYVsQY
9GdUQyMb/W5HqlhfHO3QVrZRihuRs1evJ7sN1inGbibr/ukqikwh0JBCWlYlD88RdQVAGTyxYXJE
dCcLXp6DWi5k/qnB9aCWZP2WazHHYB52OCofE5HVMDlb3hnMEQP+TWU/s5CLKan2pGwZVDtlSdya
l4zWAY9Dzsit+056YIIDYnC2U+S/bP2huLjZv0hBmnHq1H0MX38MPoOMp4TcjYG0WH+hwpp1n9TA
iex/qgaD8YxTcs2CLs4YeNhaUIAEOyTqH0KOSGmorQdz86kzw+IrF1FVeGrVtgAjqI7ySr+msvWP
VCjT7pa9rB/GRdhps+s19Qi/FcZ7QnAosESdVepU9oVPG8Ravsxy+7JKfpj8Eogmx5/JPQzI2N4g
e+dheo5zxJ5wvloh5wMavnMmZLabIValNY6WxLuZjavl++alSUK0Agus5K47/BdmPujyG8GGyuRV
kofcWyVp3+1fvVc47oXaY0jEJtkS6OHkPusYSXAgi/LOq66xBbPnaFkJ+vSpkPcZflAAOiILVOOf
kv/LZHTrOS6t3KquIR6Nr7NRUTq/nG7iNiw9OHF2/KkYV1QT0uv6fI8Mwt6igsdq7AltSjEkPVfD
VIFgnCOhl78As3AXIRfZA/Jt4b53QMR797XF6U3SCOzjDpbZCxVU3om5beZRFjZ1rZA4yV0wPYRh
MYLKmMd9LGp2Av0VDPXWBgZZCPcHc9FDMYcmY0sxUu0YwEwN7XvIYA15hz+K5PGsfUPrDACKNZf7
XUAFLiTuc3dIsMTx0r2pvdZMlAZI4BzLf3jSvSYul/sxVGUB4wLBfVrIF0Slni2m48OmXCMGJKGK
BEwLwEGx8AqvpEZ07vT5Z9Pr5n2pWUPB7i5aoFVFkG9QJ5Fg0pHnmLgHiIMFhWCerGZX1OGoY2bt
eh5jgdVKxgi7Kpo9q7onMTRJ8jK3zfnndQ+hUnOckjnAGV+rS1rxQc2qEofxaxMEkrDOsjezb9Qu
SY0dZs02SppDVf6Iu3JfkSOglnM7xqPwRVeFbzEoQgrS1p3v+4eq9DtWJe+d5wh70vER8BK/CvEv
pyy/3rA7pW78zHLtMY9kBapdI+QhiwuLQElWkzYwr0Qew/xDX3RFYjy3x/jAWetbrUkG1mKD3TqO
rx7BTuu9h/2DHbNQozMO44Ek+pSdfGKg2OpUQ5Wb3Kqv0QSdmL8YfpLZxowY0mrh3MGLCDiTON+u
FKEhJtM7c3GnpTyHop5IuP67XHfX5j/6Z/zcaNnPPloDlGvmNYIeYTQkKyz3aNlv3jvWqsFgNI32
nugGYRuDCy4r7GeFUftKlmrOowWZEvD79j71swwTVeJmMyQ/YQE2CfluOdshUhFPILFPYTG4rfQV
LlV2+XWqSGau+WGz9a65qFC0ALnL1fSyusVdss6HGJTgolpyMVMdcf9pjwCiUJazGQFvV2eYAQ6J
PgaWLP3USWZ1RI68qLbGODszXTghsw+chn6yPhVSeOlKV+LMuM3z8Z7OBZU0npNM599od7+FeDie
fxRVEo/GiKhFkiToDI0JiVbzy/XA8e3dZW1KjtQTVgwjbR9yq7DSKqNlZPqY/BEEWHSO4Mt+ScYi
R3C66qqrJuiHPpiUGS3tWM3NuOw8kBLsvGksm0WG6ZgRvPzvIvqYvQt6SEjugeWjWXd7wQqxlspj
kVzlse+2f+xONtZEOU4+IOKEq66xOD4iimvlZkpQqnv8LWdXBPkcc31oQNH5Vga7+ll9bxaL18ZF
8qppo+BaybUiaPifQ7OgfFLd/FBGPbXg3040sHkTBPpXURSPR9Tw4FhUtOjs3XHEU3cjnngUALHi
YUdcKz1n0+zcf+V7zLP5qjxohEGRJpxcWeGDsRQyR+Jecvs/RJC+tWJnXQQQZHUzYyhLCn5nBxb6
2PpGQ6+BSWtWOunObG5sBfb8t6RVmmw+3s1ZzWdVm4+Yo0DwKqQtUYG15X/jMo6Rdos5ZZZ5qRSQ
d/XnHgJIgfjnNnX3OBWhJcXi2Y+ylE1jNXa1xRdKW3PxHQus3wwqhVZoZxwxcpTxwiNH69P2GL6l
Hf9DEB3JJ8DweYDLpKFIGg37TkWMZFgrrBTCBaLnOK+zeoYdBNucj3PbQkxhJY017VY7TWi5U8sk
oy47Oflhu/JIM1lCe6mihuNqfVlBSNmMYM56a6sTM6KZYjz3z/yKNV74ja4SYXcxEVJ7AQtMqcHm
7a+IkPWUQMdNp5ktRHnIB6cc4Vv2J7J2Dui0gGF1IOkZKW1S6/GT/2IINOV9XIQvYmMcXwN2rXUS
KzFO8MTjank2MBJM2IvhBFqCJ18Q2AlLZHudddPfXzRd6XCeDk4Bm8DlE/jYBcQDmLWYn8N/y6DD
ECT00Pp6Kn8NPXOYvCYFCGX9eRkyfw07T/q+TGF5cDqCsWmxXDer9WeS7oRFMIIWSitunLbBnLd9
sG1FAcI8YY7GhTST/ZQ+ZrwGRmrPklNdY9kpVsA0rh4aypwHye0epSKqP/Fw9GUYPWWojpHvaK3/
qISpD+jjBhbwMSqoBP3Ijq0qG1AATnBnKZSnkrnMLkjpiGarG7slj18FsAV0vdS9Wz0VMtqwPzu5
hx5syoiG2CWMUGopizL+glpp1D5Kp2ywUr51d+V81bT5T0VPl9XNQy5J4S78aU0IQws1QNOx2DJL
ghuJ0nh1vhmNFUUwWtGT8KA6rZSYR2VZB2WHvYpdsTJkADVQuLjRI0UvNJNdM1rb8Sdcnluu7eiV
ScZvEnv/HDpWwT70LbGEAVgxpbB+WHd7EJvYLzJ2c6FvSxhSPWj2Pd6Rx8LF4NV0ACBDjFtOVJBZ
FBFz/eWSwG4QYdy0neoTsUERlc0nGxaogI83ylGW7JHzDlXq+jgEIZxF3AfDNBmEFFeTYRBZeNP7
yYHPe1g9+oey7CmgyJQ1b8FczQLjbfYE9pJllR6o29CYkznKGJITWyTVH1MejNR/k847KcbHo+EK
VreI5OV67g/wHRFR/2QO6cdrvdIzwH7HT3UN3ck5VwnPdKxTzTi5xFAwmwDgUr2GQ8KqM5k7f42Q
SDyxtJBbx//35osZEVDlGDSsypRgH/Kg0SJskkOi+dlmSIHYYbwdcEnFNBGfUuYyX3WEhQwnUIw5
Ss8uDm95fJePqaGyK25nP4k19FZhwVMiqEeQhyfxMsS9JHk0JEm6sMBgVOBWSpW9hoFD0KQDXMBM
ovToeHSdOfJltpPQtm8kKR7RrsLA6bOxMzonKj7wFwfxylnmJBFMqd36Joo8AVezQeaS4hs6g1d0
9xMe9OZ6IqQbDHlNbvKil6cS55P+MxUlcNl1OnOprOzyMkyxr6o6UY8cVe6wyieFWTWnU4ddgwGx
ITKQ8Eh3PD/rrQJVFnLkfk4/UTGrUf0EDiMruMlMV6XuCI8NJeIU7fS5bIsxPSzKjkJ2nez4igHc
QYPEmCXJZmO0aumo6nXalQhKL3J5frfkphWFDUGjzt0Mkd6xkh1P+dKg3Jwz0G5jI9M7SCE25pSD
sd/cYcTEqK2fE+KvpT0bfTkkEoCFUBccvTojEsyUS4R76GCU3bvqugwVb1mrPfIR8SYJZU7ugeTc
FmHzaFUEu4Kr9R8RJOezgGCRRyo6VT+WxpqtPJRtSHVgXjcfSYVxOeIVxEdJBqSuwnDgXqZmmvqu
ZwehLgl4TSvygKgfPOnw8GFY2gTR3v/F4k0arXfSGO0rLAtD2E+e2vDAOt8hdCF65pTiwMrOVmfO
G/uIN4Bh2OOj0DBKgRzpRES2WyfPs0YOVGSYCDj0FdXRoGxbzSkxscWvUlsOhowdlmJ0iUh9FbY3
r6Lab0qwlpUAXlj4a6nDcMz6yoMsHfAMXn1ztm3qaYJXtviOYTAcXKRYh4SZ082wHdHb8D9bhlUO
PwEPf9WG6KAtfe4TA2/CvsRyKRoY8GrbOEagEbWFIw8XSYRJEx91I5Xf/F2Xxsa9gS26pOCepBSp
3Op3MpDbSE6AOSrbQ9SZpmTa6A2vfm5K6/thdKkspAxTAC314Zn6N20W9mjxWRPTu5YXAaJLiumt
5kmTYijFo4PhqzAaWX/kJa+CpQvTvR4wxM8ZbWa1wYQdd+zrPiJvyW6lR0PxbU6rPM3hvgeOlLbh
ifV087TWZ0WWR9ohUGVh/+4nIeahJZnQ6wkBZeEqZAtMke7lUbQpiY4cj/kOIK1kooEK+ZLAKwax
ouAN1HXLNn28TJZyh5awoVbwdHL6LD5xc0MQyrEBT7Y6IDBl0ADNlLcmCkGHgf5G+l0kBS4yw/7l
d2RWwlwt5IYSeORXRHlmjq8ubTnG/5l5egusbATbfJ4j9OXSQ7BEHdzw1fJ4YNU+nvHPB1Lj8VfX
hptzJxfk2J2owzDZhCn/PnGVX6vaRZYRtorAnVaM9xaIhe+HoYt/LLgLxuYfKxDqeAyULxfGgFP+
5MjJKvafKpZgSwbREGvyzsZguuYb4KD8rgJr2SkeRn9o+WVc5Tw/r1/jOre31i1zuKrWr/tZQ+M8
4rnE5BQExaM7ZY3JbQpGDADq5aSju6W6pOwWq0wOnb0KZun4SmNi6LYoZO1rnt1i3wguWef7XJpi
35xEu8j3iprqeGT+4mRzhedajBUW7ff3odR7hIbcA7nCtOwcmfnkkJw/mVjVSCLk55z8TyEKIfjR
Ix9L4ralHXVabTN5KSzwirXhLjJoESH3PzdWX+xF8Ojb7e3xDB1rAqanQQb9Hd5e9TVnalAJtnI9
z7hlEDB0fuKruoHIsyw6vv/WCXmnlxGZf8tV69eENIrwqzxXqPoKSLUftseNVUhcdZE6hYYS2SWF
w6iNp8FNX17U/HgtZfC7RgLh0hmNxrH/HPT+ZWtjCCt93f4FRaMLFLPWcHKN6UOQVp+8pFVC9vYA
L0ec1WrZsfQXlGkt6AELWHgaDslcj8+hJV82JGYerk7inf90Fxz2zkgxBIwyeJlGDDC1ogs4W8V4
S308sOGDD0azbRz11jVjbnFcZ7104OJ6qgC8WzB/B75GPbgs3Og1aclyPql+L8BwWi7XsDO4Pyft
tbQys/IAZ28S1+bOkQ7z2LJGc8W6SXJHlnp2YtdgAhB7Xrfoj8ch00YhChK9mouyboLiIDQxKMca
QEQl9+xomCwho6GsxumMbzbzzCJRyW7K2Z2/fVgIaKxAxjBJNPXTGMaW/hOOIeckHbOZSUo/CLbj
XfK4uNbUlHgQRk2/+pIR7tkCVQKfyMjuegI4Na/yZXz/wBRu+3o3bdAyqNTajI0WD8OZrvk+hYSx
qMWX2LWW3qgyU5PeM7YogO7RDm/MsEzDbQVfpsY6s5HlR9eDbxCJH85YRJ1qt37IUWchfjgTC1Fd
Gewk4acx1bGSMyyvlAkA5tpaTjOuw/ai7Xw1AlF5roGSyMiBHdhT/ZKLjVwlkzN8PjMj6SNaArr/
IDxjOu3+PAYax/6sg7nFLYD82DpwiaEeJApcYho/9fxU6U5rX0cMTA2IK/5tNmuEK2p8FO2SQ0hk
nlXdOlrvdj0INmrSoI+9mjG4EmO3MgOP7ZOXkiYVq1x7tTSnX8CWG+E4YNgwngcqGqLCUaXfjWrW
mx2Ow0mhzm2fTfaXW25cfCa0HDtpgH80lcdrBUzFSsnFrK/OYlVetxGhQQCK0N915ycAXR7h5MD1
Fmyq9Ag+pC1fsHsK6J+bq3C0Taa0dQ/nMbDTR53aIBp4FqkReZjj42C+54LbOAr9UHTGebIAs6Ay
uFTiWj5fGkwc6jmxIF5Dzk9b6elg7uObhm0wqR6Mp6b5rS7GHAyaGyyhhY3Ospjj+65LM5MqaOVl
+BlEjrw2RwniZYZ11f/31BKxlfQIO4W2HQh7b7SMjn40bKsj9UHiSKC8NG2+43cbdgVcOxrC2cmK
lWiHNjKm42gQetvuvWaGmILKhhXV2siS1SRo3gfO05wABdVvunnCSf3HuKP2pR0CT6LC7uOVilPv
DoZPU0+iv3OJti8A60mg3CaCc7gHHaQHu4c8IsmwWOtkUBnWC9usCsRoovBa02fAoFMU9KmZIlvw
eJ+0qAV23F1LjT6KAvJ/w4unNJ4sPZQBlq/MYj3VdathOnqpRpGl2C4E0VKekD3FvweLCgtwpChI
qGP/778USZUPZUPsfRHblms9zne7Dl8pvbwGIVXhwNHpIl5ZwM8/Q6SdbiU20OcYyjvm2vKdtZk5
G2qobHjr7YEhbySnNoR6mbZl8aWK1to5q4J7tLhoogC0lB5kLKQRuSMJbQOx6Akg/LWvWLa/PiTt
WUQuGqppYzfk5j31HeQKqn/iE6d4TJBt8Djpf1lfUS4fVrM01ZQJTzG6BRjW84o6b81dlaUbJqfo
NgsYhZ9V1iYcBfuSVtl1S9qDqobPb8DE53Miz5oDbOr6C4aO7d+25heJdl7pqoDeQoXEnevDupZf
0JDT0cfrv7AwAeamtMp8pSXZsV/BaeVLGfGdAYl082DwQ8SzQJXf9fGvxXGOCuOXA5I6tlIjPOZu
ZBOTbf+lAIVEpuIPQQBlC39QB5Ik9QqKUIR/nKO9c6wgaO8HVzUcDTNm7qXx+qXBaE/yrc5hSx1p
l2yVnGhAOjDCHHDrnP452MV1NC9TvnM8C3XVHLIWYmnS3dNlXRmHor/CrjmEir5UE6pQD4YLCJ1Y
fi+ADyAnpe8T+FzS6jlkXPa4f70vtalDeqplbMN6xKKmVax8HjSpHsgnbbQdMVGTmijisN8KBoC9
Xe6CkDfv3XCZ078n6iIj53LiTjJOiOPwskT9jvRVLrB9pU6rsxOFHkZBuVtjnHdq7LEeaWJmSni1
jW6kLu98p1sf8aKe9AE7wbL0N6TEAZO6SKscGMxW7e7wtyVBnHZB7+nRi8Mlv4NSdiT27XNk4e6k
ElooORa/gqxFgI1QRAyESqD5+shgQ5l7MclGiS9KGyZdlqcgA+t2mdJp/cVrqKhLDYW0DsW2kNJE
w438Q1rUKyTcFGTW6E72f4RxVMFPJa80jR5OvOMhNe+AXsNlR3wZPNZTbF2nSaNQmYwOPHr+LLo8
f7FUXkcs8D6ab0nuKcj8cxWb1h2QtROWQXS0eoO1EYyY7hLzZZuY9ohD/NFUCPjXCORD5KGPeqSV
cwkw/h91c126CLzb1vJeu2oEfULlWAQTxKmTdru8++Up3yQi0aDWkF8jl2hPAFA+cOU7jr4c73ih
QptfT08GPmeZkCw4oIAMxNlqn3iNGhz11msj9YzE5et8rAuJLztYbR88xnoAFpGobHDkWbLIyHcW
ARm121CNcbT7i3ErlP3H4YWvZ1dvQBFpn/rsrL85CE8B+aavhzwcvjYlr/VMOry6HYv+dFIdPe1F
0NunoR4A/1KTi5RallLiucfknM88WyPX+97MmdMNDy2Ade5APbKvqx0wkJdykZFKY89oaeWjI8Vv
U+66OIKgF0I41mFCDU2htp6SlkHzJSV+/inTBjQseXdfTJx4wlKXwOC5y39xZNzZgdQyO+MgWYRD
eUP09yvnf27eg8lKF4YIdBap1bo5gHzafwLO/V/wlPAXqWjytCqqWdWCnTQOg8LMcdwjvG3kA33a
Gwu+Pqv4tYWrB7B439MJnMwmsDu7uu4aLhj/J7Uyfo1zuFbDJvYAROu5p0Mf77Z5d/j0m3kbd1GY
+OQ7PNvXaCq9SgK8J/0kZoo3AXTPGuhSoxxT48/v0y73WBb10YoSGJtec/9gXBUgoVvCpiWkMy17
pQ8V3jwaEM4Soy9xmnzqjrQkn+nM3QV9HOKhv6RLIpM1XKvfc4MXFHhIbJY7+Cm5PrQFXCOzLMS0
PShNnNwV+1Q6Bs6RAFxCV/IeSdWKGwJqOAh4h/BGIsHY+uYcHNfNdywTuMpdiJzee6IYbISARXln
I972gqneGejh3GtYJsjQgoLFZtTHB+MBznRR7xYtvhWMf5BdfPezSdGFhSs6G1rzHabbitcPs7G+
NEIVK9v29UCZv/N0XgYaZ7FXygw8lsBLoMm5vQQ+Z8H139f/phNQFoT0Ad5HVuF7vMBW+G243LhM
A9b6vgoCLFfVAFeZRt3tn2tSovafARBRWYAKOgHFuc544l3txDYrFIMTRwP6nOxFRweVn1Fd8ebS
E0gDc9Hz70FIMWUf6tOqP5VOdDaYlnH5OIv5lkgU+lHZgHMt6oQmIKsmetyFGqtr/GbIh4440EOc
UBaPwTpumMVu+4CwZEyIAzrPkm0EvICg9dnW9BVr7HEbljPzs8vv2LMGj5h2goofANuPOxJRyiCZ
c+y9pYOzevDyezTm+IOIPE4pZnLHNriPCWr7rWEzzr3UXt98vje9daRLF2YnRyeSiLOhE6uSw0Xb
ffbBamKU4sVD8/YdQ7pPo0zx7fUnHoAn8p8eqS3Au+vfZ9K2wJ3ug2AMTzK8ntzPlUWB+eVdKjAk
nMEvDbo3tfNm1nYniZQQMoyot7gWizeEH0i+9FKyjn6N3SzU2yvc3WFJAyt9g3/S56yUCGbsftoF
rmXhcOPgPbCdOcvQF/MbzVYRcBtMdkGk56rzdzLP7Zb5SRtCDrgiPQ6g+EWHe6zWVWTOeHn9Sv0B
26AtaRmODNi08lMSJ+bijbvn4CJaw0gY/FGA1FRBx/LvNkXCyMwiYuY/FdkYG0CdSZ/UM8RaeQbe
CcJiP2BeNDNsZkfu6yUwcurhMxqWiu4gELvJlHRATsg01xauvuzuWXVnZ+3xdAeT+UrqCoA/qQkp
e0TzylfHIP1t9AfWn5WzROZm82Zxw4Q3+s5HSRjaoRMCSAL8OlOHFnOcO7zJrShZmZvRxoLNA2f4
eeqeAcw/odsC35KgAouByj3iaSQbeqEnPm/Agq2TzS6rK4inhJtuMo6nGU+Ik4nSICmpaF0l43/e
1VgHeCYUiMmCSgY0ZHfu9FFohOGvgZq+jZcZbOCTByKzN3yVHxaBVy/W9yqJ/srS6fwAhShlkj3g
RDqbSIx0k7mD0U8MsbH7VgyNdLxjauscEqARwRHKsZJQ33fdG7C2wYXfgTsIugbhELg02FK0V3Rh
KvYZpAF8QP1qysU4OgvDclnz9GUfp/bI3CctS4szgKRPBfSZfqGZAk5f4RxBe6vsS4qUSdQojXP/
HL8x/Xr7UpD6alLK0tKnU97lqVB7RxvieJAOTKeN+JgVOARI3+xC+5P8ScggDCogXAuXB/DFyIkz
HAIY5GHdcvA3idsqdphaTXlxzHMpvw/n2+oyGB4+dj0lDNdC52iDfHohp8xOxpj+nY7tM9pVwi+P
LCcK3FbBYwJRuO4/TxpugPrhrm9lwJy9wOs4RRcpqM/oGQO5HpH9ESU/whVAUfHzpZ2hReSTfJ5V
tIbLdZSwvnxmUAIbvRt/cZNDAgSAa6J65LRNHNRI9DTbvddz//bfylHb1PLfrojGshaJI+Lzi0Fh
t+eSPFhs+PIT38rztzHw8V5FtFNGw5jxQ38Es+f3l2W9POMw/fapcZyHS+OiLrwEQpcQTyYEISgj
W1HIn5d9AlSJr0ytqm67Cj63kftOfbfYAeSX6JZsHT8GPJZWGW4Tro6hho4wnU1kT0acHIE9uDPi
0EZOHGBr7Xg1A+P7cuuOyfa9qGsUWTyTX2Akzs+vP2wlxnoMMXbIzhWmHdthlwJ+BOKN+GeiYJqp
ULXDIUUk+lJtjYseT8Rp4vNWkK3LJDmSOC5xXB6r3qEtHakiAUIM0SDfUDVyBqf1hTqJEqcCTLXc
vln1L50VZLJ5RQqpxT1Nk8Xx18AUieqXwTDRYFOgU5uZ2bTGJ3UmFkMH8waw22LCXD+X8cEUCU8W
cKXPLuIyfb2kryD2lOXe552nRunqDY+4G6kyLHwkJdJNvC5qNjSjG4RGw107bWMlm24QzLeUVFkB
9KJwUSd1TLAEJgS6Q291f5H1FeeMS29V/GQ/N1SHCGUYbLZe67k0zxkZbQFEIcS4SOJvj7UB1PKK
Kq3I0co4L/W26y9u2k099Xnm8q9O+BZ2ba8bODZLlt3/0ucMTF18FqWVXaCz934VnVDl6+N2g4GM
DjMkoVOh66LH3fQi6WYo/elJQdkWk4Ne8XszcLKgI56g8MAee4WsCuIVyj3TzpTONHNYSscsoQO2
INRWFUNv/cbGcQLde2Z4QhQe3puPuP+rWWD+TCPKsZUDWezoWNQ/Clh9jtVD9QS8/t5ULzbgD0L3
fvVt5Em82IaewEJIb2E85OKvn5pvQ3vHZnYcGyjdjnxPWJDhkkThZ+g21Vxd2K1jF6olmeLlC32X
F4IJ9LYOU3wCXtnWhiUMCySsQyPpYq+ZsN4+itIdEdvswK91sHf8yQpur7+2c6y1M+WRi07ez/Yi
leoFZeS/dCZDGAIvvwfSc4cLcnOFBFCrn5/hje6GxC4v0Iasjllejb4zVdNE+hZ8hjj9VeAPjV5i
1seOjClPhTbEgORqQ9LfmfOVApDBn22wYbsv0k1dw9MaytNn+eUyN3UtDNTFUejEopMP7ueWBBoR
NQa49xrCiUP95N7tQpUxwdF4pUdkfvGQt7mzX+j7ZqkuaJ+a+CXOXyLs66X+bg5Nwkl4oPdKGvsq
dCivjm3nP9uvHIbONeQ0J3gQi6AkQoIoGhlOVH2+/+lEyiIkdGQKDM8IeM6JHjuor2Zk0XvMxHy7
neklKWtEM0IoPtp6kGVCMHSyhim55W0gOoxh6InDYipNVIk0QAX/BLp9AwC7e8/BMpUXo69JtoM/
nT7J/N3B+LKQke+BsrI9V6mFl2D+gtZn2zZPp6reSp8PB+FLWGELHUjTq60HwzTTCUq0BFFLttNJ
WKzh+cF2udqcTy2+T+Zqk7PXCXN4pYhSFM9ETCG2pucFJ1U0fkrTuoiNyr05AyCjPtFKwCsCrBBl
oY5Lraqv1jIcS7Vw2Exevn2KdQAdm5GiQBHFTFBmGPFjY9NBEKPZ7NRbhE2UbL9ToejOtwvV+4xh
FB6TIJQf7GE/yF66Cpk25/SWbRrAv5OpY0zo6LEq45lQDXjedmh0A4eNmJSSiJKWdUAqRLRqKyXp
96m4HpMcwvILdLO9R+8OLa6s1laAoZdOXvXRai0F5q3Ra6KyxZBm0UDreAL7+RDKZlD24NFKNzIE
bVnpwTUXxH+4n9rB8uvydNl8kcB2x84GAFv17/uqMRPAzr/Lf+OqEa1xTkq7qnbjFf8UmQMHIZBg
U5LmxsakDvUy4Sep+IcyzQ+a2M+Jc3Xi33aShOI4X2nUaoxgLExYOlFvmEFI8EwT3vfUUwR+J/lC
To/pVfFWGJYu9HriHV/309/ZeV8+dSuYa7LCnJ37O4ggln24Z5nZVQ0VVzpbOjcEoD7Mo2pWoMWP
mBbeLyTNHgEf/d7+3sz6XbhEAQh36OClcqo0zPDMv/+lOiP/0i5LUjcilVjsCe4YzE32pvgXFl9g
eVeV+z68Hlm5Fd5f5doc4Tp/67tJfIfR3n7lTuPmtd+zhUIy075yTgG+wewk97E5oU2pcPiBr411
1EYArZBRUoAWitKrlCJEZNCSg7RgO2oaoyjc8kQK6w8aqj+K6S/XuZ+nyyCwhw/X/JWIBVuR4Zu+
xMZDBHSVISx7sP8X4C1ZUofRdX8bXd/pwP0kwztssv3DuiTfptsgxURmUEOViFdz662CvREh7C9c
gxtAPfcFuhyyBPn9kcJxD1TaeUL3xDBOq04jicIGmKw9lqNY4szjOfZ2doClrt2M1zJBTxQ3ov4V
ZmlQnXQRpb9uOtkwT96E3xwsi0zXHbm5qyDldc1XjjVqLn01xuHgbWB2XTzASKUBz2hUsodFdo9a
j8YTeg==
`protect end_protected
| bsd-2-clause | 874c212dfd8af05071278c8d37b2ea31 | 0.952579 | 1.814908 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/instantiation/rule_008_test_input.fixed_lower.vhd | 1 | 407 |
architecture ARCH of ENTITY1 is
begin
u_inst1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
u_inst1 : INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
end architecture ARCH;
| gpl-3.0 | 227ab9fcc73a9e02cf4117a5d0e25e0e | 0.481572 | 2.787671 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/lite_ecc_reg.vhd | 1 | 68,157 | -------------------------------------------------------------------------------
-- lite_ecc_reg.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: lite_ecc_reg.vhd
--
-- Description: This module contains the register components for the
-- ECC status & control data when enabled.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- Remove library version # dependency. Replace with work library.
-- ^^^^^^
-- JLJ 2/17/2011 v1.03a
-- ~~~~~~
-- Add ECC support for 128-bit BRAM data width.
-- Clean-up XST warnings. Add C_BRAM_ADDR_ADJUST_FACTOR parameter and
-- modify BRAM address registers.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.axi_lite_if;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity lite_ecc_reg is
generic (
C_S_AXI_PROTOCOL : string := "AXI4";
-- Used in this module to differentiate timing for error capture
C_S_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_SINGLE_PORT_BRAM : INTEGER := 1;
-- Enable single port usage of BRAM
C_BRAM_ADDR_ADJUST_FACTOR : integer := 2;
-- Adjust factor to BRAM address width based on data width (in bits)
-- AXI-Lite Register Parameters
C_S_AXI_CTRL_ADDR_WIDTH : integer := 32;
-- Width of AXI-Lite address bus (in bits)
C_S_AXI_CTRL_DATA_WIDTH : integer := 32;
-- Width of AXI-Lite data bus (in bits)
-- ECC Parameters
C_ECC_WIDTH : integer := 8;
-- Width of ECC data vector
C_FAULT_INJECT : integer := 0;
-- Enable fault injection registers
C_ECC_ONOFF_RESET_VALUE : integer := 1;
-- By default, ECC checking is on (can disable ECC @ reset by setting this to 0)
-- Hard coded parameters at top level.
-- Note: Kept in design for future enhancement.
C_ENABLE_AXI_CTRL_REG_IF : integer := 0;
-- By default the ECC AXI-Lite register interface is enabled
C_CE_FAILING_REGISTERS : integer := 0;
-- Enable CE (correctable error) failing registers
C_UE_FAILING_REGISTERS : integer := 0;
-- Enable UE (uncorrectable error) failing registers
C_ECC_STATUS_REGISTERS : integer := 0;
-- Enable ECC status registers
C_ECC_ONOFF_REGISTER : integer := 0;
-- Enable ECC on/off control register
C_CE_COUNTER_WIDTH : integer := 0
-- Selects CE counter width/threshold to assert ECC_Interrupt
);
port (
-- AXI Clock and Reset
S_AXI_AClk : in std_logic;
S_AXI_AResetn : in std_logic;
-- AXI-Lite Clock and Reset
-- Note: AXI-Lite Control IF and AXI IF share the same clock.
-- S_AXI_CTRL_AClk : in std_logic;
-- S_AXI_CTRL_AResetn : in std_logic;
Interrupt : out std_logic := '0';
ECC_UE : out std_logic := '0';
-- *** AXI-Lite ECC Register Interface Signals ***
-- All synchronized to S_AXI_CTRL_AClk
-- AXI-Lite Write Address Channel Signals (AW)
AXI_CTRL_AWVALID : in std_logic;
AXI_CTRL_AWREADY : out std_logic;
AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
-- AXI-Lite Write Data Channel Signals (W)
AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
AXI_CTRL_WVALID : in std_logic;
AXI_CTRL_WREADY : out std_logic;
-- AXI-Lite Write Data Response Channel Signals (B)
AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
AXI_CTRL_BVALID : out std_logic;
AXI_CTRL_BREADY : in std_logic;
-- AXI-Lite Read Address Channel Signals (AR)
AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
AXI_CTRL_ARVALID : in std_logic;
AXI_CTRL_ARREADY : out std_logic;
-- AXI-Lite Read Data Channel Signals (R)
AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
AXI_CTRL_RVALID : out std_logic;
AXI_CTRL_RREADY : in std_logic;
-- *** Memory Controller Interface Signals ***
-- All synchronized to S_AXI_AClk
Enable_ECC : out std_logic;
-- Indicates if and when ECC is enabled
FaultInjectClr : in std_logic;
-- Clear for Fault Inject Registers
CE_Failing_We : in std_logic;
-- WE for CE Failing Registers
-- UE_Failing_We : in std_logic;
-- WE for CE Failing Registers
CE_CounterReg_Inc : in std_logic;
-- Increment CE Counter Register
Sl_CE : in std_logic;
-- Correctable Error Flag
Sl_UE : in std_logic;
-- Uncorrectable Error Flag
BRAM_Addr_A : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- v1.03a
BRAM_Addr_B : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- v1.03a
BRAM_Addr_En : in std_logic;
Active_Wr : in std_logic;
-- BRAM_RdData_A : in std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1);
-- BRAM_RdData_B : in std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1);
-- Outputs
FaultInjectData : out std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1);
FaultInjectECC : out std_logic_vector (0 to C_ECC_WIDTH-1)
);
end entity lite_ecc_reg;
-------------------------------------------------------------------------------
architecture implementation of lite_ecc_reg is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant C_RESET_ACTIVE : std_logic := '0';
constant IF_IS_AXI4 : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4"));
constant IF_IS_AXI4LITE : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4LITE"));
-- Start LMB BRAM v3.00a HDL
constant C_HAS_FAULT_INJECT : boolean := C_FAULT_INJECT = 1;
constant C_HAS_CE_FAILING_REGISTERS : boolean := C_CE_FAILING_REGISTERS = 1;
constant C_HAS_UE_FAILING_REGISTERS : boolean := C_UE_FAILING_REGISTERS = 1;
constant C_HAS_ECC_STATUS_REGISTERS : boolean := C_ECC_STATUS_REGISTERS = 1;
constant C_HAS_ECC_ONOFF : boolean := C_ECC_ONOFF_REGISTER = 1;
constant C_HAS_CE_COUNTER : boolean := C_CE_COUNTER_WIDTH /= 0;
-- Register accesses
-- Register addresses use word address, i.e 2 LSB don't care
-- Don't decode MSB, i.e. mirrorring of registers in address space of module
constant C_REGADDR_WIDTH : integer := 8;
constant C_ECC_StatusReg : std_logic_vector := "00000000"; -- 0x0 = 00 0000 00
constant C_ECC_EnableIRQReg : std_logic_vector := "00000001"; -- 0x4 = 00 0000 01
constant C_ECC_OnOffReg : std_logic_vector := "00000010"; -- 0x8 = 00 0000 10
constant C_CE_CounterReg : std_logic_vector := "00000011"; -- 0xC = 00 0000 11
constant C_CE_FailingData_31_0 : std_logic_vector := "01000000"; -- 0x100 = 01 0000 00
constant C_CE_FailingData_63_31 : std_logic_vector := "01000001"; -- 0x104 = 01 0000 01
constant C_CE_FailingData_95_64 : std_logic_vector := "01000010"; -- 0x108 = 01 0000 10
constant C_CE_FailingData_127_96 : std_logic_vector := "01000011"; -- 0x10C = 01 0000 11
constant C_CE_FailingECC : std_logic_vector := "01100000"; -- 0x180 = 01 1000 00
constant C_CE_FailingAddress_31_0 : std_logic_vector := "01110000"; -- 0x1C0 = 01 1100 00
constant C_CE_FailingAddress_63_32 : std_logic_vector := "01110001"; -- 0x1C4 = 01 1100 01
constant C_UE_FailingData_31_0 : std_logic_vector := "10000000"; -- 0x200 = 10 0000 00
constant C_UE_FailingData_63_31 : std_logic_vector := "10000001"; -- 0x204 = 10 0000 01
constant C_UE_FailingData_95_64 : std_logic_vector := "10000010"; -- 0x208 = 10 0000 10
constant C_UE_FailingData_127_96 : std_logic_vector := "10000011"; -- 0x20C = 10 0000 11
constant C_UE_FailingECC : std_logic_vector := "10100000"; -- 0x280 = 10 1000 00
constant C_UE_FailingAddress_31_0 : std_logic_vector := "10110000"; -- 0x2C0 = 10 1100 00
constant C_UE_FailingAddress_63_32 : std_logic_vector := "10110000"; -- 0x2C4 = 10 1100 00
constant C_FaultInjectData_31_0 : std_logic_vector := "11000000"; -- 0x300 = 11 0000 00
constant C_FaultInjectData_63_32 : std_logic_vector := "11000001"; -- 0x304 = 11 0000 01
constant C_FaultInjectData_95_64 : std_logic_vector := "11000010"; -- 0x308 = 11 0000 10
constant C_FaultInjectData_127_96 : std_logic_vector := "11000011"; -- 0x30C = 11 0000 11
constant C_FaultInjectECC : std_logic_vector := "11100000"; -- 0x380 = 11 1000 00
-- ECC Status register bit positions
constant C_ECC_STATUS_CE : natural := 30;
constant C_ECC_STATUS_UE : natural := 31;
constant C_ECC_STATUS_WIDTH : natural := 2;
constant C_ECC_ENABLE_IRQ_CE : natural := 30;
constant C_ECC_ENABLE_IRQ_UE : natural := 31;
constant C_ECC_ENABLE_IRQ_WIDTH : natural := 2;
constant C_ECC_ON_OFF_WIDTH : natural := 1;
-- End LMB BRAM v3.00a HDL
constant MSB_ZERO : std_logic_vector (31 downto C_S_AXI_ADDR_WIDTH) := (others => '0');
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal S_AXI_AReset : std_logic;
-- Start LMB BRAM v3.00a HDL
-- Read and write data to internal registers
constant C_DWIDTH : integer := 32;
signal RegWrData : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
signal RegWrData_i : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
--signal RegWrData_d1 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
--signal RegWrData_d2 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
signal RegRdData : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
signal RegRdData_i : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
--signal RegRdData_d1 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
--signal RegRdData_d2 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
signal RegAddr : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0');
signal RegAddr_i : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0');
--signal RegAddr_d1 : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0');
--signal RegAddr_d2 : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0');
signal RegWr : std_logic;
signal RegWr_i : std_logic;
--signal RegWr_d1 : std_logic;
--signal RegWr_d2 : std_logic;
-- Fault Inject Register
signal FaultInjectData_WE_0 : std_logic := '0';
signal FaultInjectData_WE_1 : std_logic := '0';
signal FaultInjectData_WE_2 : std_logic := '0';
signal FaultInjectData_WE_3 : std_logic := '0';
signal FaultInjectECC_WE : std_logic := '0';
--signal FaultInjectClr : std_logic := '0';
-- Correctable Error First Failing Register
signal CE_FailingAddress : std_logic_vector(0 to 31) := (others => '0');
signal CE_Failing_We_i : std_logic := '0';
-- signal CE_FailingData : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1) := (others => '0');
-- signal CE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31);
-- Uncorrectable Error First Failing Register
-- signal UE_FailingAddress : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1) := (others => '0');
-- signal UE_Failing_We_i : std_logic := '0';
-- signal UE_FailingData : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1) := (others => '0');
-- signal UE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31) := (others => '0');
-- ECC Status and Control register
signal ECC_StatusReg : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31) := (others => '0');
signal ECC_StatusReg_WE : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31) := (others => '0');
signal ECC_EnableIRQReg : std_logic_vector(32-C_ECC_ENABLE_IRQ_WIDTH to 31) := (others => '0');
signal ECC_EnableIRQReg_WE : std_logic := '0';
-- ECC On/Off Control register
signal ECC_OnOffReg : std_logic_vector(32-C_ECC_ON_OFF_WIDTH to 31) := (others => '0');
signal ECC_OnOffReg_WE : std_logic := '0';
-- Correctable Error Counter
signal CE_CounterReg : std_logic_vector(32-C_CE_COUNTER_WIDTH to 31) := (others => '0');
signal CE_CounterReg_WE : std_logic := '0';
signal CE_CounterReg_Inc_i : std_logic := '0';
-- End LMB BRAM v3.00a HDL
signal BRAM_Addr_A_d1 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a
signal BRAM_Addr_A_d2 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a
signal FailingAddr_Ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal axi_lite_wstrb_int : std_logic_vector (C_S_AXI_CTRL_DATA_WIDTH/8-1 downto 0) := (others => '0');
signal Enable_ECC_i : std_logic := '0';
signal ECC_UE_i : std_logic := '0';
signal FaultInjectData_i : std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1) := (others => '0');
signal FaultInjectECC_i : std_logic_vector (0 to C_ECC_WIDTH-1) := (others => '0');
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
FaultInjectData <= FaultInjectData_i;
FaultInjectECC <= FaultInjectECC_i;
-- Reserve for future support.
-- S_AXI_CTRL_AReset <= not (S_AXI_CTRL_AResetn);
S_AXI_AReset <= not (S_AXI_AResetn);
---------------------------------------------------------------------------
-- Instance: I_LITE_ECC_REG
--
-- Description:
-- This module is for the AXI-Lite ECC registers.
--
-- Responsible for all AXI-Lite communication to the
-- ECC register bank. Provides user interface signals
-- to rest of AXI BRAM controller IP core for ECC functionality
-- and control.
--
-- Manages AXI-Lite write address (AW) and read address (AR),
-- write data (W), write response (B), and read data (R) channels.
--
-- Synchronized to AXI-Lite clock and reset.
-- All RegWr, RegWrData, RegAddr, RegRdData must be synchronized to
-- the AXI clock.
--
---------------------------------------------------------------------------
I_AXI_LITE_IF : entity work.axi_lite_if
generic map(
C_S_AXI_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH,
C_REGADDR_WIDTH => C_REGADDR_WIDTH,
C_DWIDTH => C_DWIDTH
)
port map (
-- Reserve for future support.
-- LMB_Clk => S_AXI_CTRL_AClk,
-- LMB_Rst => S_AXI_CTRL_AReset,
LMB_Clk => S_AXI_AClk,
LMB_Rst => S_AXI_AReset,
S_AXI_AWADDR => AXI_CTRL_AWADDR,
S_AXI_AWVALID => AXI_CTRL_AWVALID,
S_AXI_AWREADY => AXI_CTRL_AWREADY,
S_AXI_WDATA => AXI_CTRL_WDATA,
S_AXI_WSTRB => axi_lite_wstrb_int,
S_AXI_WVALID => AXI_CTRL_WVALID,
S_AXI_WREADY => AXI_CTRL_WREADY,
S_AXI_BRESP => AXI_CTRL_BRESP,
S_AXI_BVALID => AXI_CTRL_BVALID,
S_AXI_BREADY => AXI_CTRL_BREADY,
S_AXI_ARADDR => AXI_CTRL_ARADDR,
S_AXI_ARVALID => AXI_CTRL_ARVALID,
S_AXI_ARREADY => AXI_CTRL_ARREADY,
S_AXI_RDATA => AXI_CTRL_RDATA,
S_AXI_RRESP => AXI_CTRL_RRESP,
S_AXI_RVALID => AXI_CTRL_RVALID,
S_AXI_RREADY => AXI_CTRL_RREADY,
RegWr => RegWr_i,
RegWrData => RegWrData_i,
RegAddr => RegAddr_i,
RegRdData => RegRdData_i
);
-- Note: AXI-Lite Control IF and AXI IF share the same clock.
--
-- Save HDL
-- If it is decided to go back and use seperate clock inputs
-- One for AXI4 and one for AXI4-Lite on this core.
-- For now, temporarily comment out and replace the *_i signal
-- assignments.
RegWr <= RegWr_i;
RegWrData <= RegWrData_i;
RegAddr <= RegAddr_i;
RegRdData_i <= RegRdData;
-- Reserve for future support.
--
-- ---------------------------------------------------------------------------
-- --
-- -- All registers must be synchronized to the correct clock.
-- -- RegWr must be synchronized to the S_AXI_Clk
-- -- RegWrData must be synchronized to the S_AXI_Clk
-- -- RegAddr must be synchronized to the S_AXI_Clk
-- -- RegRdData must be synchronized to the S_AXI_CTRL_Clk
-- --
-- ---------------------------------------------------------------------------
--
-- SYNC_AXI_CLK: process (S_AXI_AClk)
-- begin
-- if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- RegWr_d1 <= RegWr_i;
-- RegWr_d2 <= RegWr_d1;
-- RegWrData_d1 <= RegWrData_i;
-- RegWrData_d2 <= RegWrData_d1;
-- RegAddr_d1 <= RegAddr_i;
-- RegAddr_d2 <= RegAddr_d1;
-- end if;
-- end process SYNC_AXI_CLK;
--
-- RegWr <= RegWr_d2;
-- RegWrData <= RegWrData_d2;
-- RegAddr <= RegAddr_d2;
--
--
-- SYNC_AXI_LITE_CLK: process (S_AXI_CTRL_AClk)
-- begin
-- if (S_AXI_CTRL_AClk'event and S_AXI_CTRL_AClk = '1' ) then
-- RegRdData_d1 <= RegRdData;
-- RegRdData_d2 <= RegRdData_d1;
-- end if;
-- end process SYNC_AXI_LITE_CLK;
--
-- RegRdData_i <= RegRdData_d2;
--
---------------------------------------------------------------------------
axi_lite_wstrb_int <= (others => '1');
---------------------------------------------------------------------------
-- Generate: GEN_ADDR_REG_SNG
-- Purpose: Generate two deep wrap-around address pipeline to store
-- read address presented to BRAM. Used to update ECC
-- register value when ECC correctable or uncorrectable error
-- is detected.
--
-- If single port, only register Port A address.
--
-- With CE flag being registered, must account for one more
-- pipeline stage in stored BRAM addresss that correlates to
-- failing ECC.
---------------------------------------------------------------------------
GEN_ADDR_REG_SNG: if (C_SINGLE_PORT_BRAM = 1) generate
-- 3rd pipeline stage on Port A (used for reads in single port mode) ONLY
signal BRAM_Addr_A_d3 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a
begin
BRAM_ADDR_REG: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (BRAM_Addr_En = '1') then
BRAM_Addr_A_d1 <= BRAM_Addr_A;
BRAM_Addr_A_d2 <= BRAM_Addr_A_d1;
BRAM_Addr_A_d3 <= BRAM_Addr_A_d2;
else
BRAM_Addr_A_d1 <= BRAM_Addr_A_d1;
BRAM_Addr_A_d2 <= BRAM_Addr_A_d2;
BRAM_Addr_A_d3 <= BRAM_Addr_A_d3;
end if;
end if;
end process BRAM_ADDR_REG;
---------------------------------------------------------------------------
-- Generate: GEN_L_ADDR
-- Purpose: Lower order BRAM address bits fixed @ zero depending
-- on BRAM data width size.
---------------------------------------------------------------------------
GEN_L_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate
begin
FailingAddr_Ld (i) <= '0';
end generate GEN_L_ADDR;
---------------------------------------------------------------------------
-- Generate: GEN_ADDR
-- Purpose: Assign valid BRAM address bits based on BRAM data width size.
---------------------------------------------------------------------------
GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate
begin
GEN_FA_LITE: if IF_IS_AXI4LITE generate
begin
FailingAddr_Ld (i) <= BRAM_Addr_A_d1(i); -- Only a single address active at a time.
end generate GEN_FA_LITE;
GEN_FA_AXI: if IF_IS_AXI4 generate
begin
-- During the RMW portion, only one active address (use _d1 pipeline).
-- During read operaitons, use 3-deep address pipeline to store address values.
FailingAddr_Ld (i) <= BRAM_Addr_A_d3 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i);
end generate GEN_FA_AXI;
end generate GEN_ADDR;
end generate GEN_ADDR_REG_SNG;
---------------------------------------------------------------------------
-- Generate: GEN_ADDR_REG_DUAL
-- Purpose: Generate two deep wrap-around address pipeline to store
-- read address presented to BRAM. Used to update ECC
-- register value when ECC correctable or uncorrectable error
-- is detected.
--
-- If dual port BRAM, register Port A & Port B address.
--
-- Account for CE flag register delay, add 3rd BRAM address
-- pipeline stage.
--
---------------------------------------------------------------------------
GEN_ADDR_REG_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate
-- Port B pipeline stages only used in a dual port mode configuration.
signal BRAM_Addr_B_d1 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a
signal BRAM_Addr_B_d2 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a
signal BRAM_Addr_B_d3 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a
begin
BRAM_ADDR_REG: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (BRAM_Addr_En = '1') then
BRAM_Addr_A_d1 <= BRAM_Addr_A;
BRAM_Addr_B_d1 <= BRAM_Addr_B;
BRAM_Addr_B_d2 <= BRAM_Addr_B_d1;
BRAM_Addr_B_d3 <= BRAM_Addr_B_d2;
else
BRAM_Addr_A_d1 <= BRAM_Addr_A_d1;
BRAM_Addr_B_d1 <= BRAM_Addr_B_d1;
BRAM_Addr_B_d2 <= BRAM_Addr_B_d2;
BRAM_Addr_B_d3 <= BRAM_Addr_B_d3;
end if;
end if;
end process BRAM_ADDR_REG;
---------------------------------------------------------------------------
-- Generate: GEN_L_ADDR
-- Purpose: Lower order BRAM address bits fixed @ zero depending
-- on BRAM data width size.
---------------------------------------------------------------------------
GEN_L_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate
begin
FailingAddr_Ld (i) <= '0';
end generate GEN_L_ADDR;
---------------------------------------------------------------------------
-- Generate: GEN_ADDR
-- Purpose: Assign valid BRAM address bits based on BRAM data width size.
---------------------------------------------------------------------------
GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate
begin
GEN_FA_LITE: if IF_IS_AXI4LITE generate
begin
-- Only one active operation at a time.
-- Use one deep address pipeline. Determine if Port A or B based on active read or write.
FailingAddr_Ld (i) <= BRAM_Addr_B_d1 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i);
end generate GEN_FA_LITE;
GEN_FA_AXI: if IF_IS_AXI4 generate
begin
-- During the RMW portion, only one active address (use _d1 pipeline) (and from Port A).
-- During read operations, use 3-deep address pipeline to store address values (and from Port B).
FailingAddr_Ld (i) <= BRAM_Addr_B_d3 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i);
end generate GEN_FA_AXI;
end generate GEN_ADDR;
end generate GEN_ADDR_REG_DUAL;
---------------------------------------------------------------------------
-- Generate: FAULT_INJECT
-- Purpose: Implement fault injection registers
-- Remove check for (C_WRITE_ACCESS /= NO_WRITES) (from LMB)
---------------------------------------------------------------------------
FAULT_INJECT : if C_HAS_FAULT_INJECT generate
begin
-- FaultInjectClr added to top level port list.
-- Original LMB BRAM HDL
-- FaultInjectClr <= '1' when ((sl_ready_i = '1') and (write_access = '1')) else '0';
---------------------------------------------------------------------------
-- Generate: GEN_32_FAULT
-- Purpose: Create generates based on 32-bit C_S_AXI_DATA_WIDTH
---------------------------------------------------------------------------
GEN_32_FAULT : if C_S_AXI_DATA_WIDTH = 32 generate
begin
FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0';
FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0';
-- Create fault vector for 32-bit data widths
FaultInjectDataReg : process(S_AXI_AClk) is
begin
if S_AXI_AClk'event and S_AXI_AClk = '1' then
if S_AXI_AResetn = C_RESET_ACTIVE then
FaultInjectData_i <= (others => '0');
FaultInjectECC_i <= (others => '0');
elsif FaultInjectData_WE_0 = '1' then
FaultInjectData_i (0 to 31) <= RegWrData;
elsif FaultInjectECC_WE = '1' then
-- FaultInjectECC_i <= RegWrData(0 to C_DWIDTH-1);
-- FaultInjectECC_i <= RegWrData(0 to C_ECC_WIDTH-1);
-- (25:31)
FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1);
elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write
FaultInjectData_i <= (others => '0');
FaultInjectECC_i <= (others => '0');
end if;
end if;
end process FaultInjectDataReg;
end generate GEN_32_FAULT;
---------------------------------------------------------------------------
-- Generate: GEN_64_FAULT
-- Purpose: Create generates based on 64-bit C_S_AXI_DATA_WIDTH
---------------------------------------------------------------------------
GEN_64_FAULT : if C_S_AXI_DATA_WIDTH = 64 generate
begin
FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0';
FaultInjectData_WE_1 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_63_32) else '0';
FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0';
-- Create fault vector for 64-bit data widths
FaultInjectDataReg : process(S_AXI_AClk) is
begin
if S_AXI_AClk'event and S_AXI_AClk = '1' then
if S_AXI_AResetn = C_RESET_ACTIVE then
FaultInjectData_i <= (others => '0');
FaultInjectECC_i <= (others => '0');
elsif FaultInjectData_WE_0 = '1' then
FaultInjectData_i (32 to 63) <= RegWrData;
elsif FaultInjectData_WE_1 = '1' then
FaultInjectData_i (0 to 31) <= RegWrData;
elsif FaultInjectECC_WE = '1' then
-- FaultInjectECC_i <= RegWrData(0 to C_DWIDTH-1);
-- FaultInjectECC_i <= RegWrData(0 to C_ECC_WIDTH-1);
-- (24:31)
FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1);
elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write
FaultInjectData_i <= (others => '0');
FaultInjectECC_i <= (others => '0');
end if;
end if;
end process FaultInjectDataReg;
end generate GEN_64_FAULT;
-- v1.03a
---------------------------------------------------------------------------
-- Generate: GEN_128_FAULT
-- Purpose: Create generates based on 128-bit C_S_AXI_DATA_WIDTH
---------------------------------------------------------------------------
GEN_128_FAULT : if C_S_AXI_DATA_WIDTH = 128 generate
begin
FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0';
FaultInjectData_WE_1 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_63_32) else '0';
FaultInjectData_WE_2 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_95_64) else '0';
FaultInjectData_WE_3 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_127_96) else '0';
FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0';
-- Create fault vector for 128-bit data widths
FaultInjectDataReg : process(S_AXI_AClk) is
begin
if S_AXI_AClk'event and S_AXI_AClk = '1' then
if S_AXI_AResetn = C_RESET_ACTIVE then
FaultInjectData_i <= (others => '0');
FaultInjectECC_i <= (others => '0');
elsif FaultInjectData_WE_0 = '1' then
FaultInjectData_i (96 to 127) <= RegWrData;
elsif FaultInjectData_WE_1 = '1' then
FaultInjectData_i (64 to 95) <= RegWrData;
elsif FaultInjectData_WE_2 = '1' then
FaultInjectData_i (32 to 63) <= RegWrData;
elsif FaultInjectData_WE_3 = '1' then
FaultInjectData_i (0 to 31) <= RegWrData;
elsif FaultInjectECC_WE = '1' then
FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1);
elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write
FaultInjectData_i <= (others => '0');
FaultInjectECC_i <= (others => '0');
end if;
end if;
end process FaultInjectDataReg;
end generate GEN_128_FAULT;
end generate FAULT_INJECT;
---------------------------------------------------------------------------
-- Generate: NO_FAULT_INJECT
-- Purpose: Set default outputs when no fault inject capabilities.
-- Remove check from C_WRITE_ACCESS (from LMB)
---------------------------------------------------------------------------
NO_FAULT_INJECT : if not C_HAS_FAULT_INJECT generate
begin
FaultInjectData_i <= (others => '0');
FaultInjectECC_i <= (others => '0');
end generate NO_FAULT_INJECT;
---------------------------------------------------------------------------
-- Generate: CE_FAILING_REGISTERS
-- Purpose: Implement Correctable Error First Failing Register
---------------------------------------------------------------------------
CE_FAILING_REGISTERS : if C_HAS_CE_FAILING_REGISTERS generate
begin
-- TBD (could come from axi_lite)
-- CE_Failing_We <= '1' when (Sl_CE_i = '1' and Sl_Ready_i = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0')
-- else '0';
CE_Failing_We_i <= '1' when (CE_Failing_We = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0')
else '0';
CE_FailingReg : process(S_AXI_AClk) is
begin
if S_AXI_AClk'event and S_AXI_AClk = '1' then
if S_AXI_AResetn = C_RESET_ACTIVE then
CE_FailingAddress <= (others => '0');
-- Reserve for future support.
-- CE_FailingData <= (others => '0');
elsif CE_Failing_We_i = '1' then
--As the AXI Addr Width can now be lesser than 32, the address is getting shifted
--Eg: If addr width is 16, and Failing address is 0000_fffc, the o/p on RDATA is comming as fffc_0000
CE_FailingAddress (0 to C_S_AXI_ADDR_WIDTH-1) <= FailingAddr_Ld (C_S_AXI_ADDR_WIDTH-1 downto 0);
--CE_FailingAddress <= MSB_ZERO & FailingAddr_Ld ;
-- Reserve for future support.
-- CE_FailingData (0 to C_S_AXI_DATA_WIDTH-1) <= FailingRdData(0 to C_DWIDTH-1);
end if;
end if;
end process CE_FailingReg;
-- Note: Remove storage of CE_FFE & CE_FFD registers.
-- Here for future support.
--
-- -----------------------------------------------------------------
-- -- Generate: GEN_CE_ECC_32
-- -- Purpose: Re-align ECC bits unique for 32-bit BRAM data width.
-- -----------------------------------------------------------------
-- GEN_CE_ECC_32: if C_S_AXI_DATA_WIDTH = 32 generate
-- begin
--
-- CE_FailingECCReg : process(S_AXI_AClk) is
-- begin
-- if S_AXI_AClk'event and S_AXI_AClk = '1' then
-- if S_AXI_AResetn = C_RESET_ACTIVE then
-- CE_FailingECC <= (others => '0');
-- elsif CE_Failing_We_i = '1' then
-- -- Data2Mem shifts ECC to lower data bits in remaining byte (when 32-bit data width) (33 to 39)
-- CE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH+1 to C_S_AXI_DATA_WIDTH+1+C_ECC_WIDTH-1);
-- end if;
-- end if;
-- end process CE_FailingECCReg;
--
-- end generate GEN_CE_ECC_32;
--
-- -----------------------------------------------------------------
-- -- Generate: GEN_CE_ECC_64
-- -- Purpose: Re-align ECC bits unique for 64-bit BRAM data width.
-- -----------------------------------------------------------------
-- GEN_CE_ECC_64: if C_S_AXI_DATA_WIDTH = 64 generate
-- begin
--
-- CE_FailingECCReg : process(S_AXI_AClk) is
-- begin
-- if S_AXI_AClk'event and S_AXI_AClk = '1' then
-- if S_AXI_AResetn = C_RESET_ACTIVE then
-- CE_FailingECC <= (others => '0');
-- elsif CE_Failing_We_i = '1' then
-- CE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1);
-- end if;
-- end if;
-- end process CE_FailingECCReg;
--
-- end generate GEN_CE_ECC_64;
end generate CE_FAILING_REGISTERS;
---------------------------------------------------------------------------
-- Generate: NO_CE_FAILING_REGISTERS
-- Purpose: No Correctable Error Failing registers.
---------------------------------------------------------------------------
NO_CE_FAILING_REGISTERS : if not C_HAS_CE_FAILING_REGISTERS generate
begin
CE_FailingAddress <= (others => '0');
-- CE_FailingData <= (others => '0');
-- CE_FailingECC <= (others => '0');
end generate NO_CE_FAILING_REGISTERS;
-- Note: C_HAS_UE_FAILING_REGISTERS will always be set to 0
-- This generate clause will never be evaluated.
-- Here for future support.
--
-- ---------------------------------------------------------------------------
-- -- Generate: UE_FAILING_REGISTERS
-- -- Purpose: Implement Unorrectable Error First Failing Register
-- ---------------------------------------------------------------------------
--
-- UE_FAILING_REGISTERS : if C_HAS_UE_FAILING_REGISTERS generate
-- begin
--
-- -- TBD (could come from axi_lite)
-- -- UE_Failing_We <= '1' when (Sl_UE_i = '1' and Sl_Ready_i = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0')
-- -- else '0';
--
-- UE_Failing_We_i <= '1' when (UE_Failing_We = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0')
-- else '0';
--
--
-- UE_FailingReg : process(S_AXI_AClk) is
-- begin
-- if S_AXI_AClk'event and S_AXI_AClk = '1' then
-- if S_AXI_AResetn = C_RESET_ACTIVE then
-- UE_FailingAddress <= (others => '0');
-- UE_FailingData <= (others => '0');
-- elsif UE_Failing_We = '1' then
-- UE_FailingAddress <= FailingAddr_Ld;
-- UE_FailingData <= FailingRdData(0 to C_DWIDTH-1);
-- end if;
-- end if;
-- end process UE_FailingReg;
--
-- -----------------------------------------------------------------
-- -- Generate: GEN_UE_ECC_32
-- -- Purpose: Re-align ECC bits unique for 32-bit BRAM data width.
-- -----------------------------------------------------------------
-- GEN_UE_ECC_32: if C_S_AXI_DATA_WIDTH = 32 generate
-- begin
--
-- UE_FailingECCReg : process(S_AXI_AClk) is
-- begin
-- if S_AXI_AClk'event and S_AXI_AClk = '1' then
-- if S_AXI_AResetn = C_RESET_ACTIVE then
-- UE_FailingECC <= (others => '0');
-- elsif UE_Failing_We = '1' then
-- -- Data2Mem shifts ECC to lower data bits in remaining byte (when 32-bit data width) (33 to 39)
-- UE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH+1 to C_S_AXI_DATA_WIDTH+1+C_ECC_WIDTH-1);
-- end if;
-- end if;
-- end process UE_FailingECCReg;
--
-- end generate GEN_UE_ECC_32;
--
-- -----------------------------------------------------------------
-- -- Generate: GEN_UE_ECC_64
-- -- Purpose: Re-align ECC bits unique for 64-bit BRAM data width.
-- -----------------------------------------------------------------
-- GEN_UE_ECC_64: if C_S_AXI_DATA_WIDTH = 64 generate
-- begin
--
-- UE_FailingECCReg : process(S_AXI_AClk) is
-- begin
-- if S_AXI_AClk'event and S_AXI_AClk = '1' then
-- if S_AXI_AResetn = C_RESET_ACTIVE then
-- UE_FailingECC <= (others => '0');
-- elsif UE_Failing_We = '1' then
-- UE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1);
-- end if;
-- end if;
-- end process UE_FailingECCReg;
--
-- end generate GEN_UE_ECC_64;
--
-- end generate UE_FAILING_REGISTERS;
--
--
-- ---------------------------------------------------------------------------
-- -- Generate: NO_UE_FAILING_REGISTERS
-- -- Purpose: No Uncorrectable Error Failing registers.
-- ---------------------------------------------------------------------------
--
-- NO_UE_FAILING_REGISTERS : if not C_HAS_UE_FAILING_REGISTERS generate
-- begin
-- UE_FailingAddress <= (others => '0');
-- UE_FailingData <= (others => '0');
-- UE_FailingECC <= (others => '0');
-- end generate NO_UE_FAILING_REGISTERS;
---------------------------------------------------------------------------
-- Generate: ECC_STATUS_REGISTERS
-- Purpose: Enable ECC status and interrupt enable registers.
---------------------------------------------------------------------------
ECC_STATUS_REGISTERS : if C_HAS_ECC_STATUS_REGISTERS generate
begin
ECC_StatusReg_WE (C_ECC_STATUS_CE) <= Sl_CE;
ECC_StatusReg_WE (C_ECC_STATUS_UE) <= Sl_UE;
StatusReg : process(S_AXI_AClk) is
begin
if S_AXI_AClk'event and S_AXI_AClk = '1' then
if S_AXI_AResetn = C_RESET_ACTIVE then
ECC_StatusReg <= (others => '0');
elsif RegWr = '1' and RegAddr = C_ECC_StatusReg then
-- CE Interrupt status bit
if RegWrData(C_ECC_STATUS_CE) = '1' then
ECC_StatusReg(C_ECC_STATUS_CE) <= '0'; -- Clear when write '1'
end if;
-- UE Interrupt status bit
if RegWrData(C_ECC_STATUS_UE) = '1' then
ECC_StatusReg(C_ECC_STATUS_UE) <= '0'; -- Clear when write '1'
end if;
else
if Sl_CE = '1' then
ECC_StatusReg(C_ECC_STATUS_CE) <= '1'; -- Set when CE occurs
end if;
if Sl_UE = '1' then
ECC_StatusReg(C_ECC_STATUS_UE) <= '1'; -- Set when UE occurs
end if;
end if;
end if;
end process StatusReg;
ECC_EnableIRQReg_WE <= '1' when (RegWr = '1' and RegAddr = C_ECC_EnableIRQReg) else '0';
EnableIRQReg : process(S_AXI_AClk) is
begin
if S_AXI_AClk'event and S_AXI_AClk = '1' then
if S_AXI_AResetn = C_RESET_ACTIVE then
ECC_EnableIRQReg <= (others => '0');
elsif ECC_EnableIRQReg_WE = '1' then
-- CE Interrupt enable bit
ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE) <= RegWrData(C_ECC_ENABLE_IRQ_CE);
-- UE Interrupt enable bit
ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE) <= RegWrData(C_ECC_ENABLE_IRQ_UE);
end if;
end if;
end process EnableIRQReg;
Interrupt <= (ECC_StatusReg(C_ECC_STATUS_CE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE)) or
(ECC_StatusReg(C_ECC_STATUS_UE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE));
---------------------------------------------------------------------------
-- Generate output flag for UE sticky bit
-- Modify order to ensure that ECC_UE gets set when Sl_UE is asserted.
REG_UE : process (S_AXI_AClk) is
begin
if S_AXI_AClk'event and S_AXI_AClk = '1' then
if S_AXI_AResetn = C_RESET_ACTIVE or
(Enable_ECC_i = '0') then
ECC_UE_i <= '0';
elsif Sl_UE = '1' then
ECC_UE_i <= '1';
elsif (ECC_StatusReg (C_ECC_STATUS_UE) = '0') then
ECC_UE_i <= '0';
else
ECC_UE_i <= ECC_UE_i;
end if;
end if;
end process REG_UE;
ECC_UE <= ECC_UE_i;
---------------------------------------------------------------------------
end generate ECC_STATUS_REGISTERS;
---------------------------------------------------------------------------
-- Generate: NO_ECC_STATUS_REGISTERS
-- Purpose: No ECC status or interrupt registers enabled.
---------------------------------------------------------------------------
NO_ECC_STATUS_REGISTERS : if not C_HAS_ECC_STATUS_REGISTERS generate
begin
ECC_EnableIRQReg <= (others => '0');
ECC_StatusReg <= (others => '0');
Interrupt <= '0';
ECC_UE <= '0';
end generate NO_ECC_STATUS_REGISTERS;
---------------------------------------------------------------------------
-- Generate: GEN_ECC_ONOFF
-- Purpose: Implement ECC on/off control register.
---------------------------------------------------------------------------
GEN_ECC_ONOFF : if C_HAS_ECC_ONOFF generate
begin
ECC_OnOffReg_WE <= '1' when (RegWr = '1' and RegAddr = C_ECC_OnOffReg) else '0';
EnableIRQReg : process(S_AXI_AClk) is
begin
if S_AXI_AClk'event and S_AXI_AClk = '1' then
if S_AXI_AResetn = C_RESET_ACTIVE then
if (C_ECC_ONOFF_RESET_VALUE = 0) then
ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '0';
else
ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '1';
end if;
-- ECC on by default at reset (but can be disabled)
elsif ECC_OnOffReg_WE = '1' then
ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= RegWrData(32-C_ECC_ON_OFF_WIDTH);
end if;
end if;
end process EnableIRQReg;
Enable_ECC_i <= ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH);
Enable_ECC <= Enable_ECC_i;
end generate GEN_ECC_ONOFF;
---------------------------------------------------------------------------
-- Generate: GEN_NO_ECC_ONOFF
-- Purpose: No ECC on/off control register.
---------------------------------------------------------------------------
GEN_NO_ECC_ONOFF : if not C_HAS_ECC_ONOFF generate
begin
Enable_ECC <= '0';
-- ECC ON/OFF register is only enabled when C_ECC = 1.
-- If C_ECC = 0, then no ECC on/off register (C_HAS_ECC_ONOFF = 0) then
-- ECC should be disabled.
ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '0';
end generate GEN_NO_ECC_ONOFF;
---------------------------------------------------------------------------
-- Generate: CE_COUNTER
-- Purpose: Enable Correctable Error Counter
-- Fixed to size of C_CE_COUNTER_WIDTH = 8 bits.
-- Parameterized here for future enhancements.
---------------------------------------------------------------------------
CE_COUNTER : if C_HAS_CE_COUNTER generate
-- One extra bit compare to CE_CounterReg to handle carry bit
signal CE_CounterReg_plus_1 : std_logic_vector(31-C_CE_COUNTER_WIDTH to 31);
begin
CE_CounterReg_WE <= '1' when (RegWr = '1' and RegAddr = C_CE_CounterReg) else '0';
-- TBD (could come from axi_lite)
-- CE_CounterReg_Inc <= '1' when (Sl_CE_i = '1' and Sl_Ready_i = '1' and
-- CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0')
-- else '0';
CE_CounterReg_Inc_i <= '1' when (CE_CounterReg_Inc = '1' and
CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0')
else '0';
CountReg : process(S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
CE_CounterReg <= (others => '0');
elsif CE_CounterReg_WE = '1' then
-- CE_CounterReg <= RegWrData(0 to C_DWIDTH-1);
CE_CounterReg <= RegWrData(32-C_CE_COUNTER_WIDTH to 31);
elsif CE_CounterReg_Inc_i = '1' then
CE_CounterReg <= CE_CounterReg_plus_1(32-C_CE_COUNTER_WIDTH to 31);
end if;
end if;
end process CountReg;
CE_CounterReg_plus_1 <= std_logic_vector(unsigned(('0' & CE_CounterReg)) + 1);
end generate CE_COUNTER;
-- Note: Hit this generate when C_ECC = 0.
-- Reserve for future support.
--
-- ---------------------------------------------------------------------------
-- -- Generate: NO_CE_COUNTER
-- -- Purpose: Default for no CE counter register.
-- ---------------------------------------------------------------------------
--
-- NO_CE_COUNTER : if not C_HAS_CE_COUNTER generate
-- begin
-- CE_CounterReg <= (others => '0');
-- end generate NO_CE_COUNTER;
---------------------------------------------------------------------------
-- Generate: GEN_REG_32_DATA
-- Purpose: Generate read register values & signal assignments based on
-- 32-bit BRAM data width.
---------------------------------------------------------------------------
GEN_REG_32_DATA: if C_S_AXI_DATA_WIDTH = 32 generate
begin
SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg,
CE_CounterReg, CE_FailingAddress,
FaultInjectData_i,
FaultInjectECC_i
-- CE_FailingData, CE_FailingECC,
-- UE_FailingAddress, UE_FailingData, UE_FailingECC
)
begin
RegRdData <= (others => '0');
case RegAddr is
-- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment
when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg;
when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg;
when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg;
when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg;
when C_CE_FailingAddress_31_0 => RegRdData(CE_FailingAddress'range) <= CE_FailingAddress;
when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- Temporary addition to readback fault inject register values
when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31);
when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1);
-- Note: For future enhancement.
-- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- CE_FailingData (0 to 31);
-- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= (others => '0'); -- CE_FailingECC;
-- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- UE_FailingAddress (0 to 31);
-- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- UE_FailingData (0 to 31);
-- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= (others => '0'); -- UE_FailingECC;
when others => RegRdData <= (others => '0');
end case;
end process SelRegRdData;
end generate GEN_REG_32_DATA;
---------------------------------------------------------------------------
-- Generate: GEN_REG_64_DATA
-- Purpose: Generate read register values & signal assignments based on
-- 64-bit BRAM data width.
---------------------------------------------------------------------------
GEN_REG_64_DATA: if C_S_AXI_DATA_WIDTH = 64 generate
begin
SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg,
CE_CounterReg, CE_FailingAddress,
FaultInjectData_i,
FaultInjectECC_i
-- CE_FailingData, CE_FailingECC,
-- UE_FailingAddress, UE_FailingData, UE_FailingECC
)
begin
RegRdData <= (others => '0');
case RegAddr is
-- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment
when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg;
when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg;
when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg;
when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg;
when C_CE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= CE_FailingAddress (0 to 31);
when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- Temporary addition to readback fault inject register values
when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31);
when C_FaultInjectData_63_32 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (32 to 63);
when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1);
-- Note: For future enhancement.
-- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (32 to 63);
-- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (0 to 31);
-- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC;
-- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingAddress (0 to 31);
-- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingData (32 to 63);
-- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (0 to 31);
-- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC;
when others => RegRdData <= (others => '0');
end case;
end process SelRegRdData;
end generate GEN_REG_64_DATA;
---------------------------------------------------------------------------
-- Generate: GEN_REG_128_DATA
-- Purpose: Generate read register values & signal assignments based on
-- 128-bit BRAM data width.
---------------------------------------------------------------------------
GEN_REG_128_DATA: if C_S_AXI_DATA_WIDTH = 128 generate
begin
SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg,
CE_CounterReg, CE_FailingAddress,
FaultInjectData_i,
FaultInjectECC_i
-- CE_FailingData, CE_FailingECC,
-- UE_FailingAddress, UE_FailingData, UE_FailingECC
)
begin
RegRdData <= (others => '0');
case RegAddr is
-- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment
when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg;
when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg;
when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg;
when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg;
when C_CE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= CE_FailingAddress (0 to 31);
when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- Temporary addition to readback fault inject register values
when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31);
when C_FaultInjectData_63_32 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (32 to 63);
when C_FaultInjectData_95_64 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (64 to 95);
when C_FaultInjectData_127_96 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (96 to 127);
when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1);
-- Note: For future enhancement.
-- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (96 to 127);
-- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (64 to 95);
-- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (32 to 63);
-- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (0 to 31);
-- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC;
-- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingAddress (0 to 31);
-- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingData (96 to 127);
-- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (64 to 95);
-- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (32 to 63);
-- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (0 to 31);
-- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC;
when others => RegRdData <= (others => '0');
end case;
end process SelRegRdData;
end generate GEN_REG_128_DATA;
---------------------------------------------------------------------------
end architecture implementation;
| bsd-2-clause | 7dedadd350ad0d5b8adc106210e16c93 | 0.468521 | 4.23204 | false | false | false | false |
Nibble-Knowledge/peripheral-ethernet | vhdl-serial/periph2cpu.vhd | 1 | 3,381 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:56:24 02/27/2016
-- Design Name:
-- Module Name: periph2cpu - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity periph2cpu is
Port ( clk_cpu : in STD_LOGIC;
reset : in STD_LOGIC;
in_meminuse : in STD_LOGIC;
cpu_read : in STD_LOGIC;
curmem : in STD_LOGIC_VECTOR (14 downto 0);
ram_data : in STD_LOGIC_VECTOR (7 downto 0);
cpu_ready : out STD_LOGIC;
out_meminuse : out STD_LOGIC;
cpu_data : out STD_LOGIC_VECTOR (3 downto 0);
ram_addr : out STD_LOGIC_VECTOR (14 downto 0);
debug : out std_logic);
end periph2cpu;
architecture Behavioral of periph2cpu is
signal cpumem : integer;
signal buff : std_logic_vector(7 downto 0);
type PERIPHSTATE is (NODATA, GETDATA, WAIT2MSB, TXMSB, WAIT2LSB, TXLSB);
signal CurrState : PERIPHSTATE;
signal debug_internal : std_logic;
begin
process(clk_cpu,reset)
begin
if reset = '1' then
CurrState <= NODATA;
cpumem <= 0;
cpu_ready <= '0';
out_meminuse <= '0';
cpu_data <= (others => '0');
debug_internal <= '0';
elsif rising_edge(clk_cpu) then
case CurrState is
when NODATA => --wait until cpumem != curmem and memory is not in use
debug_internal <= not debug_internal;
if cpumem /= to_integer(unsigned(curmem)) and in_meminuse = '0' then
CurrState <= GETDATA;
out_meminuse <= '1';
end if;
when GETDATA => --data should be waiting in ram_data, so copy it to the buffer
buff <= ram_data;
CurrState <= WAIT2MSB;
cpumem <= cpumem + 1;
--don't let go of memory just yet so we can have enough time to copy data into buffer
when WAIT2MSB => --wait for CPU to request a read
out_meminuse <= '0'; --we can release memory
if cpu_read = '1' then
cpu_ready <= '1';
cpu_data <= buff(7 downto 4);
CurrState <= TXMSB;
end if;
when TXMSB => --keep transmitting until cpu_read goes low
if cpu_read = '0' then
cpu_ready <= '0';
cpu_data <= (others => '0');
CurrState <= WAIT2LSB;
end if;
when WAIT2LSB => --wait for CPU to request a read
if cpu_read = '1' then
cpu_ready <= '1';
cpu_data <= buff(3 downto 0);
CurrState <= TXLSB;
end if;
when TXLSB => --keep transmitting until cpu_read goes low
if cpu_read = '0' then
cpu_ready <= '0';
cpu_data <= (others => '0');
CurrState <= NODATA;
end if;
end case;
end if;
end process;
--Do not write directly to these registers
ram_addr <= std_logic_vector(to_unsigned(cpumem, ram_addr'length));
debug <= debug_internal;
end Behavioral;
| unlicense | 5084cac94f25bc16524965be3674032d | 0.583555 | 3.418605 | false | false | false | false |
Yarr/Yarr-fw | rtl/tx-core/trigger_unit.vhd | 1 | 7,386 | -- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: Trigger Logic
-- ####################################
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity trigger_unit is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Serial Trigger Out
--trig_o : out std_logic;
trig_pulse_o : out std_logic;
-- Trigger In
ext_trig_i : in std_logic;
-- Config
--trig_word_i : in std_logic_vector(127 downto 0); -- Trigger command
--trig_word_length_i : in std_logic_vector(31 downto 0);
trig_freq_i : in std_logic_vector(31 downto 0); -- Number of clock cycles between triggers
trig_time_i : in std_logic_vector(63 downto 0); -- Clock cycles
trig_count_i : in std_logic_vector(31 downto 0); -- Fixed number of triggers
trig_conf_i : in std_logic_vector(3 downto 0); -- Internal, external, pseudo random,
trig_en_i : in std_logic;
trig_abort_i : in std_logic;
trig_done_o : out std_logic
);
end trigger_unit;
architecture Behavioral of trigger_unit is
-- Signals
signal bit_count : unsigned(7 downto 0);
signal sreg : std_logic_vector(127 downto 0);
signal trig_pulse : std_logic;
-- Registers
signal trig_word : std_logic_vector(127 downto 0);
signal trig_word_length : std_logic_vector(31 downto 0);
signal trig_freq : std_logic_vector(31 downto 0);
signal trig_time : std_logic_vector(63 downto 0);
signal trig_count : std_logic_vector(31 downto 0);
signal trig_conf : stD_logic_vector(3 downto 0);
signal trig_en : std_logic;
constant c_DONE_DELAY : integer := 32;
signal trig_done : std_logic_vector(c_DONE_DELAY-1 downto 0);
-- Counters
signal stopwatch_cnt : unsigned(63 downto 0);
signal int_trig_cnt : unsigned(31 downto 0);
signal freq_cnt : unsigned(31 downto 0);
-- Sync
signal trig_en_d0 : std_logic;
signal trig_en_d1 : std_logic;
signal trig_en_pos : std_logic;
signal trig_en_neg : std_logic;
signal ext_trig_d0 : std_logic;
signal ext_trig_d1 : std_logic;
signal ext_trig_d2 : std_logic;
signal ext_trig_d3 : std_logic;
signal ext_trig_d4 : std_logic;
signal ext_trig_pos : std_logic;
constant c_DEADTIME : integer := 10; -- Deadtime moved to trigger logic
signal deadtime : unsigned(7 downto 0);
begin
-- Done conditions
done_proc : process(clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
trig_done(0) <= '0';
elsif rising_edge(clk_i) then
if (trig_en = '0') then -- Reset done on disable
trig_done(0) <= '0';
elsif (trig_abort_i = '1') then -- Abort triggering
trig_done(0) <= '1';
elsif (trig_conf = x"0") then -- External, abot will set done
--trig_done(0) <= '0';
elsif (trig_conf = x"1") then -- Internal time
if (stopwatch_cnt = unsigned(trig_time)) then
trig_done(0) <= '1';
end if;
elsif (trig_conf = x"2") then -- Internal count
if (int_trig_cnt = unsigned(trig_count)) then
trig_done(0) <= '1';
end if;
--elsif (trig_conf = x"3") then -- Pseudo Random
else -- unknown conf
trig_done(0) <= '1';
end if;
end if;
end process done_proc;
-- Stopwatch
stopwatch_proc : process (clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
stopwatch_cnt <= (others => '0');
elsif rising_edge(clk_i) then
if (trig_done(0) = '1') then
stopwatch_cnt <= (others => '0');
elsif (trig_en = '1') then
stopwatch_cnt <= stopwatch_cnt + 1;
end if;
end if;
end process stopwatch_proc;
-- Trigger count
int_trig_cnt_proc : process (clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
int_trig_cnt <= (others => '0');
elsif rising_edge(clk_i) then
if (trig_done(0) = '1') then
int_trig_cnt <= (others => '0');
elsif (trig_en = '1' and trig_pulse = '1') then
int_trig_cnt <= int_trig_cnt + 1;
end if;
end if;
end process int_trig_cnt_proc;
-- Trigger Pulser
trig_pulse_o <= trig_pulse;
trig_pulse_proc : process(clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
trig_pulse <= '0';
freq_cnt <= (others => '0');
elsif rising_edge(clk_i) then
if (trig_conf = x"0") then -- Pusling on External rising edge
if (trig_en = '1' and ext_trig_pos = '1' and trig_done(0) = '0') then
trig_pulse <= '1';
else
trig_pulse <= '0';
end if;
else -- Pulsing on requency counter
if (trig_done(0) = '1') then
trig_pulse <= '0';
freq_cnt <= (others => '0');
elsif (trig_en = '1') then
if (freq_cnt = unsigned(trig_freq)) then
freq_cnt <= (others => '0');
trig_pulse <= '1';
else
freq_cnt <= freq_cnt + 1;
trig_pulse <= '0';
end if;
end if;
end if;
end if;
end process trig_pulse_proc;
-- Tie offs
-- trig_o <= sreg(127);
-- -- Serializer proc
-- serialize: process(clk_i, rst_n_i)
-- begin
-- if (rst_n_i = '0') then
-- sreg <= (others => '0');
-- bit_count <= (others => '0');
-- elsif rising_edge(clk_i) then
-- if (trig_pulse = '1') then
-- sreg <= trig_word;
-- bit_count <= (others => '0');
---- elsif (bit_count <= unsigned(trig_word_length(7 downto 0))) then
-- else
-- sreg <= sreg(126 downto 0) & '0';
---- bit_count <= bit_count + 1;
---- else
---- sreg <= (others => '0');
-- end if;
-- end if;
-- end process serialize;
-- Sync proc
sync_proc : process (clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
--trig_word <= (others => '0');
--trig_word_length <= (others => '0');
trig_freq <= (others => '0');
trig_time <= (others => '0');
trig_count <= (others => '0');
trig_conf <= (others => '0');
trig_en <= '0';
trig_done_o <= '0';
trig_done(c_DONE_DELAY-1 downto 1) <= (others => '0');
ext_trig_d0 <= '0';
ext_trig_d1 <= '0';
ext_trig_d2 <= '0';
ext_trig_d3 <= '0';
ext_trig_d4 <= '0';
ext_trig_pos <= '0';
trig_en_d0 <= '0';
trig_en_d1 <= '0';
trig_en_pos <= '0';
trig_en_neg <= '0';
deadtime <= (others => '0');
elsif rising_edge(clk_i) then
ext_trig_d0 <= ext_trig_i; -- async input
ext_trig_d1 <= ext_trig_d0;
ext_trig_d2 <= ext_trig_d1;
ext_trig_d3 <= ext_trig_d2;
ext_trig_d4 <= ext_trig_d3;
-- Triggered on pos edge of external signal and high longer than 25ns
if (ext_trig_d4 = '0' and ext_trig_d3 = '1' and deadtime = 0) then
ext_trig_pos <= '1';
deadtime <= to_unsigned(c_DEADTIME, 8);
else
ext_trig_pos <= '0';
end if;
trig_en_d0 <= trig_en_i;
trig_en_d1 <= trig_en_d0;
if (trig_en_d1 = '0' and trig_en_d0 = '1') then
trig_en_pos <= '1';
trig_en_neg <= '0';
elsif (trig_en_d1 = '1' and trig_en_d0 = '0') then
trig_en_pos <= '0';
trig_en_neg <= '1';
else
trig_en_neg <= '0';
trig_en_pos <= '0';
end if;
if (trig_en_pos = '1') then
--trig_word <= trig_word_i;
--trig_word_length <= trig_word_length_i;
trig_freq <= trig_freq_i;
trig_time <= trig_time_i;
trig_count <= trig_count_i;
trig_conf <= trig_conf_i;
trig_en <= '1';
elsif (trig_en_neg = '1') then
trig_en <= '0';
end if;
for I in 1 to c_DONE_DELAY-1 loop
trig_done(I) <= trig_done(I-1);
end loop;
trig_done_o <= trig_done(c_DONE_DELAY-1);
if (deadtime > 0) then
deadtime <= deadtime - 1;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 6ec402859f27bfb7ae94edca780b9b75 | 0.572841 | 2.667389 | false | false | false | false |
zcold/fft.vhdl | src/cbf_slv.vhdl | 1 | 5,130 | -- The MIT License (MIT)
-- Copyright (c) 2014 Shuo Li
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
----------------------
-- clocked butterfly operation
----------------------
-- Description
-- This design unit `cbf` is for performing clocked butterfly operation on complex
-- fixed point numbers with configurable data width. The value of the inputs are
-- limited to (+1, -1]. MSB is sign bit and the rest bits are all decimal part.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ieee_proposed;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
entity cbf_slv is
generic (
-- data width of the real and imaginary part
data_width : integer range 0 to 128 := 16
);
port (
-- clock
clk : in std_logic;
nrst : in std_logic;
-- x0, input 0
x0_re : in std_logic_vector (data_width - 1 downto 0);
x0_im : in std_logic_vector (data_width - 1 downto 0);
-- x1, input 1
x1_re : in std_logic_vector (data_width - 1 downto 0);
x1_im : in std_logic_vector (data_width - 1 downto 0);
-- wk, twiddle factor
wk_re : in std_logic_vector (data_width - 1 downto 0);
wk_im : in std_logic_vector (data_width - 1 downto 0);
-- y0, output 0
y0_re : out std_logic_vector (data_width - 1 downto 0);
y0_im : out std_logic_vector (data_width - 1 downto 0);
-- y1, output 1
y1_re : out std_logic_vector (data_width - 1 downto 0);
y1_im : out std_logic_vector (data_width - 1 downto 0)
);
end cbf_slv;
-- Function Implementation 0
architecture FIMP_0 of cbf_slv is
component cbf is
generic (
-- data width of the real and imaginary part
data_width : integer range 0 to 128 := 16
);
port (
-- clock
clk : in std_logic;
nrst : in std_logic;
-- x0, input 0
x0_re : in sfixed (0 downto 1 - data_width);
x0_im : in sfixed (0 downto 1 - data_width);
-- x1, input 1
x1_re : in sfixed (0 downto 1 - data_width);
x1_im : in sfixed (0 downto 1 - data_width);
-- wk, twiddle factor
wk_re : in sfixed (0 downto 1 - data_width);
wk_im : in sfixed (0 downto 1 - data_width);
-- y0, output 0
y0_re : out sfixed(0 downto 1 - data_width);
y0_im : out sfixed(0 downto 1 - data_width);
-- y1, output 1
y1_re : out sfixed(0 downto 1 - data_width);
y1_im : out sfixed(0 downto 1 - data_width)
);
end component;
-- internal signals for x
signal x0_re_int : sfixed (0 downto 1 - data_width);
signal x0_im_int : sfixed (0 downto 1 - data_width);
signal x1_re_int : sfixed (0 downto 1 - data_width);
signal x1_im_int : sfixed (0 downto 1 - data_width);
-- internal signals for twiddle factor
signal wk_re_int : sfixed (0 downto 1 - data_width);
signal wk_im_int : sfixed (0 downto 1 - data_width);
-- internal signals for output
signal y0_re_int : sfixed (0 downto 1 - data_width);
signal y0_im_int : sfixed (0 downto 1 - data_width);
signal y1_re_int : sfixed (0 downto 1 - data_width);
signal y1_im_int : sfixed (0 downto 1 - data_width);
begin
-- convert input std_logic_vector to signed fixed point
x0_re_int <= to_sfixed(x0_re, 0, 1 - data_width);
x0_im_int <= to_sfixed(x0_im, 0, 1 - data_width);
x1_re_int <= to_sfixed(x1_re, 0, 1 - data_width);
x1_im_int <= to_sfixed(x1_im, 0, 1 - data_width);
wk_re_int <= to_sfixed(wk_re, 0, 1 - data_width);
wk_im_int <= to_sfixed(wk_im, 0, 1 - data_width);
-- convert output signed fixed point to std_logic_vector
y0_re <= to_slv(y0_re_int);
y0_im <= to_slv(y0_im_int);
y1_re <= to_slv(y1_re_int);
y1_im <= to_slv(y1_im_int);
cbf_0: cbf
generic map (data_width)
port map(clk, nrst,
x0_re_int, x0_im_int,
x1_re_int, x1_im_int,
wk_re_int, wk_im_int,
y0_re_int, y0_im_int,
y1_re_int, y1_im_int);
end FIMP_0;
| mit | 3dc365005b0b49387d67c7d840712411 | 0.619883 | 3.352941 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_dma_v7_1/hdl/src/vhdl/axi_dma_pkg.vhd | 1 | 23,655 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_pkg.vhd
-- Description: This package contains various constants and functions for
-- AXI DMA operations.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
package axi_dma_pkg is
-------------------------------------------------------------------------------
-- Function declarations
-------------------------------------------------------------------------------
-- Find minimum required btt width
function required_btt_width (dwidth : integer;
burst_size : integer;
btt_width : integer)
return integer;
-- Return correct hertz paramter value
function hertz_prmtr_select(included : integer;
lite_frequency : integer;
sg_frequency : integer)
return integer;
-- Return SnF enable or disable
function enable_snf (sf_enabled : integer;
axi_data_width : integer;
axis_tdata_width : integer)
return integer;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AXI Responce Values
-------------------------------------------------------------------------------
constant OKAY_RESP : std_logic_vector(1 downto 0) := "00";
constant EXOKAY_RESP : std_logic_vector(1 downto 0) := "01";
constant SLVERR_RESP : std_logic_vector(1 downto 0) := "10";
constant DECERR_RESP : std_logic_vector(1 downto 0) := "11";
constant MTBF_STAGES : integer := 4;
constant C_FIFO_MTBF : integer := 4;
-------------------------------------------------------------------------------
-- Misc Constants
-------------------------------------------------------------------------------
--constant NUM_REG_TOTAL : integer := 18;
--constant NUM_REG_TOTAL : integer := 23;
constant NUM_REG_TOTAL : integer := 143; -- To accomodate S2MM registers
--constant NUM_REG_PER_CHANNEL : integer := 6;
constant NUM_REG_PER_CHANNEL : integer := 12;
constant NUM_REG_PER_S2MM : integer := 120;
--constant REG_MSB_ADDR_BIT : integer := clog2(NUM_REG_TOTAL)-1;
constant CMD_BASE_WIDTH : integer := 40;
constant BUFFER_LENGTH_WIDTH : integer := 23;
-- Constants Used in Desc Updates
constant DESC_STS_TYPE : std_logic := '1';
constant DESC_DATA_TYPE : std_logic := '0';
constant DESC_LAST : std_logic := '1';
constant DESC_NOT_LAST : std_logic := '0';
-- Interrupt Coalescing
constant ZERO_THRESHOLD : std_logic_vector(7 downto 0) := (others => '0');
constant ONE_THRESHOLD : std_logic_vector(7 downto 0) := "00000001";
constant ZERO_DELAY : std_logic_vector(7 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- AXI Lite AXI DMA Register Offsets
-------------------------------------------------------------------------------
constant MM2S_DMACR_INDEX : integer := 0;
constant MM2S_DMASR_INDEX : integer := 1;
constant MM2S_CURDESC_LSB_INDEX : integer := 2;
constant MM2S_CURDESC_MSB_INDEX : integer := 3;
constant MM2S_TAILDESC_LSB_INDEX : integer := 4;
constant MM2S_TAILDESC_MSB_INDEX : integer := 5;
constant MM2S_SA_INDEX : integer := 6;
constant RESERVED_1C_INDEX : integer := 7;
constant RESERVED_20_INDEX : integer := 8;
constant RESERVED_24_INDEX : integer := 9;
constant MM2S_LENGTH_INDEX : integer := 10;
constant RESERVED_2C_INDEX : integer := 11;
constant S2MM_DMACR_INDEX : integer := 12;
constant S2MM_DMASR_INDEX : integer := 13;
constant S2MM_CURDESC_LSB_INDEX : integer := 14;
constant S2MM_CURDESC_MSB_INDEX : integer := 15;
constant S2MM_TAILDESC_LSB_INDEX : integer := 16;
constant S2MM_TAILDESC_MSB_INDEX : integer := 17;
constant S2MM_DA_INDEX : integer := 18;
constant RESERVED_4C_INDEX : integer := 19;
constant RESERVED_50_INDEX : integer := 20;
constant RESERVED_54_INDEX : integer := 21;
--constant S2MM_LENGTH_INDEX : integer := 22;
constant S2MM_LENGTH_INDEX : integer := 142;
constant MM2S_DMACR_OFFSET : std_logic_vector(9 downto 0) := "0000000000"; -- 0x00
constant MM2S_DMASR_OFFSET : std_logic_vector(9 downto 0) := "0000000100"; -- 0x04
constant MM2S_CURDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000001000"; -- 0x08
constant MM2S_CURDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000001100"; -- 0x0C
constant MM2S_TAILDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000010000"; -- 0x10
constant MM2S_TAILDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000010100"; -- 0x14
constant MM2S_SA_OFFSET : std_logic_vector(9 downto 0) := "0000011000"; -- 0x18
constant RESERVED_1C_OFFSET : std_logic_vector(9 downto 0) := "0000011100"; -- 0x1C
constant RESERVED_20_OFFSET : std_logic_vector(9 downto 0) := "0000100000"; -- 0x20
constant RESERVED_24_OFFSET : std_logic_vector(9 downto 0) := "0000100100"; -- 0x24
constant MM2S_LENGTH_OFFSET : std_logic_vector(9 downto 0) := "0000101000"; -- 0x28
-- Following was reserved, now is used for SG xCache and xUser
constant SGCTL_OFFSET : std_logic_vector(9 downto 0) := "0000101100"; -- 0x2C
constant S2MM_DMACR_OFFSET : std_logic_vector(9 downto 0) := "0000110000"; -- 0x30
constant S2MM_DMASR_OFFSET : std_logic_vector(9 downto 0) := "0000110100"; -- 0x34
constant S2MM_CURDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000111000"; -- 0x38
constant S2MM_CURDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000111100"; -- 0x3C
constant S2MM_TAILDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001000000"; -- 0x40
constant S2MM_TAILDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001000100"; -- 0x44
constant S2MM_DA_OFFSET : std_logic_vector(9 downto 0) := "0001001000"; -- 0x48 --CR603034
constant RESERVED_4C_OFFSET : std_logic_vector(9 downto 0) := "0001001100"; -- 0x4C
constant RESERVED_50_OFFSET : std_logic_vector(9 downto 0) := "0001010000"; -- 0x50
constant RESERVED_54_OFFSET : std_logic_vector(9 downto 0) := "0001010100"; -- 0x54
constant S2MM_LENGTH_OFFSET : std_logic_vector(9 downto 0) := "0001011000"; -- 0x58
-- New registers for S2MM channels
constant S2MM_CURDESC1_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001110000"; -- 0x70
constant S2MM_CURDESC1_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001110100"; -- 0x74
constant S2MM_TAILDESC1_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001111000"; -- 0x78
constant S2MM_TAILDESC1_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001111100"; -- 0x7C
constant S2MM_CURDESC2_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010010000"; -- 0x90
constant S2MM_CURDESC2_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010010100"; -- 0x94
constant S2MM_TAILDESC2_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010011000"; -- 0x98
constant S2MM_TAILDESC2_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010011100"; -- 0x9C
constant S2MM_CURDESC3_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010110000"; -- 0xB0
constant S2MM_CURDESC3_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010110100"; -- 0xB4
constant S2MM_TAILDESC3_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010111000"; -- 0xB8
constant S2MM_TAILDESC3_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010111100"; -- 0xBC
constant S2MM_CURDESC4_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011010000"; -- 0xD0
constant S2MM_CURDESC4_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011010100"; -- 0xD4
constant S2MM_TAILDESC4_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011011000"; -- 0xD8
constant S2MM_TAILDESC4_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011011100"; -- 0xDC
constant S2MM_CURDESC5_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011110000"; -- 0xF0
constant S2MM_CURDESC5_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011110100"; -- 0xF4
constant S2MM_TAILDESC5_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011111000"; -- 0xF8
constant S2MM_TAILDESC5_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011111100"; -- 0xFC
constant S2MM_CURDESC6_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100010000"; -- 0x110
constant S2MM_CURDESC6_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100010100"; -- 0x114
constant S2MM_TAILDESC6_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100011000"; -- 0x118
constant S2MM_TAILDESC6_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100011100"; -- 0x11C
constant S2MM_CURDESC7_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100110000"; -- 0x130
constant S2MM_CURDESC7_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100110100"; -- 0x134
constant S2MM_TAILDESC7_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100111000"; -- 0x138
constant S2MM_TAILDESC7_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100111100"; -- 0x13C
constant S2MM_CURDESC8_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101010000"; -- 0x150
constant S2MM_CURDESC8_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101010100"; -- 0x154
constant S2MM_TAILDESC8_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101011000"; -- 0x158
constant S2MM_TAILDESC8_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101011100"; -- 0x15C
constant S2MM_CURDESC9_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101110000"; -- 0x170
constant S2MM_CURDESC9_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101110100"; -- 0x174
constant S2MM_TAILDESC9_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101111000"; -- 0x178
constant S2MM_TAILDESC9_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101111100"; -- 0x17C
constant S2MM_CURDESC10_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110010000"; -- 0x190
constant S2MM_CURDESC10_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110010100"; -- 0x194
constant S2MM_TAILDESC10_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110011000"; -- 0x198
constant S2MM_TAILDESC10_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110011100"; -- 0x19C
constant S2MM_CURDESC11_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110110000"; -- 0x1B0
constant S2MM_CURDESC11_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110110100"; -- 0x1B4
constant S2MM_TAILDESC11_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110111000"; -- 0x1B8
constant S2MM_TAILDESC11_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110111100"; -- 0x1BC
constant S2MM_CURDESC12_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111010000"; -- 0x1D0
constant S2MM_CURDESC12_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111010100"; -- 0x1D4
constant S2MM_TAILDESC12_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111011000"; -- 0x1D8
constant S2MM_TAILDESC12_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111011100"; -- 0x1DC
constant S2MM_CURDESC13_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111110000"; -- 0x1F0
constant S2MM_CURDESC13_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111110100"; -- 0x1F4
constant S2MM_TAILDESC13_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111111000"; -- 0x1F8
constant S2MM_TAILDESC13_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111111100"; -- 0x1FC
constant S2MM_CURDESC14_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000010000"; -- 0x210
constant S2MM_CURDESC14_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000010100"; -- 0x214
constant S2MM_TAILDESC14_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000011000"; -- 0x218
constant S2MM_TAILDESC14_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000011100"; -- 0x21C
constant S2MM_CURDESC15_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000110000"; -- 0x230
constant S2MM_CURDESC15_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000110100"; -- 0x234
constant S2MM_TAILDESC15_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000111000"; -- 0x238
constant S2MM_TAILDESC15_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000111100"; -- 0x23C
-------------------------------------------------------------------------------
-- Register Bit Constants
-------------------------------------------------------------------------------
-- DMACR
constant DMACR_RS_BIT : integer := 0;
constant DMACR_TAILPEN_BIT : integer := 1;
constant DMACR_RESET_BIT : integer := 2;
constant DMACR_KH_BIT : integer := 3;
constant CYCLIC_BIT : integer := 4;
--constant DMACR_RESERVED3_BIT : integer := 3;
--constant DMACR_RESERVED4_BIT : integer := 4;
constant DMACR_RESERVED5_BIT : integer := 5;
constant DMACR_RESERVED6_BIT : integer := 6;
constant DMACR_RESERVED7_BIT : integer := 7;
constant DMACR_RESERVED8_BIT : integer := 8;
constant DMACR_RESERVED9_BIT : integer := 9;
constant DMACR_RESERVED10_BIT : integer := 10;
constant DMACR_RESERVED11_BIT : integer := 11;
constant DMACR_IOC_IRQEN_BIT : integer := 12;
constant DMACR_DLY_IRQEN_BIT : integer := 13;
constant DMACR_ERR_IRQEN_BIT : integer := 14;
constant DMACR_RESERVED15_BIT : integer := 15;
constant DMACR_IRQTHRESH_LSB_BIT : integer := 16;
constant DMACR_IRQTHRESH_MSB_BIT : integer := 23;
constant DMACR_IRQDELAY_LSB_BIT : integer := 24;
constant DMACR_IRQDELAY_MSB_BIT : integer := 31;
-- DMASR
constant DMASR_HALTED_BIT : integer := 0;
constant DMASR_IDLE_BIT : integer := 1;
constant DMASR_CMPLT_BIT : integer := 2;
constant DMASR_ERROR_BIT : integer := 3;
constant DMASR_DMAINTERR_BIT : integer := 4;
constant DMASR_DMASLVERR_BIT : integer := 5;
constant DMASR_DMADECERR_BIT : integer := 6;
constant DMASR_RESERVED7_BIT : integer := 7;
constant DMASR_SGINTERR_BIT : integer := 8;
constant DMASR_SGSLVERR_BIT : integer := 9;
constant DMASR_SGDECERR_BIT : integer := 10;
constant DMASR_RESERVED11_BIT : integer := 11;
constant DMASR_IOCIRQ_BIT : integer := 12;
constant DMASR_DLYIRQ_BIT : integer := 13;
constant DMASR_ERRIRQ_BIT : integer := 14;
constant DMASR_RESERVED15_BIT : integer := 15;
constant DMASR_IRQTHRESH_LSB_BIT : integer := 16;
constant DMASR_IRQTHRESH_MSB_BIT : integer := 23;
constant DMASR_IRQDELAY_LSB_BIT : integer := 24;
constant DMASR_IRQDELAY_MSB_BIT : integer := 31;
-- CURDESC
constant CURDESC_LOWER_MSB_BIT : integer := 31;
constant CURDESC_LOWER_LSB_BIT : integer := 6;
constant CURDESC_RESERVED_BIT5 : integer := 5;
constant CURDESC_RESERVED_BIT4 : integer := 4;
constant CURDESC_RESERVED_BIT3 : integer := 3;
constant CURDESC_RESERVED_BIT2 : integer := 2;
constant CURDESC_RESERVED_BIT1 : integer := 1;
constant CURDESC_RESERVED_BIT0 : integer := 0;
-- TAILDESC
constant TAILDESC_LOWER_MSB_BIT : integer := 31;
constant TAILDESC_LOWER_LSB_BIT : integer := 6;
constant TAILDESC_RESERVED_BIT5 : integer := 5;
constant TAILDESC_RESERVED_BIT4 : integer := 4;
constant TAILDESC_RESERVED_BIT3 : integer := 3;
constant TAILDESC_RESERVED_BIT2 : integer := 2;
constant TAILDESC_RESERVED_BIT1 : integer := 1;
constant TAILDESC_RESERVED_BIT0 : integer := 0;
-- DataMover Command / Status Constants
constant DATAMOVER_CMDDONE_BIT : integer := 7;
constant DATAMOVER_SLVERR_BIT : integer := 6;
constant DATAMOVER_DECERR_BIT : integer := 5;
constant DATAMOVER_INTERR_BIT : integer := 4;
constant DATAMOVER_TAGMSB_BIT : integer := 3;
constant DATAMOVER_TAGLSB_BIT : integer := 0;
-- Descriptor Control Bits
constant DESC_BLENGTH_LSB_BIT : integer := 0;
constant DESC_BLENGTH_MSB_BIT : integer := 22;
constant DESC_RSVD23_BIT : integer := 23;
constant DESC_RSVD24_BIT : integer := 24;
constant DESC_RSVD25_BIT : integer := 25;
constant DESC_EOF_BIT : integer := 26;
constant DESC_SOF_BIT : integer := 27;
constant DESC_RSVD28_BIT : integer := 28;
constant DESC_RSVD29_BIT : integer := 29;
constant DESC_RSVD30_BIT : integer := 30;
constant DESC_IOC_BIT : integer := 31;
-- Descriptor Status Bits
constant DESC_STS_CMPLTD_BIT : integer := 31;
constant DESC_STS_DECERR_BIT : integer := 30;
constant DESC_STS_SLVERR_BIT : integer := 29;
constant DESC_STS_INTERR_BIT : integer := 28;
constant DESC_STS_RXSOF_BIT : integer := 27;
constant DESC_STS_RXEOF_BIT : integer := 26;
constant DESC_STS_RSVD25_BIT : integer := 25;
constant DESC_STS_RSVD24_BIT : integer := 24;
constant DESC_STS_RSVD23_BIT : integer := 23;
constant DESC_STS_XFRDBYTS_MSB_BIT : integer := 22;
constant DESC_STS_XFRDBYTS_LSB_BIT : integer := 0;
-- DataMover Command / Status Constants
constant DATAMOVER_STS_CMDDONE_BIT : integer := 7;
constant DATAMOVER_STS_SLVERR_BIT : integer := 6;
constant DATAMOVER_STS_DECERR_BIT : integer := 5;
constant DATAMOVER_STS_INTERR_BIT : integer := 4;
constant DATAMOVER_STS_TAGMSB_BIT : integer := 3;
constant DATAMOVER_STS_TAGLSB_BIT : integer := 0;
constant DATAMOVER_STS_TAGEOF_BIT : integer := 1;
constant DATAMOVER_STS_TLAST_BIT : integer := 31;
constant DATAMOVER_CMD_BTTLSB_BIT : integer := 0;
constant DATAMOVER_CMD_BTTMSB_BIT : integer := 22;
constant DATAMOVER_CMD_TYPE_BIT : integer := 23;
constant DATAMOVER_CMD_DSALSB_BIT : integer := 24;
constant DATAMOVER_CMD_DSAMSB_BIT : integer := 29;
constant DATAMOVER_CMD_EOF_BIT : integer := 30;
constant DATAMOVER_CMD_DRR_BIT : integer := 31;
constant DATAMOVER_CMD_ADDRLSB_BIT : integer := 32;
-- Note: Bit offset require adding ADDR WIDTH to get to actual bit index
constant DATAMOVER_CMD_ADDRMSB_BOFST: integer := 31;
constant DATAMOVER_CMD_TAGLSB_BOFST : integer := 32;
constant DATAMOVER_CMD_TAGMSB_BOFST : integer := 35;
constant DATAMOVER_CMD_RSVLSB_BOFST : integer := 36;
constant DATAMOVER_CMD_RSVMSB_BOFST : integer := 39;
end axi_dma_pkg;
-------------------------------------------------------------------------------
-- PACKAGE BODY
-------------------------------------------------------------------------------
package body axi_dma_pkg is
-------------------------------------------------------------------------------
-- Function to determine minimum bits required for BTT_SIZE field
-------------------------------------------------------------------------------
function required_btt_width ( dwidth : integer;
burst_size: integer;
btt_width : integer)
return integer is
variable min_width : integer;
begin
min_width := clog2((dwidth/8)*burst_size)+1;
if(min_width > btt_width)then
return min_width;
else
return btt_width;
end if;
end function required_btt_width;
-------------------------------------------------------------------------------
-- function to return Frequency Hertz parameter based on inclusion of sg engine
-------------------------------------------------------------------------------
function hertz_prmtr_select(included : integer;
lite_frequency : integer;
sg_frequency : integer)
return integer is
begin
-- 1 = Scatter Gather Included
-- 0 = Scatter Gather Excluded
if(included = 1)then
return sg_frequency;
else
return lite_frequency;
end if;
end;
-------------------------------------------------------------------------------
-- function to enable store and forward based on data width mismatch
-- or directly enabled
-------------------------------------------------------------------------------
function enable_snf (sf_enabled : integer;
axi_data_width : integer;
axis_tdata_width : integer)
return integer is
begin
-- If store and forward enable or data widths do not
-- match then return 1 to enable snf
if( (sf_enabled = 1) or (axi_data_width /= axis_tdata_width))then
return 1;
else
return 0;
end if;
end;
end package body axi_dma_pkg;
| bsd-2-clause | b941cca007be1f365722840b23edf784 | 0.600888 | 3.744065 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/comment/rule_100_test_input.vhd | 1 | 252 | --
-- This should pass
--| This should pass
----------This should pass
--==================
--This should fail
--|This should fail
----------This should pass
--
--==================
--¨
-- pragmas should be ignored
--vhdl_comp_off
--vhdl_comp_on
| gpl-3.0 | b9e97baaddbedd921e3ea65f7e1b8ce8 | 0.505976 | 3.691176 | false | false | false | false |
NicoLedwith/Dr.AluOpysel | RAT_MCU/FlagReg.vhd | 1 | 1,372 | ------------------------------------------------------------------------------
-- Company: RAT Technologies
-- Engineer: James Ratner
--
-- Create Date: 13:55:34 04/06/2014
-- Design Name:
-- Module Name: Mux - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Full featured D Flip-flop intended for use as flag register.
--
-- Dependencies:
--
-- Revision: 3.0
-- Revision 0.01 - File Created
-- Additional Comments:
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FlagReg is
Port ( D : in STD_LOGIC; --flag input
LD : in STD_LOGIC; --load Q with the D value
SET : in STD_LOGIC; --set the flag to '1'
CLR : in STD_LOGIC; --clear the flag to '0'
CLK : in STD_LOGIC; --system clock
Q : out STD_LOGIC); --flag output
end FlagReg;
architecture Behavioral of FlagReg is
signal s_D : STD_LOGIC := '0';
begin
process(CLK,LD,SET,CLR,D,s_D)
begin
if( rising_edge(CLK) ) then
if( LD = '1' ) then
s_D <= D;
elsif( SET = '1' ) then
s_D <= '1';
elsif( CLR = '1' ) then
s_D <= '0';
end if;
end if;
end process;
Q <= s_D;
end Behavioral;
| mit | 07f8972b9f522f0c902297d38abe1534 | 0.472303 | 3.658667 | false | false | false | false |
Yarr/Yarr-fw | rtl/kintex7/rx-core/aurora_rx_lane.vhd | 1 | 21,884 | -- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: RX lane
-- # Aurora style single rx lane
-- ####################################
-- # RX STATUS:
-- # [0] -> Sync
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim ;
use unisim.vcomponents.all ;
library work;
use work.board_pkg.all;
entity aurora_rx_lane is
port (
-- Sys connect
rst_n_i : in std_logic;
clk_rx_i : in std_logic;
clk_serdes_i : in std_logic;
-- Input
rx_data_i_p : in std_logic;
rx_data_i_n : in std_logic;
rx_polarity_i : in std_logic;
-- Output
rx_data_o : out std_logic_vector(63 downto 0);
rx_header_o : out std_logic_vector(1 downto 0);
rx_valid_o : out std_logic;
rx_stat_o : out std_logic_vector(7 downto 0)
);
end aurora_rx_lane;
architecture behavioral of aurora_rx_lane is
component serdes_1_to_468_idelay_ddr
generic (
S : integer := 8 ; -- Set the serdes factor to 4, 6 or 8
D : integer := 1 ; -- Set the number of inputs
CLKIN_PERIOD : real := 3.2 ; -- clock period (ns) of input clock on clkin_p
REF_FREQ : real := 300.0 ; -- Parameter to set reference frequency used by idelay controller
HIGH_PERFORMANCE_MODE : string := "TRUE" ; -- Parameter to set HIGH_PERFORMANCE_MODE of input delays to reduce jitter
DATA_FORMAT : string := "PER_CLOCK" -- Used to determine method for mapping input parallel word to output serial words
);
port (
datain_p : in std_logic_vector(D-1 downto 0) ; -- Input from LVDS receiver pin
datain_n : in std_logic_vector(D-1 downto 0) ; -- Input from LVDS receiver pin
enable_phase_detector : in std_logic ; -- Enables the phase detector logic when high
enable_monitor : in std_logic ; -- Enables the monitor logic when high, note time-shared with phase detector function
reset : in std_logic ; -- Reset line
bitslip : in std_logic ; -- bitslip
idelay_rdy : in std_logic ; -- input delays are ready
rxclk : in std_logic ; -- Global/BUFIO rx clock network
system_clk : in std_logic ; -- Global/Regional clock output
rx_lckd : out std_logic ; --
rx_data : out std_logic_vector((S*D)-1 downto 0) ; -- Output data
bit_rate_value : in std_logic_vector(15 downto 0) ; -- Bit rate in Mbps, eg X"0585
dcd_correct : in std_logic ; -- '0' = square, '1' = assume 10% DCD
bit_time_value : out std_logic_vector(4 downto 0) ; -- Calculated bit time value for slave devices
debug : out std_logic_vector(10*D+18 downto 0) ; -- Debug bus
eye_info : out std_logic_vector(32*D-1 downto 0) ; -- Eye info
m_delay_1hot : out std_logic_vector(32*D-1 downto 0) ; -- Master delay control value as a one-hot vector
clock_sweep : out std_logic_vector(31 downto 0) -- clock Eye info
);
end component serdes_1_to_468_idelay_ddr;
component cdr_serdes
port (
clk160 : in std_logic;
clk640 : in std_logic;
reset : in std_logic;
din : in std_logic;
slip : in std_logic;
data_value : out std_logic_vector(1 downto 0);
data_valid : out std_logic_vector(1 downto 0);
data_lock : out std_logic
);
end component cdr_serdes;
component gearbox32to66
port (
-- Sys connect
rst_i : in std_logic;
clk_i : in std_logic;
-- Input
data32_i : in std_logic_vector(31 downto 0);
data32_valid_i : in std_logic;
slip_i : in std_logic;
-- Outoput
data66_o : out std_logic_vector(65 downto 0);
data66_valid_o : out std_logic
);
end component gearbox32to66;
component descrambler
port (
data_in : in std_logic_vector(0 to 65);
data_out : out std_logic_vector(63 downto 0);
enable : in std_logic;
sync_info : out std_logic_vector(1 downto 0);
clk : in std_logic;
rst : in std_logic
);
end component descrambler;
signal c_SLIP_SERDES_MAX : unsigned(7 downto 0);
signal c_SERDES8_CYCLE : unsigned(3 downto 0);
-- constant g_SERDES_TYPE : string := "CUSTOM";
-- constant c_SLIP_SERDES_MAX : unsigned(7 downto 0) := to_unsigned(1, 8);
-- constant c_SERDES8_CYCLE : unsigned(3 downto 0) := to_unsigned(0, 4);
-- constant g_SERDES_TYPE : string := "XAPP1017";
-- constant c_SLIP_SERDES_MAX : unsigned(7 downto 0) := to_unsigned(8, 8);
-- constant c_SERDES8_CYCLE : unsigned(3 downto 0) := to_unsigned(1, 4);
constant c_DATA_HEADER : std_logic_vector(1 downto 0) := "01";
constant c_CMD_HEADER : std_logic_vector(1 downto 0) := "10";
constant c_SYNC_MAX : unsigned(7 downto 0) := to_unsigned(32, 8);
constant c_VALID_WAIT : unsigned(7 downto 0) := to_unsigned(16, 8);
signal rst : std_logic;
-- Serdes
signal serdes_slip : std_logic;
signal serdes_idelay_rdy : std_logic;
signal serdes_data8 : std_logic_vector(7 downto 0);
signal serdes_data8_s : std_logic_vector(7 downto 0);
signal serdes_data8_d : std_logic_vector(7 downto 0);
signal datain_p : std_logic;
signal datain_n : std_logic;
signal serdes_data2 : std_logic_vector(1 downto 0);
signal serdes_data2_s : std_logic_vector(1 downto 0);
signal serdes_data2_d : std_logic_vector(1 downto 0);
signal serdes_data2_valid : std_logic_vector(1 downto 0);
signal serdes_data2_valid_s : std_logic_vector(1 downto 0);
signal serdes_data2_sel : std_logic;
signal serdes_lock : std_logic;
-- 8 to 32
signal serdes_data32_shift : std_logic_vector(32 downto 0);
signal serdes_data32 : std_logic_vector(31 downto 0);
signal serdes_data32_valid : std_logic;
signal serdes8_cnt : unsigned(3 downto 0);
signal serdes_cnt : unsigned(5 downto 0);
-- Gearbox
signal gearbox_data66 : std_logic_vector(65 downto 0);
signal gearbox_data66_valid : std_logic;
signal gearbox_data66_valid_d : std_logic;
signal gearbox_slip : std_logic;
-- Scrambler
signal scrambled_data66 : std_logic_vector(65 downto 0);
signal scrambled_data_valid : std_logic;
signal scrambled_data_valid_d : std_logic;
signal descrambled_data : std_logic_vector(63 downto 0);
signal descrambled_header : std_logic_vector(1 downto 0);
signal descrambled_data_valid : std_logic;
-- Block Sync
signal sync_cnt : unsigned(7 downto 0);
signal slip_cnt : unsigned(3 downto 0);
signal valid_cnt : unsigned(7 downto 0);
-- SERDES debug
signal bit_time_value : std_logic_vector(4 downto 0);
signal eye_info : std_logic_vector(31 downto 0);
signal m_delay_1hot : std_logic_vector(31 downto 0);
-- DEBUG
-- DEBUG
COMPONENT ila_rx_dma_wb
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe8 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT ;
begin
rst <= not rst_n_i;
-- aurora_lane_debug : ila_rx_dma_wb
-- PORT MAP (
-- clk => clk_rx_i,
-- probe0 => serdes_data32,
-- probe1 => m_delay_1hot & eye_info,
-- probe2 => descrambled_data(63 downto 0),
-- probe3(0) => serdes_data32_valid,
-- probe4(0) => gearbox_data66_valid,
-- probe5(0) => gearbox_slip,
-- probe6(0) => serdes_slip,
-- probe7(0) => descrambled_data_valid,
-- probe8 => x"00" & std_logic_vector(sync_cnt) & "00" & serdes_data2_valid & serdes_lock & std_logic_vector(slip_cnt) & bit_time_value & descrambled_header,
-- probe9(0) => '0',
-- probe10(0) => '0',
-- probe11(0) => '0'
-- );
-- XAPP1017 style SERDES with auto-phase detection up to 1.6Gbps
xapp1017_serdes_1280: if c_RX_SPEED = "1280" generate
c_SLIP_SERDES_MAX <= to_unsigned(8, 8);
c_SERDES8_CYCLE <= to_unsigned(0, 4);
serdes_idelay_rdy <= rst_n_i;
serdes_cmp: serdes_1_to_468_idelay_ddr generic map (
S => 8,
D => 1,
CLKIN_PERIOD => 1.5625,
REF_FREQ => 310.0,
HIGH_PERFORMANCE_MODE => "TRUE",
DATA_FORMAT => "PER_CLOCK")
port map (
datain_p(0) => rx_data_i_p,
datain_n(0) => rx_data_i_n,
enable_phase_detector => '1',
enable_monitor => '1',
reset => rst,
--bitslip => '0',
bitslip => serdes_slip,
idelay_rdy => serdes_idelay_rdy,
rxclk => clk_serdes_i,
system_clk => clk_rx_i,
rx_lckd => serdes_lock,
--rx_data => serdes_data8,
rx_data(0) => serdes_data8(7),
rx_data(1) => serdes_data8(6),
rx_data(2) => serdes_data8(5),
rx_data(3) => serdes_data8(4),
rx_data(4) => serdes_data8(3),
rx_data(5) => serdes_data8(2),
rx_data(6) => serdes_data8(1),
rx_data(7) => serdes_data8(0),
bit_rate_value => x"1280", -- TODO make generic
dcd_correct => '0',
bit_time_value => bit_time_value,
debug => open,
eye_info => eye_info,
m_delay_1hot => m_delay_1hot,
clock_sweep => open
);
pol_loop: for I in 0 to 7 generate
serdes_data8_s(I) <= serdes_data8(I) xor rx_polarity_i;
end generate pol_loop;
serdes_8to32_proc : process(clk_rx_i, rst_n_i)
begin
if (rst_n_i = '0') then
serdes_data32 <= (others => '0');
serdes_data32_shift <= (others => '0');
serdes_data32_valid <= '0';
serdes_cnt <= (others => '0');
serdes8_cnt <= (others => '0');
serdes_data8_d <= (others => '0');
elsif rising_edge(clk_rx_i) then
serdes8_cnt <= serdes8_cnt + 1;
serdes_data32_valid <= '0';
if (serdes8_cnt = c_SERDES8_CYCLE) then
serdes_cnt <= serdes_cnt + 1;
--serdes_data8_d <= serdes_data8_s;
serdes_data32_shift(31 downto 8) <= serdes_data32_shift(23 downto 0);
serdes_data32_shift(7 downto 0) <= serdes_data8_s;
if (serdes_cnt = to_unsigned(3, 6)) then
serdes_data32 <= serdes_data32_shift(31 downto 0);
serdes_data32_valid <= '1';
serdes_cnt <= (others => '0');
end if;
serdes8_cnt <= (others => '0');
end if;
end if;
end process serdes_8to32_proc;
end generate xapp1017_serdes_1280;
xapp1017_serdes_640: if c_RX_SPEED = "0640" generate
c_SLIP_SERDES_MAX <= to_unsigned(8, 8);
c_SERDES8_CYCLE <= to_unsigned(1, 4);
serdes_idelay_rdy <= rst_n_i;
serdes_cmp: serdes_1_to_468_idelay_ddr generic map (
S => 8,
D => 1,
CLKIN_PERIOD => 3.125,
REF_FREQ => 310.0,
HIGH_PERFORMANCE_MODE => "TRUE",
DATA_FORMAT => "PER_CLOCK")
port map (
datain_p(0) => rx_data_i_p,
datain_n(0) => rx_data_i_n,
enable_phase_detector => '1',
enable_monitor => '1',
reset => rst,
--bitslip => '0',
bitslip => serdes_slip,
idelay_rdy => serdes_idelay_rdy,
rxclk => clk_serdes_i,
system_clk => clk_rx_i,
rx_lckd => serdes_lock,
--rx_data => serdes_data8,
rx_data(0) => serdes_data8(7),
rx_data(1) => serdes_data8(6),
rx_data(2) => serdes_data8(5),
rx_data(3) => serdes_data8(4),
rx_data(4) => serdes_data8(3),
rx_data(5) => serdes_data8(2),
rx_data(6) => serdes_data8(1),
rx_data(7) => serdes_data8(0),
bit_rate_value => x"0640", -- TODO make generic
dcd_correct => '0',
bit_time_value => bit_time_value,
debug => open,
eye_info => eye_info,
m_delay_1hot => m_delay_1hot,
clock_sweep => open
);
pol_loop: for I in 0 to 7 generate
serdes_data8_s(I) <= serdes_data8(I) xor rx_polarity_i;
end generate pol_loop;
serdes_8to32_proc : process(clk_rx_i, rst_n_i)
begin
if (rst_n_i = '0') then
serdes_data32 <= (others => '0');
serdes_data32_shift <= (others => '0');
serdes_data32_valid <= '0';
serdes_cnt <= (others => '0');
serdes8_cnt <= (others => '0');
serdes_data8_d <= (others => '0');
elsif rising_edge(clk_rx_i) then
serdes8_cnt <= serdes8_cnt + 1;
serdes_data32_valid <= '0';
if (serdes8_cnt = c_SERDES8_CYCLE) then
serdes_cnt <= serdes_cnt + 1;
--serdes_data8_d <= serdes_data8_s;
serdes_data32_shift(31 downto 8) <= serdes_data32_shift(23 downto 0);
serdes_data32_shift(7 downto 0) <= serdes_data8_s;
if (serdes_cnt = to_unsigned(3, 6)) then
serdes_data32 <= serdes_data32_shift(31 downto 0);
serdes_data32_valid <= '1';
serdes_cnt <= (others => '0');
end if;
serdes8_cnt <= (others => '0');
end if;
end if;
end process serdes_8to32_proc;
end generate xapp1017_serdes_640;
-- Quad-Oversampling style SERDES with auto-phase detection up to 160Mpbs
custom_serdes: if c_RX_SPEED = "0160" generate
c_SLIP_SERDES_MAX <= to_unsigned(1, 8);
c_SERDES8_CYCLE <= to_unsigned(0, 4);
-- data_in : IBUFDS_DIFF_OUT generic map(
-- IBUF_LOW_PWR => FALSE)
-- port map (
-- I => rx_data_i_p,
-- IB => rx_data_i_n,
-- O => datain_p,
-- OB => datain_n
-- );
datain_p <= rx_data_i_p;
datain_n <= rx_data_i_n;
cmp_cdr_serdes: cdr_serdes port map (
clk160 => clk_rx_i,
clk640 => clk_serdes_i,
reset => rst,
din => datain_p,
slip => '0',
data_value => serdes_data2_s,
data_valid => serdes_data2_valid_s,
data_lock => serdes_lock
);
pol_loop: for I in 0 to 1 generate
serdes_data2(I) <= serdes_data2_s(I) xor rx_polarity_i;
end generate pol_loop;
serdes_data2_valid <= serdes_data2_valid_s;
serdes_2to32_proc : process(clk_rx_i, rst_n_i)
begin
if (rst_n_i = '0') then
serdes_data32 <= (others => '0');
serdes_data32_shift <= (others => '0');
serdes_data32_valid <= '0';
serdes_cnt <= (others => '0');
elsif rising_edge(clk_rx_i) then
serdes_data32_valid <= '0';
if (serdes_data2_valid = "01") then
serdes_data32_shift <= serdes_data32_shift(31 downto 0) & serdes_data2(0);
serdes_cnt <= serdes_cnt + 1;
-- elsif (serdes_data2_valid = "10") then
-- serdes_data32_shift <= serdes_data32_shift(31 downto 0) & serdes_data2(1);
-- serdes_cnt <= serdes_cnt + 1;
elsif (serdes_data2_valid = "11") then
serdes_data32_shift <= serdes_data32_shift(30 downto 0) & serdes_data2(0) & serdes_data2(1);
serdes_cnt <= serdes_cnt + 2;
end if;
if (serdes_cnt = to_unsigned(31, 6)) then
serdes_data32 <= serdes_data32_shift(31 downto 0);
serdes_data32_valid <= '1';
serdes_cnt <= (others => '0');
if (serdes_data2_valid = "11") then
serdes_cnt <= to_unsigned(1, 6);
else
serdes_cnt <= to_unsigned(0, 6);
end if;
elsif (serdes_cnt = to_unsigned(32, 6)) then
serdes_data32 <= serdes_data32_shift(32 downto 1);
serdes_data32_valid <= '1';
if (serdes_data2_valid = "11") then
serdes_cnt <= to_unsigned(2, 6);
else
serdes_cnt <= to_unsigned(1, 6);
end if;
end if;
if (serdes_slip = '1') then
serdes_cnt <= serdes_cnt;
end if;
end if;
end process serdes_2to32_proc;
end generate custom_serdes;
gearbox32to66_cmp : gearbox32to66 port map (
rst_i => rst,
clk_i => clk_rx_i,
data32_i => serdes_data32,
data32_valid_i => serdes_data32_valid,
slip_i => gearbox_slip,
data66_o => gearbox_data66,
data66_valid_o => gearbox_data66_valid
);
block_sync_proc: process(clk_rx_i, rst_n_i)
begin
if (rst_n_i = '0') then
sync_cnt <= (others => '0');
slip_cnt <= (others => '0');
serdes_slip <= '0';
valid_cnt <= (others => '0');
scrambled_data66 <= (others => '0');
scrambled_data_valid <= '0';
gearbox_slip <= '0';
elsif rising_edge(clk_rx_i) then
serdes_slip <= '0';
scrambled_data_valid <= '0';
if (gearbox_data66_valid = '1') then
gearbox_slip <= '0'; -- Keep high until next valid so gearbox sees it
if (valid_cnt < c_VALID_WAIT) then
valid_cnt <= valid_cnt + 1;
end if;
if ((gearbox_data66(65 downto 64) = c_DATA_HEADER) or
(gearbox_data66(65 downto 64) = c_CMD_HEADER)) then
if (sync_cnt < c_SYNC_MAX) then
sync_cnt <= sync_cnt + 1;
end if;
elsif (valid_cnt = c_VALID_WAIT) then
sync_cnt <= (others => '0');
if (slip_cnt = c_SLIP_SERDES_MAX) then
gearbox_slip <= '1';
serdes_slip <= '0';
slip_cnt <= (others => '0');
else
serdes_slip <= '1';
slip_cnt <= slip_cnt + 1;
end if;
valid_cnt <= (others => '0');
end if;
-- Output proc
if (sync_cnt = c_SYNC_MAX) then
scrambled_data66 <= gearbox_data66(65 downto 0);
scrambled_data_valid <= '1';
end if;
end if;
end if;
end process block_sync_proc;
descrambler_cmp : descrambler port map (
data_in => scrambled_data66,
data_out => descrambled_data,
enable => scrambled_data_valid,
sync_info => descrambled_header,
clk => clk_rx_i,
rst => rst
);
descrambler_proc: process(clk_rx_i, rst_n_i)
begin
if (rst_n_i = '0') then
descrambled_data_valid <= '0';
scrambled_data_valid_d <= '0';
gearbox_data66_valid_d <= '0';
rx_data_o <= (others => '0');
rx_header_o <= "00";
rx_valid_o <= '0';
elsif rising_edge(clk_rx_i) then
gearbox_data66_valid_d <= gearbox_data66_valid;
if (gearbox_data66_valid_d = '1') then
scrambled_data_valid_d <= scrambled_data_valid;
end if;
descrambled_data_valid <= scrambled_data_valid and scrambled_data_valid_d; -- Only valid after two valid descrambles
-- Output
if (descrambled_data_valid = '1') then
rx_data_o <= descrambled_data;
rx_header_o <= descrambled_header;
end if;
rx_valid_o <= descrambled_data_valid;
end if;
end process descrambler_proc;
stat_out_proc: process(clk_rx_i, rst_n_i)
begin
if (rst_n_i = '0') then
rx_stat_o <= (others => '0');
elsif rising_edge(clk_rx_i) then
rx_stat_o <= (others => '0');
rx_stat_o(0) <= serdes_lock; -- SERDES Sync Out
if (sync_cnt = c_SYNC_MAX) then
rx_stat_o(1) <= '1'; -- Gearbox Sync Out
end if;
end if;
end process stat_out_proc;
end behavioral;
| gpl-3.0 | a5ef1212e77cb515ebec6340e22bc54d | 0.503107 | 3.579912 | false | false | false | false |
Jorge9314/ElectronicaDigital | Impresora2D/div_frecuencia_motor.vhd | 1 | 474 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity div_frecuencia_motor is
Port ( CLK : in STD_LOGIC;
b : out STD_LOGIC);
end div_frecuencia_motor;
architecture Behavioral of div_frecuencia_motor is
signal contador : integer := 2500000;
begin
process begin
wait until rising_edge(CLK);
b <= '0';
if contador < 2500000 then
contador <= contador + 1;
end if;
if contador >= 2500000 then
b <= '1';
contador <= '0';
end if;
end process;
end Behavioral;
| gpl-3.0 | 2d5f4924b594e4bf05cc95c1f22da0b7 | 0.685654 | 3.202703 | false | false | false | false |
siavooshpayandehazad/TTU_CPU_Project | pico_CPU_pipelined/Memory.vhd | 1 | 1,387 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_Std.all;
use work.pico_cpu.all;
entity Mem is
generic (BitWidth: integer);
port ( RdAddress: in std_logic_vector (BitWidth-1 downto 0);
Data_in: in std_logic_vector (BitWidth-1 downto 0);
WrtAddress: in std_logic_vector (BitWidth-1 downto 0);
clk: in std_logic;
RW: in std_logic;
rst: in std_logic;
Data_Out: out std_logic_vector (BitWidth-1 downto 0)
);
end Mem;
architecture beh of Mem is
type Mem_type is array (0 to DataMem_depth-1) of std_logic_vector(BitWidth-1 downto 0) ;
signal Mem : Mem_type := ((others=> (others=>'0')));
begin
MemProcess: process(clk,rst) is
begin
if rst = '1' then
Mem<= ((others=> (others=>'0')));
elsif rising_edge(clk) then
if RW = '1' then
if to_integer(unsigned(WrtAddress(BitWidth-1 downto 0))) <= DataMem_depth-1 then
Mem(to_integer(unsigned(WrtAddress(BitWidth-1 downto 0)))) <= Data_in;
end if;
end if;
end if;
end process MemProcess;
process(RdAddress,clk)begin
if rising_edge(clk) then
if to_integer(unsigned(RdAddress(BitWidth-1 downto 0))) <= DataMem_depth-1 then
Data_Out <= Mem(to_integer(unsigned(RdAddress(BitWidth-1 downto 0))));
else
Data_Out <= (others=> '0');
end if;
end if;
end process;
end beh;
| gpl-2.0 | d7b766c1bc497d7e06ba2c524b59bd92 | 0.627253 | 3.334135 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/ramfifo/fifo_generator_ramfifo.vhd | 2 | 77,610 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
cKZEuRPUxEc+5Ym7Rfdo4xybUv49oEv9MXm3hjSgcx58CvERI70nXaqAcWAVXI67oXkIPoPBTWDG
ptEAr3BBog==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
FhrK+34Yq2lYMCPfYfuH2YqtISRsYLaxmv1/Zwplqim6ngelk9IsL9cvV6fRXkvoVapJq8SIoiKo
ejnoevfsVco1jOj4HC3WwqKjUauvIPAshQ+4H6Aaqbu4/O4NwwVrdL4N7DqGHtsNuj+ScdcKAjye
Lkm+o3kQgHZ9OUDB0yU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
3L6YLtAKuHVJLpjkdzQrKIbQqalcUY81olzzseClC8OhC/W9myN6s3eY/Dt3qpCYp3FKLclC8gn8
Zzt+1XGuA8pWJwUssaRZjV6v59qQloRDWUom7HlP/bIaKeric+bB9ax8RXWIgyIL5DoyBDZDZ6MA
ZcB8eCjyLWK6VO/LN1UXvoC+8BXtwOtB0GJxRT0n72psC7J45DavmT68vEJ6EFmNvbM+NbWdqwF4
HJu77HQ4zlZqOerIiN5b5DamCPF3YzF92Mn6MeSL98p9B6bJchSdv7noY7byDeS/LRuQMYNXkS14
mWubK0S9i4Kx78Uluiu+cWTfRaJhplGIFKNRLg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
qQScxrgvF93WsBcCTsOJdJPFUc4/O+E0z7pF+nqkKsM6Cnb0VW7PB7E3KUv387ek5GV0pW2rZVDq
OEOlWBp8gvkCc5gtq57fP74Db1QOSZZSOAQDuaAGA/3lyzo/FFAFvtMm51dL9Vr012VHnKY5NLvV
lBRncXhqDKlhykp7ZiM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WNWHyPyEOHdlU05JuSLYaxyxTwO5PQapFfFDPPiNq7Nmae2uEfIXE9gGAwRtNYZH1sWSIlKSyxXe
HxGonGqxbGWveH5b94vabnsMVatFayNpYkHKbASJDh9i+Kc00CBZS8h97J5l1nYcVsyG3+Os0AzO
wezlLe8BE9avNm7hVlc9eQz3ubon16H6V5fabJxM2QUeZ5tgBYbuButtUJlU+t8uKgvabrZnQ3qu
uaJ84Xk0DLgkJA0lW2MWQycIj/8t6ZF2Xs9yTmyXkH/ug9uG620zaO3VGvsvv5FJdN34GRjQTQHB
Faqa3tH5XlXSKpgNZDAmGqPxYECvHg3IYC+/pw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 55712)
`protect data_block
5Ovi2vZlXPygQa4lZYCuetiyNGrSgttate8zKBnwdx9/ovvln2J2drFNH2uZH3utkSQLRlsQ6WNJ
PbUrt3qUaeyizVXArgB1eo3cJOjtOY39L+jEIH7sUDlM+HmaJ+jFz6osq3dvApV4b3oHc2JXbRVP
7DJOLaiBFqLwayX+9xYEUKZXcO6wjBBRD0gkiWCldUc/xf3I583iUOYKA/PMg4FA1am/6CxRNRrQ
QR0/PjKqwoydUVuTG6CKgSauYeqIgYNP3ohpmmf1NxLTGpip1NYB/0vamub2BkoL377IWQ0CcF55
w3agtwHHuMsiGDRmmJz7AM9zDB3EiajW6HhUyYAWiNA3Z++ZYLyfxIjnFmGGdxzwvymW913jI2W+
tcN3lIxrzzVHiPBHpRPx9o69YyMhXibtedh9FfC03utrkzYE0/eIkNl+ABe1vGypitJizvXJs5zT
gc1L4+Seap+9XfNxY5sjQU0nAw80ZkgVR+6p251ajEtyVa1GqU91sOBOY4s9K8fb4qUqlyscb+sP
W24eXo7lo6Kl1UFQVqYhWOUZCwdq1OvzOoBkITt3xZfvrN/5sSD+bsnobLPNCI/KCZErUpLA+LwK
Lifx0GlgdEiFePp+097vUKlMUTGBeRQEJezHntfmaL+KSwTyFZpUvPUx6W7/PzdoW+aYSAh31A9W
4F1CaoM6CozZ08J0BGyqS1bSakXpq9hNMXDLqr/cyj4CKKzCVDoZ4LJl+FfEa4LO250A25I9jck0
oSaBPc2O8ttDazC1+91ucpCKMYn5ri0xjqstnQdtuG8GZ0N96+r7kbvvAOFGkaFca99yBB2mgEXm
9NkpReksZxMrhO9V/8YyIJVGNE6yikVOgzYYtNalQ9e9EuYnkHEJYLpVmiqCwSGt3EYaJka2UmTL
IIuRNBa6BRMlvyIFNX9ga5hWnW7+bnuHTIvr7MxcyD0GEqY/E/ZqFgbkwewUQlvJbwaeZARekOM8
RF9zrlJ2dm2AzRiwvOWKHx1EBHlgKd6u4aXlu/LO79VTRWCkPuOKVv8/rvLG3yNGmvPxPb0viEfV
cwZBnmvPY1jrJ36wpWGP6cZB/vNoobwJfP69Ptu3Yy55hRx7k8prJue8xQnnmQKE5Q+Eyi20TYzq
CgQawYshnswOs9UIKpN/2y4jbr3TXIPgsVbG4LbZrH0ha/QWsCtmsUaSo1RbMF0J6OiVSumuor0R
FrI/Kpt/v/vPJbW6RPsdrW3FWsBbaiwKpeGdYj9xIwqxRLPC+05/m6WvOIdjFms4sfy/oSRGL1/v
ioAsDqNFIgQAykENa/2VLOZ86X5lVUbgH7uA0oc3OjMiC94yyqbS76oR2S0g+9Ib6PLAlNozv5ED
nw5dLRxE3n1tT3KYZ4leWKNNJ1p8Dub6B1LvwOWReO98jtR5vVTPvaCY0GRuILh/8XnRMKi2tEkk
BSOWToYQDv4JpYgquloGVKjHq4qA4l07RTgXd79vkc+SAgrcM0qW2tQfbICKEDITymRRCOABUwpm
dfQ+X6RneRy05abUryzcx3/VxtXa/AF318l13NpWctfOBdlMT7dPpYhe0aLIXtv2Reph93B5stN5
l6JFN/TUkpqFp5JQITt+s2ujJLfXvdh2MosmXqm9KDSicOsscZahVMk6bbYb6EPusEToG7d+Yq5d
2PSi4SGvSQwk12aoyA+oM/TvBrP6curcURbEEHyYSO9X5eZFQWOUYKsNIFKr5DfYIfBcfCze+8hZ
X3BTHcpcdQ5qhKodlKOh7NUCPRrp8XCf7kzsN3uyiaoB3u2we/v27sosd4QXU9bmvDpEuhJy4HLk
6rV4962ikVXxP17TbwWyT0DKhf8e/t+yAalicXaGp3IobC+JVJ7YWh5+ZJPXHGFxLOpu921kY9nW
xgDLMarBeLUOUbT1Zr0PfmcG7+V3vbicI/wALsXe06JnvWtHiMj1pWxz2TXDu4ymxXMreFDe2NBn
QP5GGAKe7fnMSOJzikvOcFu56985So7I/TTDLY/kdVSdOkK7CvagM3vhV07DrhCbNM/ZHAXyjPJq
r5Uv33Yvqs0sNahGAAgTVN7azS2bI7++RZz2TFciVz4bsKXHJjCNi20IFnrHtOz54LLX1QAyBM6x
KfZtmHwxlMX3VRw2PlyI8Eb4lYWRh38OkX4Qvl7yqVtPEP0rFwgjqZiY7Ei9Y6eEU9+Ry5UW6sy8
N/ongr9Iuj4hWBrcTSlnIrl0gAjugtpUJF3nDjFrz1YS9GgsTjkEQ5LCTOdzfyeEH69wsKlmkHIu
syc3JxiBTi5crDXq6tWE85hkaYzNSL3txaMOGob5jLo5dxYPOp7kS2DCm3hsaL3NL28noFCVB+la
bLlNmENmJbwV5+DZXt7InOem1sghcM5fFNPX3sZevqHjYGykZizjPdLn9nGkLyTmyKO8e9tqU5/x
A+89dVHnrqUFJ6L5t47nm7v24NFORYlIuhBtbWrPI/pJMxGT3cpi3ranuoi6Ll1zCsVGEXaWN7F3
ID8rPERu4PQU5caKynvLAzK37AtCYkgwRaV4a9Jpra6z0SWNkq+82EpGbI9rdHZhFNKXF7sS9Ivu
qpTHIxQ0peWwmabkIlpUODUfE6KFmha0ZuKULBM3osM+O4+R/YCA+YEFMpWrPGxI0IJAuo8c9RI/
UEIDXtWkITzsJtmxwmlgT7ZBXutbMgtJ5HlmtLx/wCATQBKW3TN1ufO8z3o1PsbjQybtAQ2+jSiq
XAiyvrZLRt94n6kda4p1pIuiGgjFgjIYDzFJ/AXhuoeWGuvFUGcbR015dsxwxQuvYABeJgbyKAuT
uozK+JmXXVd4Vei1K0NpPutShb0oyHAFQ4jdqI5HmuCN1QsheaUUbogLDoYUxJ885QZCxo1FPSTv
hRJwIF9Jj85K3MVzkp9+AJZ93sh/Zp8mXwRTzjqF99ZB3F7cf6TkMiZjQMcUb6jwKEJ2S8aRYbf0
PDLt33SHjAj94rwZeWRAaZ2WnnP3FZqg36tjzJs7l2W3pIe3ZQ5HYuwmzPwIzUppCnfyPuhFemys
ln1j7/TnEXbd8sgNWnbUQrAIoTJn0poXMrABIxFsxqLV16y8xd3YOP9Dhw3PvXJCoXtloTR1K3BQ
rLYqrKLAJIiRZ/tRnohwCySZmdREyVSsnCG4YMytybY7ivurGGl+27tFb5tTBKq/ZNfF9UNFCkdQ
hyakfgQ7ngYczy/erJSV/A6ghMJpPGoIVJS10Zis6vZ2fW+OIEjvfweNXRfAIgmqy2XYLZVuF6pf
9+ifqXgXMYxfrZwbI9neqeZ6LDNSyHHtHz+tQw9hP7Z1Gz7j3HvqB3RSbaZ1Y5DiskG+8G7BoZTl
snahN6JXeaXWT2yQUepfa0F3NHR6236NanVXH5TEocCp2nfjS7HLpTOQmT32+kL1wIv6Z/6tNxLM
StKJsZdl4rRI760fkEtD/UryDbSBb8/N/E+H6c2+BGXKsHyWNW6PJIZaf5nfIg0G5bP5lA2Kpyeq
GHtpKBGrYuZa33tniUyEXHAV9n/eRcY2j5GzewfhJLaNZsrE5iYGy8AOd4E9TSHYyoJvMFKhdsjt
+8bdVYFfspZNoeRurKkXd7gPBWlaEuF6Ss1bGBEJxFvxSE2RExfbDl79BosFpAPTw+ZeWOMWou7x
cijEaIgj5rOGaQO8Qyg/lGnli05zcKMfAohbglT1fmcT5gSTG/PvwIQcngK2XfZKbL4TjeJQvJZu
C1fP5r965WA15IY3aqWNsV9MQyrxp/mdjOcioUuMAR7jjcg7yTsKhib1N9XSLKfwlx2ZEsqMQYro
vF5onss/TbtY2Iq9cdiwvEV6DLwOjTdFue6Fir2s6t323hbxSPeJciMJwML6D2UA6DYMKuGdH0lD
w62o6+eekGkYAYX5i5ZjIGaMD40F5dIdaVMgUfzHMn+Kb8Hh8d9BPM8FCGnod9/yrxw1BE5xq6sf
ONp1mbIWy/HLMYiyWVWf577gmuzR124e45p+MDG3zlgEDvNRC2mwFVML740lL5k6H2Xmh9lrj7ST
DqAWMq2qJneGPjd+n8NJLqOZclv87LXWzoygXUlU4ItI2rqBOGf82aWvTo+D/urO56ADt5AZj7ok
++cX+FUk2980jf843Xv2Jo3G6KkkXfy/3oHXB5LtMjQHsnONuKIFGMOZZDuC8d+eTRy5E+iuXnav
HCm/gCPtKscnLOrlqkzDw+Sn3CeD8Ii77dTwzSF50plypy1zzAC6UrpXC1Z6GvzT3zXMsGbZcFJC
Bmfk3lpkgD1h8KOPswujedfoIGVVnavzZueVgHNWNYPOiElW/6QnZojPxznjR2j+glWPMZOtDaUB
8rYlKyJRrlW+csd7T3OIwWymwRp8BIpu5uMs9BPpj2C6UI2fYAEow8cZb3g7gDG+072BZo+ea2wI
iwqsLnt9Hpk6FySlE8HXrMGZTRdojCnEcTezcq703KlNYw06kJg9yz1eSCMlQkC8sR45ss/BbQl3
Lkvu3fAcHcK4lp3qXgLivuywm8NGXb7JTRF+Lzw6oB0BvNVYOIsrEcnRHjYG5OxPDI8hlp6eTIn8
t7MUPYgTG/oqN05RH3bQMcad2HbKRvaJtWsLJWl+6bsg+Pz3c34iucwkVIAl5p60flRm2C/WOHcO
ohyXajlsnyTlLka1/koOjZCTHZ8JqNvudAoNnToKWYM37j0YUplQ1Sb37/n/SnT+ecgZnvPVLoyg
Sg9Hsv/OnI4yOSXNL9GmmetaDTdDLtvZdisPjrr5nPiHzdf44hPRs1QwDVehdCcDzCIxsVgGWhbP
fJ2lEJcPYGYjhUU90Y1P/cJUnCPA9wJOUlJEqdJqP9q4FK8idPJ9JpDBMlxZQl6hEGJ4OwWRQrCu
nad/Od/q1ECp7YtqKSM9qFAeY7eZbio4roCQiWCpMjViW3wtkU3gf7LRakAeaaNwQuPXk5x6sdtI
0p89hSF8rjmk+mznpVggMEnTkgWdsPiYVz8GpdNu4TKXkQ9ZoSfQzwwx/C6QuzRxQAZMFZ4mxBRq
aNiGiPQqneGjo++sm0noaOjziqDfjB1eGAOjxR3p/VoDSaRUwsuY3lBOuroWAF+MbwNceI/5oX3y
Ah/Ds3D0sdi9Jlb2j0WSpVG90acxMHV/fqgo21APPx9qUcOLrWM6++FrxB9S9KuBICbo/A76l6Yi
8oKVHsHRtQFNcAnRXuIJEUKnT2s+WG5USY4oNA7Zz46iWloVGoS5XZVmvfYFBeyZv19pz6BmUx0Z
7THwuh8at7zeLgHJld7joDKm5SbQLxFpsp7eaK7lnrkTEz6hgHmJWMT3MeEGz9an5m4gvTAj3ltM
e7mzFIJQMgfG0Hb1cLAljgdnxHckzxmTt4WVLv8Hilk8zdpyjjFGN7J0qlLi1SKfw8ARPqNi0yhL
wHIM/a6RinDKVp5/0RtAMJJn6GqvjU/SJSdEP9AreqCvNB4DoHMtLKIUnoEGgJfvKvKZVQ9rvmkG
lT2rvdWaY4bbpZsa4MFYG1nm6tbF27dnq3QImoj5cg3bzEbljZC1vc5wD70hZpa/6hEqE2fdsROV
yItNO/smafD/DGGo63b0LHsAj57JCr4BZbERB4+c9CG/PcW+4JyhkDzrk7Vnv8EuhgSLl9qSIbUx
T2IVRiU9D1LEZ4ObVRNp5mDzK1QNIncuNETwNVt7jDRiYUTcQdPvGt6lOvX/t/sIBNfQ8ZtSUvHe
+Wl+YAdF4YNOtHMXbpJ4mHBeMn6iT06UwM+w1/dmchzWajfI8rsRV/oStUt9GElyZD8YMfWxMfWV
FPFviR7DC3tkQurhXRQdnfJk4JmK3PoFD5QSopfRIb4zl9JCE1Zlkk4h5IHrsPgWY5XeI1MJkDN2
wDRk207YuLE38+TkC+3ehJqrGzIBZZaKGP4/XE8Ik0QuR7X7YWjRUQVjYtdTTmUXAyQPtmSsupFe
Zpvg/ZpysJBAYMXcACj431dtVj8FmnZhHxt33BMDuEhkiAo26aFVGIU2QZNeXQg+BEs0LiR7SqpY
3ByrU3uq/aCDlXzNPf4wReKLXw3zpLSUMg22z3uEj4xbsq5z8o206DiiLV9KgtEr/JjeG2qOuvl7
fgMd5LVdHnZISDJcUfrkkkMTuvCJ7d8s+27M2nUh1dVagd7lQQl/Y+TVqLX7kOEaTs2Zqrej/2rG
UIVQ0hUaPzdnNWogHbbti2qBGX/RSP/3eQoSK+BtO2n3kMc83eQW7xR27xYe/PAXN+FynTxjJm07
MUedqdLe1xEQyD/2hpTXdHYtVDjMx9KC/U9RW+2/j5HihFIAtdT4t7ax7qhtTMoizH+a8ElcyR72
g+5OsCrjCWHdhaPoZ/35dNIUOL6MNLdlcmGckUOVddbErSY7H2xdFQQaCPBIUloKRr5cDPXZ5lAj
ofL3E/IeQBYEsks2Q7dQxvZx9Fo35EDbsvBMX+Z5BOYdt84GU55HD88zDpvjQVQUnLMf9K9ByF7k
MR/aF1hFMSQdjLLV899Kx+0FmIxc2U80RRatOiQYxLJRfduf1JSIHK1CvaPDUNFMthWr5UliQliK
9KGQNHq/Ab04SIvM1ou4Q4LOoFdXCmMMRpmfUIF8l6KGQeph+wsoMK0M33Z/ChFob3De7GZ3u8jO
VeCZPljNDW1X+BEKEE0zS8HRRl215mPopv61+tYKEMKCr5m3aI+3pQJX0A74Smtzd1cnZU003MZV
Q/HGgrbYwOJl1umuifk3oewpgq5ed5OgI4kqWPwEsvFaoL88Kcnlj6UcHCJfJX/9k5NaJMdghPIg
1kWQ6M87FCST1CQG9TgCOMvjNPkVwJjs8M10HAAyMyR+bOIIjTvuH7wQptLMDDxAzkV+kUEQ7DJl
V1y7CEiFPB/RUbrnlwgzOGZ8wLRgQNq/00eqlXHc//pSkADL2zZQ2rhDT6CLn3i6NnKl/CqaJFtU
osb18K+tMEg6Np+0OKrLZR3zQgqPnrR1X4o4xyvuR6ntwpIG6LDd0HhPKqAP/wlforN07FvF4ucp
+XLMwfy39CtyUVa9T9u+I1RTAb1VFpFHt6w3ykUwdyCtYTg8qwDfN5LM8+p1jJHD6HdWrVO4D2gp
PWEBAtHj0NxSAlSQV3gD9uNCVsuKZnme/uvFWJuhtDssackYVUkMYs8kV/m8+7DIbYWDdkqAWrx/
5ATK2s9lEDXqeJqgDsQpnyg2qoT7ZnAjUsQ2Kwk/q7PNpjXT50++lZ8DO96p+kiG8EJNqIHeXlFO
iqt+ci5rknO3x/j/O81tlkT4vTJpt58adsk7L9/uctv1iAUZExKcoLaksJBADCdfeQWPSQcXbFLy
06kpO07tmme0Pp5LEUniXTwUJjsEOfi8P9kp5Z2hpNoJK5m9fCOy5TD7Rlf8/6lrVZty1yE4VNNJ
jj8/AFYXDK5LeAc4nhVhdbWryaqsG6I/iBGmgELymvgIWXnJ5EZuBVv8jrf5eN00QntqKeibv3Is
eIEKIhekOf7cUcpwc4VJLy37COTz2bnf00yxHkm1woRmDl+I5H+bipCDiXiI7vIluEY3PrZIiMdd
zOQJBTzOD3qOUHIAkEJH4TcKTrOKkWxyYd0nI5r5GF6gLQIcSsADg+rGDXMnMWDVrRs0EBodp42D
h73Obazo1WBOQwOzZy/Qp5Ac34Gi2lxjYMyGaajTdwlmvf+CT2MbcAgEWkrghle6mY/hh4xwXrWH
zI+PkIxOpbr3zwO/3WqZ1C0o6lHLOoCWYpJMwn23mgpCNomR5Zn1xaqdBKsOldewd4iQ67CkdlCz
oK/lcpmdiyMjgDMSDoPpwUZldEUNx1Y5B537nTD7ii1lET7QxCBwqi3BY71S6M5iTx5h6w7YlSzt
n0LgU+4/9ykx2XwMwxfK74asTTMMphvnGYLEJPj92DXCXC2ElshMy5LGBPw/MdUuFMZakwCqDBs+
E4hTY6+dv7JYIe9GtTQwJVoHJjy2qd3vycSdxCbKhFBiToHtitOPNyFKEeWv8YOeEfBhsTegPfZ3
AIB/kAAnM/LyXnYVd0rJRlbYNki/gdVcfZAYL8EwHC1x7uaMpvTkJ/wzRJNfDsUqgo5treYKvuZR
ElNCGVPEbeUppNomgdkP3Yc4KodZgF3DoV1CAP3a9Fk9oIRfp3Vn/vyuPQaon5qF+kQqYD6+VyXR
1wuNisPPe0SSZ5Emwb72pyxzUTLRgDPxC+eAAWmEUkvwpiOMqnft9jux3fRPwCpsEkZSEsrrMdJd
nKDw2Bn3gJOKXzLhqxtowy3hoMouqKqS/jOBGYZFBpLbLy8/I7+XP6BIv7bqk62KoqLBoAsBBMv0
dp/LzrUJaWHyHKdbmP5aDNqs63urLxdvmWi3Myf378MNYt6NBvAj6RPup5SUkVx/lih8SdSJWlFe
WP/zGsCMX1zw9lcnvCCjP8L3YslCnd9HT+KsurkHtqw/yf3bcEPqV5xVSUOFiZZTdtA9eVBpiQu0
Uqmu4jEwGcGiAyOyyc3wx6Mh8HYE5k1XwniB/bACHN2PegsHsgd3d9ncrXHl+SLae+Db2ci4uSH/
gFpDG/pAdq1WjVvX86xDnjJutfMCqwkca6wz3x3TmHnA8YItOVi3JSsojWnRI/wIzKLICKPxMsId
AA8Bg3/QiU7flVf6lztQh4KKX8Khqccz3OQ+fqBzbdX/cDJOSsE3Ep0a1IkT7yANRVENxRll2oZ6
wBsVoTJHxRoAb1JIjOVgi1cMLj1fNm8X3YJEeHQ7WSAMzrrK88efvAhlribiqdaFp4a4xHnFTpmL
rPjtKO3Q0Q5T77Wu11MiLv9Yqr9cG3B8rVuzFm+slDw0FznPcbGga183jKxSFj21MWaUS7tTnDN/
B1Ca+Tt6s3JUn3Yp1NJvc2y6MjkNwO7ko4FgPgZMbVfDHWzIbIdwLsr7Gei8xxrcMFgYyflvRwU6
QxSaYJw/vEZDxWG3euQgMwFapLWkN7uUAHy5MuMy0qRi4u3wck55VXJEddLCHFyZ29LUC09966Sl
TT6jLGwPk5ESsOzUuMMS58guTIYeEdlWJUiktNSmL43J37NOWzE1kEib+fTCSwzF098mrJnK6QMD
de5Wlq4lA6oquR4j0TMcIAm+ad0TWOw5TfkzcQebrDcfprFCxlDb10GKU0g8pzsjaTq0BAPm1e6G
yDwfzubHFVQ9C3u+24SK0xgwO/9w/OZLT0OL/BMlrREQFbilibDUfiGvyDnoDsKTBWOWSyWqsrcO
XzjpnEWIkdYrtYV86AyJWR33gFj91is9iIroE17yg/TJvf/Yrxg6o6TygKIPfmrYkgTGs2HZBycd
JnEYgF+yg348P2Dxtfk2PSLjpGPcyrz/k1rOMmZVq4I/lLh7GvHTFz1Z7f2P0ckC4AkU3LLveboB
TiW6y8gmN4ApxuEf/2hqKd0+Ixd4FSGMuL4XVPgDDcX02GTz9xl7JOpRriWkgyo11BGfODcnHPCi
19JdBv5uri+s2SmpnSpM5y1ryB3lkxZ8Ft4bZRRWPsiyOrds7lOzirZslbIv2OYPJqnaqPK8sRgy
A3o4hNzYKY0PXfR57sqtPLPY6dZSFlQEcZoLjwpg79osz1IZGwdO1C9uAEjfJ9Q1DflKCTj2mhBs
B70ZmUM1S7a/TafxEk6FnS00JJFTA4HAUhwQae9BJhkcHSBOOm6jMDq67YdsdMIpm951obmSeU3M
qf/wbOAqNfaady42F2ZDS1FGeDuUNtJP6ehO7kH9/zyrnHZGsIm6f7xyh9AivAqi0KyAERqQ6Oct
gnwZXFc8XEVfubp7VIUS775hucMX3z7mqFXsmub/iG4jyY8pY9Dr1ei/azlfLISjiXyyFPNSqAn/
wth0VFOO6RRavSPKoLSn4dYDsa08M8MZynN8XBjUg2PLE/CJZgG6yIDeOtr+ROPttQgR6oC1lLAo
bqcPg7pWywAEfOFj7fFLysiqZArT0pDZkcVh1Zkqd7LSRQPNHBhahE9m6J3WIV3YAugSCkjD/ras
f6iY/gR3hDz/lrG6O6VRvOMSnndmymygKu6dCii0jnSQwmP3NYnhNTQtUp6sKMNqf1+2PO1GsZW0
Acfr9YNk+2Pg4yTcfa6OdkAVWNa27D14JNK3FQnQ0/qgZugB19ZJXkZMrtvnAybsekKtKkc3YssG
tr2qAMH7v22u8Us45mp9qLp2tzAnZam/v33s2XmvMUF4AKJOrjhNVFa9HiiVB5+/vUMbgx882r8s
51puWRJs0ZU4k1UDLYR6bTTwML5FZKTJuF9E8POeOQCu83OTBQriMAHQfSj/KST5zaYAtIplta0c
dp8f2Xr+qq0ZquiJEDc1McAm1OZ4MbvYDnrM0C2HM5Nz8w70RzQajCOB1q4YlOLzw4c3QzanJF56
CfaEtYPBYsBdaL1LmoffBu0PSJZj1XRLG4nTBBXbenD61p3onXBvdvGDBtzdFfB5y+5A6HhCg70r
sMwKC2sNUMOHIFN0sKJWQeP8/EAWcBB6FYPDVxEROyfu1+nVGN6RWCESd97B92bEFgtEOWU6w+xm
Ik2may3W+/sixO7DVh+ORXubKn+x38r02J+t0BrfawhE4AK1Q8foqVFNcQwXLwODWsTll3+A7JBE
mXP00woWNlAqrIIUvfUYTpRN4QHda4s2NUswyHv0zcybALzjh81whi6vLgiSGi606ew3igMnZKXH
uZ/yebNyqzjavHnXdwCgEQ5Ct2RDPThEygDIGbsN69G5+w8CcIPXRV9gQGHY0k9BTrwOdtVNffHW
o8Hn6yOw4NczvopkmXoja1pvJj3zlw/K4hG3MH0o2r9Pmzt1uQWsK5n+oQ1H8GTVN2DOaz0EaJEd
OEbmPw+7vJQqW1r0DgzxajlLc0Xi/WOLYsYQypqsNoeOfgQu5ZIgzVm7GZb+HLY80rG/T4xPPWAe
hv9hl7Eipv+UNyGLY0wjoCAwjBeVAzPJ5nQu043zkKcXSoDqw/ahG2mEDPAsfVjoJaQDFcjvhHXp
rbMTnBTkzjiBkUa342j2mC+Xvo1aW6J0jhQuJNHvG95BmiGJ4NWyGZU+Uzy7TPR9CZ88P0sYEiXT
skEAKiNhgnvS9dqty6UKeJfbt8vXAAtBGQVjCD8fzlXQXXTKjmyt+Dj7tzVY19nknuI8iTtaBQ6Q
7Qgr+IGjghV5caj8a4V5kUVB/GJs3nqFqyr/8aZzalu8QXNzYZoPzTbk1hBJGQN3XDE6lidFLFJS
vRvzMenOqpu3qdhPMy/eV2Zxan4oE8cWSB4hInJUfvPoVEs7XNV+laNGwdQZ8iK6LXDmXSGRJ3Fr
X8PNzFq+g7KF5EaF2RmAPgepLWi/sSdhP0kFl+IM5UeYliwuW7YCRFB5NTZ1zLZaeSe2DrnJ47Pl
AzmMcCRj7oHNacUtNNixQJGpchA3UVOJcllqB6J2DE0HNLe1tfKOzgysnZKE9BK1FUYrMqBnfbe4
wHvLvEQOiMRcrxaiYfka1o5k2L6VJB1Hj2D/jd93HhShELsm0neSSA6uQHnNfBHLVz/QwxAHyN7J
GYQDtIoFNnKhvM1oEkRLrs47u2FgxopkNUkualUw5OD9eaZw4wUSda804ViA4GFrvhjTHesWAKb1
7JpcSgfLgujXBEKPxsAtHKK8FV0xPTXZ5HGlY5XGWBERsCdY9Kn2GnVXzq6xfkruZtN/bJIXQioe
xSzVeA22QCopqeFYW0oIOkrgghENpfUb4D8SyciT88XYA6Ht5CWl1lOCuWJKb4Ss09mQxcBpGk8k
V+AsmqUVZVxfR2JgFO9MtUNrX+6HCbaBOgjehwsF8LLafWLLYrX409QHi1dr9pS87SspWlsNgfn1
QD+6gYS12U4atR5+XI2bClxJCylr7hjQG8zEpDL9j2dteGX0EaBEk8fbMcJppyQNBZ0tj7WKnpgX
tJ+u4C9mc6YfAGLHhATX1wVVlLNxafCzW74sKowdpByHB1hczutlB3jz9lg9zZ/ducFCiyiGIzDo
ycSYO5Etp7a0Fz3Idk4fvSnSCGCKhptrPOn8h+393nfaAYWK1qDfZN3uKljrWaN6d8hh19zcJqZp
MKkqY+pJxhJRjrP7zw+u7PmcsSiBk+U4ClJcwNGT0LH84I66S3j4gX9Y5MemuG1KRnqgRjY5E2cM
US+AQnnXZd/o+VmXwfeR5laHRXImBwYeLQ24SaUUFDlUXkcEKaN2sY1ws8Qbavf1U2nBcPI0ARkC
+rLLZflpITYSrI0GENBvaTrfOIRJRQiSI1xXTcQqUPC0Ue8jLtgXBtaZ8BSdIqBZzdusdBO8BK+p
r0YM9HybH49/i96CWdBy6E5hgrl7jY2UhbIw0eYq/wroNmo4dkkpaoAHcgfSNbTgDRF/XRcfyZRr
eyeII/89Qldxzk2tC+C8akUPu/+seq9NqHoHVjopCYayuQKhKy17oz1ttytKWCGc39Jx5PyIrKWE
6Wj/DBNbHlGlvUdYj7P/emQl8edEX+jcdwLRGhzlhL+w9rlIY80Ej9M2SyMkqujtRPYXUGRhGWvk
vBo/eqgaWIwjEXuP5zi65KjB+9jq/8PMAc3PgcO6yBBsNAyY3Fe8PwSI35d5gWazcdThzk1bfOE+
yureSDw3/TF0c2UsFZpPo2q1l4t65vtVzMZqf+ciJ+b5FpEXc0b2jZXoKIvhET/i8Iyg8oAplipq
3NEEWkp9S816dNQbw0DQ5XWsYOPH16n1eUd7k1KnvZW3Amj5ElfxX7pWVx72Rv6Ire5IjO0Hx//4
7SAS//iBuKJR9L0H8Xgk2GRbibr5IQXTy0RIKfK99x0HFv4bUi4qCKXawtmCZA9B7NWmSu1sLxph
Kx1+CNN1gpCA94HoCCW6CtnuXv0rJ9CcoDhI+oUqCEgYTM6lKOwk+gRyToOmW6/KnMxecEUD/sUL
8Q5XrfhMYQHduBDM7L5bdNaZLPORZfIqTbRBn9IfrppC2pTFrIDuC0DH4g8aCnnRA91S+TUx/2BF
kBvwJOUNOdiHdQCkGNoM1WmTufVh9c36gF8O6bSsDdXYW9flR+6GfkautcA8pP9Ti9fwryQviYxx
QeuOQciQrO/4TZqzxWZIte7pMQstl4yrIbSvTQuSGS5lf296iU0GgcIoCx7azfmKL64Oqc9speYu
BbwMIC3XDpKD2WjTDCxVTwINTAVXnRxHNQxo+Buv5c+xQ9GiQuQvilkxg/EZhRHuesLlpyyqcmKP
Wgd6cod8HCXw42p/KqJFfLNFFXeWfp2le6rKQLyRInq4KkxmtW7tjc/vucjXMvJ5Zpq3iYIeqo/0
f+NEu2K1LDOK0ugqE/mGkit/f9EWeu7H0GUSouid5ABednU6+bwMHWgqioMBtbq/4MQk34v2TE02
ErkmNrY+7OSMfwFEk8j1RHRopJG8YcuggO3cLmE2p1EYbb4Dyof3gYNGNGl1A9WO5Y2OKbP7bNJ2
kDCFtmgbpzPwAnJqvub4POuOc86mFbTFQYjtPYF3Wyf4mkAmrYPnDZwbQsELxW8McxarrCZwhA34
bmTw4KxXVLXZfx4wp/fvOGlC9vTI8I25LlqNUrmT451+RYDVL7uMKo1YbyBpNymuuogj2bpRWgMD
vOay0tdSA0ZOiH2xv5UMDoj9VYYscIc49QVJeRb4OHCfO1Qt6+5KvMlqP8g/j5+Ha2N5l7+b9UzR
p4UcZTCrIl/nR5VYGzsjbxkyXIF516xK5Lp7IumegmePLjBd+ULp2eX20DZHG75lgyR6XZvAEiKk
bz3UBTIwKvq2CfYMznGIm8DxbVvmDi+iMyXJzK9VAwBqhk+u1hI35mMz090X3MlJoUEHm4TBPPFI
zUOlH+PMM7mCbkGsc9YnXGpVHHRFloV9wWafCXCl6q8tECZy3nFMocLQ6+TQo/gB0JFqdSNf1eMp
4HHRBENzgjft3jal9YVVwRfniBQ+J7gi0/oG6eQ3uW3JVQg5oTZHWiz7m0RoWDQvEEsDa1gfSrLC
oEmIjbiTRsfCOI7lpbTc8DYZGiNe6E1cdOoxITQpDOq3P1OL2CXfBTWYvhAfpKhNiAvkPMxAs7vj
XEmvrurGWImuOjxZJ+A7u96dKydhD/DjiTNy8nxCP/KeTwfcXet3YCSppFSwzfmpDJjtb2csjJ4J
dXf6hBLKa6Y6cOvRWngCfa8D84hZ6UQSB3mJxk9Mpx/kCaU6L6aunl0kalfA0g+QOGYnBLNeoyTM
rNhH2l0bNUk2WMY9UGarplzkoh/sew2aUHAVDvqPFqaj6InuP6+1CZUthg/7qh4OdIjTQdTyewwH
ZEtbM5eG/Zsa36C91GH4MNYMrTkYbPdhJc0O4X2ex+wt9ZrPMYa3emcNWFAoED7JO5/fOESVed1f
33tETrHyeUVFriyexU5NfM4lEjgcQUEwOitq1nZCL/f1nxdoZuhji15DHMttkm9Xy9ck199w0ZsS
v984ME+zEForqhpiMjrmigPhZF3nPs66KcAKHKWS4DTWojmfjvnzxrsXV2vncrEQpeH1V1BW2TXa
3VnfY4v2obpikFdDSbE+/F6oh1yFn6dkF+f/kKXNMV2k0T7df81Nw8v387V6DqWLB+/ZntiBixiy
DC7C+iVjqNR7bpJ0SyHi2PpICHeSLg91DNvw9yB9hYyLD3plOxwC+yqPaqgpor/03ibVSml8AppS
xFoo5vtjsq9sDZimLkgMpoWQl+8oo/0ddiwIKl8liLPqNyB52j8s3PK7b8du6G8bR/gYs1yJ1cHn
Jjh1ydJL/MJ4d+kQ8BnmzZtKT6LcP2hIG2CGEU4X2eCXACNHjsu/qOBvnptsJZBZwDALGq9iEPZ8
3+FoB8QxDrtvXObmlXhikA0l4rA5+oAHLq8xwOFMGsvRfyzr+KSXse44UfpFNm6yKrgiLGk319Yw
wD2c7m3XJQ0KhOFE6CZeSpBbt40lFfJFF73Y6QsgupRYBwh8IAojB7E0oBF5TexHqSuMDrI22+3i
1fTTkOt4IPyzyX5XpqDpEoDO7K0hBHH6wYY937OoF1qfT1B5QmmujGAXzcPLMb0DemX6ULl+L0Nz
0FzAKRo8NgjzwJBaoT9aVD3YJS+gQTMZCbl4dI8jLWPTstPLupeHrAF6KITNZiI+JjcyR+GlR/Bq
uN0CoYsZE4QdbWR+ZPmn0q+9KI1mzf/mhCvGplh8bn6TM3l1RxDIBZhn5n1vGNZq7nZViHXGSHLa
DoxZgtDbD2R8ep0vqAramN56AAhf+ESbGY3b0FUpiZJbm0byZ8LKmuC3qZgm7E+pkVPc1uQQKsIf
d2jNDGKOeHOLoGR6FRCR9NeyuCzEQ3niiMdw1Hf8EW9ukHfYTxUTHi4GdxSxgbEMS1IaSajgdRzx
W8SjToExErqjdoET0UQfj8vzx25PpmGxpDQVpTpAUGAXLdR6/ldaY5bulpYJC/FZwcpFIioX8P0N
L23ZfYSLujULKFNgVIBW2synWt0K4pq2gTdYE8K9OQQWmyM0Sc0axsj4yC04BSETIT3K1PcP3rx2
NKwcXUYtZld73gajfeFY9F8LpoYSdymy9AqkXPrLV+UOHBi+GNK+a+ascj7OvktogULv5fIFzPtx
nSChH8+NzntvAaVQo0mGnTQv0vOhxjV8vVQ+90+/JyyMnOmdzjD15pKpBaqD+sOnOXztWjTbsIkm
dxaKPnaOuMFdpG6GLw2RbWE3fpYV638Bx9ib7XhfQ+aHK/uBpYu+HtfbdVMfpR+UQ5Bz3+G+ogni
aoMqzfrIWqOhPrB1cnfIYB4JtNsSF5TuYlNYsHy+fR/IlgdgIo0EaGgfxPtVgrmOHwOL9Q18EvY0
IDDS9d7KUzOiyKdKjw3ieAlvIp3QV6lcOoNLybf5ZqB5r+FzjNopi1qjvLxZsXQ/pdGP25NddtjE
DPzQdOOO0gjC61HHO4/1lTO1wSznwqjODHnZH99XHguVohIpckMgYEN2sDiDGE/+SYP8C6ao7ogS
TNmnNTzpFoAaA0YTaOCAHSqT8G+31t5+6yc6mP9qUU6gwxvgusyiUTVwh0JkgUSkWE8bHqE6CI32
07hHbtsEgFQKyOb0N+hDSHD+11nxA9szz7JLQ2ZqCeGCZMbqB1br5DQUvoq3KsGDFn1gSwMhx++Q
ehUBHYtnxvAd8eoxEMdgCgzwxjUVwZfUHc8g1iw5vBi9dz9EvaDKFGc6Xy9JAOPTIyCFRC2MKF6O
NWne42gY0ZDkfgMAxbUS5BsWR8O5f9ULPlvdWnvNB7OrLtL6VlSgzOlehWzDChIc3etO7VS0X8At
1azf1c0rsdO7NSNAh+fQrjjWm0aRFzEZA+im3S/AtppeRFcnl02yaiGaDQZcsF3UUb60CdjrZS3J
2jXxf3UyeAC2QiWa7mduwEPzSqouUsBToEv2/EzAxH/UpXNezrFLIA4NLdX49bJDgSdSAEqoG50L
UR+QuCrX6JNS2KoRCo0h6s1gmAYA23vKPzv7l+JyvpRzN71vvznsFvvEH/WZuTNKpQmm4g/9cfcv
9igRLFqjg0SnKrgD8B9Vi8JdUZtcTHi/OuAo4nCiXtAYZzx7aRWClunFIcmhYTuBJ9BtX9gEUhOT
WiZrbTuR57jq9m8dCfxSExFu/abhy/qrmwPRG7QGU8LOnownGdDcSuxwPo89LzpHwXRCpQKp9+eB
1eWhLVIa9OMc1U+FEhPRgcJRvBIEr4Ilz3oMgmeAaXjwXaM5slYjToWVXnC5Vm8/BWgefr90/jAI
dhqr0WE/wKR/7PLwD9nq0/TSqZw+kXQ1oqnCwPOle2qAU9IpkvKSr6RVeJI32jtfhvThtErVJMwp
skK1HV4uwzFaus4KyU1aJIw9ejacp27t1Z2pNnY03wiwFdq8ffn8v3sA1ibzLJrXsA8bnbQqP78w
lRvUEADP8Z0InULQN1mRCw/AmpCeZfmBiIV1ekhxuZWVpe+9/Eh/n3CSirVRmStzOLt/NHIcho/2
uLLJgQC98ijLiw0AqmhC8Yp8cG5fD/B8WZXKSuZDrHed/ojxIHBWkv6JJO4AoZa/FdYnniomHWBT
SrDfa5ybtPra3D7vq9i0NXQyVj+4rkre/oacDt/gdvb4P/I+GVcNFG+KZkRRBHdnskfj5IVxUf9l
Srq2MHsrWwVplLSrVd8XoGH+VfwNZzIR0WPI0+P+/wwtw6CV9mbFG9Ti9iD0IjjNSCjd5cNBrHhq
Ybh9SVSHTJR2t3BGX/UcbC8oU7PtcW1oyDe5HQXZmEBN+CfgoNfyUhOKfU2CoeT4NS/dnuwmEMmn
qAP7u+TOLu33M9DrlUIwEqYw1g419oUMSlzs9tPlGn9MKiihrn1RUq03uUb7AwBPIjMGlR/A/CoA
WuMr8G4E6rg6sc3ZDihSSMEoUW9oAVrPm0RvL8Co7eKavVImwpQhl2JrLkGzrbkR36u5rBDsXHub
yjKnbB3z2QYHZD1UtAujZTLp1o98AqwjwEM/R9bSBoWjTQU1jDrgL3+PPZVJcbdFTm6xj2gShWEh
JlYXzDcJgmi0C4pgIzx6TSCmOMGs5QJIcPD7dis2V8xNGrelxr9SNSTJ8fvJSD4MqGJRsaD31qlM
DKeWTOxnQsTb8Gu+qeGEDAyBCSJBYctkpRElQzkZx1oxc53UUwBCWCT0ZWSdtbtCX0sp9fA4FYc/
0a1U4j8cuIK5mqGgZqSD5ZyzWooo0A+juthfk9hWrn93wcPPm/mu8roPggOW/7lyQ8MBZ7WfHOnF
RJu9aMXpfEgh1q3xCC9YHj+qlNFV2Au5qr/SXN9LAGyRWjRaGAOcwlSbLvweKkWsOFtjVgVoocyW
KD3vgDRTos/VXdbnvWB4de9DGJtD1r42WdwC0X2avsHR50sc1ePi7HtPyghMxYOyMUVucNXVsbgn
Ln32bb1uCFCsjo5Wecv/z4or21iJ+ZMnIbIaXASMiji0QnNYVotg7z5hbjLuYZxdnaRbOkljePB4
A7BrWMPcGLrtbmonhgVhb9oJxz1NgeO77PF7CYHCsmgi55DlIFuE3BVJYsCMzov0sP3LEg0Uy1NR
gnerHiTk/EqQZhAvAqblsACiHgKCr9x4tQt6qroBkSMEerigxP9WkrPrHMjQJkLPkkkbBjjnZ1z/
CphuViSLKOK4ycVBOwkKiHmJLwikIzc7yOyVY+ET3hdfJOHL7RxbnzcNXxbgDLc4Mis/v/SlE6cM
pke6aGLBmA9vHKy0MpNx6B4PYu4NgXDv6lMWBSoL1+K+oTI2rI6THKUMV/xy53F610j9NzcXQOAh
u7iq4g/hzm+AxwOvcpw3BKU7N8HFXjz20VGKb8r4Qr458uCMUqITdT9Xc5soHos0sLK4Si3vzvLo
WA4GGcAzNN+mc6Xl0MvuxxyxVAcIYXcfk7AGUsifhP7IDHRBJJAyinWxArHzSIy/0xmXFXwSnR7C
qNI86UGj9DtndumFjyfafh2hPRkzx3fV7F014n5m8aOCeqv3r1p+z1gSWzTWUweWpp6ie6vXQZ8b
w2hdW3PuDN9/i7K49aFsNoQdIt7WdbTlqkcm+4sSntM01SQo0BaiVAvF9Z1H+6gPbNkZrvfd329O
N/pcVxfIEdDbIiusJhQQGPhQuKCDx6eyFIiVROWdCQSFUV5K/zNzjrQD6FaF4++DBw8el6KuQSBg
9a5xt9M8429TkimpXbzFexrJK0oRbDwOj6Y/6P+Rso7bQzbOx2AkFepByuP/rmGrNMgxkUX+bIXI
+go+AYnkcq/OpoFWiW1WQpoD5+NumwA2tNgU051ySc+6e69eGl2y4MFxah6K12PeWPvHGGuBrL93
AP9N/k+W1+ayWGsAflTMVlHXzYn0pl4w5WQsYUA33RIBp79s+1O7MN6fiJIDfOk383naHPswe6A3
C1AE9vphkR+mbj6t07g/jMja/o8c3G3Bc3e674mqoxue5RC2M1xwTT+QmhRd9X+ULkh7lfZ6Ak2g
egAB7iWKlYiTdWRTC03V+p2liSLgB+lKTI5FptxdPbX9wiEybryxssEMXxtBvUULZbczZK/xWobZ
tPFvP3b2Aa+VKtxhG6trGEQFQL+0v+LqEwJoYPvGBnWxpwb7Cs3WQdPxLWQeFEjjYP0niybrRkA8
bqdtV6UYSWImDZXPuGxFQj9TMfWTC1DD3pppKe2u+hO4X/cCHqGKxRBwcMlxYLXQP1lV2JTkZZW5
Xb/5djYtiexAsHbCFdu1xJNqFr0DQZYFDH0jKlYH89itcVzn9JyqIqYFOeo5Ky6WBwVigB1m2JeX
asYOi1JwS0/8W2hbXAtGke6Z7VzwZdDLvprLU6YewSnOOw3IPBkNt81KErNJVkpAinMl5y0rxPDH
K6tQM/tXOVP/E7+lKV2x7X6P56CiBo5UoK+pn0Jt68BDP8+JNkVFCMcXWIDSa/2Kz6iVQRDWP1Zx
N0Y0IE+5BbmR2Zr8GJ7wwHet9EKYw//f65dG80HHzey8zppfutPd+4zloCkpXutERU2M/3oTaGL7
2DabMjWxNsRlfQ5RM45bgbbfG8VKcP92ZItWPfkKC+0mTo1xoCzpAZPiL+919QjCy8VtxOkyTvyX
aNyF4mwCf/IZRKzAW1r3jMJP1GXeXWvuUJh5yrbd+v2s0juRk2VEAEboBwvK3k0T+VpUTWzNsLZG
QkjbBw7WJANtAsPk198o25LgOQJQLXg50G/P+kB1SfMVbC1RmcsZ6UK9MC8B61VTThlZQmHH9ncx
Lxrlxm0uthy3ioMFdBfGnKZ29iRdc1btIzt+aE1ftUcmqQJiJx1IuX8ua0c2v56QKqdOmVmu66d+
uOyo3qtp1Z3uDIvoxDlcgNx9zIWH8jiYFDhaH94Tv5LZTt9rMZJJjEG5VrHie2Z11i/cf3fXa5Dl
SJft/sJ02NOEGZehpXacOPG0c+WiVYMsswBt/B+c1VN+zbcxPeFzsbifliDWeQQ43EpjCopLzMvX
ztQ3Arn+hYb7PJnph/K6fxYDwbg/tfEMsHw9XMW8i2qCIR+nyMoiXVl3QsVwMJ9vECFYN2umTqiJ
+jz5iI6U1+qTH6Rt1ys1mH04IzpSVhmFDy37oewuP9+P56Mv8pVb02r3zV+ZEe5PpdWUuRRTb/ID
+66HKdBHSBmgqBVWy+I29rCmiiWct9vg9piy8ItWFk2lR7TanMbPBgaETs8l1QEH/xEIYrcNdkQk
rzoMgArx0VDkfvxuNIkxzRvRzriIdkCJ7ha53TD66G4UoAu6L/0IB3Kkgm+VC37iqrPgoAz6Pyd7
YkiL1g8Wqsd8dvzDnofg1MU0ifP9r8To7iNelqjg/8cnThqzb3NUA5zoPJQiFqs1hueYIohMv0HW
TUvMJlmEGjuLuO7gGDgGxIBVd60dtryKq2xUWNOnvQxHkGS56nWXMzQ5cw/UJ2kozmKm+TS0QGYv
RNsTmXnKgU5BqrF0jVdXJ3gGdBTBIpzvlwLz8tks6B/hgw/17pTXgXajkz148aCa4JZnXsHGJZ5H
30EJ3t+6w1KSYJm6VCIzO0QUgqZd+FnZHMzsk5gJjo3mQRvFFoVKj2LEli6TpXCDyo8+r9r7kgNp
QDFXo9wZKiH2FXh6EaHsV3MH+dDuMrGlm5yj5VHoni8JX9/Q1LrGT62tD4pdIwIiUu0KRIxKr595
aCekRcF+f8TimjpY2+T4NmhWbGYVo0rM+gpe1QP1T5zZTVam/VeSuYehXlwmKJ4QIOrX6HPJ0EmM
dzRN1uottba82QFnPblP6nRM5w4ir3+J6a8yvIqzrRFoglg/CBzzn+RJvLYY5C/Wow87ztb8KpON
nRaqEOo9achTEiw+KRGsSMt4c5OIw4uOSuuohPZAvxvaK41ao3kOscTFQLeJIcZM3A3IoyDUHZc3
7hk8evhYN/em5/ckzsM2vUBMoLm9HF2WUNbT7CkPkMsgO9V+BBqfSRyStnCf8gnXHSAa9bBmKPUH
FQ9ICDsW+QuEyv/SeuuMr7OPqspopc9aEo3HJpciBCLhx18OV11VgBRemyOhBBBisiTxw9EVzAFR
R0Y0Jt2ujFXee0sTDNdJm/LSAMhYZDVUsrTS6S0WZzDnJhftZa2eHjOejvpmOdtvG9yoblXpmAg/
J4itT4WiVugxFXmz1m7sPflH/x6QmELu3bu6cozkB7yIAkCxmjz9HJLqFBjpxAYvLvHMt7TK+ELm
587iQKiZSQxzc4E00xZTKYDb58yrgZqSojEEyWzlsHIEZCNrFPvKHXCfxkVIsg8NM1ghRYUsnA1R
cmjwy0qXqhz5kAiV8xHMItwzTPzAt9hofy3jhn6IEy54wtI5vT0aQNl6+H7FxTf7pV3/c8cEWh/D
xd8hqRxTHekCf+Mxejm/WFQg9D/nWV18F1GmDYFkUkKpoT6QaDuFZJCp/zFxlx687WvECzKjGGU0
7v5zdqH5Ln4c/dT3eIvn+TWPgqhFAoad9grfxWQrNsK1aWctYpP+BWXjzeXQJyL9QQV1uFdJuBS2
DTI+zNu3vCy1t2KZBPBji7psoEEiou7uVgs2IUHDczwFcCiZA5lVidu2+9tK1H/eGHjwGW8Jn3gn
z56jOIZZLVQihium89fBLSkqd6dzvbfeOJ2twkj8WbykzxWzzLN5wmPRmhafOXaIzXWtSQ2+6Id9
xNJbrBP/FlyixaZsxyh3VELs9HwC5CSXS4N8IeIXtiC7QmQl8hO3JqZ849qPGPfHx8QIvjhZ8NWc
lu7xOJkBDa6cZUCijvV699qzl1+uOBNVL+N9CFP6qdLQYpE5QWZXydWZW584t++qOH5zf4mz+UME
MnCF1Q16V+ZtfhuifJf8Ky2cZKcM9I5V0JQwrc6o7Z4T5EImF30c37VTZbaWdwY21OZYaKKWKrwu
5dL0WTJQRgNz0SbYT2+rbNUZITrVCQIvQSSUDiNmLr61By9vpjgM/y8530O9i9G+V9abkjf6LEnI
RhlW37e/ociG9d6vygAYYXGjJ89isePDjcRgEg/+wz3ctxwtDbfx6lCk7+7w4IhWzzxDKkYgSg2p
VFmxj01fyR5mSpLDfA5w+pK92L2twubbbLKYQXuZwBaIvC6XKOqt5H8Q1Ty18adLFsIUo7WxdXO4
seHisdIQs3yaOkoq/A2RkyeLpH2bSq6QgClpk+OgHDfnMamONwE7Dc4Wxw5bHep8zrCkXKF5qHL+
LiRuapo/P6LfY3fgAdXo+6z1C1sYVuR9comuXmSkSOAAHNAFbo8AHkhxGdMPGQ8OsW9DXAzBvd8X
2lspbUGo1fyscZiQuyLzFUu5byQiqmrRJl14A7dW+AxxciRfJtb6NfbIsMXdDaxWuGgRIVTOyW47
j8Qj2nI8xhA0qJT0+EPlnGmwWQ3vM1x3pPvd778s65BQNt32Tn0yjIgpZn0xUAQscVkMPAZr6Vk5
1hP5pLduq6vULqA15zS/a2AQbAoqkRo2C6sZ4PRZzx3I3Bo+0gADH9cYAzIZZaQOGIewwGzI0dAs
SxuUA5Xxi/NFZWS/NKgnVyBJJ0T1nIRdTqsSJ0wAthKCOAlCFrMs37WAs8j0FYvSBXeAdMnHiQn2
TmGWus06iQyxBEa2NZhQQIdTEHaUmxV+m6UGPtHUuGvS6w4BqV8UV8xJJnMvWzGvg7bnssvF6SRE
lFS6vYVhHFL8C5Du1JGqOui9ipnWyjJ8jTSRTRSCd9ZK4y7eF61kzObYtXvybPKCrl5B3ELjIFnL
N2izvjFoe+lUl+RPrjXhJtu1ceeMhu1M3xNDFJRnlD9ydqPVLvGZz13tKWXEaKrflJYypr7L52fA
PXVhw4SmAaWSTXRmXn4bnYHtQM7PE7ToE2zpf05qRrnfoZ6pNnaoLy3mf00zSXkcHH6DXCbU699V
IayaSG3F1HWYj1PVi2rbFA6+4eI8kHuPC4j0hicFWMX0zTqNoAfrVgCZtPpQTSKwbxAWR6JQjOKI
RxkwpVld+R8Pd9YGBISvwaShTfYaqOghGDV9Hu9+vqbcYv3J5ZpkZ8ziwbxN8e1LyqmURU2iwA2y
EohfjUlpD+SoQScex67+bxh+fFPu9IQLMXFWodY6kevUliVYWO10hzbaLh1/NJ3Jy9WGt2hYAs4Y
wXSM5xZeJRrmZZx+gQizAJQ5069SNNPwjATbp1bmDPeR/8+6eBwWkCloVtv8m2/Ik+MUksaQ3VYW
bWi5FOa/i9Pp8atb5U20qcYj88cS7Pf+atZfHe4g7AQ+RxpBZcxbog8OHlfqJSMSc1M0y/EApibC
GGSh8ayzizig9eG2vqEfCfnbQZODhbzXIhc4p6oTbuvDbo3XGfkQbpZCGD5hT+MmVcjEmeP4d9k6
vazgBm85KWMUSgSNLDGc6WH0UbXKGe1+CbQwX1kDxyLMcg/ayUgJWU5zrX3T6GzqV+N4maEAG0pJ
jQAwk4TiEOnYIOrzpzy7uhX05aTbJzYAepVj5Ogi+9PgMW+brsCRdJSC7RYw9tRKMFFcP2ZXGevj
xOQGsH/EnRiqH7UZiHQ7nUr4NoxxRvcGKHZBCDT8qnYTiqxh52oAUN5y1+RO2ftNsKBQDVfl7wrQ
KLUdOliXpPprkgmZx+n/oiRzWC/aVLZ7glhFlK715oFk2FwvptXYnc66ntePnULbPcMNTEIJfib4
5ZcM+BaeYJq60FaUbnIrSPYLES2gUb1KX1xiFvhVKh8TxAB770YqxREeuE7GZX7A9ogjSNaKkXeL
g2pwCZCHECvcPilcabd5NPBK0h3b9qd45fopDr501Tue2u4PXbp+xcZhrUTqt2c2aovuj0j6RBkj
v6FGNco6rOGyiMiBn84qkm7CeRfIkxqjaj37xU1O/kPODJ3LjFr+SaoCs2uMY8imdiPU5O8utv/5
rbGjFKnRz1E8aLsHRrsG3X++7hstjlgLRxPERYnu/GQufA9gFPEJiEcW2zz5rI5Tqge8iqK+kvJm
Ij+5GV9811BMHLNMXhHzvud6RAZKchF/9M5g2ygYcNxWsWFl0R7GmV4JoqXncW2ukQnwA3duxMqs
jZSJkb2al70afL6vQiH+9XdzB7daZ2KnAOhqzKCJCDKuydxfi/fPuYuyQ6NWZTpf/75Et6MFeg4v
1oo/j3fdyp3mTKhxhTP4lk+R5T7sv/5oEQ9tzisLDT5t25QBZRnDkOXAH0iNWUgZ9q+I/6TgPo1P
AiceeS/PXLWsedekqc7JM9mXP6TvJFF7H8aOjsaZMQW0p/4p8yhb7Zyo6a18mt+URZ+jjG35BdIh
dUlerhgf2H3Oe9dn7f6NQoLDcs/815S+Aa/zy0EkCbKWJvu6mIAWNipiaajedvstJ+AjoVpwsLWL
Y/PgVJFJRvFS6At/+VnZKv6M2GSaF3wR6adBC1dEE2JZfmf3GsqDzplXnhhSIGsl+DtieawOT4L0
pbeDfCP85cpyB5PLNVTx9JDrncfo0OGZM2eV0/Qk/5sUi7u01TItepzH6/6lvn+M2Sk93ue2rhQN
91oBsUS+mzMUsYwRUCDmrS7fAsbgO2OW2J0I8rQmnceooK9T5B88qET4kt2MkiE7MwE5h3f57qfo
SmgRUVJ3Eoscwn4n4FSGlvHWynHA4UKrgLe36dRf/gtwVap7/if+tudx414xYrBGGb8HK4G6s3cV
4Oc7ewwTpA3kDx7cF7SL79WzRk5v0/W8e3jol1BcsO8Ld08SPxJu00Zo+FOvZJaSE/tkzEGWdO38
MC3sjuqqQ92kZUzP8dxZI2Du1F2702gNqTwSGe/uIs8OXIcPOih8JTi0lrlFpSRXJbWKPLBKuDZS
3K48L8T8MdOeAc5p7MiNSaLAwSb1Wog1lvJ48ddqt8NcDbAXb+mOviqpwJluT3Vnl7GK/86sQY3p
9hv8tjTaPbj/OPl0mDTpPN7qKPuU/8mHzjBzBZM3kJ0kn4qHNKCASCCcLqYdsk+ZcAJ0jRj+NSSm
h/sZFMuq2yATYHZzriGPGw6aP8iR0/5kDoFrihkOXbd95clrXrualEjCYGfS17P5iCtrCkSIVpYx
IA+1C3jLuGw+GgDewrhEW67ReFIoySck+vfNYj/L3k3BbhuuDD4nxojvg3682jDsbNSbL/nWbITy
owtLXdNPoVpojgWe0iHsgqvDBFJCw3ZTNS15etZzBBEQRxDLprPYH2Z81blFyXPjMhhL8ThFVblO
ilr0JbjIuEpoSOpvbmkN/NZRfIAZnzfxJzgeG3Q5JoWC2tKPWs207hUuy9DbastADukFkrB5QWaR
xDkXCki8cwN+/zev2qghYc7LGq9m0YxwyDUc0tXkm9ya4zwYW0pkt4cUUIBfjG5qmGrYtDSS9P8S
9Ge068t4EUT0HXKV+VJR6lYJ0QnND4pC1awT0WaQNWT+hGIJ90+11a2Bk3Hwnh5Hw9Mb6IaFyce9
2eiJ0pF6xQfrGyDtciO3nB4aQIxYSsylKVINzyrBYdgEpYLjOD/Cy7HJii6VOBnJUC/VP1SKjrIh
ZS9FjSqrxwMOlToVwVF9ggt+E4T8IwGIEbS75Kgyh02SCVe6vBmPuSCgzWSIlgTGv2QD6Qfud5Qm
AOYXtLq+gLtyTixIhCEChseCrBOiUcpLeNZHCHU9vqEbSAA/Z3yYpM0KZrz3EOn0YwRkqWRlcHah
FvzY1ZysKilxEns+bDTfjbn5YInl83jcTvVlfdHkD1HkzqlG6/dRoRl5oW3TyxI7XrSaxjFaiQmR
T4UKcy6niZQAd8tsgsD18ZvhfV/T2syUUaZSeHZItWJJfZaBwDUbdYf7wqEQxpPjpe3zVJ3N/Jgx
8036tyxiBOdmBswEklsrZ1mXBw4EIh/W2zODl7z9H/HjfKkDN2S57TopHAoNd2Q5b6DEa8ECrwox
7vSaOjDsMQRy+dQMorM/iP9oIBcQp0OKGKqU2A7GM2Ws6XR+x5IK9pdqC/ClzHzh4uvWOTLN7feS
O0zCvKd6MmclLWuefcINmii3uhEoX4JzAIyk0Xt/tp//0kPfb/+J+A+AmNEqZDd5hkOzo0O2sC6/
tw2S/39Cs4kOyKTjY88GWNXq9sOtiwHgSA2+k5aJxsiL+/CKUY5m9mVOPPSjo+m0tmA2jkr+tKLH
PU0nyHdnPMeHjTRroEk2HCU2Ycm/wZxNX2yXAk657r2sVuXf++fvsyZR37GVTauvmpFNxnHvzBSE
LB3MiR6dPr/Udhh+2ThLOHJbEd1LmUO33EyhG6/pRjN4VCCixxdv7HQGTxkZNc4Il0kQOgadEB6E
/W0T6SQrTvLF2219/ONeK2+lKkts+gPt0+hZUTFkm0grwV8NPbEMPBJcoEx8H7tduL7zP48p7z+q
dIRcsJIchdUNg+mkL2OWH+QEv+ME7oD4rqPrrsslFcYxodJgu3o8b76r996Mvm3tpbfw2LHZctaJ
TDW5GtDPO1zgDgrrPIVjeYxDXcOvFhiRp6eunHAQbHwOKHDvFY7zFL5pdlCI0u5Uk9bnHR/Ukq/w
dWOVleYZY+0vj+3DlL5RYTgmg5TRUBKlRdy7Jlyox4qp7lbTXI3xKpZocv/GLNceG2HJaUco8N8Q
ZRgr2ZuGpB9sPFUOyvExrk839KkZFG9MW0KQv47wKX1MWzBjxSpMUeFq8FXgqubjgbQrBU2kNPKB
rxPDtkd/vhdkzZkpv39ixw8k9ODjptizO9Y8LFbQZidCLipHJXh0MRahwdDqCw76tSgIMhAsPBvF
IUcvoxvWlanWl5gqgZpp/TgzKYucaJxlyRiB++2CKRQHtZoC4MiPuZg4UWLBt+HvVNa9/RWN5HKJ
uoMbmxbInETJDpwMVHa9/9LDlFfT0rvwdKoW9UJzRL3KW3VLtmI7JtXUAt/V4gN6CzvUR2U4NOov
s1Xhu5g2z0PwYKxF1lX+6yxqK9+MTMNN91XM8K9QXekKq1EXgVMFjWp0LPSmFnlP/GTq9sbtoKeA
QwkTMM6JgrDhFFMG/4mzowoCTdIR9NtqRADdGDenVKdbq2VLcCKbHACcOBPqlKou42jH2MTCaiof
j5EbNBWigZ+K2XiOavhBsiI0c6Gr6RM1i2YJ+6ifgoS5HzNJgGPhYOwEJgYgQSSglOuXGY5iyBnW
gux6xW0ayYiM9qBzAjLKlbKZ4Qe7qCwAKot7iupN9pzV9SSfjegO94eWknvoYgYMQSuL0J6Sov8g
3iYXlc/3SGKI0AnRCcA0dDT1/7jUCdcvIF+Y2b/sq77aH6+BRXcnXdz6SaVGzFMdWT+WEXs8flYQ
qxobaND/KoQTMycMakKezENcpTKnfLXj9uqsZAOX6e+UV4zShYX+6bckmIzGeZo1xHBTlXXyAuOB
tq+KaOdb0UMb5p/dI9HR+ObChkD8r+Yj1I5poBnssoA+CG78Py2MWzPzZJGJOKxIHzYU+mvcDOvb
ow+5OOuXjQLhsCq7ap2CBb8WhUBBOU3iGu1ENSMdEy9AUAzPa103Imh42Rg7UVKqFqfS6bTpLUJb
AO70RKvXEFi+Q6hmGwSdvgWx6lpm8dK4hDLG56SO2QMxaiZuSv19x+tvScz47fCZLMZGSTmFJ0/K
gDEFK1nHVcH6rqY1fLI79fbDqrbFFfRsOTG52rAdbbbpM9aqnGj0IPwcG2nB3M5yac5goTEyGEAc
dbo05kD9u/Aooob8rBs1eSkFvwbt3NKWfzvIKL5Rf0XRIbXjbhoKVMg7H9ZGt/rTKqWO4ypFYE55
+0p+J6moXsmUOWYT4tzaJzZB1sXnDXO8mBt/THyTzmdu9bYRYZey3+sz5uiWn3uwJqUqSjKNiMCZ
DKKAUdd93ENtRpHEnzRN0Dw7ykc90KOYz/7iwI6VpnPfoFKng2eyhyEZRe7jq02kjTEGWtNbCKxf
b9L1Kcl3ojWwjuf41ewSrJ7tXIyBShM104rBqQ5DOsjwgHlfipWPwvncJtdCmhoTavcPnT5kUzsN
FK4Uu16wYbIFLfcOVns1F+U8EjjJsT20WCK6Mv0M8oRC2Rgh2Y17zHTaJ+vStbF5yAwLIGsGb5iO
23nRcyrdCgm4OrqOjGmNi9qKqLhKQ1HwOC8fTwUWI4VULSiTCrgidBBlCB50kO0sohYuAD5KaKL1
/sgDGwYDEHxCS2GYtu7lMC2SHOQ2SX73dlrzHDUJFMta/7XCzVUYRQRqAtleJ3QYQKZmuXWmoSzC
AQLa/O5MMp+HoO/4CY1JNu/T4ALdnRONYt5I5UaXQlbP/llSKsjHSVtQoBjX/YXs6NEprAKZHNVK
FZm+42i09KqSyslAeVn8t56gjZJCkmRXQytqiGCHm7NedWNeEFB9Rf8U262RNH9pO5ZWMhPPNqaI
UgwTzohW+d05YEUnnQBs1Oo5txHuKDYmPMWCUT+vIhahpRCFkM0+bpiwcRXcULdhlbt8p3giy6aL
LcPQLDSFoHwfWNocEOupiQzAp8WkIGVa9RShHCKgqdhkDI3M1GZ9/Q/sJx6Qu15i2PXwza3jIbQl
lasndQ0leAQr/7cFqFqC1KSYWvqMSGdjXTNiJdhkt98fcWGBPcPfPVIjNB1MHam1B3urka1MwOc7
rI7qwcjCD3eDxgkZx1QBOcJjtu6Tf5XLE8xk49/4SKPLtsnPynbf/xVKNNNzxkIClMFR56XuVzlB
b0ND4fOwdOibOlupT5MreNXs14twRLc3NQ0oo+FY+pDS/GjLy2K0+Vp04His+43xYts9fDG4sNyF
rAgaRcjbjr+UH8bJBYT/GTmp3CKM1zDsQppYC/x8XVeoeZj4ABHCUjbMCDu+qHTEaXwePQ1P1Nij
oKve2b7/Fs0k9YBM4Nj0itxxCr6vGFjSlpBQPPX/Ec3D0xGxrsMFY7N3ouql6J/3kJVg/EHqUJKJ
SXDXq+P/FVXYYslaH/H5lAhc1tnEgqJtMbD9sbxndx7e9Gx0p1x4Jgr7sWMRHgk7TuPqSzECguW+
SUpzBnwv9AQqPJPrEKvQP1GDWctDr6f5vfuaHrWhmtiyLjq3zl01h8CQYutisWtY6XgWht5IJQ5p
ESGyYzDYLlebz0cSaN8n8OzqYoD/zbyKV9jdwj0RtCi7kXnCNM0Y/UUZGByOc8YzcDpK9cleIP0C
WT0fUMo5LfcTC2qQgPthuQbFdEbvBRTF5M5K0WIex1eMv47KYhd2NqhPU4cYCvVSa8LPtUHt8sbZ
RGtR2EXMeUkFz87rKmk/I2HVKLP38zHGHH3cFwEX3Yt/gJIP0YoHwsYAwgQC/PRF4JVs4umILFnN
7LECPdE9ajj5qwp2KBcC9yEQcbIFwW7cAFIcOkTmAN0S1FOFDbsnfy6usoGoS6Ex6gLIpwAXz2pK
YZ558Iraf//UTurUCiJGZ0FoHJ6tPtFO0wvCgCo7IzBgp/7I6JoRA9MIwSy1x03PfcVhAwfydr91
OiFEqdSxywr0v4ZeYmG0f7Wkytip1PAbpZZi5mdAVRrZ+BRVJ2mwB7sO3WYb9GcMJWuSWbCaWIqp
FT0dvlmIVNYDAAH4CNk4GRU0f+1rXgfcaptb3DKDhK8zqP2WutuWPmL8EaxWXSLCPzBciNIFsrIk
o0I1v5lr0rGd9Mr5za6jTPvG9b/oeKZtyUV+zpaU1BdHwntoy/q/Xy4VfyxQBlpsWx76vLF44LfW
u5Xlyr9tuIa4HF7dVotSsNQ2HZ10+jaAyEFzWr2v2ZTzS98OP7KsO+g3bgvyORWhFEe0IxTQ/6NO
7O8eGux8D/rAwGC8H9R/ynpzSJETB51DoeUupyfbOMRyv3iDqbFmC7+gxIETYJzlLtP2LFHi1TSp
DJy9Ccwc8F+gyw8Z9xOAarLrvnYKAbBRBCJ+BVgQk9hhBzYTiQu/Y1y1eJS41uQuOrlF4Ra5uIAg
ZgoZ+h+uIqYEyvScsLN641EJjs5HUMYMC9cOkZPG2nYScQQjhRy3S0yasVNpN2LhsYv7J0kxmgpr
MyXAbm/yUw4c3EsUhCl/KiZ09R9lKdar37O20+INakwfeKhsYZd8bsD8gGQmy6Vt410+gc5lJLNn
yKuwhIjkiJWfCXmAJ3lLs5eLqhZT6vYfsEFlpEpYkUVEi7KEtJy6/3/VcU253dn83wBro9aDOXGU
exbjAMVBzUcZqh06mRHuGh44PMONGCYyQ3QWRwInq5vFYkm17rOQcXjx33YQlzuZxl5OuYUmlpus
Uamh9KvXomLefaGcT2DSIM8LD/5TEzg9hCovtdjv0yj2JHYWQb9w9fUey4Hju1oL2z4qjdnJrhEI
iKydfxZiUz2IGiVVsLO1g2A2I11g10RLrscoFWk8VV4yEZvQLohPEwyIRVY6tGHaUWbdI7GwV++N
gYhxQZH9n93kTx+i8E/AWNTdXX2MUHExgzytokNct0K75H3iuFd8mfoY/eQxy2/pEAzEc/joV9bK
xFJqlhxVPxny7VaIGJva7wJXJioQB4+bQbrTTvtmb5jPDF8fAKjIkdbe7wHkTFCXXMxBCAC1g+hr
FKboSdR3n+DCS3pdltxE5fKO8ixv1dfwgXAXvODc1syUrpPhz0HNpFb9Om0t7bFa5yrJzf90Y1rG
ufoXM9SJha+AeBuwKLyDhbSZyajTXc6vEJIsI7euP9uTLDCa2ZpU6YhJ/LALFm7oqzwSA1ELK8Hv
Hb6iR7aD814fHkhCpoZyu66S856xKbwX3/3+hkXv5lKm0wY77x+wmS6yl72DA+k9CtY3qkQ8IdB+
UxGWQ0j3uQiwYsMI+gGXXO9LCYvIjMkMv3t3kFxgZmxL5IsO51id9r7U/gi4ZONCjgnJXeXh7yDB
CcUbeewZJw4Ylt07wEJigDOo6/wDh9zTRB72VSyiYmda7zB2uIjMIbGkWRQskqC4oeB6H/p+Eozw
nWXir7yiF44lC11rJ28gcZriPNgSYFm8HoMJ6ZfJXbnJ+nFa+dFOHth7Wi1leOy2q845i5HigW7Q
sO4UW/aeW36m2D1041eg+goqVV4ntZ0mdd+CCJfPNfleqVPaZTdHX3DU6gn0wX2fmPArTxnME98H
/qC0ACyHymWHl/lPLGx8uUSLDFoZHOUMcw387RX9jdZGLbvgksrcdkgwmri0h1pOmhBUMlYgUupQ
dk5axJQPm69yEwO2trJWPBwMHZj50Fov6Obqm3cvnLf6tTVQyA0fZVO2rzfZOn7LzLwHKIxhLDqW
dKy7s/URWIwNwH64N29i49WiaInDv7Tt56z2QTdCDGoD9jZn4i8SipzAUQM/b4McjIhL3IHuqzDd
t26iHC1DCOWfaw32ZUYBVEDUjq0me6YXTu6+lN/PSvTmTm48nYRMoTrEukGq28B5bs2MBt0uKIrE
oMczpW/1JCbGXhVShWo2NaaHxAqImi3xmvQxNcqCu2eu92eLLK4VS4CokGbe1t6F3JvQB2hy9IxL
RJ1kj4g/fdV2ZhoN747hXC/cCdh5h4vS8MO1xjc0yLSVAIH28oWItU1blD9bdF7Wx4m2PyenINDg
lky7/IH3KGC0nswhQhZ/OkIypnEw+fP1RLR2sPKNwTG8ut5UVoeExs9mYsGKI3yqFkYtVwKMj9f6
CbR/vPKLq5zYJS8qvMfvQzfIp2Ocw9+raJkS7KzylWzvCB1cNuummrDr/zVTojdv5d/w/3pAO83Z
YQTpVE6yO15IeTv0kEMtJMwKFxHl+3rxxePSEOMvcW+DetCI+5E14IGGo41hrwRRHycmdLXhgu3b
xsZEpzgj9iEtl1i+YUHLHl9O44HLW6UrXmi1pT7grLqOq9eQN+rK9Scgyxji4Y913bo+SPPwWgUa
+Ko5BJAC7h9d3NB/XEWMf4DTkalM58vL43IHZf8cW4S9vBC1K2x7HDZ8s8QNt/0gl/kQuvTc4ho0
KP0LZdMB7fhd7TzP2439+tZwrG8pIGeUGMtloEyvtIwheaAzEb3oOLo4UMrNOY9YY5lguPSo2ftK
/UApOv+pElqw1fdrsqFfjl7BANBRkTBqvYFB28++kAE4k/G4YIBs84iRZbe4TXSOeU+X9zWjkqAe
/d2eTr+SOIOkI68b7DCGiJlShqnh+i0C2gsccrGNIZ2oZlvewGyxT+r4XqM+ECyeA3ULbgIUPpzA
zdc9idghp4jUNdeNDblQ4VDkK67DzAvdrJOXgRKn4u2tJ32SeoeDXKBe20y9jIhAOoPj5xOITcrv
6EoHXlQSj8CErRdKEHStCiLt0WVPLVYT0pCJvBcpoMFmzJfZ0oU2xkX48EasCjF4Aqm4uBF1USwL
zssf/lNF8uu3vGPwlUhnwHKHHYvIC7MWifTan0G9pjtyRL+8crjGI7V6YFuNQFmkWtRDssafbo4l
qoHCfd1pJWKdv3dD+Sudr2BdkzGp51kQI5/i1NXP2Nkk7pfDn3Lyz8Y5H/4fMhIq4c0HExv/5lQH
BTxMNO6FelZfdLAiL8R/BIaCJRzySvx4oCItvCgXjoTlNKRdrnls8RLLC2/E0fkNpYH3vZA2FU3a
UloVF+I2sXh7nmcHK+Qr2L9jVF9pVD+5YlX13/VgK/OlMVGrqutrww2RCFZIwvBmyu8HD5H0iMow
/aFh9dfbLT03q89obIXeuIAPJGiYR9opFNjnI0S7s6ttB3956Y3HsGCYO7Dt/sjSV9TlcovrSMHe
EZtLz+TwMufKYbl8nqNYU9117bhLGhG/drZTeQu4zaqg2YxNxnqjV4tYwoHzqSxmPGoKkLeGQpmG
HE714P43pDTA0JrZx3GoRYrR6vPk9ylK8JF0S9b7fsmDQK27pSZC8xrdX5Xa6+uCNEg9MBF8GEpI
YwCd52/vPMa29ZsOxpNOOflI//if8RNaMyemKScM/pJgexHKSsVoUsLYxSM0JtsF19y4F6rQAUj4
S31L01c2bVVG+ITOsGHLr89cKPSeS+Mb/whg9Hf9UztqE0bYPHeFU7y0/yZBWuM4IjvujM9mgVHd
U0JffqpPUEUFEhezHe1xcYAGr3qa7l1B927FbwQXdqEvcg2SlZBLB1ZeudCOyVCPkqG5H6g4jAR+
lCFsItaQvfrvigGBj46SmPFvlfJy8zwuKE8fkeed2r4/LTCRdKEAZFyjxLddJL4XZp8NEyHjv9b5
zzHsbZa0DQBYmL8XniLqP0d44Tu7OohceTw2y9tApqFeu+cwWDmCrmiV3r9Cr/BDMf0TS1/+asam
OY6K8biVCrke+0OHJyyLpn/AS0VqHK1dK+wnw0mN52cEFQfM1YCAmAmPDxtRHYJfJeFniuT1JDNZ
6zeiKi2BU5054s2s+6ca2Mtf6DwDtoBD2EyczAUZMTXeWKpNi4g0A2eMrQMWxvMyd8o5wje8icuG
+7IWs/wSuuxkWJze0a1ZCKzoy9eIK+Y7asx01ISjeC7RYMy7hc1MUzc5GTnBZxPgCdPETdpq7q1g
z1zDXblvcOLhOLYWhSNJXdviEDTAx/KrsnQlpIeK+mHy3xLuWIk6tBAyi4i871C0LMpE/qo6RjjU
G44GXDzIysQ57dSCmiPdVri7Th+pO1lYRCPMF69Vg+Q9+pKCA3uefOe/eSKft1sA2FeZkdZh9HRd
leaZ791R7TOa4wqTcusJmhrRckp/ZvV0KRL1cSADApC23uTTRZUyKo1tPg8wsQYJ1PsPffn7K+DB
eWcOJSSVtLc4ec7JZBtxdw95fLzIJ8DzqDeVdHELQwevoIxjgnIpVAMOKNlP/MAG+X5CrwHJfbSk
zIj4PfOTVhbNnAVzTTU9+UUxmBoCFsISLPSOAPoyJQVhopb3LYQkoY2UQj2akF+YqF7c9iLsg+mn
kzHWEx0pExIC0gYZpp4JjCD2Go5pKvER72N/u+kmbp0ZSGjjt93ZmISDifNkH8/jHHXvc0Umga6L
BHgLOfJ2XFFFqrZToLt35QvybLube4lOGzvN6FMLy9hOxadZodYfUKvVg6EHTlmCqiqheOiQxPze
Q0i3u/R98caHLQE/B6yYJvlE0es0MvFMuSUmfFjnI+BuW7SIdwAgHGI6PWHoxJLyg4Q8dv4EOtsL
lb5DZK5vtSmw2XEb9RNoIcmCcy2b3YxFhTjr6YRTc0ffWwNMTtGgFplXMV2gD0sDSaFz/0lXNJgw
AMyRIryd9eWeeVe5qL0o7JWEj4zzRsEK/zLhn2+cUtmV/jBM/ifg6Yj9KVeWm1ED1iGAvCX7MCzr
1nchc9iAz8Tq4GWc3pWQVG8XbJu0Tmk+uaYkzPIH1gxkw0FMNYh2j+953s7Y8EW2jSb2YzPKrbQ6
j1ZBFsoydJVNitCakULQUiZYYHcmDgXdFxPjVr7QvTAMds2TQd/vTEnqIFwomAZW2mx1gOwqC2fm
Lm9BVn3jkSFkpdI6dGAnYXCj/ErgdY61AKBqYRamsXbBD1Q71G7rRs4j9YwicqklFWShwS5klwNg
OdTIjHSAd5/ceLejZkyy5ogvbWDTY4WbNaAoaYQysETHlB0HTKB3WSbF2JOxRPE+/dfygmNf919m
uJYQi0km6bf92Q9SRPbEa7ynQJxOlzKd8JLpqBhdgWAp2pSLsZyhyng/8+/P1Ub8ylhB12xky0jL
qd4GOka5EWFhd8XtYV0TBWVwyQv9IpR1jD1mAWwfg45PNGLiEBIeviiDnhsVKb5XVkyw9fTawR7x
wF9RMlXSZx7yjd9wHtdcdrgYT4zOeM6P2znkAMMTcs0dGRosGYf7Hlb5FwrS46DO6t4fxcGNje2a
koNXyMmSn0m43ez2Sb67idPAHd05YFnJ8cBLVdYeqmXty46Nh3++sI4clP2G/jB2dOUsG4REuoAZ
ytGbgFiLcE3BAPI9zZygx5d7O/z2scnDCkh4TS0hD2S/MVXhTbKDlum0eEUzPGqc2j4mUfwxGEvi
EqALavNPw1SjPiSFtYtPB3/p4a+lM5Xg6HFVH3rgGvQU0prubcrnS7b6peMk05fCjY6Af3JOxaYl
doRT2GMPKq/0VlYK15jt3BXBxCmjOw7ivYPyle5px2qqivWDLCJuCOi10wmlisP+4lLgIE0RLOWS
D6WqDklnrLGk7YjYc8WGI5rGviL16V5+HL50113dzKsGCLStQJUlnmWcw6fwlkuQ71r69SOnQaMV
1KerdjeMxce2dAUyPp03OD303eMYGWdw+swP5Sg5IodiGgfaEpDTJcZfm1s43x5ecagUG196Hy/j
8egy3MlLahYpnYs3Pq3zh8JkKARxFhfeLZ40mpgRuxtodH74GQI5sH666jCEwa4Q3W0Ex+HwmHSI
I6dzweKazNToD53byysknp9/K60njPW5E9IzL+Rpe0GR5ecqbeQbDc1Ls8OR/rc6zahAop2bHKTp
/BquS1oOrjqNsmQRPUUbxuMbtKzXvQXlfXNZZyWW0kDB9/AsoRZi5ZeBl2K/oNNG5vPR1X5OsqkA
lU8u8DqK4EnoRzXp8hGumpAy9yzdIHAdXEl8PrunAPusxu0BghljeXLQnGQDLUftJmFgv9yMoPB1
PKxF1xpaIJ5CLnhvqBE720XNc7RADBPrbWxxL5ocFTc+fNZV+s6N2iUJdzML/PGUwdleaHS2LeuP
fZyQZiqsBK8W3I8+V+yrZ0N9e9QTfWMB68JkThLRSSkhpLQECmASvdNffjeXNx+ftcLEQFtt0L+g
1PaUD920iX6Xb3VCVp9Y877f80og7574l9CxwMd/VqXsOooB6PF9tIwe9rOVix5CWinaXVxIA2C6
Gj53kWdPkT1eEx4/gknAqt/EZEnZvKqgffzimaKQJwIHenAV4NlvP7uDmrvUfPkV/mZH737ebhCJ
/ML2MrKn6nttqy7g34x25tUWmRttMcpBsf209OrtEHW3q6wWNKFNgM8iM1vydurWwekIqDgW6cuk
0TNw0lZ1DEk4eO7yMyYcQi/miEcXnNPLYk5wRP7vUIo0Kx/MM21DDHZVQRz+3JHvoGkABiNxS3j4
WnzrzElSRM8CmbB/N9SMmNuaUHFLlg485cC1xkYHKfVQSd16LF1bkPNUI/yuGbZQmUBCJW+mlMTS
EWrDvvvO1OsV2jfzWyCbotOFHs4iHxU09gqwcpLEMGSa0PxZ0kjJ3KACxu4XdSV2++3MH56lICmw
qABYK8wR+YXP7Ik7Bb8wZyUO44tZuCN5hLBtRJH37sdmQVnKl55u500vtmDd9QToAJ7sAbSwrBG3
2AN/kTKzXUk3du/rfiv8q8/oML3KLLbWBtpe7F9LjrvhmUXgNWnEEnlcKW51/PoM9QQIHfpGpI7q
CYQMOk3KxKXDzdYzPOL3rVVDDNlG8SSd+NRL1UXusoSL+fZP9XER2cmTdkXE/7zD0eYMzoGZPsP0
5VokTp4kfiVEoEf4AE36s8BH2N1q08GiE1mCq+Qai8cHivsynDLLUPGyyIKOf0MqNL5VBsw+ifff
VuFt4T2ICg5bfyX+k2RRuWvp7FQlgnHut2m6SHh5QWdGQx19Dni68hXD07Q76i/jkI6XT5D8UOo8
lmtoXbom0NnKJjaKO1blhbY+HCqHYlKJamg90L/Oawo3k8DOhQNiHg/KRafRAYfstDW7l4iXzaDg
EEyBj8hWn+ilFnvUkpDcVDeYqSHDKlv2ntp3z4sD3xuGLkodCAyLcVY5NYCunOzo9XpGgkASLnu/
vIU05M/SP9P1FTGReDjgspjPmiAjP/J7VVlS67xFXK47XGMgF34Jqk1QDnhNog3F5UiB0Nw2m6dA
P9mMr7ct2LALR4QJPU4iIh4jyckc5aRhWy2OUm9LC/kQ3bRQtLoy88dUBi9u73ndKAtM56Q3+ImI
743z6AWQJxFy2KZ9XEa5yXDafTXGk4OUwgT++LR8AacZ7noYMJUoCuTY1YgHe8JTbDMUltWRPm5N
ZMXqw5mNufqdRf8X673RUrxHtgywYgxYWCYj5qAzvK/n/D/KiwmsT09ikHhnvSai1O08BtGQ3JXc
X2F0CuQH7GQn5JJoLKxWwrmKF4K5q8Z8SZVhLxHICIvVeNnUBfc+JSmtG/Cfp2Yvpk+jb4SaJ+i4
bwlp+Be5OVqVFP+m/CbjvRpnG4D5mGp7K9dcq2yZo6daYjVhk88gX9yFzKlzjIYnPgk/+LWDapr6
nT3fZLgjEEQ8DYe1+MBAWI10amSOBltz5+iVE+SWM+yuQU0CSSeDBC3yYEfPNZ1B2TfGxcp6Hkfi
30fVMEO4jGcgiQZ8yZlYbOYMe5ZePoyHzzHkY+fCD3MvHvVtX8o1Ms8Wfm7vyBWPupn/tQ4chcFQ
m6u90/wmq0HRsUQEsXmry5aiyyapxatuk8rwtjxVBytpOa4OEwGa/0VZLqyVcYgy2DSXoDr6WiJe
uc8ZMb88y+B6K2csjyGrE/bmlJIPlJkwWZHNUTHsbPj36uIvnakfdVpvO4r9pDvyLNoodPQKM+qg
CuVVEgt4+7QlkeKvAO8SwHYmA5YGFVPWQea568oN0jtHjI46SoLhUOMS/v0vItN0OOWiSYtxqJXj
KaEIOZljbignzqv35mX9EP/+kcjaWa3INcTqc0M8+ztqtlUNUsOs1Udz+pZJ3gSfB0CO3x7FHAa2
jCV5laVvGKLF/5thxAZQzPO1YUKESdEXIUAdVR0jHGPKeFkpSgLAXfBARmawsA2oR3Fdygiwr1am
PmyaE5SypC1E5UqGVJ3eBB63ROWLAicx3RCaZplpt8Q0Hf07w8F0R1VG42Gr4HB0R2Csjqr+rP6G
lB4iT5D/923cd+bBh12sWPV7PU+mcoIYFVU6fEdXC9OMEKS9CZXBeDNsJkPJ+e2JkGxbj3ahJXD/
c/srksJi/vGvMM91uaGEO0d2uZi6A99XOr0g9gkgoZYbM1RGtgDdcU121H4zl12RxE+c30z1VjcH
NYA9xd8CgasT3Ki9XBngFPNIwYhp/T/KxWHGuQK9RbRzWnOnxpXtAbD6XCBa2c/Q5+dLE3PveCLL
QaZxlYiQ2UIkxIe7qiGtVMvJfg6NwAzeiWtUjyMPnMkxPY2xdf0NnJdDuQZVo6tmjSJmO9k43alK
1YDNGAGbVzceZ7oMT1pV7peI2VKRn0K5ImSEsZTawuhP/uZ5HxfFP4EhyvHO9I6V5YrRE5ZeJY0q
G45903eGbDHRweM4GEBxr3h7d/aPUShGUTV3WOMBE4txyAov4tamgQt2XZeH8fRDb0KyXulJMG8T
bNMntbDILZXmB89G1gnX0dNSYyjiTnW5thUjCuVlUOmhteIhwinDxTFVi9l1Qws9dUWBscXRLVhT
NSSAIU6YsiJIjVURZ4uixblSJp5qK01omx2unmIAo4nDdKDPLT2YtynT0FqqeQE0IMUDSs2xWPaj
TiQfG8wpGwWsKxx2k+3f6E2d4nEV3+13p3wSuu4esXOJMVwl0SO7egqTCbdn3nWpwtdDjLadwF/E
w654sZUfOenKo+PXTIXy1qLOuJ3eTdc/CmCAc+GGlZHO/NzaeyVuB8rN/w/j5XpmnsxoCzVNaq7E
DDE7y8ifU73Ej6FxICxUnY8W662nlQnmG7Inv6+qn+BeVtzXMhJHnhZO1DrH2gmM6+ayteKKi1nD
RNbWfJDrJRUuLVDb4cpgmHQoy/93jvf4CSGaWclfKrAY8beGp3qVnQF8jQsqeAQVfQ/Nc1EIpWBY
btfGaWNOalU209tzfbl7SxwCxEOA2rZtxXvPWitIxHOGZ9Hosg+idxj+DQWdziekjFgOdmMp5Owg
eLIKTWzQqHIsz/XvvsdjNbcH6rTYpWveyRv/sC6GtcOt2V6QqgH1Crax/Q8E7cFR/pzn1Wew178G
+1ODe8Or0nMHjlVUVDWrlg04SlU2BeU/bfrPRbq+b6q/wfrCSIlCY4wt3nmwSeT4ZrERCukeqcNo
9sgCXiQeXWpQOEmW1hBFMYC5lk/Hja7/xLr790ex2EcAgPYr/voUk0/sGvs52jTqWUgTAyDEDtam
kboiWXmpQupOYkEvLjcmc0P4/V4BGaI35fwY/HuOpyB1XqFSF9JUoARmKJkodRmSuB+Ri5H0iEgS
0Vq20OisUguoir0EkeksliyPibQKZDw4SrmIPfgUX0/izCeBo6Uuhl7nIAcdQy2XDYh9qrhVD7ln
xu5Irjt9/gsHX9DuZSa0wCYSMuoAtQNLVQ7DdkMR36dP+1eLdAqG5j4WwPJFsQsGfqx4ljG5Vgbr
VZJ+sSGAziYkW0kvNcXhPj04OvJxBuUvQKdml6vgurcK6vffoHyMjApNtEfgNf3NOr21i3Kajdm/
UAtsIG5w0+C+r8rkA1MJHJO7pqhL2QuaXoTZQgk5lTrAar7It3sIxFPHlOtWps8oo77dGKm/SXnI
v0zJnS+w7DZ/v/3/MiIk74YpgRUIgDgVktESiWioLQYS1cp0KkvSoIalCges32F5xqWRHOgOYdZI
UBVJfC6ZmeblfhZhMvko6+EsfIfgpJ1eUHFBb4MlW+psQpskj05Dr/KD99D3RwC02MXaPaNwQk2U
fUdC38hxtPkWplMGzcJ8bJIyOhZGlJIS+147mzwTTMAs/5hfGah/RcVY2mWnEYwaTvpZtqEeGOwp
enIOftZjZQrhJxzVR+GBKkJeKYw0n8qiIIgKHfuvecC+ZiXWXJRN141vXkTlCszaRAzUOi0hp20I
PJtCp8+JbMmd5IbjiSuPA/LMeh3tFju+Gf+jK/dN9PPn3BvoZEsxiEvgQqud+dO+vy7GMkaVtG4X
THg6/07GTxKlK3918LQTOqsw6V0YJ60ypCxGRv+iGutYyGJTV0GNwxEuFYB0vbDm+tky/WddeHHC
4vct69r+goOC4wmrQ8uBtp4CflUdeRhqtqJjxd5KBY4tmlgnNPAutI7TxxaJZyCsEwQkCZprSxhU
f0BYGnSyxfMhpGuhCHFsM1VsbdjWD1k+LC72T0R1Hj0fU/L3pOf3Tyb9/GqXllkF6VOlBLtUOaC3
cfcQavm/vie14MKT898FN71Nz9OesVDjuMDXquyt8V3/vA/IAOe3JAEmwSblwbSC5es9RPx1gPJE
YBsJE1v3QtctE+UfGxp3/7Bgs73jjmLqDXEWWcqBZCtnzr3hoOr/a6u6FokBPnu7d1iLiNEHGQnB
Ke4fWkrtRgQkWy5kB9Qb6rQ8+GNk/qsP78n7APTy21Y/7datTP3SAcMA1eR6LQKSZIOnNVqBnB4p
WjgX5HLLtyB4AvhSg4cedFvPhJHazNzmIgfkbCt2GFtU9E3Hml4i/ujaBxhv38gOxyPPqR1Z7p+i
IS3nLFyaCvKkjfyCVYw+gblWg2Uu5zYm3rtQXf+nLidao1FXhgjgNbXW6gukLRCXe0kP2sKJhg13
C5Fr5pgb0DsZnr7dQm5tPCkYRFjlh4mX87bsbTjhil6JPWo/HzeZOE1vCd1Rq6LgIKIZubIVqpBb
fygv+QGQ76MaJJP0hrMqIe0qiLin8cNmUaodfrJMHgUNNgD/LSPgb3YHMZT7hOo0Q1oReZC1j1Kk
XUrJi3KeRGdLCKf63WWGaKxgHmmKMSSokEYaNMfQYhpDCyNGVQs4mSNTFLfWfJCSPpus9chlwaiJ
j/57fc6A8CBKyG7Gh3Pw1Q8v8I8NXD1POguRwVOqONhRXGnHBlQW21QHCjB9Sp1w3REJ32QFJoxA
3T+CADY6HsvrNtS8FjnwD05hChTGkbjCheTUOQ0TEWf4YGh48io3N6DVy5dJdO456weujwjW6vCG
pblqKttV0qYGGJAO8sCQow+T0JE4i/sSurusGNZ0r0EW+Pb+F0sgH5HKxHUCf0RXY0ZyFaFQYBHt
tSgz+tTaDrdNaA28Pu3NvkNjUZIYA6gVhNxzdaUJHL5yLlQC5WaO3y+91bMSSGxrUtqrLRQvgP0v
Uv5FJ+UjtimCjQEc5zi7vTxouL8DjYmuzel5kSj96i6rKwnFcFoO5bae9HYB4ke71FJ0pW73ytFM
/dZJZOHkpMb4+Y5B8Zo5PIA4a5YKXYQ3lxOw4q3JQ0I3ZD/mn3dlvvy1Raznh5SY+0P/3B3TacqI
fHmAywY3q2jnL972q+bPzHaoGyX5acA/Zxw/JjjUc9z4ZvJ3IrwnYmqF5bO6pPOrUL5gqTVvKsd6
MB+F+97vVaemqB0dw2/qIvBIRiERI/R1N4ZS1m4d485P9v+02sjxeN2XsQnEdHEIvhAW6MYBlf5B
8HJvEDUkj69q29DPbBM/7Y0ZQpUnwHJaAqDPnMq3XHQ1vMP7fk+LcjOQsfd9AEd5GICY1jjTFt8l
yaHF+/TD7kzbL5GyV1mf2lSeYGuSQUBHcVw/rs6I64xjSuX/sXHNnDsSnAlF7CFjD96ZllcBD4A1
CrK/CaiatYBr326fY1wYW9jFfyXby6lovuyhtsbMnHPQ4J2QtUYaWm2M85ePAOBWrY2jh25a0EHx
2Is5sezrXcSCd0EaILCjkc5NY985czjCWFTRM1UsZTPmcb0tRGot33V6mhe6LqNnriYhi4AVQQM6
HGvG6rro8iMhYNa9NsQeZcr09ZFgEPu/J8nAgamt0fz7Fse3900Yqz99PUhh8vGNrjFoNPlh2zh/
l1r2s7vhWrht+regnAhHj8dgKcv5VkWia1+aQWY4KpPBYQSUYKGCZgSqAycf1sLhmxgjQh0JaZ3Q
wYSlhr6qJb9GUF6pk4OiHdkhCxjFWLNSVhSptIKh1JUzKscIWjnenEGcriTmtzUaRjTDWkCqPOlL
3CmI/sCRlvLrvhjZOetO86T9iFAocLg+L73clBsJjScqk9VjLEiUQX2D6/7FhN3eBhYQ3hi0MiV7
ZQrpVS+4ymUnedb1Jdq4ONYiJca3bzop10QxIPat3IK+YRNxNUF9v8Bhlor9LLs4aUlmER1VtLe5
lQM1u1jq0MJXxkPMtGWL72iO8aHoxBSUydf3rCTXMQvJt0iYefn6dLwvZ0D1cSqTzE9uPpXwB9IY
3q1d5v5PSwjTcKXcpcKC/KiOApR6z5S7bsDaUCYNO631mz1zA9cipDm9j6Sg5NIXYMgviAsENVWm
wo81hGrjW7ONN1cy1wgvrbLRus0A0bhGiXjFuGHMjO/YKDc8yc7MhGuQqqh79uSfj+5EjkNJiMHg
YCW7IjakbzJIcsrGeS7tdZ/R1HoZqSS0Ffufo1NAIS2TDYPXyhliU0hIQjyF8Rn/gtFe+u7HVlPI
ICBNgOy73BOqpZYAaNkrC586yeEPsf8BBMbFmroofFtMpy28XEvePnH9gYSnq628lWz7xGs70Tgk
n4JoZQ62jTSy2JSaYLhwCAIJAWaIQd8vfLSque4UFvAJL6pT1Kw/C9gohqhQSNUutLia77f14Yce
87034axvf43RE7uzzDD/kKLpHjdO6+3YAQ+QX/p5krX2XUlpre1kJj/iceqlAGfEK1JqGBsLe32k
SR7K37k4UTG3WlztJn3agriU+xmvsoH2F7oIcxUWFS7TrTU/0Qew9IDCOAP0iCRL1cO5jTIHonXf
zAzGRN4Ru8w7Cvd81OvAVJvJ6wDdxc3CZja3JWjW84/jf842m8Q6RAjISJqn6ERUO25/m/XOGOUt
L62tPd3NK/SYFiG7LC7KQvWima3YHfF5MRxCjD6L83z8wZoVvV6scz3tKuIagKX5h3VBkaG3X+AS
7N6YGu//A1T8kFgpKkTjMKb/8UcEKXWhLkXsVjYppeNDI7eQVFrmoMy85NJ9Elay4uRk4xWFLHJy
GHoEMUvZNNlf+0aY+cCTP0vY0zSkZvjQHmDLe8kfU/fR3tzD2Zx2UO4WbS73PdMsl0Yhl7BDMLFK
Iks+L3Mk00cu/GRnz+Q2uQA4pY1Ashb8R8WebR8PxWQcv8F8tC+TAk4Byf7qjPp85WvBY8KUp0so
9DQEwf10NJL5kniJmhaJGqY1fK3+5dK8nEfG8RHMZXasRgA0XfVGuNjfWz3iv9Adnyik15jZ38wz
XTpeVMk30QDRtuz4SDqOmIQWKn8HEUF+eLsXs07UovRR7M/qag/QzuIeYqsQheMFnC92VkonPLac
b990+oclyeYftSxwiI7lwi0QeV0vW8dSKMUtjjNPGeUFXMgxxD9R0MLiUPptsMNHnuHKMODUvfAR
uiejnQ3wgS8VibiHMNxZoOY9TEumj+SY8UD9Oekq3c69RR8WWxuJK0rcfO4ztCBaJTvp2Hx/1kz6
yFwHvGvycA7oTDamiuLkznEeX4R6F/Fgi6U82ZNQrAwqUbjLtl6FcyuKF3Ihu9NBduUW1BMxEgjr
MUzi7snSai8XT77i/gbwSb4JfrVJjHKalkz22PIjmB/c5Zx6LV/3ufLXf/tmhKP6zb8BvG4w889D
hZQYoc+dqazd6oGVYQNSry3y28E9y51kXihmMScEmfPYUEe2yu7jd9bhcfpbCihyRhCDpfqZ/UkN
TojLxoeaD17fOBAXVf06cI6Ng3ANyPg4UF/FtPyYg5KkahJqHtgMH0jQBrfPmbPJTzZqBu8SA1l1
kcq8x8VUm9vetQLeOv6pOhm/nv0l9kfgVHqbXV9JZo32MfBem1v+VxQ+E5gfR8KeH8PjPkdKUsuQ
lHdbwCRmn71KVMz3A5l94NzvUg/CnDDosgpKIxdBBItN8MD3nCfsIC47WhZ1C6D12wugjEJCPIhX
zHhcx09dpdYJ6uoVC/PQ+trjDkUhhofxZR+qRICLlA5p7b87V3+s5Q+jtqRAJdcPH7ow0qf1O35Q
5KCPvSzAsB+4EG+gm2fhb+bXEMDfHDE6NYrVAUWGAQ2Ajln50D3ReqHFMKmRVIpz3TNIyqv7qZCU
8h6v9C8KeoojJP3HMmDo/FGJjXpIvc27TlpsUVe4cqawZL72eZHhXQ8KViM1Xf3LeOIOZEfpRL0F
Laj4cWcVZOMK8L6VKs/cZX6r9c5xVHm3HFMtRezksOzrlHn+jGbatoM9gZOLDGsUC7m30lMW4SnE
zcpX2ZLWLAQiubf2klI3KaVam6iQddWqUbekjRFQHSDpv+R7PNkCIjuVtFxaahdMV23CARqiNrPp
bGi7+YXsGHeBymJPspUJLFLUQaYEdwNrviBQIz83zHwOoiXGGEoCIG2GTdzpWvimB4WNx7shyC/v
/TK4xXBBWZGwzXMzsNxJ+IHJcuuq8Q+gZADLAwbF59fhDEnGY+t4x9DiY7NZjYtq2df0ru8eVpnR
hl6/1GriVJ+HmDWu0/5LVrXxSZW0uI7E+HkuIYBLFJ8XRE1Nw4NN+zWzsixlAVWbmSJTlRMOCyFJ
CiOm2/8OjuI/G4+nlaGbdNo8I/JrF04WBWo9HcuPeYIDycRqYpkPqPqx2FF/56Ww6Ph37grrEQt7
xpbd76asxfHX9ppXvp507mCeVc7BUB6M6YCq1ktzT3mIcWBwFV2lOMffg5Sh2yeNSzvSoB0UjT/N
n0Mtlp6k2d9XK16Ln7w+Nb9oMyIHlC76ujytvUa5h91LdZGvJeg5YF1NhkqxzvIKdsIOXnnsqnXX
9XnpxFbNJi6IUNYU+J1o37YoG405tPAuZstmWjy3WccJDC91yNvDnplAB/4YmeZx0dsZ6yTYXYhp
98lcwMUD98JyNOIaZEc+TLyK2XyLEJm94VQX9c5QBXW5XtiJywN+aWSNesRULHiFf3HnHWKCn+3L
8BmNcRLCg3CCy0TADd/fk1UL9jskS1C8eLMXsCgMz6H9uJ6OGNIssGWcvaWUkmyUXNuyXhXCB+p6
sSXmPh6jieLPlcUE6dn5eGFXL8CRQxGzzR6su4EDnrksvqmL9+N5YxSdBgL58Q25GHRJjHADyInM
tYmdauMe2fOrVY9YZ5H71yXWLxJgH31SPc/KFwwanuiXF+x2lk2P56RxRaEtxU+dqsVjten8Dfgo
h6bldrkgfwfv+UcKALXFlWJnA6atcH4A2LogxIlpDBwjvmnehzwLwAUogFZjtow09r4Qr1tE8xv7
FTbAGhdGGxG0qgfvx9AKtCHeqi9dbbu58kYdS0+/F4UO+sLmkf/f5XNykz55oq9hiBbuL6XdKrPY
EvKfW3jx6cxhQ50sD9PZsNaPCk11akWxd7kRc1EwCS8+zK0RiYCUPDs6SbquVC4Drtt98l/DPAIP
nHQeZU11G7XgvHu60aaWiPbERcgG3qZVrUKjMDOgJiPSFGVXcA0Gc903602CZGEDKcbEu5z/ADZn
8XKQv086/rXaTXUfLToscd4ySKbio3XZMgn79S3cmZPj7CfJc1xKtxmfRX+cEjkkVScvbjRqYpLS
RzmihyntsRmPDS4dCfb1C2iqf5g1+FHqTQcoeNjCUS1AHZIvopiwxAeeQpQ/Sw9nKTOCCMB5CyAp
eF8ZdD2P+LQjb+KNrnonTCX2OPEHqbuqb9HNVLjlZRHlJIQsefcJLWbX4bOv+N+ActkSeRB81L86
Ub8yrBHpyUGJoPnMBxMkziE+42OGqJ34qXrRx64y2VvRR3DOm16pzN3k3caJsktTYYPpw0otpy8b
1Bm2XDN1sqgCVrWzxnUvmrgr7WjWbZ+KKFun3rK1F6BuiEXsmDDo0xfu5OgR2n36y5RsQY12QoNn
sw+dyNSJt46WX/0zXz2HJ0Q33d7awookJciuQbyzCrWZNZ4MqBOY6ia+n6A1ihtlifW4CQD6x1Dw
qnPCqYFn5AXOk+b210eETavNfb1LSNahDXOB4rR/4k4SZ4W14aevxW1HDR4hqiteHvbVtMiHgqy3
XQ7T9vuaqSLMBrfPVewwN+fHbCbMTvrJ7mqWoFSct/yZrOuY0NXr3jz9zh5QQsr+apwwnMqo2nQX
NJuQAAuF998TX+PSmH9XmZUo00iTYbuPee5+v/eiEKlFyoWtnZEOyknqtj1RnTHLUPeANHhyJDRu
yVuOzq1PlwiLou9vccDCYHD48pxiKN4T3uLJWRsAR8dZQdifLnKl43pCEb6LMUgkvnhB7DGgfQCP
XqfWkKaV7aYq5HSu2SPEZ9qxGW4TI9mmBEWR6JeYfNi5O7FQa3oH+hjGsgpQMeN5r8oaqJ/PyJIL
lp6X5c2Xv5z/s/LGgjiGPVDR6Kv1R8+nnsjWVjs7lJvwwgY3WzzILMnIzw7mmir+jtTLGlpzuxgs
uDAoCIhBjV9p9mgQ+s44wpduEU1NVk1iuRP/LybLYK+n3P7D3qmofS29tVaai7bmC81YABXroc6j
StZBe0jt9oOkbkVYo9NmmrlCPJfdWDMDn3t75fgdz9e/4xaTR9eowW8+qv+FxxYwmi0tgY6Oy2cz
yN8fXzWOlpDIJFVe/CQmzY6Yk2+7gAgfa9J1hsRLZ490BsT7rlGQg44dkG3Ml1xjBfn7OHcwv0ss
D0HmoE0PGnKtJlqNiKcv/ibdlyzYX8LxUzpux7XW0iC2vsD35JkTd2yaeaBOMP2ud8JZUYneDvVV
ur4dCizj2Pc+1GnD3aoatO3a9hGRLk6shOKUB3V3+Bbm/aylA3asbRw94Ga9U/vaqIKOhj0XkCxr
3BWjOxw3WxCXINq73f6uZEewfEYitUxdgmKnWFqe45BUwxw7+40HiL6QBTzVvwMg+bfCGl5111rD
kUJsso81h/wugDEpTfLPXJkjbTw+SCEuwemg1+7Y+NBn7vzBuSstXYRXsEUQXcU6P5EyVa0DUSIw
8HksXJIM4HO+7GqIGljy4u/BZu2IrtaIh/JqG1Vo7li2Ht+TMJL0j6l0Mka5GyxBYZTqRO/dJjz+
gxxgQQysucLp9FeqSedx9eliCrEodE+0u72OLH9B2Ij1/4khwVXV/Z+kWsH31Za6VEFYVQPYRyzl
68vk09V7cKITK9GyD2iXp3yn7My185OozDvDn4jkJi6ad+XBX/VOGQ3oVt/3wNp//wbLAMhG0tmd
IgVOF/0wpPD9tUYj3pNkC+sYfl4PbwZdTK4W2N39UO+/36Iz7PbXsePFgNtKyQqcwMl/0tl97Z29
RJ3Rq3Qz4Pc6hvva3gOi0tSuTr0EkVrmVGduZoeY4kZ4mUFwDTg1QZ0KhKevQ3cr3268l+myebpm
j1+Pm7PHjih8QEHdn2sscjWGN1JDkFKJ8SyZ8vX3HHvZCvItJ8UJzrDY2tB6zUJxA7xOcPGUqlOS
YTe5qr5f+yo0ShsPOuI7JnabBQ1fMCEXhyFcb48oB+LOh0gh89Cu8p1LVb725boJkcYHRiIH6VUq
xlV5+D68dyIaWM80W0NLgnCtji0Dn6w3M5CDeVJnqXE94SDQ7l/YfSEotDAmt5nvDQarWTvaqCcD
nsNfZ3l5VgIERfJe3K20oVugv7JO9UFDUNCfhmRN14vzestDbvIm5WoNaESPlQA62VUKpqunTcDk
SsE3DkrAyR0pDnF3/QtrMg3R+L1Iqa+8DTBlqjCIo9XAnAxUg6t2of6Nh3idIz3V8r6KEKPLZ1uG
xvPvb+RgNZoS2++8cjqPxkzWIFgrvLV4TcCOEZUb9/NujUDmjmTK2AzzDXwCiajCFgvbuPgs2FI9
2wUmZH3w46Ygr1bHSbkqFOJc6chcbcJuXQIX0d7T91eN2CMMPFdBtBAnu3x+1SFUn8LAouZCn6Xz
dvfBEpEi+WH2Ucha1IX1j7LNeamdiRpwQgGIB74avaoQglSrVwecWaj204bWaFDBwTbyS7Eg1Jbl
hoNdUCKS5bgAK6yizbiA9ZxD6XBBoZG1m91iW/cZMS2izfX6aC0ieHp0W/IyEk3ofAajy9Y6W8FV
Edis6w3YM5HTpoefRfX3IyPT843eBhUVKoDy0SjhH4mHbCP2VLXmtZY/9YfAjESvdkWwC7BgS1N1
RiaKspuLY0VxE6gDot5Snx7Jm2dzNtk0TvdwvUft+8CUK9yca6QDDPrG7VRKuDd/o4zbfLPqOgnp
h+3qnZ3BRM71g8FxCtEjVKhYkvELfng05pETNX5kAb6B4wMwF+/A1qzGLTufLGzObHZtGKh4y/1y
wG0UVkcEJxBdBTs+kU5X20uJKqCWu58vjNKL3PU4OTOKOZ2oohL9f3pb04hmS4t9EmA125xjX+Zy
7Pe9wXaoQeY8lNDfdH3auVkTzTBO8PwV3qwmZhT0O14raKA1/ryyBa9TID14WYUmbmXMEBEKiTbF
F8k0GYwtC4F88yji0uzD9Zydr07gzQUfiowLS5icFdJcaxIE0TwpPjgAanAhGJyxbbxXa+Wupr5M
ZpqNezMHOfyi0PQmDrijKe5WkglgPHNrENJOo3WOP4LHvMG61AYjUIfF9LOg/+485cL9m9zGfcLB
iF3W8SzVk7y7bH8uGJJ8MCJrqOk9EshrB0rrlrUPXxbvAwRvCdwkIXJqGtGG5l5r1rAcldHKpn3v
gy/h0HkyQWKZi2uqtDleBU9y6E0j9AErKybVO+zOLApR6TbdJDIOQkxu6EbX/tSYG/kZiIyr2NZB
rHJg/rpbNd/eMimA3qBQECCZYHIvsB/H49mgAE2SqJ8MpyisjvWmZ/BCt4pacfSZ8vMlWqz9HVsm
ucvXZ/qxdYBuhzgzgSIyEG/7z8EeV4aQdTqGlhGiRx82aPaNW7DkATmCUpSGvgwSO9+0pKFFnoAc
sZrRcTSzfToKe4PQ83O59piFkw2ya3useskfZ61lFjBDQrNskZUW9qHdjeyNrQW1s/eWcZQjAoAu
0vtQ9yk5SddXpSWSULXTQazgfMKPvp0+/s8MmWtk8in1Fdv1GT7BIekBR3VXTn8Wc7WjR51N7eiw
dOSIKnE0N1s01MM8fmeF6lbhfa4fbkLUXbDbQS91DXp1qc9OGHvYWYDJOdmZoRLm19Mfu/oCPht8
vjQcsLpEoD8SlJe6ZGVyzcBayKgoU+X9QtJz6ufe/6kygpwuC1JIQajMSxnGM9l7aHRvXbKt3uzT
5KL5cTuXeEBaU2PKpQH6mL3SrPxtBw+mKvwCW4+P+nX10IVK6jIH3eCPJxMnPbXbWoigzUdNXM4/
cwar5LUon1qQRzhVx7wnyOtZMpbbAiLsSECVrBqARGbIg7dcww1TfqAHKgO8CmaGvn/LO4++hAyu
Vn8yUHngH414fLjdH7onAJ83Jt6kZVOM2DBKxthTmvBdOreUNcPqPEIJeLE6xqeudRMp7UuQd83L
S72qJ2ggOeDsOk5BghNYGhZcZm/THysw7D5M6p5GQ1kb+atz5LW2oCz5FQJprFXPz7J3fz2GagZG
lfYz3ZSISKZ7R+d7wvekgXBmTy3SKfNlom47UKNFDGgRH1F56UDEECS+ntIZZ6CFVRaxHFIKttue
tFNv78DkS4kjbgXgJ2e5TGp+w5nc866gLicBjlZDgOlCKgA0q4PQnGHZevCffxGB7VkHyklDS6h6
hTIMP0pp7fa1uDVgqu1f4dzCoTu41ZUm4C8+7LnWn50/DqiSTJwkQF//wa/0zyR9AsBFLQNsTnYG
TiqYff1mmvXL/+Wlkc0BJtfXVkAwbA/OhLdlixBFypoNXNbhrKcP0tkkQXmU1FjXSRlG449eARkN
m/LDbstKqwwzyje67GnLJuBGg7v7+LNt4wzYKDdPxtelo1fzIhL+a1DiOAEwmWNRZBORpCv8Hb7v
eSnMI8CG1gkfK/P6Kx9AAtriealbde0GgtnJ/Z725bN8M4/K476AZUr34/CkeD+E8uhGk5btmhMm
ZgnvUh5A8KUZb+AjddCGNN8f60o0KeqcZJ9LEmkWdzP0dIIK28QMoCRTlnUSpm5+XsxtT0WPJ2VT
Q2xkatj4SZ3Bp2a9o2kKUF46X0MeRVSc6PRa4ZUhELLKnERA+sIh74kzyHoKjNGu6Fmu1beA1T/D
xDHbJ5p3YulZeRsrtJLjxFTLbdA6kNjLr4Ff9ADvzSJm6TYaoiJKthAoGhQuKkTKAenbOPm9xIzu
1Vu5xisowE8wF/9SzREB2PAogSTredu+n0lFSXCJSOIk3b4e0zXj1U3R0dk0fYFTWEWGoNsOVgik
XWg5Qy36x2x1GRQol5SnpDZTy7d0O9ol5P9XH2R73rH9+RY+CFIWPoacK/wBq4LvPsBR5J8xIGv/
qpxI+hHOazN0RSv9WEdFhPMhVEUzm92/6V1rAj2gkYVGPyWowwji/BiacsHRXCaQaQj6p+8TX6Oz
pRHTewmJs21AIw4AuCdHfsCK5BW3ZhybeK+HkJQBt1mtrGvrHOlyEbCOcuzkt2W9KEjlJ1hjNIx6
kIDGwY3/nz+MfHg/9LJXLtPdklg9rID3VagaOuDnCB+ZVj5DurBuRWxBDmfdO2LgB92TD4Q+1uVT
OFDjo4ShUsgl+laeWXiPw9+tVSm2zxEjdUP3Nx5Mct+BktwQMG6xwVIk0K1tRi5x4UWoOT6B9kWE
spF/0/MyTpvAHuEFwq9JshaWOjamY06LeU2w0gaYo4t31vtnPkz94q5Sr0Aiq966KO4vX7+1skTp
MuAbLlFr0tloePDVkz2Z2nAGFl6uUBCxnB8RfEr/PLQCrGuqaoGuJsSxsmL+EZH/RYdgEw7kRN6U
ER6eawVwEaEpYXtXGc+moL2pEvYzbeJOF1nlDHxmsSQu8q3+SDlujPHxiLOnuumHmNIAXqVCdpV4
X+2n6cXGOXgpd5TuwDRGsn+6G9+dwpj+aRnJ6OfasrIlYHutcaJabA942+8n8SqmfH3I8pzCmpVA
CYtzhtJqrQWVA2k/r9MZTy9WOjgQzjN0l7KEgqDwKmyDwMkfnMcD6eC94WZw+tRd1X0MotXFtf6y
1x4m87xyEA/xkeZgzwEJT7gzQXHw79H4c7QgpFQH7C0ApfzJxJZCI+Yo2Km1G9pkXYF2j0qKX82Y
jTPmjdFDLJARMYKMio+EUL2deK2FxUUfhS0r/hH87IpGIVw+/UFde1YGvnY3W0vdum0NnwQ5Fvdb
HgpAALglP29F9aua0biUx16dZpjCdyDZVFzyxlQyD6Pc+Bcdt3HRCRh/Ap48l9CrrmNNmS1yErvk
kek+uhVNs5i6Bxp6v+T6lg8VHlR21O0HxGEYwWts4VzQR3h561N4pz/+BLoGWfxj0v909pe/DoYW
5fFIMRjBFWpqLPZzc1AOIlLMX0TzVYAtrXf8xeKw76IPjaC7wumDWuZRCc8IOP1Y+NBF/OiO4bbh
WHNdvugg4pUlcIMqWreVTxpPKoUg0Jo68cbox9hsgIjHUNuio4eAf/Zuf+wBzWx7QB1mmZZ17Qqg
ar2dSO2+2Nfg27cExN/gvM0C6IpTdrcqJkSP9C4McCuTPRlzZlVyjUe2IIynXuB6ugE8hTmWeVSl
vCeQPzktlO5zdDCa9a1Y9Nh9uvD7pHEVYIQ7XSzdf+75asuP1FC977AqqinTe+4LiUTLNVBLIqP2
QlN6IHFi3Njbmm15z+bqmN6/Ty0r/6q3XTOCAnNDMEnYs60dwuchWLgwxc2EMIj5C2a59Gs6sw0B
SgEyzbbVYNll+NyXD1kjlIkTbkcacY/bbhxy8a1yx1N0/sJPiAiQe6DWiGBpviXL+DwpAcovZcYF
dx2W+LGgfMXTDMXTs+K94nO2KrESCEUPSQcPMz3tk3Dlf67hTPumOtcIdz9ABlz5OoJLMn6u7K1w
0WKo4ucvaf/4RaPbZpwtcx3OZwsQ2o1rKQtKvWq2ZCQ3mmLfZY0wKdpM/CV+8Pf7yN6N02p/c0P8
AKRrxLYDD3JBQ5ehFaVs291wsa4SESBQzO7KBEdhLTu47lvFKVrrUEATFOKhIvPq2iJbDVgfWw+h
UQrYg+MZaQHmoHeQrPg6icsTrr4lGF6/c/52Q2H+HCEk/31ziBTrbTLdJYlLEyEGH+U3vDg9oMaz
6NQ0yZ17pCjPtzpbZG375lyaGKGDRIH1fBOLPjXJ2Rh7tXDPjGUuQlYU5/uYvDNR1UFo/iawJJHO
b5QxcGk99hQReyi0FNJy2EGz0P6p0a7on15TcELrAi7dRv7PIDxFTpZVuRWBrWAqyC1tDdcFFu5c
j80P36qtWcEzZdi7fssBwu38AbjrbSQGcGK4YCX0yc54DQbrvL9ca5aiSZTbS1/rB5V4hO5VnnWx
452aqB6yhnKWuKGWcwNeWy8zDHZNSxjL3uAhg628BetIlXev2GxlmIzDhx82pcHZhm24+csJA1gV
cnSCpG2kLYPWmK/9LmM1SJeACxpWDRRacgVGPVO3i0qZpGpprwuo+3iNcfegbAokmCEHY03GJGHU
YQ1usmKUEOnbKbphkpORAK1AX+hb8aTJwAL3jNoVrUbJ7o5mA/4V5jq6E86VWa+FiDt+QLQvuiEm
U7M9LWLcGHkAC3zbxLSHe2j80gDbUjbo2NMxD1oMStEA9q6MUtsdgabzgLe/x+gc9+KLhdCleDYm
iYapya5GyNErMGrbPtARFDbjZWykS+tH2AwL1ytjZ2Ewqq+Xn2ohVzFK4ADtgygJwTcIxif1xeIm
6Pk69aaIPGJKyDEreHCW1wRwiWlXaAAmu/61S4y1XJZu1NVbg68YKdlofn4VUary2GpZLe9jbNWn
NzL9w1ya28pBZ//kS4mEVm/B+XrzbDO53p2kGimPfb3xLrlRGMDfrhCEWjCP1qOkPK+5UoqM174k
Yq7i2j6dQEosmmkhP2EC6SlsP4gDPs29ZA2Ob5qnzxKFaDxRikbhVN+qYe8neaka7tkih2suNlGx
Uu6q3kgh7o86gdNcFBfaiPPNbGCSkaOdLIchTSTFAdVYiUSniHCKvggQDYcqTZg0HBvQLRG+gB/L
YDkfBNC7a65iKF+4ie8QgszHwekz3ruud3aHVMRsFN1IVFS9xZqgKbNOXEQItZ50YhFlrN+MVgi8
UzJucoGLBaOySHqxL7Elng0mjrMaHKo1lwC+4Cjk0iHMcWWtdJg3lCxqRwYLyrSpV9poUijQ2MHT
x37OPBpGYaRtqgR1JMTDMLadECPmRf42mhCYUIRzYSZT1JWHFVfMZuE1n1ObFIlrDTJYYxC9eYYW
9bKWEMN8HvmscDra3UFrpS9wVc/fcZCJcKt1M2lwq8eK/BvtS+fv6zOnY8uF+N8tpxUVuHYjgUA6
pzcXyiXjOARfZG3G0hzLh4kTyxFZ70q83r8SRS7K+3oruCC9F2CvOAFW3yFOtfVP9PE56VGUr+Cz
U5DTcqU6SNaSYfhsWyYL8wbIF7vCCrLjhua5kwqLLreE8xAfzIqA9kpnJzng4eExDyuNUIo5lY2X
AVlHjAgGY6p6KXBlXtzYz29MXrjxDz68r350KyeXwvaFqNux1778a91jA03YYXJYxjNrObiRJ5uh
iS8l8LAJthnAAKQ/yHzFnfW4VjCM+llPsHI2DhdHkcMCTe6GrTwuHxdoDKkMj/jw76/Tn9j+pFYX
59HikpC1NEVXQ6cxqfXaFjC3VjfF9pc6zUul5LCdoDOL3aNdK9COx3RoricpPfF+WMZTsTyzX0rl
Yg5sWSgZX60jLuAe9DOWozVu82Pu9/rG4Kz+aYaB+vDbxeyO2aVeThH8mVqQzPVCTjLCP/1rrJp0
5w9cTtMyt5H8Ebmlsf9FoQpj15A0GZPLUG3OkRJt3e8zCnylSSfDSKzup+me9x30Ecw8XxOPdZ+2
ulZbXaAMN2H8ChV0zTahFreIOHZTP7eBw+dh4afRK4Mr9O5VQLPFrrKvNzaY1VUEpA/z5OErcX2q
4BVzGcIjDMxgDhXfctmdUF52CzJT03RZmNYqZq95rvDrqsP6BHBjIRm1nzTo98J8DrRhHAqQACY1
g7TevspvlhXPyaeXBSdI16/Xywa0CVUgSk48tLZA594jhmzFTlXo0j8VV0jZIzHblB0D6ad0kUZ6
T8X3LLAaTkFyOt5CUlJnQDY33LdZGYBHammm5vn6Yd/fvmyh0usijKaT2KuJHjHHE3q+7NuQWnZ9
DSVNjtR2nF5Ch7g2xX7JlHjulhIlZA4Z/0qN3kQyhaIXtbPze9QBVU2osO9YXvATwT8K0zDdFbJ5
mMOYZbbdKzGDAvGG8ictS5ln9HeXwqptHpq60Yqp4sQor6RoYjTArm7KqsB9OAbKhvTmcuMN6n0q
mj2sMiyC67SXNZoLsR0ZregGWD0eQ8+LbmUNBIJouEjsF3bGd+y4juBwJMFSVDZSTuj5qNzL6Qxv
4/wBCDNRYWWLmh3pgE8xmRcTkIXmRQhwG92kk3lM7WxpYH92EtzBGKmZUEgu0NkelpI8z0qWpWAA
MT5YQYdK/fCGfaxSucY/VY0HJHWQ50kqhCA47kr1y+HrQKqU99tEBXXyzOhw9qvNaTyIX/axTr/d
ZSaSec2NLHDtBKM/qup0PCUPYGqgC+RCAatoctKjCKPrzr16NVRnTMwOSnBaWRZsnJLuLB9yu5Wr
w+YOp/VluipFLkZX06zyg6qmNAws1RHb+RZMCAY1fkhUcD2JoHQfdofsiCrz/YCK/SzAq1aJuLSe
cTWcbdireMCjP216sAU3hH5SIvdFlgokn0KV8OlJ6OvVi2sY2aF1ALMPmvvRHl7wG0oU8d86UoM+
OF2luaS7foy2RdNmPMxV+nx79klMp70+gyvkRuKE6hDdnwJLExv4tAAqMUbnThC4VpBAZhwmce7X
S/Fg0RCUpyJkk8Td6LXKXIozwT6MkyAblB/MeiN7mqHWeAmE/LKxZsGpSGEzbnHQo8T50HW90RLZ
hAf4tnFMkB/8kBivGmNaVu5+CJtzdXNUDI68/h0aisQCX7KJfPAyryxEG294o4Js8n1QL3Lm8co3
9LpJhD/eHreu/WDCU8dGgUbzjIZ7WseUgZAaRuUZgbaWbjtsxA3FqN+sStS4V8RDdePiwtazm0Qv
UNobXxNFp5P3aApjsxkd85Vk1tUA/6b3rGXJLL5DtdsMt25wWWMXDA2ahEBChEqdJ87R+jkdUeBD
kHg8H6l89qz5EuklPDPWJeFYRJ0y8Axq+0HoRsU+m92UPR0aoXi8HQA28csUymTu5oP6abFHQ80h
PgVHPr06MKy+j01/+tggbSAjAI8KH1aSVWjp6pdXBIEQHXWhLtOWlfTq3+u+dOf9II+zZ/5t5AWL
mgYgA2d/frSuVgDR+5byMQyObs3N4VL1LK0f/Kqo9/W2SEjdo8pt/OAODHnM4lOPXA5OFFq4sH2B
4n2EKJs9vM07PHS0yxsMH0AAGMI635o/v48JD0zz/gdDDHKkCufbcbNbK5lgcTCZwZosXtQfN09J
fIZIuyOx8Oqb8hGXmDjsQKF7zFHnEj5I3UiTwK0pzsRvJePX6/p5lWFRyZ291Ylf/v/LbjUH7af0
xrskHPcJdxr9DO6W7Yvm9HL9H7qQWVvWGCMVibO3FLn8P+kufDCndA6OP2gM2ehZot8zSKDnPIrW
eNgbbt6oGzJtI0YLf2MDUd41t3kV6Xd9wTXa2bx8n9zelscvwodbrYRtMGXZgWU8IqtDBzKQ+4VN
QKAwMUaFsufX2Ud0z4jy3svi9y420BJGKGiCdnfmIT4askgh9JbL8wSvWdQF70Ip1y3ZBA7lKfIh
JROji+7sZ/fmo/PieRgctEJX3mUReZ2zP9Pj5qcBxqUx6CrV6s+5XJUHakvTbxR6udouQ6iA0MFQ
IX4zhiESGG2widmeJtxPRitCoDbsZgNEgkzaA4mHylrsJJ7j24UQdeDLiKJIrrrEUR+8tMt7eEEf
WPDs4uv+fPz/IopEfFYgw1u6QFqVEGoC5QzpdvLrHN+5i+rmBHN6GUodEqho3VFbJkmd/WFikQVg
puEWM6HKqYmmzl1KffQYXhLxznP0wc2FWf82JyOzH3ze3tzvzhLpExfx3W6ZkI0o6pvUc4/udImp
03AGhy1INOJxbp1U/gUpw/SlUjNQSRMQJ3ddDo9eoaSRlYrgWC3bZTbBIWrutJPPa4v4lthUoTFv
6khLxhjLMXjohIX84YPpQPqA4OFzpjIItMI232QbiGqN4pCicmJIheOBQ4WWujXTBs3QVJuOJRFy
peRsGwP4Vnngf6dqIY/58znznHbZSbv+he1MMBYmoXDR/w82SH5XGWtuurCukEM2fkvgFekisrBv
WR6cvRVdxXbFzA68eDhlfZEQC7e68eih9tyrPIZu3yY7Ukv0hY0LYBwydCu8hV7DoNQRY7jzH6Ev
JvGuUlyZyjei26Uwx0j9mFEzbfWLOzSwERfprcXGT7A1Oe0dXgwBqgizGK4R33AmsMvfTxct/4Fa
5eTsX7Ey4L0g7itrC0MYM0c4OUFnyQyX9M0fjN+C4jD6pzjA/otm+aP+J+aeZIHu2p2EAhybZzau
L/sh+Z8mBjXlz4FRNPx/vrFk6W1g2aA+LqYpkNFYIaNjC8N/jg2Ox8OAkgLHTRXT5zMu5VVj6FCD
QOP3eNoS1UdJqRoiuzHQrt6IAtlEc1LRIUgvscSjemmkZYTRz4mkPf6hOmW1Ub8PohniYetM+a0S
C3e+lGne8q7Fr/MQAOEiIrtOezNAfUDupTPNx6dwUDHdhEfPM/XQ0KQWxqaNp91eorwd2oTUCTey
qa6WcnqGAHcx9UNS7q4Raay5YEmLJjhQAtzR/EQENsNqBZ7y+Vb6bCnVFYesS1pZ2D6weRj3ZnPT
RR3B9xZKxZ8Pp0qhWvljogHIajSunGBmPBT5oTHlc3s8KxVQSPTXX/bKOOJzGv77bm7jz6X/7Ekj
UciqUy+p4+pgTa31c9Ly7Mb1BWSswQUbc6RFT8c6efrEuPjEhIKji7ICmr2bsnIzXAATt66avzAV
RmG33ceVy2k8sZfezIjHLA/lUtdd2xNXuRsynPBxmIjEAEOVOS1jJbAr/3UC+xmSaHggAz8d5lxJ
5fBaG4/8K0BPnrONVL1CU8sQpaS7bceMG0rgCZvgywDk0+vqCOC3fGBaucpnQKgfBx24c/8WQ6fS
/txPhIA9nEK67/NICCAqDKY9nJfwvR7iV8ZAXoN7l0+G56/D8bW1ecThqck5wVaYiWn4hFMxFS0C
5vIw5ygfAGrQxYDM6QOpMsKUm/QOiADfDIOGgmUv5cYJ91avtQlE7ZkhiLDoD47fRPFmcRX32bsC
VNX83DhJm1h98j2Pf2KtormOg6ZkeUkbhWZh47W4Za6UKE7oKiWyqgPcZr+aE/aseLw52RtS4qlm
nIF42C0IvxQbt6IFVaQWG0U/imWmH5mN/sMC//CN+O1GAq9c60rFwYWy/Izexf7BB7LaVnuA//e3
ZE/jT76AwpKTVo5Ihg/CK0Ws4aVCVv03DuoIB24cbNQ4AYj/QSWAc3kRAT59K2VvcCezbh08dJlr
hH4lbnKHUlFXOxphAF9aDWFUOSEPjhz4QOtHv9ONlxnNNZaYpbzlc1QHBEUV+FCzJKzSh008hYqC
ync8Z1lmvRkFqRL0bIjnrOfdkhsmr81svGYL1HALyfNfKbwdV9k//omlD3aO9EqxEpc+ZJ4HQGfk
STySq7Dc4OEIA6ldjVxz3sadIb81HNUOXsbfRcANO4cd+vVz5NaIDNcHxUjW0habzViIENKCfAm+
9Vh2Ev9DQuKL8DPmedRxLuHr0IICtlQDjGpORHSqoR1O57KYjM/LgZiSdkvAGIyjut9XT0gq06EA
QFqhyt3+Amicm1dJ5G75nXZlUvPGDS/8MoLEXs0PQH7OrJXD2PVEgs/NbwbqfC71c1UvL9tuE2UO
jQuRmx7fEyshNiSevNYPLcCxdftBvnU8tCyq5ge3xCb1neZRt/aiUTY0hZn+Qz2WgQs6GeQD5JvE
OpYwgP4h/7HbVVd7JMEUyEbRBuHWpUExaT6MneJ2YPWwFh3kTJO4lF1SpJti7yY6xzUsYmfHMIby
LpHW/7fpazSSDtMjXZdnCBQVxyI6g1lJJ6ulrhd3hwpK+GVk6sNKtYsq1oyjeT/Q0sAYmKI+hWMs
MsXkqSntqa1o0AiZQrwEZjsVENN51rmnecw7kh3ip6YlItJ+vYfZXUqFHIEmHp0iVzh5HS4O9vRx
Xi7jBjFYqZ5i6BUPKrT+JC0CV9tK0JrXezERIIDDlmpaqMmPI0clQSxNnlFvOz7oM4+dE+FUiZ9C
H0XHEz2qumZ8FBpoWYIhVcZuFSsevQsTNyUKXpqOXTNQG8KXITJn32vTmiovbFUTpLd7bzFNjCcg
uKyVKN/Sbv4BAEkDzZJemSzUYxSrXikRR9Hx6BQF60IOoM58bb9e6XfIlwJsPqKFQDBFadgohoGq
/xGfoAt9D/Gmo0pkCTXA7plzz79KHXvET8Yc+9lqS02MHIZkHSsPqLTuKFBktlqZc/NYgZQWSXmN
G75uRcGU7valtMV+7FTvkAHcA/czfkiYTCGCNHas1bbCISqLoHGcZtLizFf0NCD4jU5HtpuLc3US
5n4tblr5RivvMRGuu5hz/WUY0A66K2ieP1km6QI36LgNNNMLf4TDMCBO3KrebEk8NGdfDV8um65i
CH2i8VSXWde1/vdeHohMAzm3BIGQrVcSV5drLH7sYy35YX3FuVi7iiBTcWkFGMZNlktYUzMIrhXU
/o61P6VSJ3tDAZ1Gg6CesP++rfwKYhXYX7YhSm6tYIO2G/mYdSYrVhl/F5pOx/h3K1tB1XLgWouJ
Lye2qLZicwXK88rCWhDgQu0kgWZ7jvn0h1H8dGmKtEflDwXrHHPjXI7XNGdZrSjlKSc9mPTsKeH0
vu+LOikGPkm5qponosgT9E1RnFBT5H3JsLKUOSYh2Bvn3tQJq0khobM627fAZgX7NWP6J1XWiizP
dFL+RaarADffEtoxjTc05aFXcQhJhxvo8iBTk14p1ThbFlGjleIZhd9VkLQF+N8Q7ybulvBzbAIL
0kODgT5UxnkzQYyQbP5uUTsjvuHkz7CVml0umFV6dmxlxbGBZGoixINIgeGdMyBHTTAJS1z8dBoz
RTHZoXFcwXQHhGmmyIlmHR9a67QYNdUC7eHTKDOCFjsA/cwWJ1YhOMPnd7qRbPHjWzfaNgZwDueV
i1XdHxcG/itfxwq7biNaXC4MCTfpw4F+DDcUfxGgnvQ1qno4pmMyeP7V38zS3Xq3QI6YrvfN1Wfv
RchV6mudljaADIG7O9eK7xIy3tPguqpdYEZAiBH+yfC8AoSHBmJbZntthaCS4Oh4zAVWfUDsbFQe
+Pu45XEEZNj7a7Tm7lk3joMObeTW/iDI2ZwXQhq3dEPN+xw6g/PuJus3GD7TM5zRVg8J3+w5w7zN
ugqbhfQdeu4pUalOQJheCFGtLmKtql/TrvraoULUORY5iM5usybupisD3p8JVLgiC8C8PHgus0O8
glIcQpV3qUnZkWRgHvpD6AKUouSIlGcj9PquxfASwgc8fj//aueAQ8ZUleg6aVNIniXWd1upljOn
/cERADRUqHuTiiozJpSw8bd/Qqata1lEmhpnq8X6pwTeQx62DpWJUkTJL+rxjNRTCEkAWP6DkjbT
NjBIECTEKO/ZG/haISur8V9e7uc7457C7ykNMXwt0ptSTu+YL3zXiMDxxXhwOMo04iIDF3Th+RbU
mKjMNAQpDeyDZKDjw0FfxDEf7ks3ccQTpdhWHszD3owfYKeu+9QzBa8/MTpfrodrKOpmP9sKL7DH
1Dv+ID6HTWvfii2JuyveOOSuVELbWBZmrDvTY8P248xgvYzdS04scdgCtoLsvVPa1L1MV3StGbyE
y38HGDG5MsKa3tCFFP9La8Gh7Hgl9YoOc1pjI0gLSCbVkhHbDPMgutTS6PjwRxoFqD7rPxdg5ElN
NWFGKRjlLAekOU4lfDAmU9w70vT80J+xT0vdROZvn0EoZhNX++QnDDKOB97nCN8dyreTGkCl4oGH
a/ptZcemvrLVt73Ncp7CkaI44JBG4R4/hzm2wLzG/UMMXgsAoTr33nvZEnxP/vyLpSKP4XsGOnC/
zWBTl2TE62Lm5EijXiAx2DKT4XNO005cqJrykS2EXD0i70usSG1QG3kpHOZOftvCYRpYtG6xZTxM
nmRs4sQhf5C4lD4f7vIWvfVvEe50Ae/Zr2XqPyfGpJzX1PKYAUHKU44vjefWxPMZJA7S7hDO3ZNi
/7g4A3bdrCS3M7U34wOAjxANsLgV9WQzIHQtI8/hmVr3yrFUjO8WEPsLcVTtZI8Mif4niE+AtAMf
R/V7E6dWOV3rR5mlWltfIofjtQ+kYVjFX0L8SfAz2ynlnE33/j6uo7vUlzqOoS37rTMzmqVZf6uQ
BKOZ+lPKf0YdLeaxRzdTEbPpoaAND0h7DpNTNvtm7boCPkwRsnOHrLSw5w6HBLtkwlLIuWwbYvJO
IbLmiYwI8t9DDUJbyP0ecED/2EQdN8ypdTHvmxMxAh4itSTvdr+O51eQq5wFF5uc1WLiCFJxiisW
EHb+biBILbnR315zpVY/xydzAaXRwdMc2Gj50o+sbcegK3uJj3ECdoaiBew0Kgt2Rd+QYZCEAD4k
Dkj5PamxvBsMNjT8cKxCvCUflP7Ea8JENXN7BlKvaflcCWWO/WG5tw15bvyj+gtTyL1MTymqJdgn
u1PRS1CkSWuE5uL39mGg2S77Gl4breFv36Is8SKT07M9nMfCsx8Gbsa4BFv3tDpF15cCHhVyviOS
9iz608ZKhyd2LpZ6lhpqv016vbk2Cz+KFgYSAktHomQO4oKCisvLpWhbXBSHwLyhjTAdYNJ9OiNn
uzzATRhgi9L/TP8fCeM9Irn2N6ZRKp9hIzI8aWTtV5aRFEZkiSv/uiiWyXnzbuNyxqqQziIyYuUZ
9I87MvJznpoCX0WthHkxlx5DhQA9tEPmBxNkXQVmLony9zcsJDN3xYbpawqWNQEOXpOVpUYW6C0C
s80+ib+z824vdVFNYyJg47j46Py4WvpxDknTBbraGzsMDqXbxZ1R6Y6yHiB/g9usQs8sgVlqzGPD
4MwseX3ho5X6oOwx3j9t7qfae7NkacTNfskXYz9Q/VHbNml6SDPcHNy98TkrYJ4mWlM19FRHE5IZ
t63Td71FxBqJhL7qktnD9B3gkyfe9Ec+NZ1V8pXuaFyCQMIpYcxQLVOWMCvWeTeUtxcJ4tE1NsVo
WCHj3zW7HDEPz/r1SWJtZpWIbvxMvsNI5DOMMP3ehoN3uIFZnKmdeymP4hbLFoADu6dsmAKrwHja
rWD21JMNrcWaWx7Lrwej+zTryINoQjdksI540jqvqmgS0743DxR9pb/2eSfDNn2vjggRVkP1NgIU
IAs4vq5wvRIyxBq/2u9fRNBUs58pMBs8KiRvM5awYpxAbRhcIsxqq5+rXVHSJ00bYz9xiEwD5+kN
+QAb/GFxEPOZNdOtVTms9j2/ZLwvTc3AZnxAMf5m+g217nVlPJJ6MI/oY93vVsba9FpFJNJ4F2hi
BmeloKVWIMhEBcoECo5hqiaPLZZlcf5ppu8Lo/YlGk6EAEVf97MnLA1yNujZZGaEfKZ5A8Z1+3ex
2CrPDZTa+7X/Mln2FH7BCsNvXbtRyBPN9P9cGFm/Ju8U0vtC/BQFr1pkplh0uUNXnVCWswZ+avA5
T01H5Exbuq3Qi+5BMmhsv2kH2euCELBZ04qSgfXAdcHEdjzLZVYZm9+KpqLvd6b0ukeprNPquxzy
3hrTPyof9TX52JzB7s5hwrSSDtLR1V082fN7huOiVfW7AtRHtQp1+oPC/S5TMUQLhDt6YFY56cNT
5fDjTgdN5sTUd9d4J9gvdE2nMuT0yICxBZq2r27UQMoY+wlLtAuFMYHBHUnR1a9nDUzWNPWIvT4S
cX427ICnPYIzeLHelH4lIRRUVjn0KY9EpLwgsn+9y75ljHH6Z1aZ9tM/SNvyRcCUhFy/7gz4fkqU
1nu7XiLV4EndGx2q/DOp1RzOl/szSwLL4HdKtDFwwtrWZTfk1cFrDKjufZ+D/JeJzhaAtTcjcOT4
taCpWraFqg5uarH2EZooeLhmTNLMgJo4dguvm4PN16aPvilWzjc9s45rMxf+4E4LcHL/sX5FsZGj
CrKAcY0nxfHlh7xITi1xNWlQyrwpGYna5B10lesPu+X67RjIRmoYQQynbcDheEnpjitw8PCx97RC
BIw4Kpek8FntBvRL7BjVW+3M/WtihTB72DkCWy+iADEUyBk+s1/xqv0s1V+UgsBVPu6LHEcj41JM
spH36IIpQtzCdNb8/vL5EWqKL5eVg+KsYRO4olI+fAIisOup/kpw2D21L60zT7saBSRWs2sUvXpt
REk4T0oUr9HA/MlUzm35/TTmZZA4PH0Rzcm6frvPFUi20nzd+pUp5Nt/2+i3ZeXHdEgUPzhRy+BT
/RbYpGBR1PZZOuuZOWvkZ/fmxkAE0qSIGkmqKZWP8LFQ8auZwfyntaWH2LBLWHX3VmAHttuPjW4P
Y4h7Im6gNh9LgtMyDIAmQ8yL+EQb83NNaZAMZGcPSBvZLo3BsLXqAov57DyQdastlJQYEDUdkEF4
Eq/Fd8WgKv8mow7zH4nOSzrYax0u4hBXbjIqoAxVm55EGM2Z+sdA60MkuuiCFNFFExJiUARCOOVG
4SJsTmccPhW/Dsxbb2vE/uUNb3GhAI9jYexIn0ULOya+X/6MXCo49yFjLHCE6WFGC7Ju6FNqrbL0
8xLYlZw3aLjVqnQGW04mke1E4DP//Fyl7azSdmGgG8ptegcDcAzr5t/gZOjqW+Umg/Zcqm3Dz0Iz
slK4CcfPMGHy0IG472uCDxfrvyiHvNw3Cp7Ls4GOCUZKUTGYkCH3Xh8Wfex79WSfwCymafaufF28
PxpfMjCE+n+QQAyvM3BFePCpxiqYWy67uRuDBzZawCL1qRBYual4A1AGs6FMptczyZAP9u+8A08g
O4cJ0Vku7Ien1Bs80XuN1acilEm7TEBpCFWB1Z49WshPo3OZz+mAw26J9uzwJTYjxvGnJjE//o+O
YuayJfv3vYpEgIPUgHsCQbLj0tAE+TNi5xnNtWIl+6//jBYkpVr4eyth+iNjUPmzcmG105ZfiOqK
qm/yOiwxeuvrldck+4nlJ6xjbKGRcUL3/bboNobE/CRqt4z9K0b9wVdb/Sa6bJOilFC1UhlEN1KJ
qkiSj+YNuzG0SlvrHmVvL2By2LsyHpsAIN+YkdDbILbBjpKlWfBBfViteayRMmOWj0iXezL3OJWa
lsKSck8lsSyHp0LxtGqNmBsI+7RqfLW4Ci2GMjKk6l/X1vjl/FgbMXaD9MrK00KGUftBCTtH65hG
VC5CATU7LOYnm9lvYLPS/88Wrx/rXF/LDnB0LguoIqxsv/R71vueGxgmB/9l3aULLj6bbvK0GzAg
MR9GWKskkSrwor/Im6ILDmNlZ9BDuNEwsUJ/9rOlc+atszr/kFd0AUukoLzNUxTCmSnMHbzEBNyW
1nrdZTWEcGO78dT9vJAhqbVWaNB6vgbtciwHW8vIWBUUarc+OcfRpDQ/Q6z2jfgtd+UD3EchRxE1
VxeZgECSed6zTe7gbpF6lNYqrZoK22D1h21mBAFidPDlfZsj1Fb958nKZzC/EZnmPHwVzNv3WxqP
xg9wDjnripv8Bm9DyFU6SJLOx0JUCTUXeLxyAWPQAhYd5kuCZEfPkSa2hD0MuMdeYDnyj2r5d4it
cQ9SUV56DkGvA3Z8ZpmHd/X/7dQwe68vqbEhSTrsF7sQGjNvCxOBlThf2z0KzUM7xKKm42zqu5UD
jfJhdK2dpQLspLSOvrxYVDEcLoaOPoeWMkNw+COUVD8xVMEo4OuNgxuV58UiN/u/bOf4gvk1R96H
8W8RLpGZNvk2B5AZbCmQOpPJrjBuz0BhXRVjcEvmSovopkZpu3lqttt37t3rsLLg5gLROYyd+Pqm
8wk12sjnM194K/62oeF6jYHTfKVJllCUiYzhanpZ8iMxy6MIErCqzW/mZ/edcM2efx/08sRkqwYx
LPmx0VASy44YwmpUUH328/lt2mYfqRO19FIrtCcmfvT62KibssgA37mTfM8EjQOnwQb/GWvZRvIc
B23rvrWJDapU+byxq3q9qxoFXr/gYnPifqAGitXmptdpzL5IqRdEsCTQrSXh1Wy53DHZlTU31X1Z
Zgnz+fqB4l1oY/GQCqukkNJOt4/cuDCXiXg1XJZnxCoVTWR9p1Eo2ZPmHxZecDe9W53A2yDVRjW5
dIDADXbjTGRTCB9z1dhyEMz1grbsHXEBO5FTAIp1SbXN+XvdQK3Wu5s/iXTctK/MbiVP1Tdg4zJn
rJW+PvGOUZ/MVXYkKlJjXm9nxnDVcK4vvq3OYxLPytXy4nDMhW0zcQbnEHphVsPt2zqob6DHhjUk
HyHxejCIzpB7/2FsNnmZlu9fHs58lpGDEzGq2zxjnRPbfVxqB+LqPL75cuX6R8rRZ5b7pw16vmjw
cd9zm+KAuY0qX7Qsdr9z4ChFPJtskmEc8BuBymJkHM8zVxDX5EVazPwpqoJTxNy+dA+8XqH/a/TV
TQG9LX1Ogu07dweAiEZcaZm8Ol/BGan+wHhxL5ehNVBbI76+hZsFFQh11gG4tdu3eC1wS/MgAXn5
IpyOA3ojrjCJQWo8161Zm4UqXCvR3GD9Iuc0zV0wgk9jeZJcufW0nNNKrOMewqjpKkODArbIoinH
Ih8WcIC8HJLTJGOw4wSubFLSMGkI7l0fGM2/bAvI8RI1bWFuuiyp8j+0FmYa1FdX7vLi17937wxv
R6F6dZ2361MzA5df1pjGW4yaGeVCQRAW1/rD+IxcskDEG4HUZtnaJ8VcFK6zbVfk/ifySSsFZjq2
PZhCDEDSmMIhAznJZEvzod6RJwV9NUcbN/7duK/B8PUX2KPHLJRzYgCp6a8y6zkR5Y3rwp0h6xwi
ZvYq8HbaAvThba7dm3h9OmDEf/2HCo3YvjcQvH7wMEphyfWXsLE+1YkjiGT/EuxSDb7tysNYOXqH
qFkeehUakhjw88DlnmP3ftd7EKlK30IUJWJFpXgqZm979MDJqqpEbyUsozCbu1GZeubJFx79hxdF
oC7fpUDQEraf0qks3eztMXDFKlpcnTfRrd2dvQTqahbGLyLld4VjhTWw8dVN49mCJr4Y86+kcfCS
nkGx8sXoWjEpu2HM3uyW5tJ2vHEdKMfMmhRel9LZN1+aPxdr0f7+cIGqI7MLDsp7ZswcW3x1brvH
MwunXQuzT3KPQ0y3ISxS43NvAl9MaGMisBXZ31glcFgCDqaHRFgvhkvX2y98yLWsAeU42FefJSoo
Ffo2XHqiVS3XAKKtFB3hNvqYABbvTAxc92w8znbbzQ12ICYNcSC9UD65MUT/v50ls4VxN5uX9sAL
f/lDkAHAF0yndOZCKd7AKwZNSMyq3fmKoteXyDWPfZjbS9WQizJHh2pOGgvJyraHAvHlB+amuIgP
dQLhFdVv49hIulZ7heNjeLOXf4inFT1iH5qSnERslgJUKBPYoCYcVLMGk4qg1OvvIQeYqBSW/Tid
cRjxM03hPQt5uF+1M4+qF+ca3Pqiqn6pauxLspz9tWLQQYB8udU/wsQT/HtZyJ5Ue1jASkpB7Q7W
SepGaedu008zz0nc4+74AoqWE7TNp+t9JGkPmIBkPUmpn16vbCrLYDTQUWjch8l8MgqAqXtI8Nkg
FYVUEMJ5z5iTzt0fE3ZqDvIjdqQBh2XFaFdbSjxQP5v3MGeXgxXHAvZ+gjn/PAaeRGu+vt9v5z2m
9EQLiBfemIaSX2UU0hDpgtvQVLvPAfBDKgK0uf8botddqgzQFyXUDm3Oql+jr0X0kOGwRUaQ3Vct
mmGxNSCap15wIc3dusHHIYyKwhKyyrtmyAvCw5B6IxRmPYWq8LAek2O4k6DwShVJqaN3FZVyMUaI
P69noIOt/jCHD8mhdgdO5XVMuMv6ymtos714Ij9u2VDw0GBAR3h5zThBVv8t9UlfENtN0lczdAij
AzeYqhfmck7z/LZqE3DkB7EI1d2JngtLIrY4HTEng7iInOOQfrxmXe4BxEIsgXBgTID9PewN39tx
QGGZkDyStOSjIeN4IpvLhur8vgp9a8COC86RUYTGBWUmUtHFeVtksxtXPlet/qYGi5drxGUyB8vn
qfLGjarWpTcGUJwZt10EvhqjW/PKiXlPErkArtRAJQS4zZ+lBJmUeMSpn+0yQVwTb9FNfqz5gQWF
dOd9k7wL3ZQxCeZiupHO39E0XGJuSDB8Wo4j/ZnHRgB/ODAoFqJNcyDfe7W7RDyshK4x8NbO6ulE
zNXpqCur7hu0OVoXKOnmG4m9oxe0eCgpT3Ds+6yxbssRcnywEyprhHH4LJpg54BN71jGTLVK8Whr
1DgCmhAaxdpze5E3wS3pl7mFGwgpIZSFvH8+M27EuZC1GSRy2hAbPnYzLkKRivNc5/NSichOcugg
kYFOVVjZb8GSKh1FCbLMoFkIciPd+X7Sw2u8x8LuZsCtuENgdHfTtI8Q4gSq5KdbVDmcy33EhXm6
HHZUklArf6xoDkQUy9m+cx/W8fI965DiwKrmczYFK4+N3OSIf5bawnwtRHoEgl65XTGoHkf1SN7u
4LEG8cVmFKQ8YTaR8At7McryJKkdMz/8gH4NFBO/InVm3k/ZleZBygsF4pHGNgbFhuWTut8fW0uS
aBOI1pgbgbrVb5SL/XgGyIPWL45CAFBQFNNrvip4+yJAX5f20SJZenWLFaifEx5GlgD9/3laQqDP
xb/MLbYC5FviYicns8KqEzSEm7cbWj6jTSZ+7qHuaNdK1KgaHZatkdsbjNjQ/+f/QY+IKVTmqVir
pr+3ZVLWMTATLtXBCLTpK1+Moo16OzFtCRCjuNcds6UODuicx+ByIbIM8W2pQZSxABs418r4eOOf
oPprLyyQ339EsiE8nnleXKG23YjEQvi/eB9DPgwa1TWIw9wioXpVHq6hbaQ9IIxk383iix+wHLFM
GMdsbHKcrOdkzcFMmfOsV2PzK/udBsffsjVbueqdleXDERtwO13K+w97dnkvJQ24cojFJxON94j7
ME5XnmEPATv239zxrrFC7N90UK/a7Ba8ElqbsZ+lU8E8Qkii7i5490oOX3Mq+MbJQpDUHgJTDylC
fZdhWfIT9yqud2RONf9PPAiaCme70PHz4fLgCXI+mbRVzbX0qKj27/v7mjTDDmwIsgOeTlZJwQ4f
qxkVhpDRQ0oALNbAcObyOEx2qm5CNXnQbXOXpv7/+nnZ3Roy1GHGt8vSMQ70kO4jvNiEfMYzAphc
NfT8LbFtOBIbnWKsEq65aa8v15e0HH2qKWcKmEurgKXVdu/B6S0lxLXg8Z8Xz8sJsf4T3jANQNP5
eohZq/mqNLukd+H/cfcFHn842dpXsGTbwrgYb8cP1sbyuGPhf4mLBrabgDc57n1iR5T9tOMXFBYK
1AVnOYt4f9j/EvZVwb4vKvDGBQyfjS2VHBsrx5Gv/+BJhzAq2+RkGVz8Qa0Q4OsvWq7OnJPxbNNd
DGso0rUFbtJWZS5fJ2+oleRXD9GhMYbfESaeqpvPDIQbYcCVGcc2MRFjNY7K1/E0XaYFyqE+CH9Z
UnleVx33Co4emY8YYNc/xcUPfYTu7KKvXLdu2jMaMCjKQq5a+Ktb4WUF0IuOv7p2nbFZmrQdjDJ6
45Mno85j/58T0E61W5uATbNTJkrZyR5oTpHylA9883YQbierKhcIs1jxBtPuWtFB47g2wSoLrJJj
/s3aQD7xOSo5sjZhxCIS/vzi9Og2bsdh+Hw7IbIeg0/18Izxuj4rqC+Hbp6ba+gLKuZzGJalmFgN
Zoiug6vHhqPcd85roj4KDzxwCrzho8qKCr0bbzS8xpGeTmpylmS4+Ge60ZUQQqx7CNnSBCXJStFO
wggrMrM8sQUwlpLJoJI3GrJcpUNd8WzMRRQ88HqOc1Hz8uUDmUbjt8SVzmromSWnNUX6BjyqPn4b
VzZ3/dT42/Bf4594KXAO0oGOwEfN2s2w0rRSLoa1doe5XlnyRMjFRRDkTFiDfBxtbyQObuL50aBz
HKQzs+SULvFhAukRh4zFMzsufZOQgULA63h2coanMP8A+LbLEPKGrA4o+s5j+pvPZb5hFCZW30ae
xpzT7EroYqnuyt1SecxNGWIja3rRQz6VGDVgdnC7Uu+Ixx83ymLQkSlmJNpOSko+2GAl+IyWTaEb
YWllp19HtSSQCA8Hqz2pCwD+hQRLqZKRfkVYX700XHnkaiTVTx94POlGof5rC/BVBI67ZCs7oeZ8
fH/7/E6pTi75lvDxmsI0n1T8uGQ2EQBZH0FkmhXKgDWRvBnOPvK1snwHIq0b5zN7nt+XEIlbxvzB
DS2FIp/0nDiPCzECwDKTw+3VOJXdTqMcHmHUbk4jKBQG5EG1uyMmvF1uLYQj2WVxqdGA9UaSpW56
36qPeNW/j2w85LuFlo/1Q6/8wafbVhSQS0CvKPF0GdaTLSYm8AWfasbJjRv62ZM/fPluunwG2aIA
Km8JyLBDhzzK7/OeWgKYAB00sMFSNKyJoe7IDb7vDxQmcBElOiYbznp76L3a/4oxg5YsBKrgIyM2
ivRHL4HyA2U0xYVU2W+ING5vYwzu8sNbXoAthCZZz9JPibkuOjflrJWxM//52LclGLpHkU97dSNG
z1wpFDZL3WVhxY16fsfO84H6ERzkPgSlklo5WnDgqWv87w0yS3DzhBCEAogL7FxQH/JFT89u4DXz
3hcglk7Zc+Pl7PmJtcoYG22YIGqfrDAAKy1X/uvwiutYeyqooPvGMrEzsnleGvUD67s8tvwcOi0d
8J6QSxldjMVMhg/Htq9Xc2uzYZfQqWseihshJY3AkjJOxR9u59CbCV49eqo1dGN3zMdTL/oM3fQX
XfS3mr7/A1ntSm29uLdwmXodhk4ye4WMnMfbLUEiHgnwNOJKHCBkh2aGr25P0ZzrqxBL+CmvrjZG
Au6p41xBZK5sz8GDvduVBSR4rajyfpVEYpC/dA0nGNZpJdE7YmYZXlqP7Jt4tf+cMOFjWkNGkw11
APVgn1dIWJJ7O2ps5JINbfFARYywoQ2Fk+Pcbz0VED0Ziplp73lbvxfWF3H/++bRHP7sqb04KUI8
YKKtxov3N07gQ1RXPqXVb6tM2nFz2Aymiz1JhjZLyBGjhR9p+fGSxiF8zpMFdjoAPddoB0nxR/DP
Rr3TXRVXIkfzMETqTM7+VsSlHwkFEt7cbPBJ2RfkcrK+5XZ7tPmVaFJ5xr8jjz2HhLgBCwzEVPNC
CF9TpzG7ap9XcXsxmSNdU6mTULSVJUnd1WjFnGdr4sVXKIsimnjDlaNv3n/0+O0lm3DbRPiNQldG
mujUslKgcqOXKVJk2Qy3+fBpJ8aRx0UQVFrpi+X7dyVx9jjqwAizVDxbARSPL6HVW5UcI5hLkN+X
7cLPO5pXkjRa0Mq5Xj2HGl6J64nV6gxmzi+aJZf7kufX/sqE9dGKilJfRKwYsH79te2S3tAIfeA2
7Z2AE6w0nwZBQIQXwtmbXI38OL+b/Lz2DK69Z3rQiIkggG9aD/qfCLtiN489he1MZZl1wKirGaOv
srGY3IfBKt6AkxiJzlQshlcFWmzfW8omo0MnAb2fVyY1wBrcxzJUopdgC4rZ0llRE5ypam4GlGTo
ZhfeHaIqoSUhVez49k+3kp6nV0Y9qxgmovM+FdM60/mSZcY9A6/YukQRhoKItTHkcMTC27Fr9Mvd
gLpsfGEaU4lA/JB/1TeTKtJAmKYxvnq3o0PmF4lUuUl81ZO+uADnmLqw1QFXrkPSSrIGzUh4IV5N
7btM7fubCTFaZHfuDJbQGMnk9pCynOlEs2QnjykJNN4jqNrOINd+wFCSCzXyF3wATkrOJNfLzA+i
6stHuvOuiU0XAFFVQ4bnh0exxtdbYloYs6Maoiww9QJwXzW64v3R0pb6A46XPIl+PjUG3GPDAQId
BOKTvyZNzDuMj/RlWn8qPE9HUtPl8x5jr+vXDAjevZFjKOB9yiVVF+SkR195ULUAspvfAUslKGmm
HwuYioKbiwN1u++Esq/KqhISqWNPJC//8w+fpvCermduvZgSD0A1IBeGzZ4FMH/yawfhrPhIIVQM
nVI3SDI0MBpzvohSDesmOFUOu5rpZ1YXAG6ZLNRW5jaLy9IBQOZ2Fhl5DJJCIRFp+5rbIhJh+cec
+nS0YWLop5q2bGgmJy6UGYcWdTTJeBcYbpRa53NzYz5V38+e9ZOKxkc41+KjrCNxRMvfxs4ooYn8
E7T6i3wl09wBmQwo6pgflUqdFY1hjZRQXfB7n8M7TKBpgqT46mrdtgi5QSn+M3v1f5RqgYQyuelK
/mWcERKQyCtkAH2FxVMKpB+f8Now88sHin7oovwmrMOztYmYxyJNm3tU/u6etzfNodE9FXjVrteW
top5PkYslmdb/BS1ivk+GRVSKqEWv8RUbTQCtMg+40w4zmV3dMK8hmAqgi2E0D2e0ecSximFBSN0
mxEZ8kJt217/obrMy6TGe1qErdhpKgL7XWrs1VrT1e2onPT2VmVEAilBC6RhcBAvU2BPlYgwa2lK
FNcL+AcfDXbik/+4xYmqV+T2T/VATq56smypIGfaH1TNI8SN7njHzU2cEBktSN2iNIVe6MJMkdwa
oMBQSIAOxuTBxlQP48oqRNj/zdhFxExWTZW1WaGTMV41JZf2EI9QfTHWNvuBZJo+GX7VmH9WaTji
dDxd3vH9ImjKKp7gub+Bt2yBGc/FVARPl2JH7weYM1IPWQ+Kq+szEPJvzZxalYprTv8E9FUIuGeQ
O2SMZLVNSaa1eHbEciB5Y/4DQZu+pKZYYdRPc4XAMousoyCuh+6GLPOW60ViAg9ug0EqZv+BshCl
hIpdraSBLoIazLNoa9iBKSamVk4O+jsxSzRliZbrOlEOTZW5YTYxFrRepNLVF8061UaNwLIj5bEd
0PiPjDVCjkHQ+oiBQNJEFLg+EmCCp8t8XW/1jwE3tJhKNVMBeRIWN2+oqmSPcxtRVsD0qvZKnEmh
qSx6k9V4F0QXGMjeYG05ny5RkfVOkBAxBZV6ybPSot5r2nVSBcoU7ymrkUH8vAy+uqEgGP6kTtAM
bhvrBhW3FGZEvM+7Qrh2hl4Ey2PfC7LSVkjQvcPfNoDK0uHTniY/wNQaqpzOWBapzQDW/IQL/x3V
RaJawzxFd/tZC2xjZ+1g6DSgABqVQU8eFTITkSg6VMx77RT7UoVvLhZs/Dls/KaDn0IdHjap/q8r
lmeEvDsZQ8f19Bma2oEEB1IKE0XMPGjrfLBK0fXiuYizlN0pF73gUkzCAiEKLyeculVCxjgwvX6p
jj37mT9adRtlk0SW0Dssr1ewYj2d4YkLZa0JQ5okSf/xtli8xOxavhkTW6uSsALc9M/nECaO/HHo
CLMedfQe8awCBesOy2BkVze+rSC3gCLkA3eGGgQl4QftPRvRmLAOw0ckWxdCrI3zGA6HuGilmG4D
k3BnnIsz0jBnnArszuCAtAC1mieVRAdnjGe6YwCDsaO7RXsOudPerFrhyzcMXDj3YWMbtIC+7gNN
oV6gVBVv97A+PWzH4QOyUGgN6aM2lnkqTs9G7zLHNPtF/bFGTQpG50U/i2CdZUCLNC1Z8WHDFxfo
gWu1O82G9+uNrVMBFRw3AKJcu4yUVenTO8YDMjiIIyZra04XkPTO3qSLTc0VS/rbNim6uQILgB5P
l3C/SMy0AezD/OAtVbXwso8SIQOH59rPGUIAbayTOh7uCtbBfz3IRy2yCPKJ3jeS3Jd9UV/V1l3R
CJ51AxlLs2TG/v362MHBy/VoOmTCw8PEDmEV6vIR6zC4NOPIrcfxMXNsppgPQRgTJvK7YFrfv/Uh
3ubQe4kY+LeCDXRh8eGCPuuOBDEwQq3sRxnBrym6tvm9nonyNqiccRlezjAaOZVw3uWFM93N0V/u
tLJgUxU8B2BFCXvjHjBeUvd2txfa37RtbwuFpkeI6QDqOgO5mjbq8XwGsYtoC1Sds6EJ0QoEbL5J
Q3NFBRfmvLtMRDVknGhB8YhXA5LXTtwlsGi0JH2SqFdbjqCGzcp/6PXhXKxKlgDY7duOlFfXqW5P
l7hAvrn4Nv1/TXWBEP7yNzX73mioiBD+l7CTE2zLTqAtQrZlF5VWFKEpfITaSHC+GR+B6TlcvXoo
dSB3Igq83e71ZE0Y/CkMASbv1CY5JKnSs++ZRGxF4O+XiOZfjUzx/mqd9v5XFWWb1LE+BfEVYfEA
D75yfTpCJVUorreBVAaOp3x5e6PWBxqZxkAsPmwU3B/GLsf7wbW04sM04fR1KYzWxuU5Fg/Bd3Hc
gWdvphHmzkyMjAaxhfCeiOCPSA8BXuhUlw5jcJMlG3aY0SD1PhyhCBs86SEKEY1uZag5XWyFnl7A
QNqAubNABovaJSbiC870/eC5ErkEbzD2KAYuRdQjxCVelaqJ7UalJwio613zTxiNVRBVQu2ylU1D
A7Q2YHAe4nT06yWoDlmP2eWVNX/1/f7lC0W/XolS6Q1u9gttsUVWWoaP9dZMxFnyDvhSF1lx1MsO
XOvwHhu6+1n4rB6G2NHlgls68NmBKdUuD1xpfl6QFei0qj8Ns5YJOJven8dhbBGkURddmrBS48Wk
9ReZvH63QbPf81WaclZXQc5n7bsm8SoV/xN9ezJ6eTdeUAoPJ9gggg4XeeYCtY67INUsX6dZFra4
ZaUqkxpuiVPhMJcqp4CLGQYkrletQBqyATBA4p4sE35HR6acruZmu1ZxHLyeExgBZyzsoUSO8um1
o0K0WrXYl1eYyp8zx53BKfZvjSYf4DS9HjJNav8Y74QIGz1RHDu1wkt00BSRn8xDLS/v0G1bRboA
TSTb15gabL1jFdMHyr/QtV7bzl9T5HKUPhAznc2EI3Pc1GMXr8xcX/D17eooxWoFg2w4YAU/TisM
r2zLgkle7N5p2NXJR/MZvYPEZuI4678Wrv/kIsM2OspjpgE6o5Mfr/D8Ex2GcnDoGPM3/6VLPZBT
NYep6gDn8YxQFMG3VGHmE/RG0NSnZmpVdu874gZX6+FCj+poqdUOJs+NyqobdtzUBHxTKE+2ZK4J
W7aov26bR8oAfkLQtMY7e05md1pdTjQioiTlKzOQxLQnOWgoAT4ymRtLszqT2ibbNLHIPfDIVKdt
Jz3SwyYuC3tUnaK9onEFpg+IMYDjY/MvZc+H+gllGcVf59sfQaQTosn9eVkqzgY/6oLLJ1A7wMLL
9lADzhuN+YyciHmQDiWrOUK5wI9bAGjf0u1euGOilX6i7Db0FBYAcOGeQIjhzoxvX+swlUONZRv9
t6aienhWxJG98FJQYqQkTo0qSCVUQfH0e8wS882/vHnFBolrlM8sae3c+Pnse7PDRJWoOU3syAUo
OH6onZrvhhre7VdsqtL+q0OYJyrcJ/mVDYhBzyoBpQnSknKaG9aJC4JCK8jemRFZVkokXiAdQX/Y
6NeSigIG62LlQFUo9o1PWIr7QKQw2+5RSxtLE5RSUfUZzjGrCHudw6bggZWKRPZEe8DzygqKKf8k
rcCIRGkyExJuqw/mJ6cRgDC5c6EPy9oOAfz7RXAFUEpVl48tH7rQU+q1Y7mppRD358xKkP6TAnnm
n+Q0vbc62NBTmgsAlY38Wm/AtsmZztDbZMEzM3NpAsvUnO9N8PQR2Gas5iShe/6NP2C1P0kd2iu1
n06DJwsDHEi04PBk2nsBFXWVm2TgAanGrG6MQPebV9/dtFSo0+soKrF2/pAVYlWUDAXdmGHl0QCe
x73LvOQpHASwNAo9bEYhbq1pGnaU7+J+2uBvGq4WChKtdGYCBVErTB3GdwNpIQ3rsTzMRu7JEfQZ
WD/8yLDvmabvy1rgGO6IXFtGoWhn0HIkH9MKvtCAELFRt4dmm7p4O1Rt7EX8KmssaZI4I5u+fLZv
huK0g/lvjyOHX29+TfDgf/kozlPQc5Do80lHXRqW7/P3hrb1MbOFVl+0iEvwviEG4pUojqXru1+e
ld8FGixjSJNB0efND9yqAU6FykOAKm9XN2flaPIb9wSvVZwK8rTD9wmZpt9E7oqlgKun8LM8W7Dr
VAUTFqD6xevhhR+1D+A5rRZxvNRbPY8sA9Cl3GWTKk8RrerWqh7FJyC9Jp3vcOgdi+y5nXcXHt9s
z/2NUJadEfbNyLVqLpFacu6Qe8/uZMIPRRNqGpaWkaac3mk1CGlkCahc4P18fDvEPdyWCQ8jKTd7
fN5OwvAmlEUcmMbPF5UXlWGt8oKssDAv5NHA2lc8CDQlWfTNL7ZLI0bRlN3Wk3EXTkWzKiyB65Yy
s6h+N342mncDiJSxoaDk52HuYre1VxpYsV2KjtWEO+Sr55sx4OPEdjCFaCxEG6vf3tjGVP8DS4nX
nKjxuJEOn7U70Mn8l9/dA7hTDx7f71VcmnQc1tmhmp61ysJTzfh6X1X5czkp4FYlVytOre0Ul45t
ZM0NCA/D9vUzK+xHeVtyJ+kt1odi0qa5R0awBu0kbuX6UhTEgCg2o9xYAl05Tx+j/erhi0TtmNQr
SZIqy1hcT+/9u19/WgkrWcz+ssV/vCweVBf+U8lLVGZvYD4DVyDw2BQSHgNhFZuOhMVtP7gfRdTP
tofjb/82NaIsRaFtjwNGa2KCw7nvxPtuzo1scGWIjKq3OpoVVi6lyyNQQcw/BKDljKsqXDoCy//n
BkfEPRkz4Mt9GgeWW0R1OPW303BI/67AUupMEI8c96wlpzhDmfuHjbA7/MlOMHOo2hnlvhvhbBxJ
avxdpMcq5fnnc9giGUdhHWBKhd76F9lihVo+OGgjpR5D9uWqbwSMvqeyNT/qhafdyYj2vKTmDnf7
OkpMziFHs4AjLNFiwrOJa0O1Do2FAT4yfc3OyKuvJM4s+fJg9XW//cRHnny0HNFS5+A4VlX/bgiy
Mlowi4NbEDHJqa9tVDJRinJz7EtHhbJIBxBRrJxpwwm1grhXIQ73Mw2SXmwpD4AjatxZHfmlXgQb
qKSLeXdrX+u9MjGT73/890vip+d8l01JqS+7KhsmRQ/8FN1tFrNbMwHbepw/CbrEYwnEb9VOpYGg
8c5TO/31o+wqx1JeHqWvilGGidXawPc=
`protect end_protected
| bsd-2-clause | ede9531bd0f03c6e883b3a894ce16384 | 0.95172 | 1.820293 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/blk_mem_gen_v8_0/blk_mem_output_block.vhd | 2 | 17,222 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
SbkY4Mqi+PsQdDC41WUTkv2ca+8PnDf90PPLiqWAquZCWX20/xiCAane/BI8ASR4HNzlLnTOqk9m
6ngRJqZPBg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
JAS06P2PeIKMgk4f+l4rygdI+n2nHo8TWdUc/PhOlF249S5GuNozqc1JQRM0woGy6ZRLop64YmKJ
HNlzTpbKUtSupPT5QY2ktGIGygeKaPooRm5wMQVEwdxc37PYKoLYV6a0m4KV/030Dyxeisw1f5fr
7xQ4FsFi0WmmmIOjmPI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Q70yXul657LM0ymrYdOnvknryUu4W0S/UKtDcQfmo8g9Z2dnD/mAWaNg3JZDx7rOZ6pgVqc4Rdnc
QpHkOHN6koWLH99qXNBhq69+4jPAh4OZNNHP3Hl07M7xaf6iPNp7+nyTY69KtHNmtpTg4P9Qyp3r
fZ04H54CzQJtTSLrIBcdU54nWXEMoVd1A6edHHqpT3PNty3Zi5RBRMCJzJ0SfEBwryKBwEHXXwDG
g+pMgXZDY6XXSPFmckV2q403co/vTHu2YbVuYIchL2sZeVnF3AF1LnDq5aSQf5l2CntfnzsFB4Go
TmMwonzNQy2K/ao99C82K8jKeBUiqzVTICFDaQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
ufQxSE7aqL8caXi7NPhQweztycKQk2RQqvAT2/tX64CRf7aK0lRp5OLGqcU3H/G7jgQZwlaHwXBN
dHcevHC30dr2lB5cLiO6o/B6R5IF4RbLoGnb73ffwlsxSihPA3qWX6eHlWe6CSxj130RBUxhSUjM
A79IA9eHk9kI2+V3vtg=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
tw8ba8MkgCqcCI/VSWnyz6NtXO6NS1wZ1TemOeLTJm3a/0MFgQM+1uVD8Z/3PifYBddZs72aPABD
5ilj+340/mONSLgrXAEcvh91LI/ZxpMgFxwxCPfKUE1vKAGWeUEuiQx98xEcq4zLjfi4OePb/6R+
j3nBH6XEQYDiyOqfkItUPSEpLpd8zUaHYKqNIjQsX+f/MWYR9EWZQsE+wa7LMNroeVDUFfTsXOql
CvqaFjkCzLLNQv9zFy1spA/IpK+Hzzyx5P4sXp/vkFxVUZtlab+FbOQwCmqiMEwvRl9+xG1cUZgK
L7HB3x8t9fHTHvuPnb+cDZEBrBfaw+q9tST+qQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11008)
`protect data_block
hwwhdeIOioWd9loxp3bxaIUpb0lKlp0/wtGYdtlWLbhpxByMAArj70iTKilkxolHfWv2AvSp1Xbh
zcVJDzw//+GDILkcRzZB9OGKqscWZh7eKpuCRUwP6P0b2q/vRgTiNZmEeny0FvExRKPdcg0/8X+U
hyLN0ri05Ygr3nwgori3UTYjX2kArme+6Eaqs+gR1XsH4kTYG0PjuyAWT5DXrgQBMSgDVw3nXY78
bdPamrgZPqJfDxjf1gUQ71XFPZA6E6JjUqb2igng/N/DUU1KMTltMLZJk9GZd0TL7qNS1gB18PJ7
iX3iEU+x/khYXEVM9+/+0AKS8xoXxq5DghHV4kX0FIx0olbJwwxS0dkQb7qns6VOtAB19sckCkoN
2CYzqo8fcVR3jU/N3Km9pUCPqFDWq6SSDrq+FrjKvyKBq0Gf5hVQwX9XdrBjSZcbvVfN8YsPSydz
MdcQ7GsUD19ksC/5ep0lb9WwwV2gbvYnavHSAo7Vqgj7pag5+dqM74EWa7nTTLcRPmzV/HMKdNtA
XXSgdSDYza2z0jwlrWHe7LJ7oYtIXJcTxOpjdx+cIotSW2WBKtUl2E1UPxGxT8zMtGqk7p502p6v
C35qbKuC8aUuKIlNzEzD3Csnpp9EDRlN50/Irpvzkjf8QH5I+/JcUEQlIQLrZfkhcBw3rOGggIVF
r0irNB8Wfmgg0TltdChHO9pEurXhjFljZJva2vR1uwznejijPYehbrU1ezl9xO62a3d62r+f6Bdy
OkMEba3tTN3IlJaV2TBO5OID3AMekTD9p1qywZ3wVggbaoodCzIl0IFfHeFHpwiTaU/n9AaJ+exK
KtfYweBaPJ/nJ3WQpq1O0W/HpT0SvTAJRECGRmrdHEIxkETfFSYr1jU5ZMryWNcCn0MNJcDhXfB2
R3HffIhoFbMrrscsiUGkfNX2YdUCawUGHNNmUqEFEDHpzlmPK8efT4NXTeiOAAbNAbFLlTdwPzWx
lMiZsbK+pxZMeLi1u1XsvXDo4BVfiE9yvEC42sTukfE+0jnL9nS8rSF6dMpAnqpHMhck7Tgm9mlt
yf/L5/b4a+e5LBLtTeg3vHqa2AgMnJbLJSNsZlpDvb0oIzeQ/6P2od/1KrYheINSQ2NnuohlApE6
EKbnFNl0NkiTVg+0um7/J4xWeYPW4j9sGye5Zl/l1YGnuefOtBxCRv+ZDLC/lLeMJayWjlcaxJyw
NAUYndJgYSbchvcGEZ6kS5iHnda1GeryA1gZk8THrVzBUDDWBrFoSXbzEL/2U7oZi6EMLgi7fbOd
G2UJ47YyP+yMCCxDNaZEsp0TT4oJsL2l/lAf9UDAT92eKFaplyUPJdnSAOWQ8wAm/3KmfEqQGXQx
onN2HA7aoepWXwCK6i7AdIbn9BkwjWgmNjA4FfAmx080Onb6ezSAThFdADv1ogZK6L6duOsYfgOd
bj+TGzwtXs2sv2GDoq4RWWdrUHktQ836gJwATf71BNHSzR84U89XRSQOSqYbk94gmSSJPAUVTJFB
SFGzbm8oPRElDP/M40k8mM9UXe1V8dNI99y8VR3Mqfb7oWUBj8HnVRpwIESnclB8YmNmlzIjgs4l
cKmT8ygVr1LT7YG4rg7cClcWOjIkcr5ao6gbyVqSeNC/GzWM0boZVwreIP4BuOA84DyN7AMX3rhN
5e5EZkx9AlHWXggJkwT7CnqNan+ikfMTZJOuV8x6jpsi+1ZloWrE/PNIVhTKbCQNc1FXHdYWvURg
bpWKwlmHolNC/ZH0ETiM3TJwLpHztPKwbqsobHdQx3oMxlg957rfiB+2vCdXufV2v7LriRUx9W7E
W+w/bs05GAM68jvI9kcDt9A3pHoZ5Td14c/pMprQcmgGNy2uburJBgpWRodkXy1aEnaJHqyU7VO2
cXuNowCxwETAuEhfw/7SsmP7fMZK7fd7DGoIYrGZyoxuUQvDKZmuD/DG5C2NBKcSMFfNXHEV544M
+CpTGLau7q+NREJVM6x+Hr9xtxkUg6HEPZGbFWKalhu25hr1R0lABhUcSwQFuy7AzTQkUd67Mug2
EKA+sl6KYOHnbi7VE4Raer/g2TZeAr3puzM135i8ZptZgTBm78ezfH4cZfg8w4+Az7fs3toaModV
a97A2gF/TUegCrnOOE4rD/S6vg7+7+yefqfYarQWE3dIAcon2TfCJ/SAIBqcSotuamJkioTCVlnR
K0FOuHmUi27hAmB/cb7r3NuBRwYwwGfwRnF10zTPULdZBW7sRQuB+t0m4MLzeo7uBK/sZXks4uDI
bm52FGJl5dGYY5QQuaM62jtS+esZjGnd7KMHDca2GulzIbn4h6/CccacIpo0L5u/kB9pMJuBmdyr
HHMEqZ+XybY/J0+xczLRURaQZdXVX+INsIKbqP2ixjxx8L94KXHhiqPv7Ur2vRNAeqD7kM4NfMLp
2uMwJC2i+I+9jbDwnV854uNUw5bbrm3rcw1fcSMVdKDKVJS0j56KoX8IUJIZS5tOdsznhPuuFC1g
fZbLsCww7ieiArnpCNbHbiVBH+8mX50WHuDnk+LeEpdvd7O0NDMA3SjEssUJofe87R1gPF79GgP+
igNSVPYelDhDFZVxLiNuir7l4qOctPikAeDe2Z9gS421akKCuyWq+0FXRgX18OiZZrnBsrkzkH8B
Lniemxe3M/6AVj5ScS/WyEtVsj0hiGFHrpV2LprirIBgwgI3hRFRPVfCDoXfCwXrNLB2bRNlEavc
qjaEs0vLte+n/xC+jTwPs+z2+hxVD7lVbFq8eNxNTMNLMP8w6RMxpNz5x00TbM+59QaHZvRl9X6X
mCdYWTR65d1KySeXd37w/APwXTPnlXqjMoyTEFMiYQU8TY7/8pZUVRb2pfe1sx+kEyeDie7VS9uC
qW9Vzau9Cbdozw32sQWjAqWF8kvPpTHJlKxTHxFz+OId0DZ/SpgCmqIyCmI5FstBRpy2f6Rk35oz
JuJEQOBgGg38Udo1dhSGq4kEIcaW+rpYLqjnHyhjtNtlSTcoNJud0IuwcQSShcX4h35VvWgI/ONb
Ym5XA468jPoCHTFIvlql5/DtmQ51yMvcBb94JJKYMXnwaIVkZ4mVaBC8mZuTP1IxUrGsvJrsFRBS
zju1zjtj5wXYLvOlCxK7fE4AV8URRm3UW2M0ykbQfJp3AwAdNNIbXh1a61GsrOfg5Il0q512SIak
w3JycOAX1jLrudhZ+KD7C+K2rMSMwQ2RajIn1hj3PEB7RhzKL7Im/lpOhzt0bKuE/6bp/GlpGezB
/UguSlLowK5wzGOi/p8nzw7xVZWslvTFc0eUxoJDRIobMLHvxyvKYF+03ts9ZNBzjXmEFHJ/Oud+
OihAt/w+/80qn0CjeskpJO/i4Fdrpp7YSOWyzfCQrcjN3V5c9YaGz9AwCeuR/4HE74udg8pU9AjL
MJDAXA4uj8Q3vgweZDO6jM12OzsBYAuqe5BbmMGWrq9CzZ2HOBR4HKPYp85FO5I4bIJN/KRtakyX
59ncOvHsiJeg+fGuPtFJ03fLVBlTxQcDwCnSpoUeCSVJRgdwL3ify8ybXt4oCgijVR58R+SsTYGD
Ju0y8ge38jL3nmibvd1hmwvD+IV4zoBY0BogyBpMCaCkDZIL/q7u5xf9l+cps+HThXuDWEo5sz9E
AqN1dzr2E98GtPH2cqMqqvmH4xt3Dg/dsIhIDaiVM9tDYCsfk1oM7EM2V28wfh5K48F/u2K1bcVn
xTmmCpPFSdZagAN4jdHIMSi+6PrQji7+wX3Cb1xmghW3AODv3o7u+QgSeevRL1EAYyiseVbryEsO
Dzp7tCLmUuL5pm5S0ppFvVpUw5dBnUCl1S0lUYwVcBu0e64DdtrtSBreTJHGU2fYgm7nzSfJWzqN
MB3YBR0Gha6UgVMBUL1mQZCNa7x//u7dzCbPyFqMonlmfaJMeMRAsmV65bTMSjxx5b0XinELg65m
DCvmClN4O9pkwM+zVmkYCquurnsaFr7hO3rDE4vIGpSZdoO/M+CL/eRoSuJa/9LafS3nM89OyUTR
RPNH9aZvgzpUhP9YTZ4cW3gLvYn/BNGdF/b+ZMp8KL7fZ+VEBhHYuPfci7sEgkCUIVSPYqsAMBFF
UD0g4+kjTedlheHqrkA/OJjdKPV94PfE/UhIRiSpYL/bo5JSW1lCJXQMKmjkxvSex7oKjWlu06k1
GNGAYzY0w4mWjibGTXUhrIUCuujR/kfQzQCA2rlnD/Fkp/Aj6PLxN8bhUotNeiWi25nfwrDuTRje
ZR6c2bbMeNa7lfdan8W4yzbk8Y6AKymNHgIvgQgrNt2JdZJX/2kTilaR58aKeteqM9qow5/zTpuJ
NgLUyzW3oPlwXANnZlF0jKxwErv8z51IH6Q0dWlb11EQGHCT4JPTFV1f5+yBe7QAAXBspwLoeKkG
oqyANKPU5DD+rFsOhkNNqCveyzA+LN6TgN8JyQFLeApe50fKHH8sPbOUFE6WrCdwrDoJ3X9AncHK
bbX4Jm/k1iTJHk/HIgqnNZCDuboK6VwzQS0mwbWxmPxw/hQKOnb/uPE968mAxeh2DZyAC96Bp+6o
UKguHO3Rp3pkA9mCYZqW1cNU+ZGwLpq4541PWijo4+cJ4z3sWbuz7Ryg3mfG5dYGG72bwKmA2yoz
Q+9Wnyhu4roc2nydmkTsP0j0DPpaitqKWLe7zdoCgxW7GAJ/x7q8HBxsudQURcR22O0KDpVT44W2
9r09CCLx2gtAPwZUrvLlVrY0Mf7FAHzP11ExesPOOkkC8qHP6BfwdGoN5F9hvRVj3oa4FP0kePh1
CuG+cy91CY1XPQLmco84lpZm1hAwp6wLOe1BgRRTyY7/UiEd9FeZ65hh3NYDy2b1Bk0hAjPdcB46
8DOsRlIMkShMvI5Yo36URkIrlEBuY7cR6Y3mWm93t2mtPICzp4ue2igN59OQAOUKqYRTzy7qJ148
R0tlblthm8Bps0AMtOQzJ3Sxhjpybe4b3soaWBrd2hEXT5y+SwuczNwhay7SdLEpRiK8xpbfJb9Z
N1zT3OowhET+sAB5vas93XnqDP8woF8ZEzdE2TlpQe+WtiVukAR5dxQIuifpLno31132e0TjynB6
MBBIiqRq2uCPoc63Mocyd5kXOJeb+p8+F65RnrjVuJubteMO1QD0JyPzDeC4qroht3xrsuZMvZfW
UTQBaA/WF46FbAfioqqWX+guiCPw/gjs/TGkQQMPabbgM02vsKmi3znXhhJlgut5rywwPEVVQhnW
hHe2Qkt1+VPEHlzv1tz6wxsOZmy8lx9MvvQ/SKfQxLLC3PK5ciiJUtQ0n836ulrVEbQd+a7MnyLR
AW5GrFCgdXF+XgGx9Y48ZBDLfceECIWs3e1bIuEZUkkNLaP6Ac3KZfd5roBWfcyhKMmHYUd9jIU4
g8/WSpetXwFhamJ9IrNv3N0MUOe+izHlV99bW082WigG3GBQ8vk2mxUJ/46cJeqcHyRQAcup90ra
ETgnWtDs2PivxbX9Dd6hmHdJsfLoYEDhARTgd3XSX8foz8D9dUa6E7kW/LeDHNGyTGcpEFjzmrEL
jWmyrI+9Ecc7ORNbWVVQECKbcgJ/7TL/5LmZcTRxXabuqsz4Ntj8dceOn6pmM0oQP8mqT0BOGAFj
t4PGV+0lcOTM423pvhOA080nGFn2/9s5/L0GgTf4aINbQDAVmNwljuzRWL9ScbqRp63WmI6+meP3
1EUl+r9FjmgRNYbizzBhSQc503uFUyRpqECIFC6lruKydRMcR5VsWhQv4bsZuD8gU3aqmcK8/eyV
pKI8W6qRCIClfJlvvMJmuvMJ2x3rQ+7MxkZWgRbndtJOG4D4kU0oz0RxPYPGxDd9ZKcW+yaSMY2U
u9grTvwAYogjGUZAKOf+9o8xEq5jRhREUkLEwT2+Lm3sGK/fTUbY9STDzbLvOjyM0ceejHOH3ok5
7lMkhP2TE/5yTqfXURWZMCHkqPgRtEPUDnBHXegLzUzfFzi9Ffez6lh78nRBZAvEmQ4fjtF0yJUS
Iy/hKwgle9DukMuUSMwqQ4EBen9SOP65epRbi/Qr09/o9E29qZxLUw/4z2yJ5nGf/6HBRaYMguJZ
VILBVoFfRv3SpqiWVCYM87Dm69KiFMNO46vhEwD0vZk0leZ7YjOzSFno0780TtxgLeFtDxCwS5dq
M+QhGErXq1UrPQEMPklUBncb91/1mJfwkThIqDPk4CdHtcjR4cce8YdusQCQK5bz1nEUqcqR/NBs
TaUl5fOhk2tMYrkPRtp4ur6JtWVyHUP+Cwh6hTs+7gjVWEP8SccPevdexZzvRPJw2x9aA9QNe66q
NVHN05+jIXfru/Kml1y8lZsAMVoTxE1Xaeo919ZkexRj0x+SwCgx/3kcms4nqwFTuZklFdhcjtIF
fu5SFGB4+xEELQewVVJTB6qiRQIOOOs8wVqgF6eI034HxXrtg/rIDO/dQMYsgTI/lzdwhjN7L1Fi
8+ooR9+gAb4xxk+iq4QhIFhyjuFG7aJBF3bJK76ua4pgA42AUF92AvBQ+dh3tUV/AmxZt1TYjKsk
BubXVtB6uuoUFeYaHg/I4IQQuj+tG9rr39A23ujbpAUHc/g2eUTSNGD6+9BG38v6MkGbkCa04C8s
sL/qIPcWtSoy6H0ljMM/3QPfmM/jfr963SgXlBav4x/4tRv9/TUCqnMV1nMJSycEZ/958sCEUO9L
ghyDPV+/XoWzW36Efyw25uQm6lZQue9VNMxCIgWNGSjAiToGr99xx7SqK5Cnq40XJJMxhytovpTo
EJXa/nZuuEMWa5Wm5Qz3+8HI+AlJ4b0EXfevKcE+Lq1WWyzeCLfmM6cKlRV5xbsEunA7GrZePSw2
/nnMCSfOSSUNi92SwKbeMQqAPiu0yQLK4kErNsrCwHCDyD9KmoGNKyuW5+dazk+VKS0I9kcoLBKr
JpC4oHuoobntoHinmBl0MRqfRJdBMRSKgWqgoixSuIQC+xKKlIH2UDnQffd2quraehSPfZK09RP0
DhtMIY7E8JtIVEQr/Y7qjjLZuYdaesB1WV2mF4SqSinJ4IogKqgHynQ08JSPQVlkHjceaZm6CKZ+
Utt9EufAsXpOLJQpoBSGlW7IW9/NrbzH/tfRil/LgyMkPEr0Rc1eiI3IBx7n1nReDdjWJI1InvW+
qqsmSelXVNoSjnHoVMWnakDimeOOLb2WDR9vYKDxACnRWRVJSodsYXwwr/1C+eU6tKNDT2MBQAKF
z4r1Ine9yJhLzaSXt8t+NDkT6tEwHOfoDCQP4oH147BABdGniHut/C5nGKLwHEDTYmAd+zJQksIB
8SjhOitfqNJ7EQh+jIQ6qFwktobUoxY68LpiEsf95dk7SdDQvTT1G23iMKN8MmycZ1weViE/tbZt
+aJRYF/J43nt5We9Wg3aRUY6faHvf/GPX4mG6Y6T6csW67wNYXuDfcmbhWPLkq+I+iUkHUhqaM/z
8JLSbc7QE0URhyyU700jliSaz0paSRbRVtlOYT0TEFk0VI6zPcSRq5Wqi1tlVrknH7KWRKQFRMv6
ifSb3F6XUEvmaRXHM5xTVVNPTmiJdeQ85NywrlLeOdoVqE3B88fz6PymBcguwfst/3b3w/aQgjrr
IrELG2blpEnJyOKhCdwTO2hqQs80WoSQX5GgfWk37/Eljv4L4+TfXLdkOtJBGQwRAAjiahfuHEDu
lP+dAl5bqEQVD0x2B6RXQkELhIltS3+UGxbK+P/Yd9IVLNxqlN6aU6Sk45/6vUjHy5fh6vokxsoY
6iwKPY92paO6Ctrbrdxl4ji/4wj2UN9h7x+6Gbj60ehjD5zJExUiTX2LSXU1pVXWCzEiMmv7bXKS
bjpLz0UkIdrkgxMRZt1WulDNVuvQFOLq1slVDjG0kX+CFw4yzVEZtpr7P/1QaET6qO4hkx3HKo5r
dW2jbEg4b0PfIecdz5yXgzL5R3g1uhaygBuPC1Cas7s8LGmxuVKj1zX28aAm1Cev90xP3oUviMNr
GvHVwYGwRnfCtp9Y9yl8LpE2QE9GBJnG6c4YBn8D27xD4bI4MgEjNWbOI4ZKJ8DukIA7drzFmdbG
F5c2sF7h8yKk0MXOt1hxjUDzMWl6t0fqq5rnZ49aBxhtpg3bgJxEHDApBdqMK1+YIvzAnmxnxB3T
H0qdtD/0dymL9FFC4AGKYp6IxWtA/ReLechEbhHS1CzzEUqS41p7NHBgcC5gB8IFRJkJJmY8uWTZ
0SeEB39H/+jx30MmfcSrAmQJerwjzQZl9zdWd0g2iJBxqTOU2Br6XpItxcdZWhEsZRcCxDacwPdy
0H7MsOH2w7inGO+kwh33xbYn36B4Ac0g+FN22CkPgx1BBJNYgOvQFPHYbaRic1VGdhigy/xscz+y
C/Amu6oXbQpt2jiLe6zV5tsFaW3xlIImuFnxzV6bOv23ujdn6DhxIahZaxZ/SqfO9PLacBEHFR3b
4tRr/j3QiFL3VLgNR+8t1bTIquaeOSY0xun8TB60i032tiFqnicHsUjkdw9dN8tH9ES19Juk/G/6
I9VD57srEeVSsjZAgOgcNfBkqOfABr/L5iKTGy6dv6bzt7wjF6QlMj44qBAx5WUUXYdlPvS4CqnR
lNNUZ7ZbT8kccT/5zoGBGokPT40SPtjSsGUK51DnCSO6/NziibhDNKEt2Ic83wQ3aGCb1ElUri55
CwKLjOIUqhwwhkcuGlWgrf100dWzN77xgbbNbUTnOEctWIVBpZ7ZvCHjk2/yqA0t/5pCE/ISKOve
NXHEndjq/9Dsh0kuCjKrUpWoQXYtiRtQiPT2E3vIra+M38ivRNvmlcQbOETYbkYrkscCjdNBgzZQ
83B3IP14u7CswE2qaV56teQLGMxlS5vyDph26QaXjWPND0qACwJf0DhM5onbGTCgX5nP2S0oRP4U
X14DK+TMgXppipg9T0kVe/7MwRX2XMoeienfXsApNuRrBsJ2WbEiEVPyKPvUC7yoxG39BvTNYhEp
7G4N++oWICNuOMK+t3rLLH/vnCERxviZOLj855eFB1WFyHb9DmaaOrkg4tNDFv7MducCCmVUiN4G
le9ArVex08zfK21xhmkOJAzn7oeYauLFSmqfRTsbv5aEGwxh9Ylt5W/4n0tGmlZXlZRoUN2vC+iv
+SQzSgqV7rSxmb1/8GJTZ59Y7c2gtBsTnB8Rl9Xub51TQGlKKB/0BgvniylfLvE5pNSsEGeHts0C
oRCBdO3mLv2EYvR3SFovdWKFyXV36IKQlm5Bc4jRtsvQ4Ynbp5tjx7osLCdyyE58ikXIjyElvNHE
efZB/ErmhWsBQieCORrfMNzB47E8JzeDPF/Y1QMKpLsIM/1ZOu2XYmTGHPibp9lbKIfeBOu5XXIA
Ow2Iu4DOQ0OEeh5YHwq7RrGbxcEFORqZ1tlE9dyofYKtBw3WKxWYKFnIdURG8unaAjB9Up85V1JS
pWc35yBoaIMgcapVCnRyVRPK4gDjpzymvN/0aH6G7j8gQjDFP//nTon41As4XghciavZ/0tg8cUc
asTL6TIE+Y1Wd8Uw3mFAN6+5TRYzXqCnew4jTtEy8DTZruPKXh10RrZ4FzNOxYCnXnX59g/v4cyJ
8zFfazT+e6h19eTeGRVtzZodWXDEu0jUgY/EmwU5uw0lZVK+FeMG4cjDYt0/Y6mCav/t3Tiokogr
zNGBP55Y+rKpcVXk5OwVYRC6gnPA7wpBNm5arQCths/ZOHgYiEJ7q4esgvTxOb++q/U1Oljq+L55
kSqNjI2EIMYjvsYphnWb0Aa7MfLduO5prbW7Ylk/3ebK3Pk86MLhik6ti49CepclSZ3zUdys/uic
K33A9YK8Yg4ZLk7jdDYOw2yW/ytiZPHxJYxoH6w7Q31NThZS5gDSMQoNd9GNOVVBynooxXf3N6zp
DLS+nHwoWAMqbnf996K3ohBEvqo9BUtDWWKAUfOytR0vh/GCBXrBwasILtFL1SvK2bhLxITcr0VV
MNsRGL8NXip6CR1UhMpHZSucdh2tJTL+z+1hOlx42FvaJVKZjCoxFnzE1fpZBxC9DiWSoq3v8k0c
yDaTbM84pQEwg7/pbbdFqkxDQvgVNPdNc3NHnLfnvieNqMHncKoqsZUhRdFJRxDLxyhD1+zLrcgB
9LgM6z/oDJ5AEW8Mwulow9mq8N8PAxMhGB9gLE3iuSpLSfBLBxo/y7meCLMlItJf7lmw3ZHmvQD4
4vkKTpe5o1jdvboJY+g5cT39pAsxJfJMVa66d93TspRBuw+vlPapDy5xFHoyZhYK3eqOMBbRtslH
r+fIXpofNeqIX9VvSt9An9a8e4ow9txfHPMdMHKLFIDgBlsmyIpKBO+59Gy/2YAvXzqX9m/DILsx
QIxVC0sDDL/mICxAtvvs5YNHy0j77QHM0h5Zst7h8gljqTeXGs9pG20gASuKXnM7wtlEPvh4TJH3
3rNc9F2ECvGE1NikBspItNgaF5p5TG4uLPgvBoxOy3mDpuyeJyf1pUPYCdBpDcZU1k95I2xoWhac
caJgezv0IkER0q8QGN4qXLW2/1ww5vcX6mckdT2YZbcSJ1G2wdvo3kmyt/9gVk32MK2e3F1zabCG
g1QYpx5+JFrh0jXhyx5PR2vmuftQtQ4Lzh9N719/CwqyuCWTDILLWPdCqH9m1vvTWZ7RxT4hkxfQ
3cipcFTs/0o1caq8JliM1WUiW7y5TRdt3bA++A1Y7xI93qR8nSciGjd/qc1X0oWeLEv9yUPuIQZG
WvUX9cAt2ciQzDScP33gPmYMaHRASOxyd+czKac6df7F5xhQmFP0CENxtIw0UWaiiFV9NCvYuXW8
YPi04RL/kjZ71prR24vBZlxQFYT0EFUmLsxdRkPw8Iu0T7IJ+1gLTTk3HOC0oQ2CICDmCp7fGx44
Snbd3fuYzJbuSPbxFj+F2sAjvxhjhiUgf0gSOrXy+XPsYfivfu3tSAvjTI9RcSUadzIeqBus4I5g
g34cGZHmehsqRN8CabMkva6ct2Jksn0nJU4IAE14GrgOwaxbNm38mYatsW5XKfT3XZiVuVC8JeSD
dbydW8lZvhbyZbC0BxGkxuaNNe2NKSQyG/hNnJwPDTgN96msSAVxvELQD3hEJRn3pvC+lZf8xBVd
jRJNIZpfAWnxAy4HzdEKNB1A2OJ9vshFFNOZUTzDNd7K9me6a4JmAR5ZEupJeQGlHbvcFsA38gcn
MDoSFptbsziCJj2VLvYK4FshsIotf2tKZHpIbvQES6/FL6q4YGvhXRzasMOWdr3hQyBm3VIqGMgr
cXfZaQpNNR4cVap6+tCFmI6POYjnlZ8W/yFwAlC69FjYD4nDQLaJ3OEXDnvdAIIh0Sa/fpYDNlYg
KIhWPkmv4wCUInMudFlAoYBfW5cdhQr7DlUuIVgDY3onBngHgYx9nkC31SP4FFCNzg1xfA2L6eYQ
yz+upGbjD50yPC0WkLDIuVozzpnUNcVatrOGBqpxqBQ/VX2JhW2aqsXYUVMQGdX9i+qCukz0fwi7
V/BNpsXqOce+rvIgUHHXes2lQ+CKD/Fc3giP0eEm53fVd3xKh41Yr7F01JGz7X/g+SBge9weqN+g
TiZ4bzJjRlffyL5b9uXgl3p+LyjAdGoq3q2sPSRIMmbIpaXNr77jczGl9c0F+kHxIRf2jpAOv0Fs
M7SeCGajlgrW2P5LjI0Cq8y8TlDEVVKl1IH6o9YDWq2kxJrqNN90qxlFyslRJ4be5I28C4Q4ExhG
c1BWpH4Zc903QQNwPePZJxiGRODHxzMwD4pgTWdgSl4JbfU4IQVkBuJGrYZdeoHn9i+Fa/Na0vfk
AGFBHWAbD3jd6xULjJoYmDzZGAi7fDdH2+Axy7PrFdEc2I4qG7JCCDB+oL5T0J4XEOyh+zya8Y0J
V67lGhWsZ3iRW5i1xUSXBxglL2vyGnZxFZi1JcB8rIF1/h0iJxyKIzw0un8go2WiWytFJLrSxiX0
9nxep/pydlt1tU0M7pPkq8LXMwQaZvzMR1ScxvFUUfKl6HeyBfAnoCNqISm/U4Gi4Ah5dVZRPzxw
6ZliHH3ABEyACwM7iqIPvseqMCLIlksx8fzCdeaYgT/M+E4HNYFMYAYakFVtJScIpmeX+7N269ek
nelK6gJEtjbFxccEA60FmGJvXj+Q8KTjTjhCWbey/FgJxWB1hO4c1vC0rUifebv7wfOaHkbHUi0/
qwjAglHkaMb7r173KStE5DYWJT0CvxRNThbv4v+yyMHnhAQtnKkolbtYrUmOVa2vdGG932BZX16y
P3tOZ5M5A9ozdjajtYI20qMNphnd7+pcQmc5YY2loWvo2qYfv+KR5akWqENB/IiIxihFtd2rYn9W
AvRf2BgVJqthLmSY3P8loPw8e7h2j3IgWbmERJ3U8/qxQTIVFMtvO53cTDWn7zHKDzmbvcEaaTl6
pbncGG7+0/vU7NAVZJInwXH/WrBUxDkMMEXBnG6lpp6RFp25653fs9z82LhvGxu1Xt96TH7Jdtpy
JOCNltzIJH3pmtz/b9+9OErtQ1NFLF1kyL8Q46yoK1KLwuPDdLsSeZ0GN0Uv+RgsOiHBsAOFJAXc
0gbnLzQXaFPL/Gn0eilCICBozSu83PaiWD7sgezAyKRmZhASDB9OLb58x6GjPghiNLHDc4wuCiRn
uALuGLo5YW3LF6rPIKH48WmIAOVzhNwaEpULnuA9hDAknH2GjRzbRMTjrb73vKc6CdIrxtBG8WR1
crqyUPUuHYlLGGxbGnoRoPvO9VbTiMhFQTNndx14HdmP2g1Iuy2ZYI1pylLkwObhITbHqZ+T3YLo
EdTwBweSC6fT8PR706vMi+CLs2Za3yvEJYU4VaNBFXNHoNX6GU87hbecgA1xr/Mp84/mZDVGBojA
IeDapGrKJli9KHAl/l5C0izGj8KlVGZbR2XEpTd9ooePkzHzphK3EPAFgk/Cyh4nv2grTmqDAUgk
GWzkTqIyp88J9WDqwWCX6JjQ3zFzpvIZAjoLTsOrftBeOSYuCpLBBFd53iPsNzL2GnKhfVSOpl+Z
FJNdFm9VJFz6Xx7Ty+6MQVRIw8eYKm2UkClnJwen8hVbCzmun94G+aBgjVM4+2t39T7zvAx5Xl3S
l3OW/kWgS21X7pJSw9lobk/Cmm023ndfPXTgkf8JrLs2t+HY09qIMftKsJgfMGNRHjBI5+Z8U9sO
zRJbrbGHqkvc7dMYP9MmW2IyBWSfaqXPLL6c9MICntnEHuLv5Yyn+8NY31BIOHLEDqi5/1nts6Q2
8GyuayEB8SfrEwn/fiMP+M1Bw3LYWR5/QBASQZ9mXTGjwR6KxUbe0UeXp7E5xU2WW78hwOt2zpZB
teFwI2Okk0YTaKqMvhVadhBTWavkTRLv9127xbnp12f3dL1WWqF9elUeba4zn59DYf+kBE7+jKp4
8KTVx3viHewDxUQ47UEixnYky56RpFqUzJxle7W1QXNEdx15QtvXv35TANf74mycfzEvALMJXPR0
Ej3q3FwBxfYBmRp2tIxZ79kiKZSj0Y3Zobmyyw3uX7G/XY7PyjPwGOTyMRFY+O9ueFD9c+7SDU3g
H4nm8n03+dkUGY4S0GyXp9oM/+nawUMiqXTzR4A9zDP70j80K/sMyWQPIHkvsBDb4yJXkW3PsXN2
y8q8D0n51NSDlfBxMxcInWkN0KaiQoYAszCczsWshSY106/LVOYepGKjiRbge9NCl845YfJ0MU9U
8eOvkGLZkeDfLYhhqAJJu/VeWpHRqT05FBxSXeG4uZMq33NxkcTRpqL4vNEPsgmOPS/onpfobW8D
3FVdkRxl1tf8HQcUQVXb85PIJhZP0agP7KiYRowk1P+ZKwE5IlRWTJJXEYecC3G6w96oj5imRpdK
AnyY86a+tt6Y1zMH5lNhdo8HmZSIBNwOqLLo6390bGmv8XZ8BmK6V2+xkWYuFAB/WGkm4WUt0+1E
pkFrYNuq1ukNMu86vCKh4CvPf20gWbETv8qAPsAfr2zYep5ofHOkGLssFT9oqrByK9+SEqYMmfXX
1lUGn/hLPKF28iW3E2eeb9ludhCqZYy0GT0NHbASqdcXr79XQh9O6CfwddYO+tO9DxADrD4L4eUM
+hdpWheN4w3DaqPfa27hWN5Tv9Fdz1Vu3Qj4y+xbYGDOTKMASDJ/y7f4Rp66RxE5aE3IvnLez0gy
PzmyK720wkw2kb/j7eRqV3TNmkgiI7oJoI7RmmVKze8CzZKhwUWJJpEu8DDLXCkIuaiim8tW1J1i
AZ/F8oTWp7HK92Y7EZfgewD+kxF1Rsokk7laRlzXMLhPWo2Xwj+C+72h0D49K+wqy5oMr7CteBcL
/WDqx+qdBvBptMUmWCQvcKhrhbsQXT/YlrQDDTJTxMNDKAlGzqRvhqBtbuoteudOX7jcwBl8YlU4
582fY/VZLn4e0xCYAVIlrIYE/0JZKGFjBk9qxxFqK2hQzzgntLAIrzArtDsz2pm90Gkvjiigw/9k
XNWaAn/FV1DSliZYYY6Z0XKA6+Blcryc26tEgUyMRycsHLQQ0OLjMOMc09/wl1F1Pujgc+pytFuC
y6kZFndYRylegwGI9MUpK39IAtkyUxcHTzv8GDfb3+yXCNLu39+DQxr8MR5ERCNYcRm7XxizZRym
VGuPoAX+nwzHR9/E3l5mcDT99fnWwMCL8wuT1ZORuCvG+LmMsEdaAiMujQQDQdCp9RSIT2V+nEoI
JjH/l3p7Xw==
`protect end_protected
| bsd-2-clause | 86f0ecb0607938e18fc7e416ac1f134f | 0.937173 | 1.862845 | false | false | false | false |
Logistic1994/CPU | module_SP.vhd | 1 | 2,081 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:44:13 05/29/2015
-- Design Name:
-- Module Name: module_sp - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity module_SP is
port(
clk_SP: in std_logic;
nreset: in std_logic;
SP_CS: in std_logic; --Ƭѡ
SP_UP: in std_logic; -- +1£¬¼´³öÕ»
SP_DN: in std_logic; -- -1£¬¼´ÈëÕ»
nSP_EN: in std_logic; --µ±Õâ¸öΪ0ʱ£¬upÓëdownÓÐЧ£»µ±Õâ¸öΪ1ʱ±íʾÐèÒª¸üÐÂSPÁË
ARo: out std_logic_vector(6 downto 0);
ao: out std_logic;
datai: in std_logic_vector(7 downto 0));
end module_SP;
architecture Behavioral of module_SP is
signal SP: std_logic_vector(6 downto 0);
begin
process(clk_SP, nreset)
begin
if nreset = '0' then
SP <= (others => '1'); -- ³õʼʱspÓ¦¸ÃÔÚ7F´¦£¬¼´×îµ×ÏÂ
elsif rising_edge(clk_SP) then
if SP_CS = '1' then
if nSP_EN = '1' then -- ¸üÐÂSP
SP <= datai(6 downto 0);
ARo <= (others => 'Z');
ao <= '0';
else
if SP_UP = '1' then -- ÉÏÉý
ARo <= SP; -- ÕâÑùÊǶԵÄ
ao <= '1';
SP <= std_logic_vector(unsigned(SP) - 1);
elsif SP_DN = '1' then -- Ͻµ
ARo <= std_logic_vector(unsigned(SP) + 1); -- ÕâÑùÊǶԵÄ
ao <= '1';
SP <= std_logic_vector(unsigned(SP) + 1);
else
ARo <= (others => 'Z');
ao <= '0';
end if;
end if;
else
ARo <= (others => 'Z');
ao <= '0';
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | f658aaf92f5620f3d17a5376ddee90f9 | 0.550697 | 2.745383 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/case/rule_016_test_input.fixed_upper.vhd | 1 | 589 |
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
case boolean_1 is
WHEN STATE_1 =>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_1;
PROC_2 : process (a, b, c) is
begin
case boolean_1 is
WHEN STATE_1=>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_2;
PROC_3 : process (a, b, c) is
begin
case boolean_1 is
WHEN STATE_1=>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_3;
end architecture ARCH;
| gpl-3.0 | b54c759990a6803d17007f3e3ff34568 | 0.4618 | 3.308989 | false | false | false | false |
Yarr/Yarr-fw | rtl/kintex7/wbexp-core/wbexp_core_pkg.vhd | 1 | 26,003 | ----------------------------------------------------------------------------------
-- Company: LBNL
-- Engineer: Arnaud Sautaux
--
-- Create Date: 07/27/2017 10:50:41 AM
-- Design Name: Wishbone express core
-- Module Name: wshexp_core - Behavioral
-- Project Name: YARR
-- Target Devices:
-- Tool Versions: Vivado v2016.2 (64 bit)
-- Description:
-- Wishbone express package
-- Dependencies:
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--==============================================================================
--! Package declaration
--==============================================================================
package wshexp_core_pkg is
--==============================================================================
--! Constants declaration
--==============================================================================
constant c_RST_ACTIVE : std_logic := '0'; -- Active low reset
--==============================================================================
--! Functions declaration
--==============================================================================
function f_byte_swap_64 (
constant enable : boolean;
signal din : std_logic_vector(63 downto 0);
signal byte_swap : std_logic_vector(2 downto 0))
return std_logic_vector;
function f_byte_swap (
constant enable : boolean;
signal din : std_logic_vector(31 downto 0);
signal byte_swap : std_logic_vector(1 downto 0))
return std_logic_vector;
function log2_ceil(N : natural) return positive;
--==============================================================================
--! Components declaration
--==============================================================================
Component p2l_decoder is
Port (
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
-- From Slave AXI-Stream
s_axis_rx_tdata_i : in STD_LOGIC_VECTOR (64 - 1 downto 0);
s_axis_rx_tkeep_i : in STD_LOGIC_VECTOR (64/8 - 1 downto 0);
s_axis_rx_tuser_i : in STD_LOGIC_VECTOR (21 downto 0);
s_axis_rx_tlast_i : in STD_LOGIC;
s_axis_rx_tvalid_i : in STD_LOGIC;
s_axis_rx_tready_o : out STD_LOGIC;
-- To the wishbone master
pd_wbm_address_o : out STD_LOGIC_VECTOR(63 downto 0);
pd_wbm_data_o : out STD_LOGIC_VECTOR(31 downto 0);
pd_wbm_valid_o : out std_logic;
pd_wbm_hdr_rid_o : out std_logic_vector(15 downto 0); -- Requester ID
pd_wbm_hdr_tag_o : out std_logic_vector(7 downto 0);
pd_wbm_target_mrd_o : out std_logic; -- Target memory read
pd_wbm_target_mwr_o : out std_logic; -- Target memory write
wbm_pd_ready_i : in std_logic;
-- to L2P DMA
pd_pdm_data_valid_o : out std_logic; -- Indicates Data is valid
pd_pdm_data_valid_w_o : out std_logic_vector(1 downto 0);
pd_pdm_data_last_o : out std_logic; -- Indicates end of the packet
pd_pdm_keep_o : out std_logic_vector(7 downto 0);
pd_pdm_data_o : out std_logic_vector(63 downto 0); -- Data
--debug outputs
states_do : out STD_LOGIC_VECTOR(3 downto 0);
pd_op_o : out STD_LOGIC_VECTOR(2 downto 0);
pd_header_type_o : out STD_LOGIC;
pd_payload_length_o : out STD_LOGIC_VECTOR(9 downto 0)
);
end component;
component wbmaster32 is
generic (
g_ACK_TIMEOUT : positive := 100 -- Wishbone ACK timeout (in wb_clk cycles)
);
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- From P2L packet decoder
--
-- Header
pd_wbm_hdr_start_i : in std_logic; -- Header strobe
--pd_wbm_hdr_length_i : in std_logic_vector(9 downto 0); -- Packet length in 32-bit words multiples
pd_wbm_hdr_rid_i : in std_logic_vector(15 downto 0); -- Requester ID
pd_wbm_hdr_cid_i : in std_logic_vector(15 downto 0); -- Completer ID
pd_wbm_hdr_tag_i : in std_logic_vector(7 downto 0); -- Completion ID
pd_wbm_target_mrd_i : in std_logic; -- Target memory read
pd_wbm_target_mwr_i : in std_logic; -- Target memory write
--
-- Address
pd_wbm_addr_start_i : in std_logic; -- Address strobe
pd_wbm_addr_i : in std_logic_vector(31 downto 0); -- Target address (in byte) that will increment with data
-- increment = 4 bytes
--
-- Data
pd_wbm_data_valid_i : in std_logic; -- Indicates Data is valid
--pd_wbm_data_last_i : in std_logic; -- Indicates end of the packet
pd_wbm_data_i : in std_logic_vector(31 downto 0); -- Data
--pd_wbm_be_i : in std_logic_vector(3 downto 0); -- Byte Enable for data
---------------------------------------------------------
-- P2L channel control
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- Ready to accept target write
p2l_rdy_o : out std_logic; -- De-asserted to pause transfer already in progress
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- Asserted when GN4124 ready to accept read completion with data
---------------------------------------------------------
-- To the arbiter (L2P data)
wbm_arb_tdata_o : out STD_LOGIC_VECTOR (64 - 1 downto 0);
wbm_arb_tkeep_o : out STD_LOGIC_VECTOR (64/8 - 1 downto 0);
--wbm_arb_tuser_o : out STD_LOGIC_VECTOR (3 downto 0);
wbm_arb_tlast_o : out STD_LOGIC;
wbm_arb_tvalid_o : out STD_LOGIC;
wbm_arb_tready_i : in STD_LOGIC;
wbm_arb_req_o : out std_logic;
---------------------------------------------------------
-- CSR wishbone interface
wb_clk_i : in std_logic; -- Wishbone bus clock
wb_adr_o : out std_logic_vector(30 downto 0); -- Address
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic; -- Strobe
wb_we_o : out std_logic; -- Write
wb_cyc_o : out std_logic; -- Cycle
wb_dat_i : in std_logic_vector(31 downto 0); -- Data in
wb_ack_i : in std_logic; -- Acknowledge
wb_stall_i : in std_logic; -- Stall
wb_err_i : in std_logic; -- Error
wb_rty_i : in std_logic; -- Retry
wb_int_i : in std_logic -- Interrupt
);
end component;
component dma_controller is
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- Interrupt request
dma_ctrl_irq_o : out std_logic_vector(1 downto 0);
---------------------------------------------------------
-- To the L2P DMA master and P2L DMA master
dma_ctrl_carrier_addr_o : out std_logic_vector(31 downto 0);
dma_ctrl_host_addr_h_o : out std_logic_vector(31 downto 0);
dma_ctrl_host_addr_l_o : out std_logic_vector(31 downto 0);
dma_ctrl_len_o : out std_logic_vector(31 downto 0);
dma_ctrl_start_l2p_o : out std_logic; -- To the L2P DMA master
dma_ctrl_start_p2l_o : out std_logic; -- To the P2L DMA master
dma_ctrl_start_next_o : out std_logic; -- To the P2L DMA master
dma_ctrl_byte_swap_o : out std_logic_vector(1 downto 0);
dma_ctrl_abort_o : out std_logic;
dma_ctrl_done_i : in std_logic;
dma_ctrl_error_i : in std_logic;
---------------------------------------------------------
-- From P2L DMA master
next_item_carrier_addr_i : in std_logic_vector(31 downto 0);
next_item_host_addr_h_i : in std_logic_vector(31 downto 0);
next_item_host_addr_l_i : in std_logic_vector(31 downto 0);
next_item_len_i : in std_logic_vector(31 downto 0);
next_item_next_l_i : in std_logic_vector(31 downto 0);
next_item_next_h_i : in std_logic_vector(31 downto 0);
next_item_attrib_i : in std_logic_vector(31 downto 0);
next_item_valid_i : in std_logic;
---------------------------------------------------------
-- Wishbone slave interface
wb_clk_i : in std_logic; -- Bus clock
wb_adr_i : in std_logic_vector(3 downto 0); -- Adress
wb_dat_o : out std_logic_vector(31 downto 0); -- Data in
wb_dat_i : in std_logic_vector(31 downto 0); -- Data out
wb_sel_i : in std_logic_vector(3 downto 0); -- Byte select
wb_cyc_i : in std_logic; -- Read or write cycle
wb_stb_i : in std_logic; -- Read or write strobe
wb_we_i : in std_logic; -- Write
wb_ack_o : out std_logic; -- Acknowledge
---------------------------------------------------------
-- debug outputs
dma_ctrl_current_state_do : out std_logic_vector (2 downto 0);
dma_ctrl_do : out std_logic_vector(31 downto 0);
dma_stat_do : out std_logic_vector(31 downto 0);
dma_attrib_do : out std_logic_vector(31 downto 0)
);
end component;
component p2l_dma_master is
generic (
-- Enable byte swap module (if false, no swap)
g_BYTE_SWAP : boolean := false
);
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- From PCIe IP core
l2p_rid_i : in std_logic_vector(16-1 downto 0);
---------------------------------------------------------
-- From the DMA controller
dma_ctrl_carrier_addr_i : in std_logic_vector(31 downto 0);
dma_ctrl_host_addr_h_i : in std_logic_vector(31 downto 0);
dma_ctrl_host_addr_l_i : in std_logic_vector(31 downto 0);
dma_ctrl_len_i : in std_logic_vector(31 downto 0);
dma_ctrl_start_p2l_i : in std_logic;
dma_ctrl_start_next_i : in std_logic;
dma_ctrl_done_o : out std_logic;
dma_ctrl_error_o : out std_logic;
dma_ctrl_byte_swap_i : in std_logic_vector(2 downto 0);
dma_ctrl_abort_i : in std_logic;
---------------------------------------------------------
-- From P2L Decoder (receive the read completion)
--
-- Header
pd_pdm_master_cpld_i : in std_logic; -- Master read completion with data
pd_pdm_master_cpln_i : in std_logic; -- Master read completion without data
--
-- Data
pd_pdm_data_valid_i : in std_logic; -- Indicates Data is valid
pd_pdm_data_valid_w_i: in std_logic_vector(1 downto 0);
pd_pdm_data_last_i : in std_logic; -- Indicates end of the packet
pd_pdm_data_i : in std_logic_vector(63 downto 0); -- Data
pd_pdm_be_i : in std_logic_vector(7 downto 0); -- Byte Enable for data
---------------------------------------------------------
-- P2L control
p2l_rdy_o : out std_logic; -- De-asserted to pause transfer already in progress
rx_error_o : out std_logic; -- Asserted when transfer is aborted
---------------------------------------------------------
-- To the P2L Interface (send the DMA Master Read request)
pdm_arb_tvalid_o : out std_logic; -- Read completion signals
pdm_arb_tlast_o : out std_logic; -- Toward the arbiter
pdm_arb_tdata_o : out std_logic_vector(63 downto 0);
pdm_arb_tkeep_o : out std_logic_vector(7 downto 0);
pdm_arb_req_o : out std_logic;
arb_pdm_gnt_i : in std_logic;
---------------------------------------------------------
-- DMA Interface (Pipelined Wishbone)
p2l_dma_clk_i : in std_logic; -- Bus clock
p2l_dma_adr_o : out std_logic_vector(31 downto 0); -- Adress
p2l_dma_dat_i : in std_logic_vector(63 downto 0); -- Data in
p2l_dma_dat_o : out std_logic_vector(63 downto 0); -- Data out
p2l_dma_sel_o : out std_logic_vector(7 downto 0); -- Byte select
p2l_dma_cyc_o : out std_logic; -- Read or write cycle
p2l_dma_stb_o : out std_logic; -- Read or write strobe
p2l_dma_we_o : out std_logic; -- Write
p2l_dma_ack_i : in std_logic; -- Acknowledge
p2l_dma_stall_i : in std_logic; -- for pipelined Wishbone
l2p_dma_cyc_i : in std_logic; -- L2P dma wb cycle (for bus arbitration)
---------------------------------------------------------
-- To the DMA controller
next_item_carrier_addr_o : out std_logic_vector(31 downto 0);
next_item_host_addr_h_o : out std_logic_vector(31 downto 0);
next_item_host_addr_l_o : out std_logic_vector(31 downto 0);
next_item_len_o : out std_logic_vector(31 downto 0);
next_item_next_l_o : out std_logic_vector(31 downto 0);
next_item_next_h_o : out std_logic_vector(31 downto 0);
next_item_attrib_o : out std_logic_vector(31 downto 0);
next_item_valid_o : out std_logic
);
end component;
component l2p_dma_master is
generic (
g_BYTE_SWAP : boolean := false;
axis_data_width_c : integer := 64;
wb_address_width_c : integer := 64;
wb_data_width_c : integer := 64
);
port (
-- GN4124 core clk and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- From PCIe IP core
l2p_rid_i : in std_logic_vector(16-1 downto 0);
-- From the DMA controller
dma_ctrl_target_addr_i : in std_logic_vector(32-1 downto 0);
dma_ctrl_host_addr_h_i : in std_logic_vector(32-1 downto 0);
dma_ctrl_host_addr_l_i : in std_logic_vector(32-1 downto 0);
dma_ctrl_len_i : in std_logic_vector(32-1 downto 0);
dma_ctrl_start_l2p_i : in std_logic;
dma_ctrl_done_o : out std_logic;
dma_ctrl_error_o : out std_logic;
dma_ctrl_byte_swap_i : in std_logic_vector(2 downto 0);
dma_ctrl_abort_i : in std_logic;
-- To the arbiter (L2P data)
ldm_arb_tvalid_o : out std_logic;
--ldm_arb_dframe_o : out std_logic;
ldm_arb_tlast_o : out std_logic;
ldm_arb_tdata_o : out std_logic_vector(axis_data_width_c-1 downto 0);
ldm_arb_tkeep_o : out std_logic_vector(axis_data_width_c/8-1 downto 0);
ldm_arb_tready_i : in std_logic;
ldm_arb_req_o : out std_logic;
arb_ldm_gnt_i : in std_logic;
-- L2P channel control
l2p_edb_o : out std_logic; -- Asserted when transfer is aborted
l2p_rdy_i : in std_logic; -- De-asserted to pause transdert already in progress
tx_error_i : in std_logic; -- Asserted when unexpected or malformed paket received
-- DMA Interface (Pipelined Wishbone)
l2p_dma_clk_i : in std_logic;
l2p_dma_adr_o : out std_logic_vector(wb_address_width_c-1 downto 0);
l2p_dma_dat_i : in std_logic_vector(wb_data_width_c-1 downto 0);
l2p_dma_dat_o : out std_logic_vector(wb_data_width_c-1 downto 0);
l2p_dma_sel_o : out std_logic_vector(3 downto 0);
l2p_dma_cyc_o : out std_logic;
l2p_dma_stb_o : out std_logic;
l2p_dma_we_o : out std_logic;
l2p_dma_ack_i : in std_logic;
l2p_dma_stall_i : in std_logic;
p2l_dma_cyc_i : in std_logic; -- P2L dma WB cycle for bus arbitration
--DMA Debug
l2p_current_state_do : out std_logic_vector (2 downto 0);
l2p_data_cnt_do : out unsigned(12 downto 0);
l2p_len_cnt_do : out unsigned(12 downto 0);
l2p_timeout_cnt_do : out unsigned(12 downto 0);
wb_timeout_cnt_do : out unsigned(12 downto 0);
-- Data FIFO
data_fifo_rd_do : out std_logic;
data_fifo_wr_do : out std_logic;
data_fifo_empty_do : out std_logic;
data_fifo_full_do : out std_logic;
data_fifo_dout_do : out std_logic_vector(axis_data_width_c-1 downto 0);
data_fifo_din_do : out std_logic_vector(axis_data_width_c-1 downto 0);
-- Addr FIFO
addr_fifo_rd_do : out std_logic;
addr_fifo_wr_do : out std_logic;
addr_fifo_empty_do : out std_logic;
addr_fifo_full_do : out std_logic;
addr_fifo_dout_do : out std_logic_vector(axis_data_width_c-1 downto 0);
addr_fifo_din_do : out std_logic_vector(axis_data_width_c-1 downto 0)
);
end component;
component l2p_arbiter is
generic(
axis_data_width_c : integer := 64
);
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- From Wishbone master (wbm) to arbiter (arb)
wbm_arb_tdata_i : in std_logic_vector (axis_data_width_c - 1 downto 0);
wbm_arb_tkeep_i : in std_logic_vector (axis_data_width_c/8 - 1 downto 0);
wbm_arb_tlast_i : in std_logic;
wbm_arb_tvalid_i : in std_logic;
wbm_arb_tready_o : out std_logic;
wbm_arb_req_i : in std_logic;
arb_wbm_gnt_o : out std_logic;
---------------------------------------------------------
-- From P2L DMA master (pdm) to arbiter (arb)
pdm_arb_tdata_i : in std_logic_vector (axis_data_width_c - 1 downto 0);
pdm_arb_tkeep_i : in std_logic_vector (axis_data_width_c/8 - 1 downto 0);
pdm_arb_tlast_i : in std_logic;
pdm_arb_tvalid_i : in std_logic;
pdm_arb_tready_o : out std_logic;
pdm_arb_req_i : in std_logic;
arb_pdm_gnt_o : out std_logic;
---------------------------------------------------------
-- From L2P DMA master (ldm) to arbiter (arb)
ldm_arb_tdata_i : in std_logic_vector (axis_data_width_c - 1 downto 0);
ldm_arb_tkeep_i : in std_logic_vector (axis_data_width_c/8 - 1 downto 0);
ldm_arb_tlast_i : in std_logic;
ldm_arb_tvalid_i : in std_logic;
ldm_arb_tready_o : out std_logic;
ldm_arb_req_i : in std_logic;
arb_ldm_gnt_o : out std_logic;
---------------------------------------------------------
-- From arbiter (arb) to pcie_tx (tx)
axis_tx_tdata_o : out STD_LOGIC_VECTOR (axis_data_width_c - 1 downto 0);
axis_tx_tkeep_o : out STD_LOGIC_VECTOR (axis_data_width_c/8 - 1 downto 0);
axis_tx_tuser_o : out STD_LOGIC_VECTOR (3 downto 0);
axis_tx_tlast_o : out STD_LOGIC;
axis_tx_tvalid_o : out STD_LOGIC;
axis_tx_tready_i : in STD_LOGIC;
---------------------------------------------------------
-- Debug
eop_do : out std_logic
);
end component;
COMPONENT ila_axis
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe6 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe10 : IN STD_LOGIC_VECTOR(21 DOWNTO 0);
probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe16 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe17 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe20 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe21 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
probe22 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe23 : IN STD_LOGIC_VECTOR(28 DOWNTO 0)
);
END COMPONENT ;
COMPONENT ila_wsh_pipe
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe14 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
probe15 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
probe16 : IN STD_LOGIC_VECTOR(36 DOWNTO 0);
probe17 : IN STD_LOGIC_VECTOR(28 DOWNTO 0)
);
END COMPONENT ;
-----------------------------------------------------------------------------
end wshexp_core_pkg;
package body wshexp_core_pkg is
-----------------------------------------------------------------------------
-- Byte swap function
--
-- enable | byte_swap | din | dout
-- false | XX | ABCD | ABCD
-- true | 00 | ABCD | ABCD
-- true | 01 | ABCD | BADC
-- true | 10 | ABCD | CDAB
-- true | 11 | ABCD | DCBA
-----------------------------------------------------------------------------
function f_byte_swap (
constant enable : boolean;
signal din : std_logic_vector(31 downto 0);
signal byte_swap : std_logic_vector(1 downto 0))
return std_logic_vector is
variable dout : std_logic_vector(31 downto 0) := din;
begin
if (enable = true) then
case byte_swap is
when "00" =>
dout := din;
when "01" =>
dout := din(23 downto 16)
& din(31 downto 24)
& din(7 downto 0)
& din(15 downto 8);
when "10" =>
dout := din(15 downto 0)
& din(31 downto 16);
when "11" =>
dout := din(7 downto 0)
& din(15 downto 8)
& din(23 downto 16)
& din(31 downto 24);
when others =>
dout := din;
end case;
else
dout := din;
end if;
return dout;
end function f_byte_swap;
-----------------------------------------------------------------------------
-- Byte swap function
--
-- enable | byte_swap | din | dout
-- false | XXX | ABCDEFGH | ABCDEFGH
-- true | 000 | ABCDEFGH | ABCDEFGH
-- true | 001 | ABCDEFGH | BADCFEHG
-- true | 010 | ABCDEFGH | CDABGHEF
-- true | 011 | ABCDEFGH | DCBAHGFE
-- true | 100 | ABCDEFGH | EFGHABCD
-- true | 101 | ABCDEFGH | FEHGBADC
-- true | 110 | ABCDEFGH | GHEFCDAB
-- true | 111 | ABCDEFGH | HGFEDCBA
-----------------------------------------------------------------------------
function f_byte_swap_64 (
constant enable : boolean;
signal din : std_logic_vector(63 downto 0);
signal byte_swap : std_logic_vector(2 downto 0))
return std_logic_vector is
variable dout : std_logic_vector(63 downto 0) := din;
begin
if (enable = true) then
if byte_swap(2) = '0' then
dout := f_byte_swap(true, din(63 downto 32), byte_swap(1 downto 0)) & f_byte_swap(true, din(31 downto 0), byte_swap(1 downto 0));
else
dout := f_byte_swap(true, din(31 downto 0), byte_swap(1 downto 0)) & f_byte_swap(true, din(63 downto 32), byte_swap(1 downto 0));
end if;
else
dout := din;
end if;
return dout;
end function f_byte_swap_64;
-----------------------------------------------------------------------------
-- Returns log of 2 of a natural number
-----------------------------------------------------------------------------
function log2_ceil(N : natural) return positive is
begin
if N <= 2 then
return 1;
elsif N mod 2 = 0 then
return 1 + log2_ceil(N/2);
else
return 1 + log2_ceil((N+1)/2);
end if;
end;
end wshexp_core_pkg;
| gpl-3.0 | 8b7d3fd43895143df5058b4fff73ec31 | 0.489444 | 3.644429 | false | false | false | false |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/fir_compiler_v7_1/hdl/cntrl_delay.vhd | 2 | 9,440 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Y92bo4b0+Y2GyuIWDNktz7LxGRzu9bzKVz9wLgYiqs5yBjawiPoSc68s+WHDuTwLhF8A1e0DvjMP
GfoawYu+xw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
it/0B1HgFEJ1pHo6/k3ZfTQbdwQKTdGcQ51QOwfqMlCIJu7K2y+tj57jEshniXexQmQel2fO1fRB
y+DUG66FF/GsN+NIf5J2ShQjyqkPfcEFjF2Fwej0LEkYcmtdsngu/ENnLMJhRUcARqw8LyvVCMGc
Mg9CQ5Qqf0LK9uDBoi8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QB+lQeDK8/VLQ/U3uZmQIk5R2GWBkQMkahXvP+DzqjcWcVZaf9cKdyzyRmGSqcOmAmfkpuvYsFaF
ycLHrm5+lCG9E2VhBTPZX5+1S7JYWEdluvqfZZ28Y/dcFnd9kKb4ycmWrhgg4bopu9kvOUzltS5F
+2W3F9bgT/tqpnH9pC0onUOhz5GcifFBDJls5MwToPN0AJuLBdPpxQPZ+R8PwDzZmbJM4E8BCPqG
l4tatSqHu/SG7hboAG/cQ0hPY4I31vWfj5HD4O2jUaJ4coD0u7aOishxPVkkMlbhRkAetJlbHJAl
CKuRLcVnFa+23vJYPRX2Ly+0fansukWKX0jwpg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
2nypbkcM487isI/ZQLiMjo3K8WIrTaKcGqffSF7xvJJknRTr+PXhCjp1L4y4daxM3SeopnIXNhJF
y7tP2+zP5KxtRwzRru37dnZCr+NAMCVOV4AFmkWdDK/LCDuyKnMVwaELWX/BQClPTHR3Gmi9GAWp
FN3yY5WC6cO6sNoj/jw=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Tt/Bp/zQrsZ6Z7aPbBb0mjZQd86q65t8saM6J5O/KyIDgPr9UfTyKcB8yBY6okpsShBsiB+pJALO
ASecPbbZe8hE09+ro+mcnp4oDsCXsNgHFkWeswPg1VrcAbHklAzjZ5EETk2axxK0OTaxwrcq0En3
PgXbf8Fmb/ehJTtniPisGrBB/hKZhYpLLpLAb5WSpBTSvrq1clo93q5Gn9/jfj+DNMNSbKG0a/px
HRxzrYg3cCvlmDYpUx0SMC5W/WuJwk+IAMQ1NYWwEJGve2ZLvfBPwOR75WBMd3nfK0y6lyniGZbp
BkJEXNuwa/Eq7WznwYteEeA3zao1dRBFOCQruQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5248)
`protect data_block
MPKSrJs2h5ivLkd2ZHn+vn3qjd+lFfB6v5+SO79hPwOSqXUjqjbwlE1WMk6NCPXWOUSehA4hSzop
OfGkJUwDXXzWSXmKVK2VxxnWCmNS63DeScvGHmJD3aVcx/syS/JuZVTfc7waedhp2O3N236NlicE
ecQNo9YRhX0BwQzhC91UcQ9mdGlKr8blmyKBVH02e3T8X3E6GiFGVREsVp3jDb8SkEI8sNSDcMGw
eilQQJ8yLy7Whnr1SP3mCApHOYZVcpLQyWSXxI89s64kRl7eLfflYhGu26MHcP+EyJaWd1MDb9Yc
OtbJ5obn7DC0m6rH7BtEVvqQ7SWE8y7SD1aRUPZvFVVpxAg703rLk0J1hTSgfWY9aMMGBiMijoIc
6Go07rIH44PNL+gy0DiD1x/rYnhkMY088VuvoKKyzgWQY53C0eH67P5V1dyQcA28esfQKo45HUug
aOA7GLXsOlN96NvK8ho7RA2G140+7Xo89NcvwjpaY3mNDWCTzFLQ5mSclF3WcjQsPkl/yqMPJltT
c2DG5NApHEzeNjp2lClLZDqEPvHnKuA2Or9kh156LWZTAQBzagLK8dhm9N92R6yYoG7wSANTMh24
3VcakUFpkYhs4guQdjoPD11R06eadjp34xyAJwAwmkLLexz6ZL38u5SYAdnj7LSWk/OuTVt/G0iF
C3Mrh+4EyPn9DfRRRqK8Wlt7641SjMBI+wXF1Pu2vo8/Ssbcq3CpsdDjWwHsRxptAPUQ8JQTgvP+
j2LQItJ27ic2a1fLWLD56fh/KlVpKXedTydxK/INi8KMWaelGn0MOUidxJZ1dYRBnld+5oHwUJK0
NJsg5cN0cdlQU0V9VrUQ2JOO5nN8lsYJcXkqswvwTmJckUZaBfTvWKzoT1zZwq1kEdDVZ23YBNQ+
sowAc14JaTslPWA/ZaPidK65LNSoe7ZtWFieNjGXDXZ1LcLshLcNDQ6iZvxmtWK+TMf1j8jRcf86
3O90Fl55jQ7mTO7CSP0vPTtuPAZOFG9RPXdJdrqCtjtiQkdoQDVPhR/xcJSPPXC+7nrMP7fOSuTc
KR+M1Hf3IInjiwkffEymZ+CvLGQYkem/preRiEZc90tkpGKdFe1qSx+zskXRGyNDADo4AAkCqRvz
l9e/wcuS8kTk0fdda2GgnAoD+hqPwBA8H1Dk/IryJ7ELPDwlHWZ8btLe59eylNlsRcA7b03PQ27y
M3Hftj1YUw5rRsn5S/dy5C5bP4Kp4M599fQ4Goi6y+8gQ0k2cSfUDP8qwRp7FnbUgqyGa/l0M1x6
Jgbl2bEfdW54/+l5CuS1thDo124iM7Wk4h1j0/uFI4Tmigrx7gWUkl4ETmWNFTWYzC3pBt6r8V66
2zEii2R4IkBrqQIsUN5IPLg+TDGVRmNHKOHR50gaKRGmc46QxuNakELGjZUrd/f3LXtXTUJeB9aN
X6gu/abDP+tvQ7s6uI05nXKxWxLMY4nXxxOjs26Z64YpXbboqPgvDfwL91CKoqPTYuM7syqJPrKN
q64gRWQTlNHOYaAH1IUXaKudBu997P4xcpfPJ/rKVBTGYc5C+o0Dnq5sirSubTYReK1v+Dx0MCFg
qvz/hpOvde7F+yaXcdK+U6sfVRfD1+tzZRHRgGtbvsswHZT9GQvnirNPiVNfEnVwqpQnrhxylUXT
k/f0Yn3Z0zu1t4e38o9xiLkLovOF9lJEvjKPa/CaTCidyHhyoH5/TEs70db/t1pT85osCu3IBas7
Ebmwx5khrZyC22RFiyfrG0u2fYYDr6fpFOSw9ABY9fh9z4s7OY/eaprdUiYy9XYwIYag7lYGw6zx
ge1IWryWFCeZ3acLc7NIScqwcckkvJ2njbgbjxEIC+izn8DSfhyNEUBYwXbCU4YRV+271FMQFklu
JoYGZrfj2abWsTlYGf/PNtO4d5svhS43uxGagjREMbN6yCPt5kaG0xvDBgKSY5Qv44qEoGF1tNSv
DdVE9lzHJ4JKwHPh199cpGJZbKUfInTvH5uut3LaUmGpvvNVUPJcC4EWRMMSluZu9Wt5ScFUk8wr
Q+qJre190ymkO27WXsNC0PyNAHB0dQZMMPXuKMG0FBOLtFopu2y2Ad3Koacp34uF+tft8J7Fyzay
eICER8K2zS+bLJRm4Be1ZQSLBRSWjjnjIwXTGVNtk7sEq084koAricxWKPZV69hshxFkGfwyp9Iy
vtYmXvxBkKeOpgkkzyJ39axCHWBuQ4iuJsFnKcVFLIXvAXI9sjDsll8g/4G7xwj73XTJ5agXuJl/
tt3okdVs7wdfVJyl+n82XearC/jGrtbHjgffMip0RL7v3S2hhJAJ8ViSL602Yquv5JaUP25YnG6q
AUtaL2rsafxAHtPzROxnjHieEFyjo8gVvc91HhEebnSCRtUamnvtYkZIzs/wyBplgF/KzmTdgKwy
2t3jwV31cqFFRTSHNrQqeOwL7Ck4cqdEpP8IJ3zEYFU9W0PA44iyVPkQHIpeS2kIa0AKtg5bRWE+
pSn8XDOpmQj6MCvMlU6Fm6CSeAWnWrE4H8o4Gbf4m+1pZJRdq3wqHLwI57TiLo9h8pr1WxlG70C/
yqwuAY2CqWQrMNZUawMGn2mxlZ1idoMqQg3TqonFCdnB2aWhNAAPE5ArB2vxJ64aJKOrK9+2IFYv
ZBTv5MhJ/V19MrraTpM3g6l9DJ/bt5E5aYHpAfr8IWikjncP4NkqRBGdz7RaRrWERn8OZcMjg+hC
rts5iKKbo4ownPU1d4ue7vcA6hGxV8G+Up0yQWk8NEJzybwjmcP/PH651yI6UD7folFyvAcjpjyo
J2feNY6NM/nEwW3+2Y75j1/IxqYl7TIpK0rQ8QkeFNiyccD3TrMi2Hr8zNvgHM9RpMl0KdyTlq2+
CPCqNCoe2ugQn3XWhxufm+qlHoCEVtdpAWENijWXKkp4meoFOAGLvyZZDCQ+ITrGhy5M7GCDUAIT
KuEVGH48BVPS3SZfq+A9qLdJqnYQFsgz+dlnChdfwutPz8vzrhFmLi2b6Kilkl4F3cji5GNqtEDp
Q4kgdyrHSXmvx9m5xAaQsIxK0MR3Lc6PE0cHtpAe1U+lfNXJe67BFMBht1W0E+iHH6t0i2ZoLZsW
ZqcIjBot1/yMwPBY5y7s7kGTwlMozfDJyr2xgz4qMTGsg2GPPhLs2bbnG5QAbt73yMdDE/mI1x24
qbthYb3iPzplAMRIesIQB0pJxcTuVcqzMe2WrD7VZwyj1w7lcVBil7ZZ0A3ZOLbOENJvD3aueX6N
wsdvBej/u8VMkpUnSEvZ6x0fM760jfDHdGnmYYBQ0LYAd8vYWHdS0tKZA8MK62eY+n4rIJ61DAMD
v737FA3YGysKackpN/2cPc0fTv4As28X+8D7TunJp3zSTw/O0jM+0vB/boJaWR4/vQFe8pZUV7OW
g0GuqVUTZxeOzk63AA+0x753NmZJ2aqS4f9Ak7UcJiLpAkx3aG6vdmDVllx8gHub7ujxnKPt1cfj
VaKDUgTpPgr1rrMkxk6wnW9/6gJl3i2R79KDPN9NQzoXsqVsxbjxxd8vTlwxCIBGPWtUSrReFyBW
vjNuDii7PvxPR1ABl55Epebe2C0ab0oopXG74sDQe+rAGHq9SCZ0Sfc27nGrLpKgcNVvl5jRS226
YWcNzZDmp54B+q6ASWjSUe7aoeZUVWr4klxLEna5alMFvmCF2Th5mrJodVwjCksOdysMTpidnsTu
dzeaQMUqcWPzdMJVWKBrZZEZfCnryePF8BYal8zzMGKC9vVFEZIHPUkQjTQzTAunXTrUt13lSfVy
wbROhGQ2XgGlERXbQQ4550oPGV31lBYAL7YbvzTjhFpu6vWtV0j1s4MnEf1N6u8PsxLzdQ/AMncC
YFz4RrAUG2iYr39JN2HdXTNx7MJlsa9nNTwxOelCUUpRq7a5p6TpmxZB6zNQE649fnpeycXiLnh9
8uFfhC8j0kps4zOdVV4KKiBXweji3dI5YIoqvv57sy5JUu7Nky86VBghINgscdoNdEHmD0L60L3n
nQZ5BZPv5h5wFqwLDcZ6judKA17kyRWxVuxGbOoNv5VpcmzcCzgd/jGfC2xonw0tO26PJ0K2MzA/
4dctwktGK8gQ5DWtkBOdCOZJJQQAE+ZJKxqCgDSS11aVltZ0Ndj56RmOBTqQ63MD9MIWfnJ8oGGf
OaSPmTKYmSlQShz1Tv4TDbDqUZIpcQU8WqLKJnIXkmiTfckwwgcjSmcXlzaVS5uuLDy84AFB7s4k
b1OImb3gkX0zYVXtCUm/lYG2+C6T6U3tGYlWzgCTC5LSYcc7kL0Zor/spU71SqM8BVznuyn+aher
5sTMRR1e6/3Bp2tlhBv26HEYnaDNI24MNqIdqkPC3X6O52UJg5vRwMnJ8RoBLU0Li5YIdFT9rsvG
xdNTf6MFNMY7MrIRAahvzWNfPlu4Ug0hh94w6CP4bNt8mTUapu8vBy6HVpLY582n9oI77nkwwpoW
JmEmyYtxW3hPaPzfQtoTD9MiJo9EcVL6bHnYXSAOYxYBcRxRjQpTao/T5XXbEwGWkQKPdEhS6f/z
nazkyAMXDNBQ/rqD/DGWg+YUPz1eh4tOwXIVyQSJ/z/qQL+yheC4ezqggKb8nCSfh1M8aYRjqfRy
pw3orqvFxpe2lzNOChL1YN0qCin2e2rjtVJOvafxixbCwAeCs4z2DL3OnhUaGNFC7nhaL3+Z1/cD
OJXOMlheBhlIwpV2q1S6IZud+/lpInBvprdoqwFIfwPHFvIUAJ+ueEvwnCQmhKmwKGbPkA3YjXhZ
0+agQYQrkK/kTfsuLh1a+DP4C7MNcZBtsSL/Fmcn7MG+/KqQ02E5l54SZKAqz//m9YNjeFGXnuds
rsBIYAjMkY/2TChjKDSenp7cNI5HyGWQftPng7ZScsidiXp9mVqRo7eZVkUbUhBg8vjDNDmqM0jj
/6OxYihczZJvTd/jYsWI4dUWZYw1I4yCdNsaS3z6YvSse6lD6irZOHacToT/cyxsYagM+PhJ1nhK
0qr0VFsNHoSlBZSI2EgkWqgeq1Pq1SXuLjf/vhaMGMtQPUDZACkZ1pdb1INAM6a8mfsaLmW2Iwks
QAG77iGaYs2dUX1/vJpHukbqYUS8GZzWoJL5r2E7EZVD7vkZ5ZE1gN4kWjygvzmF9GpSI4qoLATM
WvsjNSsROxNElcpZNHlwGXyPz2G9FczoVS6iObsRmKv6fminEJjJhhSwgjFvxP8pCrVPFaXMTQoV
p+RbO0AJ2Tbs+8dqCheTS4nDAPVQnn/Aa9eikxxuO3581XUyvHyPRw3jGygSbyzC14yWOgbIsJs7
QeAuSXCdwlNe6WUsb73ppmbhjXejIifXgkV29NmZUlO2jWdHzLVrP2tn4oWQiNdSJUmgQ+eDRSaT
M7U9mZHGTfmIj3s4pVyXGkR9IzQmI+FNUP/3biGyYTn5q7eJgoY4DPpGzmnW8qyFwzbzUz5B4xZu
/zoRnL1y888XJaEpIWeXG6aHaWQEz1BmLp8h1/DO25WeO7vg2MRt2r1znjqI5pxpAgdMf9g2gN7J
lLGgD30CtMpDUC/nr9MWEhRE4dfcDVrJqy+cQi67ktliyw1p0wShoSBD+oCydObWkuyAQsW+Y4RP
bgjyyXyifhWPqQFtb8DMrn3nWKPBEUJkjiQHfs+h5EDNxovEUoakB5alj49UeIjh4cFwyo2qL5S6
y7b+y+bM6/7foc7wW5B4UGkHgHzOtwmYBUyTMrJK/VA6zZQ3/09D26GV5D6iyrNk7LHuc0US3npb
xw4NR3JTLaOKu9RsFT6YCD+INIKlAvpG6JDyUo+dzZIyE+kMrtKCB7NDkbijmEXuMvkSC/YzCzK7
JQecjs4abWygwL8jnFi14hIW5egwpnKHWqGNrjJ8Q3VgFG87jPTdB3PWfQ2i/WD1Elb5cD4MYZJm
Yl9TZRBlfHpWPGmOudt04nUryQ8skx+ttiOErbVgnjVX+Czs+nln23Lv50weLq4Oj/2h7FEAmnh5
78YiyacE41GeGXt8UQPEfN2JWOTpmwkLALU0VBOXGFkAIlDHpQjzyoTRzDMJrjU/qVId0cYCjU1C
/iKIqdGaV+xiXlYGOfWn2We8cKkgphJG4UEYGysKaCoFj4vAcSsuOUCKS9U/I5AJte9Ci9+GQxpD
GBXQT0xM/bVJ+zO2ZYyFfcknwa9V6aZd50OgPDRm5lKcS7t8ZVhp3Ms6Xb77c9qePgit/8XVIwFq
ehgc3hnHoMwHBYic1YaMT3fQrvTp12rugamec/AbM7I1pRrv6wc8b0cL8CKQlWDDpv2Plo0XsQTM
gJdshU6WrD/6dpPS+i0JcY4molTHtPLsLuF0UHlNs2S3vVq9vy3DvgLyMReUro5MRDBLrrTAZshZ
bqsrpwOXCWmFCq2zpEh/TgUtD269eWRb6u0oduDWL1RMbldo1JdWC0mqRvW1pMwTq7/k/CkUWJnA
xSnqyyImOwQRZykzkudbBDoFy7RT3woZs8rPR721SFBQpMZ8lpW38aAIZ80iuUtBXHaMkLA7t0Ct
vKtzHHcY0r+N8nzfBqCzRBCUn6b6nsXNE5apnUmUAkgeIbr2Qq5Pkd3+vYbm73njb8CxZmzNvSjK
JCnLiEQSemDQJmfkS/Uh9KFxV0z9H/lIQO3f91LIgvl28d4I8Pb2RsNyz9U5BvU/j0dDgPQjjSg2
DAhN8DP4xoLL60HCkPZpOm6Si6o0tHnVth0b9YUPYD123egfSsqAvECdU+c7kIhtUYElfRFSZJW4
M+KgbbSw7yyTNtSDRuqx0fN0aOc8u4IFBE5+PEb4l7AfSE4Pi/PTvSkSF8yEi5RFVj1CScyETqUc
rhQuFPWV0n3WCPsqfg08TS6GkrGDpJhYKjwHoaZIkCyiaiABTuvCgoWyuyrqsPkGG7xreeta8Xym
hhjpZEyfPFI0jFkFLd+s8tCkhXRtd+PA1btVKIqD+Bdx7nfduR1s7tfR/Cp5odAxw2aZDmE9sKg/
cyxBPQ==
`protect end_protected
| mit | a01e1e1fc0d3fd3b78bcc710bfee7d4c | 0.924576 | 1.905916 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/generic/rule_007_test_input.fixed_lower.vhd | 1 | 1,897 |
entity FIFO is
generic (
g_width : integer := 256;
g_depth : integer := 32;
prefix_generic_suffix : integer := 20
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
entity FIFO is
generic (
g_width : integer := 256;
g_depth : integer := 32;
prefix_generic_suffix : integer := 20
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
entity FIFO is
generic (
g_width : integer := 256;
g_depth : integer := 32;
prefix_generic_suffix : integer := 20
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
entity FIFO is
generic (
g_width : integer := 256;
g_depth : integer := 32;
prefix_generic_suffix : integer := 20
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
entity FIFO is
generic(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32;
prefix_generic_suffix : integer := 20
);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
entity FIFO is
generic(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32;
prefix_generic_suffix : integer := 20
);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
entity FIFO is
generic(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32;
prefix_generic_suffix : integer := 20
);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
entity FIFO is
generic(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32;
prefix_generic_suffix : integer := 20
);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
| gpl-3.0 | 816892507ae1bc29396291f5d3eafef2 | 0.573537 | 3.120066 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/generic_map/rule_002_test_input.fixed_lower.vhd | 1 | 585 |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
g_gen_1(3 downto 0) => 3,
g_gen_2(2 downto 1) => 4,
g_gen_3 => 5
)
port map (
PORT_1(3 downto 0) => w_port_1,
PORT_2 => w_port_2,
PORT_3(2 downto 1) => w_port_3
);
-- Violations below
U_INST1 : INST1
generic map (
g_gen_1(3 downto 0) => 3,
g_gen_2(2 downto 1) => 4,
g_gen_3 => 5
)
port map (
port_1(3 downto 0) => w_port_1,
port_2 => w_port_2,
port_3(2 downto 1) => w_port_3
);
end architecture ARCH;
| gpl-3.0 | f523c0b97f17c0a30b813c3f74fa1beb | 0.492308 | 2.683486 | false | false | false | false |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.