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SoCdesign/audiomixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/channel_v1_00_a/hdl/vhdl/user_logic.vhd | 1 | 30,900 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Fri May 29 16:59:20 2015 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
CLK_48_in : in std_logic;
CLK_100M_in : in std_logic; -- get rid of this
Channel_Left_in : in std_logic_vector(23 downto 0);
Channel_Right_in : in std_logic_vector(23 downto 0);
Channel_Left_out : out std_logic_vector(23 downto 0);
Channel_Right_out : out std_logic_vector(23 downto 0);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg2 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg3 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg4 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg5 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg6 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg7 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg8 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg9 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg10 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg11 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg12 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg13 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg14 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg15 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg16 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg17 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg18 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg19 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg20 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg21 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg22 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg23 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg24 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg25 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg26 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg27 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg28 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg29 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg30 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg31 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg_write_sel : std_logic_vector(31 downto 0);
signal slv_reg_read_sel : std_logic_vector(31 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal slv_reg26_internal : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg28_internal : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg29_internal : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
--signal slv_reg30_internal : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
--signal slv_reg31_internal : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg28_internal_null : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg29_internal_null : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(31 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(31 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13) or Bus2IP_WrCE(14) or Bus2IP_WrCE(15) or Bus2IP_WrCE(16) or Bus2IP_WrCE(17) or Bus2IP_WrCE(18) or Bus2IP_WrCE(19) or Bus2IP_WrCE(20) or Bus2IP_WrCE(21) or Bus2IP_WrCE(22) or Bus2IP_WrCE(23) or Bus2IP_WrCE(24) or Bus2IP_WrCE(25) or Bus2IP_WrCE(26) or Bus2IP_WrCE(27) or Bus2IP_WrCE(28) or Bus2IP_WrCE(29) or Bus2IP_WrCE(30) or Bus2IP_WrCE(31);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6) or Bus2IP_RdCE(7) or Bus2IP_RdCE(8) or Bus2IP_RdCE(9) or Bus2IP_RdCE(10) or Bus2IP_RdCE(11) or Bus2IP_RdCE(12) or Bus2IP_RdCE(13) or Bus2IP_RdCE(14) or Bus2IP_RdCE(15) or Bus2IP_RdCE(16) or Bus2IP_RdCE(17) or Bus2IP_RdCE(18) or Bus2IP_RdCE(19) or Bus2IP_RdCE(20) or Bus2IP_RdCE(21) or Bus2IP_RdCE(22) or Bus2IP_RdCE(23) or Bus2IP_RdCE(24) or Bus2IP_RdCE(25) or Bus2IP_RdCE(26) or Bus2IP_RdCE(27) or Bus2IP_RdCE(28) or Bus2IP_RdCE(29) or Bus2IP_RdCE(30) or Bus2IP_RdCE(31);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
slv_reg12 <= (others => '0');
slv_reg13 <= (others => '0');
slv_reg14 <= (others => '0');
slv_reg15 <= (others => '0');
slv_reg16 <= (others => '0');
slv_reg17 <= (others => '0');
slv_reg18 <= (others => '0');
slv_reg19 <= (others => '0');
slv_reg20 <= (others => '0');
slv_reg21 <= (others => '0');
slv_reg22 <= (others => '0');
slv_reg23 <= (others => '0');
slv_reg24 <= (others => '0');
slv_reg25 <= (others => '0');
slv_reg26 <= (others => '0');
slv_reg27 <= (others => '0');
slv_reg28 <= (others => '0');
slv_reg29 <= (others => '0');
slv_reg30 <= (others => '0');
slv_reg31 <= (others => '0');
else
case slv_reg_write_sel is
when "10000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "01000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00100000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00010000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00001000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg4(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000100000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg5(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000010000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg6(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000001000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg7(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000100000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg8(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000010000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg9(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000001000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg10(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000100000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg11(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000010000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg12(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000001000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg13(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000100000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg14(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000010000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg15(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000001000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg16(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000100000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg17(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000010000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg18(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000001000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg19(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000100000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg20(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg21(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg22(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg23(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg24(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg25(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
-- when "00000000000000000000000000100000" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg26(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
when "00000000000000000000000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg27(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
-- when "00000000000000000000000000001000" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg28(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when "00000000000000000000000000000100" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg29(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
when "00000000000000000000000000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg30(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg31(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
slv_reg26 <= slv_reg26_internal;
slv_reg28 <= slv_reg28_internal;
slv_reg29 <= slv_reg29_internal;
--slv_reg30 <= slv_reg30_internal;
--slv_reg31 <= slv_reg31_internal;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23, slv_reg24, slv_reg25, slv_reg26, slv_reg27, slv_reg28, slv_reg29, slv_reg30, slv_reg31 ) is
begin
case slv_reg_read_sel is
when "10000000000000000000000000000000" => slv_ip2bus_data <= slv_reg0;
when "01000000000000000000000000000000" => slv_ip2bus_data <= slv_reg1;
when "00100000000000000000000000000000" => slv_ip2bus_data <= slv_reg2;
when "00010000000000000000000000000000" => slv_ip2bus_data <= slv_reg3;
when "00001000000000000000000000000000" => slv_ip2bus_data <= slv_reg4;
when "00000100000000000000000000000000" => slv_ip2bus_data <= slv_reg5;
when "00000010000000000000000000000000" => slv_ip2bus_data <= slv_reg6;
when "00000001000000000000000000000000" => slv_ip2bus_data <= slv_reg7;
when "00000000100000000000000000000000" => slv_ip2bus_data <= slv_reg8;
when "00000000010000000000000000000000" => slv_ip2bus_data <= slv_reg9;
when "00000000001000000000000000000000" => slv_ip2bus_data <= slv_reg10;
when "00000000000100000000000000000000" => slv_ip2bus_data <= slv_reg11;
when "00000000000010000000000000000000" => slv_ip2bus_data <= slv_reg12;
when "00000000000001000000000000000000" => slv_ip2bus_data <= slv_reg13;
when "00000000000000100000000000000000" => slv_ip2bus_data <= slv_reg14;
when "00000000000000010000000000000000" => slv_ip2bus_data <= slv_reg15;
when "00000000000000001000000000000000" => slv_ip2bus_data <= slv_reg16;
when "00000000000000000100000000000000" => slv_ip2bus_data <= slv_reg17;
when "00000000000000000010000000000000" => slv_ip2bus_data <= slv_reg18;
when "00000000000000000001000000000000" => slv_ip2bus_data <= slv_reg19;
when "00000000000000000000100000000000" => slv_ip2bus_data <= slv_reg20;
when "00000000000000000000010000000000" => slv_ip2bus_data <= slv_reg21;
when "00000000000000000000001000000000" => slv_ip2bus_data <= slv_reg22;
when "00000000000000000000000100000000" => slv_ip2bus_data <= slv_reg23;
when "00000000000000000000000010000000" => slv_ip2bus_data <= slv_reg24;
when "00000000000000000000000001000000" => slv_ip2bus_data <= slv_reg25;
when "00000000000000000000000000100000" => slv_ip2bus_data <= slv_reg26;
when "00000000000000000000000000010000" => slv_ip2bus_data <= slv_reg27;
when "00000000000000000000000000001000" => slv_ip2bus_data <= slv_reg28;
when "00000000000000000000000000000100" => slv_ip2bus_data <= slv_reg29;
when "00000000000000000000000000000010" => slv_ip2bus_data <= slv_reg30;
when "00000000000000000000000000000001" => slv_ip2bus_data <= slv_reg31;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
SIP : entity work.channel_internal port map (
Channel_Left_out => Channel_Left_out ,
Channel_Right_out => Channel_Right_out ,
slv_reg26 => slv_reg26_internal ,
slv_reg28 => slv_reg28_internal ,
slv_reg29 => slv_reg29_internal ,
slv_reg30 => slv_reg30 ,
slv_reg31 => slv_reg31 ,
CLK_48_in => CLK_48_in ,
CLK_100M_in => CLK_100M_in ,
Channel_Left_in => Channel_Left_in ,
Channel_Right_in => Channel_Right_in ,
slv_reg0 => slv_reg0 ,
slv_reg1 => slv_reg1 ,
slv_reg2 => slv_reg2 ,
slv_reg3 => slv_reg3 ,
slv_reg4 => slv_reg4 ,
slv_reg5 => slv_reg5 ,
slv_reg6 => slv_reg6 ,
slv_reg7 => slv_reg7 ,
slv_reg8 => slv_reg8 ,
slv_reg9 => slv_reg9 ,
slv_reg10 => slv_reg10 ,
slv_reg11 => slv_reg11 ,
slv_reg12 => slv_reg12 ,
slv_reg13 => slv_reg13 ,
slv_reg14 => slv_reg14 ,
slv_reg15 => slv_reg15 ,
slv_reg16 => slv_reg16 ,
slv_reg17 => slv_reg17 ,
slv_reg18 => slv_reg18 ,
slv_reg19 => slv_reg19 ,
slv_reg20 => slv_reg20 ,
slv_reg21 => slv_reg21 ,
slv_reg22 => slv_reg22 ,
slv_reg23 => slv_reg23 ,
slv_reg24 => slv_reg24 ,
slv_reg25 => slv_reg25 ,
slv_reg27 => slv_reg27
);
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
| mit | 2417b4a8eb36290f8a6dc5118e15b7e1 | 0.521909 | 3.677258 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/svd_2x2/svd_2x2.srcs/sources_1/ip/arctan/demo_tb/tb_arctan.vhd | 1 | 15,570 | --------------------------------------------------------------------------------
-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Description:
-- This is an example testbench for the CORDIC IP core.
-- The testbench has been generated by Vivado to accompany the IP core
-- instance you have generated.
--
-- This testbench is for demonstration purposes only. See note below for
-- instructions on how to use it with your core.
--
-- See the CORDIC product guide for further information
-- about this core.
--
--------------------------------------------------------------------------------
-- Using this testbench
--
-- This testbench instantiates your generated CORDIC core
-- instance named "arctan".
--
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
-- documentation for details.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity tb_arctan is
end tb_arctan;
architecture tb of tb_arctan is
-----------------------------------------------------------------------
-- Timing constants
-----------------------------------------------------------------------
constant CLOCK_PERIOD : time := 100 ns;
constant T_HOLD : time := 10 ns;
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
constant TEST_CYCLES : integer := 3000;
constant PHASE_CYCLES : integer := 1000;
-----------------------------------------------------------------------
-- DUT input signals
-----------------------------------------------------------------------
-- General inputs
signal aclk : std_logic := '0'; -- the master clock
-- Slave channel CARTESIAN inputs
signal s_axis_cartesian_tvalid : std_logic := '0'; -- TVALID for channel S_AXIS_CARTESIAN
signal s_axis_cartesian_tdata : std_logic_vector(31 downto 0) := (others => 'X'); -- TDATA for channel S_AXIS_CARTESIAN
-- Slave channel PHASE inputs
signal s_axis_phase_tvalid : std_logic := '0'; -- TVALID for channel S_AXIS_PHASE
signal s_axis_phase_tdata : std_logic_vector(15 downto 0) := (others => 'X'); -- TDATA for channel S_AXIS_PHASE
-----------------------------------------------------------------------
-- DUT output signals
-----------------------------------------------------------------------
-- Master channel DOUT outputs
signal m_axis_dout_tvalid : std_logic := '0'; -- TVALID for channel M_AXIS_DOUT
signal m_axis_dout_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- TDATA for channel M_AXIS_DOUT
-----------------------------------------------------------------------
-- Aliases for AXI channel TDATA fields
-- These are a convenience for viewing data in a simulator waveform viewer.
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
-- to prevent the simulator optimizing away these signals.
-----------------------------------------------------------------------
signal s_axis_cartesian_tdata_real : std_logic_vector(15 downto 0) := (others => '0');
signal s_axis_cartesian_tdata_imag : std_logic_vector(15 downto 0) := (others => '0');
signal s_axis_phase_tdata_real : std_logic_vector(15 downto 0) := (others => '0');
signal m_axis_dout_tdata_real : std_logic_vector(15 downto 0) := (others => '0');
signal m_axis_dout_tdata_imag : std_logic_vector(15 downto 0) := (others => '0');
signal m_axis_dout_tdata_phase : std_logic_vector(15 downto 0) := (others => '0');
-----------------------------------------------------------------------
-- Testbench signals
-----------------------------------------------------------------------
signal cycles : integer := 0; -- Clock cycle counter
-----------------------------------------------------------------------
-- Constants, types and functions to create input data
-- The CORDIC is fed two sinusoids exp(+/-jwt) of different frequencies and amplitudes:
-- channel CARTESIAN: exp(+jwt), frequency = clock / 30,
-- channel PHASE: exp(-jwt), frequency = clock / 32,
-----------------------------------------------------------------------
constant IP_CARTESIAN_DEPTH : integer := 30;
constant IP_CARTESIAN_WIDTH : integer := 16;
constant IP_CARTESIAN_SHIFT : integer := 3; -- bit shift for amplitude
constant IP_PHASE_DEPTH : integer := 32;
constant IP_PHASE_WIDTH : integer := 16;
constant IP_PHASE_SHIFT : integer := 0; -- no bit shift, max amplitude
type T_IP_INT_ENTRY is record
re : integer;
im : integer;
end record;
type T_IP_CARTESIAN_ENTRY is record
re : std_logic_vector(IP_CARTESIAN_WIDTH-1 downto 0);
im : std_logic_vector(IP_CARTESIAN_WIDTH-1 downto 0);
end record;
type T_IP_PHASE_ENTRY is record
re : std_logic_vector(IP_PHASE_WIDTH-1 downto 0);
end record;
type T_IP_CARTESIAN_TABLE is array (0 to IP_CARTESIAN_DEPTH-1) of T_IP_CARTESIAN_ENTRY;
type T_IP_PHASE_TABLE is array (0 to IP_PHASE_DEPTH-1) of T_IP_PHASE_ENTRY;
-- Common function to calculate sine and cosine values
function create_ip_entry(index, depth, width : integer) return T_IP_INT_ENTRY is
variable result : T_IP_INT_ENTRY;
variable theta : real;
variable limited_width : integer := width - 2;
begin
if limited_width > 30 then
limited_width := 30; --avoid integer overflow
end if;
theta := real(index) / real(depth) * 2.0 * MATH_PI;
result.re := integer(round(cos(theta) * real(2**limited_width)));
result.im := integer(round(sin(theta) * real(2**limited_width)));
return result;
end function create_ip_entry;
-- Use separate functions to calculate channel S_AXIS_CARTESIAN and S_AXIS_PHASE sinusoids as they return different types
function create_ip_cartesian_table return T_IP_CARTESIAN_TABLE is
variable result : T_IP_CARTESIAN_TABLE;
variable entry_int : T_IP_INT_ENTRY;
begin
for i in 0 to IP_CARTESIAN_DEPTH-1 loop
entry_int := create_ip_entry(i, IP_CARTESIAN_DEPTH, IP_CARTESIAN_WIDTH - IP_CARTESIAN_SHIFT);
result(i).re := std_logic_vector(to_signed(entry_int.re, IP_CARTESIAN_WIDTH));
result(i).im := std_logic_vector(to_signed(entry_int.im, IP_CARTESIAN_WIDTH));
end loop;
return result;
end function create_ip_cartesian_table;
function create_ip_phase_table return T_IP_PHASE_TABLE is
variable result : T_IP_PHASE_TABLE;
variable entry_int : T_IP_INT_ENTRY;
begin
for i in 0 to IP_PHASE_DEPTH-1 loop
entry_int := create_ip_entry(IP_PHASE_DEPTH-1-i, IP_PHASE_DEPTH, IP_PHASE_WIDTH - IP_PHASE_SHIFT); -- note rotation direction
result(i).re := std_logic_vector(to_signed(entry_int.re, IP_PHASE_WIDTH));
end loop;
return result;
end function create_ip_phase_table;
-- Call the functions to create the data
constant IP_CARTESIAN_DATA : T_IP_CARTESIAN_TABLE := create_ip_cartesian_table;
constant IP_PHASE_DATA : T_IP_PHASE_TABLE := create_ip_phase_table;
begin
-----------------------------------------------------------------------
-- Instantiate the DUT
-----------------------------------------------------------------------
dut : entity work.arctan
port map (
aclk => aclk,
s_axis_cartesian_tvalid => s_axis_cartesian_tvalid,
s_axis_cartesian_tdata => s_axis_cartesian_tdata,
m_axis_dout_tvalid => m_axis_dout_tvalid,
m_axis_dout_tdata => m_axis_dout_tdata
);
-----------------------------------------------------------------------
-- Generate clock
-----------------------------------------------------------------------
clock_gen : process
begin
aclk <= '0';
wait for CLOCK_PERIOD;
loop
cycles <= cycles + 1;
aclk <= '0';
wait for CLOCK_PERIOD/2;
aclk <= '1';
wait for CLOCK_PERIOD/2;
if cycles >= TEST_CYCLES then
report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
wait;
end if;
end loop;
end process clock_gen;
-----------------------------------------------------------------------
-- Generate inputs
-----------------------------------------------------------------------
stimuli : process
variable ip_cartesian_index : integer := 0;
variable ip_phase_index : integer := 0;
variable cartesian_tvalid_nxt : std_logic := '0';
variable phase_tvalid_nxt : std_logic := '0';
variable phase2_cycles : integer := 1;
variable phase2_count : integer := 0;
constant PHASE2_LIMIT : integer := 30;
begin
-- Test is stopped in clock_gen process, use endless loop here
loop
-- Drive inputs T_HOLD time after rising edge of clock
wait until rising_edge(aclk);
wait for T_HOLD;
-- Drive AXI TVALID signals to demonstrate different types of operation
case cycles is -- do different types of operation at different phases of the test
when 0 to PHASE_CYCLES * 1 - 1 =>
-- Phase 1: inputs always valid, no missing input data
cartesian_tvalid_nxt := '1';
phase_tvalid_nxt := '1';
when PHASE_CYCLES * 1 to PHASE_CYCLES * 2 - 1 =>
-- Phase 2: deprive channel S_AXIS_CARTESIAN of valid transactions at an increasing rate
phase_tvalid_nxt := '1';
if phase2_count < phase2_cycles then
cartesian_tvalid_nxt := '0';
else
cartesian_tvalid_nxt := '1';
end if;
phase2_count := phase2_count + 1;
if phase2_count >= PHASE2_LIMIT then
phase2_count := 0;
phase2_cycles := phase2_cycles + 1;
end if;
when PHASE_CYCLES * 2 to PHASE_CYCLES * 3 - 1 =>
-- Phase 3: deprive channel S_AXIS_CARTESIAN of 1 out of 2 transactions, and channel S_AXIS_PHASE of 1 out of 3 transactions
if cycles mod 2 = 0 then
cartesian_tvalid_nxt := '0';
else
cartesian_tvalid_nxt := '1';
end if;
if cycles mod 3 = 0 then
phase_tvalid_nxt := '0';
else
phase_tvalid_nxt := '1';
end if;
when others =>
-- Test will stop imminently - do nothing
null;
end case;
-- Drive handshake signals with local variable values
s_axis_cartesian_tvalid <= cartesian_tvalid_nxt;
s_axis_phase_tvalid <= phase_tvalid_nxt;
-- Drive AXI slave channel CARTESIAN payload
-- Drive 'X's on payload signals when not valid
if cartesian_tvalid_nxt /= '1' then
s_axis_cartesian_tdata <= (others => 'X');
else
-- TDATA: Real and imaginary components are each 16 bits wide and byte-aligned at their LSBs
s_axis_cartesian_tdata(15 downto 0) <= IP_CARTESIAN_DATA(ip_cartesian_index).re;
s_axis_cartesian_tdata(31 downto 16) <= IP_CARTESIAN_DATA(ip_cartesian_index).im;
end if;
-- Drive AXI slave channel PHASE payload
-- Drive 'X's on payload signals when not valid
if phase_tvalid_nxt /= '1' then
s_axis_phase_tdata <= (others => 'X');
else
-- TDATA: Real component is 16 bits wide and byte-aligned at its LSBs
s_axis_phase_tdata(15 downto 0) <= IP_PHASE_DATA(ip_phase_index).re;
end if;
-- Increment input data indices
if cartesian_tvalid_nxt = '1' then
ip_cartesian_index := ip_cartesian_index + 1;
if ip_cartesian_index = IP_CARTESIAN_DEPTH then
ip_cartesian_index := 0;
end if;
end if;
if phase_tvalid_nxt = '1' then
ip_phase_index := ip_phase_index + 1;
if ip_phase_index = IP_PHASE_DEPTH then
ip_phase_index := 0;
end if;
end if;
end loop;
end process stimuli;
-----------------------------------------------------------------------
-- Check outputs
-----------------------------------------------------------------------
check_outputs : process
variable check_ok : boolean := true;
begin
-- Check outputs T_STROBE time after rising edge of clock
wait until rising_edge(aclk);
wait for T_STROBE;
-- Do not check the output payload values, as this requires the behavioral model
-- which would make this demonstration testbench unwieldy.
-- Instead, check the protocol of the DOUT channel:
-- check that the payload is valid (not X) when TVALID is high
if m_axis_dout_tvalid = '1' then
if is_x(m_axis_dout_tdata) then
report "ERROR: m_axis_dout_tdata is invalid when m_axis_dout_tvalid is high" severity error;
check_ok := false;
end if;
end if;
assert check_ok
report "ERROR: terminating test with failures." severity failure;
end process check_outputs;
-----------------------------------------------------------------------
-- Assign TDATA fields to aliases, for easy simulator waveform viewing
-----------------------------------------------------------------------
s_axis_cartesian_tdata_real <= s_axis_cartesian_tdata(15 downto 0);
s_axis_cartesian_tdata_imag <= s_axis_cartesian_tdata(31 downto 16);
m_axis_dout_tdata_phase <= m_axis_dout_tdata(15 downto 0);
end tb;
| mit | a60c2dfee9712243eeba75a2a8ffb2d3 | 0.579833 | 4.241351 | false | false | false | false |
loa-org/loa-hdl | modules/motor_control/tb/symmetric_pwm_deadtime_tb.vhd | 2 | 1,746 | library ieee;
use ieee.std_logic_1164.all;
library work;
use work.motor_control_pkg.all;
use work.symmetric_pwm_deadtime_pkg.all;
entity symmetric_pwm_deadtime_tb is
end symmetric_pwm_deadtime_tb;
architecture behavior of symmetric_pwm_deadtime_tb is
constant WIDTH : positive := 8;
constant T_DEAD : natural := 10; -- Deadtime in clk cycles
signal clk : std_logic := '0';
signal clk_en : std_logic := '1';
signal reset : std_logic := '1';
signal value : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');
signal pwm : half_bridge_type;
signal center : std_logic; -- Center of the 'on'-periode
signal break : std_logic := '0';
begin
clk <= not clk after 10 NS; -- 50 Mhz clock
reset <= '1', '0' after 50 NS; -- erzeugt Resetsignal
tb : process
begin
wait until falling_edge(reset);
value <= x"7F";
wait for 100 US;
value <= x"01";
wait for 100 US;
value <= x"0a";
wait for 100 US;
value <= x"FE";
wait for 100 US;
value <= x"00";
wait for 100 US;
value <= x"FF";
wait for 100 US;
end process;
tb2 : process
begin
wait until falling_edge(reset);
wait for 40 US;
break <= '1';
wait for 30 US;
break <= '0';
wait for 150 US;
break <= '1';
wait for 30 US;
break <= '0';
end process;
uut : symmetric_pwm_deadtime
generic map (
WIDTH => WIDTH,
T_DEAD => T_DEAD)
port map (
pwm_p => pwm,
center_p => center,
clk_en_p => clk_en,
value_p => value,
break_p => break,
reset => reset,
clk => clk);
end;
| bsd-3-clause | dbcac7232305acb6b79036951e5493cc | 0.537801 | 3.437008 | false | false | false | false |
ErikAndren/SramTest-IS61LV25616AL | SramTestTop.vhd | 1 | 1,971 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Types.all;
use work.BcdPack.all;
entity SramTestTop is
generic (
Displays : positive := 8;
AddrW : positive := 18;
DataW : positive := 16
);
port (
Clk : in bit1;
RstN : in bit1;
--
Button0 : in bit1;
Button1 : in bit1;
--
Segments : out word(BcdSegs-1 downto 0);
Display : out word(Displays-1 downto 0);
--
D : inout word(DataW-1 downto 0);
AddrOut : out word(AddrW-1 downto 0);
CeN : out bit1;
OeN : out bit1;
WeN : out bit1;
UbN : out bit1;
LbN : out bit1;
--
flash_oe : out bit1;
flash_wr : out bit1;
flash_rd : out bit1
);
end entity;
architecture rtl of SramTestTop is
constant Freq : positive := 50000000;
--
signal SramAddr : word(AddrW-1 downto 0);
signal SramWrData : word(DataW-1 downto 0);
signal SramRdData : word(DataW-1 downto 0);
signal SramWe : bit1;
signal SramRe : bit1;
signal Data : word(bits(10**Displays)-1 downto 0);
begin
flash_oe <= '1';
flash_wr <= '1';
flash_rd <= '1';
BCDDisplay : entity work.BcdDisp
generic map (
Freq => Freq,
Displays => Displays
)
port map (
Clk => Clk,
RstN => RstN,
--
Data => Data,
--
Segments => Segments,
Display => Display
);
Data <= xt0(SramRdData, Data'length);
--Data <= xt0(SramAddr, Data'length);
SramCont : entity work.SramController
port map (
Clk => Clk,
RstN => RstN,
--
AddrIn => SramAddr,
WrData => SramWrData,
RdData => SramRdData,
We => SramWe,
Re => SramRe,
--
D => D,
AddrOut => AddrOut,
CeN => CeN,
OeN => OeN,
WeN => WeN,
UbN => UbN,
LbN => LbN
);
SramTest : entity work.SramControllerTestGen
port map (
Clk => Clk,
RstN => RstN,
--
Button0 => Button0,
Button1 => Button1,
--
Addr => SramAddr,
Data => SramWrData,
We => SramWe,
Re => SramRe
);
end architecture rtl; | gpl-2.0 | c8e68e6fef669e1659cfc72dc7738df6 | 0.598681 | 2.685286 | false | false | false | false |
loa-org/loa-hdl | modules/pwm/hdl/pwm.vhd | 2 | 2,242 | --!
--! Simple PWM generator
--!
--! PWM frequency (f_pwm) is: f_pwm = clk / ((2 ^ width) - 1)
--!
--! Example:
--! clk = 50 MHz
--! clk_en = constant '1' (no prescaler)
--! width = 8 => value = 0..255
--!
--! => f_pwm = 1/510ns = 0,1960784 MHz = 50/255 MHz
--!
--! Value (for width = 8):
--! 0 => output constant low
--! 1 => 254 cycle low, 1 cycle high
--! 127 => 50% (128 cycles low, 127 cycles high)
--! 128 => 50% (127 cycles low, 128 cycles high)
--! 254 => 1 cycle low, 254 cycles high
--! 255 => output constant high
--!
--! @author Fabian Greif
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm is
generic (
WIDTH : natural := 12); --! Number of bits used for the PWM (12bit => 0..4095)
port (
clk_en_p : in std_logic; --! clock enable
value_p : in std_logic_vector (width - 1 downto 0);
output_p : out std_logic;
reset : in std_logic; --! High active, Restarts the PWM period
clk : in std_logic
);
end pwm;
-- ----------------------------------------------------------------------------
architecture simple of pwm is
signal count : integer range 0 to ((2 ** WIDTH) - 2) := 0;
signal value_buf : std_logic_vector(width - 1 downto 0) := (others => '0');
begin
-- Counter
process
begin
wait until rising_edge(clk);
if reset = '1' then
-- Load new value and reset counter => restart periode
count <= 0;
value_buf <= value_p;
elsif clk_en_p = '1' then
-- counter
if count < ((2 ** WIDTH) - 2) then
count <= count + 1;
else
count <= 0;
-- Load new value from the shadow register (not active before
-- the next clock cycle)
value_buf <= value_p;
end if;
end if;
end process;
-- Generate Output
process
begin
wait until rising_edge(clk);
if reset = '1' then
output_p <= '0';
else
-- comparator for the output
if count >= to_integer(unsigned(value_buf)) then
output_p <= '0';
else
output_p <= '1';
end if;
end if;
end process;
end simple;
| bsd-3-clause | 68e197a7c389e0a462e826ca6c335026 | 0.510705 | 3.508607 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/csi2_rx/csi2_rx.srcs/sources_1/imports/mipi-csi-rx/csi_rx_top.vhd | 1 | 7,870 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--VHDL MIPI CSI-2 Rx designed for Xilinx 7-series FPGAs
--Copyright (C) 2016 David Shah
--Licensed under the MIT License
--This driver is designed for 4 lane links and has been tested with the Omnivison OV13850
--It supports resolutions up to 4k at 30fps (higher has not been tested but may work) with
--10-bit Bayer data (support for other output formats is not yet implemented). This is output
--in traditional parallel video format with a few tweaks
--For improved timing performance up to 4 pixels per clock can be output. For the ease of debayering blocks,
--the previous line's data; and whether the current line is even (BGBG) or odd (GRGR) is also output.
--At minimum you will need to provide it with suitable clocks from a PLL (the pixel clock input
--should in general either be phase locked to the master clock input to the camera or the CSI byte clock)
--and configure skew parameters and video port timings for your camera setup
--The primary testing platform is a Digilent Genesys 2 (Kintex-7 XC7K325T) with a
--custom FMC breakout board to connect two Firefly OV13850 modules.
--A previous version has also been tested on a ML605 Virtex-6 development board;
--however functioning support is not guaranteed
entity csi_rx_4lane is
generic (
--FPGA series to control SERDES/buffer generation
--either "VIRTEX6" or "7SERIES"
fpga_series : string := "7SERIES";
--Low-level PHY parameters
dphy_term_en : boolean := true; --Enable internal termination on all pairs
--Use these to invert channels if needed on your PCB
d0_invert : boolean := false;
d1_invert : boolean := false;
d2_invert : boolean := false;
d3_invert : boolean := false;
--These skew values are the delay settings for the IDELAYs on each lane
--Adjust these for optimum stability with your PCB layout and cameras
d0_skew : natural := 0;
d1_skew : natural := 0;
d2_skew : natural := 0;
d3_skew : natural := 0;
--Output port pixel timings (for included OV13850 config at 23.98fps with MCLK 24.399MHz and output clock 145Mz)
video_hlength : natural := 4041; --total visible and blanking pixels per line
video_vlength : natural := 2992; --total visible and blanking lines per frame
video_hsync_pol : boolean := true; --hsync polarity: true for positive sync, false for negative sync
video_hsync_len : natural := 48; --horizontal sync length in pixels
video_hbp_len : natural := 122; --horizontal back porch length (excluding sync)
video_h_visible : natural := 3840; --number of visible pixels per line
video_vsync_pol : boolean := true; --vsync polarity: true for positive sync, false for negative sync
video_vsync_len : natural := 3; --vertical sync length in lines
video_vbp_len : natural := 23; --vertical back porch length (excluding sync)
video_v_visible : natural := 2160; --number of visible lines per frame
pixels_per_clock : natural := 2; --Number of pixels per clock to output; 1, 2 or 4
--Set this to false if this is not the first CSI rx or other IDELAY using device in the system
generate_idelayctrl : boolean := false
);
port(
ref_clock_in : in std_logic; --IDELAY reference clock (nominally 200MHz)
pixel_clock_in : in std_logic; --Output pixel clock from PLL
byte_clock_out : out std_logic; --DSI byte clock output
enable : in std_logic; --system enable input
reset : in std_logic; --synchronous active high reset input
video_valid : out std_logic; --goes high when valid frames are being received
--DSI signals, signal 1 is P and signal 0 is N
dphy_clk : in std_logic_vector(1 downto 0);
dphy_d0 : in std_logic_vector(1 downto 0);
dphy_d1 : in std_logic_vector(1 downto 0);
dphy_d2 : in std_logic_vector(1 downto 0);
dphy_d3 : in std_logic_vector(1 downto 0);
--Pixel data output
video_hsync : out std_logic;
video_vsync : out std_logic;
video_den : out std_logic;
video_line_start : out std_logic; --like hsync but asserted for one clock period only and only for visible lines
video_odd_line : out std_logic; --LSB of y-coordinate for a downstream debayering block
video_data : out std_logic_vector(((10 * pixels_per_clock) - 1) downto 0); --LSW is leftmost pixel
video_prev_line_data : out std_logic_vector(((10 * pixels_per_clock) - 1) downto 0) --last line's data at this point, for a debayering block to use
);
end csi_rx_4lane;
architecture Behavioral of csi_rx_4lane is
signal csi_byte_clock : std_logic;
signal link_reset_out : std_logic;
signal wait_for_sync : std_logic;
signal packet_done : std_logic;
signal word_clock : std_logic;
signal word_data : std_logic_vector(31 downto 0);
signal word_valid : std_logic;
signal packet_payload : std_logic_vector(31 downto 0);
signal packet_payload_valid : std_logic;
signal csi_vsync : std_logic;
signal csi_in_frame, csi_in_line : std_logic;
signal unpack_data : std_logic_vector(39 downto 0);
signal unpack_data_valid : std_logic;
begin
link : entity work.csi_rx_4_lane_link
generic map(
fpga_series => fpga_series,
dphy_term_en => dphy_term_en,
d0_invert => d0_invert,
d1_invert => d1_invert,
d2_invert => d2_invert,
d3_invert => d3_invert,
d0_skew => d0_skew,
d1_skew => d1_skew,
d2_skew => d2_skew,
d3_skew => d3_skew,
generate_idelayctrl => generate_idelayctrl)
port map(
dphy_clk => dphy_clk,
dphy_d0 => dphy_d0,
dphy_d1 => dphy_d1,
dphy_d2 => dphy_d2,
dphy_d3 => dphy_d3,
ref_clock => ref_clock_in,
reset => reset,
enable => enable,
wait_for_sync => wait_for_sync,
packet_done => packet_done,
reset_out => link_reset_out,
word_clock => csi_byte_clock,
word_data => word_data,
word_valid => word_valid);
depacket : entity work.csi_rx_packet_handler
port map (
clock => csi_byte_clock,
reset => link_reset_out,
enable => enable,
data => word_data,
data_valid => word_valid,
sync_wait => wait_for_sync,
packet_done => packet_done,
payload_out => packet_payload,
payload_valid => packet_payload_valid,
vsync_out => csi_vsync,
in_frame => csi_in_frame,
in_line => csi_in_line);
unpack10 : entity work.csi_rx_10bit_unpack
port map (
clock => csi_byte_clock,
reset => link_reset_out,
enable => enable,
data_in => packet_payload,
din_valid => packet_payload_valid,
data_out => unpack_data,
dout_valid => unpack_data_valid);
vout : entity work.csi_rx_video_output
generic map (
video_hlength => video_hlength,
video_vlength => video_vlength,
video_hsync_pol => video_hsync_pol,
video_hsync_len => video_hsync_len,
video_hbp_len => video_hbp_len,
video_h_visible => video_h_visible,
video_vsync_pol => video_vsync_pol,
video_vsync_len => video_vsync_len,
video_vbp_len => video_vbp_len,
video_v_visible => video_v_visible,
pixels_per_clock => pixels_per_clock)
port map (
output_clock => pixel_clock_in,
csi_byte_clock => csi_byte_clock,
enable => enable,
reset => reset,
pixel_data_in => unpack_data,
pixel_data_valid => unpack_data_valid,
csi_in_frame => csi_in_frame,
csi_in_line => csi_in_line,
csi_vsync => csi_vsync,
video_valid => video_valid,
video_hsync => video_hsync,
video_vsync => video_vsync,
video_den => video_den,
video_line_start => video_line_start,
video_odd_line => video_odd_line,
video_data => video_data,
video_prev_line_data => video_prev_line_data
);
byte_clock_out <= csi_byte_clock;
end Behavioral;
| mit | 5dd1d278c5f0dd9bc0782dc4a5f132c0 | 0.664676 | 3.559475 | false | false | false | false |
loa-org/loa-hdl | modules/imotor/hdl/imotor_sender.vhd | 2 | 5,532 | -------------------------------------------------------------------------------
-- Title : iMotor Sender
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
--
-- Endianess: Little (as it is the default of ARM)
-- (Transmits lower byte first)
-- -------------------------------------------------------------------------------
-- Copyright (c) 2013 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.imotor_module_pkg.all;
-------------------------------------------------------------------------------
entity imotor_sender is
generic (
DATA_WORDS : positive := 2;
DATA_WIDTH : positive := 16;
START_BYTE : std_logic_vector(7 downto 0) := x"50";
END_BYTE : std_logic_vector(7 downto 0) := x"A0"
);
port (
-- parallel data in
data_in_p : in imotor_input_type(DATA_WORDS - 1 downto 0);
-- parallel data to UART TX
data_out_p : out std_logic_vector(7 downto 0);
start_out_p : out std_logic; -- start a transmission of data_in_p
busy_in_p : in std_logic; -- high when busy
start_in_p : in std_logic;
clk : in std_logic
);
end imotor_sender;
-------------------------------------------------------------------------------
architecture behavioural of imotor_sender is
type imotor_sender_state_type is (
IDLE, -- Idle state:
START, -- Sending start byte
DATA, -- Sending data bytes
STOP -- Sending stop byte
);
type imotor_sender_type is record
state : imotor_sender_state_type;
data_out : std_logic_vector(7 downto 0);
start : std_logic;
byte_count : integer range 0 to DATA_WORDS * 2; -- ToDo: Make dependent
-- from data width
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : imotor_sender_type := (
state => IDLE,
start => '0',
data_out => (others => '0'),
byte_count => 0
);
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-- None here. If any: in package
begin -- architecture behavourial
----------------------------------------------------------------------------
-- Connections between ports and signals
----------------------------------------------------------------------------
data_out_p <= r.data_out;
start_out_p <= r.start;
----------------------------------------------------------------------------
-- Sequential part of finite state machine (FSM)
----------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
----------------------------------------------------------------------------
-- Combinatorial part of FSM
----------------------------------------------------------------------------
comb_proc : process(busy_in_p, data_in_p(0)(7 downto 0), r, start_in_p)
variable v : imotor_sender_type;
begin
v := r;
case r.state is
when IDLE =>
if start_in_p = '1' then
-- Send Start Byte
v.state := START;
v.start := '1';
v.data_out := START_BYTE;
end if;
when START =>
v.start := '0';
if busy_in_p = '0' then
-- Send Data
v.state := DATA;
v.start := '1';
v.byte_count := 0;
if v.byte_count mod 2 = 0 then
v.data_out := data_in_p(v.byte_count / 2)(7 downto 0);
else
v.data_out := data_in_p(v.byte_count / 2)(15 downto 8);
end if;
end if;
when DATA =>
v.start := '0';
if busy_in_p = '0' then
v.byte_count := v.byte_count + 1;
v.start := '1';
if v.byte_count = DATA_WORDS * 2 then
v.state := STOP;
v.data_out := END_BYTE;
elsif v.byte_count mod 2 = 0 then
v.data_out := data_in_p(v.byte_count / 2)(7 downto 0);
else
v.data_out := data_in_p(v.byte_count / 2)(15 downto 8);
end if;
end if;
when STOP =>
v.start := '0';
if busy_in_p = '0' then
-- Do not send more data
v.state := IDLE;
end if;
end case;
rin <= v;
end process comb_proc;
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- None.
end behavioural;
| bsd-3-clause | 512aa715e732e2f50d43be0ab04d06c0 | 0.347795 | 5.093923 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_zed_hdmi_0_0/system_zed_hdmi_0_0_sim_netlist.vhdl | 1 | 804,429 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 00:41:34 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_zed_hdmi_0_0 -prefix
-- system_zed_hdmi_0_0_ system_zed_hdmi_0_0_sim_netlist.vhdl
-- Design : system_zed_hdmi_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zed_hdmi_0_0_i2c_sender is
port (
hdmi_sda : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
clk_100 : in STD_LOGIC
);
end system_zed_hdmi_0_0_i2c_sender;
architecture STRUCTURE of system_zed_hdmi_0_0_i2c_sender is
signal address : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \address[0]_i_1_n_0\ : STD_LOGIC;
signal \address[1]_i_1_n_0\ : STD_LOGIC;
signal \address[2]_i_1_n_0\ : STD_LOGIC;
signal \address[3]_i_1_n_0\ : STD_LOGIC;
signal \address[3]_i_2_n_0\ : STD_LOGIC;
signal \address[4]_i_1_n_0\ : STD_LOGIC;
signal \address[5]_i_1_n_0\ : STD_LOGIC;
signal \address[5]_i_2_n_0\ : STD_LOGIC;
signal \address[5]_i_3_n_0\ : STD_LOGIC;
signal \address[5]_i_4_n_0\ : STD_LOGIC;
signal \address[5]_i_5_n_0\ : STD_LOGIC;
signal \address[5]_i_6_n_0\ : STD_LOGIC;
signal \address[5]_i_7_n_0\ : STD_LOGIC;
signal busy_sr : STD_LOGIC;
signal \busy_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[11]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[1]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[20]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[21]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[23]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[24]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[25]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[26]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[28]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[28]_i_2_n_0\ : STD_LOGIC;
signal \busy_sr[2]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[0]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[20]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[9]\ : STD_LOGIC;
signal clk_first_quarter : STD_LOGIC_VECTOR ( 28 to 28 );
signal \clk_first_quarter[28]_i_1_n_0\ : STD_LOGIC;
signal clk_last_quarter : STD_LOGIC_VECTOR ( 28 downto 1 );
signal \clk_last_quarter[2]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[0]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[0]_i_2_n_0\ : STD_LOGIC;
signal \data_sr_reg_n_0_[0]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[20]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[9]\ : STD_LOGIC;
signal divider : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \divider[0]_i_1_n_0\ : STD_LOGIC;
signal \divider[1]_i_1_n_0\ : STD_LOGIC;
signal \divider[2]_i_1_n_0\ : STD_LOGIC;
signal \divider[3]_i_1_n_0\ : STD_LOGIC;
signal \divider[4]_i_1_n_0\ : STD_LOGIC;
signal \divider[5]_i_1_n_0\ : STD_LOGIC;
signal \divider[5]_i_2_n_0\ : STD_LOGIC;
signal \divider[6]_i_1_n_0\ : STD_LOGIC;
signal \divider[7]_i_1_n_0\ : STD_LOGIC;
signal \divider[7]_i_2_n_0\ : STD_LOGIC;
signal \divider[7]_i_3_n_0\ : STD_LOGIC;
signal finished_i_1_n_0 : STD_LOGIC;
signal finished_reg_n_0 : STD_LOGIC;
signal \initial_pause[5]_i_2_n_0\ : STD_LOGIC;
signal \initial_pause[7]_i_1_n_0\ : STD_LOGIC;
signal \initial_pause[7]_i_3_n_0\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[0]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[1]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[2]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[3]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[4]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[5]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[6]\ : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_1_in : STD_LOGIC;
signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_2_in : STD_LOGIC_VECTOR ( 18 downto 2 );
signal reg_value_reg_n_10 : STD_LOGIC;
signal reg_value_reg_n_11 : STD_LOGIC;
signal reg_value_reg_n_12 : STD_LOGIC;
signal reg_value_reg_n_13 : STD_LOGIC;
signal reg_value_reg_n_14 : STD_LOGIC;
signal reg_value_reg_n_15 : STD_LOGIC;
signal reg_value_reg_n_8 : STD_LOGIC;
signal reg_value_reg_n_9 : STD_LOGIC;
signal \tristate_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[28]_inv_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\ : STD_LOGIC;
signal \tristate_sr_reg_gate__0_n_0\ : STD_LOGIC;
signal \tristate_sr_reg_gate__1_n_0\ : STD_LOGIC;
signal tristate_sr_reg_gate_n_0 : STD_LOGIC;
signal \tristate_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \tristate_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \tristate_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \tristate_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \tristate_sr_reg_n_0_[9]\ : STD_LOGIC;
signal tristate_sr_reg_r_0_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_1_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_2_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_3_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_4_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_5_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_6_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_n_0 : STD_LOGIC;
signal NLW_reg_value_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_reg_value_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_reg_value_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \address[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \address[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \address[3]_i_2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \address[5]_i_4\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \address[5]_i_6\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \busy_sr[5]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \busy_sr[6]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \data_sr[0]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \data_sr[11]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[12]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[13]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[14]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[15]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_sr[16]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[17]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[18]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[2]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[3]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_sr[4]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \data_sr[5]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \data_sr[6]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \data_sr[7]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[8]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \data_sr[9]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \divider[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \divider[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \initial_pause[0]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \initial_pause[1]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \initial_pause[2]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \initial_pause[5]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \initial_pause[6]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \initial_pause[7]_i_2\ : label is "soft_lutpair5";
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of reg_value_reg : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of reg_value_reg : label is "p0_d16";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of reg_value_reg : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of reg_value_reg : label is 1024;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of reg_value_reg : label is "reg_value";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of reg_value_reg : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of reg_value_reg : label is 1023;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of reg_value_reg : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of reg_value_reg : label is 15;
attribute srl_bus_name : string;
attribute srl_bus_name of \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg ";
attribute srl_name : string;
attribute srl_name of \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4 ";
attribute srl_bus_name of \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg ";
attribute srl_name of \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5 ";
attribute srl_bus_name of \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg ";
attribute srl_name of \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4 ";
attribute SOFT_HLUTNM of \tristate_sr_reg_gate__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \tristate_sr_reg_gate__1\ : label is "soft_lutpair16";
begin
\address[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => p_0_in,
I1 => \address[5]_i_5_n_0\,
I2 => \address[5]_i_3_n_0\,
I3 => address(0),
O => \address[0]_i_1_n_0\
);
\address[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00080800"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => address(0),
I4 => address(1),
O => \address[1]_i_1_n_0\
);
\address[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008080808000000"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => address(1),
I4 => address(0),
I5 => address(2),
O => \address[2]_i_1_n_0\
);
\address[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"08000008"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => \address[3]_i_2_n_0\,
I4 => address(3),
O => \address[3]_i_1_n_0\
);
\address[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => address(1),
I1 => address(0),
I2 => address(2),
O => \address[3]_i_2_n_0\
);
\address[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"08000008"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => \address[5]_i_6_n_0\,
I4 => address(4),
O => \address[4]_i_1_n_0\
);
\address[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000200000"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => finished_reg_n_0,
I2 => p_1_in,
I3 => \address[5]_i_4_n_0\,
I4 => divider(7),
I5 => p_0_in,
O => \address[5]_i_1_n_0\
);
\address[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0808000800000800"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => address(4),
I4 => \address[5]_i_6_n_0\,
I5 => address(5),
O => \address[5]_i_2_n_0\
);
\address[5]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF7FFF"
)
port map (
I0 => \p_0_in__0\(2),
I1 => \p_0_in__0\(3),
I2 => \p_0_in__0\(0),
I3 => \p_0_in__0\(1),
I4 => \address[5]_i_7_n_0\,
O => \address[5]_i_3_n_0\
);
\address[5]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \divider[7]_i_3_n_0\,
I1 => divider(6),
O => \address[5]_i_4_n_0\
);
\address[5]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00400000"
)
port map (
I0 => finished_reg_n_0,
I1 => p_1_in,
I2 => divider(6),
I3 => \divider[7]_i_3_n_0\,
I4 => divider(7),
O => \address[5]_i_5_n_0\
);
\address[5]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => address(2),
I1 => address(0),
I2 => address(1),
I3 => address(3),
O => \address[5]_i_6_n_0\
);
\address[5]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \p_0_in__0\(5),
I1 => \p_0_in__0\(4),
I2 => \p_0_in__0\(7),
I3 => \p_0_in__0\(6),
O => \address[5]_i_7_n_0\
);
\address_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[0]_i_1_n_0\,
Q => address(0),
R => '0'
);
\address_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[1]_i_1_n_0\,
Q => address(1),
R => '0'
);
\address_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[2]_i_1_n_0\,
Q => address(2),
R => '0'
);
\address_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[3]_i_1_n_0\,
Q => address(3),
R => '0'
);
\address_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[4]_i_1_n_0\,
Q => address(4),
R => '0'
);
\address_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[5]_i_2_n_0\,
Q => address(5),
R => '0'
);
\busy_sr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FF200000"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => finished_reg_n_0,
I2 => p_1_in,
I3 => p_0_in,
I4 => divider(7),
I5 => \address[5]_i_4_n_0\,
O => busy_sr
);
\busy_sr[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[9]\,
O => \busy_sr[10]_i_1_n_0\
);
\busy_sr[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[10]\,
O => \busy_sr[11]_i_1_n_0\
);
\busy_sr[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[11]\,
O => \busy_sr[12]_i_1_n_0\
);
\busy_sr[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[12]\,
O => \busy_sr[13]_i_1_n_0\
);
\busy_sr[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[13]\,
O => \busy_sr[14]_i_1_n_0\
);
\busy_sr[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[14]\,
O => \busy_sr[15]_i_1_n_0\
);
\busy_sr[16]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[15]\,
O => \busy_sr[16]_i_1_n_0\
);
\busy_sr[17]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[16]\,
O => \busy_sr[17]_i_1_n_0\
);
\busy_sr[18]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[17]\,
O => \busy_sr[18]_i_1_n_0\
);
\busy_sr[19]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[18]\,
O => \busy_sr[19]_i_1_n_0\
);
\busy_sr[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[0]\,
O => \busy_sr[1]_i_1_n_0\
);
\busy_sr[20]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[19]\,
O => \busy_sr[20]_i_1_n_0\
);
\busy_sr[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[20]\,
O => \busy_sr[21]_i_1_n_0\
);
\busy_sr[22]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[21]\,
O => \busy_sr[22]_i_1_n_0\
);
\busy_sr[23]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[22]\,
O => \busy_sr[23]_i_1_n_0\
);
\busy_sr[24]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[23]\,
O => \busy_sr[24]_i_1_n_0\
);
\busy_sr[25]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[24]\,
O => \busy_sr[25]_i_1_n_0\
);
\busy_sr[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[25]\,
O => \busy_sr[26]_i_1_n_0\
);
\busy_sr[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[26]\,
O => \busy_sr[27]_i_1_n_0\
);
\busy_sr[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000040000000000"
)
port map (
I0 => \address[5]_i_4_n_0\,
I1 => divider(7),
I2 => p_0_in,
I3 => p_1_in,
I4 => finished_reg_n_0,
I5 => \address[5]_i_3_n_0\,
O => \busy_sr[28]_i_1_n_0\
);
\busy_sr[28]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[27]\,
O => \busy_sr[28]_i_2_n_0\
);
\busy_sr[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[1]\,
O => \busy_sr[2]_i_1_n_0\
);
\busy_sr[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[2]\,
O => \busy_sr[3]_i_1_n_0\
);
\busy_sr[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[3]\,
O => \busy_sr[4]_i_1_n_0\
);
\busy_sr[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[4]\,
O => \busy_sr[5]_i_1_n_0\
);
\busy_sr[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[5]\,
O => \busy_sr[6]_i_1_n_0\
);
\busy_sr[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[6]\,
O => \busy_sr[7]_i_1_n_0\
);
\busy_sr[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[7]\,
O => \busy_sr[8]_i_1_n_0\
);
\busy_sr[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[8]\,
O => \busy_sr[9]_i_1_n_0\
);
\busy_sr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \address[5]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[0]\,
R => '0'
);
\busy_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[10]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[10]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[11]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[11]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[11]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[12]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[12]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[12]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[13]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[13]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[13]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[14]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[14]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[14]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[15]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[15]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[15]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[16]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[16]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[16]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[17]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[17]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[17]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[18]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[18]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[18]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[19]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[19]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[1]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[1]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[20]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[20]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[20]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[21]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[21]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[21]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[22]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[22]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[22]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[23]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[23]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[23]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[24]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[24]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[24]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[25]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[25]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[25]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[26]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[26]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[26]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[27]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[27]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[27]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[28]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[28]_i_2_n_0\,
Q => p_0_in,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[2]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[2]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[3]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[3]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[4]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[4]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[5]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[5]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[6]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[6]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[7]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[7]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[8]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[8]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[9]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[9]\,
S => \busy_sr[28]_i_1_n_0\
);
\clk_first_quarter[28]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => clk_last_quarter(28),
O => \clk_first_quarter[28]_i_1_n_0\
);
\clk_first_quarter_reg[28]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \clk_first_quarter[28]_i_1_n_0\,
Q => clk_first_quarter(28),
S => \busy_sr[28]_i_1_n_0\
);
\clk_last_quarter[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000200000"
)
port map (
I0 => p_1_in,
I1 => finished_reg_n_0,
I2 => \address[5]_i_3_n_0\,
I3 => p_0_in,
I4 => divider(7),
I5 => \address[5]_i_4_n_0\,
O => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(9),
Q => clk_last_quarter(10),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(10),
Q => clk_last_quarter(11),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(11),
Q => clk_last_quarter(12),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(12),
Q => clk_last_quarter(13),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(13),
Q => clk_last_quarter(14),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(14),
Q => clk_last_quarter(15),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(15),
Q => clk_last_quarter(16),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(16),
Q => clk_last_quarter(17),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(17),
Q => clk_last_quarter(18),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(18),
Q => clk_last_quarter(19),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \tristate_sr[19]_i_1_n_0\,
Q => clk_last_quarter(1),
R => '0'
);
\clk_last_quarter_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(19),
Q => clk_last_quarter(20),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(20),
Q => clk_last_quarter(21),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(21),
Q => clk_last_quarter(22),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(22),
Q => clk_last_quarter(23),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(23),
Q => clk_last_quarter(24),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(24),
Q => clk_last_quarter(25),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(25),
Q => clk_last_quarter(26),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(26),
Q => clk_last_quarter(27),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(27),
Q => clk_last_quarter(28),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(1),
Q => clk_last_quarter(2),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(2),
Q => clk_last_quarter(3),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(3),
Q => clk_last_quarter(4),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(4),
Q => clk_last_quarter(5),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(5),
Q => clk_last_quarter(6),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(6),
Q => clk_last_quarter(7),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(7),
Q => clk_last_quarter(8),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(8),
Q => clk_last_quarter(9),
R => \clk_last_quarter[2]_i_1_n_0\
);
\data_sr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EAEACAEAEAEAEAEA"
)
port map (
I0 => \data_sr_reg_n_0_[0]\,
I1 => p_0_in,
I2 => \data_sr[0]_i_2_n_0\,
I3 => p_1_in,
I4 => finished_reg_n_0,
I5 => \address[5]_i_3_n_0\,
O => \data_sr[0]_i_1_n_0\
);
\data_sr[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => divider(7),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(6),
O => \data_sr[0]_i_2_n_0\
);
\data_sr[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[10]\,
I1 => p_0_in,
I2 => \p_0_in__0\(0),
O => p_2_in(11)
);
\data_sr[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[11]\,
I1 => p_0_in,
I2 => \p_0_in__0\(1),
O => p_2_in(12)
);
\data_sr[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[12]\,
I1 => p_0_in,
I2 => \p_0_in__0\(2),
O => p_2_in(13)
);
\data_sr[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[13]\,
I1 => p_0_in,
I2 => \p_0_in__0\(3),
O => p_2_in(14)
);
\data_sr[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[14]\,
I1 => p_0_in,
I2 => \p_0_in__0\(4),
O => p_2_in(15)
);
\data_sr[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[15]\,
I1 => p_0_in,
I2 => \p_0_in__0\(5),
O => p_2_in(16)
);
\data_sr[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[16]\,
I1 => p_0_in,
I2 => \p_0_in__0\(6),
O => p_2_in(17)
);
\data_sr[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[17]\,
I1 => p_0_in,
I2 => \p_0_in__0\(7),
O => p_2_in(18)
);
\data_sr[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[1]\,
I1 => p_0_in,
I2 => reg_value_reg_n_15,
O => p_2_in(2)
);
\data_sr[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[2]\,
I1 => p_0_in,
I2 => reg_value_reg_n_14,
O => p_2_in(3)
);
\data_sr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[3]\,
I1 => p_0_in,
I2 => reg_value_reg_n_13,
O => p_2_in(4)
);
\data_sr[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[4]\,
I1 => p_0_in,
I2 => reg_value_reg_n_12,
O => p_2_in(5)
);
\data_sr[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[5]\,
I1 => p_0_in,
I2 => reg_value_reg_n_11,
O => p_2_in(6)
);
\data_sr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[6]\,
I1 => p_0_in,
I2 => reg_value_reg_n_10,
O => p_2_in(7)
);
\data_sr[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[7]\,
I1 => p_0_in,
I2 => reg_value_reg_n_9,
O => p_2_in(8)
);
\data_sr[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[8]\,
I1 => p_0_in,
I2 => reg_value_reg_n_8,
O => p_2_in(9)
);
\data_sr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => '1',
D => \data_sr[0]_i_1_n_0\,
Q => \data_sr_reg_n_0_[0]\,
R => '0'
);
\data_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[9]\,
Q => \data_sr_reg_n_0_[10]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(11),
Q => \data_sr_reg_n_0_[11]\,
R => '0'
);
\data_sr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(12),
Q => \data_sr_reg_n_0_[12]\,
R => '0'
);
\data_sr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(13),
Q => \data_sr_reg_n_0_[13]\,
R => '0'
);
\data_sr_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(14),
Q => \data_sr_reg_n_0_[14]\,
R => '0'
);
\data_sr_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(15),
Q => \data_sr_reg_n_0_[15]\,
R => '0'
);
\data_sr_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(16),
Q => \data_sr_reg_n_0_[16]\,
R => '0'
);
\data_sr_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(17),
Q => \data_sr_reg_n_0_[17]\,
R => '0'
);
\data_sr_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(18),
Q => \data_sr_reg_n_0_[18]\,
R => '0'
);
\data_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[18]\,
Q => \data_sr_reg_n_0_[19]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[0]\,
Q => \data_sr_reg_n_0_[1]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[19]\,
Q => \data_sr_reg_n_0_[20]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[21]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[20]\,
Q => \data_sr_reg_n_0_[21]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[21]\,
Q => \data_sr_reg_n_0_[22]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[22]\,
Q => \data_sr_reg_n_0_[23]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[24]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[23]\,
Q => \data_sr_reg_n_0_[24]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[25]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[24]\,
Q => \data_sr_reg_n_0_[25]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[26]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[25]\,
Q => \data_sr_reg_n_0_[26]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[26]\,
Q => \data_sr_reg_n_0_[27]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[27]\,
Q => \data_sr_reg_n_0_[28]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(2),
Q => \data_sr_reg_n_0_[2]\,
R => '0'
);
\data_sr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(3),
Q => \data_sr_reg_n_0_[3]\,
R => '0'
);
\data_sr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(4),
Q => \data_sr_reg_n_0_[4]\,
R => '0'
);
\data_sr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(5),
Q => \data_sr_reg_n_0_[5]\,
R => '0'
);
\data_sr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(6),
Q => \data_sr_reg_n_0_[6]\,
R => '0'
);
\data_sr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(7),
Q => \data_sr_reg_n_0_[7]\,
R => '0'
);
\data_sr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(8),
Q => \data_sr_reg_n_0_[8]\,
R => '0'
);
\data_sr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(9),
Q => \data_sr_reg_n_0_[9]\,
R => '0'
);
\divider[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_0_in,
I1 => p_1_in,
I2 => finished_reg_n_0,
I3 => divider(0),
O => \divider[0]_i_1_n_0\
);
\divider[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00F4F400"
)
port map (
I0 => finished_reg_n_0,
I1 => p_1_in,
I2 => p_0_in,
I3 => divider(0),
I4 => divider(1),
O => \divider[1]_i_1_n_0\
);
\divider[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00F4F4F4F4000000"
)
port map (
I0 => finished_reg_n_0,
I1 => p_1_in,
I2 => p_0_in,
I3 => divider(1),
I4 => divider(0),
I5 => divider(2),
O => \divider[2]_i_1_n_0\
);
\divider[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2AAA8000"
)
port map (
I0 => \divider[7]_i_1_n_0\,
I1 => divider(2),
I2 => divider(0),
I3 => divider(1),
I4 => divider(3),
O => \divider[3]_i_1_n_0\
);
\divider[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFF000080000000"
)
port map (
I0 => divider(2),
I1 => divider(0),
I2 => divider(1),
I3 => divider(3),
I4 => \divider[7]_i_1_n_0\,
I5 => divider(4),
O => \divider[4]_i_1_n_0\
);
\divider[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88A84454"
)
port map (
I0 => \divider[5]_i_2_n_0\,
I1 => p_0_in,
I2 => p_1_in,
I3 => finished_reg_n_0,
I4 => divider(5),
O => \divider[5]_i_1_n_0\
);
\divider[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => divider(3),
I1 => divider(1),
I2 => divider(0),
I3 => divider(2),
I4 => divider(4),
O => \divider[5]_i_2_n_0\
);
\divider[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88A84454"
)
port map (
I0 => \divider[7]_i_3_n_0\,
I1 => p_0_in,
I2 => p_1_in,
I3 => finished_reg_n_0,
I4 => divider(6),
O => \divider[6]_i_1_n_0\
);
\divider[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => finished_reg_n_0,
I1 => p_1_in,
I2 => p_0_in,
O => \divider[7]_i_1_n_0\
);
\divider[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B0B0BBB040404440"
)
port map (
I0 => \divider[7]_i_3_n_0\,
I1 => divider(6),
I2 => p_0_in,
I3 => p_1_in,
I4 => finished_reg_n_0,
I5 => divider(7),
O => \divider[7]_i_2_n_0\
);
\divider[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => divider(4),
I1 => divider(2),
I2 => divider(0),
I3 => divider(1),
I4 => divider(3),
I5 => divider(5),
O => \divider[7]_i_3_n_0\
);
\divider_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[0]_i_1_n_0\,
Q => divider(0),
R => '0'
);
\divider_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[1]_i_1_n_0\,
Q => divider(1),
R => '0'
);
\divider_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[2]_i_1_n_0\,
Q => divider(2),
R => '0'
);
\divider_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[3]_i_1_n_0\,
Q => divider(3),
R => '0'
);
\divider_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[4]_i_1_n_0\,
Q => divider(4),
R => '0'
);
\divider_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[5]_i_1_n_0\,
Q => divider(5),
R => '0'
);
\divider_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[6]_i_1_n_0\,
Q => divider(6),
R => '0'
);
\divider_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[7]_i_2_n_0\,
Q => divider(7),
R => '0'
);
finished_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00000020"
)
port map (
I0 => p_1_in,
I1 => \address[5]_i_4_n_0\,
I2 => divider(7),
I3 => \address[5]_i_3_n_0\,
I4 => p_0_in,
I5 => finished_reg_n_0,
O => finished_i_1_n_0
);
finished_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => '1',
D => finished_i_1_n_0,
Q => finished_reg_n_0,
R => '0'
);
hdmi_scl_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => clk_first_quarter(28),
I1 => divider(7),
O => hdmi_scl
);
hdmi_sda_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \data_sr_reg_n_0_[28]\,
I1 => \tristate_sr_reg[28]_inv_n_0\,
O => hdmi_sda
);
\initial_pause[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => p_1_in,
I1 => p_0_in,
I2 => \initial_pause_reg_n_0_[0]\,
O => \p_1_in__0\(0)
);
\initial_pause[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0110"
)
port map (
I0 => p_0_in,
I1 => p_1_in,
I2 => \initial_pause_reg_n_0_[0]\,
I3 => \initial_pause_reg_n_0_[1]\,
O => \p_1_in__0\(1)
);
\initial_pause[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00070008"
)
port map (
I0 => \initial_pause_reg_n_0_[0]\,
I1 => \initial_pause_reg_n_0_[1]\,
I2 => p_1_in,
I3 => p_0_in,
I4 => \initial_pause_reg_n_0_[2]\,
O => \p_1_in__0\(2)
);
\initial_pause[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000007F00000080"
)
port map (
I0 => \initial_pause_reg_n_0_[1]\,
I1 => \initial_pause_reg_n_0_[0]\,
I2 => \initial_pause_reg_n_0_[2]\,
I3 => p_1_in,
I4 => p_0_in,
I5 => \initial_pause_reg_n_0_[3]\,
O => \p_1_in__0\(3)
);
\initial_pause[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFF000080000000"
)
port map (
I0 => \initial_pause_reg_n_0_[2]\,
I1 => \initial_pause_reg_n_0_[0]\,
I2 => \initial_pause_reg_n_0_[1]\,
I3 => \initial_pause_reg_n_0_[3]\,
I4 => \initial_pause[7]_i_1_n_0\,
I5 => \initial_pause_reg_n_0_[4]\,
O => \p_1_in__0\(4)
);
\initial_pause[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0201"
)
port map (
I0 => \initial_pause[5]_i_2_n_0\,
I1 => p_1_in,
I2 => p_0_in,
I3 => \initial_pause_reg_n_0_[5]\,
O => \p_1_in__0\(5)
);
\initial_pause[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \initial_pause_reg_n_0_[3]\,
I1 => \initial_pause_reg_n_0_[1]\,
I2 => \initial_pause_reg_n_0_[0]\,
I3 => \initial_pause_reg_n_0_[2]\,
I4 => \initial_pause_reg_n_0_[4]\,
O => \initial_pause[5]_i_2_n_0\
);
\initial_pause[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0201"
)
port map (
I0 => \initial_pause[7]_i_3_n_0\,
I1 => p_1_in,
I2 => p_0_in,
I3 => \initial_pause_reg_n_0_[6]\,
O => \p_1_in__0\(6)
);
\initial_pause[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in,
I1 => p_1_in,
O => \initial_pause[7]_i_1_n_0\
);
\initial_pause[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \initial_pause_reg_n_0_[6]\,
I1 => p_0_in,
I2 => p_1_in,
I3 => \initial_pause[7]_i_3_n_0\,
O => \p_1_in__0\(7)
);
\initial_pause[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \initial_pause_reg_n_0_[4]\,
I1 => \initial_pause_reg_n_0_[2]\,
I2 => \initial_pause_reg_n_0_[0]\,
I3 => \initial_pause_reg_n_0_[1]\,
I4 => \initial_pause_reg_n_0_[3]\,
I5 => \initial_pause_reg_n_0_[5]\,
O => \initial_pause[7]_i_3_n_0\
);
\initial_pause_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(0),
Q => \initial_pause_reg_n_0_[0]\,
R => '0'
);
\initial_pause_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(1),
Q => \initial_pause_reg_n_0_[1]\,
R => '0'
);
\initial_pause_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(2),
Q => \initial_pause_reg_n_0_[2]\,
R => '0'
);
\initial_pause_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(3),
Q => \initial_pause_reg_n_0_[3]\,
R => '0'
);
\initial_pause_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(4),
Q => \initial_pause_reg_n_0_[4]\,
R => '0'
);
\initial_pause_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(5),
Q => \initial_pause_reg_n_0_[5]\,
R => '0'
);
\initial_pause_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(6),
Q => \initial_pause_reg_n_0_[6]\,
R => '0'
);
\initial_pause_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(7),
Q => p_1_in,
R => '0'
);
reg_value_reg: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"AF04D03C1700163748101506F9005512E0D0A3A4A2A49D619C309AE098034110",
INIT_01 => X"2524241F23AD220421DC201D1F1B1E1C1D001C001BAD1A04193418E740004C04",
INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFF2F772E1B2D7C2C082BAD2A042900280027352601",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(13 downto 10) => B"0000",
ADDRARDADDR(9 downto 4) => address(5 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 0) => B"11111111111111",
CLKARDCLK => clk_100,
CLKBWRCLK => '0',
DIADI(15 downto 0) => B"1111111111111111",
DIBDI(15 downto 0) => B"1111111111111111",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"11",
DOADO(15 downto 8) => \p_0_in__0\(7 downto 0),
DOADO(7) => reg_value_reg_n_8,
DOADO(6) => reg_value_reg_n_9,
DOADO(5) => reg_value_reg_n_10,
DOADO(4) => reg_value_reg_n_11,
DOADO(3) => reg_value_reg_n_12,
DOADO(2) => reg_value_reg_n_13,
DOADO(1) => reg_value_reg_n_14,
DOADO(0) => reg_value_reg_n_15,
DOBDO(15 downto 0) => NLW_reg_value_reg_DOBDO_UNCONNECTED(15 downto 0),
DOPADOP(1 downto 0) => NLW_reg_value_reg_DOPADOP_UNCONNECTED(1 downto 0),
DOPBDOP(1 downto 0) => NLW_reg_value_reg_DOPBDOP_UNCONNECTED(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"00",
WEBWE(3 downto 0) => B"0000"
);
\tristate_sr[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
O => \tristate_sr[19]_i_1_n_0\
);
\tristate_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg_n_0_[9]\,
Q => \tristate_sr_reg_n_0_[10]\,
S => \address[5]_i_1_n_0\
);
\tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '0',
CE => \tristate_sr[19]_i_1_n_0\,
CLK => clk_100,
D => \tristate_sr_reg_n_0_[10]\,
Q => \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\
);
\tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\,
Q => \tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
R => '0'
);
\tristate_sr_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg_gate__0_n_0\,
Q => \tristate_sr_reg_n_0_[18]\,
R => \address[5]_i_1_n_0\
);
\tristate_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg_n_0_[18]\,
Q => \tristate_sr_reg_n_0_[19]\,
S => \address[5]_i_1_n_0\
);
\tristate_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => '0',
Q => \tristate_sr_reg_n_0_[1]\,
S => \address[5]_i_1_n_0\
);
\tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '0',
CE => \tristate_sr[19]_i_1_n_0\,
CLK => clk_100,
D => \tristate_sr_reg_n_0_[19]\,
Q => \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\
);
\tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
Q => \tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6_n_0\,
R => '0'
);
\tristate_sr_reg[28]_inv\: unisim.vcomponents.FDSE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_gate_n_0,
Q => \tristate_sr_reg[28]_inv_n_0\,
S => \address[5]_i_1_n_0\
);
\tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '0',
CE => \tristate_sr[19]_i_1_n_0\,
CLK => clk_100,
D => \tristate_sr_reg_n_0_[1]\,
Q => \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\
);
\tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\,
Q => \tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
R => '0'
);
\tristate_sr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg_gate__1_n_0\,
Q => \tristate_sr_reg_n_0_[9]\,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_gate: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6_n_0\,
I1 => tristate_sr_reg_r_6_n_0,
O => tristate_sr_reg_gate_n_0
);
\tristate_sr_reg_gate__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
I1 => tristate_sr_reg_r_5_n_0,
O => \tristate_sr_reg_gate__0_n_0\
);
\tristate_sr_reg_gate__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
I1 => tristate_sr_reg_r_5_n_0,
O => \tristate_sr_reg_gate__1_n_0\
);
tristate_sr_reg_r: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => '1',
Q => tristate_sr_reg_r_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_0: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_n_0,
Q => tristate_sr_reg_r_0_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_1: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_0_n_0,
Q => tristate_sr_reg_r_1_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_2: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_1_n_0,
Q => tristate_sr_reg_r_2_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_3: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_2_n_0,
Q => tristate_sr_reg_r_3_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_4: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_3_n_0,
Q => tristate_sr_reg_r_4_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_5: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_4_n_0,
Q => tristate_sr_reg_r_5_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_6: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_5_n_0,
Q => tristate_sr_reg_r_6_n_0,
R => \address[5]_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zed_hdmi_0_0_zed_hdmi is
port (
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_de : out STD_LOGIC;
DI : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[31]_0\ : out STD_LOGIC;
\cr_int_reg[31]_1\ : out STD_LOGIC;
O : out STD_LOGIC_VECTOR ( 1 downto 0 );
\cb_int_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[27]_0\ : out STD_LOGIC;
\cr_int_reg[27]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[31]_2\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\cr_int_reg[7]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\cr_int_reg[3]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[3]_2\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\cr_int_reg[27]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[7]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[15]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[19]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[23]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[23]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\y_int_reg[23]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[3]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[23]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\y_int_reg[23]_2\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\y_int_reg[19]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\y_int_reg[15]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cb_int_reg[3]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cb_int_reg[3]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cb_int_reg[3]_3\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cb_int_reg[27]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cb_int_reg[15]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[15]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[3]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[19]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[23]_3\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[15]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
hdmi_sda : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 7 downto 0 );
hdmi_scl : out STD_LOGIC;
clk_x2 : in STD_LOGIC;
active : in STD_LOGIC;
clk_100 : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
\rgb888[8]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[0]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[13]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[13]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[12]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[12]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_5\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_6\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_7\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_8\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[0]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[0]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_11\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_12\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_13\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_5\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_14\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_15\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_16\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_17\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_18\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_19\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\rgb888[14]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_20\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_21\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\rgb888[0]_7\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[14]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[1]\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
\rgb888[14]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_22\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_23\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_24\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_25\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_26\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_27\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_28\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_29\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_30\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_31\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\rgb888[0]_8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_32\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[0]_9\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
clk : in STD_LOGIC
);
end system_zed_hdmi_0_0_zed_hdmi;
architecture STRUCTURE of system_zed_hdmi_0_0_zed_hdmi is
signal \^co\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal D1 : STD_LOGIC;
signal \^di\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^o\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal cb : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \cb[0]_i_1_n_0\ : STD_LOGIC;
signal \cb[1]_i_1_n_0\ : STD_LOGIC;
signal \cb[2]_i_1_n_0\ : STD_LOGIC;
signal \cb[3]_i_1_n_0\ : STD_LOGIC;
signal \cb[4]_i_1_n_0\ : STD_LOGIC;
signal \cb[5]_i_1_n_0\ : STD_LOGIC;
signal \cb[6]_i_1_n_0\ : STD_LOGIC;
signal \cb[7]_i_10_n_0\ : STD_LOGIC;
signal \cb[7]_i_11_n_0\ : STD_LOGIC;
signal \cb[7]_i_13_n_0\ : STD_LOGIC;
signal \cb[7]_i_14_n_0\ : STD_LOGIC;
signal \cb[7]_i_15_n_0\ : STD_LOGIC;
signal \cb[7]_i_16_n_0\ : STD_LOGIC;
signal \cb[7]_i_17_n_0\ : STD_LOGIC;
signal \cb[7]_i_18_n_0\ : STD_LOGIC;
signal \cb[7]_i_19_n_0\ : STD_LOGIC;
signal \cb[7]_i_20_n_0\ : STD_LOGIC;
signal \cb[7]_i_21_n_0\ : STD_LOGIC;
signal \cb[7]_i_22_n_0\ : STD_LOGIC;
signal \cb[7]_i_23_n_0\ : STD_LOGIC;
signal \cb[7]_i_24_n_0\ : STD_LOGIC;
signal \cb[7]_i_25_n_0\ : STD_LOGIC;
signal \cb[7]_i_26_n_0\ : STD_LOGIC;
signal \cb[7]_i_27_n_0\ : STD_LOGIC;
signal \cb[7]_i_28_n_0\ : STD_LOGIC;
signal \cb[7]_i_2_n_0\ : STD_LOGIC;
signal \cb[7]_i_4_n_0\ : STD_LOGIC;
signal \cb[7]_i_5_n_0\ : STD_LOGIC;
signal \cb[7]_i_6_n_0\ : STD_LOGIC;
signal \cb[7]_i_7_n_0\ : STD_LOGIC;
signal \cb[7]_i_8_n_0\ : STD_LOGIC;
signal \cb[7]_i_9_n_0\ : STD_LOGIC;
signal cb_hold : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \cb_hold[7]_i_1_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_100_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_101_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_102_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_103_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_104_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_105_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_106_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_107_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_108_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_109_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_110_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_111_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_112_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_113_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_114_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_19_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_20_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_27_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_32_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_34_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_43_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_44_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_51_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_52_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_53_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_54_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_55_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_56_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_57_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_58_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_59_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_60_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_61_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_62_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_63_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_64_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_65_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_67_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_68_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_69_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_70_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_71_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_72_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_73_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_74_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_76_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_77_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_78_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_79_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_80_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_82_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_83_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_84_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_85_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_86_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_87_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_88_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_89_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_91_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_92_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_93_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_94_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_95_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_96_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_97_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_98_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_99_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_21_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_23_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_25_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_27_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_28_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_43_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_44_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_21_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_23_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_26_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_28_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_34_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_20_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_25_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_32_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_32_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_67_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_68_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_69_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_70_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_71_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_72_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_74_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_75_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_76_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_77_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_78_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_79_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_80_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_81_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_82_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_95_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_96_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_97_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_98_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_100_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_101_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_102_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_103_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_104_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_105_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_106_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_23_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_24_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_25_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_27_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_28_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_48_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_51_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_52_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_53_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_54_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_55_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_56_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_64_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_65_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_66_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_67_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_69_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_70_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_71_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_72_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_76_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_77_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_78_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_79_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_80_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_81_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_82_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_83_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_89_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_90_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_91_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_92_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_93_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_99_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_19_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_21_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_52_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_53_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_54_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_55_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_56_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_57_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_58_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_59_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_60_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_62_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_63_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_64_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_65_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_67_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_68_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_69_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_70_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_71_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_72_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_73_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_74_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_75_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_76_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_77_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_78_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_79_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_80_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_81_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_82_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_9_n_0\ : STD_LOGIC;
signal cb_int_reg2 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal cb_int_reg3 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal cb_int_reg5 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal cb_int_reg7 : STD_LOGIC_VECTOR ( 30 downto 8 );
signal cb_int_reg8 : STD_LOGIC;
signal \cb_int_reg[11]_i_16_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_16_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_16_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_16_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_17_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_17_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_17_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_17_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_18_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_18_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_4\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_5\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_6\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_7\ : STD_LOGIC;
signal \cb_int_reg[11]_i_25_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_25_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_25_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_25_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_26_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_26_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_26_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_26_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_28_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_28_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_28_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_28_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_38_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_38_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_38_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_38_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_48_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_48_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_48_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_48_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_66_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_66_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_66_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_66_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_75_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_75_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_75_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_75_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_81_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_81_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_81_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_81_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_90_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_90_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_90_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_90_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[15]_i_20_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_20_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_20_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_20_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[19]_i_20_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_20_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_20_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_20_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_25_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_25_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_25_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_25_n_3\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[23]_i_24_n_0\ : STD_LOGIC;
signal \cb_int_reg[23]_i_24_n_1\ : STD_LOGIC;
signal \cb_int_reg[23]_i_24_n_2\ : STD_LOGIC;
signal \cb_int_reg[23]_i_24_n_3\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[27]_i_9_n_1\ : STD_LOGIC;
signal \cb_int_reg[27]_i_9_n_2\ : STD_LOGIC;
signal \cb_int_reg[27]_i_9_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_11_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_11_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_12_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_12_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_12_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_12_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_14_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_14_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_14_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_14_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_30_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_30_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_30_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_30_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_34_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_34_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_37_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_37_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_37_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_37_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_7_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_7_n_3\ : STD_LOGIC;
signal \^cb_int_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cb_int_reg[3]_i_15_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_15_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_15_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_15_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_21_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_21_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_21_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_21_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_34_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_34_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_34_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_63_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_63_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_63_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_63_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_25_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_25_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_25_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_28_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_28_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_28_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_28_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_38_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_38_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_38_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_38_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_61_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_61_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_61_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_61_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_66_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_66_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_66_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_66_n_3\ : STD_LOGIC;
signal \cb_int_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \cb_int_reg_n_0_[0]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[1]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[2]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[3]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[4]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[5]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[6]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[7]\ : STD_LOGIC;
signal \cb_reg[7]_i_12_n_0\ : STD_LOGIC;
signal \cb_reg[7]_i_12_n_1\ : STD_LOGIC;
signal \cb_reg[7]_i_12_n_2\ : STD_LOGIC;
signal \cb_reg[7]_i_12_n_3\ : STD_LOGIC;
signal \cb_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \cb_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \cb_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \cb_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \cb_reg[7]_i_3_n_0\ : STD_LOGIC;
signal \cb_reg[7]_i_3_n_1\ : STD_LOGIC;
signal \cb_reg[7]_i_3_n_2\ : STD_LOGIC;
signal \cb_reg[7]_i_3_n_3\ : STD_LOGIC;
signal cb_regn_0_0 : STD_LOGIC;
signal cr : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \cr[0]_i_1_n_0\ : STD_LOGIC;
signal \cr[1]_i_1_n_0\ : STD_LOGIC;
signal \cr[2]_i_1_n_0\ : STD_LOGIC;
signal \cr[3]_i_1_n_0\ : STD_LOGIC;
signal \cr[4]_i_1_n_0\ : STD_LOGIC;
signal \cr[5]_i_1_n_0\ : STD_LOGIC;
signal \cr[6]_i_1_n_0\ : STD_LOGIC;
signal \cr[7]_i_10_n_0\ : STD_LOGIC;
signal \cr[7]_i_11_n_0\ : STD_LOGIC;
signal \cr[7]_i_13_n_0\ : STD_LOGIC;
signal \cr[7]_i_14_n_0\ : STD_LOGIC;
signal \cr[7]_i_15_n_0\ : STD_LOGIC;
signal \cr[7]_i_16_n_0\ : STD_LOGIC;
signal \cr[7]_i_17_n_0\ : STD_LOGIC;
signal \cr[7]_i_18_n_0\ : STD_LOGIC;
signal \cr[7]_i_19_n_0\ : STD_LOGIC;
signal \cr[7]_i_20_n_0\ : STD_LOGIC;
signal \cr[7]_i_21_n_0\ : STD_LOGIC;
signal \cr[7]_i_22_n_0\ : STD_LOGIC;
signal \cr[7]_i_23_n_0\ : STD_LOGIC;
signal \cr[7]_i_24_n_0\ : STD_LOGIC;
signal \cr[7]_i_25_n_0\ : STD_LOGIC;
signal \cr[7]_i_26_n_0\ : STD_LOGIC;
signal \cr[7]_i_27_n_0\ : STD_LOGIC;
signal \cr[7]_i_28_n_0\ : STD_LOGIC;
signal \cr[7]_i_2_n_0\ : STD_LOGIC;
signal \cr[7]_i_4_n_0\ : STD_LOGIC;
signal \cr[7]_i_5_n_0\ : STD_LOGIC;
signal \cr[7]_i_6_n_0\ : STD_LOGIC;
signal \cr[7]_i_7_n_0\ : STD_LOGIC;
signal \cr[7]_i_8_n_0\ : STD_LOGIC;
signal \cr[7]_i_9_n_0\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[0]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[1]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[2]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[3]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[4]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[5]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[6]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[7]\ : STD_LOGIC;
signal \cr_int[11]_i_100_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_101_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_102_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_104_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_105_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_106_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_107_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_109_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_110_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_111_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_112_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_113_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_114_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_115_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_117_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_118_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_119_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_120_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_121_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_122_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_123_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_124_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_126_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_127_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_128_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_129_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_130_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_131_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_132_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_133_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_134_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_135_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_136_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_137_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_138_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_139_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_140_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_141_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_142_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_143_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_144_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_145_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_146_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_147_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_148_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_149_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_150_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_151_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_152_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_153_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_154_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_155_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_156_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_37_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_38_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_39_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_42_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_47_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_48_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_49_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_50_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_52_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_53_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_54_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_55_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_57_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_58_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_59_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_60_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_65_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_66_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_67_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_68_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_70_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_71_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_72_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_73_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_74_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_75_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_76_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_77_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_78_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_80_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_81_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_82_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_83_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_84_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_85_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_86_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_87_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_88_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_89_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_90_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_91_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_93_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_94_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_95_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_96_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_97_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_98_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_99_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_9_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_16_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_19_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_36_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_41_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_42_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_48_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_49_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_50_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_51_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_9_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_16_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_19_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_36_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_38_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_39_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_41_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_9_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_16_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_19_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_21_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_28_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_9_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_100_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_103_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_108_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_109_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_110_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_111_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_112_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_113_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_114_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_115_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_116_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_117_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_118_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_119_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_120_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_121_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_122_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_123_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_124_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_125_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_126_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_16_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_19_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_20_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_37_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_38_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_41_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_42_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_46_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_47_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_50_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_51_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_52_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_53_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_55_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_56_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_57_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_58_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_59_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_60_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_61_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_62_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_71_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_72_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_73_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_74_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_75_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_76_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_77_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_78_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_79_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_80_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_81_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_82_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_83_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_84_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_85_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_87_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_88_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_89_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_90_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_92_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_93_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_94_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_95_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_96_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_97_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_28_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_36_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_37_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_38_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_39_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_41_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_46_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_47_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_48_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_49_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_50_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_51_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_52_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_53_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_55_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_56_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_57_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_58_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_60_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_61_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_62_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_63_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_66_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_67_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_68_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_69_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_71_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_72_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_73_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_74_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_75_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_76_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_77_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_78_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_79_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_80_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_81_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_82_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_83_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_84_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_85_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_86_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_87_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_88_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_89_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_90_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_91_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_92_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_93_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_94_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_95_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_96_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_20_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_21_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_28_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_9_n_0\ : STD_LOGIC;
signal cr_int_reg3 : STD_LOGIC_VECTOR ( 7 to 7 );
signal \cr_int_reg3__0\ : STD_LOGIC_VECTOR ( 8 downto 1 );
signal cr_int_reg4 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal cr_int_reg6 : STD_LOGIC_VECTOR ( 30 downto 8 );
signal cr_int_reg7 : STD_LOGIC;
signal \^cr_int_reg[11]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cr_int_reg[11]_i_103_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_103_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_103_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_103_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_108_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_108_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_108_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_108_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_116_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_116_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_116_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_116_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_125_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_125_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_125_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_125_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_17_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_17_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_17_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_17_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_19_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_19_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_19_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_19_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_20_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_29_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_29_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_29_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_29_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_30_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_30_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_30_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_36_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_36_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_36_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_36_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_46_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_46_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_46_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_46_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_51_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_51_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_51_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_51_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_56_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_56_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_56_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_56_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_69_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_69_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_69_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_69_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_79_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_79_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_79_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_79_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_92_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_92_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_92_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_92_n_3\ : STD_LOGIC;
signal \^cr_int_reg[15]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cr_int_reg[15]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[15]_i_20_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_20_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_28_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_28_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_28_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_28_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_4\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_5\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_6\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_7\ : STD_LOGIC;
signal \^cr_int_reg[19]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cr_int_reg[19]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[19]_i_20_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_20_n_3\ : STD_LOGIC;
signal \cr_int_reg[19]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[19]_i_28_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_28_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_28_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_28_n_3\ : STD_LOGIC;
signal \^cr_int_reg[23]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^cr_int_reg[23]_1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \cr_int_reg[23]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[23]_i_20_n_0\ : STD_LOGIC;
signal \cr_int_reg[23]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[23]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[23]_i_20_n_3\ : STD_LOGIC;
signal \^cr_int_reg[27]_0\ : STD_LOGIC;
signal \^cr_int_reg[27]_1\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^cr_int_reg[27]_2\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \cr_int_reg[27]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[27]_i_9_n_3\ : STD_LOGIC;
signal \^cr_int_reg[31]_0\ : STD_LOGIC;
signal \^cr_int_reg[31]_1\ : STD_LOGIC;
signal \^cr_int_reg[31]_2\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cr_int_reg[31]_i_101_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_101_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_101_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_101_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_12_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_12_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_24_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_24_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_24_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_24_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_36_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_36_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_36_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_36_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_48_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_48_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_63_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_63_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_70_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_70_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_70_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_70_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_8_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_8_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_8_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_8_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_9_n_3\ : STD_LOGIC;
signal \^cr_int_reg[3]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^cr_int_reg[3]_1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^cr_int_reg[3]_2\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cr_int_reg[3]_i_15_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_15_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_15_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_15_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_20_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_20_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_26_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_26_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_26_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_26_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_42_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_42_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_42_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_42_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_59_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_59_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_59_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_59_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_7\ : STD_LOGIC;
signal \^cr_int_reg[7]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^cr_int_reg[7]_1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cr_int_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[7]_i_23_n_0\ : STD_LOGIC;
signal \cr_int_reg[7]_i_23_n_1\ : STD_LOGIC;
signal \cr_int_reg[7]_i_23_n_2\ : STD_LOGIC;
signal \cr_int_reg[7]_i_23_n_3\ : STD_LOGIC;
signal \cr_int_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \cr_int_reg_n_0_[0]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[1]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[2]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[3]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[4]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[5]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[6]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[7]\ : STD_LOGIC;
signal \cr_reg[7]_i_12_n_0\ : STD_LOGIC;
signal \cr_reg[7]_i_12_n_1\ : STD_LOGIC;
signal \cr_reg[7]_i_12_n_2\ : STD_LOGIC;
signal \cr_reg[7]_i_12_n_3\ : STD_LOGIC;
signal \cr_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \cr_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \cr_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \cr_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \cr_reg[7]_i_3_n_0\ : STD_LOGIC;
signal \cr_reg[7]_i_3_n_1\ : STD_LOGIC;
signal \cr_reg[7]_i_3_n_2\ : STD_LOGIC;
signal \cr_reg[7]_i_3_n_3\ : STD_LOGIC;
signal edge : STD_LOGIC;
signal edge_i_1_n_0 : STD_LOGIC;
signal edge_rb : STD_LOGIC;
signal edge_rb_i_1_n_0 : STD_LOGIC;
signal \hdmi_d[10]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[11]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[12]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[13]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[14]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[15]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[15]_i_2_n_0\ : STD_LOGIC;
signal \hdmi_d[8]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[9]_i_1_n_0\ : STD_LOGIC;
signal hdmi_vsync_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal y : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \y[0]_i_1_n_0\ : STD_LOGIC;
signal \y[1]_i_1_n_0\ : STD_LOGIC;
signal \y[2]_i_1_n_0\ : STD_LOGIC;
signal \y[3]_i_1_n_0\ : STD_LOGIC;
signal \y[4]_i_1_n_0\ : STD_LOGIC;
signal \y[5]_i_1_n_0\ : STD_LOGIC;
signal \y[6]_i_1_n_0\ : STD_LOGIC;
signal \y[7]_i_10_n_0\ : STD_LOGIC;
signal \y[7]_i_11_n_0\ : STD_LOGIC;
signal \y[7]_i_13_n_0\ : STD_LOGIC;
signal \y[7]_i_14_n_0\ : STD_LOGIC;
signal \y[7]_i_15_n_0\ : STD_LOGIC;
signal \y[7]_i_16_n_0\ : STD_LOGIC;
signal \y[7]_i_17_n_0\ : STD_LOGIC;
signal \y[7]_i_18_n_0\ : STD_LOGIC;
signal \y[7]_i_19_n_0\ : STD_LOGIC;
signal \y[7]_i_20_n_0\ : STD_LOGIC;
signal \y[7]_i_21_n_0\ : STD_LOGIC;
signal \y[7]_i_22_n_0\ : STD_LOGIC;
signal \y[7]_i_23_n_0\ : STD_LOGIC;
signal \y[7]_i_24_n_0\ : STD_LOGIC;
signal \y[7]_i_25_n_0\ : STD_LOGIC;
signal \y[7]_i_26_n_0\ : STD_LOGIC;
signal \y[7]_i_27_n_0\ : STD_LOGIC;
signal \y[7]_i_28_n_0\ : STD_LOGIC;
signal \y[7]_i_2_n_0\ : STD_LOGIC;
signal \y[7]_i_4_n_0\ : STD_LOGIC;
signal \y[7]_i_5_n_0\ : STD_LOGIC;
signal \y[7]_i_6_n_0\ : STD_LOGIC;
signal \y[7]_i_7_n_0\ : STD_LOGIC;
signal \y[7]_i_8_n_0\ : STD_LOGIC;
signal \y[7]_i_9_n_0\ : STD_LOGIC;
signal y_hold : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \y_int[11]_i_100_n_0\ : STD_LOGIC;
signal \y_int[11]_i_10_n_0\ : STD_LOGIC;
signal \y_int[11]_i_12_n_0\ : STD_LOGIC;
signal \y_int[11]_i_16_n_0\ : STD_LOGIC;
signal \y_int[11]_i_19_n_0\ : STD_LOGIC;
signal \y_int[11]_i_29_n_0\ : STD_LOGIC;
signal \y_int[11]_i_2_n_0\ : STD_LOGIC;
signal \y_int[11]_i_30_n_0\ : STD_LOGIC;
signal \y_int[11]_i_31_n_0\ : STD_LOGIC;
signal \y_int[11]_i_32_n_0\ : STD_LOGIC;
signal \y_int[11]_i_34_n_0\ : STD_LOGIC;
signal \y_int[11]_i_35_n_0\ : STD_LOGIC;
signal \y_int[11]_i_36_n_0\ : STD_LOGIC;
signal \y_int[11]_i_37_n_0\ : STD_LOGIC;
signal \y_int[11]_i_3_n_0\ : STD_LOGIC;
signal \y_int[11]_i_40_n_0\ : STD_LOGIC;
signal \y_int[11]_i_41_n_0\ : STD_LOGIC;
signal \y_int[11]_i_42_n_0\ : STD_LOGIC;
signal \y_int[11]_i_43_n_0\ : STD_LOGIC;
signal \y_int[11]_i_45_n_0\ : STD_LOGIC;
signal \y_int[11]_i_46_n_0\ : STD_LOGIC;
signal \y_int[11]_i_47_n_0\ : STD_LOGIC;
signal \y_int[11]_i_48_n_0\ : STD_LOGIC;
signal \y_int[11]_i_4_n_0\ : STD_LOGIC;
signal \y_int[11]_i_50_n_0\ : STD_LOGIC;
signal \y_int[11]_i_51_n_0\ : STD_LOGIC;
signal \y_int[11]_i_52_n_0\ : STD_LOGIC;
signal \y_int[11]_i_53_n_0\ : STD_LOGIC;
signal \y_int[11]_i_58_n_0\ : STD_LOGIC;
signal \y_int[11]_i_59_n_0\ : STD_LOGIC;
signal \y_int[11]_i_5_n_0\ : STD_LOGIC;
signal \y_int[11]_i_60_n_0\ : STD_LOGIC;
signal \y_int[11]_i_61_n_0\ : STD_LOGIC;
signal \y_int[11]_i_62_n_0\ : STD_LOGIC;
signal \y_int[11]_i_63_n_0\ : STD_LOGIC;
signal \y_int[11]_i_64_n_0\ : STD_LOGIC;
signal \y_int[11]_i_65_n_0\ : STD_LOGIC;
signal \y_int[11]_i_66_n_0\ : STD_LOGIC;
signal \y_int[11]_i_67_n_0\ : STD_LOGIC;
signal \y_int[11]_i_68_n_0\ : STD_LOGIC;
signal \y_int[11]_i_69_n_0\ : STD_LOGIC;
signal \y_int[11]_i_6_n_0\ : STD_LOGIC;
signal \y_int[11]_i_70_n_0\ : STD_LOGIC;
signal \y_int[11]_i_71_n_0\ : STD_LOGIC;
signal \y_int[11]_i_72_n_0\ : STD_LOGIC;
signal \y_int[11]_i_73_n_0\ : STD_LOGIC;
signal \y_int[11]_i_74_n_0\ : STD_LOGIC;
signal \y_int[11]_i_75_n_0\ : STD_LOGIC;
signal \y_int[11]_i_76_n_0\ : STD_LOGIC;
signal \y_int[11]_i_77_n_0\ : STD_LOGIC;
signal \y_int[11]_i_78_n_0\ : STD_LOGIC;
signal \y_int[11]_i_79_n_0\ : STD_LOGIC;
signal \y_int[11]_i_7_n_0\ : STD_LOGIC;
signal \y_int[11]_i_81_n_0\ : STD_LOGIC;
signal \y_int[11]_i_82_n_0\ : STD_LOGIC;
signal \y_int[11]_i_83_n_0\ : STD_LOGIC;
signal \y_int[11]_i_84_n_0\ : STD_LOGIC;
signal \y_int[11]_i_86_n_0\ : STD_LOGIC;
signal \y_int[11]_i_87_n_0\ : STD_LOGIC;
signal \y_int[11]_i_88_n_0\ : STD_LOGIC;
signal \y_int[11]_i_89_n_0\ : STD_LOGIC;
signal \y_int[11]_i_8_n_0\ : STD_LOGIC;
signal \y_int[11]_i_90_n_0\ : STD_LOGIC;
signal \y_int[11]_i_91_n_0\ : STD_LOGIC;
signal \y_int[11]_i_92_n_0\ : STD_LOGIC;
signal \y_int[11]_i_93_n_0\ : STD_LOGIC;
signal \y_int[11]_i_94_n_0\ : STD_LOGIC;
signal \y_int[11]_i_95_n_0\ : STD_LOGIC;
signal \y_int[11]_i_96_n_0\ : STD_LOGIC;
signal \y_int[11]_i_97_n_0\ : STD_LOGIC;
signal \y_int[11]_i_98_n_0\ : STD_LOGIC;
signal \y_int[11]_i_99_n_0\ : STD_LOGIC;
signal \y_int[11]_i_9_n_0\ : STD_LOGIC;
signal \y_int[15]_i_10_n_0\ : STD_LOGIC;
signal \y_int[15]_i_12_n_0\ : STD_LOGIC;
signal \y_int[15]_i_16_n_0\ : STD_LOGIC;
signal \y_int[15]_i_18_n_0\ : STD_LOGIC;
signal \y_int[15]_i_25_n_0\ : STD_LOGIC;
signal \y_int[15]_i_26_n_0\ : STD_LOGIC;
signal \y_int[15]_i_27_n_0\ : STD_LOGIC;
signal \y_int[15]_i_28_n_0\ : STD_LOGIC;
signal \y_int[15]_i_29_n_0\ : STD_LOGIC;
signal \y_int[15]_i_2_n_0\ : STD_LOGIC;
signal \y_int[15]_i_30_n_0\ : STD_LOGIC;
signal \y_int[15]_i_31_n_0\ : STD_LOGIC;
signal \y_int[15]_i_32_n_0\ : STD_LOGIC;
signal \y_int[15]_i_3_n_0\ : STD_LOGIC;
signal \y_int[15]_i_40_n_0\ : STD_LOGIC;
signal \y_int[15]_i_41_n_0\ : STD_LOGIC;
signal \y_int[15]_i_42_n_0\ : STD_LOGIC;
signal \y_int[15]_i_43_n_0\ : STD_LOGIC;
signal \y_int[15]_i_48_n_0\ : STD_LOGIC;
signal \y_int[15]_i_49_n_0\ : STD_LOGIC;
signal \y_int[15]_i_4_n_0\ : STD_LOGIC;
signal \y_int[15]_i_50_n_0\ : STD_LOGIC;
signal \y_int[15]_i_51_n_0\ : STD_LOGIC;
signal \y_int[15]_i_5_n_0\ : STD_LOGIC;
signal \y_int[15]_i_6_n_0\ : STD_LOGIC;
signal \y_int[15]_i_7_n_0\ : STD_LOGIC;
signal \y_int[15]_i_8_n_0\ : STD_LOGIC;
signal \y_int[15]_i_9_n_0\ : STD_LOGIC;
signal \y_int[19]_i_10_n_0\ : STD_LOGIC;
signal \y_int[19]_i_12_n_0\ : STD_LOGIC;
signal \y_int[19]_i_16_n_0\ : STD_LOGIC;
signal \y_int[19]_i_18_n_0\ : STD_LOGIC;
signal \y_int[19]_i_25_n_0\ : STD_LOGIC;
signal \y_int[19]_i_26_n_0\ : STD_LOGIC;
signal \y_int[19]_i_27_n_0\ : STD_LOGIC;
signal \y_int[19]_i_28_n_0\ : STD_LOGIC;
signal \y_int[19]_i_29_n_0\ : STD_LOGIC;
signal \y_int[19]_i_2_n_0\ : STD_LOGIC;
signal \y_int[19]_i_30_n_0\ : STD_LOGIC;
signal \y_int[19]_i_31_n_0\ : STD_LOGIC;
signal \y_int[19]_i_32_n_0\ : STD_LOGIC;
signal \y_int[19]_i_3_n_0\ : STD_LOGIC;
signal \y_int[19]_i_48_n_0\ : STD_LOGIC;
signal \y_int[19]_i_49_n_0\ : STD_LOGIC;
signal \y_int[19]_i_4_n_0\ : STD_LOGIC;
signal \y_int[19]_i_50_n_0\ : STD_LOGIC;
signal \y_int[19]_i_51_n_0\ : STD_LOGIC;
signal \y_int[19]_i_5_n_0\ : STD_LOGIC;
signal \y_int[19]_i_6_n_0\ : STD_LOGIC;
signal \y_int[19]_i_7_n_0\ : STD_LOGIC;
signal \y_int[19]_i_8_n_0\ : STD_LOGIC;
signal \y_int[19]_i_9_n_0\ : STD_LOGIC;
signal \y_int[23]_i_100_n_0\ : STD_LOGIC;
signal \y_int[23]_i_101_n_0\ : STD_LOGIC;
signal \y_int[23]_i_102_n_0\ : STD_LOGIC;
signal \y_int[23]_i_103_n_0\ : STD_LOGIC;
signal \y_int[23]_i_104_n_0\ : STD_LOGIC;
signal \y_int[23]_i_12_n_0\ : STD_LOGIC;
signal \y_int[23]_i_14_n_0\ : STD_LOGIC;
signal \y_int[23]_i_18_n_0\ : STD_LOGIC;
signal \y_int[23]_i_20_n_0\ : STD_LOGIC;
signal \y_int[23]_i_26_n_0\ : STD_LOGIC;
signal \y_int[23]_i_27_n_0\ : STD_LOGIC;
signal \y_int[23]_i_28_n_0\ : STD_LOGIC;
signal \y_int[23]_i_29_n_0\ : STD_LOGIC;
signal \y_int[23]_i_2_n_0\ : STD_LOGIC;
signal \y_int[23]_i_30_n_0\ : STD_LOGIC;
signal \y_int[23]_i_31_n_0\ : STD_LOGIC;
signal \y_int[23]_i_36_n_0\ : STD_LOGIC;
signal \y_int[23]_i_37_n_0\ : STD_LOGIC;
signal \y_int[23]_i_38_n_0\ : STD_LOGIC;
signal \y_int[23]_i_39_n_0\ : STD_LOGIC;
signal \y_int[23]_i_3_n_0\ : STD_LOGIC;
signal \y_int[23]_i_40_n_0\ : STD_LOGIC;
signal \y_int[23]_i_41_n_0\ : STD_LOGIC;
signal \y_int[23]_i_42_n_0\ : STD_LOGIC;
signal \y_int[23]_i_43_n_0\ : STD_LOGIC;
signal \y_int[23]_i_46_n_0\ : STD_LOGIC;
signal \y_int[23]_i_47_n_0\ : STD_LOGIC;
signal \y_int[23]_i_48_n_0\ : STD_LOGIC;
signal \y_int[23]_i_49_n_0\ : STD_LOGIC;
signal \y_int[23]_i_4_n_0\ : STD_LOGIC;
signal \y_int[23]_i_52_n_0\ : STD_LOGIC;
signal \y_int[23]_i_53_n_0\ : STD_LOGIC;
signal \y_int[23]_i_54_n_0\ : STD_LOGIC;
signal \y_int[23]_i_55_n_0\ : STD_LOGIC;
signal \y_int[23]_i_56_n_0\ : STD_LOGIC;
signal \y_int[23]_i_57_n_0\ : STD_LOGIC;
signal \y_int[23]_i_5_n_0\ : STD_LOGIC;
signal \y_int[23]_i_62_n_0\ : STD_LOGIC;
signal \y_int[23]_i_63_n_0\ : STD_LOGIC;
signal \y_int[23]_i_64_n_0\ : STD_LOGIC;
signal \y_int[23]_i_65_n_0\ : STD_LOGIC;
signal \y_int[23]_i_67_n_0\ : STD_LOGIC;
signal \y_int[23]_i_68_n_0\ : STD_LOGIC;
signal \y_int[23]_i_69_n_0\ : STD_LOGIC;
signal \y_int[23]_i_6_n_0\ : STD_LOGIC;
signal \y_int[23]_i_70_n_0\ : STD_LOGIC;
signal \y_int[23]_i_71_n_0\ : STD_LOGIC;
signal \y_int[23]_i_72_n_0\ : STD_LOGIC;
signal \y_int[23]_i_73_n_0\ : STD_LOGIC;
signal \y_int[23]_i_74_n_0\ : STD_LOGIC;
signal \y_int[23]_i_76_n_0\ : STD_LOGIC;
signal \y_int[23]_i_77_n_0\ : STD_LOGIC;
signal \y_int[23]_i_78_n_0\ : STD_LOGIC;
signal \y_int[23]_i_79_n_0\ : STD_LOGIC;
signal \y_int[23]_i_7_n_0\ : STD_LOGIC;
signal \y_int[23]_i_80_n_0\ : STD_LOGIC;
signal \y_int[23]_i_81_n_0\ : STD_LOGIC;
signal \y_int[23]_i_82_n_0\ : STD_LOGIC;
signal \y_int[23]_i_83_n_0\ : STD_LOGIC;
signal \y_int[23]_i_84_n_0\ : STD_LOGIC;
signal \y_int[23]_i_85_n_0\ : STD_LOGIC;
signal \y_int[23]_i_86_n_0\ : STD_LOGIC;
signal \y_int[23]_i_87_n_0\ : STD_LOGIC;
signal \y_int[23]_i_88_n_0\ : STD_LOGIC;
signal \y_int[23]_i_8_n_0\ : STD_LOGIC;
signal \y_int[23]_i_90_n_0\ : STD_LOGIC;
signal \y_int[23]_i_91_n_0\ : STD_LOGIC;
signal \y_int[23]_i_92_n_0\ : STD_LOGIC;
signal \y_int[23]_i_93_n_0\ : STD_LOGIC;
signal \y_int[23]_i_94_n_0\ : STD_LOGIC;
signal \y_int[23]_i_95_n_0\ : STD_LOGIC;
signal \y_int[23]_i_96_n_0\ : STD_LOGIC;
signal \y_int[23]_i_97_n_0\ : STD_LOGIC;
signal \y_int[23]_i_98_n_0\ : STD_LOGIC;
signal \y_int[23]_i_99_n_0\ : STD_LOGIC;
signal \y_int[23]_i_9_n_0\ : STD_LOGIC;
signal \y_int[27]_i_2_n_0\ : STD_LOGIC;
signal \y_int[27]_i_3_n_0\ : STD_LOGIC;
signal \y_int[27]_i_4_n_0\ : STD_LOGIC;
signal \y_int[27]_i_5_n_0\ : STD_LOGIC;
signal \y_int[31]_i_101_n_0\ : STD_LOGIC;
signal \y_int[31]_i_104_n_0\ : STD_LOGIC;
signal \y_int[31]_i_105_n_0\ : STD_LOGIC;
signal \y_int[31]_i_106_n_0\ : STD_LOGIC;
signal \y_int[31]_i_107_n_0\ : STD_LOGIC;
signal \y_int[31]_i_108_n_0\ : STD_LOGIC;
signal \y_int[31]_i_109_n_0\ : STD_LOGIC;
signal \y_int[31]_i_110_n_0\ : STD_LOGIC;
signal \y_int[31]_i_111_n_0\ : STD_LOGIC;
signal \y_int[31]_i_112_n_0\ : STD_LOGIC;
signal \y_int[31]_i_113_n_0\ : STD_LOGIC;
signal \y_int[31]_i_114_n_0\ : STD_LOGIC;
signal \y_int[31]_i_115_n_0\ : STD_LOGIC;
signal \y_int[31]_i_116_n_0\ : STD_LOGIC;
signal \y_int[31]_i_13_n_0\ : STD_LOGIC;
signal \y_int[31]_i_14_n_0\ : STD_LOGIC;
signal \y_int[31]_i_15_n_0\ : STD_LOGIC;
signal \y_int[31]_i_17_n_0\ : STD_LOGIC;
signal \y_int[31]_i_18_n_0\ : STD_LOGIC;
signal \y_int[31]_i_19_n_0\ : STD_LOGIC;
signal \y_int[31]_i_20_n_0\ : STD_LOGIC;
signal \y_int[31]_i_2_n_0\ : STD_LOGIC;
signal \y_int[31]_i_32_n_0\ : STD_LOGIC;
signal \y_int[31]_i_33_n_0\ : STD_LOGIC;
signal \y_int[31]_i_34_n_0\ : STD_LOGIC;
signal \y_int[31]_i_35_n_0\ : STD_LOGIC;
signal \y_int[31]_i_36_n_0\ : STD_LOGIC;
signal \y_int[31]_i_3_n_0\ : STD_LOGIC;
signal \y_int[31]_i_40_n_0\ : STD_LOGIC;
signal \y_int[31]_i_41_n_0\ : STD_LOGIC;
signal \y_int[31]_i_42_n_0\ : STD_LOGIC;
signal \y_int[31]_i_43_n_0\ : STD_LOGIC;
signal \y_int[31]_i_44_n_0\ : STD_LOGIC;
signal \y_int[31]_i_45_n_0\ : STD_LOGIC;
signal \y_int[31]_i_46_n_0\ : STD_LOGIC;
signal \y_int[31]_i_47_n_0\ : STD_LOGIC;
signal \y_int[31]_i_4_n_0\ : STD_LOGIC;
signal \y_int[31]_i_5_n_0\ : STD_LOGIC;
signal \y_int[31]_i_63_n_0\ : STD_LOGIC;
signal \y_int[31]_i_64_n_0\ : STD_LOGIC;
signal \y_int[31]_i_65_n_0\ : STD_LOGIC;
signal \y_int[31]_i_66_n_0\ : STD_LOGIC;
signal \y_int[31]_i_67_n_0\ : STD_LOGIC;
signal \y_int[31]_i_68_n_0\ : STD_LOGIC;
signal \y_int[31]_i_69_n_0\ : STD_LOGIC;
signal \y_int[31]_i_6_n_0\ : STD_LOGIC;
signal \y_int[31]_i_70_n_0\ : STD_LOGIC;
signal \y_int[31]_i_89_n_0\ : STD_LOGIC;
signal \y_int[31]_i_90_n_0\ : STD_LOGIC;
signal \y_int[31]_i_91_n_0\ : STD_LOGIC;
signal \y_int[31]_i_92_n_0\ : STD_LOGIC;
signal \y_int[3]_i_10_n_0\ : STD_LOGIC;
signal \y_int[3]_i_13_n_0\ : STD_LOGIC;
signal \y_int[3]_i_17_n_0\ : STD_LOGIC;
signal \y_int[3]_i_18_n_0\ : STD_LOGIC;
signal \y_int[3]_i_22_n_0\ : STD_LOGIC;
signal \y_int[3]_i_23_n_0\ : STD_LOGIC;
signal \y_int[3]_i_24_n_0\ : STD_LOGIC;
signal \y_int[3]_i_25_n_0\ : STD_LOGIC;
signal \y_int[3]_i_27_n_0\ : STD_LOGIC;
signal \y_int[3]_i_28_n_0\ : STD_LOGIC;
signal \y_int[3]_i_29_n_0\ : STD_LOGIC;
signal \y_int[3]_i_2_n_0\ : STD_LOGIC;
signal \y_int[3]_i_31_n_0\ : STD_LOGIC;
signal \y_int[3]_i_32_n_0\ : STD_LOGIC;
signal \y_int[3]_i_33_n_0\ : STD_LOGIC;
signal \y_int[3]_i_34_n_0\ : STD_LOGIC;
signal \y_int[3]_i_3_n_0\ : STD_LOGIC;
signal \y_int[3]_i_4_n_0\ : STD_LOGIC;
signal \y_int[3]_i_50_n_0\ : STD_LOGIC;
signal \y_int[3]_i_51_n_0\ : STD_LOGIC;
signal \y_int[3]_i_52_n_0\ : STD_LOGIC;
signal \y_int[3]_i_53_n_0\ : STD_LOGIC;
signal \y_int[3]_i_54_n_0\ : STD_LOGIC;
signal \y_int[3]_i_56_n_0\ : STD_LOGIC;
signal \y_int[3]_i_57_n_0\ : STD_LOGIC;
signal \y_int[3]_i_58_n_0\ : STD_LOGIC;
signal \y_int[3]_i_59_n_0\ : STD_LOGIC;
signal \y_int[3]_i_5_n_0\ : STD_LOGIC;
signal \y_int[3]_i_60_n_0\ : STD_LOGIC;
signal \y_int[3]_i_61_n_0\ : STD_LOGIC;
signal \y_int[3]_i_62_n_0\ : STD_LOGIC;
signal \y_int[3]_i_63_n_0\ : STD_LOGIC;
signal \y_int[3]_i_66_n_0\ : STD_LOGIC;
signal \y_int[3]_i_67_n_0\ : STD_LOGIC;
signal \y_int[3]_i_68_n_0\ : STD_LOGIC;
signal \y_int[3]_i_69_n_0\ : STD_LOGIC;
signal \y_int[3]_i_6_n_0\ : STD_LOGIC;
signal \y_int[3]_i_71_n_0\ : STD_LOGIC;
signal \y_int[3]_i_72_n_0\ : STD_LOGIC;
signal \y_int[3]_i_73_n_0\ : STD_LOGIC;
signal \y_int[3]_i_74_n_0\ : STD_LOGIC;
signal \y_int[3]_i_7_n_0\ : STD_LOGIC;
signal \y_int[3]_i_84_n_0\ : STD_LOGIC;
signal \y_int[3]_i_85_n_0\ : STD_LOGIC;
signal \y_int[3]_i_86_n_0\ : STD_LOGIC;
signal \y_int[3]_i_87_n_0\ : STD_LOGIC;
signal \y_int[3]_i_88_n_0\ : STD_LOGIC;
signal \y_int[3]_i_89_n_0\ : STD_LOGIC;
signal \y_int[3]_i_8_n_0\ : STD_LOGIC;
signal \y_int[3]_i_90_n_0\ : STD_LOGIC;
signal \y_int[3]_i_91_n_0\ : STD_LOGIC;
signal \y_int[3]_i_92_n_0\ : STD_LOGIC;
signal \y_int[7]_i_11_n_0\ : STD_LOGIC;
signal \y_int[7]_i_13_n_0\ : STD_LOGIC;
signal \y_int[7]_i_16_n_0\ : STD_LOGIC;
signal \y_int[7]_i_19_n_0\ : STD_LOGIC;
signal \y_int[7]_i_29_n_0\ : STD_LOGIC;
signal \y_int[7]_i_2_n_0\ : STD_LOGIC;
signal \y_int[7]_i_30_n_0\ : STD_LOGIC;
signal \y_int[7]_i_31_n_0\ : STD_LOGIC;
signal \y_int[7]_i_32_n_0\ : STD_LOGIC;
signal \y_int[7]_i_33_n_0\ : STD_LOGIC;
signal \y_int[7]_i_3_n_0\ : STD_LOGIC;
signal \y_int[7]_i_4_n_0\ : STD_LOGIC;
signal \y_int[7]_i_5_n_0\ : STD_LOGIC;
signal \y_int[7]_i_6_n_0\ : STD_LOGIC;
signal \y_int[7]_i_7_n_0\ : STD_LOGIC;
signal \y_int[7]_i_8_n_0\ : STD_LOGIC;
signal \y_int[7]_i_9_n_0\ : STD_LOGIC;
signal y_int_reg1 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal y_int_reg2 : STD_LOGIC_VECTOR ( 8 downto 1 );
signal y_int_reg20_in : STD_LOGIC_VECTOR ( 22 downto 1 );
signal y_int_reg3 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal y_int_reg5 : STD_LOGIC_VECTOR ( 30 downto 8 );
signal y_int_reg6 : STD_LOGIC;
signal \y_int_reg[11]_i_14_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_14_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_14_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_14_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_15_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_15_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_15_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_15_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[11]_i_20_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_20_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_20_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_7\ : STD_LOGIC;
signal \y_int_reg[11]_i_22_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_22_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_22_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_28_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_28_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_28_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_28_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_33_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_33_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_33_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_33_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_7\ : STD_LOGIC;
signal \y_int_reg[11]_i_39_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_39_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_39_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_39_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_7\ : STD_LOGIC;
signal \y_int_reg[11]_i_49_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_49_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_49_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_49_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_80_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_80_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_80_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_80_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_85_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_85_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_85_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_85_n_3\ : STD_LOGIC;
signal \^y_int_reg[15]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \y_int_reg[15]_i_14_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_14_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_14_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_14_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_15_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_15_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_15_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_15_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_4\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_5\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_6\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_7\ : STD_LOGIC;
signal \y_int_reg[15]_i_35_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_35_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_35_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_35_n_3\ : STD_LOGIC;
signal \^y_int_reg[19]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \y_int_reg[19]_i_14_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_14_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_14_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_14_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_15_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_15_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_15_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_15_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[19]_i_35_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_35_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_35_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_35_n_3\ : STD_LOGIC;
signal \^y_int_reg[23]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^y_int_reg[23]_1\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^y_int_reg[23]_2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \y_int_reg[23]_i_10_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_10_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_10_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_11_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_16_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_16_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_16_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_16_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_17_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_17_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_17_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_17_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[23]_i_25_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_25_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_25_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_25_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_33_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_33_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_33_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_34_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_44_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_44_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_44_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_44_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_45_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_45_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_45_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_45_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_51_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_51_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_51_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_51_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_66_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_66_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_66_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_66_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_75_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_75_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_75_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_75_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_89_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_89_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_89_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_89_n_3\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_75_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_75_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_7_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_7_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_7\ : STD_LOGIC;
signal \^y_int_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^y_int_reg[3]_1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \y_int_reg[3]_i_15_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_15_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_15_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_15_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_21_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_21_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_21_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_21_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_36_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_36_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_36_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_64_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_64_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_65_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_65_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_65_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_65_n_3\ : STD_LOGIC;
signal \^y_int_reg[7]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \y_int_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_0\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_1\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_2\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_3\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_4\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_5\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_6\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_7\ : STD_LOGIC;
signal \y_int_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \y_int_reg_n_0_[0]\ : STD_LOGIC;
signal \y_int_reg_n_0_[1]\ : STD_LOGIC;
signal \y_int_reg_n_0_[2]\ : STD_LOGIC;
signal \y_int_reg_n_0_[3]\ : STD_LOGIC;
signal \y_int_reg_n_0_[4]\ : STD_LOGIC;
signal \y_int_reg_n_0_[5]\ : STD_LOGIC;
signal \y_int_reg_n_0_[6]\ : STD_LOGIC;
signal \y_int_reg_n_0_[7]\ : STD_LOGIC;
signal \y_reg[7]_i_12_n_0\ : STD_LOGIC;
signal \y_reg[7]_i_12_n_1\ : STD_LOGIC;
signal \y_reg[7]_i_12_n_2\ : STD_LOGIC;
signal \y_reg[7]_i_12_n_3\ : STD_LOGIC;
signal \y_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \y_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \y_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \y_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \y_reg[7]_i_3_n_0\ : STD_LOGIC;
signal \y_reg[7]_i_3_n_1\ : STD_LOGIC;
signal \y_reg[7]_i_3_n_2\ : STD_LOGIC;
signal \y_reg[7]_i_3_n_3\ : STD_LOGIC;
signal NLW_ODDR_inst_R_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR_inst_S_UNCONNECTED : STD_LOGIC;
signal \NLW_cb_int_reg[11]_i_18_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[11]_i_18_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_25_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_38_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_48_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_75_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_81_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_90_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[27]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[31]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[31]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_11_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_12_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_34_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[31]_i_34_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_7_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_7_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[3]_i_15_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_cb_int_reg[3]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[3]_i_26_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_cb_int_reg[3]_i_33_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_cb_int_reg[3]_i_63_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[7]_i_25_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[7]_i_38_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[7]_i_61_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[7]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_reg[7]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_reg[7]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_103_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_108_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_116_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_125_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_17_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_20_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_30_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_36_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_51_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_69_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_79_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_92_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[27]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[27]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cr_int_reg[31]_i_101_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_101_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cr_int_reg[31]_i_12_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_48_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[31]_i_48_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_63_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[31]_i_63_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_69_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[31]_i_69_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_7_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cr_int_reg[31]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[3]_i_15_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_cr_int_reg[3]_i_20_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_cr_int_reg[3]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[3]_i_26_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[3]_i_26_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[3]_i_32_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_cr_int_reg[3]_i_33_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_cr_int_reg[3]_i_42_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[3]_i_59_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[3]_i_65_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_cr_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_reg[7]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_reg[7]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[11]_i_22_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[11]_i_49_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[11]_i_80_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[11]_i_85_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[23]_i_11_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[23]_i_25_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_33_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_34_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[23]_i_34_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[23]_i_45_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_51_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_75_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_89_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[31]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[31]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[31]_i_62_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_y_int_reg[31]_i_7_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_7_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_75_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[31]_i_75_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[31]_i_86_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_y_int_reg[31]_i_88_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_y_int_reg[3]_i_15_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_y_int_reg[3]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[3]_i_35_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_y_int_reg[3]_i_55_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_y_int_reg[3]_i_64_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[3]_i_64_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[3]_i_65_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_reg[7]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_reg[7]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute \__SRVAL\ : string;
attribute \__SRVAL\ of ODDR_inst : label is "TRUE";
attribute box_type : string;
attribute box_type of ODDR_inst : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cb[0]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \cb[1]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \cb[2]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \cb[3]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \cb[4]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \cb[5]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \cb[6]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \cb[7]_i_2\ : label is "soft_lutpair34";
attribute HLUTNM : string;
attribute HLUTNM of \cb_int[11]_i_2\ : label is "lutpair8";
attribute HLUTNM of \cb_int[11]_i_3\ : label is "lutpair7";
attribute HLUTNM of \cb_int[11]_i_4\ : label is "lutpair6";
attribute HLUTNM of \cb_int[11]_i_6\ : label is "lutpair9";
attribute HLUTNM of \cb_int[11]_i_7\ : label is "lutpair8";
attribute HLUTNM of \cb_int[11]_i_8\ : label is "lutpair7";
attribute HLUTNM of \cb_int[11]_i_9\ : label is "lutpair6";
attribute HLUTNM of \cb_int[15]_i_2\ : label is "lutpair12";
attribute HLUTNM of \cb_int[15]_i_3\ : label is "lutpair11";
attribute HLUTNM of \cb_int[15]_i_4\ : label is "lutpair10";
attribute HLUTNM of \cb_int[15]_i_5\ : label is "lutpair9";
attribute HLUTNM of \cb_int[15]_i_6\ : label is "lutpair13";
attribute HLUTNM of \cb_int[15]_i_7\ : label is "lutpair12";
attribute HLUTNM of \cb_int[15]_i_8\ : label is "lutpair11";
attribute HLUTNM of \cb_int[15]_i_9\ : label is "lutpair10";
attribute HLUTNM of \cb_int[19]_i_2\ : label is "lutpair16";
attribute HLUTNM of \cb_int[19]_i_3\ : label is "lutpair15";
attribute HLUTNM of \cb_int[19]_i_4\ : label is "lutpair14";
attribute HLUTNM of \cb_int[19]_i_5\ : label is "lutpair13";
attribute HLUTNM of \cb_int[19]_i_6\ : label is "lutpair17";
attribute HLUTNM of \cb_int[19]_i_7\ : label is "lutpair16";
attribute HLUTNM of \cb_int[19]_i_8\ : label is "lutpair15";
attribute HLUTNM of \cb_int[19]_i_9\ : label is "lutpair14";
attribute HLUTNM of \cb_int[23]_i_2\ : label is "lutpair20";
attribute SOFT_HLUTNM of \cb_int[23]_i_20\ : label is "soft_lutpair19";
attribute HLUTNM of \cb_int[23]_i_3\ : label is "lutpair19";
attribute HLUTNM of \cb_int[23]_i_4\ : label is "lutpair18";
attribute HLUTNM of \cb_int[23]_i_5\ : label is "lutpair17";
attribute HLUTNM of \cb_int[23]_i_6\ : label is "lutpair21";
attribute HLUTNM of \cb_int[23]_i_7\ : label is "lutpair20";
attribute HLUTNM of \cb_int[23]_i_8\ : label is "lutpair19";
attribute HLUTNM of \cb_int[23]_i_9\ : label is "lutpair18";
attribute HLUTNM of \cb_int[27]_i_2\ : label is "lutpair21";
attribute SOFT_HLUTNM of \cb_int[31]_i_13\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \cb_int[31]_i_86\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \cb_int[31]_i_87\ : label is "soft_lutpair18";
attribute HLUTNM of \cb_int[3]_i_2\ : label is "lutpair2";
attribute HLUTNM of \cb_int[3]_i_3\ : label is "lutpair1";
attribute HLUTNM of \cb_int[3]_i_4\ : label is "lutpair39";
attribute HLUTNM of \cb_int[3]_i_5\ : label is "lutpair3";
attribute HLUTNM of \cb_int[3]_i_6\ : label is "lutpair2";
attribute HLUTNM of \cb_int[3]_i_7\ : label is "lutpair1";
attribute HLUTNM of \cb_int[3]_i_8\ : label is "lutpair39";
attribute HLUTNM of \cb_int[7]_i_3\ : label is "lutpair5";
attribute HLUTNM of \cb_int[7]_i_4\ : label is "lutpair4";
attribute HLUTNM of \cb_int[7]_i_5\ : label is "lutpair3";
attribute HLUTNM of \cb_int[7]_i_8\ : label is "lutpair5";
attribute HLUTNM of \cb_int[7]_i_9\ : label is "lutpair4";
attribute SOFT_HLUTNM of \cr[0]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \cr[1]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \cr[2]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \cr[3]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \cr[4]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \cr[5]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \cr[6]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \cr[7]_i_2\ : label is "soft_lutpair26";
attribute HLUTNM of \cr_int[11]_i_2\ : label is "lutpair29";
attribute SOFT_HLUTNM of \cr_int[11]_i_22\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \cr_int[11]_i_23\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \cr_int[11]_i_27\ : label is "soft_lutpair20";
attribute HLUTNM of \cr_int[11]_i_7\ : label is "lutpair29";
attribute HLUTNM of \cr_int[15]_i_2\ : label is "lutpair30";
attribute HLUTNM of \cr_int[15]_i_7\ : label is "lutpair30";
attribute HLUTNM of \cr_int[19]_i_2\ : label is "lutpair31";
attribute HLUTNM of \cr_int[19]_i_7\ : label is "lutpair31";
attribute HLUTNM of \cr_int[23]_i_2\ : label is "lutpair32";
attribute HLUTNM of \cr_int[23]_i_7\ : label is "lutpair32";
attribute SOFT_HLUTNM of \cr_int[31]_i_13\ : label is "soft_lutpair20";
attribute HLUTNM of \cr_int[31]_i_16\ : label is "lutpair23";
attribute HLUTNM of \cr_int[31]_i_44\ : label is "lutpair23";
attribute HLUTNM of \cr_int[3]_i_2\ : label is "lutpair25";
attribute HLUTNM of \cr_int[3]_i_3\ : label is "lutpair24";
attribute HLUTNM of \cr_int[3]_i_34\ : label is "lutpair22";
attribute HLUTNM of \cr_int[3]_i_39\ : label is "lutpair22";
attribute HLUTNM of \cr_int[3]_i_4\ : label is "lutpair40";
attribute HLUTNM of \cr_int[3]_i_5\ : label is "lutpair26";
attribute HLUTNM of \cr_int[3]_i_6\ : label is "lutpair25";
attribute HLUTNM of \cr_int[3]_i_7\ : label is "lutpair24";
attribute HLUTNM of \cr_int[3]_i_8\ : label is "lutpair40";
attribute HLUTNM of \cr_int[7]_i_3\ : label is "lutpair28";
attribute HLUTNM of \cr_int[7]_i_4\ : label is "lutpair27";
attribute HLUTNM of \cr_int[7]_i_5\ : label is "lutpair26";
attribute HLUTNM of \cr_int[7]_i_8\ : label is "lutpair28";
attribute HLUTNM of \cr_int[7]_i_9\ : label is "lutpair27";
attribute SOFT_HLUTNM of \y[0]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \y[1]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \y[2]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \y[3]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \y[4]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \y[5]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \y[6]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \y[7]_i_2\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \y_hold[0]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \y_hold[1]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \y_hold[2]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \y_hold[3]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \y_hold[4]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \y_hold[5]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \y_hold[6]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \y_hold[7]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \y_int[23]_i_12\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \y_int[31]_i_13\ : label is "soft_lutpair21";
attribute HLUTNM of \y_int[3]_i_2\ : label is "lutpair35";
attribute HLUTNM of \y_int[3]_i_3\ : label is "lutpair34";
attribute HLUTNM of \y_int[3]_i_4\ : label is "lutpair33";
attribute HLUTNM of \y_int[3]_i_5\ : label is "lutpair36";
attribute HLUTNM of \y_int[3]_i_6\ : label is "lutpair35";
attribute HLUTNM of \y_int[3]_i_7\ : label is "lutpair34";
attribute HLUTNM of \y_int[3]_i_8\ : label is "lutpair33";
attribute HLUTNM of \y_int[7]_i_3\ : label is "lutpair38";
attribute HLUTNM of \y_int[7]_i_4\ : label is "lutpair37";
attribute HLUTNM of \y_int[7]_i_5\ : label is "lutpair36";
attribute HLUTNM of \y_int[7]_i_8\ : label is "lutpair38";
attribute HLUTNM of \y_int[7]_i_9\ : label is "lutpair37";
begin
CO(0) <= \^co\(0);
DI(0) <= \^di\(0);
O(1 downto 0) <= \^o\(1 downto 0);
\cb_int_reg[3]_0\(3 downto 0) <= \^cb_int_reg[3]_0\(3 downto 0);
\cr_int_reg[11]_0\(3 downto 0) <= \^cr_int_reg[11]_0\(3 downto 0);
\cr_int_reg[15]_0\(3 downto 0) <= \^cr_int_reg[15]_0\(3 downto 0);
\cr_int_reg[19]_0\(3 downto 0) <= \^cr_int_reg[19]_0\(3 downto 0);
\cr_int_reg[23]_0\(3 downto 0) <= \^cr_int_reg[23]_0\(3 downto 0);
\cr_int_reg[23]_1\(0) <= \^cr_int_reg[23]_1\(0);
\cr_int_reg[27]_0\ <= \^cr_int_reg[27]_0\;
\cr_int_reg[27]_1\(1 downto 0) <= \^cr_int_reg[27]_1\(1 downto 0);
\cr_int_reg[27]_2\(0) <= \^cr_int_reg[27]_2\(0);
\cr_int_reg[31]_0\ <= \^cr_int_reg[31]_0\;
\cr_int_reg[31]_1\ <= \^cr_int_reg[31]_1\;
\cr_int_reg[31]_2\(1 downto 0) <= \^cr_int_reg[31]_2\(1 downto 0);
\cr_int_reg[3]_0\(2 downto 0) <= \^cr_int_reg[3]_0\(2 downto 0);
\cr_int_reg[3]_1\(0) <= \^cr_int_reg[3]_1\(0);
\cr_int_reg[3]_2\(1 downto 0) <= \^cr_int_reg[3]_2\(1 downto 0);
\cr_int_reg[7]_0\(3 downto 0) <= \^cr_int_reg[7]_0\(3 downto 0);
\cr_int_reg[7]_1\(3 downto 0) <= \^cr_int_reg[7]_1\(3 downto 0);
\y_int_reg[15]_0\(3 downto 0) <= \^y_int_reg[15]_0\(3 downto 0);
\y_int_reg[19]_0\(3 downto 0) <= \^y_int_reg[19]_0\(3 downto 0);
\y_int_reg[23]_0\(0) <= \^y_int_reg[23]_0\(0);
\y_int_reg[23]_1\(1 downto 0) <= \^y_int_reg[23]_1\(1 downto 0);
\y_int_reg[23]_2\(3 downto 0) <= \^y_int_reg[23]_2\(3 downto 0);
\y_int_reg[3]_0\(3 downto 0) <= \^y_int_reg[3]_0\(3 downto 0);
\y_int_reg[3]_1\(0) <= \^y_int_reg[3]_1\(0);
\y_int_reg[7]_0\(0) <= \^y_int_reg[7]_0\(0);
Inst_i2c_sender: entity work.system_zed_hdmi_0_0_i2c_sender
port map (
clk_100 => clk_100,
hdmi_scl => hdmi_scl,
hdmi_sda => hdmi_sda
);
ODDR_inst: unisim.vcomponents.ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
IS_C_INVERTED => '0',
IS_D1_INVERTED => '0',
IS_D2_INVERTED => '0',
SRTYPE => "SYNC"
)
port map (
C => clk_x2,
CE => '1',
D1 => D1,
D2 => D1,
Q => hdmi_clk,
R => NLW_ODDR_inst_R_UNCONNECTED,
S => NLW_ODDR_inst_S_UNCONNECTED
);
\cb[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[0]\,
I1 => \cb_int_reg__0\(31),
O => \cb[0]_i_1_n_0\
);
\cb[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[1]\,
I1 => \cb_int_reg__0\(31),
O => \cb[1]_i_1_n_0\
);
\cb[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[2]\,
I1 => \cb_int_reg__0\(31),
O => \cb[2]_i_1_n_0\
);
\cb[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[3]\,
I1 => \cb_int_reg__0\(31),
O => \cb[3]_i_1_n_0\
);
\cb[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[4]\,
I1 => \cb_int_reg__0\(31),
O => \cb[4]_i_1_n_0\
);
\cb[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[5]\,
I1 => \cb_int_reg__0\(31),
O => \cb[5]_i_1_n_0\
);
\cb[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[6]\,
I1 => \cb_int_reg__0\(31),
O => \cb[6]_i_1_n_0\
);
\cb[7]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(26),
I1 => \cb_int_reg__0\(27),
O => \cb[7]_i_10_n_0\
);
\cb[7]_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(24),
I1 => \cb_int_reg__0\(25),
O => \cb[7]_i_11_n_0\
);
\cb[7]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(22),
I1 => \cb_int_reg__0\(23),
O => \cb[7]_i_13_n_0\
);
\cb[7]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(20),
I1 => \cb_int_reg__0\(21),
O => \cb[7]_i_14_n_0\
);
\cb[7]_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(18),
I1 => \cb_int_reg__0\(19),
O => \cb[7]_i_15_n_0\
);
\cb[7]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(16),
I1 => \cb_int_reg__0\(17),
O => \cb[7]_i_16_n_0\
);
\cb[7]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(22),
I1 => \cb_int_reg__0\(23),
O => \cb[7]_i_17_n_0\
);
\cb[7]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(20),
I1 => \cb_int_reg__0\(21),
O => \cb[7]_i_18_n_0\
);
\cb[7]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(18),
I1 => \cb_int_reg__0\(19),
O => \cb[7]_i_19_n_0\
);
\cb[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[7]\,
I1 => \cb_int_reg__0\(31),
O => \cb[7]_i_2_n_0\
);
\cb[7]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(16),
I1 => \cb_int_reg__0\(17),
O => \cb[7]_i_20_n_0\
);
\cb[7]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(14),
I1 => \cb_int_reg__0\(15),
O => \cb[7]_i_21_n_0\
);
\cb[7]_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(12),
I1 => \cb_int_reg__0\(13),
O => \cb[7]_i_22_n_0\
);
\cb[7]_i_23\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(10),
I1 => \cb_int_reg__0\(11),
O => \cb[7]_i_23_n_0\
);
\cb[7]_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(8),
I1 => \cb_int_reg__0\(9),
O => \cb[7]_i_24_n_0\
);
\cb[7]_i_25\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(14),
I1 => \cb_int_reg__0\(15),
O => \cb[7]_i_25_n_0\
);
\cb[7]_i_26\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(12),
I1 => \cb_int_reg__0\(13),
O => \cb[7]_i_26_n_0\
);
\cb[7]_i_27\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(10),
I1 => \cb_int_reg__0\(11),
O => \cb[7]_i_27_n_0\
);
\cb[7]_i_28\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(8),
I1 => \cb_int_reg__0\(9),
O => \cb[7]_i_28_n_0\
);
\cb[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg__0\(30),
I1 => \cb_int_reg__0\(31),
O => \cb[7]_i_4_n_0\
);
\cb[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(28),
I1 => \cb_int_reg__0\(29),
O => \cb[7]_i_5_n_0\
);
\cb[7]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(26),
I1 => \cb_int_reg__0\(27),
O => \cb[7]_i_6_n_0\
);
\cb[7]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(24),
I1 => \cb_int_reg__0\(25),
O => \cb[7]_i_7_n_0\
);
\cb[7]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(30),
I1 => \cb_int_reg__0\(31),
O => \cb[7]_i_8_n_0\
);
\cb[7]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(28),
I1 => \cb_int_reg__0\(29),
O => \cb[7]_i_9_n_0\
);
\cb_hold[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => edge,
I1 => edge_rb,
O => \cb_hold[7]_i_1_n_0\
);
\cb_hold_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(0),
Q => cb_hold(0),
R => '0'
);
\cb_hold_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(1),
Q => cb_hold(1),
R => '0'
);
\cb_hold_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(2),
Q => cb_hold(2),
R => '0'
);
\cb_hold_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(3),
Q => cb_hold(3),
R => '0'
);
\cb_hold_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(4),
Q => cb_hold(4),
R => '0'
);
\cb_hold_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(5),
Q => cb_hold(5),
R => '0'
);
\cb_hold_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(6),
Q => cb_hold(6),
R => '0'
);
\cb_hold_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(7),
Q => cb_hold(7),
R => '0'
);
\cb_int[11]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(10),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(18),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_25_n_0\,
I5 => cb_int_reg2(10),
O => \cb_int[11]_i_10_n_0\
);
\cb_int[11]_i_100\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_6\,
I1 => \cb_int_reg[3]_i_16_n_5\,
O => \cb_int[11]_i_100_n_0\
);
\cb_int[11]_i_101\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_4\,
I1 => \cb_int_reg[3]_i_16_n_7\,
O => \cb_int[11]_i_101_n_0\
);
\cb_int[11]_i_102\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_6\,
I1 => \cb_int_reg[3]_i_26_n_5\,
O => \cb_int[11]_i_102_n_0\
);
\cb_int[11]_i_103\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_7\,
I1 => \cb_int_reg[3]_i_16_n_4\,
O => \cb_int[11]_i_103_n_0\
);
\cb_int[11]_i_104\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_5\,
I1 => \cb_int_reg[3]_i_16_n_6\,
O => \cb_int[11]_i_104_n_0\
);
\cb_int[11]_i_105\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_7\,
I1 => \cb_int_reg[3]_i_26_n_4\,
O => \cb_int[11]_i_105_n_0\
);
\cb_int[11]_i_106\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_5\,
I1 => \cb_int_reg[3]_i_26_n_6\,
O => \cb_int[11]_i_106_n_0\
);
\cb_int[11]_i_107\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_7\,
I1 => \cb_int_reg[3]_i_20_n_6\,
O => \cb_int[11]_i_107_n_0\
);
\cb_int[11]_i_108\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_7\,
I1 => \cb_int_reg[3]_i_44_n_6\,
O => \cb_int[11]_i_108_n_0\
);
\cb_int[11]_i_109\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_5\,
I1 => \cb_int_reg[3]_i_75_n_4\,
O => \cb_int[11]_i_109_n_0\
);
\cb_int[11]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(9),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(17),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_20_n_0\,
I5 => cb_int_reg2(9),
O => \cb_int[11]_i_11_n_0\
);
\cb_int[11]_i_110\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_7\,
I1 => \cb_int_reg[3]_i_75_n_6\,
O => \cb_int[11]_i_110_n_0\
);
\cb_int[11]_i_111\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_6\,
I1 => \cb_int_reg[3]_i_20_n_7\,
O => \cb_int[11]_i_111_n_0\
);
\cb_int[11]_i_112\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_6\,
I1 => \cb_int_reg[3]_i_44_n_7\,
O => \cb_int[11]_i_112_n_0\
);
\cb_int[11]_i_113\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_4\,
I1 => \cb_int_reg[3]_i_75_n_5\,
O => \cb_int[11]_i_113_n_0\
);
\cb_int[11]_i_114\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_6\,
I1 => \cb_int_reg[3]_i_75_n_7\,
O => \cb_int[11]_i_114_n_0\
);
\cb_int[11]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(9),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(17),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_20_n_0\,
I5 => cb_int_reg2(9),
O => \cb_int[11]_i_12_n_0\
);
\cb_int[11]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(8),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(16),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_22_n_0\,
I5 => cb_int_reg2(8),
O => \cb_int[11]_i_13_n_0\
);
\cb_int[11]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(8),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(16),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_22_n_0\,
I5 => cb_int_reg2(8),
O => \cb_int[11]_i_14_n_0\
);
\cb_int[11]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFE200E2"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(1),
I3 => \rgb888[0]\(3),
I4 => cb_int_reg3(7),
I5 => \cb_int[11]_i_27_n_0\,
O => \cb_int[11]_i_15_n_0\
);
\cb_int[11]_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE200E2001DFF1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(1),
I3 => \rgb888[0]\(3),
I4 => cb_int_reg3(7),
I5 => \cb_int[11]_i_27_n_0\,
O => \cb_int[11]_i_19_n_0\
);
\cb_int[11]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[11]_i_10_n_0\,
I1 => \cb_int[11]_i_11_n_0\,
O => \cb_int[11]_i_2_n_0\
);
\cb_int[11]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_4\(0),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]_0\(0),
O => \cb_int[11]_i_20_n_0\
);
\cb_int[11]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(9),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_4\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(9)
);
\cb_int[11]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_3\(3),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]\(3),
O => \cb_int[11]_i_22_n_0\
);
\cb_int[11]_i_23\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(8),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[11]_i_24_n_4\,
O => cb_int_reg2(8)
);
\cb_int[11]_i_27\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_3\(2),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[12]\(2),
I3 => \^co\(0),
I4 => \rgb888[8]_1\(0),
O => \cb_int[11]_i_27_n_0\
);
\cb_int[11]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(16),
O => \cb_int[11]_i_29_n_0\
);
\cb_int[11]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[11]_i_12_n_0\,
I1 => \cb_int[11]_i_13_n_0\,
O => \cb_int[11]_i_3_n_0\
);
\cb_int[11]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(15),
O => \cb_int[11]_i_30_n_0\
);
\cb_int[11]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(14),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_12_n_6\,
O => \cb_int[11]_i_31_n_0\
);
\cb_int[11]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(13),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_12_n_7\,
O => \cb_int[11]_i_32_n_0\
);
\cb_int[11]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_34_n_0\
);
\cb_int[11]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_35_n_0\
);
\cb_int[11]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_36_n_0\
);
\cb_int[11]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_37_n_0\
);
\cb_int[11]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_39_n_0\
);
\cb_int[11]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[11]_i_14_n_0\,
I1 => \cb_int[11]_i_15_n_0\,
O => \cb_int[11]_i_4_n_0\
);
\cb_int[11]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_40_n_0\
);
\cb_int[11]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_41_n_0\
);
\cb_int[11]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_42_n_0\
);
\cb_int[11]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_43_n_0\
);
\cb_int[11]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(2),
O => \cb_int[11]_i_44_n_0\
);
\cb_int[11]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(1),
O => \cb_int[11]_i_45_n_0\
);
\cb_int[11]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(0),
O => \cb_int[11]_i_46_n_0\
);
\cb_int[11]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(3),
O => \cb_int[11]_i_47_n_0\
);
\cb_int[11]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_49_n_0\
);
\cb_int[11]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"DD1D0000"
)
port map (
I0 => cb_int_reg5(7),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(15),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_19_n_0\,
O => \cb_int[11]_i_5_n_0\
);
\cb_int[11]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_50_n_0\
);
\cb_int[11]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_51_n_0\
);
\cb_int[11]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_52_n_0\
);
\cb_int[11]_i_53\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_4\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(2),
O => \cb_int[11]_i_53_n_0\
);
\cb_int[11]_i_54\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(1),
O => \cb_int[11]_i_54_n_0\
);
\cb_int[11]_i_55\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_6\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(0),
O => \cb_int[11]_i_55_n_0\
);
\cb_int[11]_i_56\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_7\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_0\(3),
O => \cb_int[11]_i_56_n_0\
);
\cb_int[11]_i_57\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(8),
I1 => cb_int_reg8,
I2 => \cb_int_reg[3]_i_16_n_4\,
O => \cb_int[11]_i_57_n_0\
);
\cb_int[11]_i_58\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(12),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_4\,
O => \cb_int[11]_i_58_n_0\
);
\cb_int[11]_i_59\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(11),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_5\,
O => \cb_int[11]_i_59_n_0\
);
\cb_int[11]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[15]_i_16_n_0\,
I1 => \cb_int[15]_i_17_n_0\,
I2 => \cb_int[11]_i_2_n_0\,
O => \cb_int[11]_i_6_n_0\
);
\cb_int[11]_i_60\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(10),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_6\,
O => \cb_int[11]_i_60_n_0\
);
\cb_int[11]_i_61\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(9),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_7\,
O => \cb_int[11]_i_61_n_0\
);
\cb_int[11]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_6\,
O => \cb_int[11]_i_62_n_0\
);
\cb_int[11]_i_63\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_7\,
O => \cb_int[11]_i_63_n_0\
);
\cb_int[11]_i_64\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_4\,
O => \cb_int[11]_i_64_n_0\
);
\cb_int[11]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_5\,
O => \cb_int[11]_i_65_n_0\
);
\cb_int[11]_i_67\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_67_n_0\
);
\cb_int[11]_i_68\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_68_n_0\
);
\cb_int[11]_i_69\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_69_n_0\
);
\cb_int[11]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[11]_i_10_n_0\,
I1 => \cb_int[11]_i_11_n_0\,
I2 => \cb_int[11]_i_3_n_0\,
O => \cb_int[11]_i_7_n_0\
);
\cb_int[11]_i_70\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_70_n_0\
);
\cb_int[11]_i_71\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_71_n_0\
);
\cb_int[11]_i_72\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_72_n_0\
);
\cb_int[11]_i_73\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_73_n_0\
);
\cb_int[11]_i_74\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_74_n_0\
);
\cb_int[11]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[0]\(2),
I1 => \rgb888[0]\(3),
O => \cb_int[11]_i_76_n_0\
);
\cb_int[11]_i_77\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_77_n_0\
);
\cb_int[11]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_78_n_0\
);
\cb_int[11]_i_79\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_79_n_0\
);
\cb_int[11]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[11]_i_12_n_0\,
I1 => \cb_int[11]_i_13_n_0\,
I2 => \cb_int[11]_i_4_n_0\,
O => \cb_int[11]_i_8_n_0\
);
\cb_int[11]_i_80\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \rgb888[0]\(2),
O => \cb_int[11]_i_80_n_0\
);
\cb_int[11]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_82_n_0\
);
\cb_int[11]_i_83\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_6\,
I1 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_83_n_0\
);
\cb_int[11]_i_84\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_4\,
I1 => \cb_int_reg[31]_i_12_n_7\,
O => \cb_int[11]_i_84_n_0\
);
\cb_int[11]_i_85\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_6\,
I1 => \cb_int_reg[31]_i_33_n_5\,
O => \cb_int[11]_i_85_n_0\
);
\cb_int[11]_i_86\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_86_n_0\
);
\cb_int[11]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => \cb_int_reg[31]_i_12_n_6\,
O => \cb_int[11]_i_87_n_0\
);
\cb_int[11]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_7\,
I1 => \cb_int_reg[31]_i_33_n_4\,
O => \cb_int[11]_i_88_n_0\
);
\cb_int[11]_i_89\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_5\,
I1 => \cb_int_reg[31]_i_33_n_6\,
O => \cb_int[11]_i_89_n_0\
);
\cb_int[11]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[11]_i_14_n_0\,
I1 => \cb_int[11]_i_15_n_0\,
I2 => \cb_int[11]_i_5_n_0\,
O => \cb_int[11]_i_9_n_0\
);
\cb_int[11]_i_91\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[0]\(0),
I1 => \rgb888[0]\(1),
O => \cb_int[11]_i_91_n_0\
);
\cb_int[11]_i_92\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[0]_0\(2),
I1 => \rgb888[0]_0\(3),
O => \cb_int[11]_i_92_n_0\
);
\cb_int[11]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[0]_0\(0),
I1 => \rgb888[0]_0\(1),
O => \cb_int[11]_i_93_n_0\
);
\cb_int[11]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_5\,
I1 => \cb_int_reg[3]_i_20_n_4\,
O => \cb_int[11]_i_94_n_0\
);
\cb_int[11]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(1),
I1 => \rgb888[0]\(0),
O => \cb_int[11]_i_95_n_0\
);
\cb_int[11]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(3),
I1 => \rgb888[0]_0\(2),
O => \cb_int[11]_i_96_n_0\
);
\cb_int[11]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(1),
I1 => \rgb888[0]_0\(0),
O => \cb_int[11]_i_97_n_0\
);
\cb_int[11]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_4\,
I1 => \cb_int_reg[3]_i_20_n_5\,
O => \cb_int[11]_i_98_n_0\
);
\cb_int[11]_i_99\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_4\,
I1 => \cb_int_reg[31]_i_33_n_7\,
O => \cb_int[11]_i_99_n_0\
);
\cb_int[15]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(14),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(22),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_26_n_0\,
I5 => cb_int_reg2(14),
O => \cb_int[15]_i_10_n_0\
);
\cb_int[15]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(13),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(21),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_18_n_0\,
I5 => cb_int_reg2(13),
O => \cb_int[15]_i_11_n_0\
);
\cb_int[15]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(13),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(21),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_18_n_0\,
I5 => cb_int_reg2(13),
O => \cb_int[15]_i_12_n_0\
);
\cb_int[15]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(12),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(20),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_21_n_0\,
I5 => cb_int_reg2(12),
O => \cb_int[15]_i_13_n_0\
);
\cb_int[15]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(12),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(20),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_21_n_0\,
I5 => cb_int_reg2(12),
O => \cb_int[15]_i_14_n_0\
);
\cb_int[15]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(11),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(19),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_23_n_0\,
I5 => cb_int_reg2(11),
O => \cb_int[15]_i_15_n_0\
);
\cb_int[15]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(11),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(19),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_23_n_0\,
I5 => cb_int_reg2(11),
O => \cb_int[15]_i_16_n_0\
);
\cb_int[15]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(10),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(18),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_25_n_0\,
I5 => cb_int_reg2(10),
O => \cb_int[15]_i_17_n_0\
);
\cb_int[15]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_5\(0),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_6\(0),
O => \cb_int[15]_i_18_n_0\
);
\cb_int[15]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(13),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_3\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(13)
);
\cb_int[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[15]_i_10_n_0\,
I1 => \cb_int[15]_i_11_n_0\,
O => \cb_int[15]_i_2_n_0\
);
\cb_int[15]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_4\(3),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]_0\(3),
O => \cb_int[15]_i_21_n_0\
);
\cb_int[15]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(12),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_4\(3),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(12)
);
\cb_int[15]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_4\(2),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]_0\(2),
O => \cb_int[15]_i_23_n_0\
);
\cb_int[15]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(11),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_4\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(11)
);
\cb_int[15]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_4\(1),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]_0\(1),
O => \cb_int[15]_i_25_n_0\
);
\cb_int[15]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(10),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_4\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(10)
);
\cb_int[15]_i_27\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(20),
O => \cb_int[15]_i_27_n_0\
);
\cb_int[15]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(19),
O => \cb_int[15]_i_28_n_0\
);
\cb_int[15]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(18),
O => \cb_int[15]_i_29_n_0\
);
\cb_int[15]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[15]_i_12_n_0\,
I1 => \cb_int[15]_i_13_n_0\,
O => \cb_int[15]_i_3_n_0\
);
\cb_int[15]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(17),
O => \cb_int[15]_i_30_n_0\
);
\cb_int[15]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[15]_i_14_n_0\,
I1 => \cb_int[15]_i_15_n_0\,
O => \cb_int[15]_i_4_n_0\
);
\cb_int[15]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_4\(3),
O => \cb_int[15]_i_43_n_0\
);
\cb_int[15]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_4\(2),
O => \cb_int[15]_i_44_n_0\
);
\cb_int[15]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_4\(1),
O => \cb_int[15]_i_45_n_0\
);
\cb_int[15]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_4\(0),
O => \cb_int[15]_i_46_n_0\
);
\cb_int[15]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[15]_i_16_n_0\,
I1 => \cb_int[15]_i_17_n_0\,
O => \cb_int[15]_i_5_n_0\
);
\cb_int[15]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[19]_i_16_n_0\,
I1 => \cb_int[19]_i_17_n_0\,
I2 => \cb_int[15]_i_2_n_0\,
O => \cb_int[15]_i_6_n_0\
);
\cb_int[15]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[15]_i_10_n_0\,
I1 => \cb_int[15]_i_11_n_0\,
I2 => \cb_int[15]_i_3_n_0\,
O => \cb_int[15]_i_7_n_0\
);
\cb_int[15]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[15]_i_12_n_0\,
I1 => \cb_int[15]_i_13_n_0\,
I2 => \cb_int[15]_i_4_n_0\,
O => \cb_int[15]_i_8_n_0\
);
\cb_int[15]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[15]_i_14_n_0\,
I1 => \cb_int[15]_i_15_n_0\,
I2 => \cb_int[15]_i_5_n_0\,
O => \cb_int[15]_i_9_n_0\
);
\cb_int[19]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(18),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(26),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_25_n_0\,
I5 => cb_int_reg2(18),
O => \cb_int[19]_i_10_n_0\
);
\cb_int[19]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(17),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(25),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_18_n_0\,
I5 => cb_int_reg2(17),
O => \cb_int[19]_i_11_n_0\
);
\cb_int[19]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(17),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(25),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_18_n_0\,
I5 => cb_int_reg2(17),
O => \cb_int[19]_i_12_n_0\
);
\cb_int[19]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(16),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(24),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_21_n_0\,
I5 => cb_int_reg2(16),
O => \cb_int[19]_i_13_n_0\
);
\cb_int[19]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(16),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(24),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_21_n_0\,
I5 => cb_int_reg2(16),
O => \cb_int[19]_i_14_n_0\
);
\cb_int[19]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(15),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(23),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_23_n_0\,
I5 => cb_int_reg2(15),
O => \cb_int[19]_i_15_n_0\
);
\cb_int[19]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(15),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(23),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_23_n_0\,
I5 => cb_int_reg2(15),
O => \cb_int[19]_i_16_n_0\
);
\cb_int[19]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(14),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(22),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_26_n_0\,
I5 => cb_int_reg2(14),
O => \cb_int[19]_i_17_n_0\
);
\cb_int[19]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_7\(0),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_8\(0),
O => \cb_int[19]_i_18_n_0\
);
\cb_int[19]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(17),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_2\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(17)
);
\cb_int[19]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[19]_i_10_n_0\,
I1 => \cb_int[19]_i_11_n_0\,
O => \cb_int[19]_i_2_n_0\
);
\cb_int[19]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_5\(3),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_6\(3),
O => \cb_int[19]_i_21_n_0\
);
\cb_int[19]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(16),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_3\(3),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(16)
);
\cb_int[19]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_5\(2),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_6\(2),
O => \cb_int[19]_i_23_n_0\
);
\cb_int[19]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(15),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_3\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(15)
);
\cb_int[19]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_5\(1),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_6\(1),
O => \cb_int[19]_i_26_n_0\
);
\cb_int[19]_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(14),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_3\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(14)
);
\cb_int[19]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(24),
O => \cb_int[19]_i_28_n_0\
);
\cb_int[19]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(23),
O => \cb_int[19]_i_29_n_0\
);
\cb_int[19]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[19]_i_12_n_0\,
I1 => \cb_int[19]_i_13_n_0\,
O => \cb_int[19]_i_3_n_0\
);
\cb_int[19]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(22),
O => \cb_int[19]_i_30_n_0\
);
\cb_int[19]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(21),
O => \cb_int[19]_i_31_n_0\
);
\cb_int[19]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[19]_i_34_n_0\
);
\cb_int[19]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[19]_i_35_n_0\
);
\cb_int[19]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[19]_i_36_n_0\
);
\cb_int[19]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[19]_i_37_n_0\
);
\cb_int[19]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[19]_i_14_n_0\,
I1 => \cb_int[19]_i_15_n_0\,
O => \cb_int[19]_i_4_n_0\
);
\cb_int[19]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[19]_i_16_n_0\,
I1 => \cb_int[19]_i_17_n_0\,
O => \cb_int[19]_i_5_n_0\
);
\cb_int[19]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[23]_i_16_n_0\,
I1 => \cb_int[23]_i_17_n_0\,
I2 => \cb_int[19]_i_2_n_0\,
O => \cb_int[19]_i_6_n_0\
);
\cb_int[19]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[19]_i_10_n_0\,
I1 => \cb_int[19]_i_11_n_0\,
I2 => \cb_int[19]_i_3_n_0\,
O => \cb_int[19]_i_7_n_0\
);
\cb_int[19]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[19]_i_12_n_0\,
I1 => \cb_int[19]_i_13_n_0\,
I2 => \cb_int[19]_i_4_n_0\,
O => \cb_int[19]_i_8_n_0\
);
\cb_int[19]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[19]_i_14_n_0\,
I1 => \cb_int[19]_i_15_n_0\,
I2 => \cb_int[19]_i_5_n_0\,
O => \cb_int[19]_i_9_n_0\
);
\cb_int[23]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(22),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(30),
I3 => cb_int_reg8,
I4 => \cb_int[27]_i_10_n_0\,
I5 => cb_int_reg2(22),
O => \cb_int[23]_i_10_n_0\
);
\cb_int[23]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(21),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(29),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_18_n_0\,
I5 => cb_int_reg2(21),
O => \cb_int[23]_i_11_n_0\
);
\cb_int[23]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(21),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(29),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_18_n_0\,
I5 => cb_int_reg2(21),
O => \cb_int[23]_i_12_n_0\
);
\cb_int[23]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(20),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(28),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_20_n_0\,
I5 => cb_int_reg2(20),
O => \cb_int[23]_i_13_n_0\
);
\cb_int[23]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(20),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(28),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_20_n_0\,
I5 => cb_int_reg2(20),
O => \cb_int[23]_i_14_n_0\
);
\cb_int[23]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(19),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(27),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_22_n_0\,
I5 => cb_int_reg2(19),
O => \cb_int[23]_i_15_n_0\
);
\cb_int[23]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(19),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(27),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_22_n_0\,
I5 => cb_int_reg2(19),
O => \cb_int[23]_i_16_n_0\
);
\cb_int[23]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(18),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(26),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_25_n_0\,
I5 => cb_int_reg2(18),
O => \cb_int[23]_i_17_n_0\
);
\cb_int[23]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_9\(0),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_10\(0),
O => \cb_int[23]_i_18_n_0\
);
\cb_int[23]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(21),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_1\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(21)
);
\cb_int[23]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[23]_i_10_n_0\,
I1 => \cb_int[23]_i_11_n_0\,
O => \cb_int[23]_i_2_n_0\
);
\cb_int[23]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_7\(3),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_8\(3),
O => \cb_int[23]_i_20_n_0\
);
\cb_int[23]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(20),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_2\(3),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(20)
);
\cb_int[23]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_7\(2),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_8\(2),
O => \cb_int[23]_i_22_n_0\
);
\cb_int[23]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(19),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_2\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(19)
);
\cb_int[23]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_7\(1),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_8\(1),
O => \cb_int[23]_i_25_n_0\
);
\cb_int[23]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(18),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_2\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(18)
);
\cb_int[23]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[23]_i_29_n_0\
);
\cb_int[23]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[23]_i_12_n_0\,
I1 => \cb_int[23]_i_13_n_0\,
O => \cb_int[23]_i_3_n_0\
);
\cb_int[23]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[23]_i_30_n_0\
);
\cb_int[23]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[23]_i_31_n_0\
);
\cb_int[23]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[23]_i_32_n_0\
);
\cb_int[23]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[23]_i_14_n_0\,
I1 => \cb_int[23]_i_15_n_0\,
O => \cb_int[23]_i_4_n_0\
);
\cb_int[23]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[23]_i_16_n_0\,
I1 => \cb_int[23]_i_17_n_0\,
O => \cb_int[23]_i_5_n_0\
);
\cb_int[23]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[27]_i_7_n_0\,
I1 => \cb_int[27]_i_8_n_0\,
I2 => \cb_int[23]_i_2_n_0\,
O => \cb_int[23]_i_6_n_0\
);
\cb_int[23]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[23]_i_10_n_0\,
I1 => \cb_int[23]_i_11_n_0\,
I2 => \cb_int[23]_i_3_n_0\,
O => \cb_int[23]_i_7_n_0\
);
\cb_int[23]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[23]_i_12_n_0\,
I1 => \cb_int[23]_i_13_n_0\,
I2 => \cb_int[23]_i_4_n_0\,
O => \cb_int[23]_i_8_n_0\
);
\cb_int[23]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[23]_i_14_n_0\,
I1 => \cb_int[23]_i_15_n_0\,
I2 => \cb_int[23]_i_5_n_0\,
O => \cb_int[23]_i_9_n_0\
);
\cb_int[27]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_9\(1),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_10\(1),
O => \cb_int[27]_i_10_n_0\
);
\cb_int[27]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(22),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_1\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(22)
);
\cb_int[27]_i_12\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[27]_i_12_n_0\
);
\cb_int[27]_i_13\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[27]_i_13_n_0\
);
\cb_int[27]_i_14\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[27]_i_14_n_0\
);
\cb_int[27]_i_15\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[27]_i_15_n_0\
);
\cb_int[27]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[27]_i_7_n_0\,
I1 => \cb_int[27]_i_8_n_0\,
O => \cb_int[27]_i_2_n_0\
);
\cb_int[27]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_3_n_0\
);
\cb_int[27]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_4_n_0\
);
\cb_int[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_5_n_0\
);
\cb_int[27]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[27]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_6_n_0\
);
\cb_int[27]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"1E111E11E1EE1E11"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => \cb_int_reg[31]_i_11_n_1\,
I2 => \rgb888[8]_11\(0),
I3 => \rgb888[8]_1\(1),
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_7_n_0\
);
\cb_int[27]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(22),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(30),
I3 => cb_int_reg8,
I4 => \cb_int[27]_i_10_n_0\,
I5 => cb_int_reg2(22),
O => \cb_int[27]_i_8_n_0\
);
\cb_int[31]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \rgb888[8]_11\(0),
I1 => \rgb888[8]_1\(1),
O => \cb_int[31]_i_13_n_0\
);
\cb_int[31]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_1\(1),
O => \cb_int[31]_i_15_n_0\
);
\cb_int[31]_i_16\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_1\(0),
O => \cb_int[31]_i_16_n_0\
);
\cb_int[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"4404440444040000"
)
port map (
I0 => \cb_int_reg[31]_i_7_n_1\,
I1 => \rgb888[0]\(3),
I2 => \rgb888[8]_1\(1),
I3 => \rgb888[8]_11\(0),
I4 => \cb_int_reg[31]_i_11_n_1\,
I5 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[31]_i_2_n_0\
);
\cb_int[31]_i_24\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \^di\(0)
);
\cb_int[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[31]_i_3_n_0\
);
\cb_int[31]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(30),
O => \cb_int[31]_i_31_n_0\
);
\cb_int[31]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(29),
O => \cb_int[31]_i_32_n_0\
);
\cb_int[31]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_34_n_2\,
O => \cb_int[31]_i_35_n_0\
);
\cb_int[31]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_34_n_2\,
O => \cb_int[31]_i_36_n_0\
);
\cb_int[31]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_2\(3),
O => \cb_int[31]_i_38_n_0\
);
\cb_int[31]_i_39\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_2\(2),
O => \cb_int[31]_i_39_n_0\
);
\cb_int[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[31]_i_4_n_0\
);
\cb_int[31]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_2\(1),
O => \cb_int[31]_i_40_n_0\
);
\cb_int[31]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_2\(0),
O => \cb_int[31]_i_41_n_0\
);
\cb_int[31]_i_43\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000001FFFFFFFE"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
I2 => rgb888(1),
I3 => rgb888(2),
I4 => rgb888(4),
I5 => rgb888(6),
O => \^cr_int_reg[27]_1\(1)
);
\cb_int[31]_i_44\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFE"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
I2 => rgb888(1),
I3 => rgb888(3),
I4 => rgb888(5),
O => \^cr_int_reg[27]_1\(0)
);
\cb_int[31]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[31]_i_5_n_0\
);
\cb_int[31]_i_51\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
I2 => rgb888(1),
I3 => rgb888(2),
I4 => rgb888(4),
I5 => rgb888(6),
O => \^cr_int_reg[27]_0\
);
\cb_int[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[31]_i_6_n_0\
);
\cb_int[31]_i_67\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(28),
O => \cb_int[31]_i_67_n_0\
);
\cb_int[31]_i_68\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(27),
O => \cb_int[31]_i_68_n_0\
);
\cb_int[31]_i_69\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(26),
O => \cb_int[31]_i_69_n_0\
);
\cb_int[31]_i_70\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(25),
O => \cb_int[31]_i_70_n_0\
);
\cb_int[31]_i_71\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_5\,
I1 => rgb888(23),
I2 => rgb888(22),
O => \cb_int[31]_i_71_n_0\
);
\cb_int[31]_i_72\: unisim.vcomponents.LUT3
generic map(
INIT => X"82"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_6\,
I1 => rgb888(23),
I2 => rgb888(22),
O => \cb_int[31]_i_72_n_0\
);
\cb_int[31]_i_74\: unisim.vcomponents.LUT4
generic map(
INIT => X"1FE0"
)
port map (
I0 => rgb888(22),
I1 => rgb888(23),
I2 => \cb_int_reg[31]_i_73_n_4\,
I3 => \cb_int_reg[31]_i_34_n_7\,
O => \cb_int[31]_i_74_n_0\
);
\cb_int[31]_i_75\: unisim.vcomponents.LUT4
generic map(
INIT => X"3336"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_5\,
I1 => \cb_int_reg[31]_i_73_n_4\,
I2 => rgb888(22),
I3 => rgb888(23),
O => \cb_int[31]_i_75_n_0\
);
\cb_int[31]_i_76\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_6\,
I1 => rgb888(22),
I2 => rgb888(23),
I3 => \cb_int_reg[31]_i_73_n_5\,
O => \cb_int[31]_i_76_n_0\
);
\cb_int[31]_i_77\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_7\,
I1 => \cb_int_reg[31]_i_73_n_6\,
I2 => rgb888(22),
I3 => rgb888(23),
O => \cb_int[31]_i_77_n_0\
);
\cb_int[31]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(23),
O => \cb_int[31]_i_78_n_0\
);
\cb_int[31]_i_79\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_3\(3),
O => \cb_int[31]_i_79_n_0\
);
\cb_int[31]_i_80\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_3\(2),
O => \cb_int[31]_i_80_n_0\
);
\cb_int[31]_i_81\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_3\(1),
O => \cb_int[31]_i_81_n_0\
);
\cb_int[31]_i_82\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_3\(0),
O => \cb_int[31]_i_82_n_0\
);
\cb_int[31]_i_86\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => rgb888(11),
I1 => rgb888(10),
I2 => rgb888(12),
I3 => rgb888(13),
O => \^cr_int_reg[31]_1\
);
\cb_int[31]_i_87\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => rgb888(12),
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(13),
I4 => rgb888(14),
O => \^cr_int_reg[31]_0\
);
\cb_int[31]_i_95\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(22),
O => \cb_int[31]_i_95_n_0\
);
\cb_int[31]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(23),
I1 => rgb888(21),
O => \cb_int[31]_i_96_n_0\
);
\cb_int[31]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(22),
I1 => rgb888(20),
O => \cb_int[31]_i_97_n_0\
);
\cb_int[31]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(21),
I1 => rgb888(19),
O => \cb_int[31]_i_98_n_0\
);
\cb_int[3]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_2\(1),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[13]_0\(1),
I3 => \^co\(0),
I4 => \rgb888[8]\(3),
O => \cb_int[3]_i_10_n_0\
);
\cb_int[3]_i_100\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(0),
I1 => rgb888(2),
O => \cb_int[3]_i_100_n_0\
);
\cb_int[3]_i_101\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
O => \cb_int[3]_i_101_n_0\
);
\cb_int[3]_i_102\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(0),
O => \cb_int[3]_i_102_n_0\
);
\cb_int[3]_i_103\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(8),
I1 => rgb888(11),
O => \cb_int[3]_i_103_n_0\
);
\cb_int[3]_i_104\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(10),
O => \cb_int[3]_i_104_n_0\
);
\cb_int[3]_i_105\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(9),
O => \cb_int[3]_i_105_n_0\
);
\cb_int[3]_i_106\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(8),
O => \cb_int[3]_i_106_n_0\
);
\cb_int[3]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(2),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_0\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[7]_i_29_n_6\,
O => cb_int_reg2(2)
);
\cb_int[3]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(9),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_7\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(1),
O => \cb_int[3]_i_12_n_0\
);
\cb_int[3]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_2\(0),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[13]_0\(0),
I3 => \^co\(0),
I4 => \rgb888[8]\(2),
O => \cb_int[3]_i_13_n_0\
);
\cb_int[3]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(1),
I1 => \rgb888[0]\(3),
I2 => \cb_int_reg[3]_i_20_n_4\,
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[7]_i_29_n_7\,
O => cb_int_reg2(1)
);
\cb_int[3]_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \rgb888[8]\(1),
I1 => \^co\(0),
I2 => \rgb888[13]\(0),
O => \cb_int[3]_i_17_n_0\
);
\cb_int[3]_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \cb_int_reg[3]_i_33_n_4\,
O => \cb_int[3]_i_18_n_0\
);
\cb_int[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[3]_i_9_n_0\,
I1 => \cb_int[3]_i_10_n_0\,
I2 => cb_int_reg2(2),
O => \cb_int[3]_i_2_n_0\
);
\cb_int[3]_i_22\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_6\,
O => \cb_int[3]_i_22_n_0\
);
\cb_int[3]_i_23\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_7\,
O => \cb_int[3]_i_23_n_0\
);
\cb_int[3]_i_24\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_4\,
O => \cb_int[3]_i_24_n_0\
);
\cb_int[3]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_5\,
O => \cb_int[3]_i_25_n_0\
);
\cb_int[3]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_7\,
O => \cb_int[3]_i_27_n_0\
);
\cb_int[3]_i_28\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_7\,
I1 => rgb888(22),
O => \cb_int[3]_i_28_n_0\
);
\cb_int[3]_i_29\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(21),
I1 => \cb_int_reg[3]_i_57_n_4\,
O => \cb_int[3]_i_29_n_0\
);
\cb_int[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[3]_i_12_n_0\,
I1 => \cb_int[3]_i_13_n_0\,
I2 => cb_int_reg2(1),
O => \cb_int[3]_i_3_n_0\
);
\cb_int[3]_i_30\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(20),
I1 => \cb_int_reg[3]_i_57_n_5\,
O => \cb_int[3]_i_30_n_0\
);
\cb_int[3]_i_31\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(19),
I1 => \cb_int_reg[3]_i_57_n_6\,
O => \cb_int[3]_i_31_n_0\
);
\cb_int[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"1DFF001D"
)
port map (
I0 => cb_int_reg7(8),
I1 => cb_int_reg8,
I2 => \cb_int_reg[3]_i_16_n_4\,
I3 => \cb_int[3]_i_17_n_0\,
I4 => \cb_int[3]_i_18_n_0\,
O => \cb_int[3]_i_4_n_0\
);
\cb_int[3]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(2),
I1 => rgb888(1),
I2 => \rgb888[0]_8\(1),
O => \cb_int[3]_i_45_n_0\
);
\cb_int[3]_i_46\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \rgb888[0]_8\(0),
I1 => rgb888(1),
O => \cb_int[3]_i_46_n_0\
);
\cb_int[3]_i_47\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_4\,
I1 => rgb888(0),
O => \cb_int[3]_i_47_n_0\
);
\cb_int[3]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_5\,
O => \cb_int[3]_i_48_n_0\
);
\cb_int[3]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_6\,
O => \cb_int[3]_i_49_n_0\
);
\cb_int[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[7]_i_16_n_0\,
I1 => \cb_int[7]_i_17_n_0\,
I2 => cb_int_reg2(3),
I3 => \cb_int[3]_i_2_n_0\,
O => \cb_int[3]_i_5_n_0\
);
\cb_int[3]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_6\,
O => \cb_int[3]_i_50_n_0\
);
\cb_int[3]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_7\,
O => \cb_int[3]_i_51_n_0\
);
\cb_int[3]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_4\,
O => \cb_int[3]_i_52_n_0\
);
\cb_int[3]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_5\,
O => \cb_int[3]_i_53_n_0\
);
\cb_int[3]_i_54\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(18),
I1 => \cb_int_reg[3]_i_57_n_7\,
O => \cb_int[3]_i_54_n_0\
);
\cb_int[3]_i_55\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(17),
I1 => rgb888(16),
O => \cb_int[3]_i_55_n_0\
);
\cb_int[3]_i_56\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(16),
O => \cb_int[3]_i_56_n_0\
);
\cb_int[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[3]_i_9_n_0\,
I1 => \cb_int[3]_i_10_n_0\,
I2 => cb_int_reg2(2),
I3 => \cb_int[3]_i_3_n_0\,
O => \cb_int[3]_i_6_n_0\
);
\cb_int[3]_i_64\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_5\,
O => \cb_int[3]_i_64_n_0\
);
\cb_int[3]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_6\,
O => \cb_int[3]_i_65_n_0\
);
\cb_int[3]_i_66\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_7\,
O => \cb_int[3]_i_66_n_0\
);
\cb_int[3]_i_67\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_6\,
O => \cb_int[3]_i_67_n_0\
);
\cb_int[3]_i_69\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(8),
I1 => rgb888(10),
I2 => \rgb888[8]_31\(2),
O => \cb_int[3]_i_69_n_0\
);
\cb_int[3]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[3]_i_12_n_0\,
I1 => \cb_int[3]_i_13_n_0\,
I2 => cb_int_reg2(1),
I3 => \cb_int[3]_i_4_n_0\,
O => \cb_int[3]_i_7_n_0\
);
\cb_int[3]_i_70\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_31\(1),
I1 => rgb888(9),
O => \cb_int[3]_i_70_n_0\
);
\cb_int[3]_i_71\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_31\(0),
I1 => rgb888(8),
O => \cb_int[3]_i_71_n_0\
);
\cb_int[3]_i_72\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[3]_i_94_n_4\,
O => \cb_int[3]_i_72_n_0\
);
\cb_int[3]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(7),
I1 => rgb888(5),
O => \cb_int[3]_i_76_n_0\
);
\cb_int[3]_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
O => \cb_int[3]_i_77_n_0\
);
\cb_int[3]_i_78\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
O => \cb_int[3]_i_78_n_0\
);
\cb_int[3]_i_79\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
O => \cb_int[3]_i_79_n_0\
);
\cb_int[3]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"1DE2E21D"
)
port map (
I0 => cb_int_reg7(8),
I1 => cb_int_reg8,
I2 => \cb_int_reg[3]_i_16_n_4\,
I3 => \cb_int[3]_i_17_n_0\,
I4 => \cb_int[3]_i_18_n_0\,
O => \cb_int[3]_i_8_n_0\
);
\cb_int[3]_i_80\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
O => \cb_int[3]_i_80_n_0\
);
\cb_int[3]_i_81\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(19),
I1 => rgb888(17),
O => \cb_int[3]_i_81_n_0\
);
\cb_int[3]_i_82\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(18),
I1 => rgb888(16),
O => \cb_int[3]_i_82_n_0\
);
\cb_int[3]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(17),
O => \cb_int[3]_i_83_n_0\
);
\cb_int[3]_i_89\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_7\,
O => \cb_int[3]_i_89_n_0\
);
\cb_int[3]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(10),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_6\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(2),
O => \cb_int[3]_i_9_n_0\
);
\cb_int[3]_i_90\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_7\,
O => \cb_int[3]_i_90_n_0\
);
\cb_int[3]_i_91\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_4\,
O => \cb_int[3]_i_91_n_0\
);
\cb_int[3]_i_92\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_5\,
O => \cb_int[3]_i_92_n_0\
);
\cb_int[3]_i_93\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_6\,
O => \cb_int[3]_i_93_n_0\
);
\cb_int[3]_i_99\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
O => \cb_int[3]_i_99_n_0\
);
\cb_int[7]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(13),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_12_n_7\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(5),
O => \cb_int[7]_i_10_n_0\
);
\cb_int[7]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_3\(0),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[12]\(0),
I3 => \^co\(0),
I4 => \rgb888[8]_0\(2),
O => \cb_int[7]_i_11_n_0\
);
\cb_int[7]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(5),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_0\(3),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[11]_i_24_n_7\,
O => cb_int_reg2(5)
);
\cb_int[7]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(12),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_4\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(4),
O => \cb_int[7]_i_13_n_0\
);
\cb_int[7]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_2\(3),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[13]_0\(3),
I3 => \^co\(0),
I4 => \rgb888[8]_0\(1),
O => \cb_int[7]_i_14_n_0\
);
\cb_int[7]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(4),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_0\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[7]_i_29_n_4\,
O => cb_int_reg2(4)
);
\cb_int[7]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(11),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_5\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(3),
O => \cb_int[7]_i_16_n_0\
);
\cb_int[7]_i_17\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_2\(2),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[13]_0\(2),
I3 => \^co\(0),
I4 => \rgb888[8]_0\(0),
O => \cb_int[7]_i_17_n_0\
);
\cb_int[7]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(3),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_0\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[7]_i_29_n_5\,
O => cb_int_reg2(3)
);
\cb_int[7]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0BF"
)
port map (
I0 => cb_int_reg8,
I1 => cb_int_reg7(15),
I2 => \cb_int_reg[31]_i_12_n_1\,
I3 => cb_int_reg5(7),
O => \cb_int[7]_i_19_n_0\
);
\cb_int[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"5959A959"
)
port map (
I0 => \cb_int[11]_i_19_n_0\,
I1 => cb_int_reg5(7),
I2 => \cb_int_reg[31]_i_12_n_1\,
I3 => cb_int_reg7(15),
I4 => cb_int_reg8,
O => \cb_int[7]_i_2_n_0\
);
\cb_int[7]_i_20\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(6),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[11]_i_24_n_6\,
O => cb_int_reg2(6)
);
\cb_int[7]_i_21\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_3\(1),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[12]\(1),
I3 => \^co\(0),
I4 => \rgb888[8]_0\(3),
O => \cb_int[7]_i_21_n_0\
);
\cb_int[7]_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(14),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_12_n_6\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(6),
O => \cb_int[7]_i_22_n_0\
);
\cb_int[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[7]_i_10_n_0\,
I1 => \cb_int[7]_i_11_n_0\,
I2 => cb_int_reg2(5),
O => \cb_int[7]_i_3_n_0\
);
\cb_int[7]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_39_n_0\
);
\cb_int[7]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[7]_i_13_n_0\,
I1 => \cb_int[7]_i_14_n_0\,
I2 => cb_int_reg2(4),
O => \cb_int[7]_i_4_n_0\
);
\cb_int[7]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_40_n_0\
);
\cb_int[7]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_41_n_0\
);
\cb_int[7]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_42_n_0\
);
\cb_int[7]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[7]_i_16_n_0\,
I1 => \cb_int[7]_i_17_n_0\,
I2 => cb_int_reg2(3),
O => \cb_int[7]_i_5_n_0\
);
\cb_int[7]_i_52\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[3]_i_33_n_4\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \cb_int_reg[3]_i_20_n_5\,
O => \cb_int[7]_i_52_n_0\
);
\cb_int[7]_i_53\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_29_n_4\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_0\(2),
O => \cb_int[7]_i_53_n_0\
);
\cb_int[7]_i_54\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_29_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_0\(1),
O => \cb_int[7]_i_54_n_0\
);
\cb_int[7]_i_55\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_29_n_6\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_0\(0),
O => \cb_int[7]_i_55_n_0\
);
\cb_int[7]_i_56\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_29_n_7\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \cb_int_reg[3]_i_20_n_4\,
O => \cb_int[7]_i_56_n_0\
);
\cb_int[7]_i_57\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(2),
O => \cb_int[7]_i_57_n_0\
);
\cb_int[7]_i_58\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(1),
O => \cb_int[7]_i_58_n_0\
);
\cb_int[7]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(0),
O => \cb_int[7]_i_59_n_0\
);
\cb_int[7]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"99969666"
)
port map (
I0 => \cb_int[7]_i_19_n_0\,
I1 => \cb_int[11]_i_19_n_0\,
I2 => cb_int_reg2(6),
I3 => \cb_int[7]_i_21_n_0\,
I4 => \cb_int[7]_i_22_n_0\,
O => \cb_int[7]_i_6_n_0\
);
\cb_int[7]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_4\,
O => \cb_int[7]_i_60_n_0\
);
\cb_int[7]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_62_n_0\
);
\cb_int[7]_i_63\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_63_n_0\
);
\cb_int[7]_i_64\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_64_n_0\
);
\cb_int[7]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_65_n_0\
);
\cb_int[7]_i_67\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_0\(3),
I1 => \rgb888[8]_1\(0),
O => \cb_int[7]_i_67_n_0\
);
\cb_int[7]_i_68\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_0\(1),
I1 => \rgb888[8]_0\(2),
O => \cb_int[7]_i_68_n_0\
);
\cb_int[7]_i_69\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]\(3),
I1 => \rgb888[8]_0\(0),
O => \cb_int[7]_i_69_n_0\
);
\cb_int[7]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[7]_i_3_n_0\,
I1 => cb_int_reg2(6),
I2 => \cb_int[7]_i_21_n_0\,
I3 => \cb_int[7]_i_22_n_0\,
O => \cb_int[7]_i_7_n_0\
);
\cb_int[7]_i_70\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]\(1),
I1 => \rgb888[8]\(2),
O => \cb_int[7]_i_70_n_0\
);
\cb_int[7]_i_71\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(0),
I1 => \rgb888[8]_0\(3),
O => \cb_int[7]_i_71_n_0\
);
\cb_int[7]_i_72\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_0\(2),
I1 => \rgb888[8]_0\(1),
O => \cb_int[7]_i_72_n_0\
);
\cb_int[7]_i_73\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_0\(0),
I1 => \rgb888[8]\(3),
O => \cb_int[7]_i_73_n_0\
);
\cb_int[7]_i_74\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]\(2),
I1 => \rgb888[8]\(1),
O => \cb_int[7]_i_74_n_0\
);
\cb_int[7]_i_75\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cb_int_reg[3]_0\(3),
I1 => \rgb888[8]\(0),
O => \cb_int[7]_i_75_n_0\
);
\cb_int[7]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cb_int_reg[3]_0\(1),
I1 => \^cb_int_reg[3]_0\(2),
O => \cb_int[7]_i_76_n_0\
);
\cb_int[7]_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^o\(1),
I1 => \^cb_int_reg[3]_0\(0),
O => \cb_int[7]_i_77_n_0\
);
\cb_int[7]_i_78\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb888(8),
I1 => \^o\(0),
O => \cb_int[7]_i_78_n_0\
);
\cb_int[7]_i_79\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]\(0),
I1 => \^cb_int_reg[3]_0\(3),
O => \cb_int[7]_i_79_n_0\
);
\cb_int[7]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[7]_i_10_n_0\,
I1 => \cb_int[7]_i_11_n_0\,
I2 => cb_int_reg2(5),
I3 => \cb_int[7]_i_4_n_0\,
O => \cb_int[7]_i_8_n_0\
);
\cb_int[7]_i_80\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cb_int_reg[3]_0\(2),
I1 => \^cb_int_reg[3]_0\(1),
O => \cb_int[7]_i_80_n_0\
);
\cb_int[7]_i_81\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cb_int_reg[3]_0\(0),
I1 => \^o\(1),
O => \cb_int[7]_i_81_n_0\
);
\cb_int[7]_i_82\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^o\(0),
I1 => rgb888(8),
O => \cb_int[7]_i_82_n_0\
);
\cb_int[7]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[7]_i_13_n_0\,
I1 => \cb_int[7]_i_14_n_0\,
I2 => cb_int_reg2(4),
I3 => \cb_int[7]_i_5_n_0\,
O => \cb_int[7]_i_9_n_0\
);
\cb_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[3]_i_1_n_7\,
Q => \cb_int_reg_n_0_[0]\,
R => '0'
);
\cb_int_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[11]_i_1_n_5\,
Q => \cb_int_reg__0\(10),
R => '0'
);
\cb_int_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[11]_i_1_n_4\,
Q => \cb_int_reg__0\(11),
R => '0'
);
\cb_int_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_1_n_0\,
CO(3) => \cb_int_reg[11]_i_1_n_0\,
CO(2) => \cb_int_reg[11]_i_1_n_1\,
CO(1) => \cb_int_reg[11]_i_1_n_2\,
CO(0) => \cb_int_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[11]_i_2_n_0\,
DI(2) => \cb_int[11]_i_3_n_0\,
DI(1) => \cb_int[11]_i_4_n_0\,
DI(0) => \cb_int[11]_i_5_n_0\,
O(3) => \cb_int_reg[11]_i_1_n_4\,
O(2) => \cb_int_reg[11]_i_1_n_5\,
O(1) => \cb_int_reg[11]_i_1_n_6\,
O(0) => \cb_int_reg[11]_i_1_n_7\,
S(3) => \cb_int[11]_i_6_n_0\,
S(2) => \cb_int[11]_i_7_n_0\,
S(1) => \cb_int[11]_i_8_n_0\,
S(0) => \cb_int[11]_i_9_n_0\
);
\cb_int_reg[11]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_28_n_0\,
CO(3) => \cb_int_reg[11]_i_16_n_0\,
CO(2) => \cb_int_reg[11]_i_16_n_1\,
CO(1) => \cb_int_reg[11]_i_16_n_2\,
CO(0) => \cb_int_reg[11]_i_16_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(8 downto 5),
S(3) => \cb_int[11]_i_29_n_0\,
S(2) => \cb_int[11]_i_30_n_0\,
S(1) => \cb_int[11]_i_31_n_0\,
S(0) => \cb_int[11]_i_32_n_0\
);
\cb_int_reg[11]_i_17\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_33_n_0\,
CO(3) => \cb_int_reg[11]_i_17_n_0\,
CO(2) => \cb_int_reg[11]_i_17_n_1\,
CO(1) => \cb_int_reg[11]_i_17_n_2\,
CO(0) => \cb_int_reg[11]_i_17_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(18 downto 15),
S(3) => \cb_int[11]_i_34_n_0\,
S(2) => \cb_int[11]_i_35_n_0\,
S(1) => \cb_int[11]_i_36_n_0\,
S(0) => \cb_int[11]_i_37_n_0\
);
\cb_int_reg[11]_i_18\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_38_n_0\,
CO(3) => \NLW_cb_int_reg[11]_i_18_CO_UNCONNECTED\(3),
CO(2) => cb_int_reg8,
CO(1) => \cb_int_reg[11]_i_18_n_2\,
CO(0) => \cb_int_reg[11]_i_18_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \cb_int[11]_i_39_n_0\,
DI(0) => \cb_int[11]_i_40_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_18_O_UNCONNECTED\(3 downto 0),
S(3) => '0',
S(2) => \cb_int[11]_i_41_n_0\,
S(1) => \cb_int[11]_i_42_n_0\,
S(0) => \cb_int[11]_i_43_n_0\
);
\cb_int_reg[11]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_29_n_0\,
CO(3) => \cb_int_reg[15]_0\(0),
CO(2) => \cb_int_reg[11]_i_24_n_1\,
CO(1) => \cb_int_reg[11]_i_24_n_2\,
CO(0) => \cb_int_reg[11]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[11]_i_24_n_4\,
O(2) => \cb_int_reg[11]_i_24_n_5\,
O(1) => \cb_int_reg[11]_i_24_n_6\,
O(0) => \cb_int_reg[11]_i_24_n_7\,
S(3) => \cb_int[11]_i_44_n_0\,
S(2) => \cb_int[11]_i_45_n_0\,
S(1) => \cb_int[11]_i_46_n_0\,
S(0) => \cb_int[11]_i_47_n_0\
);
\cb_int_reg[11]_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_48_n_0\,
CO(3) => \cb_int_reg[11]_i_25_n_0\,
CO(2) => \cb_int_reg[11]_i_25_n_1\,
CO(1) => \cb_int_reg[11]_i_25_n_2\,
CO(0) => \cb_int_reg[11]_i_25_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \rgb888[0]\(3),
DI(1) => \rgb888[0]\(3),
DI(0) => \rgb888[0]\(3),
O(3 downto 0) => \NLW_cb_int_reg[11]_i_25_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_49_n_0\,
S(2) => \cb_int[11]_i_50_n_0\,
S(1) => \cb_int[11]_i_51_n_0\,
S(0) => \cb_int[11]_i_52_n_0\
);
\cb_int_reg[11]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_28_n_0\,
CO(3) => \cb_int_reg[11]_i_26_n_0\,
CO(2) => \cb_int_reg[11]_i_26_n_1\,
CO(1) => \cb_int_reg[11]_i_26_n_2\,
CO(0) => \cb_int_reg[11]_i_26_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(8 downto 5),
S(3) => \cb_int[11]_i_53_n_0\,
S(2) => \cb_int[11]_i_54_n_0\,
S(1) => \cb_int[11]_i_55_n_0\,
S(0) => \cb_int[11]_i_56_n_0\
);
\cb_int_reg[11]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[11]_i_28_n_0\,
CO(2) => \cb_int_reg[11]_i_28_n_1\,
CO(1) => \cb_int_reg[11]_i_28_n_2\,
CO(0) => \cb_int_reg[11]_i_28_n_3\,
CYINIT => \cb_int[11]_i_57_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(4 downto 1),
S(3) => \cb_int[11]_i_58_n_0\,
S(2) => \cb_int[11]_i_59_n_0\,
S(1) => \cb_int[11]_i_60_n_0\,
S(0) => \cb_int[11]_i_61_n_0\
);
\cb_int_reg[11]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_15_n_0\,
CO(3) => \cb_int_reg[11]_i_33_n_0\,
CO(2) => \cb_int_reg[11]_i_33_n_1\,
CO(1) => \cb_int_reg[11]_i_33_n_2\,
CO(0) => \cb_int_reg[11]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(14 downto 11),
S(3) => \cb_int[11]_i_62_n_0\,
S(2) => \cb_int[11]_i_63_n_0\,
S(1) => \cb_int[11]_i_64_n_0\,
S(0) => \cb_int[11]_i_65_n_0\
);
\cb_int_reg[11]_i_38\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_66_n_0\,
CO(3) => \cb_int_reg[11]_i_38_n_0\,
CO(2) => \cb_int_reg[11]_i_38_n_1\,
CO(1) => \cb_int_reg[11]_i_38_n_2\,
CO(0) => \cb_int_reg[11]_i_38_n_3\,
CYINIT => '0',
DI(3) => \cb_int[11]_i_67_n_0\,
DI(2) => \cb_int[11]_i_68_n_0\,
DI(1) => \cb_int[11]_i_69_n_0\,
DI(0) => \cb_int[11]_i_70_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_38_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_71_n_0\,
S(2) => \cb_int[11]_i_72_n_0\,
S(1) => \cb_int[11]_i_73_n_0\,
S(0) => \cb_int[11]_i_74_n_0\
);
\cb_int_reg[11]_i_48\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_75_n_0\,
CO(3) => \cb_int_reg[11]_i_48_n_0\,
CO(2) => \cb_int_reg[11]_i_48_n_1\,
CO(1) => \cb_int_reg[11]_i_48_n_2\,
CO(0) => \cb_int_reg[11]_i_48_n_3\,
CYINIT => '0',
DI(3) => \rgb888[0]\(3),
DI(2) => \rgb888[0]\(3),
DI(1) => \rgb888[0]\(3),
DI(0) => \cb_int[11]_i_76_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_48_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_77_n_0\,
S(2) => \cb_int[11]_i_78_n_0\,
S(1) => \cb_int[11]_i_79_n_0\,
S(0) => \cb_int[11]_i_80_n_0\
);
\cb_int_reg[11]_i_66\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_81_n_0\,
CO(3) => \cb_int_reg[11]_i_66_n_0\,
CO(2) => \cb_int_reg[11]_i_66_n_1\,
CO(1) => \cb_int_reg[11]_i_66_n_2\,
CO(0) => \cb_int_reg[11]_i_66_n_3\,
CYINIT => '0',
DI(3) => \cb_int[11]_i_82_n_0\,
DI(2) => \cb_int[11]_i_83_n_0\,
DI(1) => \cb_int[11]_i_84_n_0\,
DI(0) => \cb_int[11]_i_85_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_66_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_86_n_0\,
S(2) => \cb_int[11]_i_87_n_0\,
S(1) => \cb_int[11]_i_88_n_0\,
S(0) => \cb_int[11]_i_89_n_0\
);
\cb_int_reg[11]_i_75\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_90_n_0\,
CO(3) => \cb_int_reg[11]_i_75_n_0\,
CO(2) => \cb_int_reg[11]_i_75_n_1\,
CO(1) => \cb_int_reg[11]_i_75_n_2\,
CO(0) => \cb_int_reg[11]_i_75_n_3\,
CYINIT => '0',
DI(3) => \cb_int[11]_i_91_n_0\,
DI(2) => \cb_int[11]_i_92_n_0\,
DI(1) => \cb_int[11]_i_93_n_0\,
DI(0) => \cb_int[11]_i_94_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_75_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_95_n_0\,
S(2) => \cb_int[11]_i_96_n_0\,
S(1) => \cb_int[11]_i_97_n_0\,
S(0) => \cb_int[11]_i_98_n_0\
);
\cb_int_reg[11]_i_81\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[11]_i_81_n_0\,
CO(2) => \cb_int_reg[11]_i_81_n_1\,
CO(1) => \cb_int_reg[11]_i_81_n_2\,
CO(0) => \cb_int_reg[11]_i_81_n_3\,
CYINIT => '1',
DI(3) => \cb_int[11]_i_99_n_0\,
DI(2) => \cb_int[11]_i_100_n_0\,
DI(1) => \cb_int[11]_i_101_n_0\,
DI(0) => \cb_int[11]_i_102_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_81_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_103_n_0\,
S(2) => \cb_int[11]_i_104_n_0\,
S(1) => \cb_int[11]_i_105_n_0\,
S(0) => \cb_int[11]_i_106_n_0\
);
\cb_int_reg[11]_i_90\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[11]_i_90_n_0\,
CO(2) => \cb_int_reg[11]_i_90_n_1\,
CO(1) => \cb_int_reg[11]_i_90_n_2\,
CO(0) => \cb_int_reg[11]_i_90_n_3\,
CYINIT => '1',
DI(3) => \cb_int[11]_i_107_n_0\,
DI(2) => \cb_int[11]_i_108_n_0\,
DI(1) => \cb_int[11]_i_109_n_0\,
DI(0) => \cb_int[11]_i_110_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_90_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_111_n_0\,
S(2) => \cb_int[11]_i_112_n_0\,
S(1) => \cb_int[11]_i_113_n_0\,
S(0) => \cb_int[11]_i_114_n_0\
);
\cb_int_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[15]_i_1_n_7\,
Q => \cb_int_reg__0\(12),
R => '0'
);
\cb_int_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[15]_i_1_n_6\,
Q => \cb_int_reg__0\(13),
R => '0'
);
\cb_int_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[15]_i_1_n_5\,
Q => \cb_int_reg__0\(14),
R => '0'
);
\cb_int_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[15]_i_1_n_4\,
Q => \cb_int_reg__0\(15),
R => '0'
);
\cb_int_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_1_n_0\,
CO(3) => \cb_int_reg[15]_i_1_n_0\,
CO(2) => \cb_int_reg[15]_i_1_n_1\,
CO(1) => \cb_int_reg[15]_i_1_n_2\,
CO(0) => \cb_int_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[15]_i_2_n_0\,
DI(2) => \cb_int[15]_i_3_n_0\,
DI(1) => \cb_int[15]_i_4_n_0\,
DI(0) => \cb_int[15]_i_5_n_0\,
O(3) => \cb_int_reg[15]_i_1_n_4\,
O(2) => \cb_int_reg[15]_i_1_n_5\,
O(1) => \cb_int_reg[15]_i_1_n_6\,
O(0) => \cb_int_reg[15]_i_1_n_7\,
S(3) => \cb_int[15]_i_6_n_0\,
S(2) => \cb_int[15]_i_7_n_0\,
S(1) => \cb_int[15]_i_8_n_0\,
S(0) => \cb_int[15]_i_9_n_0\
);
\cb_int_reg[15]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_16_n_0\,
CO(3) => \cb_int_reg[15]_i_20_n_0\,
CO(2) => \cb_int_reg[15]_i_20_n_1\,
CO(1) => \cb_int_reg[15]_i_20_n_2\,
CO(0) => \cb_int_reg[15]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(12 downto 9),
S(3) => \cb_int[15]_i_27_n_0\,
S(2) => \cb_int[15]_i_28_n_0\,
S(1) => \cb_int[15]_i_29_n_0\,
S(0) => \cb_int[15]_i_30_n_0\
);
\cb_int_reg[15]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_26_n_0\,
CO(3) => \cb_int_reg[15]_i_33_n_0\,
CO(2) => \cb_int_reg[15]_i_33_n_1\,
CO(1) => \cb_int_reg[15]_i_33_n_2\,
CO(0) => \cb_int_reg[15]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(12 downto 9),
S(3) => \cb_int[15]_i_43_n_0\,
S(2) => \cb_int[15]_i_44_n_0\,
S(1) => \cb_int[15]_i_45_n_0\,
S(0) => \cb_int[15]_i_46_n_0\
);
\cb_int_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[19]_i_1_n_7\,
Q => \cb_int_reg__0\(16),
R => '0'
);
\cb_int_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[19]_i_1_n_6\,
Q => \cb_int_reg__0\(17),
R => '0'
);
\cb_int_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[19]_i_1_n_5\,
Q => \cb_int_reg__0\(18),
R => '0'
);
\cb_int_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[19]_i_1_n_4\,
Q => \cb_int_reg__0\(19),
R => '0'
);
\cb_int_reg[19]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_1_n_0\,
CO(3) => \cb_int_reg[19]_i_1_n_0\,
CO(2) => \cb_int_reg[19]_i_1_n_1\,
CO(1) => \cb_int_reg[19]_i_1_n_2\,
CO(0) => \cb_int_reg[19]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[19]_i_2_n_0\,
DI(2) => \cb_int[19]_i_3_n_0\,
DI(1) => \cb_int[19]_i_4_n_0\,
DI(0) => \cb_int[19]_i_5_n_0\,
O(3) => \cb_int_reg[19]_i_1_n_4\,
O(2) => \cb_int_reg[19]_i_1_n_5\,
O(1) => \cb_int_reg[19]_i_1_n_6\,
O(0) => \cb_int_reg[19]_i_1_n_7\,
S(3) => \cb_int[19]_i_6_n_0\,
S(2) => \cb_int[19]_i_7_n_0\,
S(1) => \cb_int[19]_i_8_n_0\,
S(0) => \cb_int[19]_i_9_n_0\
);
\cb_int_reg[19]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_20_n_0\,
CO(3) => \cb_int_reg[19]_i_20_n_0\,
CO(2) => \cb_int_reg[19]_i_20_n_1\,
CO(1) => \cb_int_reg[19]_i_20_n_2\,
CO(0) => \cb_int_reg[19]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(16 downto 13),
S(3) => \cb_int[19]_i_28_n_0\,
S(2) => \cb_int[19]_i_29_n_0\,
S(1) => \cb_int[19]_i_30_n_0\,
S(0) => \cb_int[19]_i_31_n_0\
);
\cb_int_reg[19]_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_17_n_0\,
CO(3) => \cb_int_reg[19]_i_25_n_0\,
CO(2) => \cb_int_reg[19]_i_25_n_1\,
CO(1) => \cb_int_reg[19]_i_25_n_2\,
CO(0) => \cb_int_reg[19]_i_25_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(22 downto 19),
S(3) => \cb_int[19]_i_34_n_0\,
S(2) => \cb_int[19]_i_35_n_0\,
S(1) => \cb_int[19]_i_36_n_0\,
S(0) => \cb_int[19]_i_37_n_0\
);
\cb_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[3]_i_1_n_6\,
Q => \cb_int_reg_n_0_[1]\,
R => '0'
);
\cb_int_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[23]_i_1_n_7\,
Q => \cb_int_reg__0\(20),
R => '0'
);
\cb_int_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[23]_i_1_n_6\,
Q => \cb_int_reg__0\(21),
R => '0'
);
\cb_int_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[23]_i_1_n_5\,
Q => \cb_int_reg__0\(22),
R => '0'
);
\cb_int_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[23]_i_1_n_4\,
Q => \cb_int_reg__0\(23),
R => '0'
);
\cb_int_reg[23]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_1_n_0\,
CO(3) => \cb_int_reg[23]_i_1_n_0\,
CO(2) => \cb_int_reg[23]_i_1_n_1\,
CO(1) => \cb_int_reg[23]_i_1_n_2\,
CO(0) => \cb_int_reg[23]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[23]_i_2_n_0\,
DI(2) => \cb_int[23]_i_3_n_0\,
DI(1) => \cb_int[23]_i_4_n_0\,
DI(0) => \cb_int[23]_i_5_n_0\,
O(3) => \cb_int_reg[23]_i_1_n_4\,
O(2) => \cb_int_reg[23]_i_1_n_5\,
O(1) => \cb_int_reg[23]_i_1_n_6\,
O(0) => \cb_int_reg[23]_i_1_n_7\,
S(3) => \cb_int[23]_i_6_n_0\,
S(2) => \cb_int[23]_i_7_n_0\,
S(1) => \cb_int[23]_i_8_n_0\,
S(0) => \cb_int[23]_i_9_n_0\
);
\cb_int_reg[23]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_25_n_0\,
CO(3) => \cb_int_reg[23]_i_24_n_0\,
CO(2) => \cb_int_reg[23]_i_24_n_1\,
CO(1) => \cb_int_reg[23]_i_24_n_2\,
CO(0) => \cb_int_reg[23]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(26 downto 23),
S(3) => \cb_int[23]_i_29_n_0\,
S(2) => \cb_int[23]_i_30_n_0\,
S(1) => \cb_int[23]_i_31_n_0\,
S(0) => \cb_int[23]_i_32_n_0\
);
\cb_int_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[27]_i_1_n_7\,
Q => \cb_int_reg__0\(24),
R => '0'
);
\cb_int_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[27]_i_1_n_6\,
Q => \cb_int_reg__0\(25),
R => '0'
);
\cb_int_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[27]_i_1_n_5\,
Q => \cb_int_reg__0\(26),
R => '0'
);
\cb_int_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[27]_i_1_n_4\,
Q => \cb_int_reg__0\(27),
R => '0'
);
\cb_int_reg[27]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[23]_i_1_n_0\,
CO(3) => \cb_int_reg[27]_i_1_n_0\,
CO(2) => \cb_int_reg[27]_i_1_n_1\,
CO(1) => \cb_int_reg[27]_i_1_n_2\,
CO(0) => \cb_int_reg[27]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[31]_i_2_n_0\,
DI(2) => \cb_int[31]_i_2_n_0\,
DI(1) => \cb_int[31]_i_2_n_0\,
DI(0) => \cb_int[27]_i_2_n_0\,
O(3) => \cb_int_reg[27]_i_1_n_4\,
O(2) => \cb_int_reg[27]_i_1_n_5\,
O(1) => \cb_int_reg[27]_i_1_n_6\,
O(0) => \cb_int_reg[27]_i_1_n_7\,
S(3) => \cb_int[27]_i_3_n_0\,
S(2) => \cb_int[27]_i_4_n_0\,
S(1) => \cb_int[27]_i_5_n_0\,
S(0) => \cb_int[27]_i_6_n_0\
);
\cb_int_reg[27]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[23]_i_24_n_0\,
CO(3) => \NLW_cb_int_reg[27]_i_9_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[27]_i_9_n_1\,
CO(1) => \cb_int_reg[27]_i_9_n_2\,
CO(0) => \cb_int_reg[27]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(30 downto 27),
S(3) => \cb_int[27]_i_12_n_0\,
S(2) => \cb_int[27]_i_13_n_0\,
S(1) => \cb_int[27]_i_14_n_0\,
S(0) => \cb_int[27]_i_15_n_0\
);
\cb_int_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[31]_i_1_n_7\,
Q => \cb_int_reg__0\(28),
R => '0'
);
\cb_int_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[31]_i_1_n_6\,
Q => \cb_int_reg__0\(29),
R => '0'
);
\cb_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[3]_i_1_n_5\,
Q => \cb_int_reg_n_0_[2]\,
R => '0'
);
\cb_int_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[31]_i_1_n_5\,
Q => \cb_int_reg__0\(30),
R => '0'
);
\cb_int_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[31]_i_1_n_4\,
Q => \cb_int_reg__0\(31),
R => '0'
);
\cb_int_reg[31]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[27]_i_1_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_1_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_1_n_1\,
CO(1) => \cb_int_reg[31]_i_1_n_2\,
CO(0) => \cb_int_reg[31]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \cb_int[31]_i_2_n_0\,
DI(1) => \cb_int[31]_i_2_n_0\,
DI(0) => \cb_int[31]_i_2_n_0\,
O(3) => \cb_int_reg[31]_i_1_n_4\,
O(2) => \cb_int_reg[31]_i_1_n_5\,
O(1) => \cb_int_reg[31]_i_1_n_6\,
O(0) => \cb_int_reg[31]_i_1_n_7\,
S(3) => \cb_int[31]_i_3_n_0\,
S(2) => \cb_int[31]_i_4_n_0\,
S(1) => \cb_int[31]_i_5_n_0\,
S(0) => \cb_int[31]_i_6_n_0\
);
\cb_int_reg[31]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_30_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_11_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_11_n_1\,
CO(1) => \NLW_cb_int_reg[31]_i_11_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[31]_i_11_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_11_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => cb_int_reg5(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \cb_int[31]_i_31_n_0\,
S(0) => \cb_int[31]_i_32_n_0\
);
\cb_int_reg[31]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_33_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_12_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_12_n_1\,
CO(1) => \NLW_cb_int_reg[31]_i_12_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[31]_i_12_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \cb_int_reg[31]_i_34_n_2\,
DI(0) => '0',
O(3 downto 2) => \NLW_cb_int_reg[31]_i_12_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_12_n_6\,
O(0) => \cb_int_reg[31]_i_12_n_7\,
S(3 downto 2) => B"01",
S(1) => \cb_int[31]_i_35_n_0\,
S(0) => \cb_int[31]_i_36_n_0\
);
\cb_int_reg[31]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_37_n_0\,
CO(3) => \cb_int_reg[31]_i_14_n_0\,
CO(2) => \cb_int_reg[31]_i_14_n_1\,
CO(1) => \cb_int_reg[31]_i_14_n_2\,
CO(0) => \cb_int_reg[31]_i_14_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(20 downto 17),
S(3) => \cb_int[31]_i_38_n_0\,
S(2) => \cb_int[31]_i_39_n_0\,
S(1) => \cb_int[31]_i_40_n_0\,
S(0) => \cb_int[31]_i_41_n_0\
);
\cb_int_reg[31]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_20_n_0\,
CO(3) => \cb_int_reg[31]_i_30_n_0\,
CO(2) => \cb_int_reg[31]_i_30_n_1\,
CO(1) => \cb_int_reg[31]_i_30_n_2\,
CO(0) => \cb_int_reg[31]_i_30_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(20 downto 17),
S(3) => \cb_int[31]_i_67_n_0\,
S(2) => \cb_int[31]_i_68_n_0\,
S(1) => \cb_int[31]_i_69_n_0\,
S(0) => \cb_int[31]_i_70_n_0\
);
\cb_int_reg[31]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_16_n_0\,
CO(3) => \cb_int_reg[31]_i_33_n_0\,
CO(2) => \cb_int_reg[31]_i_33_n_1\,
CO(1) => \cb_int_reg[31]_i_33_n_2\,
CO(0) => \cb_int_reg[31]_i_33_n_3\,
CYINIT => '0',
DI(3) => \cb_int_reg[31]_i_34_n_7\,
DI(2) => \cb_int[31]_i_71_n_0\,
DI(1) => \cb_int[31]_i_72_n_0\,
DI(0) => \cb_int_reg[31]_i_73_n_7\,
O(3) => \cb_int_reg[31]_i_33_n_4\,
O(2) => \cb_int_reg[31]_i_33_n_5\,
O(1) => \cb_int_reg[31]_i_33_n_6\,
O(0) => \cb_int_reg[31]_i_33_n_7\,
S(3) => \cb_int[31]_i_74_n_0\,
S(2) => \cb_int[31]_i_75_n_0\,
S(1) => \cb_int[31]_i_76_n_0\,
S(0) => \cb_int[31]_i_77_n_0\
);
\cb_int_reg[31]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_73_n_0\,
CO(3 downto 2) => \NLW_cb_int_reg[31]_i_34_CO_UNCONNECTED\(3 downto 2),
CO(1) => \cb_int_reg[31]_i_34_n_2\,
CO(0) => \NLW_cb_int_reg[31]_i_34_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(23),
O(3 downto 1) => \NLW_cb_int_reg[31]_i_34_O_UNCONNECTED\(3 downto 1),
O(0) => \cb_int_reg[31]_i_34_n_7\,
S(3 downto 1) => B"001",
S(0) => \cb_int[31]_i_78_n_0\
);
\cb_int_reg[31]_i_37\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_33_n_0\,
CO(3) => \cb_int_reg[31]_i_37_n_0\,
CO(2) => \cb_int_reg[31]_i_37_n_1\,
CO(1) => \cb_int_reg[31]_i_37_n_2\,
CO(0) => \cb_int_reg[31]_i_37_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(16 downto 13),
S(3) => \cb_int[31]_i_79_n_0\,
S(2) => \cb_int[31]_i_80_n_0\,
S(1) => \cb_int[31]_i_81_n_0\,
S(0) => \cb_int[31]_i_82_n_0\
);
\cb_int_reg[31]_i_7\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_14_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_7_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_7_n_1\,
CO(1) => \NLW_cb_int_reg[31]_i_7_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[31]_i_7_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_7_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => cb_int_reg3(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \cb_int[31]_i_15_n_0\,
S(0) => \cb_int[31]_i_16_n_0\
);
\cb_int_reg[31]_i_73\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_57_n_0\,
CO(3) => \cb_int_reg[31]_i_73_n_0\,
CO(2) => \cb_int_reg[31]_i_73_n_1\,
CO(1) => \cb_int_reg[31]_i_73_n_2\,
CO(0) => \cb_int_reg[31]_i_73_n_3\,
CYINIT => '0',
DI(3) => rgb888(22),
DI(2 downto 0) => rgb888(23 downto 21),
O(3) => \cb_int_reg[31]_i_73_n_4\,
O(2) => \cb_int_reg[31]_i_73_n_5\,
O(1) => \cb_int_reg[31]_i_73_n_6\,
O(0) => \cb_int_reg[31]_i_73_n_7\,
S(3) => \cb_int[31]_i_95_n_0\,
S(2) => \cb_int[31]_i_96_n_0\,
S(1) => \cb_int[31]_i_97_n_0\,
S(0) => \cb_int[31]_i_98_n_0\
);
\cb_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[3]_i_1_n_4\,
Q => \cb_int_reg_n_0_[3]\,
R => '0'
);
\cb_int_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_1_n_0\,
CO(2) => \cb_int_reg[3]_i_1_n_1\,
CO(1) => \cb_int_reg[3]_i_1_n_2\,
CO(0) => \cb_int_reg[3]_i_1_n_3\,
CYINIT => '1',
DI(3) => \cb_int[3]_i_2_n_0\,
DI(2) => \cb_int[3]_i_3_n_0\,
DI(1) => \cb_int[3]_i_4_n_0\,
DI(0) => '1',
O(3) => \cb_int_reg[3]_i_1_n_4\,
O(2) => \cb_int_reg[3]_i_1_n_5\,
O(1) => \cb_int_reg[3]_i_1_n_6\,
O(0) => \cb_int_reg[3]_i_1_n_7\,
S(3) => \cb_int[3]_i_5_n_0\,
S(2) => \cb_int[3]_i_6_n_0\,
S(1) => \cb_int[3]_i_7_n_0\,
S(0) => \cb_int[3]_i_8_n_0\
);
\cb_int_reg[3]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_21_n_0\,
CO(3) => \cb_int_reg[3]_i_15_n_0\,
CO(2) => \cb_int_reg[3]_i_15_n_1\,
CO(1) => \cb_int_reg[3]_i_15_n_2\,
CO(0) => \cb_int_reg[3]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => cb_int_reg7(10 downto 8),
O(0) => \NLW_cb_int_reg[3]_i_15_O_UNCONNECTED\(0),
S(3) => \cb_int[3]_i_22_n_0\,
S(2) => \cb_int[3]_i_23_n_0\,
S(1) => \cb_int[3]_i_24_n_0\,
S(0) => \cb_int[3]_i_25_n_0\
);
\cb_int_reg[3]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_26_n_0\,
CO(3) => \cb_int_reg[3]_i_16_n_0\,
CO(2) => \cb_int_reg[3]_i_16_n_1\,
CO(1) => \cb_int_reg[3]_i_16_n_2\,
CO(0) => \cb_int_reg[3]_i_16_n_3\,
CYINIT => '0',
DI(3) => \cb_int[3]_i_27_n_0\,
DI(2 downto 0) => rgb888(21 downto 19),
O(3) => \cb_int_reg[3]_i_16_n_4\,
O(2) => \cb_int_reg[3]_i_16_n_5\,
O(1) => \cb_int_reg[3]_i_16_n_6\,
O(0) => \cb_int_reg[3]_i_16_n_7\,
S(3) => \cb_int[3]_i_28_n_0\,
S(2) => \cb_int[3]_i_29_n_0\,
S(1) => \cb_int[3]_i_30_n_0\,
S(0) => \cb_int[3]_i_31_n_0\
);
\cb_int_reg[3]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[27]_0\(0),
CO(2) => \cb_int_reg[3]_i_20_n_1\,
CO(1) => \cb_int_reg[3]_i_20_n_2\,
CO(0) => \cb_int_reg[3]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 2) => \rgb888[0]_8\(1 downto 0),
DI(1) => \cb_int_reg[3]_i_44_n_4\,
DI(0) => '0',
O(3) => \cb_int_reg[3]_i_20_n_4\,
O(2) => \cb_int_reg[3]_i_20_n_5\,
O(1) => \cb_int_reg[3]_i_20_n_6\,
O(0) => \cb_int_reg[3]_i_20_n_7\,
S(3) => \cb_int[3]_i_45_n_0\,
S(2) => \cb_int[3]_i_46_n_0\,
S(1) => \cb_int[3]_i_47_n_0\,
S(0) => \cb_int[3]_i_48_n_0\
);
\cb_int_reg[3]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_21_n_0\,
CO(2) => \cb_int_reg[3]_i_21_n_1\,
CO(1) => \cb_int_reg[3]_i_21_n_2\,
CO(0) => \cb_int_reg[3]_i_21_n_3\,
CYINIT => \cb_int[3]_i_49_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cb_int_reg[3]_i_21_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[3]_i_50_n_0\,
S(2) => \cb_int[3]_i_51_n_0\,
S(1) => \cb_int[3]_i_52_n_0\,
S(0) => \cb_int[3]_i_53_n_0\
);
\cb_int_reg[3]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_26_n_0\,
CO(2) => \cb_int_reg[3]_i_26_n_1\,
CO(1) => \cb_int_reg[3]_i_26_n_2\,
CO(0) => \cb_int_reg[3]_i_26_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(18 downto 16),
DI(0) => '0',
O(3) => \cb_int_reg[3]_i_26_n_4\,
O(2) => \cb_int_reg[3]_i_26_n_5\,
O(1) => \cb_int_reg[3]_i_26_n_6\,
O(0) => \NLW_cb_int_reg[3]_i_26_O_UNCONNECTED\(0),
S(3) => \cb_int[3]_i_54_n_0\,
S(2) => \cb_int[3]_i_55_n_0\,
S(1) => \cb_int[3]_i_56_n_0\,
S(0) => '0'
);
\cb_int_reg[3]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_63_n_0\,
CO(3) => \cb_int_reg[3]_i_33_n_0\,
CO(2) => \cb_int_reg[3]_i_33_n_1\,
CO(1) => \cb_int_reg[3]_i_33_n_2\,
CO(0) => \cb_int_reg[3]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[3]_i_33_n_4\,
O(2 downto 0) => \NLW_cb_int_reg[3]_i_33_O_UNCONNECTED\(2 downto 0),
S(3) => \cb_int[3]_i_64_n_0\,
S(2) => \cb_int[3]_i_65_n_0\,
S(1) => \cb_int[3]_i_66_n_0\,
S(0) => \cb_int[3]_i_67_n_0\
);
\cb_int_reg[3]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_2\(0),
CO(2) => \cb_int_reg[3]_i_34_n_1\,
CO(1) => \cb_int_reg[3]_i_34_n_2\,
CO(0) => \cb_int_reg[3]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 1) => \rgb888[8]_31\(2 downto 0),
DI(0) => '0',
O(3 downto 0) => \^cb_int_reg[3]_0\(3 downto 0),
S(3) => \cb_int[3]_i_69_n_0\,
S(2) => \cb_int[3]_i_70_n_0\,
S(1) => \cb_int[3]_i_71_n_0\,
S(0) => \cb_int[3]_i_72_n_0\
);
\cb_int_reg[3]_i_44\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_75_n_0\,
CO(3) => \cb_int_reg[3]_3\(0),
CO(2) => \cb_int_reg[3]_i_44_n_1\,
CO(1) => \cb_int_reg[3]_i_44_n_2\,
CO(0) => \cb_int_reg[3]_i_44_n_3\,
CYINIT => '0',
DI(3 downto 0) => rgb888(5 downto 2),
O(3) => \cb_int_reg[3]_i_44_n_4\,
O(2) => \cb_int_reg[3]_i_44_n_5\,
O(1) => \cb_int_reg[3]_i_44_n_6\,
O(0) => \cb_int_reg[3]_i_44_n_7\,
S(3) => \cb_int[3]_i_76_n_0\,
S(2) => \cb_int[3]_i_77_n_0\,
S(1) => \cb_int[3]_i_78_n_0\,
S(0) => \cb_int[3]_i_79_n_0\
);
\cb_int_reg[3]_i_57\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_57_n_0\,
CO(2) => \cb_int_reg[3]_i_57_n_1\,
CO(1) => \cb_int_reg[3]_i_57_n_2\,
CO(0) => \cb_int_reg[3]_i_57_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(20 downto 18),
DI(0) => '0',
O(3) => \cb_int_reg[3]_i_57_n_4\,
O(2) => \cb_int_reg[3]_i_57_n_5\,
O(1) => \cb_int_reg[3]_i_57_n_6\,
O(0) => \cb_int_reg[3]_i_57_n_7\,
S(3) => \cb_int[3]_i_80_n_0\,
S(2) => \cb_int[3]_i_81_n_0\,
S(1) => \cb_int[3]_i_82_n_0\,
S(0) => \cb_int[3]_i_83_n_0\
);
\cb_int_reg[3]_i_63\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_63_n_0\,
CO(2) => \cb_int_reg[3]_i_63_n_1\,
CO(1) => \cb_int_reg[3]_i_63_n_2\,
CO(0) => \cb_int_reg[3]_i_63_n_3\,
CYINIT => \cb_int[3]_i_89_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cb_int_reg[3]_i_63_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[3]_i_90_n_0\,
S(2) => \cb_int[3]_i_91_n_0\,
S(1) => \cb_int[3]_i_92_n_0\,
S(0) => \cb_int[3]_i_93_n_0\
);
\cb_int_reg[3]_i_75\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_75_n_0\,
CO(2) => \cb_int_reg[3]_i_75_n_1\,
CO(1) => \cb_int_reg[3]_i_75_n_2\,
CO(0) => \cb_int_reg[3]_i_75_n_3\,
CYINIT => '0',
DI(3 downto 2) => rgb888(1 downto 0),
DI(1 downto 0) => B"01",
O(3) => \cb_int_reg[3]_i_75_n_4\,
O(2) => \cb_int_reg[3]_i_75_n_5\,
O(1) => \cb_int_reg[3]_i_75_n_6\,
O(0) => \cb_int_reg[3]_i_75_n_7\,
S(3) => \cb_int[3]_i_99_n_0\,
S(2) => \cb_int[3]_i_100_n_0\,
S(1) => \cb_int[3]_i_101_n_0\,
S(0) => \cb_int[3]_i_102_n_0\
);
\cb_int_reg[3]_i_94\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_1\(0),
CO(2) => \cb_int_reg[3]_i_94_n_1\,
CO(1) => \cb_int_reg[3]_i_94_n_2\,
CO(0) => \cb_int_reg[3]_i_94_n_3\,
CYINIT => '0',
DI(3) => rgb888(8),
DI(2 downto 0) => B"001",
O(3) => \cb_int_reg[3]_i_94_n_4\,
O(2 downto 1) => \^o\(1 downto 0),
O(0) => \cb_int_reg[3]_i_94_n_7\,
S(3) => \cb_int[3]_i_103_n_0\,
S(2) => \cb_int[3]_i_104_n_0\,
S(1) => \cb_int[3]_i_105_n_0\,
S(0) => \cb_int[3]_i_106_n_0\
);
\cb_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[7]_i_1_n_7\,
Q => \cb_int_reg_n_0_[4]\,
R => '0'
);
\cb_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[7]_i_1_n_6\,
Q => \cb_int_reg_n_0_[5]\,
R => '0'
);
\cb_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[7]_i_1_n_5\,
Q => \cb_int_reg_n_0_[6]\,
R => '0'
);
\cb_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[7]_i_1_n_4\,
Q => \cb_int_reg_n_0_[7]\,
R => '0'
);
\cb_int_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_1_n_0\,
CO(3) => \cb_int_reg[7]_i_1_n_0\,
CO(2) => \cb_int_reg[7]_i_1_n_1\,
CO(1) => \cb_int_reg[7]_i_1_n_2\,
CO(0) => \cb_int_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[7]_i_2_n_0\,
DI(2) => \cb_int[7]_i_3_n_0\,
DI(1) => \cb_int[7]_i_4_n_0\,
DI(0) => \cb_int[7]_i_5_n_0\,
O(3) => \cb_int_reg[7]_i_1_n_4\,
O(2) => \cb_int_reg[7]_i_1_n_5\,
O(1) => \cb_int_reg[7]_i_1_n_6\,
O(0) => \cb_int_reg[7]_i_1_n_7\,
S(3) => \cb_int[7]_i_6_n_0\,
S(2) => \cb_int[7]_i_7_n_0\,
S(1) => \cb_int[7]_i_8_n_0\,
S(0) => \cb_int[7]_i_9_n_0\
);
\cb_int_reg[7]_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_38_n_0\,
CO(3) => \^co\(0),
CO(2) => \cb_int_reg[7]_i_25_n_1\,
CO(1) => \cb_int_reg[7]_i_25_n_2\,
CO(0) => \cb_int_reg[7]_i_25_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \rgb888[8]_1\(1),
DI(1) => \rgb888[8]_1\(1),
DI(0) => \rgb888[8]_1\(1),
O(3 downto 0) => \NLW_cb_int_reg[7]_i_25_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[7]_i_39_n_0\,
S(2) => \cb_int[7]_i_40_n_0\,
S(1) => \cb_int[7]_i_41_n_0\,
S(0) => \cb_int[7]_i_42_n_0\
);
\cb_int_reg[7]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[7]_i_28_n_0\,
CO(2) => \cb_int_reg[7]_i_28_n_1\,
CO(1) => \cb_int_reg[7]_i_28_n_2\,
CO(0) => \cb_int_reg[7]_i_28_n_3\,
CYINIT => \cb_int[7]_i_52_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(4 downto 1),
S(3) => \cb_int[7]_i_53_n_0\,
S(2) => \cb_int[7]_i_54_n_0\,
S(1) => \cb_int[7]_i_55_n_0\,
S(0) => \cb_int[7]_i_56_n_0\
);
\cb_int_reg[7]_i_29\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_33_n_0\,
CO(3) => \cb_int_reg[7]_i_29_n_0\,
CO(2) => \cb_int_reg[7]_i_29_n_1\,
CO(1) => \cb_int_reg[7]_i_29_n_2\,
CO(0) => \cb_int_reg[7]_i_29_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_29_n_4\,
O(2) => \cb_int_reg[7]_i_29_n_5\,
O(1) => \cb_int_reg[7]_i_29_n_6\,
O(0) => \cb_int_reg[7]_i_29_n_7\,
S(3) => \cb_int[7]_i_57_n_0\,
S(2) => \cb_int[7]_i_58_n_0\,
S(1) => \cb_int[7]_i_59_n_0\,
S(0) => \cb_int[7]_i_60_n_0\
);
\cb_int_reg[7]_i_38\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_61_n_0\,
CO(3) => \cb_int_reg[7]_i_38_n_0\,
CO(2) => \cb_int_reg[7]_i_38_n_1\,
CO(1) => \cb_int_reg[7]_i_38_n_2\,
CO(0) => \cb_int_reg[7]_i_38_n_3\,
CYINIT => '0',
DI(3) => \rgb888[8]_1\(1),
DI(2) => \rgb888[8]_1\(1),
DI(1) => \rgb888[8]_1\(1),
DI(0) => \rgb888[8]_1\(1),
O(3 downto 0) => \NLW_cb_int_reg[7]_i_38_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[7]_i_62_n_0\,
S(2) => \cb_int[7]_i_63_n_0\,
S(1) => \cb_int[7]_i_64_n_0\,
S(0) => \cb_int[7]_i_65_n_0\
);
\cb_int_reg[7]_i_61\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_66_n_0\,
CO(3) => \cb_int_reg[7]_i_61_n_0\,
CO(2) => \cb_int_reg[7]_i_61_n_1\,
CO(1) => \cb_int_reg[7]_i_61_n_2\,
CO(0) => \cb_int_reg[7]_i_61_n_3\,
CYINIT => '0',
DI(3) => \cb_int[7]_i_67_n_0\,
DI(2) => \cb_int[7]_i_68_n_0\,
DI(1) => \cb_int[7]_i_69_n_0\,
DI(0) => \cb_int[7]_i_70_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[7]_i_61_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[7]_i_71_n_0\,
S(2) => \cb_int[7]_i_72_n_0\,
S(1) => \cb_int[7]_i_73_n_0\,
S(0) => \cb_int[7]_i_74_n_0\
);
\cb_int_reg[7]_i_66\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[7]_i_66_n_0\,
CO(2) => \cb_int_reg[7]_i_66_n_1\,
CO(1) => \cb_int_reg[7]_i_66_n_2\,
CO(0) => \cb_int_reg[7]_i_66_n_3\,
CYINIT => '1',
DI(3) => \cb_int[7]_i_75_n_0\,
DI(2) => \cb_int[7]_i_76_n_0\,
DI(1) => \cb_int[7]_i_77_n_0\,
DI(0) => \cb_int[7]_i_78_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[7]_i_66_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[7]_i_79_n_0\,
S(2) => \cb_int[7]_i_80_n_0\,
S(1) => \cb_int[7]_i_81_n_0\,
S(0) => \cb_int[7]_i_82_n_0\
);
\cb_int_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[11]_i_1_n_7\,
Q => \cb_int_reg__0\(8),
R => '0'
);
\cb_int_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[11]_i_1_n_6\,
Q => \cb_int_reg__0\(9),
R => '0'
);
\cb_reg[0]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[0]_i_1_n_0\,
Q => cb(0),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[1]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[1]_i_1_n_0\,
Q => cb(1),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[2]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[2]_i_1_n_0\,
Q => cb(2),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[3]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[3]_i_1_n_0\,
Q => cb(3),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[4]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[4]_i_1_n_0\,
Q => cb(4),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[5]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[5]_i_1_n_0\,
Q => cb(5),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[6]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[6]_i_1_n_0\,
Q => cb(6),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[7]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[7]_i_2_n_0\,
Q => cb(7),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_reg[7]_i_3_n_0\,
CO(3) => \cb_reg[7]_i_1_n_0\,
CO(2) => \cb_reg[7]_i_1_n_1\,
CO(1) => \cb_reg[7]_i_1_n_2\,
CO(0) => \cb_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb[7]_i_4_n_0\,
DI(2) => \cb[7]_i_5_n_0\,
DI(1) => \cb[7]_i_6_n_0\,
DI(0) => \cb[7]_i_7_n_0\,
O(3 downto 0) => \NLW_cb_reg[7]_i_1_O_UNCONNECTED\(3 downto 0),
S(3) => \cb[7]_i_8_n_0\,
S(2) => \cb[7]_i_9_n_0\,
S(1) => \cb[7]_i_10_n_0\,
S(0) => \cb[7]_i_11_n_0\
);
\cb_reg[7]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_reg[7]_i_12_n_0\,
CO(2) => \cb_reg[7]_i_12_n_1\,
CO(1) => \cb_reg[7]_i_12_n_2\,
CO(0) => \cb_reg[7]_i_12_n_3\,
CYINIT => '0',
DI(3) => \cb[7]_i_21_n_0\,
DI(2) => \cb[7]_i_22_n_0\,
DI(1) => \cb[7]_i_23_n_0\,
DI(0) => \cb[7]_i_24_n_0\,
O(3 downto 0) => \NLW_cb_reg[7]_i_12_O_UNCONNECTED\(3 downto 0),
S(3) => \cb[7]_i_25_n_0\,
S(2) => \cb[7]_i_26_n_0\,
S(1) => \cb[7]_i_27_n_0\,
S(0) => \cb[7]_i_28_n_0\
);
\cb_reg[7]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \cb_reg[7]_i_12_n_0\,
CO(3) => \cb_reg[7]_i_3_n_0\,
CO(2) => \cb_reg[7]_i_3_n_1\,
CO(1) => \cb_reg[7]_i_3_n_2\,
CO(0) => \cb_reg[7]_i_3_n_3\,
CYINIT => '0',
DI(3) => \cb[7]_i_13_n_0\,
DI(2) => \cb[7]_i_14_n_0\,
DI(1) => \cb[7]_i_15_n_0\,
DI(0) => \cb[7]_i_16_n_0\,
O(3 downto 0) => \NLW_cb_reg[7]_i_3_O_UNCONNECTED\(3 downto 0),
S(3) => \cb[7]_i_17_n_0\,
S(2) => \cb[7]_i_18_n_0\,
S(1) => \cb[7]_i_19_n_0\,
S(0) => \cb[7]_i_20_n_0\
);
cb_regi_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => clk,
O => cb_regn_0_0
);
\cr[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[0]\,
I1 => \cr_int_reg__0\(31),
O => \cr[0]_i_1_n_0\
);
\cr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[1]\,
I1 => \cr_int_reg__0\(31),
O => \cr[1]_i_1_n_0\
);
\cr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[2]\,
I1 => \cr_int_reg__0\(31),
O => \cr[2]_i_1_n_0\
);
\cr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[3]\,
I1 => \cr_int_reg__0\(31),
O => \cr[3]_i_1_n_0\
);
\cr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[4]\,
I1 => \cr_int_reg__0\(31),
O => \cr[4]_i_1_n_0\
);
\cr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[5]\,
I1 => \cr_int_reg__0\(31),
O => \cr[5]_i_1_n_0\
);
\cr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[6]\,
I1 => \cr_int_reg__0\(31),
O => \cr[6]_i_1_n_0\
);
\cr[7]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(26),
I1 => \cr_int_reg__0\(27),
O => \cr[7]_i_10_n_0\
);
\cr[7]_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(24),
I1 => \cr_int_reg__0\(25),
O => \cr[7]_i_11_n_0\
);
\cr[7]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(22),
I1 => \cr_int_reg__0\(23),
O => \cr[7]_i_13_n_0\
);
\cr[7]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(20),
I1 => \cr_int_reg__0\(21),
O => \cr[7]_i_14_n_0\
);
\cr[7]_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(18),
I1 => \cr_int_reg__0\(19),
O => \cr[7]_i_15_n_0\
);
\cr[7]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(16),
I1 => \cr_int_reg__0\(17),
O => \cr[7]_i_16_n_0\
);
\cr[7]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(22),
I1 => \cr_int_reg__0\(23),
O => \cr[7]_i_17_n_0\
);
\cr[7]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(20),
I1 => \cr_int_reg__0\(21),
O => \cr[7]_i_18_n_0\
);
\cr[7]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(18),
I1 => \cr_int_reg__0\(19),
O => \cr[7]_i_19_n_0\
);
\cr[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[7]\,
I1 => \cr_int_reg__0\(31),
O => \cr[7]_i_2_n_0\
);
\cr[7]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(16),
I1 => \cr_int_reg__0\(17),
O => \cr[7]_i_20_n_0\
);
\cr[7]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(14),
I1 => \cr_int_reg__0\(15),
O => \cr[7]_i_21_n_0\
);
\cr[7]_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(12),
I1 => \cr_int_reg__0\(13),
O => \cr[7]_i_22_n_0\
);
\cr[7]_i_23\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(10),
I1 => \cr_int_reg__0\(11),
O => \cr[7]_i_23_n_0\
);
\cr[7]_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(8),
I1 => \cr_int_reg__0\(9),
O => \cr[7]_i_24_n_0\
);
\cr[7]_i_25\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(14),
I1 => \cr_int_reg__0\(15),
O => \cr[7]_i_25_n_0\
);
\cr[7]_i_26\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(12),
I1 => \cr_int_reg__0\(13),
O => \cr[7]_i_26_n_0\
);
\cr[7]_i_27\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(10),
I1 => \cr_int_reg__0\(11),
O => \cr[7]_i_27_n_0\
);
\cr[7]_i_28\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(8),
I1 => \cr_int_reg__0\(9),
O => \cr[7]_i_28_n_0\
);
\cr[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg__0\(30),
I1 => \cr_int_reg__0\(31),
O => \cr[7]_i_4_n_0\
);
\cr[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(28),
I1 => \cr_int_reg__0\(29),
O => \cr[7]_i_5_n_0\
);
\cr[7]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(26),
I1 => \cr_int_reg__0\(27),
O => \cr[7]_i_6_n_0\
);
\cr[7]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(24),
I1 => \cr_int_reg__0\(25),
O => \cr[7]_i_7_n_0\
);
\cr[7]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(30),
I1 => \cr_int_reg__0\(31),
O => \cr[7]_i_8_n_0\
);
\cr[7]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(28),
I1 => \cr_int_reg__0\(29),
O => \cr[7]_i_9_n_0\
);
\cr_hold_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(0),
Q => \cr_hold_reg_n_0_[0]\,
R => '0'
);
\cr_hold_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(1),
Q => \cr_hold_reg_n_0_[1]\,
R => '0'
);
\cr_hold_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(2),
Q => \cr_hold_reg_n_0_[2]\,
R => '0'
);
\cr_hold_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(3),
Q => \cr_hold_reg_n_0_[3]\,
R => '0'
);
\cr_hold_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(4),
Q => \cr_hold_reg_n_0_[4]\,
R => '0'
);
\cr_hold_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(5),
Q => \cr_hold_reg_n_0_[5]\,
R => '0'
);
\cr_hold_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(6),
Q => \cr_hold_reg_n_0_[6]\,
R => '0'
);
\cr_hold_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(7),
Q => \cr_hold_reg_n_0_[7]\,
R => '0'
);
\cr_int[11]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(18),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(10),
I4 => \cr_int[15]_i_26_n_0\,
I5 => \cr_int[15]_i_27_n_0\,
O => \cr_int[11]_i_10_n_0\
);
\cr_int[11]_i_100\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(11),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_30_n_6\,
O => \cr_int[11]_i_100_n_0\
);
\cr_int[11]_i_101\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(10),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_30_n_7\,
O => \cr_int[11]_i_101_n_0\
);
\cr_int[11]_i_102\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(9),
I1 => cr_int_reg7,
I2 => \cr_int_reg[3]_i_16_n_4\,
O => \cr_int[11]_i_102_n_0\
);
\cr_int[11]_i_104\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_104_n_0\
);
\cr_int[11]_i_105\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_105_n_0\
);
\cr_int[11]_i_106\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_106_n_0\
);
\cr_int[11]_i_107\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_107_n_0\
);
\cr_int[11]_i_109\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_6\,
I1 => \cr_int_reg[31]_i_7_n_5\,
O => \cr_int[11]_i_109_n_0\
);
\cr_int[11]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(17),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(9),
I4 => \cr_int[11]_i_24_n_0\,
I5 => \cr_int[11]_i_25_n_0\,
O => \cr_int[11]_i_11_n_0\
);
\cr_int[11]_i_110\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_4\,
I1 => \cr_int_reg[31]_i_7_n_7\,
O => \cr_int[11]_i_110_n_0\
);
\cr_int[11]_i_111\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_6\,
I1 => \cr_int_reg[31]_i_14_n_5\,
O => \cr_int[11]_i_111_n_0\
);
\cr_int[11]_i_112\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_112_n_0\
);
\cr_int[11]_i_113\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_5\,
I1 => \cr_int_reg[31]_i_7_n_6\,
O => \cr_int[11]_i_113_n_0\
);
\cr_int[11]_i_114\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_7\,
I1 => \cr_int_reg[31]_i_14_n_4\,
O => \cr_int[11]_i_114_n_0\
);
\cr_int[11]_i_115\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_5\,
I1 => \cr_int_reg[31]_i_14_n_6\,
O => \cr_int[11]_i_115_n_0\
);
\cr_int[11]_i_117\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_7\,
I1 => \cr_int_reg[31]_i_11_n_6\,
O => \cr_int[11]_i_117_n_0\
);
\cr_int[11]_i_118\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_5\,
I1 => \cr_int_reg[31]_i_30_n_4\,
O => \cr_int[11]_i_118_n_0\
);
\cr_int[11]_i_119\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_7\,
I1 => \cr_int_reg[31]_i_30_n_6\,
O => \cr_int[11]_i_119_n_0\
);
\cr_int[11]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(17),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(9),
I4 => \cr_int[11]_i_24_n_0\,
I5 => \cr_int[11]_i_25_n_0\,
O => \cr_int[11]_i_12_n_0\
);
\cr_int[11]_i_120\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_5\,
I1 => \cr_int_reg[3]_i_16_n_4\,
O => \cr_int[11]_i_120_n_0\
);
\cr_int[11]_i_121\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_6\,
I1 => \cr_int_reg[31]_i_11_n_7\,
O => \cr_int[11]_i_121_n_0\
);
\cr_int[11]_i_122\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_4\,
I1 => \cr_int_reg[31]_i_30_n_5\,
O => \cr_int[11]_i_122_n_0\
);
\cr_int[11]_i_123\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_6\,
I1 => \cr_int_reg[31]_i_30_n_7\,
O => \cr_int[11]_i_123_n_0\
);
\cr_int[11]_i_124\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_4\,
I1 => \cr_int_reg[3]_i_16_n_5\,
O => \cr_int[11]_i_124_n_0\
);
\cr_int[11]_i_126\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cr_int_reg[7]_0\(3),
I1 => \^cr_int_reg[31]_2\(0),
O => \cr_int[11]_i_126_n_0\
);
\cr_int[11]_i_127\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cr_int_reg[7]_0\(1),
I1 => \^cr_int_reg[7]_0\(2),
O => \cr_int[11]_i_127_n_0\
);
\cr_int[11]_i_128\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cr_int_reg[3]_0\(2),
I1 => \^cr_int_reg[7]_0\(0),
O => \cr_int[11]_i_128_n_0\
);
\cr_int[11]_i_129\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cr_int_reg[3]_0\(0),
I1 => \^cr_int_reg[3]_0\(1),
O => \cr_int[11]_i_129_n_0\
);
\cr_int[11]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"8EEE8E888EEE8EEE"
)
port map (
I0 => \cr_int_reg3__0\(8),
I1 => \cr_int[11]_i_27_n_0\,
I2 => \cr_int_reg[11]_i_16_n_4\,
I3 => \^cr_int_reg[27]_2\(0),
I4 => \cr_int_reg[11]_i_17_n_0\,
I5 => \cr_int_reg[11]_i_18_n_4\,
O => \cr_int[11]_i_13_n_0\
);
\cr_int[11]_i_130\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(0),
I1 => \^cr_int_reg[7]_0\(3),
O => \cr_int[11]_i_130_n_0\
);
\cr_int[11]_i_131\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(2),
I1 => \^cr_int_reg[7]_0\(1),
O => \cr_int[11]_i_131_n_0\
);
\cr_int[11]_i_132\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(0),
I1 => \^cr_int_reg[3]_0\(2),
O => \cr_int[11]_i_132_n_0\
);
\cr_int[11]_i_133\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[3]_0\(1),
I1 => \^cr_int_reg[3]_0\(0),
O => \cr_int[11]_i_133_n_0\
);
\cr_int[11]_i_134\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_4\,
I1 => \cr_int_reg[31]_i_14_n_7\,
O => \cr_int[11]_i_134_n_0\
);
\cr_int[11]_i_135\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_6\,
I1 => \cr_int_reg[31]_i_39_n_5\,
O => \cr_int[11]_i_135_n_0\
);
\cr_int[11]_i_136\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_6\,
I1 => \cr_int_reg[31]_i_39_n_7\,
O => \cr_int[11]_i_136_n_0\
);
\cr_int[11]_i_137\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb888(0),
I1 => \cr_int_reg[31]_i_86_n_7\,
O => \cr_int[11]_i_137_n_0\
);
\cr_int[11]_i_138\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_7\,
I1 => \cr_int_reg[31]_i_39_n_4\,
O => \cr_int[11]_i_138_n_0\
);
\cr_int[11]_i_139\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_5\,
I1 => \cr_int_reg[31]_i_39_n_6\,
O => \cr_int[11]_i_139_n_0\
);
\cr_int[11]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"6999696669996999"
)
port map (
I0 => \cr_int_reg3__0\(8),
I1 => \cr_int[11]_i_27_n_0\,
I2 => \cr_int_reg[11]_i_16_n_4\,
I3 => \^cr_int_reg[27]_2\(0),
I4 => \cr_int_reg[11]_i_17_n_0\,
I5 => \cr_int_reg[11]_i_18_n_4\,
O => \cr_int[11]_i_14_n_0\
);
\cr_int[11]_i_140\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_7\,
I1 => \cr_int_reg[31]_i_86_n_6\,
O => \cr_int[11]_i_140_n_0\
);
\cr_int[11]_i_141\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_7\,
I1 => rgb888(0),
O => \cr_int[11]_i_141_n_0\
);
\cr_int[11]_i_142\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_7\,
I1 => \cr_int_reg[3]_i_16_n_6\,
O => \cr_int[11]_i_142_n_0\
);
\cr_int[11]_i_143\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_7\,
I1 => \cr_int_reg[3]_i_27_n_6\,
O => \cr_int[11]_i_143_n_0\
);
\cr_int[11]_i_144\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_5\,
I1 => \cr_int_reg[3]_i_54_n_4\,
O => \cr_int[11]_i_144_n_0\
);
\cr_int[11]_i_145\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_7\,
I1 => \cr_int_reg[3]_i_54_n_6\,
O => \cr_int[11]_i_145_n_0\
);
\cr_int[11]_i_146\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_6\,
I1 => \cr_int_reg[3]_i_16_n_7\,
O => \cr_int[11]_i_146_n_0\
);
\cr_int[11]_i_147\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_6\,
I1 => \cr_int_reg[3]_i_27_n_7\,
O => \cr_int[11]_i_147_n_0\
);
\cr_int[11]_i_148\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_4\,
I1 => \cr_int_reg[3]_i_54_n_5\,
O => \cr_int[11]_i_148_n_0\
);
\cr_int[11]_i_149\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_6\,
I1 => \cr_int_reg[3]_i_54_n_7\,
O => \cr_int[11]_i_149_n_0\
);
\cr_int[11]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_13\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[11]_0\(1),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[31]_2\(0),
O => \cr_int[11]_i_15_n_0\
);
\cr_int[11]_i_150\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_4\,
I1 => \cr_int_reg[3]_i_19_n_7\,
O => \cr_int[11]_i_150_n_0\
);
\cr_int[11]_i_151\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_6\,
I1 => \cr_int_reg[3]_i_33_n_5\,
O => \cr_int[11]_i_151_n_0\
);
\cr_int[11]_i_152\: unisim.vcomponents.LUT3
generic map(
INIT => X"BE"
)
port map (
I0 => \cr_int_reg[3]_i_65_n_6\,
I1 => \cr_int_reg[3]_i_65_n_5\,
I2 => rgb888(8),
O => \cr_int[11]_i_152_n_0\
);
\cr_int[11]_i_153\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_19_n_7\,
I1 => \cr_int_reg[3]_i_33_n_4\,
O => \cr_int[11]_i_153_n_0\
);
\cr_int[11]_i_154\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_5\,
I1 => \cr_int_reg[3]_i_33_n_6\,
O => \cr_int[11]_i_154_n_0\
);
\cr_int[11]_i_155\: unisim.vcomponents.LUT3
generic map(
INIT => X"09"
)
port map (
I0 => rgb888(8),
I1 => \cr_int_reg[3]_i_65_n_5\,
I2 => \cr_int_reg[3]_i_65_n_6\,
O => \cr_int[11]_i_155_n_0\
);
\cr_int[11]_i_156\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_94_n_7\,
O => \cr_int[11]_i_156_n_0\
);
\cr_int[11]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[11]_i_10_n_0\,
I1 => \cr_int[11]_i_11_n_0\,
O => \cr_int[11]_i_2_n_0\
);
\cr_int[11]_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"0DFDF202"
)
port map (
I0 => \cr_int_reg[11]_i_18_n_5\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \^cr_int_reg[27]_2\(0),
I3 => \cr_int_reg[11]_i_16_n_5\,
I4 => \cr_int[11]_i_15_n_0\,
O => \cr_int[11]_i_22_n_0\
);
\cr_int[11]_i_23\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF0DFD"
)
port map (
I0 => \cr_int_reg[11]_i_18_n_5\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \^cr_int_reg[27]_2\(0),
I3 => \cr_int_reg[11]_i_16_n_5\,
I4 => \cr_int[11]_i_15_n_0\,
O => \cr_int[11]_i_23_n_0\
);
\cr_int[11]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_14\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[11]_0\(3),
O => \cr_int[11]_i_24_n_0\
);
\cr_int[11]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[15]_i_38_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]\(0),
O => \cr_int[11]_i_25_n_0\
);
\cr_int[11]_i_26\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(8),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_11_n_5\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(16),
O => \cr_int_reg3__0\(8)
);
\cr_int[11]_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_13\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[11]_0\(2),
O => \cr_int[11]_i_27_n_0\
);
\cr_int[11]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[11]_i_12_n_0\,
I1 => \cr_int[11]_i_13_n_0\,
O => \cr_int[11]_i_3_n_0\
);
\cr_int[11]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[11]_i_18_n_4\,
O => \cr_int[11]_i_32_n_0\
);
\cr_int[11]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[11]_i_18_n_5\,
O => \cr_int[11]_i_33_n_0\
);
\cr_int[11]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[11]_i_18_n_6\,
O => \cr_int[11]_i_34_n_0\
);
\cr_int[11]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_18_n_7\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_7_n_5\,
O => \cr_int[11]_i_35_n_0\
);
\cr_int[11]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_37_n_0\
);
\cr_int[11]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_38_n_0\
);
\cr_int[11]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_39_n_0\
);
\cr_int[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAA8A888AAA8AAA"
)
port map (
I0 => \cr_int[11]_i_14_n_0\,
I1 => \cr_int[11]_i_15_n_0\,
I2 => \cr_int_reg[11]_i_16_n_5\,
I3 => \^cr_int_reg[27]_2\(0),
I4 => \cr_int_reg[11]_i_17_n_0\,
I5 => \cr_int_reg[11]_i_18_n_5\,
O => \cr_int[11]_i_4_n_0\
);
\cr_int[11]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_40_n_0\
);
\cr_int[11]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_42_n_0\
);
\cr_int[11]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_43_n_0\
);
\cr_int[11]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_44_n_0\
);
\cr_int[11]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_5\,
O => \cr_int[11]_i_45_n_0\
);
\cr_int[11]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_5\,
O => \cr_int[11]_i_47_n_0\
);
\cr_int[11]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_6\,
O => \cr_int[11]_i_48_n_0\
);
\cr_int[11]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_7\,
O => \cr_int[11]_i_49_n_0\
);
\cr_int[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE200E200000000"
)
port map (
I0 => cr_int_reg6(15),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_11_n_6\,
I3 => \cr_int_reg[31]_i_11_n_4\,
I4 => cr_int_reg4(7),
I5 => \cr_int[11]_i_22_n_0\,
O => \cr_int[11]_i_5_n_0\
);
\cr_int[11]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_4\,
O => \cr_int[11]_i_50_n_0\
);
\cr_int[11]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_52_n_0\
);
\cr_int[11]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_53_n_0\
);
\cr_int[11]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_54_n_0\
);
\cr_int[11]_i_55\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_55_n_0\
);
\cr_int[11]_i_57\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(16),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_11_n_5\,
O => \cr_int[11]_i_57_n_0\
);
\cr_int[11]_i_58\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(15),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_11_n_6\,
O => \cr_int[11]_i_58_n_0\
);
\cr_int[11]_i_59\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(14),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_11_n_7\,
O => \cr_int[11]_i_59_n_0\
);
\cr_int[11]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[15]_i_16_n_0\,
I1 => \cr_int[15]_i_17_n_0\,
I2 => \cr_int[11]_i_2_n_0\,
O => \cr_int[11]_i_6_n_0\
);
\cr_int[11]_i_60\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(13),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_30_n_4\,
O => \cr_int[11]_i_60_n_0\
);
\cr_int[11]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_65_n_0\
);
\cr_int[11]_i_66\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_66_n_0\
);
\cr_int[11]_i_67\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(0),
O => \cr_int[11]_i_67_n_0\
);
\cr_int[11]_i_68\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(3),
O => \cr_int[11]_i_68_n_0\
);
\cr_int[11]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[11]_i_10_n_0\,
I1 => \cr_int[11]_i_11_n_0\,
I2 => \cr_int[11]_i_3_n_0\,
O => \cr_int[11]_i_7_n_0\
);
\cr_int[11]_i_70\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_70_n_0\
);
\cr_int[11]_i_71\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_71_n_0\
);
\cr_int[11]_i_72\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_72_n_0\
);
\cr_int[11]_i_73\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_73_n_0\
);
\cr_int[11]_i_74\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[3]_i_32_n_4\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_14_n_6\,
O => \cr_int[11]_i_74_n_0\
);
\cr_int[11]_i_75\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_41_n_4\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_7_n_6\,
O => \cr_int[11]_i_75_n_0\
);
\cr_int[11]_i_76\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_41_n_5\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_7_n_7\,
O => \cr_int[11]_i_76_n_0\
);
\cr_int[11]_i_77\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_41_n_6\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_14_n_4\,
O => \cr_int[11]_i_77_n_0\
);
\cr_int[11]_i_78\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_41_n_7\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_14_n_5\,
O => \cr_int[11]_i_78_n_0\
);
\cr_int[11]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[11]_i_12_n_0\,
I1 => \cr_int[11]_i_13_n_0\,
I2 => \cr_int[11]_i_4_n_0\,
O => \cr_int[11]_i_8_n_0\
);
\cr_int[11]_i_80\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_80_n_0\
);
\cr_int[11]_i_81\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_81_n_0\
);
\cr_int[11]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_82_n_0\
);
\cr_int[11]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_83_n_0\
);
\cr_int[11]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_6\,
O => \cr_int[11]_i_84_n_0\
);
\cr_int[11]_i_85\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_7\,
O => \cr_int[11]_i_85_n_0\
);
\cr_int[11]_i_86\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_4\,
O => \cr_int[11]_i_86_n_0\
);
\cr_int[11]_i_87\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_5\,
O => \cr_int[11]_i_87_n_0\
);
\cr_int[11]_i_88\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_5\,
O => \cr_int[11]_i_88_n_0\
);
\cr_int[11]_i_89\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_6\,
O => \cr_int[11]_i_89_n_0\
);
\cr_int[11]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[11]_i_5_n_0\,
I1 => \cr_int[11]_i_14_n_0\,
I2 => \cr_int[11]_i_23_n_0\,
O => \cr_int[11]_i_9_n_0\
);
\cr_int[11]_i_90\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_7\,
O => \cr_int[11]_i_90_n_0\
);
\cr_int[11]_i_91\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_4\,
O => \cr_int[11]_i_91_n_0\
);
\cr_int[11]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_5\,
I1 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_93_n_0\
);
\cr_int[11]_i_94\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_94_n_0\
);
\cr_int[11]_i_95\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_95_n_0\
);
\cr_int[11]_i_96\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_96_n_0\
);
\cr_int[11]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => \cr_int_reg[31]_i_11_n_5\,
O => \cr_int[11]_i_97_n_0\
);
\cr_int[11]_i_98\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(8),
I1 => cr_int_reg7,
I2 => \cr_int_reg[3]_i_16_n_5\,
O => \cr_int[11]_i_98_n_0\
);
\cr_int[11]_i_99\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(12),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_30_n_5\,
O => \cr_int[11]_i_99_n_0\
);
\cr_int[15]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(22),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(14),
I4 => \cr_int[19]_i_26_n_0\,
I5 => \cr_int[19]_i_27_n_0\,
O => \cr_int[15]_i_10_n_0\
);
\cr_int[15]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(21),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(13),
I4 => \cr_int[15]_i_18_n_0\,
I5 => \cr_int[15]_i_19_n_0\,
O => \cr_int[15]_i_11_n_0\
);
\cr_int[15]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(21),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(13),
I4 => \cr_int[15]_i_18_n_0\,
I5 => \cr_int[15]_i_19_n_0\,
O => \cr_int[15]_i_12_n_0\
);
\cr_int[15]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(20),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(12),
I4 => \cr_int[15]_i_22_n_0\,
I5 => \cr_int[15]_i_23_n_0\,
O => \cr_int[15]_i_13_n_0\
);
\cr_int[15]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(20),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(12),
I4 => \cr_int[15]_i_22_n_0\,
I5 => \cr_int[15]_i_23_n_0\,
O => \cr_int[15]_i_14_n_0\
);
\cr_int[15]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(19),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(11),
I4 => \cr_int[15]_i_24_n_0\,
I5 => \cr_int[15]_i_25_n_0\,
O => \cr_int[15]_i_15_n_0\
);
\cr_int[15]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(19),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(11),
I4 => \cr_int[15]_i_24_n_0\,
I5 => \cr_int[15]_i_25_n_0\,
O => \cr_int[15]_i_16_n_0\
);
\cr_int[15]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(18),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(10),
I4 => \cr_int[15]_i_26_n_0\,
I5 => \cr_int[15]_i_27_n_0\,
O => \cr_int[15]_i_17_n_0\
);
\cr_int[15]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_15\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[15]_0\(3),
O => \cr_int[15]_i_18_n_0\
);
\cr_int[15]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_49_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]_0\(0),
O => \cr_int[15]_i_19_n_0\
);
\cr_int[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[15]_i_10_n_0\,
I1 => \cr_int[15]_i_11_n_0\,
O => \cr_int[15]_i_2_n_0\
);
\cr_int[15]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_14\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[15]_0\(2),
O => \cr_int[15]_i_22_n_0\
);
\cr_int[15]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[15]_i_38_n_4\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]\(3),
O => \cr_int[15]_i_23_n_0\
);
\cr_int[15]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_14\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[15]_0\(1),
O => \cr_int[15]_i_24_n_0\
);
\cr_int[15]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[15]_i_38_n_5\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]\(2),
O => \cr_int[15]_i_25_n_0\
);
\cr_int[15]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_14\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[15]_0\(0),
O => \cr_int[15]_i_26_n_0\
);
\cr_int[15]_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[15]_i_38_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]\(1),
O => \cr_int[15]_i_27_n_0\
);
\cr_int[15]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[15]_i_29_n_0\
);
\cr_int[15]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[15]_i_12_n_0\,
I1 => \cr_int[15]_i_13_n_0\,
O => \cr_int[15]_i_3_n_0\
);
\cr_int[15]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[15]_i_30_n_0\
);
\cr_int[15]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[15]_i_31_n_0\
);
\cr_int[15]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[15]_i_32_n_0\
);
\cr_int[15]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(20),
O => \cr_int[15]_i_33_n_0\
);
\cr_int[15]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(19),
O => \cr_int[15]_i_34_n_0\
);
\cr_int[15]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(18),
O => \cr_int[15]_i_35_n_0\
);
\cr_int[15]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(17),
O => \cr_int[15]_i_36_n_0\
);
\cr_int[15]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[15]_i_14_n_0\,
I1 => \cr_int[15]_i_15_n_0\,
O => \cr_int[15]_i_4_n_0\
);
\cr_int[15]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[15]_i_40_n_0\
);
\cr_int[15]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[15]_i_41_n_0\
);
\cr_int[15]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[15]_i_42_n_0\
);
\cr_int[15]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[15]_i_43_n_0\
);
\cr_int[15]_i_48\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]\(3),
O => \cr_int[15]_i_48_n_0\
);
\cr_int[15]_i_49\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]\(2),
O => \cr_int[15]_i_49_n_0\
);
\cr_int[15]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[15]_i_16_n_0\,
I1 => \cr_int[15]_i_17_n_0\,
O => \cr_int[15]_i_5_n_0\
);
\cr_int[15]_i_50\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]\(1),
O => \cr_int[15]_i_50_n_0\
);
\cr_int[15]_i_51\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]\(0),
O => \cr_int[15]_i_51_n_0\
);
\cr_int[15]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[19]_i_16_n_0\,
I1 => \cr_int[19]_i_17_n_0\,
I2 => \cr_int[15]_i_2_n_0\,
O => \cr_int[15]_i_6_n_0\
);
\cr_int[15]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[15]_i_10_n_0\,
I1 => \cr_int[15]_i_11_n_0\,
I2 => \cr_int[15]_i_3_n_0\,
O => \cr_int[15]_i_7_n_0\
);
\cr_int[15]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[15]_i_12_n_0\,
I1 => \cr_int[15]_i_13_n_0\,
I2 => \cr_int[15]_i_4_n_0\,
O => \cr_int[15]_i_8_n_0\
);
\cr_int[15]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[15]_i_14_n_0\,
I1 => \cr_int[15]_i_15_n_0\,
I2 => \cr_int[15]_i_5_n_0\,
O => \cr_int[15]_i_9_n_0\
);
\cr_int[19]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(26),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(18),
I4 => \cr_int[23]_i_25_n_0\,
I5 => \cr_int[23]_i_26_n_0\,
O => \cr_int[19]_i_10_n_0\
);
\cr_int[19]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(25),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(17),
I4 => \cr_int[19]_i_18_n_0\,
I5 => \cr_int[19]_i_19_n_0\,
O => \cr_int[19]_i_11_n_0\
);
\cr_int[19]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(25),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(17),
I4 => \cr_int[19]_i_18_n_0\,
I5 => \cr_int[19]_i_19_n_0\,
O => \cr_int[19]_i_12_n_0\
);
\cr_int[19]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(24),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(16),
I4 => \cr_int[19]_i_22_n_0\,
I5 => \cr_int[19]_i_23_n_0\,
O => \cr_int[19]_i_13_n_0\
);
\cr_int[19]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(24),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(16),
I4 => \cr_int[19]_i_22_n_0\,
I5 => \cr_int[19]_i_23_n_0\,
O => \cr_int[19]_i_14_n_0\
);
\cr_int[19]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(23),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(15),
I4 => \cr_int[19]_i_24_n_0\,
I5 => \cr_int[19]_i_25_n_0\,
O => \cr_int[19]_i_15_n_0\
);
\cr_int[19]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(23),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(15),
I4 => \cr_int[19]_i_24_n_0\,
I5 => \cr_int[19]_i_25_n_0\,
O => \cr_int[19]_i_16_n_0\
);
\cr_int[19]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(22),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(14),
I4 => \cr_int[19]_i_26_n_0\,
I5 => \cr_int[19]_i_27_n_0\,
O => \cr_int[19]_i_17_n_0\
);
\cr_int[19]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_16\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[19]_0\(3),
O => \cr_int[19]_i_18_n_0\
);
\cr_int[19]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_21_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_5\(0),
O => \cr_int[19]_i_19_n_0\
);
\cr_int[19]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[19]_i_10_n_0\,
I1 => \cr_int[19]_i_11_n_0\,
O => \cr_int[19]_i_2_n_0\
);
\cr_int[19]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_15\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[19]_0\(2),
O => \cr_int[19]_i_22_n_0\
);
\cr_int[19]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_49_n_4\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]_0\(3),
O => \cr_int[19]_i_23_n_0\
);
\cr_int[19]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_15\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[19]_0\(1),
O => \cr_int[19]_i_24_n_0\
);
\cr_int[19]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_49_n_5\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]_0\(2),
O => \cr_int[19]_i_25_n_0\
);
\cr_int[19]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_15\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[19]_0\(0),
O => \cr_int[19]_i_26_n_0\
);
\cr_int[19]_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_49_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]_0\(1),
O => \cr_int[19]_i_27_n_0\
);
\cr_int[19]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[19]_i_29_n_0\
);
\cr_int[19]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[19]_i_12_n_0\,
I1 => \cr_int[19]_i_13_n_0\,
O => \cr_int[19]_i_3_n_0\
);
\cr_int[19]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[19]_i_30_n_0\
);
\cr_int[19]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[19]_i_31_n_0\
);
\cr_int[19]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[19]_i_32_n_0\
);
\cr_int[19]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(24),
O => \cr_int[19]_i_33_n_0\
);
\cr_int[19]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(23),
O => \cr_int[19]_i_34_n_0\
);
\cr_int[19]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(22),
O => \cr_int[19]_i_35_n_0\
);
\cr_int[19]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(21),
O => \cr_int[19]_i_36_n_0\
);
\cr_int[19]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[19]_i_38_n_0\
);
\cr_int[19]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[19]_i_39_n_0\
);
\cr_int[19]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[19]_i_14_n_0\,
I1 => \cr_int[19]_i_15_n_0\,
O => \cr_int[19]_i_4_n_0\
);
\cr_int[19]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[19]_i_40_n_0\
);
\cr_int[19]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[19]_i_41_n_0\
);
\cr_int[19]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[19]_i_16_n_0\,
I1 => \cr_int[19]_i_17_n_0\,
O => \cr_int[19]_i_5_n_0\
);
\cr_int[19]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[23]_i_16_n_0\,
I1 => \cr_int[23]_i_17_n_0\,
I2 => \cr_int[19]_i_2_n_0\,
O => \cr_int[19]_i_6_n_0\
);
\cr_int[19]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[19]_i_10_n_0\,
I1 => \cr_int[19]_i_11_n_0\,
I2 => \cr_int[19]_i_3_n_0\,
O => \cr_int[19]_i_7_n_0\
);
\cr_int[19]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[19]_i_12_n_0\,
I1 => \cr_int[19]_i_13_n_0\,
I2 => \cr_int[19]_i_4_n_0\,
O => \cr_int[19]_i_8_n_0\
);
\cr_int[19]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[19]_i_14_n_0\,
I1 => \cr_int[19]_i_15_n_0\,
I2 => \cr_int[19]_i_5_n_0\,
O => \cr_int[19]_i_9_n_0\
);
\cr_int[23]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(30),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(22),
I4 => \cr_int[27]_i_10_n_0\,
I5 => \cr_int[27]_i_11_n_0\,
O => \cr_int[23]_i_10_n_0\
);
\cr_int[23]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(29),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(21),
I4 => \cr_int[23]_i_18_n_0\,
I5 => \cr_int[23]_i_19_n_0\,
O => \cr_int[23]_i_11_n_0\
);
\cr_int[23]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(29),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(21),
I4 => \cr_int[23]_i_18_n_0\,
I5 => \cr_int[23]_i_19_n_0\,
O => \cr_int[23]_i_12_n_0\
);
\cr_int[23]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(28),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(20),
I4 => \cr_int[23]_i_21_n_0\,
I5 => \cr_int[23]_i_22_n_0\,
O => \cr_int[23]_i_13_n_0\
);
\cr_int[23]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(28),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(20),
I4 => \cr_int[23]_i_21_n_0\,
I5 => \cr_int[23]_i_22_n_0\,
O => \cr_int[23]_i_14_n_0\
);
\cr_int[23]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(27),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(19),
I4 => \cr_int[23]_i_23_n_0\,
I5 => \cr_int[23]_i_24_n_0\,
O => \cr_int[23]_i_15_n_0\
);
\cr_int[23]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(27),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(19),
I4 => \cr_int[23]_i_23_n_0\,
I5 => \cr_int[23]_i_24_n_0\,
O => \cr_int[23]_i_16_n_0\
);
\cr_int[23]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(26),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(18),
I4 => \cr_int[23]_i_25_n_0\,
I5 => \cr_int[23]_i_26_n_0\,
O => \cr_int[23]_i_17_n_0\
);
\cr_int[23]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_17\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_0\(3),
O => \cr_int[23]_i_18_n_0\
);
\cr_int[23]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_8_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_6\(0),
O => \cr_int[23]_i_19_n_0\
);
\cr_int[23]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[23]_i_10_n_0\,
I1 => \cr_int[23]_i_11_n_0\,
O => \cr_int[23]_i_2_n_0\
);
\cr_int[23]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_16\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_0\(2),
O => \cr_int[23]_i_21_n_0\
);
\cr_int[23]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_21_n_4\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_5\(3),
O => \cr_int[23]_i_22_n_0\
);
\cr_int[23]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_16\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_0\(1),
O => \cr_int[23]_i_23_n_0\
);
\cr_int[23]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_21_n_5\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_5\(2),
O => \cr_int[23]_i_24_n_0\
);
\cr_int[23]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_16\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_0\(0),
O => \cr_int[23]_i_25_n_0\
);
\cr_int[23]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_21_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_5\(1),
O => \cr_int[23]_i_26_n_0\
);
\cr_int[23]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[23]_i_27_n_0\
);
\cr_int[23]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[23]_i_28_n_0\
);
\cr_int[23]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[23]_i_29_n_0\
);
\cr_int[23]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[23]_i_12_n_0\,
I1 => \cr_int[23]_i_13_n_0\,
O => \cr_int[23]_i_3_n_0\
);
\cr_int[23]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[23]_i_30_n_0\
);
\cr_int[23]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[23]_i_14_n_0\,
I1 => \cr_int[23]_i_15_n_0\,
O => \cr_int[23]_i_4_n_0\
);
\cr_int[23]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[23]_i_16_n_0\,
I1 => \cr_int[23]_i_17_n_0\,
O => \cr_int[23]_i_5_n_0\
);
\cr_int[23]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[27]_i_7_n_0\,
I1 => \cr_int[27]_i_8_n_0\,
I2 => \cr_int[23]_i_2_n_0\,
O => \cr_int[23]_i_6_n_0\
);
\cr_int[23]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[23]_i_10_n_0\,
I1 => \cr_int[23]_i_11_n_0\,
I2 => \cr_int[23]_i_3_n_0\,
O => \cr_int[23]_i_7_n_0\
);
\cr_int[23]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[23]_i_12_n_0\,
I1 => \cr_int[23]_i_13_n_0\,
I2 => \cr_int[23]_i_4_n_0\,
O => \cr_int[23]_i_8_n_0\
);
\cr_int[23]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[23]_i_14_n_0\,
I1 => \cr_int[23]_i_15_n_0\,
I2 => \cr_int[23]_i_5_n_0\,
O => \cr_int[23]_i_9_n_0\
);
\cr_int[27]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_17\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_1\(0),
O => \cr_int[27]_i_10_n_0\
);
\cr_int[27]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_8_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_6\(1),
O => \cr_int[27]_i_11_n_0\
);
\cr_int[27]_i_12\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[27]_i_12_n_0\
);
\cr_int[27]_i_13\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[27]_i_13_n_0\
);
\cr_int[27]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[27]_i_7_n_0\,
I1 => \cr_int[27]_i_8_n_0\,
O => \cr_int[27]_i_2_n_0\
);
\cr_int[27]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_3_n_0\
);
\cr_int[27]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_4_n_0\
);
\cr_int[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_5_n_0\
);
\cr_int[27]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[27]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_6_n_0\
);
\cr_int[27]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"4B44B4BB4B444B44"
)
port map (
I0 => \cr_int_reg[31]_i_12_n_1\,
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \rgb888[8]_18\(0),
I3 => \^cr_int_reg[31]_2\(1),
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_7_n_0\
);
\cr_int[27]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(30),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(22),
I4 => \cr_int[27]_i_10_n_0\,
I5 => \cr_int[27]_i_11_n_0\,
O => \cr_int[27]_i_8_n_0\
);
\cr_int[31]_i_100\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => rgb888(13),
I1 => rgb888(11),
I2 => rgb888(10),
I3 => rgb888(12),
I4 => rgb888(14),
I5 => rgb888(15),
O => \cr_int[31]_i_100_n_0\
);
\cr_int[31]_i_103\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \cr_int[31]_i_103_n_0\
);
\cr_int[31]_i_108\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_108_n_0\
);
\cr_int[31]_i_109\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_109_n_0\
);
\cr_int[31]_i_110\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_110_n_0\
);
\cr_int[31]_i_111\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_111_n_0\
);
\cr_int[31]_i_112\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_112_n_0\
);
\cr_int[31]_i_113\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
O => \cr_int[31]_i_113_n_0\
);
\cr_int[31]_i_114\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
O => \cr_int[31]_i_114_n_0\
);
\cr_int[31]_i_115\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(2),
I1 => rgb888(0),
O => \cr_int[31]_i_115_n_0\
);
\cr_int[31]_i_116\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(1),
O => \cr_int[31]_i_116_n_0\
);
\cr_int[31]_i_117\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(6),
O => \cr_int[31]_i_117_n_0\
);
\cr_int[31]_i_118\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(7),
I1 => rgb888(5),
O => \cr_int[31]_i_118_n_0\
);
\cr_int[31]_i_119\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
O => \cr_int[31]_i_119_n_0\
);
\cr_int[31]_i_120\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
O => \cr_int[31]_i_120_n_0\
);
\cr_int[31]_i_121\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \cr_int[31]_i_121_n_0\
);
\cr_int[31]_i_122\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(15),
I1 => rgb888(14),
O => \cr_int[31]_i_122_n_0\
);
\cr_int[31]_i_123\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(14),
O => \cr_int[31]_i_123_n_0\
);
\cr_int[31]_i_124\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
O => \cr_int[31]_i_124_n_0\
);
\cr_int[31]_i_125\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(14),
I1 => rgb888(12),
O => \cr_int[31]_i_125_n_0\
);
\cr_int[31]_i_126\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(13),
I1 => rgb888(11),
O => \cr_int[31]_i_126_n_0\
);
\cr_int[31]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \rgb888[8]_18\(0),
I1 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_13_n_0\
);
\cr_int[31]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"60"
)
port map (
I0 => \^cr_int_reg[27]_0\,
I1 => rgb888(7),
I2 => \cr_int_reg[31]_i_48_n_2\,
O => \cr_int[31]_i_15_n_0\
);
\cr_int[31]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_1\(1),
I1 => \cr_int_reg[31]_i_48_n_2\,
O => \cr_int[31]_i_16_n_0\
);
\cr_int[31]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => \^cr_int_reg[27]_0\,
O => \cr_int[31]_i_17_n_0\
);
\cr_int[31]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => \^cr_int_reg[27]_0\,
O => \cr_int[31]_i_18_n_0\
);
\cr_int[31]_i_19\: unisim.vcomponents.LUT3
generic map(
INIT => X"17"
)
port map (
I0 => \cr_int_reg[31]_i_48_n_2\,
I1 => \^cr_int_reg[27]_0\,
I2 => rgb888(7),
O => \cr_int[31]_i_19_n_0\
);
\cr_int[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000DD0D0000"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[31]_i_8_n_1\,
I2 => \^cr_int_reg[31]_2\(1),
I3 => \rgb888[8]_18\(0),
I4 => \cr_int_reg[31]_i_11_n_4\,
I5 => \cr_int_reg[31]_i_12_n_1\,
O => \cr_int[31]_i_2_n_0\
);
\cr_int[31]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \^cr_int_reg[27]_0\,
I1 => rgb888(7),
I2 => \cr_int[31]_i_16_n_0\,
I3 => \cr_int_reg[31]_i_48_n_2\,
O => \cr_int[31]_i_20_n_0\
);
\cr_int[31]_i_22\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_6\(1),
O => \cr_int[31]_i_22_n_0\
);
\cr_int[31]_i_23\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_6\(0),
O => \cr_int[31]_i_23_n_0\
);
\cr_int[31]_i_25\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \cr_int[31]_i_25_n_0\
);
\cr_int[31]_i_26\: unisim.vcomponents.LUT2
generic map(
INIT => X"4"
)
port map (
I0 => \cr_int_reg[31]_i_63_n_2\,
I1 => \^di\(0),
O => \cr_int[31]_i_26_n_0\
);
\cr_int[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[31]_i_3_n_0\
);
\cr_int[31]_i_31\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA9"
)
port map (
I0 => rgb888(22),
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(17),
I4 => rgb888(19),
I5 => rgb888(21),
O => \cr_int[31]_i_31_n_0\
);
\cr_int[31]_i_32\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(23),
I1 => \cr_int[31]_i_79_n_0\,
O => \cr_int[31]_i_32_n_0\
);
\cr_int[31]_i_33\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(23),
I1 => \cr_int[31]_i_79_n_0\,
O => \cr_int[31]_i_33_n_0\
);
\cr_int[31]_i_34\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(23),
I1 => \cr_int[31]_i_79_n_0\,
O => \cr_int[31]_i_34_n_0\
);
\cr_int[31]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"95"
)
port map (
I0 => rgb888(23),
I1 => \cr_int[31]_i_80_n_0\,
I2 => rgb888(22),
O => \cr_int[31]_i_35_n_0\
);
\cr_int[31]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(30),
O => \cr_int[31]_i_37_n_0\
);
\cr_int[31]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(29),
O => \cr_int[31]_i_38_n_0\
);
\cr_int[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[31]_i_4_n_0\
);
\cr_int[31]_i_40\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888888888882"
)
port map (
I0 => \cr_int_reg[31]_i_48_n_7\,
I1 => rgb888(5),
I2 => rgb888(3),
I3 => rgb888(1),
I4 => rgb888(2),
I5 => rgb888(4),
O => \cr_int[31]_i_40_n_0\
);
\cr_int[31]_i_41\: unisim.vcomponents.LUT5
generic map(
INIT => X"EEEEEEEB"
)
port map (
I0 => \cr_int_reg[31]_i_91_n_4\,
I1 => rgb888(4),
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
O => \cr_int[31]_i_41_n_0\
);
\cr_int[31]_i_42\: unisim.vcomponents.LUT5
generic map(
INIT => X"99999996"
)
port map (
I0 => \cr_int_reg[31]_i_91_n_4\,
I1 => rgb888(4),
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
O => \cr_int[31]_i_42_n_0\
);
\cr_int[31]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"82"
)
port map (
I0 => \cr_int_reg[31]_i_91_n_6\,
I1 => rgb888(2),
I2 => rgb888(1),
O => \cr_int[31]_i_43_n_0\
);
\cr_int[31]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^cr_int_reg[27]_1\(1),
I1 => \cr_int_reg[31]_i_48_n_2\,
I2 => \cr_int[31]_i_40_n_0\,
O => \cr_int[31]_i_44_n_0\
);
\cr_int[31]_i_45\: unisim.vcomponents.LUT4
generic map(
INIT => X"1EE1"
)
port map (
I0 => \cr_int[31]_i_92_n_0\,
I1 => \cr_int_reg[31]_i_91_n_4\,
I2 => \^cr_int_reg[27]_1\(0),
I3 => \cr_int_reg[31]_i_48_n_7\,
O => \cr_int[31]_i_45_n_0\
);
\cr_int[31]_i_46\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969699999999996"
)
port map (
I0 => rgb888(4),
I1 => \cr_int_reg[31]_i_91_n_4\,
I2 => \cr_int_reg[31]_i_91_n_5\,
I3 => rgb888(2),
I4 => rgb888(1),
I5 => rgb888(3),
O => \cr_int[31]_i_46_n_0\
);
\cr_int[31]_i_47\: unisim.vcomponents.LUT5
generic map(
INIT => X"817E7E81"
)
port map (
I0 => \cr_int_reg[31]_i_91_n_6\,
I1 => rgb888(2),
I2 => rgb888(1),
I3 => rgb888(3),
I4 => \cr_int_reg[31]_i_91_n_5\,
O => \cr_int[31]_i_47_n_0\
);
\cr_int[31]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[31]_i_5_n_0\
);
\cr_int[31]_i_50\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_5\(3),
O => \cr_int[31]_i_50_n_0\
);
\cr_int[31]_i_51\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_5\(2),
O => \cr_int[31]_i_51_n_0\
);
\cr_int[31]_i_52\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_5\(1),
O => \cr_int[31]_i_52_n_0\
);
\cr_int[31]_i_53\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_5\(0),
O => \cr_int[31]_i_53_n_0\
);
\cr_int[31]_i_55\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int[31]_i_100_n_0\,
I1 => \cr_int_reg[31]_i_63_n_2\,
O => \cr_int[31]_i_55_n_0\
);
\cr_int[31]_i_56\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAA00000000"
)
port map (
I0 => rgb888(14),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => \cr_int_reg[31]_i_63_n_7\,
O => \cr_int[31]_i_56_n_0\
);
\cr_int[31]_i_57\: unisim.vcomponents.LUT6
generic map(
INIT => X"BFFFEAAA2AAA8000"
)
port map (
I0 => \cr_int_reg[31]_i_101_n_1\,
I1 => rgb888(11),
I2 => rgb888(10),
I3 => rgb888(12),
I4 => rgb888(13),
I5 => \cr_int_reg[31]_i_102_n_4\,
O => \cr_int[31]_i_57_n_0\
);
\cr_int[31]_i_58\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFEA2A80"
)
port map (
I0 => \cr_int_reg[31]_i_101_n_6\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(12),
I4 => \cr_int_reg[31]_i_102_n_5\,
O => \cr_int[31]_i_58_n_0\
);
\cr_int[31]_i_59\: unisim.vcomponents.LUT3
generic map(
INIT => X"36"
)
port map (
I0 => \cr_int[31]_i_100_n_0\,
I1 => \^di\(0),
I2 => \cr_int_reg[31]_i_63_n_2\,
O => \cr_int[31]_i_59_n_0\
);
\cr_int[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[31]_i_6_n_0\
);
\cr_int[31]_i_60\: unisim.vcomponents.LUT4
generic map(
INIT => X"7887"
)
port map (
I0 => \cr_int_reg[31]_i_63_n_7\,
I1 => \^cr_int_reg[31]_0\,
I2 => \cr_int_reg[31]_i_63_n_2\,
I3 => \cr_int[31]_i_100_n_0\,
O => \cr_int[31]_i_60_n_0\
);
\cr_int[31]_i_61\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[31]_i_57_n_0\,
I1 => \^cr_int_reg[31]_0\,
I2 => \cr_int_reg[31]_i_63_n_7\,
O => \cr_int[31]_i_61_n_0\
);
\cr_int[31]_i_62\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int[31]_i_58_n_0\,
I1 => \cr_int_reg[31]_i_102_n_4\,
I2 => \^cr_int_reg[31]_1\,
I3 => \cr_int_reg[31]_i_101_n_1\,
O => \cr_int[31]_i_62_n_0\
);
\cr_int[31]_i_71\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000001FFFFFFFE"
)
port map (
I0 => rgb888(21),
I1 => rgb888(19),
I2 => rgb888(17),
I3 => rgb888(18),
I4 => rgb888(20),
I5 => rgb888(22),
O => \cr_int[31]_i_71_n_0\
);
\cr_int[31]_i_72\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFE"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
I2 => rgb888(17),
I3 => rgb888(19),
I4 => rgb888(21),
O => \cr_int[31]_i_72_n_0\
);
\cr_int[31]_i_73\: unisim.vcomponents.LUT5
generic map(
INIT => X"99999996"
)
port map (
I0 => \cr_int_reg[3]_i_26_n_1\,
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(17),
I4 => rgb888(19),
O => \cr_int[31]_i_73_n_0\
);
\cr_int[31]_i_74\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(18),
I1 => rgb888(17),
O => \cr_int[31]_i_74_n_0\
);
\cr_int[31]_i_75\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA955555555"
)
port map (
I0 => rgb888(22),
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(17),
I4 => rgb888(19),
I5 => rgb888(21),
O => \cr_int[31]_i_75_n_0\
);
\cr_int[31]_i_76\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCC999999993"
)
port map (
I0 => \cr_int_reg[3]_i_26_n_1\,
I1 => rgb888(21),
I2 => rgb888(19),
I3 => rgb888(17),
I4 => rgb888(18),
I5 => rgb888(20),
O => \cr_int[31]_i_76_n_0\
);
\cr_int[31]_i_77\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA99995"
)
port map (
I0 => rgb888(20),
I1 => \cr_int_reg[3]_i_26_n_1\,
I2 => rgb888(18),
I3 => rgb888(17),
I4 => rgb888(19),
O => \cr_int[31]_i_77_n_0\
);
\cr_int[31]_i_78\: unisim.vcomponents.LUT4
generic map(
INIT => X"6A95"
)
port map (
I0 => \cr_int_reg[3]_i_26_n_1\,
I1 => rgb888(18),
I2 => rgb888(17),
I3 => rgb888(19),
O => \cr_int[31]_i_78_n_0\
);
\cr_int[31]_i_79\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => rgb888(21),
I1 => rgb888(19),
I2 => rgb888(17),
I3 => rgb888(18),
I4 => rgb888(20),
I5 => rgb888(22),
O => \cr_int[31]_i_79_n_0\
);
\cr_int[31]_i_80\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
I2 => rgb888(17),
I3 => rgb888(19),
I4 => rgb888(21),
O => \cr_int[31]_i_80_n_0\
);
\cr_int[31]_i_81\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(28),
O => \cr_int[31]_i_81_n_0\
);
\cr_int[31]_i_82\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(27),
O => \cr_int[31]_i_82_n_0\
);
\cr_int[31]_i_83\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(26),
O => \cr_int[31]_i_83_n_0\
);
\cr_int[31]_i_84\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(25),
O => \cr_int[31]_i_84_n_0\
);
\cr_int[31]_i_85\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
O => \cr_int[31]_i_85_n_0\
);
\cr_int[31]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(2),
I1 => \cr_int_reg[31]_i_91_n_6\,
O => \cr_int[31]_i_87_n_0\
);
\cr_int[31]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(1),
I1 => \cr_int_reg[31]_i_91_n_7\,
O => \cr_int[31]_i_88_n_0\
);
\cr_int[31]_i_89\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_4\,
I1 => rgb888(0),
O => \cr_int[31]_i_89_n_0\
);
\cr_int[31]_i_90\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_5\,
O => \cr_int[31]_i_90_n_0\
);
\cr_int[31]_i_92\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE01"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
I2 => rgb888(2),
I3 => rgb888(4),
O => \cr_int[31]_i_92_n_0\
);
\cr_int[31]_i_93\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(7),
O => \cr_int[31]_i_93_n_0\
);
\cr_int[31]_i_94\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]_0\(3),
O => \cr_int[31]_i_94_n_0\
);
\cr_int[31]_i_95\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]_0\(2),
O => \cr_int[31]_i_95_n_0\
);
\cr_int[31]_i_96\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]_0\(1),
O => \cr_int[31]_i_96_n_0\
);
\cr_int[31]_i_97\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]_0\(0),
O => \cr_int[31]_i_97_n_0\
);
\cr_int[3]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_12\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[7]_1\(0),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[3]_0\(2),
O => \cr_int[3]_i_10_n_0\
);
\cr_int[3]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_31_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_41_n_6\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_14_n_4\,
O => \cr_int[3]_i_11_n_0\
);
\cr_int[3]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(1),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[3]_i_16_n_4\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(9),
O => \cr_int_reg3__0\(1)
);
\cr_int[3]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_12\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_2\(1),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[3]_0\(1),
O => \cr_int[3]_i_13_n_0\
);
\cr_int[3]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_31_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_41_n_7\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_14_n_5\,
O => \cr_int[3]_i_14_n_0\
);
\cr_int[3]_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^cr_int_reg[3]_0\(0),
I1 => \^cr_int_reg[3]_1\(0),
I2 => \^cr_int_reg[3]_2\(0),
O => \cr_int[3]_i_17_n_0\
);
\cr_int[3]_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_6\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[3]_i_32_n_4\,
O => \cr_int[3]_i_18_n_0\
);
\cr_int[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(2),
I1 => \cr_int[3]_i_10_n_0\,
I2 => \cr_int[3]_i_11_n_0\,
O => \cr_int[3]_i_2_n_0\
);
\cr_int[3]_i_22\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_5\,
O => \cr_int[3]_i_22_n_0\
);
\cr_int[3]_i_23\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_6\,
O => \cr_int[3]_i_23_n_0\
);
\cr_int[3]_i_24\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_7\,
O => \cr_int[3]_i_24_n_0\
);
\cr_int[3]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_6\,
O => \cr_int[3]_i_25_n_0\
);
\cr_int[3]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(18),
I1 => rgb888(17),
I2 => \cr_int_reg[3]_i_26_n_6\,
O => \cr_int[3]_i_28_n_0\
);
\cr_int[3]_i_29\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \cr_int_reg[3]_i_26_n_7\,
I1 => rgb888(17),
O => \cr_int[3]_i_29_n_0\
);
\cr_int[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(1),
I1 => \cr_int[3]_i_13_n_0\,
I2 => \cr_int[3]_i_14_n_0\,
O => \cr_int[3]_i_3_n_0\
);
\cr_int[3]_i_30\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_4\,
I1 => rgb888(16),
O => \cr_int[3]_i_30_n_0\
);
\cr_int[3]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_5\,
O => \cr_int[3]_i_31_n_0\
);
\cr_int[3]_i_34\: unisim.vcomponents.LUT4
generic map(
INIT => X"BE28"
)
port map (
I0 => \cr_int_reg[31]_i_101_n_7\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => \cr_int_reg[31]_i_102_n_6\,
O => \cr_int[3]_i_34_n_0\
);
\cr_int[3]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => rgb888(10),
I1 => \cr_int_reg[3]_i_64_n_4\,
I2 => \cr_int_reg[31]_i_102_n_7\,
O => \cr_int[3]_i_35_n_0\
);
\cr_int[3]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg[3]_i_64_n_5\,
I1 => rgb888(9),
I2 => \cr_int_reg[3]_i_70_n_4\,
O => \cr_int[3]_i_36_n_0\
);
\cr_int[3]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int_reg[3]_i_64_n_5\,
I1 => rgb888(9),
I2 => \cr_int_reg[3]_i_70_n_4\,
O => \cr_int[3]_i_37_n_0\
);
\cr_int[3]_i_38\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669696969969696"
)
port map (
I0 => \cr_int[3]_i_34_n_0\,
I1 => \cr_int_reg[31]_i_102_n_5\,
I2 => rgb888(12),
I3 => rgb888(11),
I4 => rgb888(10),
I5 => \cr_int_reg[31]_i_101_n_6\,
O => \cr_int[3]_i_38_n_0\
);
\cr_int[3]_i_39\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \cr_int_reg[31]_i_101_n_7\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => \cr_int_reg[31]_i_102_n_6\,
I4 => \cr_int[3]_i_35_n_0\,
O => \cr_int[3]_i_39_n_0\
);
\cr_int[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00E2E2FF"
)
port map (
I0 => cr_int_reg6(8),
I1 => cr_int_reg7,
I2 => \cr_int_reg[3]_i_16_n_5\,
I3 => \cr_int[3]_i_17_n_0\,
I4 => \cr_int[3]_i_18_n_0\,
O => \cr_int[3]_i_4_n_0\
);
\cr_int[3]_i_40\: unisim.vcomponents.LUT6
generic map(
INIT => X"E81717E817E8E817"
)
port map (
I0 => \cr_int_reg[3]_i_70_n_4\,
I1 => rgb888(9),
I2 => \cr_int_reg[3]_i_64_n_5\,
I3 => \cr_int_reg[31]_i_102_n_7\,
I4 => rgb888(10),
I5 => \cr_int_reg[3]_i_64_n_4\,
O => \cr_int[3]_i_40_n_0\
);
\cr_int[3]_i_41\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969696"
)
port map (
I0 => \cr_int_reg[3]_i_70_n_4\,
I1 => rgb888(9),
I2 => \cr_int_reg[3]_i_64_n_5\,
I3 => \cr_int_reg[3]_i_70_n_5\,
I4 => rgb888(8),
O => \cr_int[3]_i_41_n_0\
);
\cr_int[3]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[3]_0\(1),
O => \cr_int[3]_i_43_n_0\
);
\cr_int[3]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[3]_0\(0),
O => \cr_int[3]_i_44_n_0\
);
\cr_int[3]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_19_n_7\,
O => \cr_int[3]_i_45_n_0\
);
\cr_int[3]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_4\,
O => \cr_int[3]_i_46_n_0\
);
\cr_int[3]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_7\,
O => \cr_int[3]_i_47_n_0\
);
\cr_int[3]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_7\,
O => \cr_int[3]_i_48_n_0\
);
\cr_int[3]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_4\,
O => \cr_int[3]_i_49_n_0\
);
\cr_int[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(3),
I1 => \cr_int[7]_i_17_n_0\,
I2 => \cr_int[7]_i_18_n_0\,
I3 => \cr_int[3]_i_2_n_0\,
O => \cr_int[3]_i_5_n_0\
);
\cr_int[3]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_5\,
O => \cr_int[3]_i_50_n_0\
);
\cr_int[3]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_6\,
O => \cr_int[3]_i_51_n_0\
);
\cr_int[3]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(23),
O => \cr_int[3]_i_52_n_0\
);
\cr_int[3]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(22),
O => \cr_int[3]_i_53_n_0\
);
\cr_int[3]_i_55\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(21),
I1 => rgb888(23),
O => \cr_int[3]_i_55_n_0\
);
\cr_int[3]_i_56\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(20),
I1 => rgb888(22),
O => \cr_int[3]_i_56_n_0\
);
\cr_int[3]_i_57\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(19),
I1 => rgb888(21),
O => \cr_int[3]_i_57_n_0\
);
\cr_int[3]_i_58\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(18),
I1 => rgb888(20),
O => \cr_int[3]_i_58_n_0\
);
\cr_int[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(2),
I1 => \cr_int[3]_i_10_n_0\,
I2 => \cr_int[3]_i_11_n_0\,
I3 => \cr_int[3]_i_3_n_0\,
O => \cr_int[3]_i_6_n_0\
);
\cr_int[3]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_6\,
O => \cr_int[3]_i_60_n_0\
);
\cr_int[3]_i_61\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_7\,
O => \cr_int[3]_i_61_n_0\
);
\cr_int[3]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_4\,
O => \cr_int[3]_i_62_n_0\
);
\cr_int[3]_i_63\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_5\,
O => \cr_int[3]_i_63_n_0\
);
\cr_int[3]_i_66\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(8),
I1 => \cr_int_reg[3]_i_70_n_5\,
I2 => \cr_int_reg[3]_i_64_n_6\,
O => \cr_int[3]_i_66_n_0\
);
\cr_int[3]_i_67\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[3]_i_64_n_7\,
I1 => \cr_int_reg[3]_i_70_n_6\,
O => \cr_int[3]_i_67_n_0\
);
\cr_int[3]_i_68\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[3]_i_65_n_4\,
I1 => \cr_int_reg[3]_i_70_n_7\,
O => \cr_int[3]_i_68_n_0\
);
\cr_int[3]_i_69\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[3]_i_65_n_5\,
I1 => rgb888(8),
O => \cr_int[3]_i_69_n_0\
);
\cr_int[3]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(1),
I1 => \cr_int[3]_i_13_n_0\,
I2 => \cr_int[3]_i_14_n_0\,
I3 => \cr_int[3]_i_4_n_0\,
O => \cr_int[3]_i_7_n_0\
);
\cr_int[3]_i_71\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_94_n_7\,
O => \cr_int[3]_i_71_n_0\
);
\cr_int[3]_i_72\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_5\,
O => \cr_int[3]_i_72_n_0\
);
\cr_int[3]_i_73\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_6\,
O => \cr_int[3]_i_73_n_0\
);
\cr_int[3]_i_74\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(8),
I1 => \cr_int_reg[3]_i_65_n_5\,
O => \cr_int[3]_i_74_n_0\
);
\cr_int[3]_i_75\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_65_n_6\,
O => \cr_int[3]_i_75_n_0\
);
\cr_int[3]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(17),
I1 => rgb888(19),
O => \cr_int[3]_i_76_n_0\
);
\cr_int[3]_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(16),
I1 => rgb888(18),
O => \cr_int[3]_i_77_n_0\
);
\cr_int[3]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(17),
O => \cr_int[3]_i_78_n_0\
);
\cr_int[3]_i_79\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(16),
O => \cr_int[3]_i_79_n_0\
);
\cr_int[3]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"1DE2E21D"
)
port map (
I0 => cr_int_reg6(8),
I1 => cr_int_reg7,
I2 => \cr_int_reg[3]_i_16_n_5\,
I3 => \cr_int[3]_i_17_n_0\,
I4 => \cr_int[3]_i_18_n_0\,
O => \cr_int[3]_i_8_n_0\
);
\cr_int[3]_i_80\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(0),
O => \cr_int[3]_i_80_n_0\
);
\cr_int[3]_i_81\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_6\,
O => \cr_int[3]_i_81_n_0\
);
\cr_int[3]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_7\,
O => \cr_int[3]_i_82_n_0\
);
\cr_int[3]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_6\,
O => \cr_int[3]_i_83_n_0\
);
\cr_int[3]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_7\,
O => \cr_int[3]_i_84_n_0\
);
\cr_int[3]_i_85\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
O => \cr_int[3]_i_85_n_0\
);
\cr_int[3]_i_86\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(12),
I1 => rgb888(14),
O => \cr_int[3]_i_86_n_0\
);
\cr_int[3]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(11),
I1 => rgb888(13),
O => \cr_int[3]_i_87_n_0\
);
\cr_int[3]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(10),
I1 => rgb888(12),
O => \cr_int[3]_i_88_n_0\
);
\cr_int[3]_i_89\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(9),
I1 => rgb888(11),
O => \cr_int[3]_i_89_n_0\
);
\cr_int[3]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(2),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_30_n_7\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(10),
O => \cr_int_reg3__0\(2)
);
\cr_int[3]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(8),
I1 => rgb888(10),
O => \cr_int[3]_i_90_n_0\
);
\cr_int[3]_i_91\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(9),
O => \cr_int[3]_i_91_n_0\
);
\cr_int[3]_i_92\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(8),
O => \cr_int[3]_i_92_n_0\
);
\cr_int[3]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(12),
I1 => rgb888(10),
O => \cr_int[3]_i_93_n_0\
);
\cr_int[3]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(11),
I1 => rgb888(9),
O => \cr_int[3]_i_94_n_0\
);
\cr_int[3]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(10),
I1 => rgb888(8),
O => \cr_int[3]_i_95_n_0\
);
\cr_int[3]_i_96\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(9),
O => \cr_int[3]_i_96_n_0\
);
\cr_int[7]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(5),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_30_n_4\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(13),
O => \cr_int_reg3__0\(5)
);
\cr_int[7]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_13\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[7]_1\(3),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[7]_0\(2),
O => \cr_int[7]_i_11_n_0\
);
\cr_int[7]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_16_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_18_n_7\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_7_n_5\,
O => \cr_int[7]_i_12_n_0\
);
\cr_int[7]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(4),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_30_n_5\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(12),
O => \cr_int_reg3__0\(4)
);
\cr_int[7]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_12\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[7]_1\(2),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[7]_0\(1),
O => \cr_int[7]_i_14_n_0\
);
\cr_int[7]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_31_n_4\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_41_n_4\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_7_n_6\,
O => \cr_int[7]_i_15_n_0\
);
\cr_int[7]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(3),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_30_n_6\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(11),
O => \cr_int_reg3__0\(3)
);
\cr_int[7]_i_17\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_12\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[7]_1\(1),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[7]_0\(0),
O => \cr_int[7]_i_17_n_0\
);
\cr_int[7]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_31_n_5\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_41_n_5\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_7_n_7\,
O => \cr_int[7]_i_18_n_0\
);
\cr_int[7]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(7),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_11_n_6\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(15),
O => cr_int_reg3(7)
);
\cr_int[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555556A6AAAA56A6"
)
port map (
I0 => \cr_int[11]_i_22_n_0\,
I1 => cr_int_reg6(15),
I2 => cr_int_reg7,
I3 => \cr_int_reg[31]_i_11_n_6\,
I4 => \cr_int_reg[31]_i_11_n_4\,
I5 => cr_int_reg4(7),
O => \cr_int[7]_i_2_n_0\
);
\cr_int[7]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[11]_i_16_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \cr_int_reg[11]_i_18_n_6\,
O => \cr_int[7]_i_20_n_0\
);
\cr_int[7]_i_21\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_13\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[11]_0\(0),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[7]_0\(3),
O => \cr_int[7]_i_21_n_0\
);
\cr_int[7]_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(6),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_11_n_7\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(14),
O => \cr_int_reg3__0\(6)
);
\cr_int[7]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(2),
O => \cr_int[7]_i_25_n_0\
);
\cr_int[7]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(1),
O => \cr_int[7]_i_26_n_0\
);
\cr_int[7]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(0),
O => \cr_int[7]_i_27_n_0\
);
\cr_int[7]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[3]_0\(2),
O => \cr_int[7]_i_28_n_0\
);
\cr_int[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(5),
I1 => \cr_int[7]_i_11_n_0\,
I2 => \cr_int[7]_i_12_n_0\,
O => \cr_int[7]_i_3_n_0\
);
\cr_int[7]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(4),
I1 => \cr_int[7]_i_14_n_0\,
I2 => \cr_int[7]_i_15_n_0\,
O => \cr_int[7]_i_4_n_0\
);
\cr_int[7]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(3),
I1 => \cr_int[7]_i_17_n_0\,
I2 => \cr_int[7]_i_18_n_0\,
O => \cr_int[7]_i_5_n_0\
);
\cr_int[7]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"99969666"
)
port map (
I0 => cr_int_reg3(7),
I1 => \cr_int[11]_i_22_n_0\,
I2 => \cr_int[7]_i_20_n_0\,
I3 => \cr_int[7]_i_21_n_0\,
I4 => \cr_int_reg3__0\(6),
O => \cr_int[7]_i_6_n_0\
);
\cr_int[7]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int[7]_i_3_n_0\,
I1 => \cr_int[7]_i_20_n_0\,
I2 => \cr_int[7]_i_21_n_0\,
I3 => \cr_int_reg3__0\(6),
O => \cr_int[7]_i_7_n_0\
);
\cr_int[7]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(5),
I1 => \cr_int[7]_i_11_n_0\,
I2 => \cr_int[7]_i_12_n_0\,
I3 => \cr_int[7]_i_4_n_0\,
O => \cr_int[7]_i_8_n_0\
);
\cr_int[7]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(4),
I1 => \cr_int[7]_i_14_n_0\,
I2 => \cr_int[7]_i_15_n_0\,
I3 => \cr_int[7]_i_5_n_0\,
O => \cr_int[7]_i_9_n_0\
);
\cr_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[3]_i_1_n_7\,
Q => \cr_int_reg_n_0_[0]\,
R => '0'
);
\cr_int_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[11]_i_1_n_5\,
Q => \cr_int_reg__0\(10),
R => '0'
);
\cr_int_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[11]_i_1_n_4\,
Q => \cr_int_reg__0\(11),
R => '0'
);
\cr_int_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[7]_i_1_n_0\,
CO(3) => \cr_int_reg[11]_i_1_n_0\,
CO(2) => \cr_int_reg[11]_i_1_n_1\,
CO(1) => \cr_int_reg[11]_i_1_n_2\,
CO(0) => \cr_int_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[11]_i_2_n_0\,
DI(2) => \cr_int[11]_i_3_n_0\,
DI(1) => \cr_int[11]_i_4_n_0\,
DI(0) => \cr_int[11]_i_5_n_0\,
O(3) => \cr_int_reg[11]_i_1_n_4\,
O(2) => \cr_int_reg[11]_i_1_n_5\,
O(1) => \cr_int_reg[11]_i_1_n_6\,
O(0) => \cr_int_reg[11]_i_1_n_7\,
S(3) => \cr_int[11]_i_6_n_0\,
S(2) => \cr_int[11]_i_7_n_0\,
S(1) => \cr_int[11]_i_8_n_0\,
S(0) => \cr_int[11]_i_9_n_0\
);
\cr_int_reg[11]_i_103\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_125_n_0\,
CO(3) => \cr_int_reg[11]_i_103_n_0\,
CO(2) => \cr_int_reg[11]_i_103_n_1\,
CO(1) => \cr_int_reg[11]_i_103_n_2\,
CO(0) => \cr_int_reg[11]_i_103_n_3\,
CYINIT => '0',
DI(3) => \cr_int[11]_i_126_n_0\,
DI(2) => \cr_int[11]_i_127_n_0\,
DI(1) => \cr_int[11]_i_128_n_0\,
DI(0) => \cr_int[11]_i_129_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_103_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_130_n_0\,
S(2) => \cr_int[11]_i_131_n_0\,
S(1) => \cr_int[11]_i_132_n_0\,
S(0) => \cr_int[11]_i_133_n_0\
);
\cr_int_reg[11]_i_108\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_108_n_0\,
CO(2) => \cr_int_reg[11]_i_108_n_1\,
CO(1) => \cr_int_reg[11]_i_108_n_2\,
CO(0) => \cr_int_reg[11]_i_108_n_3\,
CYINIT => '1',
DI(3) => \cr_int[11]_i_134_n_0\,
DI(2) => \cr_int[11]_i_135_n_0\,
DI(1) => \cr_int[11]_i_136_n_0\,
DI(0) => \cr_int[11]_i_137_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_108_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_138_n_0\,
S(2) => \cr_int[11]_i_139_n_0\,
S(1) => \cr_int[11]_i_140_n_0\,
S(0) => \cr_int[11]_i_141_n_0\
);
\cr_int_reg[11]_i_116\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_116_n_0\,
CO(2) => \cr_int_reg[11]_i_116_n_1\,
CO(1) => \cr_int_reg[11]_i_116_n_2\,
CO(0) => \cr_int_reg[11]_i_116_n_3\,
CYINIT => '1',
DI(3) => \cr_int[11]_i_142_n_0\,
DI(2) => \cr_int[11]_i_143_n_0\,
DI(1) => \cr_int[11]_i_144_n_0\,
DI(0) => \cr_int[11]_i_145_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_116_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_146_n_0\,
S(2) => \cr_int[11]_i_147_n_0\,
S(1) => \cr_int[11]_i_148_n_0\,
S(0) => \cr_int[11]_i_149_n_0\
);
\cr_int_reg[11]_i_125\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_125_n_0\,
CO(2) => \cr_int_reg[11]_i_125_n_1\,
CO(1) => \cr_int_reg[11]_i_125_n_2\,
CO(0) => \cr_int_reg[11]_i_125_n_3\,
CYINIT => '1',
DI(3) => \cr_int[11]_i_150_n_0\,
DI(2) => \cr_int[11]_i_151_n_0\,
DI(1) => \cr_int[11]_i_152_n_0\,
DI(0) => \cb_int_reg[3]_i_94_n_7\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_125_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_153_n_0\,
S(2) => \cr_int[11]_i_154_n_0\,
S(1) => \cr_int[11]_i_155_n_0\,
S(0) => \cr_int[11]_i_156_n_0\
);
\cr_int_reg[11]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_31_n_0\,
CO(3) => \cr_int_reg[11]_i_16_n_0\,
CO(2) => \cr_int_reg[11]_i_16_n_1\,
CO(1) => \cr_int_reg[11]_i_16_n_2\,
CO(0) => \cr_int_reg[11]_i_16_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_16_n_4\,
O(2) => \cr_int_reg[11]_i_16_n_5\,
O(1) => \cr_int_reg[11]_i_16_n_6\,
O(0) => \cr_int_reg[11]_i_16_n_7\,
S(3) => \cr_int[11]_i_32_n_0\,
S(2) => \cr_int[11]_i_33_n_0\,
S(1) => \cr_int[11]_i_34_n_0\,
S(0) => \cr_int[11]_i_35_n_0\
);
\cr_int_reg[11]_i_17\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_36_n_0\,
CO(3) => \cr_int_reg[11]_i_17_n_0\,
CO(2) => \cr_int_reg[11]_i_17_n_1\,
CO(1) => \cr_int_reg[11]_i_17_n_2\,
CO(0) => \cr_int_reg[11]_i_17_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \^cr_int_reg[27]_2\(0),
DI(1) => \^cr_int_reg[27]_2\(0),
DI(0) => \^cr_int_reg[27]_2\(0),
O(3 downto 0) => \NLW_cr_int_reg[11]_i_17_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_37_n_0\,
S(2) => \cr_int[11]_i_38_n_0\,
S(1) => \cr_int[11]_i_39_n_0\,
S(0) => \cr_int[11]_i_40_n_0\
);
\cr_int_reg[11]_i_18\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_41_n_0\,
CO(3) => \cr_int_reg[15]_1\(0),
CO(2) => \cr_int_reg[11]_i_18_n_1\,
CO(1) => \cr_int_reg[11]_i_18_n_2\,
CO(0) => \cr_int_reg[11]_i_18_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_18_n_4\,
O(2) => \cr_int_reg[11]_i_18_n_5\,
O(1) => \cr_int_reg[11]_i_18_n_6\,
O(0) => \cr_int_reg[11]_i_18_n_7\,
S(3) => \cr_int[11]_i_42_n_0\,
S(2) => \cr_int[11]_i_43_n_0\,
S(1) => \cr_int[11]_i_44_n_0\,
S(0) => \cr_int[11]_i_45_n_0\
);
\cr_int_reg[11]_i_19\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_46_n_0\,
CO(3) => \cr_int_reg[11]_i_19_n_0\,
CO(2) => \cr_int_reg[11]_i_19_n_1\,
CO(1) => \cr_int_reg[11]_i_19_n_2\,
CO(0) => \cr_int_reg[11]_i_19_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(16 downto 13),
S(3) => \cr_int[11]_i_47_n_0\,
S(2) => \cr_int[11]_i_48_n_0\,
S(1) => \cr_int[11]_i_49_n_0\,
S(0) => \cr_int[11]_i_50_n_0\
);
\cr_int_reg[11]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_51_n_0\,
CO(3) => cr_int_reg7,
CO(2) => \cr_int_reg[11]_i_20_n_1\,
CO(1) => \cr_int_reg[11]_i_20_n_2\,
CO(0) => \cr_int_reg[11]_i_20_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \cr_int_reg[31]_i_11_n_4\,
DI(1) => \cr_int_reg[31]_i_11_n_4\,
DI(0) => \cr_int_reg[31]_i_11_n_4\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_20_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_52_n_0\,
S(2) => \cr_int[11]_i_53_n_0\,
S(1) => \cr_int[11]_i_54_n_0\,
S(0) => \cr_int[11]_i_55_n_0\
);
\cr_int_reg[11]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_56_n_0\,
CO(3) => \cr_int_reg[11]_i_21_n_0\,
CO(2) => \cr_int_reg[11]_i_21_n_1\,
CO(1) => \cr_int_reg[11]_i_21_n_2\,
CO(0) => \cr_int_reg[11]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(8 downto 5),
S(3) => \cr_int[11]_i_57_n_0\,
S(2) => \cr_int[11]_i_58_n_0\,
S(1) => \cr_int[11]_i_59_n_0\,
S(0) => \cr_int[11]_i_60_n_0\
);
\cr_int_reg[11]_i_29\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[7]_i_23_n_0\,
CO(3) => \cr_int_reg[11]_i_29_n_0\,
CO(2) => \cr_int_reg[11]_i_29_n_1\,
CO(1) => \cr_int_reg[11]_i_29_n_2\,
CO(0) => \cr_int_reg[11]_i_29_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[11]_0\(3 downto 0),
S(3) => \cr_int[11]_i_65_n_0\,
S(2) => \cr_int[11]_i_66_n_0\,
S(1) => \cr_int[11]_i_67_n_0\,
S(0) => \cr_int[11]_i_68_n_0\
);
\cr_int_reg[11]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_69_n_0\,
CO(3) => \^cr_int_reg[3]_1\(0),
CO(2) => \cr_int_reg[11]_i_30_n_1\,
CO(1) => \cr_int_reg[11]_i_30_n_2\,
CO(0) => \cr_int_reg[11]_i_30_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \^cr_int_reg[31]_2\(1),
DI(1) => \^cr_int_reg[31]_2\(1),
DI(0) => \^cr_int_reg[31]_2\(1),
O(3 downto 0) => \NLW_cr_int_reg[11]_i_30_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_70_n_0\,
S(2) => \cr_int[11]_i_71_n_0\,
S(1) => \cr_int[11]_i_72_n_0\,
S(0) => \cr_int[11]_i_73_n_0\
);
\cr_int_reg[11]_i_31\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_31_n_0\,
CO(2) => \cr_int_reg[11]_i_31_n_1\,
CO(1) => \cr_int_reg[11]_i_31_n_2\,
CO(0) => \cr_int_reg[11]_i_31_n_3\,
CYINIT => \cr_int[11]_i_74_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_31_n_4\,
O(2) => \cr_int_reg[11]_i_31_n_5\,
O(1) => \cr_int_reg[11]_i_31_n_6\,
O(0) => \cr_int_reg[11]_i_31_n_7\,
S(3) => \cr_int[11]_i_75_n_0\,
S(2) => \cr_int[11]_i_76_n_0\,
S(1) => \cr_int[11]_i_77_n_0\,
S(0) => \cr_int[11]_i_78_n_0\
);
\cr_int_reg[11]_i_36\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_79_n_0\,
CO(3) => \cr_int_reg[11]_i_36_n_0\,
CO(2) => \cr_int_reg[11]_i_36_n_1\,
CO(1) => \cr_int_reg[11]_i_36_n_2\,
CO(0) => \cr_int_reg[11]_i_36_n_3\,
CYINIT => '0',
DI(3) => \^cr_int_reg[27]_2\(0),
DI(2) => \^cr_int_reg[27]_2\(0),
DI(1) => \^cr_int_reg[27]_2\(0),
DI(0) => \^cr_int_reg[27]_2\(0),
O(3 downto 0) => \NLW_cr_int_reg[11]_i_36_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_80_n_0\,
S(2) => \cr_int[11]_i_81_n_0\,
S(1) => \cr_int[11]_i_82_n_0\,
S(0) => \cr_int[11]_i_83_n_0\
);
\cr_int_reg[11]_i_41\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_32_n_0\,
CO(3) => \cr_int_reg[11]_i_41_n_0\,
CO(2) => \cr_int_reg[11]_i_41_n_1\,
CO(1) => \cr_int_reg[11]_i_41_n_2\,
CO(0) => \cr_int_reg[11]_i_41_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_41_n_4\,
O(2) => \cr_int_reg[11]_i_41_n_5\,
O(1) => \cr_int_reg[11]_i_41_n_6\,
O(0) => \cr_int_reg[11]_i_41_n_7\,
S(3) => \cr_int[11]_i_84_n_0\,
S(2) => \cr_int[11]_i_85_n_0\,
S(1) => \cr_int[11]_i_86_n_0\,
S(0) => \cr_int[11]_i_87_n_0\
);
\cr_int_reg[11]_i_46\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_15_n_0\,
CO(3) => \cr_int_reg[11]_i_46_n_0\,
CO(2) => \cr_int_reg[11]_i_46_n_1\,
CO(1) => \cr_int_reg[11]_i_46_n_2\,
CO(0) => \cr_int_reg[11]_i_46_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(12 downto 9),
S(3) => \cr_int[11]_i_88_n_0\,
S(2) => \cr_int[11]_i_89_n_0\,
S(1) => \cr_int[11]_i_90_n_0\,
S(0) => \cr_int[11]_i_91_n_0\
);
\cr_int_reg[11]_i_51\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_92_n_0\,
CO(3) => \cr_int_reg[11]_i_51_n_0\,
CO(2) => \cr_int_reg[11]_i_51_n_1\,
CO(1) => \cr_int_reg[11]_i_51_n_2\,
CO(0) => \cr_int_reg[11]_i_51_n_3\,
CYINIT => '0',
DI(3) => \cr_int_reg[31]_i_11_n_4\,
DI(2) => \cr_int_reg[31]_i_11_n_4\,
DI(1) => \cr_int_reg[31]_i_11_n_4\,
DI(0) => \cr_int[11]_i_93_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_51_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_94_n_0\,
S(2) => \cr_int[11]_i_95_n_0\,
S(1) => \cr_int[11]_i_96_n_0\,
S(0) => \cr_int[11]_i_97_n_0\
);
\cr_int_reg[11]_i_56\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_56_n_0\,
CO(2) => \cr_int_reg[11]_i_56_n_1\,
CO(1) => \cr_int_reg[11]_i_56_n_2\,
CO(0) => \cr_int_reg[11]_i_56_n_3\,
CYINIT => \cr_int[11]_i_98_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(4 downto 1),
S(3) => \cr_int[11]_i_99_n_0\,
S(2) => \cr_int[11]_i_100_n_0\,
S(1) => \cr_int[11]_i_101_n_0\,
S(0) => \cr_int[11]_i_102_n_0\
);
\cr_int_reg[11]_i_69\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_103_n_0\,
CO(3) => \cr_int_reg[11]_i_69_n_0\,
CO(2) => \cr_int_reg[11]_i_69_n_1\,
CO(1) => \cr_int_reg[11]_i_69_n_2\,
CO(0) => \cr_int_reg[11]_i_69_n_3\,
CYINIT => '0',
DI(3) => \^cr_int_reg[31]_2\(1),
DI(2) => \^cr_int_reg[31]_2\(1),
DI(1) => \^cr_int_reg[31]_2\(1),
DI(0) => \^cr_int_reg[31]_2\(1),
O(3 downto 0) => \NLW_cr_int_reg[11]_i_69_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_104_n_0\,
S(2) => \cr_int[11]_i_105_n_0\,
S(1) => \cr_int[11]_i_106_n_0\,
S(0) => \cr_int[11]_i_107_n_0\
);
\cr_int_reg[11]_i_79\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_108_n_0\,
CO(3) => \cr_int_reg[11]_i_79_n_0\,
CO(2) => \cr_int_reg[11]_i_79_n_1\,
CO(1) => \cr_int_reg[11]_i_79_n_2\,
CO(0) => \cr_int_reg[11]_i_79_n_3\,
CYINIT => '0',
DI(3) => \^cr_int_reg[27]_2\(0),
DI(2) => \cr_int[11]_i_109_n_0\,
DI(1) => \cr_int[11]_i_110_n_0\,
DI(0) => \cr_int[11]_i_111_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_79_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_112_n_0\,
S(2) => \cr_int[11]_i_113_n_0\,
S(1) => \cr_int[11]_i_114_n_0\,
S(0) => \cr_int[11]_i_115_n_0\
);
\cr_int_reg[11]_i_92\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_116_n_0\,
CO(3) => \cr_int_reg[11]_i_92_n_0\,
CO(2) => \cr_int_reg[11]_i_92_n_1\,
CO(1) => \cr_int_reg[11]_i_92_n_2\,
CO(0) => \cr_int_reg[11]_i_92_n_3\,
CYINIT => '0',
DI(3) => \cr_int[11]_i_117_n_0\,
DI(2) => \cr_int[11]_i_118_n_0\,
DI(1) => \cr_int[11]_i_119_n_0\,
DI(0) => \cr_int[11]_i_120_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_92_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_121_n_0\,
S(2) => \cr_int[11]_i_122_n_0\,
S(1) => \cr_int[11]_i_123_n_0\,
S(0) => \cr_int[11]_i_124_n_0\
);
\cr_int_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[15]_i_1_n_7\,
Q => \cr_int_reg__0\(12),
R => '0'
);
\cr_int_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[15]_i_1_n_6\,
Q => \cr_int_reg__0\(13),
R => '0'
);
\cr_int_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[15]_i_1_n_5\,
Q => \cr_int_reg__0\(14),
R => '0'
);
\cr_int_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[15]_i_1_n_4\,
Q => \cr_int_reg__0\(15),
R => '0'
);
\cr_int_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_1_n_0\,
CO(3) => \cr_int_reg[15]_i_1_n_0\,
CO(2) => \cr_int_reg[15]_i_1_n_1\,
CO(1) => \cr_int_reg[15]_i_1_n_2\,
CO(0) => \cr_int_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[15]_i_2_n_0\,
DI(2) => \cr_int[15]_i_3_n_0\,
DI(1) => \cr_int[15]_i_4_n_0\,
DI(0) => \cr_int[15]_i_5_n_0\,
O(3) => \cr_int_reg[15]_i_1_n_4\,
O(2) => \cr_int_reg[15]_i_1_n_5\,
O(1) => \cr_int_reg[15]_i_1_n_6\,
O(0) => \cr_int_reg[15]_i_1_n_7\,
S(3) => \cr_int[15]_i_6_n_0\,
S(2) => \cr_int[15]_i_7_n_0\,
S(1) => \cr_int[15]_i_8_n_0\,
S(0) => \cr_int[15]_i_9_n_0\
);
\cr_int_reg[15]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_19_n_0\,
CO(3) => \cr_int_reg[15]_i_20_n_0\,
CO(2) => \cr_int_reg[15]_i_20_n_1\,
CO(1) => \cr_int_reg[15]_i_20_n_2\,
CO(0) => \cr_int_reg[15]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(20 downto 17),
S(3) => \cr_int[15]_i_29_n_0\,
S(2) => \cr_int[15]_i_30_n_0\,
S(1) => \cr_int[15]_i_31_n_0\,
S(0) => \cr_int[15]_i_32_n_0\
);
\cr_int_reg[15]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_21_n_0\,
CO(3) => \cr_int_reg[15]_i_21_n_0\,
CO(2) => \cr_int_reg[15]_i_21_n_1\,
CO(1) => \cr_int_reg[15]_i_21_n_2\,
CO(0) => \cr_int_reg[15]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(12 downto 9),
S(3) => \cr_int[15]_i_33_n_0\,
S(2) => \cr_int[15]_i_34_n_0\,
S(1) => \cr_int[15]_i_35_n_0\,
S(0) => \cr_int[15]_i_36_n_0\
);
\cr_int_reg[15]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_29_n_0\,
CO(3) => \cr_int_reg[15]_i_28_n_0\,
CO(2) => \cr_int_reg[15]_i_28_n_1\,
CO(1) => \cr_int_reg[15]_i_28_n_2\,
CO(0) => \cr_int_reg[15]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[15]_0\(3 downto 0),
S(3) => \cr_int[15]_i_40_n_0\,
S(2) => \cr_int[15]_i_41_n_0\,
S(1) => \cr_int[15]_i_42_n_0\,
S(0) => \cr_int[15]_i_43_n_0\
);
\cr_int_reg[15]_i_38\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_16_n_0\,
CO(3) => \cr_int_reg[15]_i_38_n_0\,
CO(2) => \cr_int_reg[15]_i_38_n_1\,
CO(1) => \cr_int_reg[15]_i_38_n_2\,
CO(0) => \cr_int_reg[15]_i_38_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[15]_i_38_n_4\,
O(2) => \cr_int_reg[15]_i_38_n_5\,
O(1) => \cr_int_reg[15]_i_38_n_6\,
O(0) => \cr_int_reg[15]_i_38_n_7\,
S(3) => \cr_int[15]_i_48_n_0\,
S(2) => \cr_int[15]_i_49_n_0\,
S(1) => \cr_int[15]_i_50_n_0\,
S(0) => \cr_int[15]_i_51_n_0\
);
\cr_int_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[19]_i_1_n_7\,
Q => \cr_int_reg__0\(16),
R => '0'
);
\cr_int_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[19]_i_1_n_6\,
Q => \cr_int_reg__0\(17),
R => '0'
);
\cr_int_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[19]_i_1_n_5\,
Q => \cr_int_reg__0\(18),
R => '0'
);
\cr_int_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[19]_i_1_n_4\,
Q => \cr_int_reg__0\(19),
R => '0'
);
\cr_int_reg[19]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_1_n_0\,
CO(3) => \cr_int_reg[19]_i_1_n_0\,
CO(2) => \cr_int_reg[19]_i_1_n_1\,
CO(1) => \cr_int_reg[19]_i_1_n_2\,
CO(0) => \cr_int_reg[19]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[19]_i_2_n_0\,
DI(2) => \cr_int[19]_i_3_n_0\,
DI(1) => \cr_int[19]_i_4_n_0\,
DI(0) => \cr_int[19]_i_5_n_0\,
O(3) => \cr_int_reg[19]_i_1_n_4\,
O(2) => \cr_int_reg[19]_i_1_n_5\,
O(1) => \cr_int_reg[19]_i_1_n_6\,
O(0) => \cr_int_reg[19]_i_1_n_7\,
S(3) => \cr_int[19]_i_6_n_0\,
S(2) => \cr_int[19]_i_7_n_0\,
S(1) => \cr_int[19]_i_8_n_0\,
S(0) => \cr_int[19]_i_9_n_0\
);
\cr_int_reg[19]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_20_n_0\,
CO(3) => \cr_int_reg[19]_i_20_n_0\,
CO(2) => \cr_int_reg[19]_i_20_n_1\,
CO(1) => \cr_int_reg[19]_i_20_n_2\,
CO(0) => \cr_int_reg[19]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(24 downto 21),
S(3) => \cr_int[19]_i_29_n_0\,
S(2) => \cr_int[19]_i_30_n_0\,
S(1) => \cr_int[19]_i_31_n_0\,
S(0) => \cr_int[19]_i_32_n_0\
);
\cr_int_reg[19]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_21_n_0\,
CO(3) => \cr_int_reg[19]_i_21_n_0\,
CO(2) => \cr_int_reg[19]_i_21_n_1\,
CO(1) => \cr_int_reg[19]_i_21_n_2\,
CO(0) => \cr_int_reg[19]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(16 downto 13),
S(3) => \cr_int[19]_i_33_n_0\,
S(2) => \cr_int[19]_i_34_n_0\,
S(1) => \cr_int[19]_i_35_n_0\,
S(0) => \cr_int[19]_i_36_n_0\
);
\cr_int_reg[19]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_28_n_0\,
CO(3) => \cr_int_reg[19]_i_28_n_0\,
CO(2) => \cr_int_reg[19]_i_28_n_1\,
CO(1) => \cr_int_reg[19]_i_28_n_2\,
CO(0) => \cr_int_reg[19]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[19]_0\(3 downto 0),
S(3) => \cr_int[19]_i_38_n_0\,
S(2) => \cr_int[19]_i_39_n_0\,
S(1) => \cr_int[19]_i_40_n_0\,
S(0) => \cr_int[19]_i_41_n_0\
);
\cr_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[3]_i_1_n_6\,
Q => \cr_int_reg_n_0_[1]\,
R => '0'
);
\cr_int_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[23]_i_1_n_7\,
Q => \cr_int_reg__0\(20),
R => '0'
);
\cr_int_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[23]_i_1_n_6\,
Q => \cr_int_reg__0\(21),
R => '0'
);
\cr_int_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[23]_i_1_n_5\,
Q => \cr_int_reg__0\(22),
R => '0'
);
\cr_int_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[23]_i_1_n_4\,
Q => \cr_int_reg__0\(23),
R => '0'
);
\cr_int_reg[23]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_1_n_0\,
CO(3) => \cr_int_reg[23]_i_1_n_0\,
CO(2) => \cr_int_reg[23]_i_1_n_1\,
CO(1) => \cr_int_reg[23]_i_1_n_2\,
CO(0) => \cr_int_reg[23]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[23]_i_2_n_0\,
DI(2) => \cr_int[23]_i_3_n_0\,
DI(1) => \cr_int[23]_i_4_n_0\,
DI(0) => \cr_int[23]_i_5_n_0\,
O(3) => \cr_int_reg[23]_i_1_n_4\,
O(2) => \cr_int_reg[23]_i_1_n_5\,
O(1) => \cr_int_reg[23]_i_1_n_6\,
O(0) => \cr_int_reg[23]_i_1_n_7\,
S(3) => \cr_int[23]_i_6_n_0\,
S(2) => \cr_int[23]_i_7_n_0\,
S(1) => \cr_int[23]_i_8_n_0\,
S(0) => \cr_int[23]_i_9_n_0\
);
\cr_int_reg[23]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_20_n_0\,
CO(3) => \cr_int_reg[23]_i_20_n_0\,
CO(2) => \cr_int_reg[23]_i_20_n_1\,
CO(1) => \cr_int_reg[23]_i_20_n_2\,
CO(0) => \cr_int_reg[23]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(28 downto 25),
S(3) => \cr_int[23]_i_27_n_0\,
S(2) => \cr_int[23]_i_28_n_0\,
S(1) => \cr_int[23]_i_29_n_0\,
S(0) => \cr_int[23]_i_30_n_0\
);
\cr_int_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[27]_i_1_n_7\,
Q => \cr_int_reg__0\(24),
R => '0'
);
\cr_int_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[27]_i_1_n_6\,
Q => \cr_int_reg__0\(25),
R => '0'
);
\cr_int_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[27]_i_1_n_5\,
Q => \cr_int_reg__0\(26),
R => '0'
);
\cr_int_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[27]_i_1_n_4\,
Q => \cr_int_reg__0\(27),
R => '0'
);
\cr_int_reg[27]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[23]_i_1_n_0\,
CO(3) => \cr_int_reg[27]_i_1_n_0\,
CO(2) => \cr_int_reg[27]_i_1_n_1\,
CO(1) => \cr_int_reg[27]_i_1_n_2\,
CO(0) => \cr_int_reg[27]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_2_n_0\,
DI(2) => \cr_int[31]_i_2_n_0\,
DI(1) => \cr_int[31]_i_2_n_0\,
DI(0) => \cr_int[27]_i_2_n_0\,
O(3) => \cr_int_reg[27]_i_1_n_4\,
O(2) => \cr_int_reg[27]_i_1_n_5\,
O(1) => \cr_int_reg[27]_i_1_n_6\,
O(0) => \cr_int_reg[27]_i_1_n_7\,
S(3) => \cr_int[27]_i_3_n_0\,
S(2) => \cr_int[27]_i_4_n_0\,
S(1) => \cr_int[27]_i_5_n_0\,
S(0) => \cr_int[27]_i_6_n_0\
);
\cr_int_reg[27]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[23]_i_20_n_0\,
CO(3 downto 1) => \NLW_cr_int_reg[27]_i_9_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cr_int_reg[27]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[27]_i_9_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => cr_int_reg6(30 downto 29),
S(3 downto 2) => B"00",
S(1) => \cr_int[27]_i_12_n_0\,
S(0) => \cr_int[27]_i_13_n_0\
);
\cr_int_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[31]_i_1_n_7\,
Q => \cr_int_reg__0\(28),
R => '0'
);
\cr_int_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[31]_i_1_n_6\,
Q => \cr_int_reg__0\(29),
R => '0'
);
\cr_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[3]_i_1_n_5\,
Q => \cr_int_reg_n_0_[2]\,
R => '0'
);
\cr_int_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[31]_i_1_n_5\,
Q => \cr_int_reg__0\(30),
R => '0'
);
\cr_int_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[31]_i_1_n_4\,
Q => \cr_int_reg__0\(31),
R => '0'
);
\cr_int_reg[31]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[27]_i_1_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_1_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_1_n_1\,
CO(1) => \cr_int_reg[31]_i_1_n_2\,
CO(0) => \cr_int_reg[31]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \cr_int[31]_i_2_n_0\,
DI(1) => \cr_int[31]_i_2_n_0\,
DI(0) => \cr_int[31]_i_2_n_0\,
O(3) => \cr_int_reg[31]_i_1_n_4\,
O(2) => \cr_int_reg[31]_i_1_n_5\,
O(1) => \cr_int_reg[31]_i_1_n_6\,
O(0) => \cr_int_reg[31]_i_1_n_7\,
S(3) => \cr_int[31]_i_3_n_0\,
S(2) => \cr_int[31]_i_4_n_0\,
S(1) => \cr_int[31]_i_5_n_0\,
S(0) => \cr_int[31]_i_6_n_0\
);
\cr_int_reg[31]_i_101\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_64_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_101_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_101_n_1\,
CO(1) => \NLW_cr_int_reg[31]_i_101_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[31]_i_101_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1 downto 0) => rgb888(15 downto 14),
O(3 downto 2) => \NLW_cr_int_reg[31]_i_101_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[31]_i_101_n_6\,
O(0) => \cr_int_reg[31]_i_101_n_7\,
S(3 downto 2) => B"01",
S(1) => \cr_int[31]_i_121_n_0\,
S(0) => \cr_int[31]_i_122_n_0\
);
\cr_int_reg[31]_i_102\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_70_n_0\,
CO(3) => \cr_int_reg[31]_i_102_n_0\,
CO(2) => \cr_int_reg[31]_i_102_n_1\,
CO(1) => \cr_int_reg[31]_i_102_n_2\,
CO(0) => \cr_int_reg[31]_i_102_n_3\,
CYINIT => '0',
DI(3) => rgb888(14),
DI(2 downto 0) => rgb888(15 downto 13),
O(3) => \cr_int_reg[31]_i_102_n_4\,
O(2) => \cr_int_reg[31]_i_102_n_5\,
O(1) => \cr_int_reg[31]_i_102_n_6\,
O(0) => \cr_int_reg[31]_i_102_n_7\,
S(3) => \cr_int[31]_i_123_n_0\,
S(2) => \cr_int[31]_i_124_n_0\,
S(1) => \cr_int[31]_i_125_n_0\,
S(0) => \cr_int[31]_i_126_n_0\
);
\cr_int_reg[31]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_30_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_11_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_11_n_1\,
CO(1) => \cr_int_reg[31]_i_11_n_2\,
CO(0) => \cr_int_reg[31]_i_11_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \cr_int[31]_i_31_n_0\,
O(3) => \cr_int_reg[31]_i_11_n_4\,
O(2) => \cr_int_reg[31]_i_11_n_5\,
O(1) => \cr_int_reg[31]_i_11_n_6\,
O(0) => \cr_int_reg[31]_i_11_n_7\,
S(3) => \cr_int[31]_i_32_n_0\,
S(2) => \cr_int[31]_i_33_n_0\,
S(1) => \cr_int[31]_i_34_n_0\,
S(0) => \cr_int[31]_i_35_n_0\
);
\cr_int_reg[31]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_36_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_12_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_12_n_1\,
CO(1) => \NLW_cr_int_reg[31]_i_12_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[31]_i_12_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[31]_i_12_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => cr_int_reg4(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \cr_int[31]_i_37_n_0\,
S(0) => \cr_int[31]_i_38_n_0\
);
\cr_int_reg[31]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_39_n_0\,
CO(3) => \cr_int_reg[31]_i_14_n_0\,
CO(2) => \cr_int_reg[31]_i_14_n_1\,
CO(1) => \cr_int_reg[31]_i_14_n_2\,
CO(0) => \cr_int_reg[31]_i_14_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_40_n_0\,
DI(2) => \cr_int[31]_i_41_n_0\,
DI(1) => \cr_int[31]_i_42_n_0\,
DI(0) => \cr_int[31]_i_43_n_0\,
O(3) => \cr_int_reg[31]_i_14_n_4\,
O(2) => \cr_int_reg[31]_i_14_n_5\,
O(1) => \cr_int_reg[31]_i_14_n_6\,
O(0) => \cr_int_reg[31]_i_14_n_7\,
S(3) => \cr_int[31]_i_44_n_0\,
S(2) => \cr_int[31]_i_45_n_0\,
S(1) => \cr_int[31]_i_46_n_0\,
S(0) => \cr_int[31]_i_47_n_0\
);
\cr_int_reg[31]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_49_n_0\,
CO(3) => \cr_int_reg[31]_i_21_n_0\,
CO(2) => \cr_int_reg[31]_i_21_n_1\,
CO(1) => \cr_int_reg[31]_i_21_n_2\,
CO(0) => \cr_int_reg[31]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[31]_i_21_n_4\,
O(2) => \cr_int_reg[31]_i_21_n_5\,
O(1) => \cr_int_reg[31]_i_21_n_6\,
O(0) => \cr_int_reg[31]_i_21_n_7\,
S(3) => \cr_int[31]_i_50_n_0\,
S(2) => \cr_int[31]_i_51_n_0\,
S(1) => \cr_int[31]_i_52_n_0\,
S(0) => \cr_int[31]_i_53_n_0\
);
\cr_int_reg[31]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_19_n_0\,
CO(3) => \cr_int_reg[31]_i_24_n_0\,
CO(2) => \cr_int_reg[31]_i_24_n_1\,
CO(1) => \cr_int_reg[31]_i_24_n_2\,
CO(0) => \cr_int_reg[31]_i_24_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_55_n_0\,
DI(2) => \cr_int[31]_i_56_n_0\,
DI(1) => \cr_int[31]_i_57_n_0\,
DI(0) => \cr_int[31]_i_58_n_0\,
O(3 downto 0) => \^cr_int_reg[7]_0\(3 downto 0),
S(3) => \cr_int[31]_i_59_n_0\,
S(2) => \cr_int[31]_i_60_n_0\,
S(1) => \cr_int[31]_i_61_n_0\,
S(0) => \cr_int[31]_i_62_n_0\
);
\cr_int_reg[31]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_16_n_0\,
CO(3) => \cr_int_reg[31]_i_30_n_0\,
CO(2) => \cr_int_reg[31]_i_30_n_1\,
CO(1) => \cr_int_reg[31]_i_30_n_2\,
CO(0) => \cr_int_reg[31]_i_30_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_71_n_0\,
DI(2) => \cr_int[31]_i_72_n_0\,
DI(1) => \cr_int[31]_i_73_n_0\,
DI(0) => \cr_int[31]_i_74_n_0\,
O(3) => \cr_int_reg[31]_i_30_n_4\,
O(2) => \cr_int_reg[31]_i_30_n_5\,
O(1) => \cr_int_reg[31]_i_30_n_6\,
O(0) => \cr_int_reg[31]_i_30_n_7\,
S(3) => \cr_int[31]_i_75_n_0\,
S(2) => \cr_int[31]_i_76_n_0\,
S(1) => \cr_int[31]_i_77_n_0\,
S(0) => \cr_int[31]_i_78_n_0\
);
\cr_int_reg[31]_i_36\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_21_n_0\,
CO(3) => \cr_int_reg[31]_i_36_n_0\,
CO(2) => \cr_int_reg[31]_i_36_n_1\,
CO(1) => \cr_int_reg[31]_i_36_n_2\,
CO(0) => \cr_int_reg[31]_i_36_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(20 downto 17),
S(3) => \cr_int[31]_i_81_n_0\,
S(2) => \cr_int[31]_i_82_n_0\,
S(1) => \cr_int[31]_i_83_n_0\,
S(0) => \cr_int[31]_i_84_n_0\
);
\cr_int_reg[31]_i_39\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[31]_i_39_n_0\,
CO(2) => \cr_int_reg[31]_i_39_n_1\,
CO(1) => \cr_int_reg[31]_i_39_n_2\,
CO(0) => \cr_int_reg[31]_i_39_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_85_n_0\,
DI(2) => rgb888(1),
DI(1) => \cr_int_reg[31]_i_86_n_4\,
DI(0) => '0',
O(3) => \cr_int_reg[31]_i_39_n_4\,
O(2) => \cr_int_reg[31]_i_39_n_5\,
O(1) => \cr_int_reg[31]_i_39_n_6\,
O(0) => \cr_int_reg[31]_i_39_n_7\,
S(3) => \cr_int[31]_i_87_n_0\,
S(2) => \cr_int[31]_i_88_n_0\,
S(1) => \cr_int[31]_i_89_n_0\,
S(0) => \cr_int[31]_i_90_n_0\
);
\cr_int_reg[31]_i_48\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_91_n_0\,
CO(3 downto 2) => \NLW_cr_int_reg[31]_i_48_CO_UNCONNECTED\(3 downto 2),
CO(1) => \cr_int_reg[31]_i_48_n_2\,
CO(0) => \NLW_cr_int_reg[31]_i_48_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(7),
O(3 downto 1) => \NLW_cr_int_reg[31]_i_48_O_UNCONNECTED\(3 downto 1),
O(0) => \cr_int_reg[31]_i_48_n_7\,
S(3 downto 1) => B"001",
S(0) => \cr_int[31]_i_93_n_0\
);
\cr_int_reg[31]_i_49\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_38_n_0\,
CO(3) => \cr_int_reg[31]_i_49_n_0\,
CO(2) => \cr_int_reg[31]_i_49_n_1\,
CO(1) => \cr_int_reg[31]_i_49_n_2\,
CO(0) => \cr_int_reg[31]_i_49_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[31]_i_49_n_4\,
O(2) => \cr_int_reg[31]_i_49_n_5\,
O(1) => \cr_int_reg[31]_i_49_n_6\,
O(0) => \cr_int_reg[31]_i_49_n_7\,
S(3) => \cr_int[31]_i_94_n_0\,
S(2) => \cr_int[31]_i_95_n_0\,
S(1) => \cr_int[31]_i_96_n_0\,
S(0) => \cr_int[31]_i_97_n_0\
);
\cr_int_reg[31]_i_63\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_102_n_0\,
CO(3 downto 2) => \NLW_cr_int_reg[31]_i_63_CO_UNCONNECTED\(3 downto 2),
CO(1) => \cr_int_reg[31]_i_63_n_2\,
CO(0) => \NLW_cr_int_reg[31]_i_63_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(15),
O(3 downto 1) => \NLW_cr_int_reg[31]_i_63_O_UNCONNECTED\(3 downto 1),
O(0) => \cr_int_reg[31]_i_63_n_7\,
S(3 downto 1) => B"001",
S(0) => \cr_int[31]_i_103_n_0\
);
\cr_int_reg[31]_i_69\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_70_n_0\,
CO(3 downto 0) => \NLW_cr_int_reg[31]_i_69_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_cr_int_reg[31]_i_69_O_UNCONNECTED\(3 downto 1),
O(0) => \^cr_int_reg[23]_1\(0),
S(3 downto 1) => B"000",
S(0) => \cr_int[31]_i_108_n_0\
);
\cr_int_reg[31]_i_7\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_14_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_7_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_7_n_1\,
CO(1) => \cr_int_reg[31]_i_7_n_2\,
CO(0) => \cr_int_reg[31]_i_7_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \cr_int[31]_i_15_n_0\,
DI(0) => \cr_int[31]_i_16_n_0\,
O(3) => \^cr_int_reg[27]_2\(0),
O(2) => \cr_int_reg[31]_i_7_n_5\,
O(1) => \cr_int_reg[31]_i_7_n_6\,
O(0) => \cr_int_reg[31]_i_7_n_7\,
S(3) => \cr_int[31]_i_17_n_0\,
S(2) => \cr_int[31]_i_18_n_0\,
S(1) => \cr_int[31]_i_19_n_0\,
S(0) => \cr_int[31]_i_20_n_0\
);
\cr_int_reg[31]_i_70\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_28_n_0\,
CO(3) => \cr_int_reg[31]_i_70_n_0\,
CO(2) => \cr_int_reg[31]_i_70_n_1\,
CO(1) => \cr_int_reg[31]_i_70_n_2\,
CO(0) => \cr_int_reg[31]_i_70_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[23]_0\(3 downto 0),
S(3) => \cr_int[31]_i_109_n_0\,
S(2) => \cr_int[31]_i_110_n_0\,
S(1) => \cr_int[31]_i_111_n_0\,
S(0) => \cr_int[31]_i_112_n_0\
);
\cr_int_reg[31]_i_8\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_21_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_8_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_8_n_1\,
CO(1) => \NLW_cr_int_reg[31]_i_8_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[31]_i_8_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[31]_i_8_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[31]_i_8_n_6\,
O(0) => \cr_int_reg[31]_i_8_n_7\,
S(3 downto 2) => B"01",
S(1) => \cr_int[31]_i_22_n_0\,
S(0) => \cr_int[31]_i_23_n_0\
);
\cr_int_reg[31]_i_86\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[31]_i_86_n_0\,
CO(2) => \cr_int_reg[31]_i_86_n_1\,
CO(1) => \cr_int_reg[31]_i_86_n_2\,
CO(0) => \cr_int_reg[31]_i_86_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(4 downto 2),
DI(0) => '0',
O(3) => \cr_int_reg[31]_i_86_n_4\,
O(2) => \cr_int_reg[31]_i_86_n_5\,
O(1) => \cr_int_reg[31]_i_86_n_6\,
O(0) => \cr_int_reg[31]_i_86_n_7\,
S(3) => \cr_int[31]_i_113_n_0\,
S(2) => \cr_int[31]_i_114_n_0\,
S(1) => \cr_int[31]_i_115_n_0\,
S(0) => \cr_int[31]_i_116_n_0\
);
\cr_int_reg[31]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_24_n_0\,
CO(3 downto 1) => \NLW_cr_int_reg[31]_i_9_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cr_int_reg[31]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \^di\(0),
O(3 downto 2) => \NLW_cr_int_reg[31]_i_9_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => \^cr_int_reg[31]_2\(1 downto 0),
S(3 downto 2) => B"00",
S(1) => \cr_int[31]_i_25_n_0\,
S(0) => \cr_int[31]_i_26_n_0\
);
\cr_int_reg[31]_i_91\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_86_n_0\,
CO(3) => \cr_int_reg[31]_i_91_n_0\,
CO(2) => \cr_int_reg[31]_i_91_n_1\,
CO(1) => \cr_int_reg[31]_i_91_n_2\,
CO(0) => \cr_int_reg[31]_i_91_n_3\,
CYINIT => '0',
DI(3) => rgb888(6),
DI(2 downto 0) => rgb888(7 downto 5),
O(3) => \cr_int_reg[31]_i_91_n_4\,
O(2) => \cr_int_reg[31]_i_91_n_5\,
O(1) => \cr_int_reg[31]_i_91_n_6\,
O(0) => \cr_int_reg[31]_i_91_n_7\,
S(3) => \cr_int[31]_i_117_n_0\,
S(2) => \cr_int[31]_i_118_n_0\,
S(1) => \cr_int[31]_i_119_n_0\,
S(0) => \cr_int[31]_i_120_n_0\
);
\cr_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[3]_i_1_n_4\,
Q => \cr_int_reg_n_0_[3]\,
R => '0'
);
\cr_int_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_1_n_0\,
CO(2) => \cr_int_reg[3]_i_1_n_1\,
CO(1) => \cr_int_reg[3]_i_1_n_2\,
CO(0) => \cr_int_reg[3]_i_1_n_3\,
CYINIT => '1',
DI(3) => \cr_int[3]_i_2_n_0\,
DI(2) => \cr_int[3]_i_3_n_0\,
DI(1) => \cr_int[3]_i_4_n_0\,
DI(0) => '1',
O(3) => \cr_int_reg[3]_i_1_n_4\,
O(2) => \cr_int_reg[3]_i_1_n_5\,
O(1) => \cr_int_reg[3]_i_1_n_6\,
O(0) => \cr_int_reg[3]_i_1_n_7\,
S(3) => \cr_int[3]_i_5_n_0\,
S(2) => \cr_int[3]_i_6_n_0\,
S(1) => \cr_int[3]_i_7_n_0\,
S(0) => \cr_int[3]_i_8_n_0\
);
\cr_int_reg[3]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_21_n_0\,
CO(3) => \cr_int_reg[3]_i_15_n_0\,
CO(2) => \cr_int_reg[3]_i_15_n_1\,
CO(1) => \cr_int_reg[3]_i_15_n_2\,
CO(0) => \cr_int_reg[3]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => cr_int_reg6(8),
O(2 downto 0) => \NLW_cr_int_reg[3]_i_15_O_UNCONNECTED\(2 downto 0),
S(3) => \cr_int[3]_i_22_n_0\,
S(2) => \cr_int[3]_i_23_n_0\,
S(1) => \cr_int[3]_i_24_n_0\,
S(0) => \cr_int[3]_i_25_n_0\
);
\cr_int_reg[3]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_16_n_0\,
CO(2) => \cr_int_reg[3]_i_16_n_1\,
CO(1) => \cr_int_reg[3]_i_16_n_2\,
CO(0) => \cr_int_reg[3]_i_16_n_3\,
CYINIT => '0',
DI(3) => \cr_int_reg[3]_i_26_n_6\,
DI(2) => \cr_int_reg[3]_i_26_n_7\,
DI(1) => \cr_int_reg[3]_i_27_n_4\,
DI(0) => '0',
O(3) => \cr_int_reg[3]_i_16_n_4\,
O(2) => \cr_int_reg[3]_i_16_n_5\,
O(1) => \cr_int_reg[3]_i_16_n_6\,
O(0) => \cr_int_reg[3]_i_16_n_7\,
S(3) => \cr_int[3]_i_28_n_0\,
S(2) => \cr_int[3]_i_29_n_0\,
S(1) => \cr_int[3]_i_30_n_0\,
S(0) => \cr_int[3]_i_31_n_0\
);
\cr_int_reg[3]_i_19\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_33_n_0\,
CO(3) => \cr_int_reg[3]_i_19_n_0\,
CO(2) => \cr_int_reg[3]_i_19_n_1\,
CO(1) => \cr_int_reg[3]_i_19_n_2\,
CO(0) => \cr_int_reg[3]_i_19_n_3\,
CYINIT => '0',
DI(3) => \cr_int[3]_i_34_n_0\,
DI(2) => \cr_int[3]_i_35_n_0\,
DI(1) => \cr_int[3]_i_36_n_0\,
DI(0) => \cr_int[3]_i_37_n_0\,
O(3 downto 1) => \^cr_int_reg[3]_0\(2 downto 0),
O(0) => \cr_int_reg[3]_i_19_n_7\,
S(3) => \cr_int[3]_i_38_n_0\,
S(2) => \cr_int[3]_i_39_n_0\,
S(1) => \cr_int[3]_i_40_n_0\,
S(0) => \cr_int[3]_i_41_n_0\
);
\cr_int_reg[3]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_42_n_0\,
CO(3) => \cr_int_reg[3]_i_20_n_0\,
CO(2) => \cr_int_reg[3]_i_20_n_1\,
CO(1) => \cr_int_reg[3]_i_20_n_2\,
CO(0) => \cr_int_reg[3]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \^cr_int_reg[3]_2\(1 downto 0),
O(1 downto 0) => \NLW_cr_int_reg[3]_i_20_O_UNCONNECTED\(1 downto 0),
S(3) => \cr_int[3]_i_43_n_0\,
S(2) => \cr_int[3]_i_44_n_0\,
S(1) => \cr_int[3]_i_45_n_0\,
S(0) => \cr_int[3]_i_46_n_0\
);
\cr_int_reg[3]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_21_n_0\,
CO(2) => \cr_int_reg[3]_i_21_n_1\,
CO(1) => \cr_int_reg[3]_i_21_n_2\,
CO(0) => \cr_int_reg[3]_i_21_n_3\,
CYINIT => \cr_int[3]_i_47_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cr_int_reg[3]_i_21_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[3]_i_48_n_0\,
S(2) => \cr_int[3]_i_49_n_0\,
S(1) => \cr_int[3]_i_50_n_0\,
S(0) => \cr_int[3]_i_51_n_0\
);
\cr_int_reg[3]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_27_n_0\,
CO(3) => \NLW_cr_int_reg[3]_i_26_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[3]_i_26_n_1\,
CO(1) => \NLW_cr_int_reg[3]_i_26_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[3]_i_26_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => rgb888(23),
DI(0) => '0',
O(3 downto 2) => \NLW_cr_int_reg[3]_i_26_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[3]_i_26_n_6\,
O(0) => \cr_int_reg[3]_i_26_n_7\,
S(3 downto 2) => B"01",
S(1) => \cr_int[3]_i_52_n_0\,
S(0) => \cr_int[3]_i_53_n_0\
);
\cr_int_reg[3]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_54_n_0\,
CO(3) => \cr_int_reg[3]_i_27_n_0\,
CO(2) => \cr_int_reg[3]_i_27_n_1\,
CO(1) => \cr_int_reg[3]_i_27_n_2\,
CO(0) => \cr_int_reg[3]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => rgb888(21 downto 18),
O(3) => \cr_int_reg[3]_i_27_n_4\,
O(2) => \cr_int_reg[3]_i_27_n_5\,
O(1) => \cr_int_reg[3]_i_27_n_6\,
O(0) => \cr_int_reg[3]_i_27_n_7\,
S(3) => \cr_int[3]_i_55_n_0\,
S(2) => \cr_int[3]_i_56_n_0\,
S(1) => \cr_int[3]_i_57_n_0\,
S(0) => \cr_int[3]_i_58_n_0\
);
\cr_int_reg[3]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_59_n_0\,
CO(3) => \cr_int_reg[3]_i_32_n_0\,
CO(2) => \cr_int_reg[3]_i_32_n_1\,
CO(1) => \cr_int_reg[3]_i_32_n_2\,
CO(0) => \cr_int_reg[3]_i_32_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[3]_i_32_n_4\,
O(2 downto 0) => \NLW_cr_int_reg[3]_i_32_O_UNCONNECTED\(2 downto 0),
S(3) => \cr_int[3]_i_60_n_0\,
S(2) => \cr_int[3]_i_61_n_0\,
S(1) => \cr_int[3]_i_62_n_0\,
S(0) => \cr_int[3]_i_63_n_0\
);
\cr_int_reg[3]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_33_n_0\,
CO(2) => \cr_int_reg[3]_i_33_n_1\,
CO(1) => \cr_int_reg[3]_i_33_n_2\,
CO(0) => \cr_int_reg[3]_i_33_n_3\,
CYINIT => '0',
DI(3) => \cr_int_reg[3]_i_64_n_6\,
DI(2) => \cr_int_reg[3]_i_64_n_7\,
DI(1) => \cr_int_reg[3]_i_65_n_4\,
DI(0) => \cr_int_reg[3]_i_65_n_5\,
O(3) => \cr_int_reg[3]_i_33_n_4\,
O(2) => \cr_int_reg[3]_i_33_n_5\,
O(1) => \cr_int_reg[3]_i_33_n_6\,
O(0) => \NLW_cr_int_reg[3]_i_33_O_UNCONNECTED\(0),
S(3) => \cr_int[3]_i_66_n_0\,
S(2) => \cr_int[3]_i_67_n_0\,
S(1) => \cr_int[3]_i_68_n_0\,
S(0) => \cr_int[3]_i_69_n_0\
);
\cr_int_reg[3]_i_42\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_42_n_0\,
CO(2) => \cr_int_reg[3]_i_42_n_1\,
CO(1) => \cr_int_reg[3]_i_42_n_2\,
CO(0) => \cr_int_reg[3]_i_42_n_3\,
CYINIT => \cr_int[3]_i_71_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cr_int_reg[3]_i_42_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[3]_i_72_n_0\,
S(2) => \cr_int[3]_i_73_n_0\,
S(1) => \cr_int[3]_i_74_n_0\,
S(0) => \cr_int[3]_i_75_n_0\
);
\cr_int_reg[3]_i_54\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_54_n_0\,
CO(2) => \cr_int_reg[3]_i_54_n_1\,
CO(1) => \cr_int_reg[3]_i_54_n_2\,
CO(0) => \cr_int_reg[3]_i_54_n_3\,
CYINIT => '0',
DI(3 downto 2) => rgb888(17 downto 16),
DI(1 downto 0) => B"01",
O(3) => \cr_int_reg[3]_i_54_n_4\,
O(2) => \cr_int_reg[3]_i_54_n_5\,
O(1) => \cr_int_reg[3]_i_54_n_6\,
O(0) => \cr_int_reg[3]_i_54_n_7\,
S(3) => \cr_int[3]_i_76_n_0\,
S(2) => \cr_int[3]_i_77_n_0\,
S(1) => \cr_int[3]_i_78_n_0\,
S(0) => \cr_int[3]_i_79_n_0\
);
\cr_int_reg[3]_i_59\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_59_n_0\,
CO(2) => \cr_int_reg[3]_i_59_n_1\,
CO(1) => \cr_int_reg[3]_i_59_n_2\,
CO(0) => \cr_int_reg[3]_i_59_n_3\,
CYINIT => \cr_int[3]_i_80_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cr_int_reg[3]_i_59_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[3]_i_81_n_0\,
S(2) => \cr_int[3]_i_82_n_0\,
S(1) => \cr_int[3]_i_83_n_0\,
S(0) => \cr_int[3]_i_84_n_0\
);
\cr_int_reg[3]_i_64\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_65_n_0\,
CO(3) => \cr_int_reg[3]_i_64_n_0\,
CO(2) => \cr_int_reg[3]_i_64_n_1\,
CO(1) => \cr_int_reg[3]_i_64_n_2\,
CO(0) => \cr_int_reg[3]_i_64_n_3\,
CYINIT => '0',
DI(3) => rgb888(15),
DI(2 downto 0) => rgb888(12 downto 10),
O(3) => \cr_int_reg[3]_i_64_n_4\,
O(2) => \cr_int_reg[3]_i_64_n_5\,
O(1) => \cr_int_reg[3]_i_64_n_6\,
O(0) => \cr_int_reg[3]_i_64_n_7\,
S(3) => \cr_int[3]_i_85_n_0\,
S(2) => \cr_int[3]_i_86_n_0\,
S(1) => \cr_int[3]_i_87_n_0\,
S(0) => \cr_int[3]_i_88_n_0\
);
\cr_int_reg[3]_i_65\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_65_n_0\,
CO(2) => \cr_int_reg[3]_i_65_n_1\,
CO(1) => \cr_int_reg[3]_i_65_n_2\,
CO(0) => \cr_int_reg[3]_i_65_n_3\,
CYINIT => '0',
DI(3 downto 2) => rgb888(9 downto 8),
DI(1 downto 0) => B"01",
O(3) => \cr_int_reg[3]_i_65_n_4\,
O(2) => \cr_int_reg[3]_i_65_n_5\,
O(1) => \cr_int_reg[3]_i_65_n_6\,
O(0) => \NLW_cr_int_reg[3]_i_65_O_UNCONNECTED\(0),
S(3) => \cr_int[3]_i_89_n_0\,
S(2) => \cr_int[3]_i_90_n_0\,
S(1) => \cr_int[3]_i_91_n_0\,
S(0) => \cr_int[3]_i_92_n_0\
);
\cr_int_reg[3]_i_70\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_70_n_0\,
CO(2) => \cr_int_reg[3]_i_70_n_1\,
CO(1) => \cr_int_reg[3]_i_70_n_2\,
CO(0) => \cr_int_reg[3]_i_70_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(12 downto 10),
DI(0) => '0',
O(3) => \cr_int_reg[3]_i_70_n_4\,
O(2) => \cr_int_reg[3]_i_70_n_5\,
O(1) => \cr_int_reg[3]_i_70_n_6\,
O(0) => \cr_int_reg[3]_i_70_n_7\,
S(3) => \cr_int[3]_i_93_n_0\,
S(2) => \cr_int[3]_i_94_n_0\,
S(1) => \cr_int[3]_i_95_n_0\,
S(0) => \cr_int[3]_i_96_n_0\
);
\cr_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[7]_i_1_n_7\,
Q => \cr_int_reg_n_0_[4]\,
R => '0'
);
\cr_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[7]_i_1_n_6\,
Q => \cr_int_reg_n_0_[5]\,
R => '0'
);
\cr_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[7]_i_1_n_5\,
Q => \cr_int_reg_n_0_[6]\,
R => '0'
);
\cr_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[7]_i_1_n_4\,
Q => \cr_int_reg_n_0_[7]\,
R => '0'
);
\cr_int_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_1_n_0\,
CO(3) => \cr_int_reg[7]_i_1_n_0\,
CO(2) => \cr_int_reg[7]_i_1_n_1\,
CO(1) => \cr_int_reg[7]_i_1_n_2\,
CO(0) => \cr_int_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[7]_i_2_n_0\,
DI(2) => \cr_int[7]_i_3_n_0\,
DI(1) => \cr_int[7]_i_4_n_0\,
DI(0) => \cr_int[7]_i_5_n_0\,
O(3) => \cr_int_reg[7]_i_1_n_4\,
O(2) => \cr_int_reg[7]_i_1_n_5\,
O(1) => \cr_int_reg[7]_i_1_n_6\,
O(0) => \cr_int_reg[7]_i_1_n_7\,
S(3) => \cr_int[7]_i_6_n_0\,
S(2) => \cr_int[7]_i_7_n_0\,
S(1) => \cr_int[7]_i_8_n_0\,
S(0) => \cr_int[7]_i_9_n_0\
);
\cr_int_reg[7]_i_23\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_20_n_0\,
CO(3) => \cr_int_reg[7]_i_23_n_0\,
CO(2) => \cr_int_reg[7]_i_23_n_1\,
CO(1) => \cr_int_reg[7]_i_23_n_2\,
CO(0) => \cr_int_reg[7]_i_23_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[7]_1\(3 downto 0),
S(3) => \cr_int[7]_i_25_n_0\,
S(2) => \cr_int[7]_i_26_n_0\,
S(1) => \cr_int[7]_i_27_n_0\,
S(0) => \cr_int[7]_i_28_n_0\
);
\cr_int_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[11]_i_1_n_7\,
Q => \cr_int_reg__0\(8),
R => '0'
);
\cr_int_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[11]_i_1_n_6\,
Q => \cr_int_reg__0\(9),
R => '0'
);
\cr_reg[0]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[0]_i_1_n_0\,
Q => cr(0),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[1]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[1]_i_1_n_0\,
Q => cr(1),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[2]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[2]_i_1_n_0\,
Q => cr(2),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[3]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[3]_i_1_n_0\,
Q => cr(3),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[4]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[4]_i_1_n_0\,
Q => cr(4),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[5]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[5]_i_1_n_0\,
Q => cr(5),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[6]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[6]_i_1_n_0\,
Q => cr(6),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[7]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[7]_i_2_n_0\,
Q => cr(7),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_reg[7]_i_3_n_0\,
CO(3) => \cr_reg[7]_i_1_n_0\,
CO(2) => \cr_reg[7]_i_1_n_1\,
CO(1) => \cr_reg[7]_i_1_n_2\,
CO(0) => \cr_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr[7]_i_4_n_0\,
DI(2) => \cr[7]_i_5_n_0\,
DI(1) => \cr[7]_i_6_n_0\,
DI(0) => \cr[7]_i_7_n_0\,
O(3 downto 0) => \NLW_cr_reg[7]_i_1_O_UNCONNECTED\(3 downto 0),
S(3) => \cr[7]_i_8_n_0\,
S(2) => \cr[7]_i_9_n_0\,
S(1) => \cr[7]_i_10_n_0\,
S(0) => \cr[7]_i_11_n_0\
);
\cr_reg[7]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_reg[7]_i_12_n_0\,
CO(2) => \cr_reg[7]_i_12_n_1\,
CO(1) => \cr_reg[7]_i_12_n_2\,
CO(0) => \cr_reg[7]_i_12_n_3\,
CYINIT => '0',
DI(3) => \cr[7]_i_21_n_0\,
DI(2) => \cr[7]_i_22_n_0\,
DI(1) => \cr[7]_i_23_n_0\,
DI(0) => \cr[7]_i_24_n_0\,
O(3 downto 0) => \NLW_cr_reg[7]_i_12_O_UNCONNECTED\(3 downto 0),
S(3) => \cr[7]_i_25_n_0\,
S(2) => \cr[7]_i_26_n_0\,
S(1) => \cr[7]_i_27_n_0\,
S(0) => \cr[7]_i_28_n_0\
);
\cr_reg[7]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \cr_reg[7]_i_12_n_0\,
CO(3) => \cr_reg[7]_i_3_n_0\,
CO(2) => \cr_reg[7]_i_3_n_1\,
CO(1) => \cr_reg[7]_i_3_n_2\,
CO(0) => \cr_reg[7]_i_3_n_3\,
CYINIT => '0',
DI(3) => \cr[7]_i_13_n_0\,
DI(2) => \cr[7]_i_14_n_0\,
DI(1) => \cr[7]_i_15_n_0\,
DI(0) => \cr[7]_i_16_n_0\,
O(3 downto 0) => \NLW_cr_reg[7]_i_3_O_UNCONNECTED\(3 downto 0),
S(3) => \cr[7]_i_17_n_0\,
S(2) => \cr[7]_i_18_n_0\,
S(1) => \cr[7]_i_19_n_0\,
S(0) => \cr[7]_i_20_n_0\
);
edge_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => edge,
O => edge_i_1_n_0
);
edge_rb_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => edge,
I1 => edge_rb,
O => edge_rb_i_1_n_0
);
edge_rb_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x2,
CE => '1',
D => edge_rb_i_1_n_0,
Q => edge_rb,
R => \hdmi_d[15]_i_1_n_0\
);
edge_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x2,
CE => '1',
D => edge_i_1_n_0,
Q => edge,
R => '0'
);
\hdmi_clk_bits_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => edge_i_1_n_0,
Q => D1,
R => '0'
);
\hdmi_d[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(2),
I1 => \cr_hold_reg_n_0_[2]\,
I2 => y_hold(2),
I3 => edge_rb,
I4 => y(2),
I5 => edge,
O => \hdmi_d[10]_i_1_n_0\
);
\hdmi_d[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(3),
I1 => \cr_hold_reg_n_0_[3]\,
I2 => y_hold(3),
I3 => edge_rb,
I4 => y(3),
I5 => edge,
O => \hdmi_d[11]_i_1_n_0\
);
\hdmi_d[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(4),
I1 => \cr_hold_reg_n_0_[4]\,
I2 => y_hold(4),
I3 => edge_rb,
I4 => y(4),
I5 => edge,
O => \hdmi_d[12]_i_1_n_0\
);
\hdmi_d[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(5),
I1 => \cr_hold_reg_n_0_[5]\,
I2 => y_hold(5),
I3 => edge_rb,
I4 => y(5),
I5 => edge,
O => \hdmi_d[13]_i_1_n_0\
);
\hdmi_d[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(6),
I1 => \cr_hold_reg_n_0_[6]\,
I2 => y_hold(6),
I3 => edge_rb,
I4 => y(6),
I5 => edge,
O => \hdmi_d[14]_i_1_n_0\
);
\hdmi_d[15]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active,
O => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(7),
I1 => \cr_hold_reg_n_0_[7]\,
I2 => y_hold(7),
I3 => edge_rb,
I4 => y(7),
I5 => edge,
O => \hdmi_d[15]_i_2_n_0\
);
\hdmi_d[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(0),
I1 => \cr_hold_reg_n_0_[0]\,
I2 => y_hold(0),
I3 => edge_rb,
I4 => y(0),
I5 => edge,
O => \hdmi_d[8]_i_1_n_0\
);
\hdmi_d[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(1),
I1 => \cr_hold_reg_n_0_[1]\,
I2 => y_hold(1),
I3 => edge_rb,
I4 => y(1),
I5 => edge,
O => \hdmi_d[9]_i_1_n_0\
);
\hdmi_d_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[10]_i_1_n_0\,
Q => hdmi_d(2),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[11]_i_1_n_0\,
Q => hdmi_d(3),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[12]_i_1_n_0\,
Q => hdmi_d(4),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[13]_i_1_n_0\,
Q => hdmi_d(5),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[14]_i_1_n_0\,
Q => hdmi_d(6),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[15]_i_2_n_0\,
Q => hdmi_d(7),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[8]_i_1_n_0\,
Q => hdmi_d(0),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[9]_i_1_n_0\,
Q => hdmi_d(1),
R => \hdmi_d[15]_i_1_n_0\
);
hdmi_de_reg: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => active,
Q => hdmi_de,
R => '0'
);
hdmi_hsync_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => hsync,
O => p_0_in
);
hdmi_hsync_reg: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => p_0_in,
Q => hdmi_hsync,
R => '0'
);
hdmi_vsync_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => vsync,
O => hdmi_vsync_i_1_n_0
);
hdmi_vsync_reg: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => hdmi_vsync_i_1_n_0,
Q => hdmi_vsync,
R => '0'
);
\y[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[0]\,
I1 => \y_int_reg__0\(31),
O => \y[0]_i_1_n_0\
);
\y[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[1]\,
I1 => \y_int_reg__0\(31),
O => \y[1]_i_1_n_0\
);
\y[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[2]\,
I1 => \y_int_reg__0\(31),
O => \y[2]_i_1_n_0\
);
\y[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[3]\,
I1 => \y_int_reg__0\(31),
O => \y[3]_i_1_n_0\
);
\y[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[4]\,
I1 => \y_int_reg__0\(31),
O => \y[4]_i_1_n_0\
);
\y[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[5]\,
I1 => \y_int_reg__0\(31),
O => \y[5]_i_1_n_0\
);
\y[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[6]\,
I1 => \y_int_reg__0\(31),
O => \y[6]_i_1_n_0\
);
\y[7]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(26),
I1 => \y_int_reg__0\(27),
O => \y[7]_i_10_n_0\
);
\y[7]_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(24),
I1 => \y_int_reg__0\(25),
O => \y[7]_i_11_n_0\
);
\y[7]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(22),
I1 => \y_int_reg__0\(23),
O => \y[7]_i_13_n_0\
);
\y[7]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(20),
I1 => \y_int_reg__0\(21),
O => \y[7]_i_14_n_0\
);
\y[7]_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(18),
I1 => \y_int_reg__0\(19),
O => \y[7]_i_15_n_0\
);
\y[7]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(16),
I1 => \y_int_reg__0\(17),
O => \y[7]_i_16_n_0\
);
\y[7]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(22),
I1 => \y_int_reg__0\(23),
O => \y[7]_i_17_n_0\
);
\y[7]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(20),
I1 => \y_int_reg__0\(21),
O => \y[7]_i_18_n_0\
);
\y[7]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(18),
I1 => \y_int_reg__0\(19),
O => \y[7]_i_19_n_0\
);
\y[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[7]\,
I1 => \y_int_reg__0\(31),
O => \y[7]_i_2_n_0\
);
\y[7]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(16),
I1 => \y_int_reg__0\(17),
O => \y[7]_i_20_n_0\
);
\y[7]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(14),
I1 => \y_int_reg__0\(15),
O => \y[7]_i_21_n_0\
);
\y[7]_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(12),
I1 => \y_int_reg__0\(13),
O => \y[7]_i_22_n_0\
);
\y[7]_i_23\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(10),
I1 => \y_int_reg__0\(11),
O => \y[7]_i_23_n_0\
);
\y[7]_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(8),
I1 => \y_int_reg__0\(9),
O => \y[7]_i_24_n_0\
);
\y[7]_i_25\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(14),
I1 => \y_int_reg__0\(15),
O => \y[7]_i_25_n_0\
);
\y[7]_i_26\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(12),
I1 => \y_int_reg__0\(13),
O => \y[7]_i_26_n_0\
);
\y[7]_i_27\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(10),
I1 => \y_int_reg__0\(11),
O => \y[7]_i_27_n_0\
);
\y[7]_i_28\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(8),
I1 => \y_int_reg__0\(9),
O => \y[7]_i_28_n_0\
);
\y[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg__0\(30),
I1 => \y_int_reg__0\(31),
O => \y[7]_i_4_n_0\
);
\y[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(28),
I1 => \y_int_reg__0\(29),
O => \y[7]_i_5_n_0\
);
\y[7]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(26),
I1 => \y_int_reg__0\(27),
O => \y[7]_i_6_n_0\
);
\y[7]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(24),
I1 => \y_int_reg__0\(25),
O => \y[7]_i_7_n_0\
);
\y[7]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(30),
I1 => \y_int_reg__0\(31),
O => \y[7]_i_8_n_0\
);
\y[7]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(28),
I1 => \y_int_reg__0\(29),
O => \y[7]_i_9_n_0\
);
\y_hold[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(0),
I1 => y(0),
I2 => edge_rb,
O => p_1_in(0)
);
\y_hold[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(1),
I1 => y(1),
I2 => edge_rb,
O => p_1_in(1)
);
\y_hold[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(2),
I1 => y(2),
I2 => edge_rb,
O => p_1_in(2)
);
\y_hold[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(3),
I1 => y(3),
I2 => edge_rb,
O => p_1_in(3)
);
\y_hold[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(4),
I1 => y(4),
I2 => edge_rb,
O => p_1_in(4)
);
\y_hold[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(5),
I1 => y(5),
I2 => edge_rb,
O => p_1_in(5)
);
\y_hold[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(6),
I1 => y(6),
I2 => edge_rb,
O => p_1_in(6)
);
\y_hold[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(7),
I1 => y(7),
I2 => edge_rb,
O => p_1_in(7)
);
\y_hold_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(0),
Q => y_hold(0),
R => '0'
);
\y_hold_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(1),
Q => y_hold(1),
R => '0'
);
\y_hold_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(2),
Q => y_hold(2),
R => '0'
);
\y_hold_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(3),
Q => y_hold(3),
R => '0'
);
\y_hold_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(4),
Q => y_hold(4),
R => '0'
);
\y_hold_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(5),
Q => y_hold(5),
R => '0'
);
\y_hold_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(6),
Q => y_hold(6),
R => '0'
);
\y_hold_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(7),
Q => y_hold(7),
R => '0'
);
\y_int[11]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \y_int_reg[15]_i_33_n_6\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_29\(0),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[11]_i_10_n_0\
);
\y_int[11]_i_100\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
I1 => rgb888(0),
O => \y_int[11]_i_100_n_0\
);
\y_int[11]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(1),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[15]_0\(1),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(10)
);
\y_int[11]_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \y_int_reg[15]_i_33_n_7\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_22\(3),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[11]_i_12_n_0\
);
\y_int[11]_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(0),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[15]_0\(0),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(9)
);
\y_int[11]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[11]_i_38_n_4\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_21\(1),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[8]_22\(2),
O => \y_int[11]_i_16_n_0\
);
\y_int[11]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg2(8),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[11]_i_21_n_4\,
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(8)
);
\y_int[11]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(7),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_8_n_6\,
I3 => y_int_reg6,
I4 => y_int_reg5(15),
O => y_int_reg20_in(7)
);
\y_int[11]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[11]_i_38_n_5\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_21\(0),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[8]_22\(1),
O => \y_int[11]_i_19_n_0\
);
\y_int[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(18),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(10),
I4 => \y_int[11]_i_10_n_0\,
I5 => y_int_reg1(10),
O => \y_int[11]_i_2_n_0\
);
\y_int[11]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(11),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(19),
I3 => y_int_reg6,
O => y_int_reg20_in(11)
);
\y_int[11]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(10),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(18),
I3 => y_int_reg6,
O => y_int_reg20_in(10)
);
\y_int[11]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(9),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(17),
I3 => y_int_reg6,
O => y_int_reg20_in(9)
);
\y_int[11]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(8),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(16),
I3 => y_int_reg6,
O => y_int_reg20_in(8)
);
\y_int[11]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[11]_i_29_n_0\
);
\y_int[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(17),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(9),
I4 => \y_int[11]_i_12_n_0\,
I5 => y_int_reg1(9),
O => \y_int[11]_i_3_n_0\
);
\y_int[11]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_6\,
O => \y_int[11]_i_30_n_0\
);
\y_int[11]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_7\,
O => \y_int[11]_i_31_n_0\
);
\y_int[11]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_4\,
O => \y_int[11]_i_32_n_0\
);
\y_int[11]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(16),
O => \y_int[11]_i_34_n_0\
);
\y_int[11]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(15),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_8_n_6\,
O => \y_int[11]_i_35_n_0\
);
\y_int[11]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(14),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_8_n_7\,
O => \y_int[11]_i_36_n_0\
);
\y_int[11]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(13),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_16_n_4\,
O => \y_int[11]_i_37_n_0\
);
\y_int[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(16),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(8),
I4 => \y_int[11]_i_16_n_0\,
I5 => y_int_reg1(8),
O => \y_int[11]_i_4_n_0\
);
\y_int[11]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[11]_i_21_n_4\,
O => \y_int[11]_i_40_n_0\
);
\y_int[11]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[11]_i_21_n_5\,
O => \y_int[11]_i_41_n_0\
);
\y_int[11]_i_42\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[11]_i_21_n_6\,
O => \y_int[11]_i_42_n_0\
);
\y_int[11]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_21_n_7\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_11_n_5\,
O => \y_int[11]_i_43_n_0\
);
\y_int[11]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_45_n_0\
);
\y_int[11]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_46_n_0\
);
\y_int[11]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_47_n_0\
);
\y_int[11]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_5\,
O => \y_int[11]_i_48_n_0\
);
\y_int[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"E888E888E8EEE888"
)
port map (
I0 => y_int_reg20_in(7),
I1 => \y_int[11]_i_19_n_0\,
I2 => y_int_reg2(7),
I3 => \^y_int_reg[23]_0\(0),
I4 => \y_int_reg[11]_i_21_n_5\,
I5 => \^y_int_reg[7]_0\(0),
O => \y_int[11]_i_5_n_0\
);
\y_int[11]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_50_n_0\
);
\y_int[11]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_51_n_0\
);
\y_int[11]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_52_n_0\
);
\y_int[11]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_53_n_0\
);
\y_int[11]_i_58\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_5\,
O => \y_int[11]_i_58_n_0\
);
\y_int[11]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_6\,
O => \y_int[11]_i_59_n_0\
);
\y_int[11]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[11]_i_2_n_0\,
I1 => y_int_reg1(11),
I2 => \y_int[15]_i_18_n_0\,
I3 => y_int_reg20_in(11),
O => \y_int[11]_i_6_n_0\
);
\y_int[11]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_7\,
O => \y_int[11]_i_60_n_0\
);
\y_int[11]_i_61\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_4\,
O => \y_int[11]_i_61_n_0\
);
\y_int[11]_i_62\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(8),
I1 => y_int_reg6,
I2 => \y_int_reg[3]_i_16_n_5\,
O => \y_int[11]_i_62_n_0\
);
\y_int[11]_i_63\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(12),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_16_n_5\,
O => \y_int[11]_i_63_n_0\
);
\y_int[11]_i_64\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(11),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_16_n_6\,
O => \y_int[11]_i_64_n_0\
);
\y_int[11]_i_65\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(10),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_16_n_7\,
O => \y_int[11]_i_65_n_0\
);
\y_int[11]_i_66\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(9),
I1 => y_int_reg6,
I2 => \y_int_reg[3]_i_16_n_4\,
O => \y_int[11]_i_66_n_0\
);
\y_int[11]_i_67\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[8]_22\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_21\(1),
O => \y_int[11]_i_67_n_0\
);
\y_int[11]_i_68\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[8]_22\(1),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_21\(0),
O => \y_int[11]_i_68_n_0\
);
\y_int[11]_i_69\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[8]_22\(0),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_20\(3),
O => \y_int[11]_i_69_n_0\
);
\y_int[11]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[11]_i_3_n_0\,
I1 => y_int_reg1(10),
I2 => \y_int[11]_i_10_n_0\,
I3 => y_int_reg20_in(10),
O => \y_int[11]_i_7_n_0\
);
\y_int[11]_i_70\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_1\(3),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_20\(2),
O => \y_int[11]_i_70_n_0\
);
\y_int[11]_i_71\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[3]_i_35_n_4\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_30_n_6\,
O => \y_int[11]_i_71_n_0\
);
\y_int[11]_i_72\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_44_n_4\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_11_n_6\,
O => \y_int[11]_i_72_n_0\
);
\y_int[11]_i_73\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_44_n_5\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_11_n_7\,
O => \y_int[11]_i_73_n_0\
);
\y_int[11]_i_74\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_44_n_6\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_30_n_4\,
O => \y_int[11]_i_74_n_0\
);
\y_int[11]_i_75\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_44_n_7\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_30_n_5\,
O => \y_int[11]_i_75_n_0\
);
\y_int[11]_i_76\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_6\,
O => \y_int[11]_i_76_n_0\
);
\y_int[11]_i_77\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_7\,
O => \y_int[11]_i_77_n_0\
);
\y_int[11]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_4\,
O => \y_int[11]_i_78_n_0\
);
\y_int[11]_i_79\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_5\,
O => \y_int[11]_i_79_n_0\
);
\y_int[11]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[11]_i_4_n_0\,
I1 => y_int_reg1(9),
I2 => \y_int[11]_i_12_n_0\,
I3 => y_int_reg20_in(9),
O => \y_int[11]_i_8_n_0\
);
\y_int[11]_i_81\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_81_n_0\
);
\y_int[11]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_82_n_0\
);
\y_int[11]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_83_n_0\
);
\y_int[11]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_84_n_0\
);
\y_int[11]_i_86\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_11_n_6\,
I1 => \y_int_reg[31]_i_11_n_5\,
O => \y_int[11]_i_86_n_0\
);
\y_int[11]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_30_n_4\,
I1 => \y_int_reg[31]_i_11_n_7\,
O => \y_int[11]_i_87_n_0\
);
\y_int[11]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_30_n_6\,
I1 => \y_int_reg[31]_i_30_n_5\,
O => \y_int[11]_i_88_n_0\
);
\y_int[11]_i_89\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_89_n_0\
);
\y_int[11]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[11]_i_5_n_0\,
I1 => y_int_reg1(8),
I2 => \y_int[11]_i_16_n_0\,
I3 => y_int_reg20_in(8),
O => \y_int[11]_i_9_n_0\
);
\y_int[11]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_5\,
I1 => \y_int_reg[31]_i_11_n_6\,
O => \y_int[11]_i_90_n_0\
);
\y_int[11]_i_91\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_7\,
I1 => \y_int_reg[31]_i_30_n_4\,
O => \y_int[11]_i_91_n_0\
);
\y_int[11]_i_92\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_5\,
I1 => \y_int_reg[31]_i_30_n_6\,
O => \y_int[11]_i_92_n_0\
);
\y_int[11]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_62_n_4\,
I1 => \y_int_reg[31]_i_30_n_7\,
O => \y_int[11]_i_93_n_0\
);
\y_int[11]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_62_n_6\,
I1 => \y_int_reg[31]_i_62_n_5\,
O => \y_int[11]_i_94_n_0\
);
\y_int[11]_i_95\: unisim.vcomponents.LUT3
generic map(
INIT => X"BE"
)
port map (
I0 => \y_int_reg[31]_i_88_n_6\,
I1 => \y_int_reg[31]_i_88_n_5\,
I2 => rgb888(0),
O => \y_int[11]_i_95_n_0\
);
\y_int[11]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb888(0),
I1 => rgb888(1),
O => \y_int[11]_i_96_n_0\
);
\y_int[11]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_7\,
I1 => \y_int_reg[31]_i_62_n_4\,
O => \y_int[11]_i_97_n_0\
);
\y_int[11]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_62_n_5\,
I1 => \y_int_reg[31]_i_62_n_6\,
O => \y_int[11]_i_98_n_0\
);
\y_int[11]_i_99\: unisim.vcomponents.LUT3
generic map(
INIT => X"09"
)
port map (
I0 => rgb888(0),
I1 => \y_int_reg[31]_i_88_n_5\,
I2 => \y_int_reg[31]_i_88_n_6\,
O => \y_int[11]_i_99_n_0\
);
\y_int[15]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_28\(1),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_27\(0),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[15]_i_10_n_0\
);
\y_int[15]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(5),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[19]_0\(1),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(14)
);
\y_int[15]_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_28\(0),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_29\(3),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[15]_i_12_n_0\
);
\y_int[15]_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(4),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[19]_0\(0),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(13)
);
\y_int[15]_i_16\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \y_int_reg[15]_i_33_n_4\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_29\(2),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[15]_i_16_n_0\
);
\y_int[15]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(3),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[15]_0\(3),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(12)
);
\y_int[15]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \y_int_reg[15]_i_33_n_5\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_29\(1),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[15]_i_18_n_0\
);
\y_int[15]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(2),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[15]_0\(2),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(11)
);
\y_int[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(22),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(14),
I4 => \y_int[15]_i_10_n_0\,
I5 => y_int_reg1(14),
O => \y_int[15]_i_2_n_0\
);
\y_int[15]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(15),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(23),
I3 => y_int_reg6,
O => y_int_reg20_in(15)
);
\y_int[15]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(14),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(22),
I3 => y_int_reg6,
O => y_int_reg20_in(14)
);
\y_int[15]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(13),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(21),
I3 => y_int_reg6,
O => y_int_reg20_in(13)
);
\y_int[15]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(12),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(20),
I3 => y_int_reg6,
O => y_int_reg20_in(12)
);
\y_int[15]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[15]_i_25_n_0\
);
\y_int[15]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[15]_i_26_n_0\
);
\y_int[15]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[15]_i_27_n_0\
);
\y_int[15]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[15]_i_28_n_0\
);
\y_int[15]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(20),
O => \y_int[15]_i_29_n_0\
);
\y_int[15]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(21),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(13),
I4 => \y_int[15]_i_12_n_0\,
I5 => y_int_reg1(13),
O => \y_int[15]_i_3_n_0\
);
\y_int[15]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(19),
O => \y_int[15]_i_30_n_0\
);
\y_int[15]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(18),
O => \y_int[15]_i_31_n_0\
);
\y_int[15]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(17),
O => \y_int[15]_i_32_n_0\
);
\y_int[15]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(20),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(12),
I4 => \y_int[15]_i_16_n_0\,
I5 => y_int_reg1(12),
O => \y_int[15]_i_4_n_0\
);
\y_int[15]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_29\(2),
O => \y_int[15]_i_40_n_0\
);
\y_int[15]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_29\(1),
O => \y_int[15]_i_41_n_0\
);
\y_int[15]_i_42\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_29\(0),
O => \y_int[15]_i_42_n_0\
);
\y_int[15]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_22\(3),
O => \y_int[15]_i_43_n_0\
);
\y_int[15]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[15]_i_48_n_0\
);
\y_int[15]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[15]_i_49_n_0\
);
\y_int[15]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(19),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(11),
I4 => \y_int[15]_i_18_n_0\,
I5 => y_int_reg1(11),
O => \y_int[15]_i_5_n_0\
);
\y_int[15]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[15]_i_50_n_0\
);
\y_int[15]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[15]_i_51_n_0\
);
\y_int[15]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[15]_i_2_n_0\,
I1 => y_int_reg1(15),
I2 => \y_int[19]_i_18_n_0\,
I3 => y_int_reg20_in(15),
O => \y_int[15]_i_6_n_0\
);
\y_int[15]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[15]_i_3_n_0\,
I1 => y_int_reg1(14),
I2 => \y_int[15]_i_10_n_0\,
I3 => y_int_reg20_in(14),
O => \y_int[15]_i_7_n_0\
);
\y_int[15]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[15]_i_4_n_0\,
I1 => y_int_reg1(13),
I2 => \y_int[15]_i_12_n_0\,
I3 => y_int_reg20_in(13),
O => \y_int[15]_i_8_n_0\
);
\y_int[15]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[15]_i_5_n_0\,
I1 => y_int_reg1(12),
I2 => \y_int[15]_i_16_n_0\,
I3 => y_int_reg20_in(12),
O => \y_int[15]_i_9_n_0\
);
\y_int[19]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_26\(1),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_25\(0),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[19]_i_10_n_0\
);
\y_int[19]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(9),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_2\(1),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(18)
);
\y_int[19]_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_26\(0),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_27\(3),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[19]_i_12_n_0\
);
\y_int[19]_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(8),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_2\(0),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(17)
);
\y_int[19]_i_16\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_28\(3),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_27\(2),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[19]_i_16_n_0\
);
\y_int[19]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(7),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[19]_0\(3),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(16)
);
\y_int[19]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_28\(2),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_27\(1),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[19]_i_18_n_0\
);
\y_int[19]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(6),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[19]_0\(2),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(15)
);
\y_int[19]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(26),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(18),
I4 => \y_int[19]_i_10_n_0\,
I5 => y_int_reg1(18),
O => \y_int[19]_i_2_n_0\
);
\y_int[19]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(19),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(27),
I3 => y_int_reg6,
O => y_int_reg20_in(19)
);
\y_int[19]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(18),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(26),
I3 => y_int_reg6,
O => y_int_reg20_in(18)
);
\y_int[19]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(17),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(25),
I3 => y_int_reg6,
O => y_int_reg20_in(17)
);
\y_int[19]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(16),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(24),
I3 => y_int_reg6,
O => y_int_reg20_in(16)
);
\y_int[19]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[19]_i_25_n_0\
);
\y_int[19]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[19]_i_26_n_0\
);
\y_int[19]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[19]_i_27_n_0\
);
\y_int[19]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[19]_i_28_n_0\
);
\y_int[19]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(24),
O => \y_int[19]_i_29_n_0\
);
\y_int[19]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(25),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(17),
I4 => \y_int[19]_i_12_n_0\,
I5 => y_int_reg1(17),
O => \y_int[19]_i_3_n_0\
);
\y_int[19]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(23),
O => \y_int[19]_i_30_n_0\
);
\y_int[19]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(22),
O => \y_int[19]_i_31_n_0\
);
\y_int[19]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(21),
O => \y_int[19]_i_32_n_0\
);
\y_int[19]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(24),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(16),
I4 => \y_int[19]_i_16_n_0\,
I5 => y_int_reg1(16),
O => \y_int[19]_i_4_n_0\
);
\y_int[19]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[19]_i_48_n_0\
);
\y_int[19]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[19]_i_49_n_0\
);
\y_int[19]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(23),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(15),
I4 => \y_int[19]_i_18_n_0\,
I5 => y_int_reg1(15),
O => \y_int[19]_i_5_n_0\
);
\y_int[19]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[19]_i_50_n_0\
);
\y_int[19]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[19]_i_51_n_0\
);
\y_int[19]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[19]_i_2_n_0\,
I1 => y_int_reg1(19),
I2 => \y_int[23]_i_20_n_0\,
I3 => y_int_reg20_in(19),
O => \y_int[19]_i_6_n_0\
);
\y_int[19]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[19]_i_3_n_0\,
I1 => y_int_reg1(18),
I2 => \y_int[19]_i_10_n_0\,
I3 => y_int_reg20_in(18),
O => \y_int[19]_i_7_n_0\
);
\y_int[19]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[19]_i_4_n_0\,
I1 => y_int_reg1(17),
I2 => \y_int[19]_i_12_n_0\,
I3 => y_int_reg20_in(17),
O => \y_int[19]_i_8_n_0\
);
\y_int[19]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[19]_i_5_n_0\,
I1 => y_int_reg1(16),
I2 => \y_int[19]_i_16_n_0\,
I3 => y_int_reg20_in(16),
O => \y_int[19]_i_9_n_0\
);
\y_int[23]_i_100\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_19\(0),
I1 => \^y_int_reg[3]_0\(0),
O => \y_int[23]_i_100_n_0\
);
\y_int[23]_i_101\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[14]\(0),
I1 => \^y_int_reg[3]_0\(3),
O => \y_int[23]_i_101_n_0\
);
\y_int[23]_i_102\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[3]_0\(2),
I1 => \^y_int_reg[3]_0\(1),
O => \y_int[23]_i_102_n_0\
);
\y_int[23]_i_103\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[3]_0\(0),
I1 => \rgb888[8]_19\(0),
O => \y_int[23]_i_103_n_0\
);
\y_int[23]_i_104\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(8),
O => \y_int[23]_i_104_n_0\
);
\y_int[23]_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_23\(1),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_24\(0),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[23]_i_12_n_0\
);
\y_int[23]_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(13),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_1\(1),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(22)
);
\y_int[23]_i_14\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_23\(0),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_25\(3),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[23]_i_14_n_0\
);
\y_int[23]_i_15\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(12),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_1\(0),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(21)
);
\y_int[23]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_26\(3),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_25\(2),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[23]_i_18_n_0\
);
\y_int[23]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(11),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_2\(3),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(20)
);
\y_int[23]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(30),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(22),
I4 => \y_int[23]_i_12_n_0\,
I5 => y_int_reg1(22),
O => \y_int[23]_i_2_n_0\
);
\y_int[23]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_26\(2),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_25\(1),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[23]_i_20_n_0\
);
\y_int[23]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(10),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_2\(2),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(19)
);
\y_int[23]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(22),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(30),
I3 => y_int_reg6,
O => y_int_reg20_in(22)
);
\y_int[23]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(21),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(29),
I3 => y_int_reg6,
O => y_int_reg20_in(21)
);
\y_int[23]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(20),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(28),
I3 => y_int_reg6,
O => y_int_reg20_in(20)
);
\y_int[23]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_26_n_0\
);
\y_int[23]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_27_n_0\
);
\y_int[23]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_28_n_0\
);
\y_int[23]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_29_n_0\
);
\y_int[23]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(29),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(21),
I4 => \y_int[23]_i_14_n_0\,
I5 => y_int_reg1(21),
O => \y_int[23]_i_3_n_0\
);
\y_int[23]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_30_n_0\
);
\y_int[23]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_31_n_0\
);
\y_int[23]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_36_n_0\
);
\y_int[23]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_37_n_0\
);
\y_int[23]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_38_n_0\
);
\y_int[23]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_39_n_0\
);
\y_int[23]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(28),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(20),
I4 => \y_int[23]_i_18_n_0\,
I5 => y_int_reg1(20),
O => \y_int[23]_i_4_n_0\
);
\y_int[23]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(28),
O => \y_int[23]_i_40_n_0\
);
\y_int[23]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(27),
O => \y_int[23]_i_41_n_0\
);
\y_int[23]_i_42\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(26),
O => \y_int[23]_i_42_n_0\
);
\y_int[23]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(25),
O => \y_int[23]_i_43_n_0\
);
\y_int[23]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_46_n_0\
);
\y_int[23]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_47_n_0\
);
\y_int[23]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_48_n_0\
);
\y_int[23]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_49_n_0\
);
\y_int[23]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(27),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(19),
I4 => \y_int[23]_i_20_n_0\,
I5 => y_int_reg1(19),
O => \y_int[23]_i_5_n_0\
);
\y_int[23]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_52_n_0\
);
\y_int[23]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_53_n_0\
);
\y_int[23]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_54_n_0\
);
\y_int[23]_i_55\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_55_n_0\
);
\y_int[23]_i_56\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_56_n_0\
);
\y_int[23]_i_57\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_57_n_0\
);
\y_int[23]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[23]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[23]_i_6_n_0\
);
\y_int[23]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_62_n_0\
);
\y_int[23]_i_63\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_63_n_0\
);
\y_int[23]_i_64\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_64_n_0\
);
\y_int[23]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_65_n_0\
);
\y_int[23]_i_67\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_8_n_7\,
I1 => \y_int_reg[31]_i_8_n_6\,
O => \y_int[23]_i_67_n_0\
);
\y_int[23]_i_68\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_16_n_5\,
I1 => \y_int_reg[31]_i_16_n_4\,
O => \y_int[23]_i_68_n_0\
);
\y_int[23]_i_69\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_16_n_7\,
I1 => \y_int_reg[31]_i_16_n_6\,
O => \y_int[23]_i_69_n_0\
);
\y_int[23]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[23]_i_3_n_0\,
I1 => y_int_reg1(22),
I2 => \y_int[23]_i_12_n_0\,
I3 => y_int_reg20_in(22),
O => \y_int[23]_i_7_n_0\
);
\y_int[23]_i_70\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[3]_i_16_n_5\,
I1 => \y_int_reg[3]_i_16_n_4\,
O => \y_int[23]_i_70_n_0\
);
\y_int[23]_i_71\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_6\,
I1 => \y_int_reg[31]_i_8_n_7\,
O => \y_int[23]_i_71_n_0\
);
\y_int[23]_i_72\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_4\,
I1 => \y_int_reg[31]_i_16_n_5\,
O => \y_int[23]_i_72_n_0\
);
\y_int[23]_i_73\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_6\,
I1 => \y_int_reg[31]_i_16_n_7\,
O => \y_int[23]_i_73_n_0\
);
\y_int[23]_i_74\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_4\,
I1 => \y_int_reg[3]_i_16_n_5\,
O => \y_int[23]_i_74_n_0\
);
\y_int[23]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_21\(1),
I1 => \rgb888[8]_21\(2),
O => \y_int[23]_i_76_n_0\
);
\y_int[23]_i_77\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_77_n_0\
);
\y_int[23]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_78_n_0\
);
\y_int[23]_i_79\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_79_n_0\
);
\y_int[23]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[23]_i_4_n_0\,
I1 => y_int_reg1(21),
I2 => \y_int[23]_i_14_n_0\,
I3 => y_int_reg20_in(21),
O => \y_int[23]_i_8_n_0\
);
\y_int[23]_i_80\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \rgb888[8]_21\(1),
O => \y_int[23]_i_80_n_0\
);
\y_int[23]_i_81\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[3]_i_16_n_7\,
I1 => \y_int_reg[3]_i_16_n_6\,
O => \y_int[23]_i_81_n_0\
);
\y_int[23]_i_82\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[3]_i_26_n_5\,
I1 => \y_int_reg[3]_i_26_n_4\,
O => \y_int[23]_i_82_n_0\
);
\y_int[23]_i_83\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[3]_i_26_n_7\,
I1 => \y_int_reg[3]_i_26_n_6\,
O => \y_int[23]_i_83_n_0\
);
\y_int[23]_i_84\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb888(16),
I1 => rgb888(17),
O => \y_int[23]_i_84_n_0\
);
\y_int[23]_i_85\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_6\,
I1 => \y_int_reg[3]_i_16_n_7\,
O => \y_int[23]_i_85_n_0\
);
\y_int[23]_i_86\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_4\,
I1 => \y_int_reg[3]_i_26_n_5\,
O => \y_int[23]_i_86_n_0\
);
\y_int[23]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_6\,
I1 => \y_int_reg[3]_i_26_n_7\,
O => \y_int[23]_i_87_n_0\
);
\y_int[23]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(17),
I1 => rgb888(16),
O => \y_int[23]_i_88_n_0\
);
\y_int[23]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[23]_i_5_n_0\,
I1 => y_int_reg1(20),
I2 => \y_int[23]_i_18_n_0\,
I3 => y_int_reg20_in(20),
O => \y_int[23]_i_9_n_0\
);
\y_int[23]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_20\(3),
I1 => \rgb888[8]_21\(0),
O => \y_int[23]_i_90_n_0\
);
\y_int[23]_i_91\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_20\(1),
I1 => \rgb888[8]_20\(2),
O => \y_int[23]_i_91_n_0\
);
\y_int[23]_i_92\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[14]\(3),
I1 => \rgb888[8]_20\(0),
O => \y_int[23]_i_92_n_0\
);
\y_int[23]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[14]\(1),
I1 => \rgb888[14]\(2),
O => \y_int[23]_i_93_n_0\
);
\y_int[23]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(0),
I1 => \rgb888[8]_20\(3),
O => \y_int[23]_i_94_n_0\
);
\y_int[23]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_20\(2),
I1 => \rgb888[8]_20\(1),
O => \y_int[23]_i_95_n_0\
);
\y_int[23]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_20\(0),
I1 => \rgb888[14]\(3),
O => \y_int[23]_i_96_n_0\
);
\y_int[23]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[14]\(2),
I1 => \rgb888[14]\(1),
O => \y_int[23]_i_97_n_0\
);
\y_int[23]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^y_int_reg[3]_0\(3),
I1 => \rgb888[14]\(0),
O => \y_int[23]_i_98_n_0\
);
\y_int[23]_i_99\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^y_int_reg[3]_0\(1),
I1 => \^y_int_reg[3]_0\(2),
O => \y_int[23]_i_99_n_0\
);
\y_int[27]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[27]_i_2_n_0\
);
\y_int[27]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[27]_i_3_n_0\
);
\y_int[27]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[27]_i_4_n_0\
);
\y_int[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[27]_i_5_n_0\
);
\y_int[31]_i_101\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(7),
O => \y_int[31]_i_101_n_0\
);
\y_int[31]_i_104\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(1),
I1 => rgb888(3),
O => \y_int[31]_i_104_n_0\
);
\y_int[31]_i_105\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
I2 => rgb888(2),
O => \y_int[31]_i_105_n_0\
);
\y_int[31]_i_106\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(2),
I1 => rgb888(0),
O => \y_int[31]_i_106_n_0\
);
\y_int[31]_i_107\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
O => \y_int[31]_i_107_n_0\
);
\y_int[31]_i_108\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(0),
O => \y_int[31]_i_108_n_0\
);
\y_int[31]_i_109\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(6),
O => \y_int[31]_i_109_n_0\
);
\y_int[31]_i_110\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(7),
I1 => rgb888(5),
O => \y_int[31]_i_110_n_0\
);
\y_int[31]_i_111\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
O => \y_int[31]_i_111_n_0\
);
\y_int[31]_i_112\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
O => \y_int[31]_i_112_n_0\
);
\y_int[31]_i_113\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
O => \y_int[31]_i_113_n_0\
);
\y_int[31]_i_114\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
O => \y_int[31]_i_114_n_0\
);
\y_int[31]_i_115\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(2),
I1 => rgb888(0),
O => \y_int[31]_i_115_n_0\
);
\y_int[31]_i_116\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(1),
O => \y_int[31]_i_116_n_0\
);
\y_int[31]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \rgb888[8]_30\(0),
O => \y_int[31]_i_13_n_0\
);
\y_int[31]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(30),
O => \y_int[31]_i_14_n_0\
);
\y_int[31]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(29),
O => \y_int[31]_i_15_n_0\
);
\y_int[31]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
I2 => rgb888(19),
I3 => rgb888(21),
I4 => rgb888(22),
I5 => rgb888(23),
O => \y_int[31]_i_17_n_0\
);
\y_int[31]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(23),
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(19),
I4 => rgb888(21),
I5 => rgb888(22),
O => \y_int[31]_i_18_n_0\
);
\y_int[31]_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(23),
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(19),
I4 => rgb888(21),
I5 => rgb888(22),
O => \y_int[31]_i_19_n_0\
);
\y_int[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040004044F40040"
)
port map (
I0 => \y_int_reg[31]_i_7_n_1\,
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \rgb888[8]_21\(2),
I3 => \rgb888[8]_30\(0),
I4 => \^y_int_reg[23]_0\(0),
I5 => \rgb888[1]_0\(0),
O => \y_int[31]_i_2_n_0\
);
\y_int[31]_i_20\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000007FFFFFFF"
)
port map (
I0 => rgb888(22),
I1 => rgb888(21),
I2 => rgb888(19),
I3 => rgb888(18),
I4 => rgb888(20),
I5 => rgb888(23),
O => \y_int[31]_i_20_n_0\
);
\y_int[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[31]_i_3_n_0\
);
\y_int[31]_i_32\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[0]_7\(3),
I1 => \y_int_reg[31]_i_75_n_2\,
O => \y_int[31]_i_32_n_0\
);
\y_int[31]_i_33\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[0]_9\(2),
O => \y_int[31]_i_33_n_0\
);
\y_int[31]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[0]_9\(2),
O => \y_int[31]_i_34_n_0\
);
\y_int[31]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \y_int_reg[31]_i_75_n_2\,
I1 => \rgb888[0]_9\(0),
I2 => \rgb888[0]_9\(1),
O => \y_int[31]_i_35_n_0\
);
\y_int[31]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"36"
)
port map (
I0 => \rgb888[0]_7\(3),
I1 => \rgb888[0]_9\(0),
I2 => \y_int_reg[31]_i_75_n_2\,
O => \y_int[31]_i_36_n_0\
);
\y_int[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[31]_i_4_n_0\
);
\y_int[31]_i_40\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
I2 => rgb888(19),
I3 => rgb888(21),
I4 => rgb888(22),
O => \y_int[31]_i_40_n_0\
);
\y_int[31]_i_41\: unisim.vcomponents.LUT5
generic map(
INIT => X"BEEEEEEE"
)
port map (
I0 => \y_int_reg[3]_i_64_n_2\,
I1 => rgb888(21),
I2 => rgb888(20),
I3 => rgb888(18),
I4 => rgb888(19),
O => \y_int[31]_i_41_n_0\
);
\y_int[31]_i_42\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FD51540"
)
port map (
I0 => \y_int_reg[3]_i_64_n_2\,
I1 => rgb888(18),
I2 => rgb888(19),
I3 => rgb888(20),
I4 => rgb888(23),
O => \y_int[31]_i_42_n_0\
);
\y_int[31]_i_43\: unisim.vcomponents.LUT4
generic map(
INIT => X"BE28"
)
port map (
I0 => \y_int_reg[3]_i_64_n_7\,
I1 => rgb888(18),
I2 => rgb888(19),
I3 => rgb888(22),
O => \y_int[31]_i_43_n_0\
);
\y_int[31]_i_44\: unisim.vcomponents.LUT6
generic map(
INIT => X"A999999999999999"
)
port map (
I0 => rgb888(23),
I1 => rgb888(22),
I2 => rgb888(21),
I3 => rgb888(19),
I4 => rgb888(18),
I5 => rgb888(20),
O => \y_int[31]_i_44_n_0\
);
\y_int[31]_i_45\: unisim.vcomponents.LUT6
generic map(
INIT => X"6CC9C9C9C9C9C9C9"
)
port map (
I0 => \y_int_reg[3]_i_64_n_2\,
I1 => rgb888(22),
I2 => rgb888(21),
I3 => rgb888(19),
I4 => rgb888(18),
I5 => rgb888(20),
O => \y_int[31]_i_45_n_0\
);
\y_int[31]_i_46\: unisim.vcomponents.LUT6
generic map(
INIT => X"157FEA807FEA8015"
)
port map (
I0 => rgb888(23),
I1 => rgb888(19),
I2 => rgb888(18),
I3 => rgb888(20),
I4 => rgb888(21),
I5 => \y_int_reg[3]_i_64_n_2\,
O => \y_int[31]_i_46_n_0\
);
\y_int[31]_i_47\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996699669"
)
port map (
I0 => \y_int[31]_i_43_n_0\,
I1 => \y_int_reg[3]_i_64_n_2\,
I2 => rgb888(23),
I3 => rgb888(20),
I4 => rgb888(19),
I5 => rgb888(18),
O => \y_int[31]_i_47_n_0\
);
\y_int[31]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[31]_i_5_n_0\
);
\y_int[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[31]_i_6_n_0\
);
\y_int[31]_i_63\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \rgb888[0]_7\(2),
I1 => \y_int_reg[31]_i_75_n_7\,
O => \y_int[31]_i_63_n_0\
);
\y_int[31]_i_64\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_87_n_4\,
I1 => \rgb888[0]_7\(1),
O => \y_int[31]_i_64_n_0\
);
\y_int[31]_i_65\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \y_int_reg[31]_i_87_n_4\,
I1 => \rgb888[0]_7\(1),
O => \y_int[31]_i_65_n_0\
);
\y_int[31]_i_66\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \y_int_reg[31]_i_86_n_4\,
I1 => \y_int_reg[31]_i_87_n_6\,
O => \y_int[31]_i_66_n_0\
);
\y_int[31]_i_67\: unisim.vcomponents.LUT4
generic map(
INIT => X"7887"
)
port map (
I0 => \y_int_reg[31]_i_75_n_7\,
I1 => \rgb888[0]_7\(2),
I2 => \y_int_reg[31]_i_75_n_2\,
I3 => \rgb888[0]_7\(3),
O => \y_int[31]_i_67_n_0\
);
\y_int[31]_i_68\: unisim.vcomponents.LUT4
generic map(
INIT => X"E11E"
)
port map (
I0 => \rgb888[0]_7\(1),
I1 => \y_int_reg[31]_i_87_n_4\,
I2 => \rgb888[0]_7\(2),
I3 => \y_int_reg[31]_i_75_n_7\,
O => \y_int[31]_i_68_n_0\
);
\y_int[31]_i_69\: unisim.vcomponents.LUT4
generic map(
INIT => X"6999"
)
port map (
I0 => \rgb888[0]_7\(1),
I1 => \y_int_reg[31]_i_87_n_4\,
I2 => \y_int_reg[31]_i_87_n_5\,
I3 => \rgb888[0]_7\(0),
O => \y_int[31]_i_69_n_0\
);
\y_int[31]_i_70\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \y_int_reg[31]_i_87_n_6\,
I1 => \y_int_reg[31]_i_86_n_4\,
I2 => \rgb888[0]_7\(0),
I3 => \y_int_reg[31]_i_87_n_5\,
O => \y_int[31]_i_70_n_0\
);
\y_int[31]_i_89\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \y_int_reg[31]_i_86_n_5\,
I1 => \y_int_reg[31]_i_86_n_4\,
I2 => \y_int_reg[31]_i_87_n_6\,
O => \y_int[31]_i_89_n_0\
);
\y_int[31]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \y_int_reg[31]_i_86_n_5\,
I1 => \y_int_reg[31]_i_87_n_7\,
O => \y_int[31]_i_90_n_0\
);
\y_int[31]_i_91\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[31]_i_88_n_4\,
I1 => \y_int_reg[31]_i_86_n_6\,
O => \y_int[31]_i_91_n_0\
);
\y_int[31]_i_92\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[31]_i_88_n_5\,
I1 => rgb888(0),
O => \y_int[31]_i_92_n_0\
);
\y_int[3]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[7]_i_24_n_6\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[14]\(3),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_1\(0),
O => \y_int[3]_i_10_n_0\
);
\y_int[3]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(2),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_30_n_4\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_44_n_6\,
O => y_int_reg1(2)
);
\y_int[3]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(1),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[3]_i_16_n_4\,
I3 => y_int_reg6,
I4 => y_int_reg5(9),
O => y_int_reg20_in(1)
);
\y_int[3]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[7]_i_24_n_7\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[14]\(2),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_0\(1),
O => \y_int[3]_i_13_n_0\
);
\y_int[3]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(1),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_30_n_5\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_44_n_7\,
O => y_int_reg1(1)
);
\y_int[3]_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \rgb888[14]\(1),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[14]_0\(0),
O => \y_int[3]_i_17_n_0\
);
\y_int[3]_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \y_int_reg[31]_i_30_n_6\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[3]_i_35_n_4\,
O => \y_int[3]_i_18_n_0\
);
\y_int[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(2),
I1 => \y_int[3]_i_10_n_0\,
I2 => y_int_reg1(2),
O => \y_int[3]_i_2_n_0\
);
\y_int[3]_i_22\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_5\,
O => \y_int[3]_i_22_n_0\
);
\y_int[3]_i_23\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_6\,
O => \y_int[3]_i_23_n_0\
);
\y_int[3]_i_24\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_7\,
O => \y_int[3]_i_24_n_0\
);
\y_int[3]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_4\,
O => \y_int[3]_i_25_n_0\
);
\y_int[3]_i_27\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => rgb888(18),
I1 => \y_int_reg[3]_i_30_n_4\,
I2 => rgb888(21),
O => \y_int[3]_i_27_n_0\
);
\y_int[3]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \y_int_reg[3]_i_30_n_5\,
I1 => rgb888(17),
I2 => rgb888(20),
O => \y_int[3]_i_28_n_0\
);
\y_int[3]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \y_int_reg[3]_i_30_n_5\,
I1 => rgb888(17),
I2 => rgb888(20),
O => \y_int[3]_i_29_n_0\
);
\y_int[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(1),
I1 => \y_int[3]_i_13_n_0\,
I2 => y_int_reg1(1),
O => \y_int[3]_i_3_n_0\
);
\y_int[3]_i_31\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \y_int[3]_i_27_n_0\,
I1 => rgb888(22),
I2 => rgb888(19),
I3 => rgb888(18),
I4 => \y_int_reg[3]_i_64_n_7\,
O => \y_int[3]_i_31_n_0\
);
\y_int[3]_i_32\: unisim.vcomponents.LUT6
generic map(
INIT => X"E81717E817E8E817"
)
port map (
I0 => rgb888(20),
I1 => rgb888(17),
I2 => \y_int_reg[3]_i_30_n_5\,
I3 => rgb888(21),
I4 => rgb888(18),
I5 => \y_int_reg[3]_i_30_n_4\,
O => \y_int[3]_i_32_n_0\
);
\y_int[3]_i_33\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969696"
)
port map (
I0 => rgb888(20),
I1 => rgb888(17),
I2 => \y_int_reg[3]_i_30_n_5\,
I3 => rgb888(19),
I4 => rgb888(16),
O => \y_int[3]_i_33_n_0\
);
\y_int[3]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(16),
I1 => rgb888(19),
I2 => \y_int_reg[3]_i_30_n_6\,
O => \y_int[3]_i_34_n_0\
);
\y_int[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2E200"
)
port map (
I0 => y_int_reg5(8),
I1 => y_int_reg6,
I2 => \y_int_reg[3]_i_16_n_5\,
I3 => \y_int[3]_i_17_n_0\,
I4 => \y_int[3]_i_18_n_0\,
O => \y_int[3]_i_4_n_0\
);
\y_int[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(3),
I1 => \y_int[7]_i_19_n_0\,
I2 => y_int_reg1(3),
I3 => \y_int[3]_i_2_n_0\,
O => \y_int[3]_i_5_n_0\
);
\y_int[3]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(16),
O => \y_int[3]_i_50_n_0\
);
\y_int[3]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_5\,
O => \y_int[3]_i_51_n_0\
);
\y_int[3]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_6\,
O => \y_int[3]_i_52_n_0\
);
\y_int[3]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_7\,
O => \y_int[3]_i_53_n_0\
);
\y_int[3]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(17),
O => \y_int[3]_i_54_n_0\
);
\y_int[3]_i_56\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[3]_i_30_n_7\,
I1 => rgb888(18),
O => \y_int[3]_i_56_n_0\
);
\y_int[3]_i_57\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[3]_i_55_n_4\,
I1 => rgb888(17),
O => \y_int[3]_i_57_n_0\
);
\y_int[3]_i_58\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[3]_i_55_n_5\,
I1 => rgb888(16),
O => \y_int[3]_i_58_n_0\
);
\y_int[3]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg[3]_i_55_n_6\,
O => \y_int[3]_i_59_n_0\
);
\y_int[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(2),
I1 => \y_int[3]_i_10_n_0\,
I2 => y_int_reg1(2),
I3 => \y_int[3]_i_3_n_0\,
O => \y_int[3]_i_6_n_0\
);
\y_int[3]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(22),
O => \y_int[3]_i_60_n_0\
);
\y_int[3]_i_61\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(23),
I1 => rgb888(21),
O => \y_int[3]_i_61_n_0\
);
\y_int[3]_i_62\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(22),
I1 => rgb888(20),
O => \y_int[3]_i_62_n_0\
);
\y_int[3]_i_63\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(21),
I1 => rgb888(19),
O => \y_int[3]_i_63_n_0\
);
\y_int[3]_i_66\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_6\,
O => \y_int[3]_i_66_n_0\
);
\y_int[3]_i_67\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_7\,
O => \y_int[3]_i_67_n_0\
);
\y_int[3]_i_68\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_62_n_4\,
O => \y_int[3]_i_68_n_0\
);
\y_int[3]_i_69\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_62_n_5\,
O => \y_int[3]_i_69_n_0\
);
\y_int[3]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(1),
I1 => \y_int[3]_i_13_n_0\,
I2 => y_int_reg1(1),
I3 => \y_int[3]_i_4_n_0\,
O => \y_int[3]_i_7_n_0\
);
\y_int[3]_i_71\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_32\(1),
I1 => rgb888(10),
O => \y_int[3]_i_71_n_0\
);
\y_int[3]_i_72\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_32\(0),
I1 => rgb888(9),
O => \y_int[3]_i_72_n_0\
);
\y_int[3]_i_73\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_19\(2),
I1 => rgb888(8),
O => \y_int[3]_i_73_n_0\
);
\y_int[3]_i_74\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[8]_19\(1),
O => \y_int[3]_i_74_n_0\
);
\y_int[3]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"E21D1DE2"
)
port map (
I0 => y_int_reg5(8),
I1 => y_int_reg6,
I2 => \y_int_reg[3]_i_16_n_5\,
I3 => \y_int[3]_i_17_n_0\,
I4 => \y_int[3]_i_18_n_0\,
O => \y_int[3]_i_8_n_0\
);
\y_int[3]_i_84\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
O => \y_int[3]_i_84_n_0\
);
\y_int[3]_i_85\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(19),
I1 => rgb888(17),
O => \y_int[3]_i_85_n_0\
);
\y_int[3]_i_86\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(18),
I1 => rgb888(16),
O => \y_int[3]_i_86_n_0\
);
\y_int[3]_i_87\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(17),
O => \y_int[3]_i_87_n_0\
);
\y_int[3]_i_88\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(23),
O => \y_int[3]_i_88_n_0\
);
\y_int[3]_i_89\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_62_n_6\,
O => \y_int[3]_i_89_n_0\
);
\y_int[3]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(2),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_16_n_7\,
I3 => y_int_reg6,
I4 => y_int_reg5(10),
O => y_int_reg20_in(2)
);
\y_int[3]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(0),
I1 => \y_int_reg[31]_i_88_n_5\,
O => \y_int[3]_i_90_n_0\
);
\y_int[3]_i_91\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_88_n_6\,
O => \y_int[3]_i_91_n_0\
);
\y_int[3]_i_92\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
O => \y_int[3]_i_92_n_0\
);
\y_int[7]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(6),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_8_n_7\,
I3 => y_int_reg6,
I4 => y_int_reg5(14),
O => y_int_reg20_in(6)
);
\y_int[7]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[11]_i_38_n_6\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_20\(3),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[8]_22\(0),
O => \y_int[7]_i_11_n_0\
);
\y_int[7]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(5),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_16_n_4\,
I3 => y_int_reg6,
I4 => y_int_reg5(13),
O => y_int_reg20_in(5)
);
\y_int[7]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[11]_i_38_n_7\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_20\(2),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_1\(3),
O => \y_int[7]_i_13_n_0\
);
\y_int[7]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(5),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_11_n_5\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_21_n_7\,
O => y_int_reg1(5)
);
\y_int[7]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(4),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_16_n_5\,
I3 => y_int_reg6,
I4 => y_int_reg5(12),
O => y_int_reg20_in(4)
);
\y_int[7]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[7]_i_24_n_4\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_20\(1),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_1\(2),
O => \y_int[7]_i_16_n_0\
);
\y_int[7]_i_17\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(4),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_11_n_6\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_44_n_4\,
O => y_int_reg1(4)
);
\y_int[7]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(3),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_16_n_6\,
I3 => y_int_reg6,
I4 => y_int_reg5(11),
O => y_int_reg20_in(3)
);
\y_int[7]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[7]_i_24_n_5\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_20\(0),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_1\(1),
O => \y_int[7]_i_19_n_0\
);
\y_int[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"E888E888E8EEE888"
)
port map (
I0 => y_int_reg20_in(6),
I1 => \y_int[7]_i_11_n_0\,
I2 => y_int_reg2(6),
I3 => \^y_int_reg[23]_0\(0),
I4 => \y_int_reg[11]_i_21_n_6\,
I5 => \^y_int_reg[7]_0\(0),
O => \y_int[7]_i_2_n_0\
);
\y_int[7]_i_20\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(3),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_11_n_7\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_44_n_5\,
O => y_int_reg1(3)
);
\y_int[7]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg2(7),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[11]_i_21_n_5\,
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(7)
);
\y_int[7]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg2(6),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[11]_i_21_n_6\,
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(6)
);
\y_int[7]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_0\(0),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[14]\(1),
O => \y_int[7]_i_29_n_0\
);
\y_int[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(5),
I1 => \y_int[7]_i_13_n_0\,
I2 => y_int_reg1(5),
O => \y_int[7]_i_3_n_0\
);
\y_int[7]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_1\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_20\(1),
O => \y_int[7]_i_30_n_0\
);
\y_int[7]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_1\(1),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_20\(0),
O => \y_int[7]_i_31_n_0\
);
\y_int[7]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_1\(0),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[14]\(3),
O => \y_int[7]_i_32_n_0\
);
\y_int[7]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_0\(1),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[14]\(2),
O => \y_int[7]_i_33_n_0\
);
\y_int[7]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(4),
I1 => \y_int[7]_i_16_n_0\,
I2 => y_int_reg1(4),
O => \y_int[7]_i_4_n_0\
);
\y_int[7]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(3),
I1 => \y_int[7]_i_19_n_0\,
I2 => y_int_reg1(3),
O => \y_int[7]_i_5_n_0\
);
\y_int[7]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[7]_i_2_n_0\,
I1 => y_int_reg1(7),
I2 => \y_int[11]_i_19_n_0\,
I3 => y_int_reg20_in(7),
O => \y_int[7]_i_6_n_0\
);
\y_int[7]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[7]_i_3_n_0\,
I1 => y_int_reg1(6),
I2 => \y_int[7]_i_11_n_0\,
I3 => y_int_reg20_in(6),
O => \y_int[7]_i_7_n_0\
);
\y_int[7]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(5),
I1 => \y_int[7]_i_13_n_0\,
I2 => y_int_reg1(5),
I3 => \y_int[7]_i_4_n_0\,
O => \y_int[7]_i_8_n_0\
);
\y_int[7]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(4),
I1 => \y_int[7]_i_16_n_0\,
I2 => y_int_reg1(4),
I3 => \y_int[7]_i_5_n_0\,
O => \y_int[7]_i_9_n_0\
);
\y_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[3]_i_1_n_7\,
Q => \y_int_reg_n_0_[0]\,
R => '0'
);
\y_int_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[11]_i_1_n_5\,
Q => \y_int_reg__0\(10),
R => '0'
);
\y_int_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[11]_i_1_n_4\,
Q => \y_int_reg__0\(11),
R => '0'
);
\y_int_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[7]_i_1_n_0\,
CO(3) => \y_int_reg[11]_i_1_n_0\,
CO(2) => \y_int_reg[11]_i_1_n_1\,
CO(1) => \y_int_reg[11]_i_1_n_2\,
CO(0) => \y_int_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[11]_i_2_n_0\,
DI(2) => \y_int[11]_i_3_n_0\,
DI(1) => \y_int[11]_i_4_n_0\,
DI(0) => \y_int[11]_i_5_n_0\,
O(3) => \y_int_reg[11]_i_1_n_4\,
O(2) => \y_int_reg[11]_i_1_n_5\,
O(1) => \y_int_reg[11]_i_1_n_6\,
O(0) => \y_int_reg[11]_i_1_n_7\,
S(3) => \y_int[11]_i_6_n_0\,
S(2) => \y_int[11]_i_7_n_0\,
S(1) => \y_int[11]_i_8_n_0\,
S(0) => \y_int[11]_i_9_n_0\
);
\y_int_reg[11]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_28_n_0\,
CO(3) => \y_int_reg[11]_i_14_n_0\,
CO(2) => \y_int_reg[11]_i_14_n_1\,
CO(1) => \y_int_reg[11]_i_14_n_2\,
CO(0) => \y_int_reg[11]_i_14_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(16 downto 13),
S(3) => \y_int[11]_i_29_n_0\,
S(2) => \y_int[11]_i_30_n_0\,
S(1) => \y_int[11]_i_31_n_0\,
S(0) => \y_int[11]_i_32_n_0\
);
\y_int_reg[11]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_33_n_0\,
CO(3) => \y_int_reg[11]_i_15_n_0\,
CO(2) => \y_int_reg[11]_i_15_n_1\,
CO(1) => \y_int_reg[11]_i_15_n_2\,
CO(0) => \y_int_reg[11]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(8 downto 5),
S(3) => \y_int[11]_i_34_n_0\,
S(2) => \y_int[11]_i_35_n_0\,
S(1) => \y_int[11]_i_36_n_0\,
S(0) => \y_int[11]_i_37_n_0\
);
\y_int_reg[11]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_39_n_0\,
CO(3) => \y_int_reg[15]_1\(0),
CO(2) => \y_int_reg[11]_i_20_n_1\,
CO(1) => \y_int_reg[11]_i_20_n_2\,
CO(0) => \y_int_reg[11]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(8 downto 5),
S(3) => \y_int[11]_i_40_n_0\,
S(2) => \y_int[11]_i_41_n_0\,
S(1) => \y_int[11]_i_42_n_0\,
S(0) => \y_int[11]_i_43_n_0\
);
\y_int_reg[11]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_44_n_0\,
CO(3) => \y_int_reg[11]_i_21_n_0\,
CO(2) => \y_int_reg[11]_i_21_n_1\,
CO(1) => \y_int_reg[11]_i_21_n_2\,
CO(0) => \y_int_reg[11]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[11]_i_21_n_4\,
O(2) => \y_int_reg[11]_i_21_n_5\,
O(1) => \y_int_reg[11]_i_21_n_6\,
O(0) => \y_int_reg[11]_i_21_n_7\,
S(3) => \y_int[11]_i_45_n_0\,
S(2) => \y_int[11]_i_46_n_0\,
S(1) => \y_int[11]_i_47_n_0\,
S(0) => \y_int[11]_i_48_n_0\
);
\y_int_reg[11]_i_22\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_49_n_0\,
CO(3) => \^y_int_reg[7]_0\(0),
CO(2) => \y_int_reg[11]_i_22_n_1\,
CO(1) => \y_int_reg[11]_i_22_n_2\,
CO(0) => \y_int_reg[11]_i_22_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \^y_int_reg[23]_0\(0),
DI(1) => \^y_int_reg[23]_0\(0),
DI(0) => \^y_int_reg[23]_0\(0),
O(3 downto 0) => \NLW_y_int_reg[11]_i_22_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[11]_i_50_n_0\,
S(2) => \y_int[11]_i_51_n_0\,
S(1) => \y_int[11]_i_52_n_0\,
S(0) => \y_int[11]_i_53_n_0\
);
\y_int_reg[11]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_15_n_0\,
CO(3) => \y_int_reg[11]_i_28_n_0\,
CO(2) => \y_int_reg[11]_i_28_n_1\,
CO(1) => \y_int_reg[11]_i_28_n_2\,
CO(0) => \y_int_reg[11]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(12 downto 9),
S(3) => \y_int[11]_i_58_n_0\,
S(2) => \y_int[11]_i_59_n_0\,
S(1) => \y_int[11]_i_60_n_0\,
S(0) => \y_int[11]_i_61_n_0\
);
\y_int_reg[11]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[11]_i_33_n_0\,
CO(2) => \y_int_reg[11]_i_33_n_1\,
CO(1) => \y_int_reg[11]_i_33_n_2\,
CO(0) => \y_int_reg[11]_i_33_n_3\,
CYINIT => \y_int[11]_i_62_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(4 downto 1),
S(3) => \y_int[11]_i_63_n_0\,
S(2) => \y_int[11]_i_64_n_0\,
S(1) => \y_int[11]_i_65_n_0\,
S(0) => \y_int[11]_i_66_n_0\
);
\y_int_reg[11]_i_38\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[7]_i_24_n_0\,
CO(3) => \y_int_reg[11]_i_38_n_0\,
CO(2) => \y_int_reg[11]_i_38_n_1\,
CO(1) => \y_int_reg[11]_i_38_n_2\,
CO(0) => \y_int_reg[11]_i_38_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[11]_i_38_n_4\,
O(2) => \y_int_reg[11]_i_38_n_5\,
O(1) => \y_int_reg[11]_i_38_n_6\,
O(0) => \y_int_reg[11]_i_38_n_7\,
S(3) => \y_int[11]_i_67_n_0\,
S(2) => \y_int[11]_i_68_n_0\,
S(1) => \y_int[11]_i_69_n_0\,
S(0) => \y_int[11]_i_70_n_0\
);
\y_int_reg[11]_i_39\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[11]_i_39_n_0\,
CO(2) => \y_int_reg[11]_i_39_n_1\,
CO(1) => \y_int_reg[11]_i_39_n_2\,
CO(0) => \y_int_reg[11]_i_39_n_3\,
CYINIT => \y_int[11]_i_71_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(4 downto 1),
S(3) => \y_int[11]_i_72_n_0\,
S(2) => \y_int[11]_i_73_n_0\,
S(1) => \y_int[11]_i_74_n_0\,
S(0) => \y_int[11]_i_75_n_0\
);
\y_int_reg[11]_i_44\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_35_n_0\,
CO(3) => \y_int_reg[11]_i_44_n_0\,
CO(2) => \y_int_reg[11]_i_44_n_1\,
CO(1) => \y_int_reg[11]_i_44_n_2\,
CO(0) => \y_int_reg[11]_i_44_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[11]_i_44_n_4\,
O(2) => \y_int_reg[11]_i_44_n_5\,
O(1) => \y_int_reg[11]_i_44_n_6\,
O(0) => \y_int_reg[11]_i_44_n_7\,
S(3) => \y_int[11]_i_76_n_0\,
S(2) => \y_int[11]_i_77_n_0\,
S(1) => \y_int[11]_i_78_n_0\,
S(0) => \y_int[11]_i_79_n_0\
);
\y_int_reg[11]_i_49\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_80_n_0\,
CO(3) => \y_int_reg[11]_i_49_n_0\,
CO(2) => \y_int_reg[11]_i_49_n_1\,
CO(1) => \y_int_reg[11]_i_49_n_2\,
CO(0) => \y_int_reg[11]_i_49_n_3\,
CYINIT => '0',
DI(3) => \^y_int_reg[23]_0\(0),
DI(2) => \^y_int_reg[23]_0\(0),
DI(1) => \^y_int_reg[23]_0\(0),
DI(0) => \^y_int_reg[23]_0\(0),
O(3 downto 0) => \NLW_y_int_reg[11]_i_49_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[11]_i_81_n_0\,
S(2) => \y_int[11]_i_82_n_0\,
S(1) => \y_int[11]_i_83_n_0\,
S(0) => \y_int[11]_i_84_n_0\
);
\y_int_reg[11]_i_80\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_85_n_0\,
CO(3) => \y_int_reg[11]_i_80_n_0\,
CO(2) => \y_int_reg[11]_i_80_n_1\,
CO(1) => \y_int_reg[11]_i_80_n_2\,
CO(0) => \y_int_reg[11]_i_80_n_3\,
CYINIT => '0',
DI(3) => \^y_int_reg[23]_0\(0),
DI(2) => \y_int[11]_i_86_n_0\,
DI(1) => \y_int[11]_i_87_n_0\,
DI(0) => \y_int[11]_i_88_n_0\,
O(3 downto 0) => \NLW_y_int_reg[11]_i_80_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[11]_i_89_n_0\,
S(2) => \y_int[11]_i_90_n_0\,
S(1) => \y_int[11]_i_91_n_0\,
S(0) => \y_int[11]_i_92_n_0\
);
\y_int_reg[11]_i_85\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[11]_i_85_n_0\,
CO(2) => \y_int_reg[11]_i_85_n_1\,
CO(1) => \y_int_reg[11]_i_85_n_2\,
CO(0) => \y_int_reg[11]_i_85_n_3\,
CYINIT => '1',
DI(3) => \y_int[11]_i_93_n_0\,
DI(2) => \y_int[11]_i_94_n_0\,
DI(1) => \y_int[11]_i_95_n_0\,
DI(0) => \y_int[11]_i_96_n_0\,
O(3 downto 0) => \NLW_y_int_reg[11]_i_85_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[11]_i_97_n_0\,
S(2) => \y_int[11]_i_98_n_0\,
S(1) => \y_int[11]_i_99_n_0\,
S(0) => \y_int[11]_i_100_n_0\
);
\y_int_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[15]_i_1_n_7\,
Q => \y_int_reg__0\(12),
R => '0'
);
\y_int_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[15]_i_1_n_6\,
Q => \y_int_reg__0\(13),
R => '0'
);
\y_int_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[15]_i_1_n_5\,
Q => \y_int_reg__0\(14),
R => '0'
);
\y_int_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[15]_i_1_n_4\,
Q => \y_int_reg__0\(15),
R => '0'
);
\y_int_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_1_n_0\,
CO(3) => \y_int_reg[15]_i_1_n_0\,
CO(2) => \y_int_reg[15]_i_1_n_1\,
CO(1) => \y_int_reg[15]_i_1_n_2\,
CO(0) => \y_int_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[15]_i_2_n_0\,
DI(2) => \y_int[15]_i_3_n_0\,
DI(1) => \y_int[15]_i_4_n_0\,
DI(0) => \y_int[15]_i_5_n_0\,
O(3) => \y_int_reg[15]_i_1_n_4\,
O(2) => \y_int_reg[15]_i_1_n_5\,
O(1) => \y_int_reg[15]_i_1_n_6\,
O(0) => \y_int_reg[15]_i_1_n_7\,
S(3) => \y_int[15]_i_6_n_0\,
S(2) => \y_int[15]_i_7_n_0\,
S(1) => \y_int[15]_i_8_n_0\,
S(0) => \y_int[15]_i_9_n_0\
);
\y_int_reg[15]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_14_n_0\,
CO(3) => \y_int_reg[15]_i_14_n_0\,
CO(2) => \y_int_reg[15]_i_14_n_1\,
CO(1) => \y_int_reg[15]_i_14_n_2\,
CO(0) => \y_int_reg[15]_i_14_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(20 downto 17),
S(3) => \y_int[15]_i_25_n_0\,
S(2) => \y_int[15]_i_26_n_0\,
S(1) => \y_int[15]_i_27_n_0\,
S(0) => \y_int[15]_i_28_n_0\
);
\y_int_reg[15]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_15_n_0\,
CO(3) => \y_int_reg[15]_i_15_n_0\,
CO(2) => \y_int_reg[15]_i_15_n_1\,
CO(1) => \y_int_reg[15]_i_15_n_2\,
CO(0) => \y_int_reg[15]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(12 downto 9),
S(3) => \y_int[15]_i_29_n_0\,
S(2) => \y_int[15]_i_30_n_0\,
S(1) => \y_int[15]_i_31_n_0\,
S(0) => \y_int[15]_i_32_n_0\
);
\y_int_reg[15]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_38_n_0\,
CO(3) => \y_int_reg[19]_1\(0),
CO(2) => \y_int_reg[15]_i_33_n_1\,
CO(1) => \y_int_reg[15]_i_33_n_2\,
CO(0) => \y_int_reg[15]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[15]_i_33_n_4\,
O(2) => \y_int_reg[15]_i_33_n_5\,
O(1) => \y_int_reg[15]_i_33_n_6\,
O(0) => \y_int_reg[15]_i_33_n_7\,
S(3) => \y_int[15]_i_40_n_0\,
S(2) => \y_int[15]_i_41_n_0\,
S(1) => \y_int[15]_i_42_n_0\,
S(0) => \y_int[15]_i_43_n_0\
);
\y_int_reg[15]_i_35\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_21_n_0\,
CO(3) => \y_int_reg[15]_i_35_n_0\,
CO(2) => \y_int_reg[15]_i_35_n_1\,
CO(1) => \y_int_reg[15]_i_35_n_2\,
CO(0) => \y_int_reg[15]_i_35_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^y_int_reg[15]_0\(3 downto 0),
S(3) => \y_int[15]_i_48_n_0\,
S(2) => \y_int[15]_i_49_n_0\,
S(1) => \y_int[15]_i_50_n_0\,
S(0) => \y_int[15]_i_51_n_0\
);
\y_int_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[19]_i_1_n_7\,
Q => \y_int_reg__0\(16),
R => '0'
);
\y_int_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[19]_i_1_n_6\,
Q => \y_int_reg__0\(17),
R => '0'
);
\y_int_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[19]_i_1_n_5\,
Q => \y_int_reg__0\(18),
R => '0'
);
\y_int_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[19]_i_1_n_4\,
Q => \y_int_reg__0\(19),
R => '0'
);
\y_int_reg[19]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_1_n_0\,
CO(3) => \y_int_reg[19]_i_1_n_0\,
CO(2) => \y_int_reg[19]_i_1_n_1\,
CO(1) => \y_int_reg[19]_i_1_n_2\,
CO(0) => \y_int_reg[19]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[19]_i_2_n_0\,
DI(2) => \y_int[19]_i_3_n_0\,
DI(1) => \y_int[19]_i_4_n_0\,
DI(0) => \y_int[19]_i_5_n_0\,
O(3) => \y_int_reg[19]_i_1_n_4\,
O(2) => \y_int_reg[19]_i_1_n_5\,
O(1) => \y_int_reg[19]_i_1_n_6\,
O(0) => \y_int_reg[19]_i_1_n_7\,
S(3) => \y_int[19]_i_6_n_0\,
S(2) => \y_int[19]_i_7_n_0\,
S(1) => \y_int[19]_i_8_n_0\,
S(0) => \y_int[19]_i_9_n_0\
);
\y_int_reg[19]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_14_n_0\,
CO(3) => \y_int_reg[19]_i_14_n_0\,
CO(2) => \y_int_reg[19]_i_14_n_1\,
CO(1) => \y_int_reg[19]_i_14_n_2\,
CO(0) => \y_int_reg[19]_i_14_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(24 downto 21),
S(3) => \y_int[19]_i_25_n_0\,
S(2) => \y_int[19]_i_26_n_0\,
S(1) => \y_int[19]_i_27_n_0\,
S(0) => \y_int[19]_i_28_n_0\
);
\y_int_reg[19]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_15_n_0\,
CO(3) => \y_int_reg[19]_i_15_n_0\,
CO(2) => \y_int_reg[19]_i_15_n_1\,
CO(1) => \y_int_reg[19]_i_15_n_2\,
CO(0) => \y_int_reg[19]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(16 downto 13),
S(3) => \y_int[19]_i_29_n_0\,
S(2) => \y_int[19]_i_30_n_0\,
S(1) => \y_int[19]_i_31_n_0\,
S(0) => \y_int[19]_i_32_n_0\
);
\y_int_reg[19]_i_35\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_35_n_0\,
CO(3) => \y_int_reg[19]_i_35_n_0\,
CO(2) => \y_int_reg[19]_i_35_n_1\,
CO(1) => \y_int_reg[19]_i_35_n_2\,
CO(0) => \y_int_reg[19]_i_35_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^y_int_reg[19]_0\(3 downto 0),
S(3) => \y_int[19]_i_48_n_0\,
S(2) => \y_int[19]_i_49_n_0\,
S(1) => \y_int[19]_i_50_n_0\,
S(0) => \y_int[19]_i_51_n_0\
);
\y_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[3]_i_1_n_6\,
Q => \y_int_reg_n_0_[1]\,
R => '0'
);
\y_int_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[23]_i_1_n_7\,
Q => \y_int_reg__0\(20),
R => '0'
);
\y_int_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[23]_i_1_n_6\,
Q => \y_int_reg__0\(21),
R => '0'
);
\y_int_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[23]_i_1_n_5\,
Q => \y_int_reg__0\(22),
R => '0'
);
\y_int_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[23]_i_1_n_4\,
Q => \y_int_reg__0\(23),
R => '0'
);
\y_int_reg[23]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_1_n_0\,
CO(3) => \y_int_reg[23]_i_1_n_0\,
CO(2) => \y_int_reg[23]_i_1_n_1\,
CO(1) => \y_int_reg[23]_i_1_n_2\,
CO(0) => \y_int_reg[23]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[23]_i_2_n_0\,
DI(2) => \y_int[23]_i_3_n_0\,
DI(1) => \y_int[23]_i_4_n_0\,
DI(0) => \y_int[23]_i_5_n_0\,
O(3) => \y_int_reg[23]_i_1_n_4\,
O(2) => \y_int_reg[23]_i_1_n_5\,
O(1) => \y_int_reg[23]_i_1_n_6\,
O(0) => \y_int_reg[23]_i_1_n_7\,
S(3) => \y_int[23]_i_6_n_0\,
S(2) => \y_int[23]_i_7_n_0\,
S(1) => \y_int[23]_i_8_n_0\,
S(0) => \y_int[23]_i_9_n_0\
);
\y_int_reg[23]_i_10\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_25_n_0\,
CO(3) => y_int_reg6,
CO(2) => \y_int_reg[23]_i_10_n_1\,
CO(1) => \y_int_reg[23]_i_10_n_2\,
CO(0) => \y_int_reg[23]_i_10_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \y_int_reg[31]_i_8_n_5\,
DI(1) => \y_int_reg[31]_i_8_n_5\,
DI(0) => \y_int_reg[31]_i_8_n_5\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_10_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_26_n_0\,
S(2) => \y_int[23]_i_27_n_0\,
S(1) => \y_int[23]_i_28_n_0\,
S(0) => \y_int[23]_i_29_n_0\
);
\y_int_reg[23]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_16_n_0\,
CO(3 downto 1) => \NLW_y_int_reg[23]_i_11_CO_UNCONNECTED\(3 downto 1),
CO(0) => \y_int_reg[23]_i_11_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[23]_i_11_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => y_int_reg5(30 downto 29),
S(3 downto 2) => B"00",
S(1) => \y_int[23]_i_30_n_0\,
S(0) => \y_int[23]_i_31_n_0\
);
\y_int_reg[23]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_14_n_0\,
CO(3) => \y_int_reg[23]_i_16_n_0\,
CO(2) => \y_int_reg[23]_i_16_n_1\,
CO(1) => \y_int_reg[23]_i_16_n_2\,
CO(0) => \y_int_reg[23]_i_16_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(28 downto 25),
S(3) => \y_int[23]_i_36_n_0\,
S(2) => \y_int[23]_i_37_n_0\,
S(1) => \y_int[23]_i_38_n_0\,
S(0) => \y_int[23]_i_39_n_0\
);
\y_int_reg[23]_i_17\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_15_n_0\,
CO(3) => \y_int_reg[23]_i_17_n_0\,
CO(2) => \y_int_reg[23]_i_17_n_1\,
CO(1) => \y_int_reg[23]_i_17_n_2\,
CO(0) => \y_int_reg[23]_i_17_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(20 downto 17),
S(3) => \y_int[23]_i_40_n_0\,
S(2) => \y_int[23]_i_41_n_0\,
S(1) => \y_int[23]_i_42_n_0\,
S(0) => \y_int[23]_i_43_n_0\
);
\y_int_reg[23]_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_45_n_0\,
CO(3) => \y_int_reg[23]_i_25_n_0\,
CO(2) => \y_int_reg[23]_i_25_n_1\,
CO(1) => \y_int_reg[23]_i_25_n_2\,
CO(0) => \y_int_reg[23]_i_25_n_3\,
CYINIT => '0',
DI(3) => \y_int_reg[31]_i_8_n_5\,
DI(2) => \y_int_reg[31]_i_8_n_5\,
DI(1) => \y_int_reg[31]_i_8_n_5\,
DI(0) => \y_int_reg[31]_i_8_n_5\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_25_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_46_n_0\,
S(2) => \y_int[23]_i_47_n_0\,
S(1) => \y_int[23]_i_48_n_0\,
S(0) => \y_int[23]_i_49_n_0\
);
\y_int_reg[23]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_51_n_0\,
CO(3) => \^y_int_reg[3]_1\(0),
CO(2) => \y_int_reg[23]_i_33_n_1\,
CO(1) => \y_int_reg[23]_i_33_n_2\,
CO(0) => \y_int_reg[23]_i_33_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \rgb888[8]_21\(2),
DI(1) => \rgb888[8]_21\(2),
DI(0) => \rgb888[8]_21\(2),
O(3 downto 0) => \NLW_y_int_reg[23]_i_33_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_52_n_0\,
S(2) => \y_int[23]_i_53_n_0\,
S(1) => \y_int[23]_i_54_n_0\,
S(0) => \y_int[23]_i_55_n_0\
);
\y_int_reg[23]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_44_n_0\,
CO(3 downto 1) => \NLW_y_int_reg[23]_i_34_CO_UNCONNECTED\(3 downto 1),
CO(0) => \y_int_reg[23]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[23]_i_34_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => \^y_int_reg[23]_1\(1 downto 0),
S(3 downto 2) => B"00",
S(1) => \y_int[23]_i_56_n_0\,
S(0) => \y_int[23]_i_57_n_0\
);
\y_int_reg[23]_i_44\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_35_n_0\,
CO(3) => \y_int_reg[23]_i_44_n_0\,
CO(2) => \y_int_reg[23]_i_44_n_1\,
CO(1) => \y_int_reg[23]_i_44_n_2\,
CO(0) => \y_int_reg[23]_i_44_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^y_int_reg[23]_2\(3 downto 0),
S(3) => \y_int[23]_i_62_n_0\,
S(2) => \y_int[23]_i_63_n_0\,
S(1) => \y_int[23]_i_64_n_0\,
S(0) => \y_int[23]_i_65_n_0\
);
\y_int_reg[23]_i_45\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_66_n_0\,
CO(3) => \y_int_reg[23]_i_45_n_0\,
CO(2) => \y_int_reg[23]_i_45_n_1\,
CO(1) => \y_int_reg[23]_i_45_n_2\,
CO(0) => \y_int_reg[23]_i_45_n_3\,
CYINIT => '0',
DI(3) => \y_int[23]_i_67_n_0\,
DI(2) => \y_int[23]_i_68_n_0\,
DI(1) => \y_int[23]_i_69_n_0\,
DI(0) => \y_int[23]_i_70_n_0\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_45_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_71_n_0\,
S(2) => \y_int[23]_i_72_n_0\,
S(1) => \y_int[23]_i_73_n_0\,
S(0) => \y_int[23]_i_74_n_0\
);
\y_int_reg[23]_i_51\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_75_n_0\,
CO(3) => \y_int_reg[23]_i_51_n_0\,
CO(2) => \y_int_reg[23]_i_51_n_1\,
CO(1) => \y_int_reg[23]_i_51_n_2\,
CO(0) => \y_int_reg[23]_i_51_n_3\,
CYINIT => '0',
DI(3) => \rgb888[8]_21\(2),
DI(2) => \rgb888[8]_21\(2),
DI(1) => \rgb888[8]_21\(2),
DI(0) => \y_int[23]_i_76_n_0\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_51_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_77_n_0\,
S(2) => \y_int[23]_i_78_n_0\,
S(1) => \y_int[23]_i_79_n_0\,
S(0) => \y_int[23]_i_80_n_0\
);
\y_int_reg[23]_i_66\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[23]_i_66_n_0\,
CO(2) => \y_int_reg[23]_i_66_n_1\,
CO(1) => \y_int_reg[23]_i_66_n_2\,
CO(0) => \y_int_reg[23]_i_66_n_3\,
CYINIT => '1',
DI(3) => \y_int[23]_i_81_n_0\,
DI(2) => \y_int[23]_i_82_n_0\,
DI(1) => \y_int[23]_i_83_n_0\,
DI(0) => \y_int[23]_i_84_n_0\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_66_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_85_n_0\,
S(2) => \y_int[23]_i_86_n_0\,
S(1) => \y_int[23]_i_87_n_0\,
S(0) => \y_int[23]_i_88_n_0\
);
\y_int_reg[23]_i_75\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_89_n_0\,
CO(3) => \y_int_reg[23]_i_75_n_0\,
CO(2) => \y_int_reg[23]_i_75_n_1\,
CO(1) => \y_int_reg[23]_i_75_n_2\,
CO(0) => \y_int_reg[23]_i_75_n_3\,
CYINIT => '0',
DI(3) => \y_int[23]_i_90_n_0\,
DI(2) => \y_int[23]_i_91_n_0\,
DI(1) => \y_int[23]_i_92_n_0\,
DI(0) => \y_int[23]_i_93_n_0\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_75_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_94_n_0\,
S(2) => \y_int[23]_i_95_n_0\,
S(1) => \y_int[23]_i_96_n_0\,
S(0) => \y_int[23]_i_97_n_0\
);
\y_int_reg[23]_i_89\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[23]_i_89_n_0\,
CO(2) => \y_int_reg[23]_i_89_n_1\,
CO(1) => \y_int_reg[23]_i_89_n_2\,
CO(0) => \y_int_reg[23]_i_89_n_3\,
CYINIT => '1',
DI(3) => \y_int[23]_i_98_n_0\,
DI(2) => \y_int[23]_i_99_n_0\,
DI(1) => \y_int[23]_i_100_n_0\,
DI(0) => rgb888(8),
O(3 downto 0) => \NLW_y_int_reg[23]_i_89_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_101_n_0\,
S(2) => \y_int[23]_i_102_n_0\,
S(1) => \y_int[23]_i_103_n_0\,
S(0) => \y_int[23]_i_104_n_0\
);
\y_int_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[27]_i_1_n_7\,
Q => \y_int_reg__0\(24),
R => '0'
);
\y_int_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[27]_i_1_n_6\,
Q => \y_int_reg__0\(25),
R => '0'
);
\y_int_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[27]_i_1_n_5\,
Q => \y_int_reg__0\(26),
R => '0'
);
\y_int_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[27]_i_1_n_4\,
Q => \y_int_reg__0\(27),
R => '0'
);
\y_int_reg[27]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_1_n_0\,
CO(3) => \y_int_reg[27]_i_1_n_0\,
CO(2) => \y_int_reg[27]_i_1_n_1\,
CO(1) => \y_int_reg[27]_i_1_n_2\,
CO(0) => \y_int_reg[27]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_2_n_0\,
DI(2) => \y_int[31]_i_2_n_0\,
DI(1) => \y_int[31]_i_2_n_0\,
DI(0) => \y_int[31]_i_2_n_0\,
O(3) => \y_int_reg[27]_i_1_n_4\,
O(2) => \y_int_reg[27]_i_1_n_5\,
O(1) => \y_int_reg[27]_i_1_n_6\,
O(0) => \y_int_reg[27]_i_1_n_7\,
S(3) => \y_int[27]_i_2_n_0\,
S(2) => \y_int[27]_i_3_n_0\,
S(1) => \y_int[27]_i_4_n_0\,
S(0) => \y_int[27]_i_5_n_0\
);
\y_int_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[31]_i_1_n_7\,
Q => \y_int_reg__0\(28),
R => '0'
);
\y_int_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[31]_i_1_n_6\,
Q => \y_int_reg__0\(29),
R => '0'
);
\y_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[3]_i_1_n_5\,
Q => \y_int_reg_n_0_[2]\,
R => '0'
);
\y_int_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[31]_i_1_n_5\,
Q => \y_int_reg__0\(30),
R => '0'
);
\y_int_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[31]_i_1_n_4\,
Q => \y_int_reg__0\(31),
R => '0'
);
\y_int_reg[31]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[27]_i_1_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_1_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_1_n_1\,
CO(1) => \y_int_reg[31]_i_1_n_2\,
CO(0) => \y_int_reg[31]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \y_int[31]_i_2_n_0\,
DI(1) => \y_int[31]_i_2_n_0\,
DI(0) => \y_int[31]_i_2_n_0\,
O(3) => \y_int_reg[31]_i_1_n_4\,
O(2) => \y_int_reg[31]_i_1_n_5\,
O(1) => \y_int_reg[31]_i_1_n_6\,
O(0) => \y_int_reg[31]_i_1_n_7\,
S(3) => \y_int[31]_i_3_n_0\,
S(2) => \y_int[31]_i_4_n_0\,
S(1) => \y_int[31]_i_5_n_0\,
S(0) => \y_int[31]_i_6_n_0\
);
\y_int_reg[31]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_30_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_11_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_11_n_1\,
CO(1) => \y_int_reg[31]_i_11_n_2\,
CO(0) => \y_int_reg[31]_i_11_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \rgb888[0]_9\(1),
DI(0) => \y_int[31]_i_32_n_0\,
O(3) => \^y_int_reg[23]_0\(0),
O(2) => \y_int_reg[31]_i_11_n_5\,
O(1) => \y_int_reg[31]_i_11_n_6\,
O(0) => \y_int_reg[31]_i_11_n_7\,
S(3) => \y_int[31]_i_33_n_0\,
S(2) => \y_int[31]_i_34_n_0\,
S(1) => \y_int[31]_i_35_n_0\,
S(0) => \y_int[31]_i_36_n_0\
);
\y_int_reg[31]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_16_n_0\,
CO(3) => \y_int_reg[31]_i_16_n_0\,
CO(2) => \y_int_reg[31]_i_16_n_1\,
CO(1) => \y_int_reg[31]_i_16_n_2\,
CO(0) => \y_int_reg[31]_i_16_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_40_n_0\,
DI(2) => \y_int[31]_i_41_n_0\,
DI(1) => \y_int[31]_i_42_n_0\,
DI(0) => \y_int[31]_i_43_n_0\,
O(3) => \y_int_reg[31]_i_16_n_4\,
O(2) => \y_int_reg[31]_i_16_n_5\,
O(1) => \y_int_reg[31]_i_16_n_6\,
O(0) => \y_int_reg[31]_i_16_n_7\,
S(3) => \y_int[31]_i_44_n_0\,
S(2) => \y_int[31]_i_45_n_0\,
S(1) => \y_int[31]_i_46_n_0\,
S(0) => \y_int[31]_i_47_n_0\
);
\y_int_reg[31]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_62_n_0\,
CO(3) => \y_int_reg[31]_i_30_n_0\,
CO(2) => \y_int_reg[31]_i_30_n_1\,
CO(1) => \y_int_reg[31]_i_30_n_2\,
CO(0) => \y_int_reg[31]_i_30_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_63_n_0\,
DI(2) => \y_int[31]_i_64_n_0\,
DI(1) => \y_int[31]_i_65_n_0\,
DI(0) => \y_int[31]_i_66_n_0\,
O(3) => \y_int_reg[31]_i_30_n_4\,
O(2) => \y_int_reg[31]_i_30_n_5\,
O(1) => \y_int_reg[31]_i_30_n_6\,
O(0) => \y_int_reg[31]_i_30_n_7\,
S(3) => \y_int[31]_i_67_n_0\,
S(2) => \y_int[31]_i_68_n_0\,
S(1) => \y_int[31]_i_69_n_0\,
S(0) => \y_int[31]_i_70_n_0\
);
\y_int_reg[31]_i_62\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[31]_i_62_n_0\,
CO(2) => \y_int_reg[31]_i_62_n_1\,
CO(1) => \y_int_reg[31]_i_62_n_2\,
CO(0) => \y_int_reg[31]_i_62_n_3\,
CYINIT => '0',
DI(3) => \y_int_reg[31]_i_86_n_5\,
DI(2) => \y_int_reg[31]_i_87_n_7\,
DI(1) => \y_int_reg[31]_i_88_n_4\,
DI(0) => \y_int_reg[31]_i_88_n_5\,
O(3) => \y_int_reg[31]_i_62_n_4\,
O(2) => \y_int_reg[31]_i_62_n_5\,
O(1) => \y_int_reg[31]_i_62_n_6\,
O(0) => \NLW_y_int_reg[31]_i_62_O_UNCONNECTED\(0),
S(3) => \y_int[31]_i_89_n_0\,
S(2) => \y_int[31]_i_90_n_0\,
S(1) => \y_int[31]_i_91_n_0\,
S(0) => \y_int[31]_i_92_n_0\
);
\y_int_reg[31]_i_7\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_17_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_7_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_7_n_1\,
CO(1) => \NLW_y_int_reg[31]_i_7_CO_UNCONNECTED\(1),
CO(0) => \y_int_reg[31]_i_7_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[31]_i_7_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => y_int_reg3(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_14_n_0\,
S(0) => \y_int[31]_i_15_n_0\
);
\y_int_reg[31]_i_75\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_87_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[31]_i_75_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[31]_i_75_n_2\,
CO(0) => \NLW_y_int_reg[31]_i_75_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(7),
O(3 downto 1) => \NLW_y_int_reg[31]_i_75_O_UNCONNECTED\(3 downto 1),
O(0) => \y_int_reg[31]_i_75_n_7\,
S(3 downto 1) => B"001",
S(0) => \y_int[31]_i_101_n_0\
);
\y_int_reg[31]_i_8\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_16_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[31]_i_8_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[31]_i_8_n_2\,
CO(0) => \y_int_reg[31]_i_8_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \y_int[31]_i_17_n_0\,
O(3) => \NLW_y_int_reg[31]_i_8_O_UNCONNECTED\(3),
O(2) => \y_int_reg[31]_i_8_n_5\,
O(1) => \y_int_reg[31]_i_8_n_6\,
O(0) => \y_int_reg[31]_i_8_n_7\,
S(3) => '0',
S(2) => \y_int[31]_i_18_n_0\,
S(1) => \y_int[31]_i_19_n_0\,
S(0) => \y_int[31]_i_20_n_0\
);
\y_int_reg[31]_i_86\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[23]_3\(0),
CO(2) => \y_int_reg[31]_i_86_n_1\,
CO(1) => \y_int_reg[31]_i_86_n_2\,
CO(0) => \y_int_reg[31]_i_86_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_104_n_0\,
DI(2) => rgb888(2),
DI(1 downto 0) => B"01",
O(3) => \y_int_reg[31]_i_86_n_4\,
O(2) => \y_int_reg[31]_i_86_n_5\,
O(1) => \y_int_reg[31]_i_86_n_6\,
O(0) => \NLW_y_int_reg[31]_i_86_O_UNCONNECTED\(0),
S(3) => \y_int[31]_i_105_n_0\,
S(2) => \y_int[31]_i_106_n_0\,
S(1) => \y_int[31]_i_107_n_0\,
S(0) => \y_int[31]_i_108_n_0\
);
\y_int_reg[31]_i_87\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_88_n_0\,
CO(3) => \y_int_reg[31]_i_87_n_0\,
CO(2) => \y_int_reg[31]_i_87_n_1\,
CO(1) => \y_int_reg[31]_i_87_n_2\,
CO(0) => \y_int_reg[31]_i_87_n_3\,
CYINIT => '0',
DI(3) => rgb888(6),
DI(2 downto 0) => rgb888(7 downto 5),
O(3) => \y_int_reg[31]_i_87_n_4\,
O(2) => \y_int_reg[31]_i_87_n_5\,
O(1) => \y_int_reg[31]_i_87_n_6\,
O(0) => \y_int_reg[31]_i_87_n_7\,
S(3) => \y_int[31]_i_109_n_0\,
S(2) => \y_int[31]_i_110_n_0\,
S(1) => \y_int[31]_i_111_n_0\,
S(0) => \y_int[31]_i_112_n_0\
);
\y_int_reg[31]_i_88\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[31]_i_88_n_0\,
CO(2) => \y_int_reg[31]_i_88_n_1\,
CO(1) => \y_int_reg[31]_i_88_n_2\,
CO(0) => \y_int_reg[31]_i_88_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(4 downto 2),
DI(0) => '0',
O(3) => \y_int_reg[31]_i_88_n_4\,
O(2) => \y_int_reg[31]_i_88_n_5\,
O(1) => \y_int_reg[31]_i_88_n_6\,
O(0) => \NLW_y_int_reg[31]_i_88_O_UNCONNECTED\(0),
S(3) => \y_int[31]_i_113_n_0\,
S(2) => \y_int[31]_i_114_n_0\,
S(1) => \y_int[31]_i_115_n_0\,
S(0) => \y_int[31]_i_116_n_0\
);
\y_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[3]_i_1_n_4\,
Q => \y_int_reg_n_0_[3]\,
R => '0'
);
\y_int_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_1_n_0\,
CO(2) => \y_int_reg[3]_i_1_n_1\,
CO(1) => \y_int_reg[3]_i_1_n_2\,
CO(0) => \y_int_reg[3]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[3]_i_2_n_0\,
DI(2) => \y_int[3]_i_3_n_0\,
DI(1) => \y_int[3]_i_4_n_0\,
DI(0) => '0',
O(3) => \y_int_reg[3]_i_1_n_4\,
O(2) => \y_int_reg[3]_i_1_n_5\,
O(1) => \y_int_reg[3]_i_1_n_6\,
O(0) => \y_int_reg[3]_i_1_n_7\,
S(3) => \y_int[3]_i_5_n_0\,
S(2) => \y_int[3]_i_6_n_0\,
S(1) => \y_int[3]_i_7_n_0\,
S(0) => \y_int[3]_i_8_n_0\
);
\y_int_reg[3]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_21_n_0\,
CO(3) => \y_int_reg[3]_i_15_n_0\,
CO(2) => \y_int_reg[3]_i_15_n_1\,
CO(1) => \y_int_reg[3]_i_15_n_2\,
CO(0) => \y_int_reg[3]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => y_int_reg5(8),
O(2 downto 0) => \NLW_y_int_reg[3]_i_15_O_UNCONNECTED\(2 downto 0),
S(3) => \y_int[3]_i_22_n_0\,
S(2) => \y_int[3]_i_23_n_0\,
S(1) => \y_int[3]_i_24_n_0\,
S(0) => \y_int[3]_i_25_n_0\
);
\y_int_reg[3]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_26_n_0\,
CO(3) => \y_int_reg[3]_i_16_n_0\,
CO(2) => \y_int_reg[3]_i_16_n_1\,
CO(1) => \y_int_reg[3]_i_16_n_2\,
CO(0) => \y_int_reg[3]_i_16_n_3\,
CYINIT => '0',
DI(3) => \y_int[3]_i_27_n_0\,
DI(2) => \y_int[3]_i_28_n_0\,
DI(1) => \y_int[3]_i_29_n_0\,
DI(0) => \y_int_reg[3]_i_30_n_6\,
O(3) => \y_int_reg[3]_i_16_n_4\,
O(2) => \y_int_reg[3]_i_16_n_5\,
O(1) => \y_int_reg[3]_i_16_n_6\,
O(0) => \y_int_reg[3]_i_16_n_7\,
S(3) => \y_int[3]_i_31_n_0\,
S(2) => \y_int[3]_i_32_n_0\,
S(1) => \y_int[3]_i_33_n_0\,
S(0) => \y_int[3]_i_34_n_0\
);
\y_int_reg[3]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_21_n_0\,
CO(2) => \y_int_reg[3]_i_21_n_1\,
CO(1) => \y_int_reg[3]_i_21_n_2\,
CO(0) => \y_int_reg[3]_i_21_n_3\,
CYINIT => \y_int[3]_i_50_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_y_int_reg[3]_i_21_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[3]_i_51_n_0\,
S(2) => \y_int[3]_i_52_n_0\,
S(1) => \y_int[3]_i_53_n_0\,
S(0) => \y_int[3]_i_54_n_0\
);
\y_int_reg[3]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_26_n_0\,
CO(2) => \y_int_reg[3]_i_26_n_1\,
CO(1) => \y_int_reg[3]_i_26_n_2\,
CO(0) => \y_int_reg[3]_i_26_n_3\,
CYINIT => '0',
DI(3) => \y_int_reg[3]_i_30_n_7\,
DI(2) => \y_int_reg[3]_i_55_n_4\,
DI(1) => \y_int_reg[3]_i_55_n_5\,
DI(0) => '0',
O(3) => \y_int_reg[3]_i_26_n_4\,
O(2) => \y_int_reg[3]_i_26_n_5\,
O(1) => \y_int_reg[3]_i_26_n_6\,
O(0) => \y_int_reg[3]_i_26_n_7\,
S(3) => \y_int[3]_i_56_n_0\,
S(2) => \y_int[3]_i_57_n_0\,
S(1) => \y_int[3]_i_58_n_0\,
S(0) => \y_int[3]_i_59_n_0\
);
\y_int_reg[3]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_55_n_0\,
CO(3) => \y_int_reg[3]_i_30_n_0\,
CO(2) => \y_int_reg[3]_i_30_n_1\,
CO(1) => \y_int_reg[3]_i_30_n_2\,
CO(0) => \y_int_reg[3]_i_30_n_3\,
CYINIT => '0',
DI(3) => rgb888(22),
DI(2 downto 0) => rgb888(23 downto 21),
O(3) => \y_int_reg[3]_i_30_n_4\,
O(2) => \y_int_reg[3]_i_30_n_5\,
O(1) => \y_int_reg[3]_i_30_n_6\,
O(0) => \y_int_reg[3]_i_30_n_7\,
S(3) => \y_int[3]_i_60_n_0\,
S(2) => \y_int[3]_i_61_n_0\,
S(1) => \y_int[3]_i_62_n_0\,
S(0) => \y_int[3]_i_63_n_0\
);
\y_int_reg[3]_i_35\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_65_n_0\,
CO(3) => \y_int_reg[3]_i_35_n_0\,
CO(2) => \y_int_reg[3]_i_35_n_1\,
CO(1) => \y_int_reg[3]_i_35_n_2\,
CO(0) => \y_int_reg[3]_i_35_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[3]_i_35_n_4\,
O(2 downto 0) => \NLW_y_int_reg[3]_i_35_O_UNCONNECTED\(2 downto 0),
S(3) => \y_int[3]_i_66_n_0\,
S(2) => \y_int[3]_i_67_n_0\,
S(1) => \y_int[3]_i_68_n_0\,
S(0) => \y_int[3]_i_69_n_0\
);
\y_int_reg[3]_i_36\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_2\(0),
CO(2) => \y_int_reg[3]_i_36_n_1\,
CO(1) => \y_int_reg[3]_i_36_n_2\,
CO(0) => \y_int_reg[3]_i_36_n_3\,
CYINIT => '0',
DI(3 downto 2) => \rgb888[8]_32\(1 downto 0),
DI(1) => \rgb888[8]_19\(2),
DI(0) => '0',
O(3 downto 0) => \^y_int_reg[3]_0\(3 downto 0),
S(3) => \y_int[3]_i_71_n_0\,
S(2) => \y_int[3]_i_72_n_0\,
S(1) => \y_int[3]_i_73_n_0\,
S(0) => \y_int[3]_i_74_n_0\
);
\y_int_reg[3]_i_55\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_55_n_0\,
CO(2) => \y_int_reg[3]_i_55_n_1\,
CO(1) => \y_int_reg[3]_i_55_n_2\,
CO(0) => \y_int_reg[3]_i_55_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(20 downto 18),
DI(0) => '0',
O(3) => \y_int_reg[3]_i_55_n_4\,
O(2) => \y_int_reg[3]_i_55_n_5\,
O(1) => \y_int_reg[3]_i_55_n_6\,
O(0) => \NLW_y_int_reg[3]_i_55_O_UNCONNECTED\(0),
S(3) => \y_int[3]_i_84_n_0\,
S(2) => \y_int[3]_i_85_n_0\,
S(1) => \y_int[3]_i_86_n_0\,
S(0) => \y_int[3]_i_87_n_0\
);
\y_int_reg[3]_i_64\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_30_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[3]_i_64_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[3]_i_64_n_2\,
CO(0) => \NLW_y_int_reg[3]_i_64_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(23),
O(3 downto 1) => \NLW_y_int_reg[3]_i_64_O_UNCONNECTED\(3 downto 1),
O(0) => \y_int_reg[3]_i_64_n_7\,
S(3 downto 1) => B"001",
S(0) => \y_int[3]_i_88_n_0\
);
\y_int_reg[3]_i_65\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_65_n_0\,
CO(2) => \y_int_reg[3]_i_65_n_1\,
CO(1) => \y_int_reg[3]_i_65_n_2\,
CO(0) => \y_int_reg[3]_i_65_n_3\,
CYINIT => \cr_int[3]_i_80_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_y_int_reg[3]_i_65_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[3]_i_89_n_0\,
S(2) => \y_int[3]_i_90_n_0\,
S(1) => \y_int[3]_i_91_n_0\,
S(0) => \y_int[3]_i_92_n_0\
);
\y_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[7]_i_1_n_7\,
Q => \y_int_reg_n_0_[4]\,
R => '0'
);
\y_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[7]_i_1_n_6\,
Q => \y_int_reg_n_0_[5]\,
R => '0'
);
\y_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[7]_i_1_n_5\,
Q => \y_int_reg_n_0_[6]\,
R => '0'
);
\y_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[7]_i_1_n_4\,
Q => \y_int_reg_n_0_[7]\,
R => '0'
);
\y_int_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_1_n_0\,
CO(3) => \y_int_reg[7]_i_1_n_0\,
CO(2) => \y_int_reg[7]_i_1_n_1\,
CO(1) => \y_int_reg[7]_i_1_n_2\,
CO(0) => \y_int_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[7]_i_2_n_0\,
DI(2) => \y_int[7]_i_3_n_0\,
DI(1) => \y_int[7]_i_4_n_0\,
DI(0) => \y_int[7]_i_5_n_0\,
O(3) => \y_int_reg[7]_i_1_n_4\,
O(2) => \y_int_reg[7]_i_1_n_5\,
O(1) => \y_int_reg[7]_i_1_n_6\,
O(0) => \y_int_reg[7]_i_1_n_7\,
S(3) => \y_int[7]_i_6_n_0\,
S(2) => \y_int[7]_i_7_n_0\,
S(1) => \y_int[7]_i_8_n_0\,
S(0) => \y_int[7]_i_9_n_0\
);
\y_int_reg[7]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[7]_i_24_n_0\,
CO(2) => \y_int_reg[7]_i_24_n_1\,
CO(1) => \y_int_reg[7]_i_24_n_2\,
CO(0) => \y_int_reg[7]_i_24_n_3\,
CYINIT => \y_int[7]_i_29_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[7]_i_24_n_4\,
O(2) => \y_int_reg[7]_i_24_n_5\,
O(1) => \y_int_reg[7]_i_24_n_6\,
O(0) => \y_int_reg[7]_i_24_n_7\,
S(3) => \y_int[7]_i_30_n_0\,
S(2) => \y_int[7]_i_31_n_0\,
S(1) => \y_int[7]_i_32_n_0\,
S(0) => \y_int[7]_i_33_n_0\
);
\y_int_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[11]_i_1_n_7\,
Q => \y_int_reg__0\(8),
R => '0'
);
\y_int_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[11]_i_1_n_6\,
Q => \y_int_reg__0\(9),
R => '0'
);
\y_reg[0]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[0]_i_1_n_0\,
Q => y(0),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[1]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[1]_i_1_n_0\,
Q => y(1),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[2]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[2]_i_1_n_0\,
Q => y(2),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[3]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[3]_i_1_n_0\,
Q => y(3),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[4]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[4]_i_1_n_0\,
Q => y(4),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[5]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[5]_i_1_n_0\,
Q => y(5),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[6]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[6]_i_1_n_0\,
Q => y(6),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[7]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[7]_i_2_n_0\,
Q => y(7),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_reg[7]_i_3_n_0\,
CO(3) => \y_reg[7]_i_1_n_0\,
CO(2) => \y_reg[7]_i_1_n_1\,
CO(1) => \y_reg[7]_i_1_n_2\,
CO(0) => \y_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y[7]_i_4_n_0\,
DI(2) => \y[7]_i_5_n_0\,
DI(1) => \y[7]_i_6_n_0\,
DI(0) => \y[7]_i_7_n_0\,
O(3 downto 0) => \NLW_y_reg[7]_i_1_O_UNCONNECTED\(3 downto 0),
S(3) => \y[7]_i_8_n_0\,
S(2) => \y[7]_i_9_n_0\,
S(1) => \y[7]_i_10_n_0\,
S(0) => \y[7]_i_11_n_0\
);
\y_reg[7]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_reg[7]_i_12_n_0\,
CO(2) => \y_reg[7]_i_12_n_1\,
CO(1) => \y_reg[7]_i_12_n_2\,
CO(0) => \y_reg[7]_i_12_n_3\,
CYINIT => '0',
DI(3) => \y[7]_i_21_n_0\,
DI(2) => \y[7]_i_22_n_0\,
DI(1) => \y[7]_i_23_n_0\,
DI(0) => \y[7]_i_24_n_0\,
O(3 downto 0) => \NLW_y_reg[7]_i_12_O_UNCONNECTED\(3 downto 0),
S(3) => \y[7]_i_25_n_0\,
S(2) => \y[7]_i_26_n_0\,
S(1) => \y[7]_i_27_n_0\,
S(0) => \y[7]_i_28_n_0\
);
\y_reg[7]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \y_reg[7]_i_12_n_0\,
CO(3) => \y_reg[7]_i_3_n_0\,
CO(2) => \y_reg[7]_i_3_n_1\,
CO(1) => \y_reg[7]_i_3_n_2\,
CO(0) => \y_reg[7]_i_3_n_3\,
CYINIT => '0',
DI(3) => \y[7]_i_13_n_0\,
DI(2) => \y[7]_i_14_n_0\,
DI(1) => \y[7]_i_15_n_0\,
DI(0) => \y[7]_i_16_n_0\,
O(3 downto 0) => \NLW_y_reg[7]_i_3_O_UNCONNECTED\(3 downto 0),
S(3) => \y[7]_i_17_n_0\,
S(2) => \y[7]_i_18_n_0\,
S(1) => \y[7]_i_19_n_0\,
S(0) => \y[7]_i_20_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zed_hdmi_0_0 is
port (
clk : in STD_LOGIC;
clk_x2 : in STD_LOGIC;
clk_100 : in STD_LOGIC;
active : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_zed_hdmi_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_zed_hdmi_0_0 : entity is "system_zed_hdmi_0_0,zed_hdmi,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_zed_hdmi_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_zed_hdmi_0_0 : entity is "zed_hdmi,Vivado 2016.4";
end system_zed_hdmi_0_0;
architecture STRUCTURE of system_zed_hdmi_0_0 is
signal \<const0>\ : STD_LOGIC;
signal U0_n_10 : STD_LOGIC;
signal U0_n_11 : STD_LOGIC;
signal U0_n_12 : STD_LOGIC;
signal U0_n_13 : STD_LOGIC;
signal U0_n_14 : STD_LOGIC;
signal U0_n_15 : STD_LOGIC;
signal U0_n_16 : STD_LOGIC;
signal U0_n_17 : STD_LOGIC;
signal U0_n_18 : STD_LOGIC;
signal U0_n_19 : STD_LOGIC;
signal U0_n_20 : STD_LOGIC;
signal U0_n_21 : STD_LOGIC;
signal U0_n_22 : STD_LOGIC;
signal U0_n_23 : STD_LOGIC;
signal U0_n_24 : STD_LOGIC;
signal U0_n_25 : STD_LOGIC;
signal U0_n_26 : STD_LOGIC;
signal U0_n_27 : STD_LOGIC;
signal U0_n_28 : STD_LOGIC;
signal U0_n_29 : STD_LOGIC;
signal U0_n_30 : STD_LOGIC;
signal U0_n_31 : STD_LOGIC;
signal U0_n_32 : STD_LOGIC;
signal U0_n_33 : STD_LOGIC;
signal U0_n_34 : STD_LOGIC;
signal U0_n_35 : STD_LOGIC;
signal U0_n_36 : STD_LOGIC;
signal U0_n_37 : STD_LOGIC;
signal U0_n_38 : STD_LOGIC;
signal U0_n_39 : STD_LOGIC;
signal U0_n_4 : STD_LOGIC;
signal U0_n_40 : STD_LOGIC;
signal U0_n_41 : STD_LOGIC;
signal U0_n_42 : STD_LOGIC;
signal U0_n_43 : STD_LOGIC;
signal U0_n_44 : STD_LOGIC;
signal U0_n_45 : STD_LOGIC;
signal U0_n_46 : STD_LOGIC;
signal U0_n_47 : STD_LOGIC;
signal U0_n_48 : STD_LOGIC;
signal U0_n_49 : STD_LOGIC;
signal U0_n_5 : STD_LOGIC;
signal U0_n_50 : STD_LOGIC;
signal U0_n_51 : STD_LOGIC;
signal U0_n_52 : STD_LOGIC;
signal U0_n_53 : STD_LOGIC;
signal U0_n_54 : STD_LOGIC;
signal U0_n_55 : STD_LOGIC;
signal U0_n_56 : STD_LOGIC;
signal U0_n_57 : STD_LOGIC;
signal U0_n_58 : STD_LOGIC;
signal U0_n_59 : STD_LOGIC;
signal U0_n_6 : STD_LOGIC;
signal U0_n_60 : STD_LOGIC;
signal U0_n_61 : STD_LOGIC;
signal U0_n_62 : STD_LOGIC;
signal U0_n_63 : STD_LOGIC;
signal U0_n_64 : STD_LOGIC;
signal U0_n_65 : STD_LOGIC;
signal U0_n_66 : STD_LOGIC;
signal U0_n_67 : STD_LOGIC;
signal U0_n_68 : STD_LOGIC;
signal U0_n_69 : STD_LOGIC;
signal U0_n_7 : STD_LOGIC;
signal U0_n_70 : STD_LOGIC;
signal U0_n_71 : STD_LOGIC;
signal U0_n_72 : STD_LOGIC;
signal U0_n_73 : STD_LOGIC;
signal U0_n_74 : STD_LOGIC;
signal U0_n_75 : STD_LOGIC;
signal U0_n_76 : STD_LOGIC;
signal U0_n_77 : STD_LOGIC;
signal U0_n_78 : STD_LOGIC;
signal U0_n_79 : STD_LOGIC;
signal U0_n_8 : STD_LOGIC;
signal U0_n_80 : STD_LOGIC;
signal U0_n_81 : STD_LOGIC;
signal U0_n_9 : STD_LOGIC;
signal \cb_int[15]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_48_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_43_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_44_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_33_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_34_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_100_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_101_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_19_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_20_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_21_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_25_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_26_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_28_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_48_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_52_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_53_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_54_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_55_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_56_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_57_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_58_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_59_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_60_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_62_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_63_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_64_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_65_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_83_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_84_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_88_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_89_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_90_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_91_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_92_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_93_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_94_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_99_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_59_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_60_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_61_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_62_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_73_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_74_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_84_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_85_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_86_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_87_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_88_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_95_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_96_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_97_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_98_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_32_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_33_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_34_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_43_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_44_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_48_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_51_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_4\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_5\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_6\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_7\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_4\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_5\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_6\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_7\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_4\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_5\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_6\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_7\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_4\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_5\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_6\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_7\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_4\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_5\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_6\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_7\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_0\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_1\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_2\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_3\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_4\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_5\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_6\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_7\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_0\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_1\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_2\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_3\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_4\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_5\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_6\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_10_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_10_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_10_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_10_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_42_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_42_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_42_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_66_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_66_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_66_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_9_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_9_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_9_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_43_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_43_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_43_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_43_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_58_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_58_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_58_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_58_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_7\ : STD_LOGIC;
signal \cr_int[11]_i_61_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_62_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_63_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_64_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_46_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_47_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_52_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_53_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_54_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_55_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_42_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_104_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_105_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_106_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_107_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_28_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_65_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_66_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_67_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_68_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_98_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_99_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_33_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_7\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_4\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_5\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_6\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_7\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_4\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_5\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_6\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_7\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_3\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_4\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_5\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_6\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_7\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_0\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_1\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_2\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_3\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_4\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_5\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_6\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_10_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_10_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_10_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_10_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_54_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_54_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_54_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_7\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_0\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_1\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_2\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_3\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_4\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_5\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_6\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_7\ : STD_LOGIC;
signal \^hdmi_d\ : STD_LOGIC_VECTOR ( 15 downto 8 );
signal \y_int[11]_i_54_n_0\ : STD_LOGIC;
signal \y_int[11]_i_55_n_0\ : STD_LOGIC;
signal \y_int[11]_i_56_n_0\ : STD_LOGIC;
signal \y_int[11]_i_57_n_0\ : STD_LOGIC;
signal \y_int[15]_i_36_n_0\ : STD_LOGIC;
signal \y_int[15]_i_37_n_0\ : STD_LOGIC;
signal \y_int[15]_i_38_n_0\ : STD_LOGIC;
signal \y_int[15]_i_39_n_0\ : STD_LOGIC;
signal \y_int[15]_i_44_n_0\ : STD_LOGIC;
signal \y_int[15]_i_45_n_0\ : STD_LOGIC;
signal \y_int[15]_i_46_n_0\ : STD_LOGIC;
signal \y_int[15]_i_47_n_0\ : STD_LOGIC;
signal \y_int[19]_i_36_n_0\ : STD_LOGIC;
signal \y_int[19]_i_37_n_0\ : STD_LOGIC;
signal \y_int[19]_i_38_n_0\ : STD_LOGIC;
signal \y_int[19]_i_39_n_0\ : STD_LOGIC;
signal \y_int[19]_i_40_n_0\ : STD_LOGIC;
signal \y_int[19]_i_41_n_0\ : STD_LOGIC;
signal \y_int[19]_i_42_n_0\ : STD_LOGIC;
signal \y_int[19]_i_43_n_0\ : STD_LOGIC;
signal \y_int[19]_i_44_n_0\ : STD_LOGIC;
signal \y_int[19]_i_45_n_0\ : STD_LOGIC;
signal \y_int[19]_i_46_n_0\ : STD_LOGIC;
signal \y_int[19]_i_47_n_0\ : STD_LOGIC;
signal \y_int[23]_i_50_n_0\ : STD_LOGIC;
signal \y_int[23]_i_58_n_0\ : STD_LOGIC;
signal \y_int[23]_i_59_n_0\ : STD_LOGIC;
signal \y_int[23]_i_60_n_0\ : STD_LOGIC;
signal \y_int[23]_i_61_n_0\ : STD_LOGIC;
signal \y_int[31]_i_100_n_0\ : STD_LOGIC;
signal \y_int[31]_i_102_n_0\ : STD_LOGIC;
signal \y_int[31]_i_103_n_0\ : STD_LOGIC;
signal \y_int[31]_i_22_n_0\ : STD_LOGIC;
signal \y_int[31]_i_23_n_0\ : STD_LOGIC;
signal \y_int[31]_i_24_n_0\ : STD_LOGIC;
signal \y_int[31]_i_25_n_0\ : STD_LOGIC;
signal \y_int[31]_i_26_n_0\ : STD_LOGIC;
signal \y_int[31]_i_28_n_0\ : STD_LOGIC;
signal \y_int[31]_i_29_n_0\ : STD_LOGIC;
signal \y_int[31]_i_38_n_0\ : STD_LOGIC;
signal \y_int[31]_i_39_n_0\ : STD_LOGIC;
signal \y_int[31]_i_48_n_0\ : STD_LOGIC;
signal \y_int[31]_i_49_n_0\ : STD_LOGIC;
signal \y_int[31]_i_50_n_0\ : STD_LOGIC;
signal \y_int[31]_i_51_n_0\ : STD_LOGIC;
signal \y_int[31]_i_52_n_0\ : STD_LOGIC;
signal \y_int[31]_i_53_n_0\ : STD_LOGIC;
signal \y_int[31]_i_54_n_0\ : STD_LOGIC;
signal \y_int[31]_i_55_n_0\ : STD_LOGIC;
signal \y_int[31]_i_56_n_0\ : STD_LOGIC;
signal \y_int[31]_i_57_n_0\ : STD_LOGIC;
signal \y_int[31]_i_58_n_0\ : STD_LOGIC;
signal \y_int[31]_i_59_n_0\ : STD_LOGIC;
signal \y_int[31]_i_60_n_0\ : STD_LOGIC;
signal \y_int[31]_i_61_n_0\ : STD_LOGIC;
signal \y_int[31]_i_72_n_0\ : STD_LOGIC;
signal \y_int[31]_i_73_n_0\ : STD_LOGIC;
signal \y_int[31]_i_74_n_0\ : STD_LOGIC;
signal \y_int[31]_i_76_n_0\ : STD_LOGIC;
signal \y_int[31]_i_77_n_0\ : STD_LOGIC;
signal \y_int[31]_i_78_n_0\ : STD_LOGIC;
signal \y_int[31]_i_79_n_0\ : STD_LOGIC;
signal \y_int[31]_i_80_n_0\ : STD_LOGIC;
signal \y_int[31]_i_81_n_0\ : STD_LOGIC;
signal \y_int[31]_i_83_n_0\ : STD_LOGIC;
signal \y_int[31]_i_84_n_0\ : STD_LOGIC;
signal \y_int[31]_i_85_n_0\ : STD_LOGIC;
signal \y_int[31]_i_93_n_0\ : STD_LOGIC;
signal \y_int[31]_i_94_n_0\ : STD_LOGIC;
signal \y_int[31]_i_95_n_0\ : STD_LOGIC;
signal \y_int[31]_i_96_n_0\ : STD_LOGIC;
signal \y_int[31]_i_97_n_0\ : STD_LOGIC;
signal \y_int[31]_i_98_n_0\ : STD_LOGIC;
signal \y_int[31]_i_99_n_0\ : STD_LOGIC;
signal \y_int[3]_i_37_n_0\ : STD_LOGIC;
signal \y_int[3]_i_38_n_0\ : STD_LOGIC;
signal \y_int[3]_i_39_n_0\ : STD_LOGIC;
signal \y_int[3]_i_41_n_0\ : STD_LOGIC;
signal \y_int[3]_i_42_n_0\ : STD_LOGIC;
signal \y_int[3]_i_43_n_0\ : STD_LOGIC;
signal \y_int[3]_i_44_n_0\ : STD_LOGIC;
signal \y_int[3]_i_46_n_0\ : STD_LOGIC;
signal \y_int[3]_i_47_n_0\ : STD_LOGIC;
signal \y_int[3]_i_48_n_0\ : STD_LOGIC;
signal \y_int[3]_i_49_n_0\ : STD_LOGIC;
signal \y_int[3]_i_75_n_0\ : STD_LOGIC;
signal \y_int[3]_i_76_n_0\ : STD_LOGIC;
signal \y_int[3]_i_77_n_0\ : STD_LOGIC;
signal \y_int[3]_i_78_n_0\ : STD_LOGIC;
signal \y_int[3]_i_79_n_0\ : STD_LOGIC;
signal \y_int[3]_i_80_n_0\ : STD_LOGIC;
signal \y_int[3]_i_81_n_0\ : STD_LOGIC;
signal \y_int[3]_i_82_n_0\ : STD_LOGIC;
signal \y_int[3]_i_83_n_0\ : STD_LOGIC;
signal \y_int[3]_i_93_n_0\ : STD_LOGIC;
signal \y_int[3]_i_94_n_0\ : STD_LOGIC;
signal \y_int[3]_i_95_n_0\ : STD_LOGIC;
signal \y_int[3]_i_96_n_0\ : STD_LOGIC;
signal \y_int[7]_i_25_n_0\ : STD_LOGIC;
signal \y_int[7]_i_26_n_0\ : STD_LOGIC;
signal \y_int[7]_i_27_n_0\ : STD_LOGIC;
signal \y_int[7]_i_28_n_0\ : STD_LOGIC;
signal y_int_reg2 : STD_LOGIC_VECTOR ( 22 downto 9 );
signal \y_int_reg[11]_i_27_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_7\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_4\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_5\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_6\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_7\ : STD_LOGIC;
signal \y_int_reg[15]_i_34_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_34_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_34_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_34_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_4\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_5\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_6\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_7\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_4\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_5\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_6\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_7\ : STD_LOGIC;
signal \y_int_reg[19]_i_34_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_34_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_34_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_34_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_32_n_7\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_4\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_5\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_6\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_10_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_10_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_10_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_10_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_12_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_12_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_37_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_37_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_37_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_37_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_82_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_82_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_82_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_82_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_45_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_45_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_45_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_45_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_6\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_0\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_1\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_2\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_3\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_4\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_5\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_6\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_7\ : STD_LOGIC;
signal \NLW_cb_int_reg[31]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_42_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_42_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_66_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[31]_i_85_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_cb_int_reg[31]_i_85_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[31]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[3]_i_32_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_cb_int_reg[3]_i_43_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[3]_i_43_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[3]_i_58_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[31]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_54_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_54_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[23]_i_32_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_32_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_12_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_31_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_31_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[31]_i_82_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_82_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[3]_i_20_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_y_int_reg[3]_i_45_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[3]_i_70_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute HLUTNM : string;
attribute HLUTNM of \cb_int[3]_i_35\ : label is "lutpair0";
attribute HLUTNM of \cb_int[3]_i_40\ : label is "lutpair0";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \y_int[31]_i_57\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \y_int[31]_i_80\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \y_int[31]_i_81\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \y_int[31]_i_84\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \y_int[31]_i_85\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \y_int[3]_i_79\ : label is "soft_lutpair38";
begin
hdmi_d(15 downto 8) <= \^hdmi_d\(15 downto 8);
hdmi_d(7) <= \<const0>\;
hdmi_d(6) <= \<const0>\;
hdmi_d(5) <= \<const0>\;
hdmi_d(4) <= \<const0>\;
hdmi_d(3) <= \<const0>\;
hdmi_d(2) <= \<const0>\;
hdmi_d(1) <= \<const0>\;
hdmi_d(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_zed_hdmi_0_0_zed_hdmi
port map (
CO(0) => U0_n_16,
DI(0) => U0_n_4,
O(1) => U0_n_7,
O(0) => U0_n_8,
active => active,
\cb_int_reg[15]_0\(0) => U0_n_76,
\cb_int_reg[27]_0\(0) => U0_n_75,
\cb_int_reg[3]_0\(3) => U0_n_9,
\cb_int_reg[3]_0\(2) => U0_n_10,
\cb_int_reg[3]_0\(1) => U0_n_11,
\cb_int_reg[3]_0\(0) => U0_n_12,
\cb_int_reg[3]_1\(0) => U0_n_72,
\cb_int_reg[3]_2\(0) => U0_n_73,
\cb_int_reg[3]_3\(0) => U0_n_74,
clk => clk,
clk_100 => clk_100,
clk_x2 => clk_x2,
\cr_int_reg[11]_0\(3) => U0_n_34,
\cr_int_reg[11]_0\(2) => U0_n_35,
\cr_int_reg[11]_0\(1) => U0_n_36,
\cr_int_reg[11]_0\(0) => U0_n_37,
\cr_int_reg[15]_0\(3) => U0_n_38,
\cr_int_reg[15]_0\(2) => U0_n_39,
\cr_int_reg[15]_0\(1) => U0_n_40,
\cr_int_reg[15]_0\(0) => U0_n_41,
\cr_int_reg[15]_1\(0) => U0_n_77,
\cr_int_reg[19]_0\(3) => U0_n_42,
\cr_int_reg[19]_0\(2) => U0_n_43,
\cr_int_reg[19]_0\(1) => U0_n_44,
\cr_int_reg[19]_0\(0) => U0_n_45,
\cr_int_reg[23]_0\(3) => U0_n_46,
\cr_int_reg[23]_0\(2) => U0_n_47,
\cr_int_reg[23]_0\(1) => U0_n_48,
\cr_int_reg[23]_0\(0) => U0_n_49,
\cr_int_reg[23]_1\(0) => U0_n_50,
\cr_int_reg[27]_0\ => U0_n_13,
\cr_int_reg[27]_1\(1) => U0_n_14,
\cr_int_reg[27]_1\(0) => U0_n_15,
\cr_int_reg[27]_2\(0) => U0_n_29,
\cr_int_reg[31]_0\ => U0_n_5,
\cr_int_reg[31]_1\ => U0_n_6,
\cr_int_reg[31]_2\(1) => U0_n_17,
\cr_int_reg[31]_2\(0) => U0_n_18,
\cr_int_reg[3]_0\(2) => U0_n_23,
\cr_int_reg[3]_0\(1) => U0_n_24,
\cr_int_reg[3]_0\(0) => U0_n_25,
\cr_int_reg[3]_1\(0) => U0_n_26,
\cr_int_reg[3]_2\(1) => U0_n_27,
\cr_int_reg[3]_2\(0) => U0_n_28,
\cr_int_reg[7]_0\(3) => U0_n_19,
\cr_int_reg[7]_0\(2) => U0_n_20,
\cr_int_reg[7]_0\(1) => U0_n_21,
\cr_int_reg[7]_0\(0) => U0_n_22,
\cr_int_reg[7]_1\(3) => U0_n_30,
\cr_int_reg[7]_1\(2) => U0_n_31,
\cr_int_reg[7]_1\(1) => U0_n_32,
\cr_int_reg[7]_1\(0) => U0_n_33,
hdmi_clk => hdmi_clk,
hdmi_d(7 downto 0) => \^hdmi_d\(15 downto 8),
hdmi_de => hdmi_de,
hdmi_hsync => hdmi_hsync,
hdmi_scl => hdmi_scl,
hdmi_sda => hdmi_sda,
hdmi_vsync => hdmi_vsync,
hsync => hsync,
rgb888(23 downto 0) => rgb888(23 downto 0),
\rgb888[0]\(3) => \cb_int_reg[31]_i_8_n_4\,
\rgb888[0]\(2) => \cb_int_reg[31]_i_8_n_5\,
\rgb888[0]\(1) => \cb_int_reg[31]_i_8_n_6\,
\rgb888[0]\(0) => \cb_int_reg[31]_i_8_n_7\,
\rgb888[0]_0\(3) => \cb_int_reg[31]_i_17_n_4\,
\rgb888[0]_0\(2) => \cb_int_reg[31]_i_17_n_5\,
\rgb888[0]_0\(1) => \cb_int_reg[31]_i_17_n_6\,
\rgb888[0]_0\(0) => \cb_int_reg[31]_i_17_n_7\,
\rgb888[0]_1\(1) => \cb_int_reg[31]_i_42_n_6\,
\rgb888[0]_1\(0) => \cb_int_reg[31]_i_42_n_7\,
\rgb888[0]_2\(3) => \cb_int_reg[23]_i_28_n_4\,
\rgb888[0]_2\(2) => \cb_int_reg[23]_i_28_n_5\,
\rgb888[0]_2\(1) => \cb_int_reg[23]_i_28_n_6\,
\rgb888[0]_2\(0) => \cb_int_reg[23]_i_28_n_7\,
\rgb888[0]_3\(3) => \cb_int_reg[19]_i_33_n_4\,
\rgb888[0]_3\(2) => \cb_int_reg[19]_i_33_n_5\,
\rgb888[0]_3\(1) => \cb_int_reg[19]_i_33_n_6\,
\rgb888[0]_3\(0) => \cb_int_reg[19]_i_33_n_7\,
\rgb888[0]_4\(3) => \cb_int_reg[15]_i_34_n_4\,
\rgb888[0]_4\(2) => \cb_int_reg[15]_i_34_n_5\,
\rgb888[0]_4\(1) => \cb_int_reg[15]_i_34_n_6\,
\rgb888[0]_4\(0) => \cb_int_reg[15]_i_34_n_7\,
\rgb888[0]_5\(3) => \cr_int_reg[23]_i_31_n_4\,
\rgb888[0]_5\(2) => \cr_int_reg[23]_i_31_n_5\,
\rgb888[0]_5\(1) => \cr_int_reg[23]_i_31_n_6\,
\rgb888[0]_5\(0) => \cr_int_reg[23]_i_31_n_7\,
\rgb888[0]_6\(1) => \cr_int_reg[31]_i_54_n_6\,
\rgb888[0]_6\(0) => \cr_int_reg[31]_i_54_n_7\,
\rgb888[0]_7\(3) => \y_int_reg[31]_i_71_n_4\,
\rgb888[0]_7\(2) => \y_int_reg[31]_i_71_n_5\,
\rgb888[0]_7\(1) => \y_int_reg[31]_i_71_n_6\,
\rgb888[0]_7\(0) => \y_int_reg[31]_i_71_n_7\,
\rgb888[0]_8\(1) => \cb_int_reg[3]_i_43_n_6\,
\rgb888[0]_8\(0) => \cb_int_reg[3]_i_43_n_7\,
\rgb888[0]_9\(2) => \y_int_reg[31]_i_31_n_5\,
\rgb888[0]_9\(1) => \y_int_reg[31]_i_31_n_6\,
\rgb888[0]_9\(0) => \y_int_reg[31]_i_31_n_7\,
\rgb888[12]\(3) => \cb_int_reg[7]_i_24_n_4\,
\rgb888[12]\(2) => \cb_int_reg[7]_i_24_n_5\,
\rgb888[12]\(1) => \cb_int_reg[7]_i_24_n_6\,
\rgb888[12]\(0) => \cb_int_reg[7]_i_24_n_7\,
\rgb888[12]_0\(3) => \cb_int_reg[15]_i_32_n_4\,
\rgb888[12]_0\(2) => \cb_int_reg[15]_i_32_n_5\,
\rgb888[12]_0\(1) => \cb_int_reg[15]_i_32_n_6\,
\rgb888[12]_0\(0) => \cb_int_reg[15]_i_32_n_7\,
\rgb888[13]\(0) => \cb_int_reg[3]_i_32_n_4\,
\rgb888[13]_0\(3) => \cb_int_reg[7]_i_27_n_4\,
\rgb888[13]_0\(2) => \cb_int_reg[7]_i_27_n_5\,
\rgb888[13]_0\(1) => \cb_int_reg[7]_i_27_n_6\,
\rgb888[13]_0\(0) => \cb_int_reg[7]_i_27_n_7\,
\rgb888[14]\(3) => \y_int_reg[3]_i_19_n_4\,
\rgb888[14]\(2) => \y_int_reg[3]_i_19_n_5\,
\rgb888[14]\(1) => \y_int_reg[3]_i_19_n_6\,
\rgb888[14]\(0) => \y_int_reg[3]_i_19_n_7\,
\rgb888[14]_0\(1) => \y_int_reg[3]_i_20_n_4\,
\rgb888[14]_0\(0) => \y_int_reg[3]_i_20_n_5\,
\rgb888[14]_1\(3) => \y_int_reg[7]_i_23_n_4\,
\rgb888[14]_1\(2) => \y_int_reg[7]_i_23_n_5\,
\rgb888[14]_1\(1) => \y_int_reg[7]_i_23_n_6\,
\rgb888[14]_1\(0) => \y_int_reg[7]_i_23_n_7\,
\rgb888[1]\(13 downto 0) => y_int_reg2(22 downto 9),
\rgb888[1]_0\(0) => \y_int_reg[31]_i_12_n_1\,
\rgb888[3]\(3) => \cr_int_reg[15]_i_39_n_4\,
\rgb888[3]\(2) => \cr_int_reg[15]_i_39_n_5\,
\rgb888[3]\(1) => \cr_int_reg[15]_i_39_n_6\,
\rgb888[3]\(0) => \cr_int_reg[15]_i_39_n_7\,
\rgb888[3]_0\(3) => \cr_int_reg[19]_i_37_n_4\,
\rgb888[3]_0\(2) => \cr_int_reg[19]_i_37_n_5\,
\rgb888[3]_0\(1) => \cr_int_reg[19]_i_37_n_6\,
\rgb888[3]_0\(0) => \cr_int_reg[19]_i_37_n_7\,
\rgb888[8]\(3) => \cb_int_reg[3]_i_19_n_4\,
\rgb888[8]\(2) => \cb_int_reg[3]_i_19_n_5\,
\rgb888[8]\(1) => \cb_int_reg[3]_i_19_n_6\,
\rgb888[8]\(0) => \cb_int_reg[3]_i_19_n_7\,
\rgb888[8]_0\(3) => \cb_int_reg[31]_i_23_n_4\,
\rgb888[8]_0\(2) => \cb_int_reg[31]_i_23_n_5\,
\rgb888[8]_0\(1) => \cb_int_reg[31]_i_23_n_6\,
\rgb888[8]_0\(0) => \cb_int_reg[31]_i_23_n_7\,
\rgb888[8]_1\(1) => \cb_int_reg[31]_i_9_n_6\,
\rgb888[8]_1\(0) => \cb_int_reg[31]_i_9_n_7\,
\rgb888[8]_10\(1) => \cb_int_reg[31]_i_66_n_6\,
\rgb888[8]_10\(0) => \cb_int_reg[31]_i_66_n_7\,
\rgb888[8]_11\(0) => \cb_int_reg[31]_i_10_n_1\,
\rgb888[8]_12\(3) => \cr_int_reg[7]_i_24_n_4\,
\rgb888[8]_12\(2) => \cr_int_reg[7]_i_24_n_5\,
\rgb888[8]_12\(1) => \cr_int_reg[7]_i_24_n_6\,
\rgb888[8]_12\(0) => \cr_int_reg[7]_i_24_n_7\,
\rgb888[8]_13\(3) => \cr_int_reg[11]_i_28_n_4\,
\rgb888[8]_13\(2) => \cr_int_reg[11]_i_28_n_5\,
\rgb888[8]_13\(1) => \cr_int_reg[11]_i_28_n_6\,
\rgb888[8]_13\(0) => \cr_int_reg[11]_i_28_n_7\,
\rgb888[8]_14\(3) => \cr_int_reg[15]_i_37_n_4\,
\rgb888[8]_14\(2) => \cr_int_reg[15]_i_37_n_5\,
\rgb888[8]_14\(1) => \cr_int_reg[15]_i_37_n_6\,
\rgb888[8]_14\(0) => \cr_int_reg[15]_i_37_n_7\,
\rgb888[8]_15\(3) => \cr_int_reg[31]_i_64_n_4\,
\rgb888[8]_15\(2) => \cr_int_reg[31]_i_64_n_5\,
\rgb888[8]_15\(1) => \cr_int_reg[31]_i_64_n_6\,
\rgb888[8]_15\(0) => \cr_int_reg[31]_i_64_n_7\,
\rgb888[8]_16\(3) => \cr_int_reg[31]_i_27_n_4\,
\rgb888[8]_16\(2) => \cr_int_reg[31]_i_27_n_5\,
\rgb888[8]_16\(1) => \cr_int_reg[31]_i_27_n_6\,
\rgb888[8]_16\(0) => \cr_int_reg[31]_i_27_n_7\,
\rgb888[8]_17\(1) => \cr_int_reg[31]_i_10_n_6\,
\rgb888[8]_17\(0) => \cr_int_reg[31]_i_10_n_7\,
\rgb888[8]_18\(0) => \cr_int_reg[31]_i_10_n_1\,
\rgb888[8]_19\(2) => \y_int_reg[3]_i_70_n_4\,
\rgb888[8]_19\(1) => \y_int_reg[3]_i_70_n_5\,
\rgb888[8]_19\(0) => \y_int_reg[3]_i_70_n_6\,
\rgb888[8]_2\(3) => \cb_int_reg[7]_i_26_n_4\,
\rgb888[8]_2\(2) => \cb_int_reg[7]_i_26_n_5\,
\rgb888[8]_2\(1) => \cb_int_reg[7]_i_26_n_6\,
\rgb888[8]_2\(0) => \cb_int_reg[7]_i_26_n_7\,
\rgb888[8]_20\(3) => \y_int_reg[31]_i_21_n_4\,
\rgb888[8]_20\(2) => \y_int_reg[31]_i_21_n_5\,
\rgb888[8]_20\(1) => \y_int_reg[31]_i_21_n_6\,
\rgb888[8]_20\(0) => \y_int_reg[31]_i_21_n_7\,
\rgb888[8]_21\(2) => \y_int_reg[31]_i_9_n_5\,
\rgb888[8]_21\(1) => \y_int_reg[31]_i_9_n_6\,
\rgb888[8]_21\(0) => \y_int_reg[31]_i_9_n_7\,
\rgb888[8]_22\(3) => \y_int_reg[11]_i_27_n_4\,
\rgb888[8]_22\(2) => \y_int_reg[11]_i_27_n_5\,
\rgb888[8]_22\(1) => \y_int_reg[11]_i_27_n_6\,
\rgb888[8]_22\(0) => \y_int_reg[11]_i_27_n_7\,
\rgb888[8]_23\(1) => \y_int_reg[31]_i_10_n_6\,
\rgb888[8]_23\(0) => \y_int_reg[31]_i_10_n_7\,
\rgb888[8]_24\(0) => \y_int_reg[23]_i_32_n_7\,
\rgb888[8]_25\(3) => \y_int_reg[23]_i_35_n_4\,
\rgb888[8]_25\(2) => \y_int_reg[23]_i_35_n_5\,
\rgb888[8]_25\(1) => \y_int_reg[23]_i_35_n_6\,
\rgb888[8]_25\(0) => \y_int_reg[23]_i_35_n_7\,
\rgb888[8]_26\(3) => \y_int_reg[31]_i_27_n_4\,
\rgb888[8]_26\(2) => \y_int_reg[31]_i_27_n_5\,
\rgb888[8]_26\(1) => \y_int_reg[31]_i_27_n_6\,
\rgb888[8]_26\(0) => \y_int_reg[31]_i_27_n_7\,
\rgb888[8]_27\(3) => \y_int_reg[19]_i_24_n_4\,
\rgb888[8]_27\(2) => \y_int_reg[19]_i_24_n_5\,
\rgb888[8]_27\(1) => \y_int_reg[19]_i_24_n_6\,
\rgb888[8]_27\(0) => \y_int_reg[19]_i_24_n_7\,
\rgb888[8]_28\(3) => \y_int_reg[19]_i_33_n_4\,
\rgb888[8]_28\(2) => \y_int_reg[19]_i_33_n_5\,
\rgb888[8]_28\(1) => \y_int_reg[19]_i_33_n_6\,
\rgb888[8]_28\(0) => \y_int_reg[19]_i_33_n_7\,
\rgb888[8]_29\(3) => \y_int_reg[15]_i_24_n_4\,
\rgb888[8]_29\(2) => \y_int_reg[15]_i_24_n_5\,
\rgb888[8]_29\(1) => \y_int_reg[15]_i_24_n_6\,
\rgb888[8]_29\(0) => \y_int_reg[15]_i_24_n_7\,
\rgb888[8]_3\(3) => \cb_int_reg[7]_i_23_n_4\,
\rgb888[8]_3\(2) => \cb_int_reg[7]_i_23_n_5\,
\rgb888[8]_3\(1) => \cb_int_reg[7]_i_23_n_6\,
\rgb888[8]_3\(0) => \cb_int_reg[7]_i_23_n_7\,
\rgb888[8]_30\(0) => \y_int_reg[31]_i_10_n_1\,
\rgb888[8]_31\(2) => \cb_int_reg[3]_i_68_n_5\,
\rgb888[8]_31\(1) => \cb_int_reg[3]_i_68_n_6\,
\rgb888[8]_31\(0) => \cb_int_reg[3]_i_68_n_7\,
\rgb888[8]_32\(1) => \y_int_reg[3]_i_40_n_6\,
\rgb888[8]_32\(0) => \y_int_reg[3]_i_40_n_7\,
\rgb888[8]_4\(3) => \cb_int_reg[15]_i_31_n_4\,
\rgb888[8]_4\(2) => \cb_int_reg[15]_i_31_n_5\,
\rgb888[8]_4\(1) => \cb_int_reg[15]_i_31_n_6\,
\rgb888[8]_4\(0) => \cb_int_reg[15]_i_31_n_7\,
\rgb888[8]_5\(3) => \cb_int_reg[31]_i_61_n_4\,
\rgb888[8]_5\(2) => \cb_int_reg[31]_i_61_n_5\,
\rgb888[8]_5\(1) => \cb_int_reg[31]_i_61_n_6\,
\rgb888[8]_5\(0) => \cb_int_reg[31]_i_61_n_7\,
\rgb888[8]_6\(3) => \cb_int_reg[19]_i_32_n_4\,
\rgb888[8]_6\(2) => \cb_int_reg[19]_i_32_n_5\,
\rgb888[8]_6\(1) => \cb_int_reg[19]_i_32_n_6\,
\rgb888[8]_6\(0) => \cb_int_reg[19]_i_32_n_7\,
\rgb888[8]_7\(3) => \cb_int_reg[31]_i_27_n_4\,
\rgb888[8]_7\(2) => \cb_int_reg[31]_i_27_n_5\,
\rgb888[8]_7\(1) => \cb_int_reg[31]_i_27_n_6\,
\rgb888[8]_7\(0) => \cb_int_reg[31]_i_27_n_7\,
\rgb888[8]_8\(3) => \cb_int_reg[23]_i_27_n_4\,
\rgb888[8]_8\(2) => \cb_int_reg[23]_i_27_n_5\,
\rgb888[8]_8\(1) => \cb_int_reg[23]_i_27_n_6\,
\rgb888[8]_8\(0) => \cb_int_reg[23]_i_27_n_7\,
\rgb888[8]_9\(1) => \cb_int_reg[31]_i_10_n_6\,
\rgb888[8]_9\(0) => \cb_int_reg[31]_i_10_n_7\,
vsync => vsync,
\y_int_reg[15]_0\(3) => U0_n_68,
\y_int_reg[15]_0\(2) => U0_n_69,
\y_int_reg[15]_0\(1) => U0_n_70,
\y_int_reg[15]_0\(0) => U0_n_71,
\y_int_reg[15]_1\(0) => U0_n_81,
\y_int_reg[19]_0\(3) => U0_n_64,
\y_int_reg[19]_0\(2) => U0_n_65,
\y_int_reg[19]_0\(1) => U0_n_66,
\y_int_reg[19]_0\(0) => U0_n_67,
\y_int_reg[19]_1\(0) => U0_n_79,
\y_int_reg[23]_0\(0) => U0_n_55,
\y_int_reg[23]_1\(1) => U0_n_58,
\y_int_reg[23]_1\(0) => U0_n_59,
\y_int_reg[23]_2\(3) => U0_n_60,
\y_int_reg[23]_2\(2) => U0_n_61,
\y_int_reg[23]_2\(1) => U0_n_62,
\y_int_reg[23]_2\(0) => U0_n_63,
\y_int_reg[23]_3\(0) => U0_n_80,
\y_int_reg[3]_0\(3) => U0_n_51,
\y_int_reg[3]_0\(2) => U0_n_52,
\y_int_reg[3]_0\(1) => U0_n_53,
\y_int_reg[3]_0\(0) => U0_n_54,
\y_int_reg[3]_1\(0) => U0_n_57,
\y_int_reg[3]_2\(0) => U0_n_78,
\y_int_reg[7]_0\(0) => U0_n_56
);
\cb_int[15]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[15]_i_32_n_4\,
O => \cb_int[15]_i_35_n_0\
);
\cb_int[15]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[15]_i_32_n_5\,
O => \cb_int[15]_i_36_n_0\
);
\cb_int[15]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[15]_i_32_n_6\,
O => \cb_int[15]_i_37_n_0\
);
\cb_int[15]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[15]_i_32_n_7\,
O => \cb_int[15]_i_38_n_0\
);
\cb_int[15]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[15]_i_39_n_0\
);
\cb_int[15]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[15]_i_40_n_0\
);
\cb_int[15]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[15]_i_41_n_0\
);
\cb_int[15]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[15]_i_42_n_0\
);
\cb_int[15]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[15]_i_47_n_0\
);
\cb_int[15]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[15]_i_48_n_0\
);
\cb_int[15]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[15]_i_49_n_0\
);
\cb_int[15]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[15]_i_50_n_0\
);
\cb_int[19]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[19]_i_38_n_0\
);
\cb_int[19]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[19]_i_39_n_0\
);
\cb_int[19]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[19]_i_40_n_0\
);
\cb_int[19]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[19]_i_41_n_0\
);
\cb_int[19]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[19]_i_42_n_0\
);
\cb_int[19]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[19]_i_43_n_0\
);
\cb_int[19]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[19]_i_44_n_0\
);
\cb_int[19]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[19]_i_45_n_0\
);
\cb_int[23]_i_33\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[23]_i_33_n_0\
);
\cb_int[23]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[23]_i_34_n_0\
);
\cb_int[23]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[23]_i_35_n_0\
);
\cb_int[23]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[23]_i_36_n_0\
);
\cb_int[23]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[23]_i_37_n_0\
);
\cb_int[23]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[23]_i_38_n_0\
);
\cb_int[23]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[23]_i_39_n_0\
);
\cb_int[23]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[23]_i_40_n_0\
);
\cb_int[31]_i_100\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(14),
O => \cb_int[31]_i_100_n_0\
);
\cb_int[31]_i_101\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(13),
O => \cb_int[31]_i_101_n_0\
);
\cb_int[31]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_n_13,
I1 => rgb888(7),
O => \cb_int[31]_i_18_n_0\
);
\cb_int[31]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => U0_n_13,
O => \cb_int[31]_i_19_n_0\
);
\cb_int[31]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => U0_n_13,
O => \cb_int[31]_i_20_n_0\
);
\cb_int[31]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => U0_n_13,
O => \cb_int[31]_i_21_n_0\
);
\cb_int[31]_i_22\: unisim.vcomponents.LUT3
generic map(
INIT => X"95"
)
port map (
I0 => rgb888(7),
I1 => \cb_int[31]_i_52_n_0\,
I2 => rgb888(6),
O => \cb_int[31]_i_22_n_0\
);
\cb_int[31]_i_25\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \cb_int[31]_i_25_n_0\
);
\cb_int[31]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \cb_int[31]_i_26_n_0\
);
\cb_int[31]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_66_n_6\,
O => \cb_int[31]_i_28_n_0\
);
\cb_int[31]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_66_n_7\,
O => \cb_int[31]_i_29_n_0\
);
\cb_int[31]_i_45\: unisim.vcomponents.LUT5
generic map(
INIT => X"99999996"
)
port map (
I0 => \cb_int_reg[3]_i_43_n_1\,
I1 => rgb888(4),
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
O => \cb_int[31]_i_45_n_0\
);
\cb_int[31]_i_46\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(2),
I1 => rgb888(1),
O => \cb_int[31]_i_46_n_0\
);
\cb_int[31]_i_47\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA955555555"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
I5 => rgb888(5),
O => \cb_int[31]_i_47_n_0\
);
\cb_int[31]_i_48\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCC999999993"
)
port map (
I0 => \cb_int_reg[3]_i_43_n_1\,
I1 => rgb888(5),
I2 => rgb888(3),
I3 => rgb888(1),
I4 => rgb888(2),
I5 => rgb888(4),
O => \cb_int[31]_i_48_n_0\
);
\cb_int[31]_i_49\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA99995"
)
port map (
I0 => rgb888(4),
I1 => \cb_int_reg[3]_i_43_n_1\,
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
O => \cb_int[31]_i_49_n_0\
);
\cb_int[31]_i_50\: unisim.vcomponents.LUT4
generic map(
INIT => X"6A95"
)
port map (
I0 => \cb_int_reg[3]_i_43_n_1\,
I1 => rgb888(2),
I2 => rgb888(1),
I3 => rgb888(3),
O => \cb_int[31]_i_50_n_0\
);
\cb_int[31]_i_52\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
I2 => rgb888(1),
I3 => rgb888(3),
I4 => rgb888(5),
O => \cb_int[31]_i_52_n_0\
);
\cb_int[31]_i_53\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => rgb888(14),
I1 => rgb888(12),
I2 => rgb888(10),
I3 => rgb888(11),
I4 => rgb888(13),
I5 => rgb888(15),
O => \cb_int[31]_i_53_n_0\
);
\cb_int[31]_i_54\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000006AAAAAAA"
)
port map (
I0 => rgb888(14),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(15),
O => \cb_int[31]_i_54_n_0\
);
\cb_int[31]_i_55\: unisim.vcomponents.LUT6
generic map(
INIT => X"2BBBBBBBB2222222"
)
port map (
I0 => \cb_int_reg[31]_i_85_n_0\,
I1 => rgb888(15),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(13),
O => \cb_int[31]_i_55_n_0\
);
\cb_int[31]_i_56\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFEA2A80"
)
port map (
I0 => \cb_int_reg[31]_i_85_n_5\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(12),
I4 => rgb888(14),
O => \cb_int[31]_i_56_n_0\
);
\cb_int[31]_i_57\: unisim.vcomponents.LUT6
generic map(
INIT => X"9555555555555555"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \cb_int[31]_i_57_n_0\
);
\cb_int[31]_i_58\: unisim.vcomponents.LUT6
generic map(
INIT => X"2AAAAAAABFFFFFFF"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \cb_int[31]_i_58_n_0\
);
\cb_int[31]_i_59\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => U0_n_6,
I1 => \cb_int_reg[31]_i_85_n_0\,
I2 => rgb888(15),
I3 => U0_n_5,
O => \cb_int[31]_i_59_n_0\
);
\cb_int[31]_i_60\: unisim.vcomponents.LUT6
generic map(
INIT => X"E81717E817E8E817"
)
port map (
I0 => rgb888(14),
I1 => \cb_int[31]_i_88_n_0\,
I2 => \cb_int_reg[31]_i_85_n_5\,
I3 => U0_n_6,
I4 => rgb888(15),
I5 => \cb_int_reg[31]_i_85_n_0\,
O => \cb_int[31]_i_60_n_0\
);
\cb_int[31]_i_62\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[23]_i_27_n_4\,
O => \cb_int[31]_i_62_n_0\
);
\cb_int[31]_i_63\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[23]_i_27_n_5\,
O => \cb_int[31]_i_63_n_0\
);
\cb_int[31]_i_64\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[23]_i_27_n_6\,
O => \cb_int[31]_i_64_n_0\
);
\cb_int[31]_i_65\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[23]_i_27_n_7\,
O => \cb_int[31]_i_65_n_0\
);
\cb_int[31]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[31]_i_83_n_0\
);
\cb_int[31]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[31]_i_84_n_0\
);
\cb_int[31]_i_88\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => rgb888(10),
I1 => rgb888(11),
I2 => rgb888(12),
O => \cb_int[31]_i_88_n_0\
);
\cb_int[31]_i_89\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[19]_i_32_n_4\,
O => \cb_int[31]_i_89_n_0\
);
\cb_int[31]_i_90\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[19]_i_32_n_5\,
O => \cb_int[31]_i_90_n_0\
);
\cb_int[31]_i_91\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[19]_i_32_n_6\,
O => \cb_int[31]_i_91_n_0\
);
\cb_int[31]_i_92\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[19]_i_32_n_7\,
O => \cb_int[31]_i_92_n_0\
);
\cb_int[31]_i_93\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[31]_i_93_n_0\
);
\cb_int[31]_i_94\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[31]_i_94_n_0\
);
\cb_int[31]_i_99\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \cb_int[31]_i_99_n_0\
);
\cb_int[3]_i_35\: unisim.vcomponents.LUT4
generic map(
INIT => X"BE28"
)
port map (
I0 => \cb_int_reg[31]_i_85_n_6\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(13),
O => \cb_int[3]_i_35_n_0\
);
\cb_int[3]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => rgb888(10),
I1 => \cb_int_reg[31]_i_85_n_7\,
I2 => rgb888(12),
O => \cb_int[3]_i_36_n_0\
);
\cb_int[3]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int_reg[3]_i_68_n_4\,
I1 => rgb888(9),
I2 => rgb888(11),
O => \cb_int[3]_i_37_n_0\
);
\cb_int[3]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int_reg[3]_i_68_n_4\,
I1 => rgb888(9),
I2 => rgb888(11),
O => \cb_int[3]_i_38_n_0\
);
\cb_int[3]_i_39\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669696969969696"
)
port map (
I0 => \cb_int[3]_i_35_n_0\,
I1 => rgb888(14),
I2 => rgb888(12),
I3 => rgb888(11),
I4 => rgb888(10),
I5 => \cb_int_reg[31]_i_85_n_5\,
O => \cb_int[3]_i_39_n_0\
);
\cb_int[3]_i_40\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \cb_int_reg[31]_i_85_n_6\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(13),
I4 => \cb_int[3]_i_36_n_0\,
O => \cb_int[3]_i_40_n_0\
);
\cb_int[3]_i_41\: unisim.vcomponents.LUT6
generic map(
INIT => X"E81717E817E8E817"
)
port map (
I0 => rgb888(11),
I1 => rgb888(9),
I2 => \cb_int_reg[3]_i_68_n_4\,
I3 => rgb888(12),
I4 => rgb888(10),
I5 => \cb_int_reg[31]_i_85_n_7\,
O => \cb_int[3]_i_41_n_0\
);
\cb_int[3]_i_42\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969696"
)
port map (
I0 => rgb888(11),
I1 => rgb888(9),
I2 => \cb_int_reg[3]_i_68_n_4\,
I3 => rgb888(10),
I4 => rgb888(8),
O => \cb_int[3]_i_42_n_0\
);
\cb_int[3]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_19_n_6\,
O => \cb_int[3]_i_59_n_0\
);
\cb_int[3]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_19_n_7\,
O => \cb_int[3]_i_60_n_0\
);
\cb_int[3]_i_61\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_9,
O => \cb_int[3]_i_61_n_0\
);
\cb_int[3]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_10,
O => \cb_int[3]_i_62_n_0\
);
\cb_int[3]_i_73\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(7),
O => \cb_int[3]_i_73_n_0\
);
\cb_int[3]_i_74\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(6),
O => \cb_int[3]_i_74_n_0\
);
\cb_int[3]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(8),
O => \cb_int[3]_i_84_n_0\
);
\cb_int[3]_i_85\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_11,
O => \cb_int[3]_i_85_n_0\
);
\cb_int[3]_i_86\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_12,
O => \cb_int[3]_i_86_n_0\
);
\cb_int[3]_i_87\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_7,
O => \cb_int[3]_i_87_n_0\
);
\cb_int[3]_i_88\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_8,
O => \cb_int[3]_i_88_n_0\
);
\cb_int[3]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(12),
I1 => rgb888(15),
O => \cb_int[3]_i_95_n_0\
);
\cb_int[3]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(11),
I1 => rgb888(14),
O => \cb_int[3]_i_96_n_0\
);
\cb_int[3]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(10),
I1 => rgb888(13),
O => \cb_int[3]_i_97_n_0\
);
\cb_int[3]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(9),
I1 => rgb888(12),
O => \cb_int[3]_i_98_n_0\
);
\cb_int[7]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[7]_i_24_n_4\,
O => \cb_int[7]_i_30_n_0\
);
\cb_int[7]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_24_n_5\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_9_n_7\,
O => \cb_int[7]_i_31_n_0\
);
\cb_int[7]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_24_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_23_n_4\,
O => \cb_int[7]_i_32_n_0\
);
\cb_int[7]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_24_n_7\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_23_n_5\,
O => \cb_int[7]_i_33_n_0\
);
\cb_int[7]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[7]_i_34_n_0\
);
\cb_int[7]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_7\,
O => \cb_int[7]_i_35_n_0\
);
\cb_int[7]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_23_n_4\,
O => \cb_int[7]_i_36_n_0\
);
\cb_int[7]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_23_n_5\,
O => \cb_int[7]_i_37_n_0\
);
\cb_int[7]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[3]_i_32_n_4\,
I1 => U0_n_16,
I2 => \cb_int_reg[3]_i_19_n_6\,
O => \cb_int[7]_i_43_n_0\
);
\cb_int[7]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_27_n_4\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_23_n_6\,
O => \cb_int[7]_i_44_n_0\
);
\cb_int[7]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_27_n_5\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_23_n_7\,
O => \cb_int[7]_i_45_n_0\
);
\cb_int[7]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_27_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[3]_i_19_n_4\,
O => \cb_int[7]_i_46_n_0\
);
\cb_int[7]_i_47\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_27_n_7\,
I1 => U0_n_16,
I2 => \cb_int_reg[3]_i_19_n_5\,
O => \cb_int[7]_i_47_n_0\
);
\cb_int[7]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_23_n_6\,
O => \cb_int[7]_i_48_n_0\
);
\cb_int[7]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_23_n_7\,
O => \cb_int[7]_i_49_n_0\
);
\cb_int[7]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_19_n_4\,
O => \cb_int[7]_i_50_n_0\
);
\cb_int[7]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_19_n_5\,
O => \cb_int[7]_i_51_n_0\
);
\cb_int_reg[15]_i_31\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_23_n_0\,
CO(3) => \cb_int_reg[15]_i_31_n_0\,
CO(2) => \cb_int_reg[15]_i_31_n_1\,
CO(1) => \cb_int_reg[15]_i_31_n_2\,
CO(0) => \cb_int_reg[15]_i_31_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[15]_i_31_n_4\,
O(2) => \cb_int_reg[15]_i_31_n_5\,
O(1) => \cb_int_reg[15]_i_31_n_6\,
O(0) => \cb_int_reg[15]_i_31_n_7\,
S(3) => \cb_int[15]_i_35_n_0\,
S(2) => \cb_int[15]_i_36_n_0\,
S(1) => \cb_int[15]_i_37_n_0\,
S(0) => \cb_int[15]_i_38_n_0\
);
\cb_int_reg[15]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_24_n_0\,
CO(3) => \cb_int_reg[15]_i_32_n_0\,
CO(2) => \cb_int_reg[15]_i_32_n_1\,
CO(1) => \cb_int_reg[15]_i_32_n_2\,
CO(0) => \cb_int_reg[15]_i_32_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[15]_i_32_n_4\,
O(2) => \cb_int_reg[15]_i_32_n_5\,
O(1) => \cb_int_reg[15]_i_32_n_6\,
O(0) => \cb_int_reg[15]_i_32_n_7\,
S(3) => \cb_int[15]_i_39_n_0\,
S(2) => \cb_int[15]_i_40_n_0\,
S(1) => \cb_int[15]_i_41_n_0\,
S(0) => \cb_int[15]_i_42_n_0\
);
\cb_int_reg[15]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_76,
CO(3) => \cb_int_reg[15]_i_34_n_0\,
CO(2) => \cb_int_reg[15]_i_34_n_1\,
CO(1) => \cb_int_reg[15]_i_34_n_2\,
CO(0) => \cb_int_reg[15]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[15]_i_34_n_4\,
O(2) => \cb_int_reg[15]_i_34_n_5\,
O(1) => \cb_int_reg[15]_i_34_n_6\,
O(0) => \cb_int_reg[15]_i_34_n_7\,
S(3) => \cb_int[15]_i_47_n_0\,
S(2) => \cb_int[15]_i_48_n_0\,
S(1) => \cb_int[15]_i_49_n_0\,
S(0) => \cb_int[15]_i_50_n_0\
);
\cb_int_reg[19]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_32_n_0\,
CO(3) => \cb_int_reg[19]_i_32_n_0\,
CO(2) => \cb_int_reg[19]_i_32_n_1\,
CO(1) => \cb_int_reg[19]_i_32_n_2\,
CO(0) => \cb_int_reg[19]_i_32_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[19]_i_32_n_4\,
O(2) => \cb_int_reg[19]_i_32_n_5\,
O(1) => \cb_int_reg[19]_i_32_n_6\,
O(0) => \cb_int_reg[19]_i_32_n_7\,
S(3) => \cb_int[19]_i_38_n_0\,
S(2) => \cb_int[19]_i_39_n_0\,
S(1) => \cb_int[19]_i_40_n_0\,
S(0) => \cb_int[19]_i_41_n_0\
);
\cb_int_reg[19]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_34_n_0\,
CO(3) => \cb_int_reg[19]_i_33_n_0\,
CO(2) => \cb_int_reg[19]_i_33_n_1\,
CO(1) => \cb_int_reg[19]_i_33_n_2\,
CO(0) => \cb_int_reg[19]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[19]_i_33_n_4\,
O(2) => \cb_int_reg[19]_i_33_n_5\,
O(1) => \cb_int_reg[19]_i_33_n_6\,
O(0) => \cb_int_reg[19]_i_33_n_7\,
S(3) => \cb_int[19]_i_42_n_0\,
S(2) => \cb_int[19]_i_43_n_0\,
S(1) => \cb_int[19]_i_44_n_0\,
S(0) => \cb_int[19]_i_45_n_0\
);
\cb_int_reg[23]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_32_n_0\,
CO(3) => \cb_int_reg[23]_i_27_n_0\,
CO(2) => \cb_int_reg[23]_i_27_n_1\,
CO(1) => \cb_int_reg[23]_i_27_n_2\,
CO(0) => \cb_int_reg[23]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[23]_i_27_n_4\,
O(2) => \cb_int_reg[23]_i_27_n_5\,
O(1) => \cb_int_reg[23]_i_27_n_6\,
O(0) => \cb_int_reg[23]_i_27_n_7\,
S(3) => \cb_int[23]_i_33_n_0\,
S(2) => \cb_int[23]_i_34_n_0\,
S(1) => \cb_int[23]_i_35_n_0\,
S(0) => \cb_int[23]_i_36_n_0\
);
\cb_int_reg[23]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_33_n_0\,
CO(3) => \cb_int_reg[23]_i_28_n_0\,
CO(2) => \cb_int_reg[23]_i_28_n_1\,
CO(1) => \cb_int_reg[23]_i_28_n_2\,
CO(0) => \cb_int_reg[23]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[23]_i_28_n_4\,
O(2) => \cb_int_reg[23]_i_28_n_5\,
O(1) => \cb_int_reg[23]_i_28_n_6\,
O(0) => \cb_int_reg[23]_i_28_n_7\,
S(3) => \cb_int[23]_i_37_n_0\,
S(2) => \cb_int[23]_i_38_n_0\,
S(1) => \cb_int[23]_i_39_n_0\,
S(0) => \cb_int[23]_i_40_n_0\
);
\cb_int_reg[31]_i_10\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_27_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_10_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_10_n_1\,
CO(1) => \NLW_cb_int_reg[31]_i_10_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[31]_i_10_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_10_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_10_n_6\,
O(0) => \cb_int_reg[31]_i_10_n_7\,
S(3 downto 2) => B"01",
S(1) => \cb_int[31]_i_28_n_0\,
S(0) => \cb_int[31]_i_29_n_0\
);
\cb_int_reg[31]_i_17\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_75,
CO(3) => \cb_int_reg[31]_i_17_n_0\,
CO(2) => \cb_int_reg[31]_i_17_n_1\,
CO(1) => \cb_int_reg[31]_i_17_n_2\,
CO(0) => \cb_int_reg[31]_i_17_n_3\,
CYINIT => '0',
DI(3) => U0_n_14,
DI(2) => U0_n_15,
DI(1) => \cb_int[31]_i_45_n_0\,
DI(0) => \cb_int[31]_i_46_n_0\,
O(3) => \cb_int_reg[31]_i_17_n_4\,
O(2) => \cb_int_reg[31]_i_17_n_5\,
O(1) => \cb_int_reg[31]_i_17_n_6\,
O(0) => \cb_int_reg[31]_i_17_n_7\,
S(3) => \cb_int[31]_i_47_n_0\,
S(2) => \cb_int[31]_i_48_n_0\,
S(1) => \cb_int[31]_i_49_n_0\,
S(0) => \cb_int[31]_i_50_n_0\
);
\cb_int_reg[31]_i_23\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_19_n_0\,
CO(3) => \cb_int_reg[31]_i_23_n_0\,
CO(2) => \cb_int_reg[31]_i_23_n_1\,
CO(1) => \cb_int_reg[31]_i_23_n_2\,
CO(0) => \cb_int_reg[31]_i_23_n_3\,
CYINIT => '0',
DI(3) => \cb_int[31]_i_53_n_0\,
DI(2) => \cb_int[31]_i_54_n_0\,
DI(1) => \cb_int[31]_i_55_n_0\,
DI(0) => \cb_int[31]_i_56_n_0\,
O(3) => \cb_int_reg[31]_i_23_n_4\,
O(2) => \cb_int_reg[31]_i_23_n_5\,
O(1) => \cb_int_reg[31]_i_23_n_6\,
O(0) => \cb_int_reg[31]_i_23_n_7\,
S(3) => \cb_int[31]_i_57_n_0\,
S(2) => \cb_int[31]_i_58_n_0\,
S(1) => \cb_int[31]_i_59_n_0\,
S(0) => \cb_int[31]_i_60_n_0\
);
\cb_int_reg[31]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_61_n_0\,
CO(3) => \cb_int_reg[31]_i_27_n_0\,
CO(2) => \cb_int_reg[31]_i_27_n_1\,
CO(1) => \cb_int_reg[31]_i_27_n_2\,
CO(0) => \cb_int_reg[31]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[31]_i_27_n_4\,
O(2) => \cb_int_reg[31]_i_27_n_5\,
O(1) => \cb_int_reg[31]_i_27_n_6\,
O(0) => \cb_int_reg[31]_i_27_n_7\,
S(3) => \cb_int[31]_i_62_n_0\,
S(2) => \cb_int[31]_i_63_n_0\,
S(1) => \cb_int[31]_i_64_n_0\,
S(0) => \cb_int[31]_i_65_n_0\
);
\cb_int_reg[31]_i_42\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[23]_i_28_n_0\,
CO(3 downto 1) => \NLW_cb_int_reg[31]_i_42_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cb_int_reg[31]_i_42_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_42_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_42_n_6\,
O(0) => \cb_int_reg[31]_i_42_n_7\,
S(3 downto 2) => B"00",
S(1) => \cb_int[31]_i_83_n_0\,
S(0) => \cb_int[31]_i_84_n_0\
);
\cb_int_reg[31]_i_61\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_31_n_0\,
CO(3) => \cb_int_reg[31]_i_61_n_0\,
CO(2) => \cb_int_reg[31]_i_61_n_1\,
CO(1) => \cb_int_reg[31]_i_61_n_2\,
CO(0) => \cb_int_reg[31]_i_61_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[31]_i_61_n_4\,
O(2) => \cb_int_reg[31]_i_61_n_5\,
O(1) => \cb_int_reg[31]_i_61_n_6\,
O(0) => \cb_int_reg[31]_i_61_n_7\,
S(3) => \cb_int[31]_i_89_n_0\,
S(2) => \cb_int[31]_i_90_n_0\,
S(1) => \cb_int[31]_i_91_n_0\,
S(0) => \cb_int[31]_i_92_n_0\
);
\cb_int_reg[31]_i_66\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[23]_i_27_n_0\,
CO(3 downto 1) => \NLW_cb_int_reg[31]_i_66_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cb_int_reg[31]_i_66_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_66_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_66_n_6\,
O(0) => \cb_int_reg[31]_i_66_n_7\,
S(3 downto 2) => B"00",
S(1) => \cb_int[31]_i_93_n_0\,
S(0) => \cb_int[31]_i_94_n_0\
);
\cb_int_reg[31]_i_8\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_17_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_8_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_8_n_1\,
CO(1) => \cb_int_reg[31]_i_8_n_2\,
CO(0) => \cb_int_reg[31]_i_8_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \cb_int[31]_i_18_n_0\,
O(3) => \cb_int_reg[31]_i_8_n_4\,
O(2) => \cb_int_reg[31]_i_8_n_5\,
O(1) => \cb_int_reg[31]_i_8_n_6\,
O(0) => \cb_int_reg[31]_i_8_n_7\,
S(3) => \cb_int[31]_i_19_n_0\,
S(2) => \cb_int[31]_i_20_n_0\,
S(1) => \cb_int[31]_i_21_n_0\,
S(0) => \cb_int[31]_i_22_n_0\
);
\cb_int_reg[31]_i_85\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_68_n_0\,
CO(3) => \cb_int_reg[31]_i_85_n_0\,
CO(2) => \NLW_cb_int_reg[31]_i_85_CO_UNCONNECTED\(2),
CO(1) => \cb_int_reg[31]_i_85_n_2\,
CO(0) => \cb_int_reg[31]_i_85_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 1) => rgb888(15 downto 14),
DI(0) => '0',
O(3) => \NLW_cb_int_reg[31]_i_85_O_UNCONNECTED\(3),
O(2) => \cb_int_reg[31]_i_85_n_5\,
O(1) => \cb_int_reg[31]_i_85_n_6\,
O(0) => \cb_int_reg[31]_i_85_n_7\,
S(3) => '1',
S(2) => \cb_int[31]_i_99_n_0\,
S(1) => \cb_int[31]_i_100_n_0\,
S(0) => \cb_int[31]_i_101_n_0\
);
\cb_int_reg[31]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_23_n_0\,
CO(3 downto 1) => \NLW_cb_int_reg[31]_i_9_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cb_int_reg[31]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => U0_n_4,
O(3 downto 2) => \NLW_cb_int_reg[31]_i_9_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_9_n_6\,
O(0) => \cb_int_reg[31]_i_9_n_7\,
S(3 downto 2) => B"00",
S(1) => \cb_int[31]_i_25_n_0\,
S(0) => \cb_int[31]_i_26_n_0\
);
\cb_int_reg[3]_i_19\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_73,
CO(3) => \cb_int_reg[3]_i_19_n_0\,
CO(2) => \cb_int_reg[3]_i_19_n_1\,
CO(1) => \cb_int_reg[3]_i_19_n_2\,
CO(0) => \cb_int_reg[3]_i_19_n_3\,
CYINIT => '0',
DI(3) => \cb_int[3]_i_35_n_0\,
DI(2) => \cb_int[3]_i_36_n_0\,
DI(1) => \cb_int[3]_i_37_n_0\,
DI(0) => \cb_int[3]_i_38_n_0\,
O(3) => \cb_int_reg[3]_i_19_n_4\,
O(2) => \cb_int_reg[3]_i_19_n_5\,
O(1) => \cb_int_reg[3]_i_19_n_6\,
O(0) => \cb_int_reg[3]_i_19_n_7\,
S(3) => \cb_int[3]_i_39_n_0\,
S(2) => \cb_int[3]_i_40_n_0\,
S(1) => \cb_int[3]_i_41_n_0\,
S(0) => \cb_int[3]_i_42_n_0\
);
\cb_int_reg[3]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_58_n_0\,
CO(3) => \cb_int_reg[3]_i_32_n_0\,
CO(2) => \cb_int_reg[3]_i_32_n_1\,
CO(1) => \cb_int_reg[3]_i_32_n_2\,
CO(0) => \cb_int_reg[3]_i_32_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[3]_i_32_n_4\,
O(2 downto 0) => \NLW_cb_int_reg[3]_i_32_O_UNCONNECTED\(2 downto 0),
S(3) => \cb_int[3]_i_59_n_0\,
S(2) => \cb_int[3]_i_60_n_0\,
S(1) => \cb_int[3]_i_61_n_0\,
S(0) => \cb_int[3]_i_62_n_0\
);
\cb_int_reg[3]_i_43\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_74,
CO(3) => \NLW_cb_int_reg[3]_i_43_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[3]_i_43_n_1\,
CO(1) => \NLW_cb_int_reg[3]_i_43_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[3]_i_43_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => rgb888(7),
DI(0) => '0',
O(3 downto 2) => \NLW_cb_int_reg[3]_i_43_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[3]_i_43_n_6\,
O(0) => \cb_int_reg[3]_i_43_n_7\,
S(3 downto 2) => B"01",
S(1) => \cb_int[3]_i_73_n_0\,
S(0) => \cb_int[3]_i_74_n_0\
);
\cb_int_reg[3]_i_58\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_58_n_0\,
CO(2) => \cb_int_reg[3]_i_58_n_1\,
CO(1) => \cb_int_reg[3]_i_58_n_2\,
CO(0) => \cb_int_reg[3]_i_58_n_3\,
CYINIT => \cb_int[3]_i_84_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cb_int_reg[3]_i_58_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[3]_i_85_n_0\,
S(2) => \cb_int[3]_i_86_n_0\,
S(1) => \cb_int[3]_i_87_n_0\,
S(0) => \cb_int[3]_i_88_n_0\
);
\cb_int_reg[3]_i_68\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_72,
CO(3) => \cb_int_reg[3]_i_68_n_0\,
CO(2) => \cb_int_reg[3]_i_68_n_1\,
CO(1) => \cb_int_reg[3]_i_68_n_2\,
CO(0) => \cb_int_reg[3]_i_68_n_3\,
CYINIT => '0',
DI(3 downto 0) => rgb888(12 downto 9),
O(3) => \cb_int_reg[3]_i_68_n_4\,
O(2) => \cb_int_reg[3]_i_68_n_5\,
O(1) => \cb_int_reg[3]_i_68_n_6\,
O(0) => \cb_int_reg[3]_i_68_n_7\,
S(3) => \cb_int[3]_i_95_n_0\,
S(2) => \cb_int[3]_i_96_n_0\,
S(1) => \cb_int[3]_i_97_n_0\,
S(0) => \cb_int[3]_i_98_n_0\
);
\cb_int_reg[7]_i_23\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_26_n_0\,
CO(3) => \cb_int_reg[7]_i_23_n_0\,
CO(2) => \cb_int_reg[7]_i_23_n_1\,
CO(1) => \cb_int_reg[7]_i_23_n_2\,
CO(0) => \cb_int_reg[7]_i_23_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_23_n_4\,
O(2) => \cb_int_reg[7]_i_23_n_5\,
O(1) => \cb_int_reg[7]_i_23_n_6\,
O(0) => \cb_int_reg[7]_i_23_n_7\,
S(3) => \cb_int[7]_i_30_n_0\,
S(2) => \cb_int[7]_i_31_n_0\,
S(1) => \cb_int[7]_i_32_n_0\,
S(0) => \cb_int[7]_i_33_n_0\
);
\cb_int_reg[7]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_27_n_0\,
CO(3) => \cb_int_reg[7]_i_24_n_0\,
CO(2) => \cb_int_reg[7]_i_24_n_1\,
CO(1) => \cb_int_reg[7]_i_24_n_2\,
CO(0) => \cb_int_reg[7]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_24_n_4\,
O(2) => \cb_int_reg[7]_i_24_n_5\,
O(1) => \cb_int_reg[7]_i_24_n_6\,
O(0) => \cb_int_reg[7]_i_24_n_7\,
S(3) => \cb_int[7]_i_34_n_0\,
S(2) => \cb_int[7]_i_35_n_0\,
S(1) => \cb_int[7]_i_36_n_0\,
S(0) => \cb_int[7]_i_37_n_0\
);
\cb_int_reg[7]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[7]_i_26_n_0\,
CO(2) => \cb_int_reg[7]_i_26_n_1\,
CO(1) => \cb_int_reg[7]_i_26_n_2\,
CO(0) => \cb_int_reg[7]_i_26_n_3\,
CYINIT => \cb_int[7]_i_43_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_26_n_4\,
O(2) => \cb_int_reg[7]_i_26_n_5\,
O(1) => \cb_int_reg[7]_i_26_n_6\,
O(0) => \cb_int_reg[7]_i_26_n_7\,
S(3) => \cb_int[7]_i_44_n_0\,
S(2) => \cb_int[7]_i_45_n_0\,
S(1) => \cb_int[7]_i_46_n_0\,
S(0) => \cb_int[7]_i_47_n_0\
);
\cb_int_reg[7]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_32_n_0\,
CO(3) => \cb_int_reg[7]_i_27_n_0\,
CO(2) => \cb_int_reg[7]_i_27_n_1\,
CO(1) => \cb_int_reg[7]_i_27_n_2\,
CO(0) => \cb_int_reg[7]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_27_n_4\,
O(2) => \cb_int_reg[7]_i_27_n_5\,
O(1) => \cb_int_reg[7]_i_27_n_6\,
O(0) => \cb_int_reg[7]_i_27_n_7\,
S(3) => \cb_int[7]_i_48_n_0\,
S(2) => \cb_int[7]_i_49_n_0\,
S(1) => \cb_int[7]_i_50_n_0\,
S(0) => \cb_int[7]_i_51_n_0\
);
\cr_int[11]_i_61\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_35,
O => \cr_int[11]_i_61_n_0\
);
\cr_int[11]_i_62\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_36,
I1 => U0_n_26,
I2 => U0_n_18,
O => \cr_int[11]_i_62_n_0\
);
\cr_int[11]_i_63\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_37,
I1 => U0_n_26,
I2 => U0_n_19,
O => \cr_int[11]_i_63_n_0\
);
\cr_int[11]_i_64\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_30,
I1 => U0_n_26,
I2 => U0_n_20,
O => \cr_int[11]_i_64_n_0\
);
\cr_int[15]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_39,
O => \cr_int[15]_i_44_n_0\
);
\cr_int[15]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_40,
O => \cr_int[15]_i_45_n_0\
);
\cr_int[15]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_41,
O => \cr_int[15]_i_46_n_0\
);
\cr_int[15]_i_47\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_34,
O => \cr_int[15]_i_47_n_0\
);
\cr_int[15]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[15]_i_52_n_0\
);
\cr_int[15]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[15]_i_53_n_0\
);
\cr_int[15]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[15]_i_54_n_0\
);
\cr_int[15]_i_55\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[15]_i_55_n_0\
);
\cr_int[19]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[19]_i_42_n_0\
);
\cr_int[19]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[19]_i_43_n_0\
);
\cr_int[19]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[19]_i_44_n_0\
);
\cr_int[19]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[19]_i_45_n_0\
);
\cr_int[23]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[23]_i_32_n_0\
);
\cr_int[23]_i_33\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[23]_i_33_n_0\
);
\cr_int[23]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[23]_i_34_n_0\
);
\cr_int[23]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[23]_i_35_n_0\
);
\cr_int[31]_i_104\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_43,
O => \cr_int[31]_i_104_n_0\
);
\cr_int[31]_i_105\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_44,
O => \cr_int[31]_i_105_n_0\
);
\cr_int[31]_i_106\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_45,
O => \cr_int[31]_i_106_n_0\
);
\cr_int[31]_i_107\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_38,
O => \cr_int[31]_i_107_n_0\
);
\cr_int[31]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_50,
O => \cr_int[31]_i_28_n_0\
);
\cr_int[31]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_46,
O => \cr_int[31]_i_29_n_0\
);
\cr_int[31]_i_65\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_47,
O => \cr_int[31]_i_65_n_0\
);
\cr_int[31]_i_66\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_48,
O => \cr_int[31]_i_66_n_0\
);
\cr_int[31]_i_67\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_49,
O => \cr_int[31]_i_67_n_0\
);
\cr_int[31]_i_68\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_42,
O => \cr_int[31]_i_68_n_0\
);
\cr_int[31]_i_98\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[31]_i_98_n_0\
);
\cr_int[31]_i_99\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[31]_i_99_n_0\
);
\cr_int[7]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_28,
I1 => U0_n_26,
I2 => U0_n_25,
O => \cr_int[7]_i_29_n_0\
);
\cr_int[7]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_31,
I1 => U0_n_26,
I2 => U0_n_21,
O => \cr_int[7]_i_30_n_0\
);
\cr_int[7]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_32,
I1 => U0_n_26,
I2 => U0_n_22,
O => \cr_int[7]_i_31_n_0\
);
\cr_int[7]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_33,
I1 => U0_n_26,
I2 => U0_n_23,
O => \cr_int[7]_i_32_n_0\
);
\cr_int[7]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_27,
I1 => U0_n_26,
I2 => U0_n_24,
O => \cr_int[7]_i_33_n_0\
);
\cr_int_reg[11]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[7]_i_24_n_0\,
CO(3) => \cr_int_reg[11]_i_28_n_0\,
CO(2) => \cr_int_reg[11]_i_28_n_1\,
CO(1) => \cr_int_reg[11]_i_28_n_2\,
CO(0) => \cr_int_reg[11]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_28_n_4\,
O(2) => \cr_int_reg[11]_i_28_n_5\,
O(1) => \cr_int_reg[11]_i_28_n_6\,
O(0) => \cr_int_reg[11]_i_28_n_7\,
S(3) => \cr_int[11]_i_61_n_0\,
S(2) => \cr_int[11]_i_62_n_0\,
S(1) => \cr_int[11]_i_63_n_0\,
S(0) => \cr_int[11]_i_64_n_0\
);
\cr_int_reg[15]_i_37\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_28_n_0\,
CO(3) => \cr_int_reg[15]_i_37_n_0\,
CO(2) => \cr_int_reg[15]_i_37_n_1\,
CO(1) => \cr_int_reg[15]_i_37_n_2\,
CO(0) => \cr_int_reg[15]_i_37_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[15]_i_37_n_4\,
O(2) => \cr_int_reg[15]_i_37_n_5\,
O(1) => \cr_int_reg[15]_i_37_n_6\,
O(0) => \cr_int_reg[15]_i_37_n_7\,
S(3) => \cr_int[15]_i_44_n_0\,
S(2) => \cr_int[15]_i_45_n_0\,
S(1) => \cr_int[15]_i_46_n_0\,
S(0) => \cr_int[15]_i_47_n_0\
);
\cr_int_reg[15]_i_39\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_77,
CO(3) => \cr_int_reg[15]_i_39_n_0\,
CO(2) => \cr_int_reg[15]_i_39_n_1\,
CO(1) => \cr_int_reg[15]_i_39_n_2\,
CO(0) => \cr_int_reg[15]_i_39_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[15]_i_39_n_4\,
O(2) => \cr_int_reg[15]_i_39_n_5\,
O(1) => \cr_int_reg[15]_i_39_n_6\,
O(0) => \cr_int_reg[15]_i_39_n_7\,
S(3) => \cr_int[15]_i_52_n_0\,
S(2) => \cr_int[15]_i_53_n_0\,
S(1) => \cr_int[15]_i_54_n_0\,
S(0) => \cr_int[15]_i_55_n_0\
);
\cr_int_reg[19]_i_37\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_39_n_0\,
CO(3) => \cr_int_reg[19]_i_37_n_0\,
CO(2) => \cr_int_reg[19]_i_37_n_1\,
CO(1) => \cr_int_reg[19]_i_37_n_2\,
CO(0) => \cr_int_reg[19]_i_37_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[19]_i_37_n_4\,
O(2) => \cr_int_reg[19]_i_37_n_5\,
O(1) => \cr_int_reg[19]_i_37_n_6\,
O(0) => \cr_int_reg[19]_i_37_n_7\,
S(3) => \cr_int[19]_i_42_n_0\,
S(2) => \cr_int[19]_i_43_n_0\,
S(1) => \cr_int[19]_i_44_n_0\,
S(0) => \cr_int[19]_i_45_n_0\
);
\cr_int_reg[23]_i_31\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_37_n_0\,
CO(3) => \cr_int_reg[23]_i_31_n_0\,
CO(2) => \cr_int_reg[23]_i_31_n_1\,
CO(1) => \cr_int_reg[23]_i_31_n_2\,
CO(0) => \cr_int_reg[23]_i_31_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[23]_i_31_n_4\,
O(2) => \cr_int_reg[23]_i_31_n_5\,
O(1) => \cr_int_reg[23]_i_31_n_6\,
O(0) => \cr_int_reg[23]_i_31_n_7\,
S(3) => \cr_int[23]_i_32_n_0\,
S(2) => \cr_int[23]_i_33_n_0\,
S(1) => \cr_int[23]_i_34_n_0\,
S(0) => \cr_int[23]_i_35_n_0\
);
\cr_int_reg[31]_i_10\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_27_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_10_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_10_n_1\,
CO(1) => \NLW_cr_int_reg[31]_i_10_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[31]_i_10_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[31]_i_10_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[31]_i_10_n_6\,
O(0) => \cr_int_reg[31]_i_10_n_7\,
S(3 downto 2) => B"01",
S(1) => \cr_int[31]_i_28_n_0\,
S(0) => \cr_int[31]_i_29_n_0\
);
\cr_int_reg[31]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_64_n_0\,
CO(3) => \cr_int_reg[31]_i_27_n_0\,
CO(2) => \cr_int_reg[31]_i_27_n_1\,
CO(1) => \cr_int_reg[31]_i_27_n_2\,
CO(0) => \cr_int_reg[31]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[31]_i_27_n_4\,
O(2) => \cr_int_reg[31]_i_27_n_5\,
O(1) => \cr_int_reg[31]_i_27_n_6\,
O(0) => \cr_int_reg[31]_i_27_n_7\,
S(3) => \cr_int[31]_i_65_n_0\,
S(2) => \cr_int[31]_i_66_n_0\,
S(1) => \cr_int[31]_i_67_n_0\,
S(0) => \cr_int[31]_i_68_n_0\
);
\cr_int_reg[31]_i_54\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[23]_i_31_n_0\,
CO(3 downto 1) => \NLW_cr_int_reg[31]_i_54_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cr_int_reg[31]_i_54_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[31]_i_54_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[31]_i_54_n_6\,
O(0) => \cr_int_reg[31]_i_54_n_7\,
S(3 downto 2) => B"00",
S(1) => \cr_int[31]_i_98_n_0\,
S(0) => \cr_int[31]_i_99_n_0\
);
\cr_int_reg[31]_i_64\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_37_n_0\,
CO(3) => \cr_int_reg[31]_i_64_n_0\,
CO(2) => \cr_int_reg[31]_i_64_n_1\,
CO(1) => \cr_int_reg[31]_i_64_n_2\,
CO(0) => \cr_int_reg[31]_i_64_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[31]_i_64_n_4\,
O(2) => \cr_int_reg[31]_i_64_n_5\,
O(1) => \cr_int_reg[31]_i_64_n_6\,
O(0) => \cr_int_reg[31]_i_64_n_7\,
S(3) => \cr_int[31]_i_104_n_0\,
S(2) => \cr_int[31]_i_105_n_0\,
S(1) => \cr_int[31]_i_106_n_0\,
S(0) => \cr_int[31]_i_107_n_0\
);
\cr_int_reg[7]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[7]_i_24_n_0\,
CO(2) => \cr_int_reg[7]_i_24_n_1\,
CO(1) => \cr_int_reg[7]_i_24_n_2\,
CO(0) => \cr_int_reg[7]_i_24_n_3\,
CYINIT => \cr_int[7]_i_29_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[7]_i_24_n_4\,
O(2) => \cr_int_reg[7]_i_24_n_5\,
O(1) => \cr_int_reg[7]_i_24_n_6\,
O(0) => \cr_int_reg[7]_i_24_n_7\,
S(3) => \cr_int[7]_i_30_n_0\,
S(2) => \cr_int[7]_i_31_n_0\,
S(1) => \cr_int[7]_i_32_n_0\,
S(0) => \cr_int[7]_i_33_n_0\
);
\y_int[11]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[11]_i_54_n_0\
);
\y_int[11]_i_55\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_6\,
O => \y_int[11]_i_55_n_0\
);
\y_int[11]_i_56\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_7\,
O => \y_int[11]_i_56_n_0\
);
\y_int[11]_i_57\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_21_n_4\,
O => \y_int[11]_i_57_n_0\
);
\y_int[15]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[15]_i_36_n_0\
);
\y_int[15]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[15]_i_37_n_0\
);
\y_int[15]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[15]_i_38_n_0\
);
\y_int[15]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[15]_i_39_n_0\
);
\y_int[15]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_68,
O => \y_int[15]_i_44_n_0\
);
\y_int[15]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_69,
O => \y_int[15]_i_45_n_0\
);
\y_int[15]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_70,
O => \y_int[15]_i_46_n_0\
);
\y_int[15]_i_47\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_71,
O => \y_int[15]_i_47_n_0\
);
\y_int[19]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[19]_i_36_n_0\
);
\y_int[19]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[19]_i_37_n_0\
);
\y_int[19]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[19]_i_38_n_0\
);
\y_int[19]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[19]_i_39_n_0\
);
\y_int[19]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[19]_i_24_n_5\,
O => \y_int[19]_i_40_n_0\
);
\y_int[19]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[19]_i_24_n_6\,
O => \y_int[19]_i_41_n_0\
);
\y_int[19]_i_42\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[19]_i_24_n_7\,
O => \y_int[19]_i_42_n_0\
);
\y_int[19]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[15]_i_24_n_4\,
O => \y_int[19]_i_43_n_0\
);
\y_int[19]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_64,
O => \y_int[19]_i_44_n_0\
);
\y_int[19]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_65,
O => \y_int[19]_i_45_n_0\
);
\y_int[19]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_66,
O => \y_int[19]_i_46_n_0\
);
\y_int[19]_i_47\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_67,
O => \y_int[19]_i_47_n_0\
);
\y_int[23]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_50_n_0\
);
\y_int[23]_i_58\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_58_n_0\
);
\y_int[23]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_59_n_0\
);
\y_int[23]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_60_n_0\
);
\y_int[23]_i_61\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_61_n_0\
);
\y_int[31]_i_100\: unisim.vcomponents.LUT4
generic map(
INIT => X"D22D"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
I2 => rgb888(4),
I3 => rgb888(2),
O => \y_int[31]_i_100_n_0\
);
\y_int[31]_i_102\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \y_int[31]_i_102_n_0\
);
\y_int[31]_i_103\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(15),
I1 => rgb888(14),
O => \y_int[31]_i_103_n_0\
);
\y_int[31]_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(15),
I1 => \y_int[31]_i_56_n_0\,
O => \y_int[31]_i_22_n_0\
);
\y_int[31]_i_23\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => rgb888(15),
I1 => \y_int[31]_i_57_n_0\,
I2 => rgb888(14),
O => \y_int[31]_i_23_n_0\
);
\y_int[31]_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(15),
I1 => \y_int[31]_i_56_n_0\,
O => \y_int[31]_i_24_n_0\
);
\y_int[31]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \y_int[31]_i_25_n_0\
);
\y_int[31]_i_26\: unisim.vcomponents.LUT3
generic map(
INIT => X"15"
)
port map (
I0 => rgb888(15),
I1 => rgb888(14),
I2 => \y_int[31]_i_57_n_0\,
O => \y_int[31]_i_26_n_0\
);
\y_int[31]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_32_n_7\,
O => \y_int[31]_i_28_n_0\
);
\y_int[31]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_35_n_4\,
O => \y_int[31]_i_29_n_0\
);
\y_int[31]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_58,
O => \y_int[31]_i_38_n_0\
);
\y_int[31]_i_39\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_59,
O => \y_int[31]_i_39_n_0\
);
\y_int[31]_i_48\: unisim.vcomponents.LUT4
generic map(
INIT => X"1002"
)
port map (
I0 => rgb888(14),
I1 => rgb888(15),
I2 => \y_int[31]_i_80_n_0\,
I3 => rgb888(13),
O => \y_int[31]_i_48_n_0\
);
\y_int[31]_i_49\: unisim.vcomponents.LUT5
generic map(
INIT => X"81560042"
)
port map (
I0 => rgb888(13),
I1 => rgb888(12),
I2 => \y_int[31]_i_81_n_0\,
I3 => rgb888(15),
I4 => \y_int_reg[31]_i_82_n_1\,
O => \y_int[31]_i_49_n_0\
);
\y_int[31]_i_50\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A88A80808008"
)
port map (
I0 => \y_int[31]_i_83_n_0\,
I1 => rgb888(14),
I2 => rgb888(11),
I3 => rgb888(9),
I4 => rgb888(10),
I5 => \y_int_reg[31]_i_82_n_6\,
O => \y_int[31]_i_50_n_0\
);
\y_int[31]_i_51\: unisim.vcomponents.LUT6
generic map(
INIT => X"9696966996000069"
)
port map (
I0 => rgb888(14),
I1 => rgb888(11),
I2 => \y_int_reg[31]_i_82_n_6\,
I3 => rgb888(9),
I4 => rgb888(10),
I5 => rgb888(13),
O => \y_int[31]_i_51_n_0\
);
\y_int[31]_i_52\: unisim.vcomponents.LUT4
generic map(
INIT => X"6559"
)
port map (
I0 => \y_int[31]_i_48_n_0\,
I1 => rgb888(15),
I2 => \y_int[31]_i_57_n_0\,
I3 => rgb888(14),
O => \y_int[31]_i_52_n_0\
);
\y_int[31]_i_53\: unisim.vcomponents.LUT6
generic map(
INIT => X"6CCCCCC9CCCCC993"
)
port map (
I0 => \y_int_reg[31]_i_82_n_1\,
I1 => rgb888(14),
I2 => rgb888(12),
I3 => \y_int[31]_i_81_n_0\,
I4 => rgb888(13),
I5 => rgb888(15),
O => \y_int[31]_i_53_n_0\
);
\y_int[31]_i_54\: unisim.vcomponents.LUT6
generic map(
INIT => X"366C6CC96CC9C993"
)
port map (
I0 => \y_int[31]_i_84_n_0\,
I1 => rgb888(13),
I2 => \y_int[31]_i_81_n_0\,
I3 => rgb888(12),
I4 => rgb888(15),
I5 => \y_int_reg[31]_i_82_n_1\,
O => \y_int[31]_i_54_n_0\
);
\y_int[31]_i_55\: unisim.vcomponents.LUT5
generic map(
INIT => X"99969666"
)
port map (
I0 => \y_int[31]_i_51_n_0\,
I1 => \y_int[31]_i_83_n_0\,
I2 => \y_int_reg[31]_i_82_n_6\,
I3 => \y_int[31]_i_85_n_0\,
I4 => rgb888(14),
O => \y_int[31]_i_55_n_0\
);
\y_int[31]_i_56\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => rgb888(13),
I1 => rgb888(11),
I2 => rgb888(9),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \y_int[31]_i_56_n_0\
);
\y_int[31]_i_57\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => rgb888(12),
I1 => rgb888(10),
I2 => rgb888(9),
I3 => rgb888(11),
I4 => rgb888(13),
O => \y_int[31]_i_57_n_0\
);
\y_int[31]_i_58\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_35_n_5\,
O => \y_int[31]_i_58_n_0\
);
\y_int[31]_i_59\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_35_n_6\,
O => \y_int[31]_i_59_n_0\
);
\y_int[31]_i_60\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_35_n_7\,
O => \y_int[31]_i_60_n_0\
);
\y_int[31]_i_61\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[19]_i_24_n_4\,
O => \y_int[31]_i_61_n_0\
);
\y_int[31]_i_72\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(5),
I1 => rgb888(7),
O => \y_int[31]_i_72_n_0\
);
\y_int[31]_i_73\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(6),
I1 => rgb888(7),
O => \y_int[31]_i_73_n_0\
);
\y_int[31]_i_74\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => rgb888(7),
I1 => rgb888(5),
I2 => rgb888(6),
O => \y_int[31]_i_74_n_0\
);
\y_int[31]_i_76\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_60,
O => \y_int[31]_i_76_n_0\
);
\y_int[31]_i_77\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_61,
O => \y_int[31]_i_77_n_0\
);
\y_int[31]_i_78\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_62,
O => \y_int[31]_i_78_n_0\
);
\y_int[31]_i_79\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_63,
O => \y_int[31]_i_79_n_0\
);
\y_int[31]_i_80\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => rgb888(11),
I1 => rgb888(9),
I2 => rgb888(10),
I3 => rgb888(12),
O => \y_int[31]_i_80_n_0\
);
\y_int[31]_i_81\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => rgb888(10),
I1 => rgb888(9),
I2 => rgb888(11),
O => \y_int[31]_i_81_n_0\
);
\y_int[31]_i_83\: unisim.vcomponents.LUT6
generic map(
INIT => X"6666666999999996"
)
port map (
I0 => \y_int_reg[31]_i_82_n_1\,
I1 => rgb888(15),
I2 => rgb888(11),
I3 => rgb888(9),
I4 => rgb888(10),
I5 => rgb888(12),
O => \y_int[31]_i_83_n_0\
);
\y_int[31]_i_84\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEABA802"
)
port map (
I0 => \y_int_reg[31]_i_82_n_6\,
I1 => rgb888(10),
I2 => rgb888(9),
I3 => rgb888(11),
I4 => rgb888(14),
O => \y_int[31]_i_84_n_0\
);
\y_int[31]_i_85\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => rgb888(10),
I1 => rgb888(9),
I2 => rgb888(11),
O => \y_int[31]_i_85_n_0\
);
\y_int[31]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(4),
I1 => rgb888(6),
O => \y_int[31]_i_93_n_0\
);
\y_int[31]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(3),
I1 => rgb888(5),
O => \y_int[31]_i_94_n_0\
);
\y_int[31]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(2),
I1 => rgb888(4),
O => \y_int[31]_i_95_n_0\
);
\y_int[31]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(1),
I1 => rgb888(3),
O => \y_int[31]_i_96_n_0\
);
\y_int[31]_i_97\: unisim.vcomponents.LUT4
generic map(
INIT => X"D22D"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
I2 => rgb888(7),
I3 => rgb888(5),
O => \y_int[31]_i_97_n_0\
);
\y_int[31]_i_98\: unisim.vcomponents.LUT4
generic map(
INIT => X"D22D"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
I2 => rgb888(6),
I3 => rgb888(4),
O => \y_int[31]_i_98_n_0\
);
\y_int[31]_i_99\: unisim.vcomponents.LUT4
generic map(
INIT => X"D22D"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
I2 => rgb888(5),
I3 => rgb888(3),
O => \y_int[31]_i_99_n_0\
);
\y_int[3]_i_37\: unisim.vcomponents.LUT4
generic map(
INIT => X"8228"
)
port map (
I0 => \y_int_reg[31]_i_82_n_7\,
I1 => rgb888(9),
I2 => rgb888(10),
I3 => rgb888(13),
O => \y_int[3]_i_37_n_0\
);
\y_int[3]_i_38\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(9),
I1 => rgb888(10),
I2 => rgb888(13),
I3 => \y_int_reg[31]_i_82_n_7\,
O => \y_int[3]_i_38_n_0\
);
\y_int[3]_i_39\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \y_int_reg[3]_i_40_n_4\,
I1 => rgb888(9),
I2 => rgb888(12),
O => \y_int[3]_i_39_n_0\
);
\y_int[3]_i_41\: unisim.vcomponents.LUT5
generic map(
INIT => X"99969699"
)
port map (
I0 => \y_int[3]_i_37_n_0\,
I1 => \y_int[3]_i_79_n_0\,
I2 => rgb888(13),
I3 => rgb888(10),
I4 => rgb888(9),
O => \y_int[3]_i_41_n_0\
);
\y_int[3]_i_42\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669696969696996"
)
port map (
I0 => \y_int_reg[31]_i_82_n_7\,
I1 => rgb888(13),
I2 => rgb888(10),
I3 => rgb888(12),
I4 => \y_int_reg[3]_i_40_n_4\,
I5 => rgb888(9),
O => \y_int[3]_i_42_n_0\
);
\y_int[3]_i_43\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696969"
)
port map (
I0 => rgb888(12),
I1 => rgb888(9),
I2 => \y_int_reg[3]_i_40_n_4\,
I3 => rgb888(11),
I4 => rgb888(8),
O => \y_int[3]_i_43_n_0\
);
\y_int[3]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(8),
I1 => rgb888(11),
I2 => \y_int_reg[3]_i_40_n_5\,
O => \y_int[3]_i_44_n_0\
);
\y_int[3]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_19_n_5\,
O => \y_int[3]_i_46_n_0\
);
\y_int[3]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_19_n_6\,
O => \y_int[3]_i_47_n_0\
);
\y_int[3]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_19_n_7\,
O => \y_int[3]_i_48_n_0\
);
\y_int[3]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_51,
O => \y_int[3]_i_49_n_0\
);
\y_int[3]_i_75\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
O => \y_int[3]_i_75_n_0\
);
\y_int[3]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(12),
I1 => rgb888(14),
O => \y_int[3]_i_76_n_0\
);
\y_int[3]_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(11),
I1 => rgb888(13),
O => \y_int[3]_i_77_n_0\
);
\y_int[3]_i_78\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(10),
I1 => rgb888(12),
O => \y_int[3]_i_78_n_0\
);
\y_int[3]_i_79\: unisim.vcomponents.LUT5
generic map(
INIT => X"A95656A9"
)
port map (
I0 => \y_int_reg[31]_i_82_n_6\,
I1 => rgb888(10),
I2 => rgb888(9),
I3 => rgb888(11),
I4 => rgb888(14),
O => \y_int[3]_i_79_n_0\
);
\y_int[3]_i_80\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_52,
O => \y_int[3]_i_80_n_0\
);
\y_int[3]_i_81\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_53,
O => \y_int[3]_i_81_n_0\
);
\y_int[3]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_54,
O => \y_int[3]_i_82_n_0\
);
\y_int[3]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_70_n_6\,
O => \y_int[3]_i_83_n_0\
);
\y_int[3]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(9),
I1 => rgb888(11),
O => \y_int[3]_i_93_n_0\
);
\y_int[3]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(8),
I1 => rgb888(10),
O => \y_int[3]_i_94_n_0\
);
\y_int[3]_i_95\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(9),
O => \y_int[3]_i_95_n_0\
);
\y_int[3]_i_96\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(8),
O => \y_int[3]_i_96_n_0\
);
\y_int[7]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_21_n_5\,
O => \y_int[7]_i_25_n_0\
);
\y_int[7]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_21_n_6\,
O => \y_int[7]_i_26_n_0\
);
\y_int[7]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_21_n_7\,
O => \y_int[7]_i_27_n_0\
);
\y_int[7]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_19_n_4\,
O => \y_int[7]_i_28_n_0\
);
\y_int_reg[11]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[7]_i_23_n_0\,
CO(3) => \y_int_reg[11]_i_27_n_0\,
CO(2) => \y_int_reg[11]_i_27_n_1\,
CO(1) => \y_int_reg[11]_i_27_n_2\,
CO(0) => \y_int_reg[11]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[11]_i_27_n_4\,
O(2) => \y_int_reg[11]_i_27_n_5\,
O(1) => \y_int_reg[11]_i_27_n_6\,
O(0) => \y_int_reg[11]_i_27_n_7\,
S(3) => \y_int[11]_i_54_n_0\,
S(2) => \y_int[11]_i_55_n_0\,
S(1) => \y_int[11]_i_56_n_0\,
S(0) => \y_int[11]_i_57_n_0\
);
\y_int_reg[15]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_27_n_0\,
CO(3) => \y_int_reg[15]_i_24_n_0\,
CO(2) => \y_int_reg[15]_i_24_n_1\,
CO(1) => \y_int_reg[15]_i_24_n_2\,
CO(0) => \y_int_reg[15]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[15]_i_24_n_4\,
O(2) => \y_int_reg[15]_i_24_n_5\,
O(1) => \y_int_reg[15]_i_24_n_6\,
O(0) => \y_int_reg[15]_i_24_n_7\,
S(3) => \y_int[15]_i_36_n_0\,
S(2) => \y_int[15]_i_37_n_0\,
S(1) => \y_int[15]_i_38_n_0\,
S(0) => \y_int[15]_i_39_n_0\
);
\y_int_reg[15]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_81,
CO(3) => \y_int_reg[15]_i_34_n_0\,
CO(2) => \y_int_reg[15]_i_34_n_1\,
CO(1) => \y_int_reg[15]_i_34_n_2\,
CO(0) => \y_int_reg[15]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(12 downto 9),
S(3) => \y_int[15]_i_44_n_0\,
S(2) => \y_int[15]_i_45_n_0\,
S(1) => \y_int[15]_i_46_n_0\,
S(0) => \y_int[15]_i_47_n_0\
);
\y_int_reg[19]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_24_n_0\,
CO(3) => \y_int_reg[19]_i_24_n_0\,
CO(2) => \y_int_reg[19]_i_24_n_1\,
CO(1) => \y_int_reg[19]_i_24_n_2\,
CO(0) => \y_int_reg[19]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[19]_i_24_n_4\,
O(2) => \y_int_reg[19]_i_24_n_5\,
O(1) => \y_int_reg[19]_i_24_n_6\,
O(0) => \y_int_reg[19]_i_24_n_7\,
S(3) => \y_int[19]_i_36_n_0\,
S(2) => \y_int[19]_i_37_n_0\,
S(1) => \y_int[19]_i_38_n_0\,
S(0) => \y_int[19]_i_39_n_0\
);
\y_int_reg[19]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_79,
CO(3) => \y_int_reg[19]_i_33_n_0\,
CO(2) => \y_int_reg[19]_i_33_n_1\,
CO(1) => \y_int_reg[19]_i_33_n_2\,
CO(0) => \y_int_reg[19]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[19]_i_33_n_4\,
O(2) => \y_int_reg[19]_i_33_n_5\,
O(1) => \y_int_reg[19]_i_33_n_6\,
O(0) => \y_int_reg[19]_i_33_n_7\,
S(3) => \y_int[19]_i_40_n_0\,
S(2) => \y_int[19]_i_41_n_0\,
S(1) => \y_int[19]_i_42_n_0\,
S(0) => \y_int[19]_i_43_n_0\
);
\y_int_reg[19]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_34_n_0\,
CO(3) => \y_int_reg[19]_i_34_n_0\,
CO(2) => \y_int_reg[19]_i_34_n_1\,
CO(1) => \y_int_reg[19]_i_34_n_2\,
CO(0) => \y_int_reg[19]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(16 downto 13),
S(3) => \y_int[19]_i_44_n_0\,
S(2) => \y_int[19]_i_45_n_0\,
S(1) => \y_int[19]_i_46_n_0\,
S(0) => \y_int[19]_i_47_n_0\
);
\y_int_reg[23]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_35_n_0\,
CO(3 downto 0) => \NLW_y_int_reg[23]_i_32_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_y_int_reg[23]_i_32_O_UNCONNECTED\(3 downto 1),
O(0) => \y_int_reg[23]_i_32_n_7\,
S(3 downto 1) => B"000",
S(0) => \y_int[23]_i_50_n_0\
);
\y_int_reg[23]_i_35\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_24_n_0\,
CO(3) => \y_int_reg[23]_i_35_n_0\,
CO(2) => \y_int_reg[23]_i_35_n_1\,
CO(1) => \y_int_reg[23]_i_35_n_2\,
CO(0) => \y_int_reg[23]_i_35_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[23]_i_35_n_4\,
O(2) => \y_int_reg[23]_i_35_n_5\,
O(1) => \y_int_reg[23]_i_35_n_6\,
O(0) => \y_int_reg[23]_i_35_n_7\,
S(3) => \y_int[23]_i_58_n_0\,
S(2) => \y_int[23]_i_59_n_0\,
S(1) => \y_int[23]_i_60_n_0\,
S(0) => \y_int[23]_i_61_n_0\
);
\y_int_reg[31]_i_10\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_27_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_10_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_10_n_1\,
CO(1) => \NLW_y_int_reg[31]_i_10_CO_UNCONNECTED\(1),
CO(0) => \y_int_reg[31]_i_10_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[31]_i_10_O_UNCONNECTED\(3 downto 2),
O(1) => \y_int_reg[31]_i_10_n_6\,
O(0) => \y_int_reg[31]_i_10_n_7\,
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_28_n_0\,
S(0) => \y_int[31]_i_29_n_0\
);
\y_int_reg[31]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_37_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_12_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_12_n_1\,
CO(1) => \NLW_y_int_reg[31]_i_12_CO_UNCONNECTED\(1),
CO(0) => \y_int_reg[31]_i_12_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[31]_i_12_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => y_int_reg2(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_38_n_0\,
S(0) => \y_int[31]_i_39_n_0\
);
\y_int_reg[31]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_19_n_0\,
CO(3) => \y_int_reg[31]_i_21_n_0\,
CO(2) => \y_int_reg[31]_i_21_n_1\,
CO(1) => \y_int_reg[31]_i_21_n_2\,
CO(0) => \y_int_reg[31]_i_21_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_48_n_0\,
DI(2) => \y_int[31]_i_49_n_0\,
DI(1) => \y_int[31]_i_50_n_0\,
DI(0) => \y_int[31]_i_51_n_0\,
O(3) => \y_int_reg[31]_i_21_n_4\,
O(2) => \y_int_reg[31]_i_21_n_5\,
O(1) => \y_int_reg[31]_i_21_n_6\,
O(0) => \y_int_reg[31]_i_21_n_7\,
S(3) => \y_int[31]_i_52_n_0\,
S(2) => \y_int[31]_i_53_n_0\,
S(1) => \y_int[31]_i_54_n_0\,
S(0) => \y_int[31]_i_55_n_0\
);
\y_int_reg[31]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_33_n_0\,
CO(3) => \y_int_reg[31]_i_27_n_0\,
CO(2) => \y_int_reg[31]_i_27_n_1\,
CO(1) => \y_int_reg[31]_i_27_n_2\,
CO(0) => \y_int_reg[31]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[31]_i_27_n_4\,
O(2) => \y_int_reg[31]_i_27_n_5\,
O(1) => \y_int_reg[31]_i_27_n_6\,
O(0) => \y_int_reg[31]_i_27_n_7\,
S(3) => \y_int[31]_i_58_n_0\,
S(2) => \y_int[31]_i_59_n_0\,
S(1) => \y_int[31]_i_60_n_0\,
S(0) => \y_int[31]_i_61_n_0\
);
\y_int_reg[31]_i_31\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_71_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[31]_i_31_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[31]_i_31_n_2\,
CO(0) => \y_int_reg[31]_i_31_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => rgb888(6),
DI(0) => \y_int[31]_i_72_n_0\,
O(3) => \NLW_y_int_reg[31]_i_31_O_UNCONNECTED\(3),
O(2) => \y_int_reg[31]_i_31_n_5\,
O(1) => \y_int_reg[31]_i_31_n_6\,
O(0) => \y_int_reg[31]_i_31_n_7\,
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_73_n_0\,
S(0) => \y_int[31]_i_74_n_0\
);
\y_int_reg[31]_i_37\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_34_n_0\,
CO(3) => \y_int_reg[31]_i_37_n_0\,
CO(2) => \y_int_reg[31]_i_37_n_1\,
CO(1) => \y_int_reg[31]_i_37_n_2\,
CO(0) => \y_int_reg[31]_i_37_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(20 downto 17),
S(3) => \y_int[31]_i_76_n_0\,
S(2) => \y_int[31]_i_77_n_0\,
S(1) => \y_int[31]_i_78_n_0\,
S(0) => \y_int[31]_i_79_n_0\
);
\y_int_reg[31]_i_71\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_80,
CO(3) => \y_int_reg[31]_i_71_n_0\,
CO(2) => \y_int_reg[31]_i_71_n_1\,
CO(1) => \y_int_reg[31]_i_71_n_2\,
CO(0) => \y_int_reg[31]_i_71_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_93_n_0\,
DI(2) => \y_int[31]_i_94_n_0\,
DI(1) => \y_int[31]_i_95_n_0\,
DI(0) => \y_int[31]_i_96_n_0\,
O(3) => \y_int_reg[31]_i_71_n_4\,
O(2) => \y_int_reg[31]_i_71_n_5\,
O(1) => \y_int_reg[31]_i_71_n_6\,
O(0) => \y_int_reg[31]_i_71_n_7\,
S(3) => \y_int[31]_i_97_n_0\,
S(2) => \y_int[31]_i_98_n_0\,
S(1) => \y_int[31]_i_99_n_0\,
S(0) => \y_int[31]_i_100_n_0\
);
\y_int_reg[31]_i_82\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_40_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_82_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_82_n_1\,
CO(1) => \NLW_y_int_reg[31]_i_82_CO_UNCONNECTED\(1),
CO(0) => \y_int_reg[31]_i_82_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1 downto 0) => rgb888(15 downto 14),
O(3 downto 2) => \NLW_y_int_reg[31]_i_82_O_UNCONNECTED\(3 downto 2),
O(1) => \y_int_reg[31]_i_82_n_6\,
O(0) => \y_int_reg[31]_i_82_n_7\,
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_102_n_0\,
S(0) => \y_int[31]_i_103_n_0\
);
\y_int_reg[31]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_21_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[31]_i_9_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[31]_i_9_n_2\,
CO(0) => \y_int_reg[31]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \y_int[31]_i_22_n_0\,
DI(0) => \y_int[31]_i_23_n_0\,
O(3) => \NLW_y_int_reg[31]_i_9_O_UNCONNECTED\(3),
O(2) => \y_int_reg[31]_i_9_n_5\,
O(1) => \y_int_reg[31]_i_9_n_6\,
O(0) => \y_int_reg[31]_i_9_n_7\,
S(3) => '0',
S(2) => \y_int[31]_i_24_n_0\,
S(1) => \y_int[31]_i_25_n_0\,
S(0) => \y_int[31]_i_26_n_0\
);
\y_int_reg[3]_i_19\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_78,
CO(3) => \y_int_reg[3]_i_19_n_0\,
CO(2) => \y_int_reg[3]_i_19_n_1\,
CO(1) => \y_int_reg[3]_i_19_n_2\,
CO(0) => \y_int_reg[3]_i_19_n_3\,
CYINIT => '0',
DI(3) => \y_int[3]_i_37_n_0\,
DI(2) => \y_int[3]_i_38_n_0\,
DI(1) => \y_int[3]_i_39_n_0\,
DI(0) => \y_int_reg[3]_i_40_n_5\,
O(3) => \y_int_reg[3]_i_19_n_4\,
O(2) => \y_int_reg[3]_i_19_n_5\,
O(1) => \y_int_reg[3]_i_19_n_6\,
O(0) => \y_int_reg[3]_i_19_n_7\,
S(3) => \y_int[3]_i_41_n_0\,
S(2) => \y_int[3]_i_42_n_0\,
S(1) => \y_int[3]_i_43_n_0\,
S(0) => \y_int[3]_i_44_n_0\
);
\y_int_reg[3]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_45_n_0\,
CO(3) => \y_int_reg[3]_i_20_n_0\,
CO(2) => \y_int_reg[3]_i_20_n_1\,
CO(1) => \y_int_reg[3]_i_20_n_2\,
CO(0) => \y_int_reg[3]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[3]_i_20_n_4\,
O(2) => \y_int_reg[3]_i_20_n_5\,
O(1 downto 0) => \NLW_y_int_reg[3]_i_20_O_UNCONNECTED\(1 downto 0),
S(3) => \y_int[3]_i_46_n_0\,
S(2) => \y_int[3]_i_47_n_0\,
S(1) => \y_int[3]_i_48_n_0\,
S(0) => \y_int[3]_i_49_n_0\
);
\y_int_reg[3]_i_40\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_70_n_0\,
CO(3) => \y_int_reg[3]_i_40_n_0\,
CO(2) => \y_int_reg[3]_i_40_n_1\,
CO(1) => \y_int_reg[3]_i_40_n_2\,
CO(0) => \y_int_reg[3]_i_40_n_3\,
CYINIT => '0',
DI(3) => rgb888(15),
DI(2 downto 0) => rgb888(12 downto 10),
O(3) => \y_int_reg[3]_i_40_n_4\,
O(2) => \y_int_reg[3]_i_40_n_5\,
O(1) => \y_int_reg[3]_i_40_n_6\,
O(0) => \y_int_reg[3]_i_40_n_7\,
S(3) => \y_int[3]_i_75_n_0\,
S(2) => \y_int[3]_i_76_n_0\,
S(1) => \y_int[3]_i_77_n_0\,
S(0) => \y_int[3]_i_78_n_0\
);
\y_int_reg[3]_i_45\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_45_n_0\,
CO(2) => \y_int_reg[3]_i_45_n_1\,
CO(1) => \y_int_reg[3]_i_45_n_2\,
CO(0) => \y_int_reg[3]_i_45_n_3\,
CYINIT => \cb_int[3]_i_84_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_y_int_reg[3]_i_45_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[3]_i_80_n_0\,
S(2) => \y_int[3]_i_81_n_0\,
S(1) => \y_int[3]_i_82_n_0\,
S(0) => \y_int[3]_i_83_n_0\
);
\y_int_reg[3]_i_70\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_70_n_0\,
CO(2) => \y_int_reg[3]_i_70_n_1\,
CO(1) => \y_int_reg[3]_i_70_n_2\,
CO(0) => \y_int_reg[3]_i_70_n_3\,
CYINIT => '0',
DI(3 downto 2) => rgb888(9 downto 8),
DI(1 downto 0) => B"01",
O(3) => \y_int_reg[3]_i_70_n_4\,
O(2) => \y_int_reg[3]_i_70_n_5\,
O(1) => \y_int_reg[3]_i_70_n_6\,
O(0) => \NLW_y_int_reg[3]_i_70_O_UNCONNECTED\(0),
S(3) => \y_int[3]_i_93_n_0\,
S(2) => \y_int[3]_i_94_n_0\,
S(1) => \y_int[3]_i_95_n_0\,
S(0) => \y_int[3]_i_96_n_0\
);
\y_int_reg[7]_i_23\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_20_n_0\,
CO(3) => \y_int_reg[7]_i_23_n_0\,
CO(2) => \y_int_reg[7]_i_23_n_1\,
CO(1) => \y_int_reg[7]_i_23_n_2\,
CO(0) => \y_int_reg[7]_i_23_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[7]_i_23_n_4\,
O(2) => \y_int_reg[7]_i_23_n_5\,
O(1) => \y_int_reg[7]_i_23_n_6\,
O(0) => \y_int_reg[7]_i_23_n_7\,
S(3) => \y_int[7]_i_25_n_0\,
S(2) => \y_int[7]_i_26_n_0\,
S(1) => \y_int[7]_i_27_n_0\,
S(0) => \y_int[7]_i_28_n_0\
);
end STRUCTURE;
| mit | e3b42195c87596d0330cba44694193f9 | 0.480034 | 2.231649 | false | false | false | false |
CampbellGroup/fpga | ltc1450/clock.vhd | 1 | 589 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY signal_generator IS
PORT (clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_out : OUT STD_LOGIC);
END signal_generator;
ARCHITECTURE behavior of signal_generator IS
BEGIN
PROCESS(reset,clk)
VARIABLE count : integer;
BEGIN
IF (reset = '0') THEN
clk_out<='0';
count:=0;
ELSIF (clk'event AND clk='1') then
IF (count=24999999) then --((input clock)/2-1)
clk_out<=NOT(clk_out);
count:=0;
ELSE
count:=count+1;
END IF;
END IF;
END PROCESS;
END behavior; | mit | f5b43170ca3603cab79b7677b9127611 | 0.684211 | 2.752336 | false | false | false | false |
SoCdesign/audiomixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/adau1761_audio_v1_00_a/hdl/vhdl/adau1761_audio.vhd | 1 | 18,133 | ------------------------------------------------------------------------------
-- adau1761_audio.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: adau1761_audio.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Tue May 20 11:28:03 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library adau1761_audio_v1_00_a;
use adau1761_audio_v1_00_a.user_logic;
library unisim;
use unisim.vcomponents.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity adau1761_audio is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
clk_100 : IN std_logic;
clk_48_o : OUT std_logic;
AC_GPIO1 : IN std_logic;
AC_GPIO2 : IN std_logic;
AC_GPIO3 : IN std_logic;
--AC_SDA : INOUT std_logic;
AC_SDA_I : IN std_logic;
AC_SDA_O : OUT std_logic;
AC_SDA_T : OUT std_logic;
AUDIO_OUT_L : OUT STD_LOGIC_VECTOR(23 downto 0);
AUDIO_OUT_R : OUT STD_LOGIC_VECTOR(23 downto 0);
AUDIO_IN_L : IN STD_LOGIC_VECTOR(23 downto 0);
AUDIO_IN_R : IN STD_LOGIC_VECTOR(23 downto 0);
AC_ADR0 : OUT std_logic;
AC_ADR1 : OUT std_logic;
AC_GPIO0 : OUT std_logic;
AC_MCLK : OUT std_logic;
AC_SCK : OUT std_logic;
new_sample : OUT std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity adau1761_audio;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of adau1761_audio is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 2;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
signal AC_SDA_tmp : std_logic;
signal clk_48_s : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity adau1761_audio_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
clk_100 => clk_100,
clk_48_o => clk_48_s,
AC_ADR0 => AC_ADR0,
AC_ADR1 => AC_ADR1,
AC_GPIO0 => AC_GPIO0,
AC_GPIO1 => AC_GPIO1,
AC_GPIO2 => AC_GPIO2,
AC_GPIO3 => AC_GPIO3,
AC_MCLK => AC_MCLK,
AC_SCK => AC_SCK,
new_sample => new_sample,
AC_SDA_I => AC_SDA_I,
AC_SDA_O => AC_SDA_O,
AC_SDA_T => AC_SDA_T,
--AC_SDA => AC_SDA,
AUDIO_OUT_L => AUDIO_OUT_L,
AUDIO_OUT_R => AUDIO_OUT_R,
AUDIO_IN_L => AUDIO_IN_L,
AUDIO_IN_R => AUDIO_IN_R,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
clk_48_o <= clk_48_s;
--AC_SDA_tmp <= AC_SDA_I when AC_SDA_T = '0' else 'Z';
--AC_SDA_O <= AC_SDA_tmp;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
| mit | 89cb8001b08c73e2810781ff6f43afcd | 0.466387 | 3.97131 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_clk_wiz_0_0/system_clk_wiz_0_0_sim_netlist.vhdl | 1 | 7,418 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Feb 08 00:47:16 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_clk_wiz_0_0 -prefix
-- system_clk_wiz_0_0_ system_clk_wiz_0_0_sim_netlist.vhdl
-- Design : system_clk_wiz_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz is
port (
clk_out1 : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
end system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz;
architecture STRUCTURE of system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz is
signal clk_in1_system_clk_wiz_0_0 : STD_LOGIC;
signal clk_out1_system_clk_wiz_0_0 : STD_LOGIC;
signal clkfbout_buf_system_clk_wiz_0_0 : STD_LOGIC;
signal clkfbout_system_clk_wiz_0_0 : STD_LOGIC;
signal reset_high : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_system_clk_wiz_0_0,
O => clkfbout_buf_system_clk_wiz_0_0
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_system_clk_wiz_0_0
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_out1_system_clk_wiz_0_0,
O => clk_out1
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 9.125000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 36.500000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_system_clk_wiz_0_0,
CLKFBOUT => clkfbout_system_clk_wiz_0_0,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_in1_system_clk_wiz_0_0,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_out1_system_clk_wiz_0_0,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => locked,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => reset_high
);
mmcm_adv_inst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => resetn,
O => reset_high
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clk_wiz_0_0 is
port (
clk_out1 : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_clk_wiz_0_0 : entity is true;
end system_clk_wiz_0_0;
architecture STRUCTURE of system_clk_wiz_0_0 is
begin
inst: entity work.system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1,
locked => locked,
resetn => resetn
);
end STRUCTURE;
| mit | 76a4a5997d14444721da53c0a5c3b90a | 0.634538 | 3.30276 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_multiplier_1_2/affine_block_ieee754_fp_multiplier_1_2_sim_netlist.vhdl | 1 | 200,504 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 20 13:53:00 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top affine_block_ieee754_fp_multiplier_1_2 -prefix
-- affine_block_ieee754_fp_multiplier_1_2_ affine_block_ieee754_fp_multiplier_0_0_sim_netlist.vhdl
-- Design : affine_block_ieee754_fp_multiplier_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity affine_block_ieee754_fp_multiplier_1_2_ieee754_fp_multiplier is
port (
z : out STD_LOGIC_VECTOR ( 7 downto 0 );
z_mantissa : out STD_LOGIC_VECTOR ( 22 downto 0 );
x : in STD_LOGIC_VECTOR ( 30 downto 0 );
y : in STD_LOGIC_VECTOR ( 30 downto 0 );
\y_11__s_port_\ : in STD_LOGIC
);
end affine_block_ieee754_fp_multiplier_1_2_ieee754_fp_multiplier;
architecture STRUCTURE of affine_block_ieee754_fp_multiplier_1_2_ieee754_fp_multiplier is
signal L1 : STD_LOGIC;
signal \L1_carry__0_i_1_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_2_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_3_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_4_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_5_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_6_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_7_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_8_n_0\ : STD_LOGIC;
signal \L1_carry__0_n_0\ : STD_LOGIC;
signal \L1_carry__0_n_1\ : STD_LOGIC;
signal \L1_carry__0_n_2\ : STD_LOGIC;
signal \L1_carry__0_n_3\ : STD_LOGIC;
signal \L1_carry__1_i_1_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_2_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_3_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_4_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_5_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_6_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_7_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_8_n_0\ : STD_LOGIC;
signal \L1_carry__1_n_0\ : STD_LOGIC;
signal \L1_carry__1_n_1\ : STD_LOGIC;
signal \L1_carry__1_n_2\ : STD_LOGIC;
signal \L1_carry__1_n_3\ : STD_LOGIC;
signal \L1_carry__2_i_1_n_0\ : STD_LOGIC;
signal \L1_carry__2_i_2_n_0\ : STD_LOGIC;
signal \L1_carry__2_i_3_n_0\ : STD_LOGIC;
signal \L1_carry__2_i_4_n_0\ : STD_LOGIC;
signal \L1_carry__2_i_5_n_0\ : STD_LOGIC;
signal \L1_carry__2_i_6_n_0\ : STD_LOGIC;
signal \L1_carry__2_i_7_n_0\ : STD_LOGIC;
signal \L1_carry__2_n_1\ : STD_LOGIC;
signal \L1_carry__2_n_2\ : STD_LOGIC;
signal \L1_carry__2_n_3\ : STD_LOGIC;
signal L1_carry_i_10_n_0 : STD_LOGIC;
signal L1_carry_i_11_n_0 : STD_LOGIC;
signal L1_carry_i_12_n_0 : STD_LOGIC;
signal L1_carry_i_13_n_0 : STD_LOGIC;
signal L1_carry_i_14_n_0 : STD_LOGIC;
signal L1_carry_i_15_n_0 : STD_LOGIC;
signal L1_carry_i_16_n_0 : STD_LOGIC;
signal L1_carry_i_17_n_0 : STD_LOGIC;
signal L1_carry_i_18_n_0 : STD_LOGIC;
signal L1_carry_i_19_n_0 : STD_LOGIC;
signal L1_carry_i_1_n_0 : STD_LOGIC;
signal L1_carry_i_20_n_0 : STD_LOGIC;
signal L1_carry_i_21_n_0 : STD_LOGIC;
signal L1_carry_i_22_n_0 : STD_LOGIC;
signal L1_carry_i_23_n_0 : STD_LOGIC;
signal L1_carry_i_24_n_0 : STD_LOGIC;
signal L1_carry_i_25_n_0 : STD_LOGIC;
signal L1_carry_i_26_n_0 : STD_LOGIC;
signal L1_carry_i_27_n_0 : STD_LOGIC;
signal L1_carry_i_28_n_0 : STD_LOGIC;
signal L1_carry_i_29_n_0 : STD_LOGIC;
signal L1_carry_i_2_n_0 : STD_LOGIC;
signal L1_carry_i_30_n_0 : STD_LOGIC;
signal L1_carry_i_31_n_0 : STD_LOGIC;
signal L1_carry_i_32_n_0 : STD_LOGIC;
signal L1_carry_i_33_n_0 : STD_LOGIC;
signal L1_carry_i_34_n_0 : STD_LOGIC;
signal L1_carry_i_35_n_0 : STD_LOGIC;
signal L1_carry_i_36_n_0 : STD_LOGIC;
signal L1_carry_i_37_n_0 : STD_LOGIC;
signal L1_carry_i_38_n_0 : STD_LOGIC;
signal L1_carry_i_39_n_0 : STD_LOGIC;
signal L1_carry_i_3_n_0 : STD_LOGIC;
signal L1_carry_i_40_n_0 : STD_LOGIC;
signal L1_carry_i_41_n_0 : STD_LOGIC;
signal L1_carry_i_42_n_0 : STD_LOGIC;
signal L1_carry_i_43_n_0 : STD_LOGIC;
signal L1_carry_i_44_n_0 : STD_LOGIC;
signal L1_carry_i_45_n_0 : STD_LOGIC;
signal L1_carry_i_46_n_0 : STD_LOGIC;
signal L1_carry_i_47_n_0 : STD_LOGIC;
signal L1_carry_i_48_n_0 : STD_LOGIC;
signal L1_carry_i_49_n_0 : STD_LOGIC;
signal L1_carry_i_4_n_0 : STD_LOGIC;
signal L1_carry_i_50_n_0 : STD_LOGIC;
signal L1_carry_i_51_n_0 : STD_LOGIC;
signal L1_carry_i_52_n_0 : STD_LOGIC;
signal L1_carry_i_53_n_0 : STD_LOGIC;
signal L1_carry_i_54_n_0 : STD_LOGIC;
signal L1_carry_i_5_n_0 : STD_LOGIC;
signal L1_carry_i_6_n_0 : STD_LOGIC;
signal L1_carry_i_7_n_0 : STD_LOGIC;
signal L1_carry_i_8_n_0 : STD_LOGIC;
signal L1_carry_i_9_n_0 : STD_LOGIC;
signal L1_carry_n_0 : STD_LOGIC;
signal L1_carry_n_1 : STD_LOGIC;
signal L1_carry_n_2 : STD_LOGIC;
signal L1_carry_n_3 : STD_LOGIC;
signal \_carry__0_i_1_n_0\ : STD_LOGIC;
signal \_carry__0_i_2_n_0\ : STD_LOGIC;
signal \_carry__0_i_3_n_0\ : STD_LOGIC;
signal \_carry__0_i_4_n_0\ : STD_LOGIC;
signal \_carry__0_n_0\ : STD_LOGIC;
signal \_carry__0_n_1\ : STD_LOGIC;
signal \_carry__0_n_2\ : STD_LOGIC;
signal \_carry__0_n_3\ : STD_LOGIC;
signal \_carry__0_n_4\ : STD_LOGIC;
signal \_carry__0_n_5\ : STD_LOGIC;
signal \_carry__0_n_6\ : STD_LOGIC;
signal \_carry__0_n_7\ : STD_LOGIC;
signal \_carry__1_i_1_n_0\ : STD_LOGIC;
signal \_carry__1_i_2_n_0\ : STD_LOGIC;
signal \_carry__1_i_3_n_0\ : STD_LOGIC;
signal \_carry__1_i_4_n_0\ : STD_LOGIC;
signal \_carry__1_n_0\ : STD_LOGIC;
signal \_carry__1_n_1\ : STD_LOGIC;
signal \_carry__1_n_2\ : STD_LOGIC;
signal \_carry__1_n_3\ : STD_LOGIC;
signal \_carry__1_n_4\ : STD_LOGIC;
signal \_carry__1_n_5\ : STD_LOGIC;
signal \_carry__1_n_6\ : STD_LOGIC;
signal \_carry__1_n_7\ : STD_LOGIC;
signal \_carry__2_i_1_n_0\ : STD_LOGIC;
signal \_carry__2_i_2_n_0\ : STD_LOGIC;
signal \_carry__2_i_3_n_0\ : STD_LOGIC;
signal \_carry__2_i_4_n_0\ : STD_LOGIC;
signal \_carry__2_n_0\ : STD_LOGIC;
signal \_carry__2_n_1\ : STD_LOGIC;
signal \_carry__2_n_2\ : STD_LOGIC;
signal \_carry__2_n_3\ : STD_LOGIC;
signal \_carry__2_n_4\ : STD_LOGIC;
signal \_carry__2_n_5\ : STD_LOGIC;
signal \_carry__2_n_6\ : STD_LOGIC;
signal \_carry__2_n_7\ : STD_LOGIC;
signal \_carry__3_i_1_n_0\ : STD_LOGIC;
signal \_carry__3_i_2_n_0\ : STD_LOGIC;
signal \_carry__3_i_3_n_0\ : STD_LOGIC;
signal \_carry__3_i_4_n_0\ : STD_LOGIC;
signal \_carry__3_n_0\ : STD_LOGIC;
signal \_carry__3_n_1\ : STD_LOGIC;
signal \_carry__3_n_2\ : STD_LOGIC;
signal \_carry__3_n_3\ : STD_LOGIC;
signal \_carry__3_n_4\ : STD_LOGIC;
signal \_carry__3_n_5\ : STD_LOGIC;
signal \_carry__3_n_6\ : STD_LOGIC;
signal \_carry__3_n_7\ : STD_LOGIC;
signal \_carry__4_i_1_n_0\ : STD_LOGIC;
signal \_carry__4_i_2_n_0\ : STD_LOGIC;
signal \_carry__4_i_3_n_0\ : STD_LOGIC;
signal \_carry__4_i_4_n_0\ : STD_LOGIC;
signal \_carry__4_n_0\ : STD_LOGIC;
signal \_carry__4_n_1\ : STD_LOGIC;
signal \_carry__4_n_2\ : STD_LOGIC;
signal \_carry__4_n_3\ : STD_LOGIC;
signal \_carry__4_n_4\ : STD_LOGIC;
signal \_carry__4_n_5\ : STD_LOGIC;
signal \_carry__4_n_6\ : STD_LOGIC;
signal \_carry__4_n_7\ : STD_LOGIC;
signal \_carry__5_i_1_n_0\ : STD_LOGIC;
signal \_carry__5_i_2_n_0\ : STD_LOGIC;
signal \_carry__5_i_3_n_0\ : STD_LOGIC;
signal \_carry__5_i_4_n_0\ : STD_LOGIC;
signal \_carry__5_n_0\ : STD_LOGIC;
signal \_carry__5_n_1\ : STD_LOGIC;
signal \_carry__5_n_2\ : STD_LOGIC;
signal \_carry__5_n_3\ : STD_LOGIC;
signal \_carry__5_n_4\ : STD_LOGIC;
signal \_carry__5_n_5\ : STD_LOGIC;
signal \_carry__5_n_6\ : STD_LOGIC;
signal \_carry__5_n_7\ : STD_LOGIC;
signal \_carry__6_i_1_n_0\ : STD_LOGIC;
signal \_carry__6_i_2_n_0\ : STD_LOGIC;
signal \_carry__6_n_3\ : STD_LOGIC;
signal \_carry__6_n_6\ : STD_LOGIC;
signal \_carry__6_n_7\ : STD_LOGIC;
signal \_carry_i_10_n_0\ : STD_LOGIC;
signal \_carry_i_11_n_0\ : STD_LOGIC;
signal \_carry_i_12_n_0\ : STD_LOGIC;
signal \_carry_i_13_n_0\ : STD_LOGIC;
signal \_carry_i_14_n_0\ : STD_LOGIC;
signal \_carry_i_15_n_0\ : STD_LOGIC;
signal \_carry_i_16_n_0\ : STD_LOGIC;
signal \_carry_i_17_n_0\ : STD_LOGIC;
signal \_carry_i_18_n_0\ : STD_LOGIC;
signal \_carry_i_19_n_0\ : STD_LOGIC;
signal \_carry_i_1_n_0\ : STD_LOGIC;
signal \_carry_i_20_n_0\ : STD_LOGIC;
signal \_carry_i_21_n_0\ : STD_LOGIC;
signal \_carry_i_22_n_0\ : STD_LOGIC;
signal \_carry_i_23_n_0\ : STD_LOGIC;
signal \_carry_i_24_n_0\ : STD_LOGIC;
signal \_carry_i_2_n_0\ : STD_LOGIC;
signal \_carry_i_3_n_0\ : STD_LOGIC;
signal \_carry_i_4_n_0\ : STD_LOGIC;
signal \_carry_i_6_n_0\ : STD_LOGIC;
signal \_carry_i_7_n_0\ : STD_LOGIC;
signal \_carry_i_8_n_0\ : STD_LOGIC;
signal \_carry_i_9_n_0\ : STD_LOGIC;
signal \_carry_n_0\ : STD_LOGIC;
signal \_carry_n_1\ : STD_LOGIC;
signal \_carry_n_2\ : STD_LOGIC;
signal \_carry_n_3\ : STD_LOGIC;
signal \_carry_n_4\ : STD_LOGIC;
signal \_carry_n_5\ : STD_LOGIC;
signal \_carry_n_6\ : STD_LOGIC;
signal \_carry_n_7\ : STD_LOGIC;
signal data0 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal data1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \msb1__1\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal msb1_n_106 : STD_LOGIC;
signal msb1_n_107 : STD_LOGIC;
signal msb1_n_108 : STD_LOGIC;
signal msb1_n_109 : STD_LOGIC;
signal msb1_n_110 : STD_LOGIC;
signal msb1_n_111 : STD_LOGIC;
signal msb1_n_112 : STD_LOGIC;
signal msb1_n_113 : STD_LOGIC;
signal msb1_n_114 : STD_LOGIC;
signal msb1_n_115 : STD_LOGIC;
signal msb1_n_116 : STD_LOGIC;
signal msb1_n_117 : STD_LOGIC;
signal msb1_n_118 : STD_LOGIC;
signal msb1_n_119 : STD_LOGIC;
signal msb1_n_120 : STD_LOGIC;
signal msb1_n_121 : STD_LOGIC;
signal msb1_n_122 : STD_LOGIC;
signal msb1_n_123 : STD_LOGIC;
signal msb1_n_124 : STD_LOGIC;
signal msb1_n_125 : STD_LOGIC;
signal msb1_n_126 : STD_LOGIC;
signal msb1_n_127 : STD_LOGIC;
signal msb1_n_128 : STD_LOGIC;
signal msb1_n_129 : STD_LOGIC;
signal msb1_n_130 : STD_LOGIC;
signal msb1_n_131 : STD_LOGIC;
signal msb1_n_132 : STD_LOGIC;
signal msb1_n_133 : STD_LOGIC;
signal msb1_n_134 : STD_LOGIC;
signal msb1_n_135 : STD_LOGIC;
signal msb1_n_136 : STD_LOGIC;
signal msb1_n_137 : STD_LOGIC;
signal msb1_n_138 : STD_LOGIC;
signal msb1_n_139 : STD_LOGIC;
signal msb1_n_140 : STD_LOGIC;
signal msb1_n_141 : STD_LOGIC;
signal msb1_n_142 : STD_LOGIC;
signal msb1_n_143 : STD_LOGIC;
signal msb1_n_144 : STD_LOGIC;
signal msb1_n_145 : STD_LOGIC;
signal msb1_n_146 : STD_LOGIC;
signal msb1_n_147 : STD_LOGIC;
signal msb1_n_148 : STD_LOGIC;
signal msb1_n_149 : STD_LOGIC;
signal msb1_n_150 : STD_LOGIC;
signal msb1_n_151 : STD_LOGIC;
signal msb1_n_152 : STD_LOGIC;
signal msb1_n_153 : STD_LOGIC;
signal msb1_n_58 : STD_LOGIC;
signal msb1_n_59 : STD_LOGIC;
signal msb1_n_60 : STD_LOGIC;
signal msb1_n_61 : STD_LOGIC;
signal msb1_n_62 : STD_LOGIC;
signal msb1_n_63 : STD_LOGIC;
signal msb1_n_64 : STD_LOGIC;
signal msb1_n_65 : STD_LOGIC;
signal msb1_n_66 : STD_LOGIC;
signal msb1_n_67 : STD_LOGIC;
signal msb1_n_68 : STD_LOGIC;
signal msb1_n_69 : STD_LOGIC;
signal msb1_n_70 : STD_LOGIC;
signal msb1_n_71 : STD_LOGIC;
signal msb1_n_72 : STD_LOGIC;
signal msb1_n_73 : STD_LOGIC;
signal msb1_n_74 : STD_LOGIC;
signal msb1_n_75 : STD_LOGIC;
signal msb1_n_76 : STD_LOGIC;
signal msb1_n_77 : STD_LOGIC;
signal msb1_n_78 : STD_LOGIC;
signal msb1_n_79 : STD_LOGIC;
signal msb1_n_80 : STD_LOGIC;
signal msb1_n_81 : STD_LOGIC;
signal msb1_n_82 : STD_LOGIC;
signal msb1_n_83 : STD_LOGIC;
signal msb1_n_84 : STD_LOGIC;
signal msb1_n_85 : STD_LOGIC;
signal msb1_n_86 : STD_LOGIC;
signal msb1_n_87 : STD_LOGIC;
signal msb1_n_88 : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 1 to 1 );
signal sel0 : STD_LOGIC_VECTOR ( 22 downto 0 );
signal \y_11__s_net_1\ : STD_LOGIC;
signal \z[11]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_1_n_1\ : STD_LOGIC;
signal \z[11]_INST_0_i_1_n_2\ : STD_LOGIC;
signal \z[11]_INST_0_i_1_n_3\ : STD_LOGIC;
signal \z[11]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \z[15]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[15]_INST_0_i_1_n_1\ : STD_LOGIC;
signal \z[15]_INST_0_i_1_n_2\ : STD_LOGIC;
signal \z[15]_INST_0_i_1_n_3\ : STD_LOGIC;
signal \z[15]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[15]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \z[15]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \z[19]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[19]_INST_0_i_1_n_1\ : STD_LOGIC;
signal \z[19]_INST_0_i_1_n_2\ : STD_LOGIC;
signal \z[19]_INST_0_i_1_n_3\ : STD_LOGIC;
signal \z[22]_INST_0_i_1_n_2\ : STD_LOGIC;
signal \z[22]_INST_0_i_1_n_3\ : STD_LOGIC;
signal \z[22]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_100_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_101_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_102_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_103_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_104_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_105_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_106_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_107_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_108_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_109_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_110_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_111_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_112_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_113_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_114_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_115_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_116_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_117_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_118_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_119_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_120_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_121_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_122_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_123_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_124_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_125_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_126_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_127_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_128_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_129_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_130_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_131_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_132_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_133_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_134_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_135_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_136_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_137_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_138_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_139_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_13_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_140_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_141_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_142_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_143_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_144_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_145_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_146_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_147_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_148_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_149_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_14_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_150_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_151_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_152_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_153_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_154_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_155_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_156_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_157_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_158_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_159_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_15_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_160_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_161_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_162_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_163_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_164_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_165_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_166_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_167_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_168_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_169_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_16_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_170_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_171_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_172_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_173_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_174_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_175_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_176_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_177_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_178_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_179_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_17_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_180_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_181_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_182_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_183_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_184_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_185_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_186_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_187_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_188_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_189_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_18_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_190_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_191_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_192_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_193_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_194_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_195_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_196_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_197_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_198_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_199_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_19_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_200_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_201_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_202_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_203_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_204_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_205_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_206_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_207_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_208_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_209_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_20_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_210_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_211_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_212_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_213_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_214_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_215_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_216_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_217_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_218_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_219_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_21_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_220_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_221_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_222_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_223_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_224_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_225_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_226_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_227_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_228_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_229_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_22_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_230_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_231_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_232_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_233_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_234_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_235_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_236_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_237_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_238_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_239_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_240_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_241_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_242_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_243_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_244_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_245_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_246_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_29_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_30_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_31_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_32_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_33_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_34_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_35_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_36_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_37_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_38_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_39_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_40_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_41_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_42_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_43_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_44_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_45_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_46_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_47_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_48_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_49_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_50_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_51_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_52_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_53_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_54_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_55_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_56_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_57_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_58_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_59_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_60_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_61_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_62_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_63_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_64_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_65_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_66_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_67_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_68_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_69_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_70_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_71_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_72_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_73_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_74_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_75_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_76_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_77_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_78_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_79_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_80_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_81_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_82_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_83_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_94_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_95_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_96_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_97_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_98_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_99_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_1_n_1\ : STD_LOGIC;
signal \z[3]_INST_0_i_1_n_2\ : STD_LOGIC;
signal \z[3]_INST_0_i_1_n_3\ : STD_LOGIC;
signal \z[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_12_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_1_n_1\ : STD_LOGIC;
signal \z[7]_INST_0_i_1_n_2\ : STD_LOGIC;
signal \z[7]_INST_0_i_1_n_3\ : STD_LOGIC;
signal \z[7]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_5_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_6_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_7_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_8_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_n_1\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_n_2\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_n_3\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_1_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_2_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_3_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_4_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_5_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_6_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_7_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_n_1\ : STD_LOGIC;
signal \z_exponent0__0_carry_n_2\ : STD_LOGIC;
signal \z_exponent0__0_carry_n_3\ : STD_LOGIC;
signal \z_exponent1_carry__0_n_1\ : STD_LOGIC;
signal \z_exponent1_carry__0_n_2\ : STD_LOGIC;
signal \z_exponent1_carry__0_n_3\ : STD_LOGIC;
signal \z_exponent1_carry_i_1__0_n_0\ : STD_LOGIC;
signal z_exponent1_carry_i_1_n_0 : STD_LOGIC;
signal \z_exponent1_carry_i_2__0_n_0\ : STD_LOGIC;
signal z_exponent1_carry_i_2_n_0 : STD_LOGIC;
signal \z_exponent1_carry_i_3__0_n_0\ : STD_LOGIC;
signal z_exponent1_carry_i_3_n_0 : STD_LOGIC;
signal \z_exponent1_carry_i_4__0_n_0\ : STD_LOGIC;
signal z_exponent1_carry_i_4_n_0 : STD_LOGIC;
signal z_exponent1_carry_i_5_n_0 : STD_LOGIC;
signal z_exponent1_carry_n_0 : STD_LOGIC;
signal z_exponent1_carry_n_1 : STD_LOGIC;
signal z_exponent1_carry_n_2 : STD_LOGIC;
signal z_exponent1_carry_n_3 : STD_LOGIC;
signal NLW_L1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_L1_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_L1_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_L1_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW__carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW__carry__6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_msb1_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_msb1_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_msb1_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_msb1_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_msb1_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_msb1_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_msb1_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_msb1_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_msb1_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_msb1__0_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_msb1__0_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_msb1__0_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_msb1__0_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_msb1__0_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_msb1__0_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_msb1__0_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_msb1__0_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_msb1__0_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_msb1__0_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 31 );
signal \NLW_msb1__0_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_z[22]_INST_0_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_z[22]_INST_0_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_z_exponent0__0_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_z_exponent1_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of L1_carry_i_18 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of L1_carry_i_19 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of L1_carry_i_22 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of L1_carry_i_23 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of L1_carry_i_27 : label is "soft_lutpair44";
attribute SOFT_HLUTNM of L1_carry_i_30 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of L1_carry_i_31 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of L1_carry_i_33 : label is "soft_lutpair30";
attribute SOFT_HLUTNM of L1_carry_i_34 : label is "soft_lutpair27";
attribute SOFT_HLUTNM of L1_carry_i_36 : label is "soft_lutpair31";
attribute SOFT_HLUTNM of L1_carry_i_39 : label is "soft_lutpair29";
attribute SOFT_HLUTNM of L1_carry_i_46 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of L1_carry_i_47 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of L1_carry_i_49 : label is "soft_lutpair24";
attribute SOFT_HLUTNM of L1_carry_i_52 : label is "soft_lutpair29";
attribute SOFT_HLUTNM of L1_carry_i_53 : label is "soft_lutpair31";
attribute SOFT_HLUTNM of L1_carry_i_54 : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \_carry_i_11\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \_carry_i_18\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \_carry_i_19\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \_carry_i_20\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \_carry_i_22\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \_carry_i_24\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \_carry_i_6\ : label is "soft_lutpair27";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of msb1 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \msb1__0\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute SOFT_HLUTNM of \z[11]_INST_0_i_8\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \z[11]_INST_0_i_9\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \z[15]_INST_0_i_8\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_102\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_111\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_112\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_113\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_114\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_173\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_174\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_175\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_176\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_177\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_178\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_179\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_180\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_181\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_182\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_183\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_184\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_185\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_186\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_187\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_188\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_191\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_192\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_197\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_198\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_202\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_203\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_204\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_205\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_212\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_213\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_214\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_215\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_216\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_217\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_220\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_231\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_246\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_31\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_37\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_38\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_39\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_43\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_44\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_47\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_48\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_49\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_50\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_51\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_52\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_57\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_59\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_62\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_63\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_65\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_68\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_70\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_72\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_77\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_79\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_95\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_97\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \z[7]_INST_0_i_10\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \z[7]_INST_0_i_12\ : label is "soft_lutpair32";
attribute HLUTNM : string;
attribute HLUTNM of \z_exponent0__0_carry__0_i_2\ : label is "lutpair3";
attribute SOFT_HLUTNM of \z_exponent0__0_carry__0_i_8\ : label is "soft_lutpair2";
attribute HLUTNM of \z_exponent0__0_carry_i_1\ : label is "lutpair2";
attribute HLUTNM of \z_exponent0__0_carry_i_2\ : label is "lutpair1";
attribute HLUTNM of \z_exponent0__0_carry_i_3\ : label is "lutpair0";
attribute HLUTNM of \z_exponent0__0_carry_i_7\ : label is "lutpair0";
attribute HLUTNM of \z_exponent1_carry_i_1__0\ : label is "lutpair4";
attribute HLUTNM of \z_exponent1_carry_i_3__0\ : label is "lutpair2";
attribute HLUTNM of z_exponent1_carry_i_4 : label is "lutpair1";
attribute HLUTNM of \z_exponent1_carry_i_4__0\ : label is "lutpair3";
attribute HLUTNM of z_exponent1_carry_i_5 : label is "lutpair4";
begin
\y_11__s_net_1\ <= \y_11__s_port_\;
L1_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => L1_carry_n_0,
CO(2) => L1_carry_n_1,
CO(1) => L1_carry_n_2,
CO(0) => L1_carry_n_3,
CYINIT => '1',
DI(3) => L1_carry_i_1_n_0,
DI(2) => L1_carry_i_2_n_0,
DI(1) => L1_carry_i_3_n_0,
DI(0) => L1_carry_i_4_n_0,
O(3 downto 0) => NLW_L1_carry_O_UNCONNECTED(3 downto 0),
S(3) => L1_carry_i_5_n_0,
S(2) => L1_carry_i_6_n_0,
S(1) => L1_carry_i_7_n_0,
S(0) => L1_carry_i_8_n_0
);
\L1_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => L1_carry_n_0,
CO(3) => \L1_carry__0_n_0\,
CO(2) => \L1_carry__0_n_1\,
CO(1) => \L1_carry__0_n_2\,
CO(0) => \L1_carry__0_n_3\,
CYINIT => '0',
DI(3) => \L1_carry__0_i_1_n_0\,
DI(2) => \L1_carry__0_i_2_n_0\,
DI(1) => \L1_carry__0_i_3_n_0\,
DI(0) => \L1_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_L1_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \L1_carry__0_i_5_n_0\,
S(2) => \L1_carry__0_i_6_n_0\,
S(1) => \L1_carry__0_i_7_n_0\,
S(0) => \L1_carry__0_i_8_n_0\
);
\L1_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_1_n_0\
);
\L1_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_2_n_0\
);
\L1_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_3_n_0\
);
\L1_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_4_n_0\
);
\L1_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_5_n_0\
);
\L1_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_6_n_0\
);
\L1_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_7_n_0\
);
\L1_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_8_n_0\
);
\L1_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \L1_carry__0_n_0\,
CO(3) => \L1_carry__1_n_0\,
CO(2) => \L1_carry__1_n_1\,
CO(1) => \L1_carry__1_n_2\,
CO(0) => \L1_carry__1_n_3\,
CYINIT => '0',
DI(3) => \L1_carry__1_i_1_n_0\,
DI(2) => \L1_carry__1_i_2_n_0\,
DI(1) => \L1_carry__1_i_3_n_0\,
DI(0) => \L1_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_L1_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \L1_carry__1_i_5_n_0\,
S(2) => \L1_carry__1_i_6_n_0\,
S(1) => \L1_carry__1_i_7_n_0\,
S(0) => \L1_carry__1_i_8_n_0\
);
\L1_carry__1_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_1_n_0\
);
\L1_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_2_n_0\
);
\L1_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_3_n_0\
);
\L1_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_4_n_0\
);
\L1_carry__1_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_5_n_0\
);
\L1_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_6_n_0\
);
\L1_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_7_n_0\
);
\L1_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_8_n_0\
);
\L1_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \L1_carry__1_n_0\,
CO(3) => L1,
CO(2) => \L1_carry__2_n_1\,
CO(1) => \L1_carry__2_n_2\,
CO(0) => \L1_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \L1_carry__2_i_1_n_0\,
DI(1) => \L1_carry__2_i_2_n_0\,
DI(0) => \L1_carry__2_i_3_n_0\,
O(3 downto 0) => \NLW_L1_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \L1_carry__2_i_4_n_0\,
S(2) => \L1_carry__2_i_5_n_0\,
S(1) => \L1_carry__2_i_6_n_0\,
S(0) => \L1_carry__2_i_7_n_0\
);
\L1_carry__2_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_1_n_0\
);
\L1_carry__2_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_2_n_0\
);
\L1_carry__2_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_3_n_0\
);
\L1_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_4_n_0\
);
\L1_carry__2_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_5_n_0\
);
\L1_carry__2_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_6_n_0\
);
\L1_carry__2_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_7_n_0\
);
L1_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => L1_carry_i_1_n_0
);
L1_carry_i_10: unisim.vcomponents.LUT6
generic map(
INIT => X"4555FFFF45554555"
)
port map (
I0 => L1_carry_i_24_n_0,
I1 => L1_carry_i_25_n_0,
I2 => L1_carry_i_26_n_0,
I3 => L1_carry_i_27_n_0,
I4 => L1_carry_i_28_n_0,
I5 => L1_carry_i_29_n_0,
O => L1_carry_i_10_n_0
);
L1_carry_i_11: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFF7550000"
)
port map (
I0 => L1_carry_i_30_n_0,
I1 => L1_carry_i_31_n_0,
I2 => L1_carry_i_32_n_0,
I3 => L1_carry_i_33_n_0,
I4 => L1_carry_i_34_n_0,
I5 => L1_carry_i_35_n_0,
O => L1_carry_i_11_n_0
);
L1_carry_i_12: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => L1_carry_i_22_n_0,
I2 => L1_carry_i_19_n_0,
O => L1_carry_i_12_n_0
);
L1_carry_i_13: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \msb1__1\(40),
I1 => \msb1__1\(41),
I2 => \msb1__1\(43),
I3 => \msb1__1\(42),
I4 => L1_carry_i_34_n_0,
I5 => L1_carry_i_23_n_0,
O => L1_carry_i_13_n_0
);
L1_carry_i_14: unisim.vcomponents.LUT5
generic map(
INIT => X"A9AA5555"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_10_n_0,
I3 => \_carry_i_1_n_0\,
I4 => L1_carry_i_9_n_0,
O => L1_carry_i_14_n_0
);
L1_carry_i_15: unisim.vcomponents.LUT6
generic map(
INIT => X"0200AAAAFDFF5555"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_10_n_0,
I3 => \_carry_i_1_n_0\,
I4 => L1_carry_i_9_n_0,
I5 => L1_carry_i_13_n_0,
O => L1_carry_i_15_n_0
);
L1_carry_i_16: unisim.vcomponents.LUT3
generic map(
INIT => X"65"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_10_n_0,
I2 => \_carry_i_1_n_0\,
O => L1_carry_i_16_n_0
);
L1_carry_i_17: unisim.vcomponents.LUT4
generic map(
INIT => X"10EF"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_10_n_0,
I2 => \_carry_i_1_n_0\,
I3 => L1_carry_i_9_n_0,
O => L1_carry_i_17_n_0
);
L1_carry_i_18: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => L1_carry_i_34_n_0,
I1 => \msb1__1\(42),
I2 => \msb1__1\(43),
I3 => \msb1__1\(41),
I4 => \msb1__1\(40),
O => L1_carry_i_18_n_0
);
L1_carry_i_19: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => L1_carry_i_36_n_0,
I1 => \msb1__1\(26),
I2 => \msb1__1\(27),
I3 => \msb1__1\(25),
I4 => \msb1__1\(24),
O => L1_carry_i_19_n_0
);
L1_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => L1_carry_i_14_n_0,
I1 => L1_carry_i_15_n_0,
O => L1_carry_i_2_n_0
);
L1_carry_i_20: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(10),
I1 => \msb1__1\(11),
I2 => \msb1__1\(9),
I3 => \msb1__1\(8),
O => L1_carry_i_20_n_0
);
L1_carry_i_21: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \msb1__1\(14),
I1 => \msb1__1\(15),
I2 => \msb1__1\(13),
I3 => \msb1__1\(12),
O => L1_carry_i_21_n_0
);
L1_carry_i_22: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => L1_carry_i_37_n_0,
I1 => \msb1__1\(16),
I2 => \msb1__1\(17),
I3 => \msb1__1\(19),
I4 => \msb1__1\(18),
O => L1_carry_i_22_n_0
);
L1_carry_i_23: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => L1_carry_i_33_n_0,
I1 => \msb1__1\(32),
I2 => \msb1__1\(33),
I3 => \msb1__1\(35),
I4 => \msb1__1\(34),
O => L1_carry_i_23_n_0
);
L1_carry_i_24: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF000EFFFF"
)
port map (
I0 => \msb1__1\(39),
I1 => \msb1__1\(38),
I2 => \msb1__1\(41),
I3 => \msb1__1\(40),
I4 => L1_carry_i_29_n_0,
I5 => L1_carry_i_38_n_0,
O => L1_carry_i_24_n_0
);
L1_carry_i_25: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000F100"
)
port map (
I0 => L1_carry_i_39_n_0,
I1 => L1_carry_i_40_n_0,
I2 => L1_carry_i_41_n_0,
I3 => L1_carry_i_42_n_0,
I4 => \msb1__1\(35),
I5 => \msb1__1\(34),
O => L1_carry_i_25_n_0
);
L1_carry_i_26: unisim.vcomponents.LUT6
generic map(
INIT => X"1111110011111101"
)
port map (
I0 => \msb1__1\(37),
I1 => \msb1__1\(36),
I2 => \msb1__1\(33),
I3 => \msb1__1\(34),
I4 => \msb1__1\(35),
I5 => \msb1__1\(32),
O => L1_carry_i_26_n_0
);
L1_carry_i_27: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(41),
I1 => \msb1__1\(40),
O => L1_carry_i_27_n_0
);
L1_carry_i_28: unisim.vcomponents.LUT6
generic map(
INIT => X"1111111011111111"
)
port map (
I0 => \msb1__1\(45),
I1 => \msb1__1\(44),
I2 => L1_carry_i_43_n_0,
I3 => L1_carry_i_44_n_0,
I4 => L1_carry_i_39_n_0,
I5 => L1_carry_i_45_n_0,
O => L1_carry_i_28_n_0
);
L1_carry_i_29: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(46),
I1 => \msb1__1\(47),
O => L1_carry_i_29_n_0
);
L1_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => L1_carry_i_16_n_0,
I1 => L1_carry_i_17_n_0,
O => L1_carry_i_3_n_0
);
L1_carry_i_30: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(40),
I1 => \msb1__1\(41),
I2 => \msb1__1\(43),
I3 => \msb1__1\(42),
O => L1_carry_i_30_n_0
);
L1_carry_i_31: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(34),
I1 => \msb1__1\(35),
I2 => \msb1__1\(33),
I3 => \msb1__1\(32),
O => L1_carry_i_31_n_0
);
L1_carry_i_32: unisim.vcomponents.LUT6
generic map(
INIT => X"8A888A888A88AA88"
)
port map (
I0 => L1_carry_i_36_n_0,
I1 => L1_carry_i_46_n_0,
I2 => L1_carry_i_47_n_0,
I3 => L1_carry_i_37_n_0,
I4 => L1_carry_i_20_n_0,
I5 => L1_carry_i_21_n_0,
O => L1_carry_i_32_n_0
);
L1_carry_i_33: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(37),
I1 => \msb1__1\(36),
I2 => \msb1__1\(38),
I3 => \msb1__1\(39),
O => L1_carry_i_33_n_0
);
L1_carry_i_34: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(47),
I1 => \msb1__1\(46),
I2 => \msb1__1\(45),
I3 => \msb1__1\(44),
O => L1_carry_i_34_n_0
);
L1_carry_i_35: unisim.vcomponents.LUT6
generic map(
INIT => X"0000400000000000"
)
port map (
I0 => L1_carry_i_48_n_0,
I1 => L1_carry_i_49_n_0,
I2 => L1_carry_i_34_n_0,
I3 => L1_carry_i_36_n_0,
I4 => L1_carry_i_21_n_0,
I5 => L1_carry_i_37_n_0,
O => L1_carry_i_35_n_0
);
L1_carry_i_36: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(28),
I1 => \msb1__1\(29),
I2 => \msb1__1\(30),
I3 => \msb1__1\(31),
O => L1_carry_i_36_n_0
);
L1_carry_i_37: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(23),
I1 => \msb1__1\(22),
I2 => \msb1__1\(20),
I3 => \msb1__1\(21),
O => L1_carry_i_37_n_0
);
L1_carry_i_38: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(42),
I1 => \msb1__1\(43),
O => L1_carry_i_38_n_0
);
L1_carry_i_39: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \msb1__1\(23),
I1 => \msb1__1\(22),
I2 => \msb1__1\(18),
I3 => \msb1__1\(19),
O => L1_carry_i_39_n_0
);
L1_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"D"
)
port map (
I0 => \_carry_i_1_n_0\,
I1 => L1_carry_i_10_n_0,
O => L1_carry_i_4_n_0
);
L1_carry_i_40: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000FFF2"
)
port map (
I0 => L1_carry_i_50_n_0,
I1 => L1_carry_i_51_n_0,
I2 => \msb1__1\(15),
I3 => \msb1__1\(14),
I4 => \msb1__1\(17),
I5 => \msb1__1\(16),
O => L1_carry_i_40_n_0
);
L1_carry_i_41: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFE0FF"
)
port map (
I0 => \msb1__1\(21),
I1 => \msb1__1\(20),
I2 => L1_carry_i_52_n_0,
I3 => L1_carry_i_53_n_0,
I4 => \msb1__1\(25),
I5 => \msb1__1\(24),
O => L1_carry_i_41_n_0
);
L1_carry_i_42: unisim.vcomponents.LUT6
generic map(
INIT => X"1111111111110001"
)
port map (
I0 => \msb1__1\(30),
I1 => \msb1__1\(31),
I2 => \msb1__1\(26),
I3 => \msb1__1\(27),
I4 => \msb1__1\(29),
I5 => \msb1__1\(28),
O => L1_carry_i_42_n_0
);
L1_carry_i_43: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFEFFFF"
)
port map (
I0 => \msb1__1\(2),
I1 => \msb1__1\(3),
I2 => \msb1__1\(26),
I3 => \msb1__1\(27),
I4 => L1_carry_i_54_n_0,
I5 => L1_carry_i_38_n_0,
O => L1_carry_i_43_n_0
);
L1_carry_i_44: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \msb1__1\(7),
I1 => \msb1__1\(6),
I2 => \msb1__1\(10),
I3 => \msb1__1\(11),
O => L1_carry_i_44_n_0
);
L1_carry_i_45: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \msb1__1\(34),
I1 => \msb1__1\(35),
I2 => \msb1__1\(15),
I3 => \msb1__1\(14),
I4 => \msb1__1\(31),
I5 => \msb1__1\(30),
O => L1_carry_i_45_n_0
);
L1_carry_i_46: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \msb1__1\(24),
I1 => \msb1__1\(25),
I2 => \msb1__1\(27),
I3 => \msb1__1\(26),
O => L1_carry_i_46_n_0
);
L1_carry_i_47: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(18),
I1 => \msb1__1\(19),
I2 => \msb1__1\(17),
I3 => \msb1__1\(16),
O => L1_carry_i_47_n_0
);
L1_carry_i_48: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \msb1__1\(7),
I1 => \msb1__1\(6),
I2 => \msb1__1\(39),
I3 => \msb1__1\(38),
I4 => \msb1__1\(36),
I5 => \msb1__1\(37),
O => L1_carry_i_48_n_0
);
L1_carry_i_49: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(5),
I1 => \msb1__1\(4),
O => L1_carry_i_49_n_0
);
L1_carry_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => L1_carry_i_5_n_0
);
L1_carry_i_50: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF1"
)
port map (
I0 => \msb1__1\(4),
I1 => \msb1__1\(5),
I2 => \msb1__1\(11),
I3 => \msb1__1\(10),
I4 => \msb1__1\(6),
I5 => \msb1__1\(7),
O => L1_carry_i_50_n_0
);
L1_carry_i_51: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEEEEEEFFFE"
)
port map (
I0 => \msb1__1\(13),
I1 => \msb1__1\(12),
I2 => \msb1__1\(8),
I3 => \msb1__1\(9),
I4 => \msb1__1\(11),
I5 => \msb1__1\(10),
O => L1_carry_i_51_n_0
);
L1_carry_i_52: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(22),
I1 => \msb1__1\(23),
O => L1_carry_i_52_n_0
);
L1_carry_i_53: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(29),
I1 => \msb1__1\(28),
O => L1_carry_i_53_n_0
);
L1_carry_i_54: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(39),
I1 => \msb1__1\(38),
O => L1_carry_i_54_n_0
);
L1_carry_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => L1_carry_i_15_n_0,
I1 => L1_carry_i_14_n_0,
O => L1_carry_i_6_n_0
);
L1_carry_i_7: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => L1_carry_i_17_n_0,
I1 => L1_carry_i_16_n_0,
O => L1_carry_i_7_n_0
);
L1_carry_i_8: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \_carry_i_1_n_0\,
I1 => L1_carry_i_10_n_0,
O => L1_carry_i_8_n_0
);
L1_carry_i_9: unisim.vcomponents.LUT6
generic map(
INIT => X"00808888AAAAAAAA"
)
port map (
I0 => L1_carry_i_18_n_0,
I1 => L1_carry_i_19_n_0,
I2 => L1_carry_i_20_n_0,
I3 => L1_carry_i_21_n_0,
I4 => L1_carry_i_22_n_0,
I5 => L1_carry_i_23_n_0,
O => L1_carry_i_9_n_0
);
\_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \_carry_n_0\,
CO(2) => \_carry_n_1\,
CO(1) => \_carry_n_2\,
CO(0) => \_carry_n_3\,
CYINIT => \_carry_i_1_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \_carry_n_4\,
O(2) => \_carry_n_5\,
O(1) => \_carry_n_6\,
O(0) => \_carry_n_7\,
S(3) => \_carry_i_2_n_0\,
S(2) => \_carry_i_3_n_0\,
S(1) => \_carry_i_4_n_0\,
S(0) => p_0_in(1)
);
\_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \_carry_n_0\,
CO(3) => \_carry__0_n_0\,
CO(2) => \_carry__0_n_1\,
CO(1) => \_carry__0_n_2\,
CO(0) => \_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \_carry__0_n_4\,
O(2) => \_carry__0_n_5\,
O(1) => \_carry__0_n_6\,
O(0) => \_carry__0_n_7\,
S(3) => \_carry__0_i_1_n_0\,
S(2) => \_carry__0_i_2_n_0\,
S(1) => \_carry__0_i_3_n_0\,
S(0) => \_carry__0_i_4_n_0\
);
\_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__0_i_1_n_0\
);
\_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__0_i_2_n_0\
);
\_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__0_i_3_n_0\
);
\_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0200AAAAFDFF5555"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_10_n_0,
I3 => \_carry_i_1_n_0\,
I4 => L1_carry_i_9_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__0_i_4_n_0\
);
\_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__0_n_0\,
CO(3) => \_carry__1_n_0\,
CO(2) => \_carry__1_n_1\,
CO(1) => \_carry__1_n_2\,
CO(0) => \_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \_carry__1_n_4\,
O(2) => \_carry__1_n_5\,
O(1) => \_carry__1_n_6\,
O(0) => \_carry__1_n_7\,
S(3) => \_carry__1_i_1_n_0\,
S(2) => \_carry__1_i_2_n_0\,
S(1) => \_carry__1_i_3_n_0\,
S(0) => \_carry__1_i_4_n_0\
);
\_carry__1_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__1_i_1_n_0\
);
\_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__1_i_2_n_0\
);
\_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__1_i_3_n_0\
);
\_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__1_i_4_n_0\
);
\_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__1_n_0\,
CO(3) => \_carry__2_n_0\,
CO(2) => \_carry__2_n_1\,
CO(1) => \_carry__2_n_2\,
CO(0) => \_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \_carry__2_n_4\,
O(2) => \_carry__2_n_5\,
O(1) => \_carry__2_n_6\,
O(0) => \_carry__2_n_7\,
S(3) => \_carry__2_i_1_n_0\,
S(2) => \_carry__2_i_2_n_0\,
S(1) => \_carry__2_i_3_n_0\,
S(0) => \_carry__2_i_4_n_0\
);
\_carry__2_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__2_i_1_n_0\
);
\_carry__2_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__2_i_2_n_0\
);
\_carry__2_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__2_i_3_n_0\
);
\_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__2_i_4_n_0\
);
\_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__2_n_0\,
CO(3) => \_carry__3_n_0\,
CO(2) => \_carry__3_n_1\,
CO(1) => \_carry__3_n_2\,
CO(0) => \_carry__3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \_carry__3_n_4\,
O(2) => \_carry__3_n_5\,
O(1) => \_carry__3_n_6\,
O(0) => \_carry__3_n_7\,
S(3) => \_carry__3_i_1_n_0\,
S(2) => \_carry__3_i_2_n_0\,
S(1) => \_carry__3_i_3_n_0\,
S(0) => \_carry__3_i_4_n_0\
);
\_carry__3_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__3_i_1_n_0\
);
\_carry__3_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__3_i_2_n_0\
);
\_carry__3_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__3_i_3_n_0\
);
\_carry__3_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__3_i_4_n_0\
);
\_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__3_n_0\,
CO(3) => \_carry__4_n_0\,
CO(2) => \_carry__4_n_1\,
CO(1) => \_carry__4_n_2\,
CO(0) => \_carry__4_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \_carry__4_n_4\,
O(2) => \_carry__4_n_5\,
O(1) => \_carry__4_n_6\,
O(0) => \_carry__4_n_7\,
S(3) => \_carry__4_i_1_n_0\,
S(2) => \_carry__4_i_2_n_0\,
S(1) => \_carry__4_i_3_n_0\,
S(0) => \_carry__4_i_4_n_0\
);
\_carry__4_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__4_i_1_n_0\
);
\_carry__4_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__4_i_2_n_0\
);
\_carry__4_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__4_i_3_n_0\
);
\_carry__4_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__4_i_4_n_0\
);
\_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__4_n_0\,
CO(3) => \_carry__5_n_0\,
CO(2) => \_carry__5_n_1\,
CO(1) => \_carry__5_n_2\,
CO(0) => \_carry__5_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \_carry__5_n_4\,
O(2) => \_carry__5_n_5\,
O(1) => \_carry__5_n_6\,
O(0) => \_carry__5_n_7\,
S(3) => \_carry__5_i_1_n_0\,
S(2) => \_carry__5_i_2_n_0\,
S(1) => \_carry__5_i_3_n_0\,
S(0) => \_carry__5_i_4_n_0\
);
\_carry__5_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__5_i_1_n_0\
);
\_carry__5_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__5_i_2_n_0\
);
\_carry__5_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__5_i_3_n_0\
);
\_carry__5_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__5_i_4_n_0\
);
\_carry__6\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__5_n_0\,
CO(3 downto 1) => \NLW__carry__6_CO_UNCONNECTED\(3 downto 1),
CO(0) => \_carry__6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW__carry__6_O_UNCONNECTED\(3 downto 2),
O(1) => \_carry__6_n_6\,
O(0) => \_carry__6_n_7\,
S(3 downto 2) => B"00",
S(1) => \_carry__6_i_1_n_0\,
S(0) => \_carry__6_i_2_n_0\
);
\_carry__6_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__6_i_1_n_0\
);
\_carry__6_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__6_i_2_n_0\
);
\_carry_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BBBBABAA"
)
port map (
I0 => \msb1__1\(47),
I1 => \_carry_i_6_n_0\,
I2 => \_carry_i_7_n_0\,
I3 => \_carry_i_8_n_0\,
I4 => \_carry_i_9_n_0\,
O => \_carry_i_1_n_0\
);
\_carry_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \_carry_i_1_n_0\,
I1 => L1_carry_i_10_n_0,
O => \_carry_i_10_n_0\
);
\_carry_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(42),
I1 => \msb1__1\(40),
O => \_carry_i_11_n_0\
);
\_carry_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0FFF0FFFFFFF4"
)
port map (
I0 => \msb1__1\(25),
I1 => \msb1__1\(24),
I2 => \msb1__1\(28),
I3 => \_carry_i_18_n_0\,
I4 => \msb1__1\(26),
I5 => \msb1__1\(27),
O => \_carry_i_12_n_0\
);
\_carry_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0FFF0FFFFFFF4"
)
port map (
I0 => \msb1__1\(15),
I1 => \msb1__1\(14),
I2 => \msb1__1\(18),
I3 => \_carry_i_19_n_0\,
I4 => \msb1__1\(16),
I5 => \msb1__1\(17),
O => \_carry_i_13_n_0\
);
\_carry_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000EFEE"
)
port map (
I0 => \_carry_i_20_n_0\,
I1 => \msb1__1\(7),
I2 => \msb1__1\(6),
I3 => \msb1__1\(5),
I4 => \_carry_i_21_n_0\,
O => \_carry_i_14_n_0\
);
\_carry_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF00BA"
)
port map (
I0 => \msb1__1\(11),
I1 => \msb1__1\(10),
I2 => \msb1__1\(9),
I3 => \msb1__1\(12),
I4 => \_carry_i_22_n_0\,
I5 => \msb1__1\(13),
O => \_carry_i_15_n_0\
);
\_carry_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0FFF0FFFFFFF4"
)
port map (
I0 => \msb1__1\(20),
I1 => \msb1__1\(19),
I2 => \msb1__1\(23),
I3 => \_carry_i_23_n_0\,
I4 => \msb1__1\(21),
I5 => \msb1__1\(22),
O => \_carry_i_16_n_0\
);
\_carry_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0FFF0FFFFFFF4"
)
port map (
I0 => \msb1__1\(30),
I1 => \msb1__1\(29),
I2 => \msb1__1\(33),
I3 => \_carry_i_24_n_0\,
I4 => \msb1__1\(31),
I5 => \msb1__1\(32),
O => \_carry_i_17_n_0\
);
\_carry_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(32),
I1 => \msb1__1\(30),
O => \_carry_i_18_n_0\
);
\_carry_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(22),
I1 => \msb1__1\(20),
O => \_carry_i_19_n_0\
);
\_carry_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"555DAAA2"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
O => \_carry_i_2_n_0\
);
\_carry_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"5504"
)
port map (
I0 => \msb1__1\(4),
I1 => \msb1__1\(1),
I2 => \msb1__1\(2),
I3 => \msb1__1\(3),
O => \_carry_i_20_n_0\
);
\_carry_i_21\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFF4"
)
port map (
I0 => \msb1__1\(7),
I1 => \msb1__1\(6),
I2 => \msb1__1\(12),
I3 => \msb1__1\(10),
I4 => \msb1__1\(8),
O => \_carry_i_21_n_0\
);
\_carry_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(17),
I1 => \msb1__1\(15),
O => \_carry_i_22_n_0\
);
\_carry_i_23\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(27),
I1 => \msb1__1\(25),
O => \_carry_i_23_n_0\
);
\_carry_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(37),
I1 => \msb1__1\(35),
O => \_carry_i_24_n_0\
);
\_carry_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"10EF"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_10_n_0,
I2 => \_carry_i_1_n_0\,
I3 => L1_carry_i_9_n_0,
O => \_carry_i_3_n_0\
);
\_carry_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => L1_carry_i_16_n_0,
O => \_carry_i_4_n_0\
);
\_carry_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \_carry_i_10_n_0\,
O => p_0_in(1)
);
\_carry_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \msb1__1\(46),
I1 => \msb1__1\(45),
I2 => \msb1__1\(44),
O => \_carry_i_6_n_0\
);
\_carry_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0FFF0FFFFFFF4"
)
port map (
I0 => \msb1__1\(35),
I1 => \msb1__1\(34),
I2 => \msb1__1\(38),
I3 => \_carry_i_11_n_0\,
I4 => \msb1__1\(36),
I5 => \msb1__1\(37),
O => \_carry_i_7_n_0\
);
\_carry_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF55551110"
)
port map (
I0 => \_carry_i_12_n_0\,
I1 => \_carry_i_13_n_0\,
I2 => \_carry_i_14_n_0\,
I3 => \_carry_i_15_n_0\,
I4 => \_carry_i_16_n_0\,
I5 => \_carry_i_17_n_0\,
O => \_carry_i_8_n_0\
);
\_carry_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF00F4"
)
port map (
I0 => \msb1__1\(40),
I1 => \msb1__1\(39),
I2 => \msb1__1\(41),
I3 => \msb1__1\(42),
I4 => \msb1__1\(45),
I5 => \msb1__1\(43),
O => \_carry_i_9_n_0\
);
msb1: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29 downto 23) => B"0000001",
A(22 downto 0) => y(22 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_msb1_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => '0',
B(16 downto 0) => x(16 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_msb1_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_msb1_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_msb1_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_msb1_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_msb1_OVERFLOW_UNCONNECTED,
P(47) => msb1_n_58,
P(46) => msb1_n_59,
P(45) => msb1_n_60,
P(44) => msb1_n_61,
P(43) => msb1_n_62,
P(42) => msb1_n_63,
P(41) => msb1_n_64,
P(40) => msb1_n_65,
P(39) => msb1_n_66,
P(38) => msb1_n_67,
P(37) => msb1_n_68,
P(36) => msb1_n_69,
P(35) => msb1_n_70,
P(34) => msb1_n_71,
P(33) => msb1_n_72,
P(32) => msb1_n_73,
P(31) => msb1_n_74,
P(30) => msb1_n_75,
P(29) => msb1_n_76,
P(28) => msb1_n_77,
P(27) => msb1_n_78,
P(26) => msb1_n_79,
P(25) => msb1_n_80,
P(24) => msb1_n_81,
P(23) => msb1_n_82,
P(22) => msb1_n_83,
P(21) => msb1_n_84,
P(20) => msb1_n_85,
P(19) => msb1_n_86,
P(18) => msb1_n_87,
P(17) => msb1_n_88,
P(16 downto 0) => \msb1__1\(16 downto 0),
PATTERNBDETECT => NLW_msb1_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_msb1_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47) => msb1_n_106,
PCOUT(46) => msb1_n_107,
PCOUT(45) => msb1_n_108,
PCOUT(44) => msb1_n_109,
PCOUT(43) => msb1_n_110,
PCOUT(42) => msb1_n_111,
PCOUT(41) => msb1_n_112,
PCOUT(40) => msb1_n_113,
PCOUT(39) => msb1_n_114,
PCOUT(38) => msb1_n_115,
PCOUT(37) => msb1_n_116,
PCOUT(36) => msb1_n_117,
PCOUT(35) => msb1_n_118,
PCOUT(34) => msb1_n_119,
PCOUT(33) => msb1_n_120,
PCOUT(32) => msb1_n_121,
PCOUT(31) => msb1_n_122,
PCOUT(30) => msb1_n_123,
PCOUT(29) => msb1_n_124,
PCOUT(28) => msb1_n_125,
PCOUT(27) => msb1_n_126,
PCOUT(26) => msb1_n_127,
PCOUT(25) => msb1_n_128,
PCOUT(24) => msb1_n_129,
PCOUT(23) => msb1_n_130,
PCOUT(22) => msb1_n_131,
PCOUT(21) => msb1_n_132,
PCOUT(20) => msb1_n_133,
PCOUT(19) => msb1_n_134,
PCOUT(18) => msb1_n_135,
PCOUT(17) => msb1_n_136,
PCOUT(16) => msb1_n_137,
PCOUT(15) => msb1_n_138,
PCOUT(14) => msb1_n_139,
PCOUT(13) => msb1_n_140,
PCOUT(12) => msb1_n_141,
PCOUT(11) => msb1_n_142,
PCOUT(10) => msb1_n_143,
PCOUT(9) => msb1_n_144,
PCOUT(8) => msb1_n_145,
PCOUT(7) => msb1_n_146,
PCOUT(6) => msb1_n_147,
PCOUT(5) => msb1_n_148,
PCOUT(4) => msb1_n_149,
PCOUT(3) => msb1_n_150,
PCOUT(2) => msb1_n_151,
PCOUT(1) => msb1_n_152,
PCOUT(0) => msb1_n_153,
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_msb1_UNDERFLOW_UNCONNECTED
);
\msb1__0\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29 downto 23) => B"0000001",
A(22 downto 0) => y(22 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_msb1__0_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17 downto 6) => B"000000000001",
B(5 downto 0) => x(22 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_msb1__0_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_msb1__0_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_msb1__0_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_msb1__0_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"1010101",
OVERFLOW => \NLW_msb1__0_OVERFLOW_UNCONNECTED\,
P(47 downto 31) => \NLW_msb1__0_P_UNCONNECTED\(47 downto 31),
P(30 downto 0) => \msb1__1\(47 downto 17),
PATTERNBDETECT => \NLW_msb1__0_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_msb1__0_PATTERNDETECT_UNCONNECTED\,
PCIN(47) => msb1_n_106,
PCIN(46) => msb1_n_107,
PCIN(45) => msb1_n_108,
PCIN(44) => msb1_n_109,
PCIN(43) => msb1_n_110,
PCIN(42) => msb1_n_111,
PCIN(41) => msb1_n_112,
PCIN(40) => msb1_n_113,
PCIN(39) => msb1_n_114,
PCIN(38) => msb1_n_115,
PCIN(37) => msb1_n_116,
PCIN(36) => msb1_n_117,
PCIN(35) => msb1_n_118,
PCIN(34) => msb1_n_119,
PCIN(33) => msb1_n_120,
PCIN(32) => msb1_n_121,
PCIN(31) => msb1_n_122,
PCIN(30) => msb1_n_123,
PCIN(29) => msb1_n_124,
PCIN(28) => msb1_n_125,
PCIN(27) => msb1_n_126,
PCIN(26) => msb1_n_127,
PCIN(25) => msb1_n_128,
PCIN(24) => msb1_n_129,
PCIN(23) => msb1_n_130,
PCIN(22) => msb1_n_131,
PCIN(21) => msb1_n_132,
PCIN(20) => msb1_n_133,
PCIN(19) => msb1_n_134,
PCIN(18) => msb1_n_135,
PCIN(17) => msb1_n_136,
PCIN(16) => msb1_n_137,
PCIN(15) => msb1_n_138,
PCIN(14) => msb1_n_139,
PCIN(13) => msb1_n_140,
PCIN(12) => msb1_n_141,
PCIN(11) => msb1_n_142,
PCIN(10) => msb1_n_143,
PCIN(9) => msb1_n_144,
PCIN(8) => msb1_n_145,
PCIN(7) => msb1_n_146,
PCIN(6) => msb1_n_147,
PCIN(5) => msb1_n_148,
PCIN(4) => msb1_n_149,
PCIN(3) => msb1_n_150,
PCIN(2) => msb1_n_151,
PCIN(1) => msb1_n_152,
PCIN(0) => msb1_n_153,
PCOUT(47 downto 0) => \NLW_msb1__0_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_msb1__0_UNDERFLOW_UNCONNECTED\
);
\z[11]_INST_0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \z[7]_INST_0_i_1_n_0\,
CO(3) => \z[11]_INST_0_i_1_n_0\,
CO(2) => \z[11]_INST_0_i_1_n_1\,
CO(1) => \z[11]_INST_0_i_1_n_2\,
CO(0) => \z[11]_INST_0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => z_mantissa(11 downto 8),
S(3) => sel0(11),
S(2) => \z[11]_INST_0_i_3_n_0\,
S(1 downto 0) => sel0(9 downto 8)
);
\z[11]_INST_0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_11_n_0\,
O => sel0(11)
);
\z[11]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_50_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_47_n_0\,
I4 => \z[30]_INST_0_i_51_n_0\,
O => \z[11]_INST_0_i_3_n_0\
);
\z[11]_INST_0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[11]_INST_0_i_6_n_0\,
O => sel0(9)
);
\z[11]_INST_0_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[11]_INST_0_i_7_n_0\,
O => sel0(8)
);
\z[11]_INST_0_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[11]_INST_0_i_8_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[30]_INST_0_i_50_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_52_n_0\,
O => \z[11]_INST_0_i_6_n_0\
);
\z[11]_INST_0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[11]_INST_0_i_9_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[11]_INST_0_i_8_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_54_n_0\,
O => \z[11]_INST_0_i_7_n_0\
);
\z[11]_INST_0_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_121_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_98_n_0\,
O => \z[11]_INST_0_i_8_n_0\
);
\z[11]_INST_0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_100_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_101_n_0\,
O => \z[11]_INST_0_i_9_n_0\
);
\z[15]_INST_0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \z[11]_INST_0_i_1_n_0\,
CO(3) => \z[15]_INST_0_i_1_n_0\,
CO(2) => \z[15]_INST_0_i_1_n_1\,
CO(1) => \z[15]_INST_0_i_1_n_2\,
CO(0) => \z[15]_INST_0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => z_mantissa(15 downto 12),
S(3 downto 0) => sel0(15 downto 12)
);
\z[15]_INST_0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_14_n_0\,
O => sel0(15)
);
\z[15]_INST_0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_15_n_0\,
O => sel0(14)
);
\z[15]_INST_0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[15]_INST_0_i_6_n_0\,
O => sel0(13)
);
\z[15]_INST_0_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[15]_INST_0_i_7_n_0\,
O => sel0(12)
);
\z[15]_INST_0_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[15]_INST_0_i_8_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[30]_INST_0_i_60_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_63_n_0\,
O => \z[15]_INST_0_i_6_n_0\
);
\z[15]_INST_0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[30]_INST_0_i_48_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[15]_INST_0_i_8_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_65_n_0\,
O => \z[15]_INST_0_i_7_n_0\
);
\z[15]_INST_0_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_142_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_120_n_0\,
O => \z[15]_INST_0_i_8_n_0\
);
\z[19]_INST_0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \z[15]_INST_0_i_1_n_0\,
CO(3) => \z[19]_INST_0_i_1_n_0\,
CO(2) => \z[19]_INST_0_i_1_n_1\,
CO(1) => \z[19]_INST_0_i_1_n_2\,
CO(0) => \z[19]_INST_0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => z_mantissa(19 downto 16),
S(3 downto 0) => sel0(19 downto 16)
);
\z[19]_INST_0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_17_n_0\,
O => sel0(19)
);
\z[19]_INST_0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_18_n_0\,
O => sel0(18)
);
\z[19]_INST_0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_19_n_0\,
O => sel0(17)
);
\z[19]_INST_0_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_20_n_0\,
O => sel0(16)
);
\z[22]_INST_0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \z[19]_INST_0_i_1_n_0\,
CO(3 downto 2) => \NLW_z[22]_INST_0_i_1_CO_UNCONNECTED\(3 downto 2),
CO(1) => \z[22]_INST_0_i_1_n_2\,
CO(0) => \z[22]_INST_0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_z[22]_INST_0_i_1_O_UNCONNECTED\(3),
O(2 downto 0) => z_mantissa(22 downto 20),
S(3) => '0',
S(2 downto 0) => sel0(22 downto 20)
);
\z[22]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F2F2FFF2"
)
port map (
I0 => \z[30]_INST_0_i_57_n_0\,
I1 => \z[30]_INST_0_i_81_n_0\,
I2 => \z[30]_INST_0_i_76_n_0\,
I3 => L1,
I4 => \z[22]_INST_0_i_5_n_0\,
O => sel0(22)
);
\z[22]_INST_0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_22_n_0\,
O => sel0(21)
);
\z[22]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"22F222F2FFFF22F2"
)
port map (
I0 => \z[30]_INST_0_i_43_n_0\,
I1 => \z[30]_INST_0_i_82_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_67_n_0\,
I4 => L1,
I5 => \z[22]_INST_0_i_6_n_0\,
O => sel0(20)
);
\z[22]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_168_n_0\,
I1 => \z[30]_INST_0_i_154_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_159_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_158_n_0\,
O => \z[22]_INST_0_i_5_n_0\
);
\z[22]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_154_n_0\,
I1 => \z[30]_INST_0_i_155_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_158_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_152_n_0\,
O => \z[22]_INST_0_i_6_n_0\
);
\z[23]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(0),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(0),
I5 => \y_11__s_net_1\,
O => z(0)
);
\z[24]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(1),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(1),
I5 => \y_11__s_net_1\,
O => z(1)
);
\z[25]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(2),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(2),
I5 => \y_11__s_net_1\,
O => z(2)
);
\z[26]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(3),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(3),
I5 => \y_11__s_net_1\,
O => z(3)
);
\z[27]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(4),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(4),
I5 => \y_11__s_net_1\,
O => z(4)
);
\z[28]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(5),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(5),
I5 => \y_11__s_net_1\,
O => z(5)
);
\z[29]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(6),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(6),
I5 => \y_11__s_net_1\,
O => z(6)
);
\z[30]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(7),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(7),
I5 => \y_11__s_net_1\,
O => z(7)
);
\z[30]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEFFFFFFFFFFF"
)
port map (
I0 => \z[30]_INST_0_i_5_n_0\,
I1 => \z[30]_INST_0_i_6_n_0\,
I2 => sel0(3),
I3 => sel0(0),
I4 => \z[30]_INST_0_i_9_n_0\,
I5 => sel0(2),
O => \z[30]_INST_0_i_1_n_0\
);
\z[30]_INST_0_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_44_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_37_n_0\,
I4 => \z[30]_INST_0_i_46_n_0\,
O => sel0(2)
);
\z[30]_INST_0_i_100\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_181_n_0\,
I1 => \z[30]_INST_0_i_182_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_183_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_184_n_0\,
O => \z[30]_INST_0_i_100_n_0\
);
\z[30]_INST_0_i_101\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_185_n_0\,
I1 => \z[30]_INST_0_i_186_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_187_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_188_n_0\,
O => \z[30]_INST_0_i_101_n_0\
);
\z[30]_INST_0_i_102\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_189_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_171_n_0\,
O => \z[30]_INST_0_i_102_n_0\
);
\z[30]_INST_0_i_103\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFF4FFF7"
)
port map (
I0 => \msb1__1\(1),
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_118_n_0\,
I3 => \z[30]_INST_0_i_170_n_0\,
I4 => \msb1__1\(3),
I5 => \z[30]_INST_0_i_169_n_0\,
O => \z[30]_INST_0_i_103_n_0\
);
\z[30]_INST_0_i_104\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_183_n_0\,
I1 => \z[30]_INST_0_i_184_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_190_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_181_n_0\,
O => \z[30]_INST_0_i_104_n_0\
);
\z[30]_INST_0_i_105\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_187_n_0\,
I1 => \z[30]_INST_0_i_188_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_191_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_185_n_0\,
O => \z[30]_INST_0_i_105_n_0\
);
\z[30]_INST_0_i_106\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_175_n_0\,
I1 => \z[30]_INST_0_i_176_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_192_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_173_n_0\,
O => \z[30]_INST_0_i_106_n_0\
);
\z[30]_INST_0_i_107\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFEAEFFFF"
)
port map (
I0 => \z[30]_INST_0_i_118_n_0\,
I1 => \_carry_n_4\,
I2 => L1,
I3 => L1_carry_i_14_n_0,
I4 => \msb1__1\(3),
I5 => \z[30]_INST_0_i_169_n_0\,
O => \z[30]_INST_0_i_107_n_0\
);
\z[30]_INST_0_i_108\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_179_n_0\,
I1 => \z[30]_INST_0_i_180_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_193_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_177_n_0\,
O => \z[30]_INST_0_i_108_n_0\
);
\z[30]_INST_0_i_109\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFF4F7FFFF"
)
port map (
I0 => \msb1__1\(0),
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_118_n_0\,
I3 => \msb1__1\(2),
I4 => \z[30]_INST_0_i_194_n_0\,
I5 => \z[30]_INST_0_i_169_n_0\,
O => \z[30]_INST_0_i_109_n_0\
);
\z[30]_INST_0_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[30]_INST_0_i_47_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[30]_INST_0_i_48_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_49_n_0\,
O => \z[30]_INST_0_i_11_n_0\
);
\z[30]_INST_0_i_110\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_190_n_0\,
I1 => \z[30]_INST_0_i_181_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_195_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_183_n_0\,
O => \z[30]_INST_0_i_110_n_0\
);
\z[30]_INST_0_i_111\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_191_n_0\,
I1 => L1_carry_i_17_n_0,
I2 => \z[30]_INST_0_i_185_n_0\,
O => \z[30]_INST_0_i_111_n_0\
);
\z[30]_INST_0_i_112\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_196_n_0\,
I1 => L1_carry_i_17_n_0,
I2 => \z[30]_INST_0_i_187_n_0\,
O => \z[30]_INST_0_i_112_n_0\
);
\z[30]_INST_0_i_113\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_192_n_0\,
I1 => L1_carry_i_17_n_0,
I2 => \z[30]_INST_0_i_173_n_0\,
O => \z[30]_INST_0_i_113_n_0\
);
\z[30]_INST_0_i_114\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_197_n_0\,
I1 => L1_carry_i_17_n_0,
I2 => \z[30]_INST_0_i_175_n_0\,
O => \z[30]_INST_0_i_114_n_0\
);
\z[30]_INST_0_i_115\: unisim.vcomponents.LUT6
generic map(
INIT => X"3FFF3FAAFFFFFFFF"
)
port map (
I0 => \_carry_n_5\,
I1 => L1_carry_i_17_n_0,
I2 => \z[30]_INST_0_i_198_n_0\,
I3 => L1,
I4 => \_carry_n_4\,
I5 => \msb1__1\(0),
O => \z[30]_INST_0_i_115_n_0\
);
\z[30]_INST_0_i_116\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \z[30]_INST_0_i_199_n_0\,
I1 => \_carry__0_n_6\,
I2 => \_carry__5_n_6\,
I3 => \_carry__0_n_5\,
I4 => \z[30]_INST_0_i_200_n_0\,
I5 => \z[30]_INST_0_i_201_n_0\,
O => \z[30]_INST_0_i_116_n_0\
);
\z[30]_INST_0_i_117\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF3FFFFFFF3FAFAF"
)
port map (
I0 => \_carry_n_5\,
I1 => L1_carry_i_17_n_0,
I2 => \msb1__1\(1),
I3 => L1_carry_i_14_n_0,
I4 => L1,
I5 => \_carry_n_4\,
O => \z[30]_INST_0_i_117_n_0\
);
\z[30]_INST_0_i_118\: unisim.vcomponents.LUT5
generic map(
INIT => X"3C33AAAA"
)
port map (
I0 => \_carry_n_6\,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_10_n_0,
I3 => \_carry_i_1_n_0\,
I4 => L1,
O => \z[30]_INST_0_i_118_n_0\
);
\z[30]_INST_0_i_119\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFEAEFFFF"
)
port map (
I0 => \z[30]_INST_0_i_118_n_0\,
I1 => \_carry_n_4\,
I2 => L1,
I3 => L1_carry_i_14_n_0,
I4 => \msb1__1\(1),
I5 => \z[30]_INST_0_i_169_n_0\,
O => \z[30]_INST_0_i_119_n_0\
);
\z[30]_INST_0_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_50_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_47_n_0\,
I4 => \z[30]_INST_0_i_51_n_0\,
O => sel0(10)
);
\z[30]_INST_0_i_120\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_176_n_0\,
I1 => \z[30]_INST_0_i_202_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_173_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_174_n_0\,
O => \z[30]_INST_0_i_120_n_0\
);
\z[30]_INST_0_i_121\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_180_n_0\,
I1 => \z[30]_INST_0_i_203_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_177_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_178_n_0\,
O => \z[30]_INST_0_i_121_n_0\
);
\z[30]_INST_0_i_122\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_184_n_0\,
I1 => \z[30]_INST_0_i_204_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_181_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_182_n_0\,
O => \z[30]_INST_0_i_122_n_0\
);
\z[30]_INST_0_i_123\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_188_n_0\,
I1 => \z[30]_INST_0_i_205_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_185_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_186_n_0\,
O => \z[30]_INST_0_i_123_n_0\
);
\z[30]_INST_0_i_124\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \z[30]_INST_0_i_206_n_0\,
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \z[30]_INST_0_i_207_n_0\,
I3 => \z[30]_INST_0_i_95_n_0\,
I4 => \z[30]_INST_0_i_208_n_0\,
O => \z[30]_INST_0_i_124_n_0\
);
\z[30]_INST_0_i_125\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \z[30]_INST_0_i_209_n_0\,
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \z[30]_INST_0_i_132_n_0\,
I3 => \z[30]_INST_0_i_95_n_0\,
I4 => \z[30]_INST_0_i_210_n_0\,
O => \z[30]_INST_0_i_125_n_0\
);
\z[30]_INST_0_i_126\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[30]_INST_0_i_96_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_206_n_0\,
I3 => \z[30]_INST_0_i_118_n_0\,
I4 => \z[30]_INST_0_i_207_n_0\,
O => \z[30]_INST_0_i_126_n_0\
);
\z[30]_INST_0_i_127\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[30]_INST_0_i_172_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_209_n_0\,
I3 => \z[30]_INST_0_i_118_n_0\,
I4 => \z[30]_INST_0_i_132_n_0\,
O => \z[30]_INST_0_i_127_n_0\
);
\z[30]_INST_0_i_128\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA03030AFA03F3F"
)
port map (
I0 => \z[30]_INST_0_i_211_n_0\,
I1 => \z[30]_INST_0_i_212_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_213_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_202_n_0\,
O => \z[30]_INST_0_i_128_n_0\
);
\z[30]_INST_0_i_129\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => \z[30]_INST_0_i_178_n_0\,
I1 => \z[30]_INST_0_i_214_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_180_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_203_n_0\,
O => \z[30]_INST_0_i_129_n_0\
);
\z[30]_INST_0_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"115F1F5F"
)
port map (
I0 => \z[30]_INST_0_i_52_n_0\,
I1 => \z[30]_INST_0_i_53_n_0\,
I2 => \z[30]_INST_0_i_54_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_55_n_0\,
O => \z[30]_INST_0_i_13_n_0\
);
\z[30]_INST_0_i_130\: unisim.vcomponents.LUT6
generic map(
INIT => X"505FC0C0505FCFCF"
)
port map (
I0 => \z[30]_INST_0_i_182_n_0\,
I1 => \z[30]_INST_0_i_215_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_184_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_204_n_0\,
O => \z[30]_INST_0_i_130_n_0\
);
\z[30]_INST_0_i_131\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0AF3030A0AF3F3F"
)
port map (
I0 => \z[30]_INST_0_i_216_n_0\,
I1 => \z[30]_INST_0_i_217_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_188_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_205_n_0\,
O => \z[30]_INST_0_i_131_n_0\
);
\z[30]_INST_0_i_132\: unisim.vcomponents.LUT6
generic map(
INIT => X"1510D5DFFFFFFFFF"
)
port map (
I0 => \msb1__1\(0),
I1 => L1_carry_i_17_n_0,
I2 => L1,
I3 => \_carry_n_5\,
I4 => \msb1__1\(8),
I5 => \z[30]_INST_0_i_194_n_0\,
O => \z[30]_INST_0_i_132_n_0\
);
\z[30]_INST_0_i_133\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF444F4FFF777F7"
)
port map (
I0 => \msb1__1\(4),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \_carry_n_4\,
I3 => L1,
I4 => L1_carry_i_14_n_0,
I5 => \msb1__1\(12),
O => \z[30]_INST_0_i_133_n_0\
);
\z[30]_INST_0_i_134\: unisim.vcomponents.LUT6
generic map(
INIT => X"1510D5DFFFFFFFFF"
)
port map (
I0 => \msb1__1\(2),
I1 => L1_carry_i_17_n_0,
I2 => L1,
I3 => \_carry_n_5\,
I4 => \msb1__1\(10),
I5 => \z[30]_INST_0_i_194_n_0\,
O => \z[30]_INST_0_i_134_n_0\
);
\z[30]_INST_0_i_135\: unisim.vcomponents.LUT6
generic map(
INIT => X"1510D5DFFFFFFFFF"
)
port map (
I0 => \msb1__1\(6),
I1 => L1_carry_i_17_n_0,
I2 => L1,
I3 => \_carry_n_5\,
I4 => \msb1__1\(14),
I5 => \z[30]_INST_0_i_194_n_0\,
O => \z[30]_INST_0_i_135_n_0\
);
\z[30]_INST_0_i_136\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFBBA088"
)
port map (
I0 => \z[30]_INST_0_i_207_n_0\,
I1 => \_carry_n_6\,
I2 => L1_carry_i_16_n_0,
I3 => L1,
I4 => \z[30]_INST_0_i_146_n_0\,
O => \z[30]_INST_0_i_136_n_0\
);
\z[30]_INST_0_i_137\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFBBA088"
)
port map (
I0 => \z[30]_INST_0_i_218_n_0\,
I1 => \_carry_n_6\,
I2 => L1_carry_i_16_n_0,
I3 => L1,
I4 => \z[30]_INST_0_i_148_n_0\,
O => \z[30]_INST_0_i_137_n_0\
);
\z[30]_INST_0_i_138\: unisim.vcomponents.LUT6
generic map(
INIT => X"B080FFFFB0800000"
)
port map (
I0 => \msb1__1\(36),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(20),
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_217_n_0\,
O => \z[30]_INST_0_i_138_n_0\
);
\z[30]_INST_0_i_139\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8BB8888B8B88888"
)
port map (
I0 => \z[30]_INST_0_i_188_n_0\,
I1 => L1_carry_i_17_n_0,
I2 => \msb1__1\(40),
I3 => L1_carry_i_14_n_0,
I4 => L1_carry_i_15_n_0,
I5 => \msb1__1\(24),
O => \z[30]_INST_0_i_139_n_0\
);
\z[30]_INST_0_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0DDD0D0000DD0D"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_56_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_58_n_0\,
I4 => \z[30]_INST_0_i_43_n_0\,
I5 => \z[30]_INST_0_i_59_n_0\,
O => \z[30]_INST_0_i_14_n_0\
);
\z[30]_INST_0_i_140\: unisim.vcomponents.LUT6
generic map(
INIT => X"B080FFFFB0800000"
)
port map (
I0 => \msb1__1\(37),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(21),
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_212_n_0\,
O => \z[30]_INST_0_i_140_n_0\
);
\z[30]_INST_0_i_141\: unisim.vcomponents.LUT6
generic map(
INIT => X"B080FFFFB0800000"
)
port map (
I0 => \msb1__1\(33),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(17),
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_202_n_0\,
O => \z[30]_INST_0_i_141_n_0\
);
\z[30]_INST_0_i_142\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_178_n_0\,
I1 => \z[30]_INST_0_i_214_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_180_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_203_n_0\,
O => \z[30]_INST_0_i_142_n_0\
);
\z[30]_INST_0_i_143\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[30]_INST_0_i_208_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_207_n_0\,
I3 => \z[30]_INST_0_i_118_n_0\,
I4 => \z[30]_INST_0_i_146_n_0\,
O => \z[30]_INST_0_i_143_n_0\
);
\z[30]_INST_0_i_144\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[30]_INST_0_i_210_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_132_n_0\,
I3 => \z[30]_INST_0_i_118_n_0\,
I4 => \z[30]_INST_0_i_133_n_0\,
O => \z[30]_INST_0_i_144_n_0\
);
\z[30]_INST_0_i_145\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_186_n_0\,
I1 => \z[30]_INST_0_i_217_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_188_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_205_n_0\,
O => \z[30]_INST_0_i_145_n_0\
);
\z[30]_INST_0_i_146\: unisim.vcomponents.LUT6
generic map(
INIT => X"4747FF47FFFFFF47"
)
port map (
I0 => \msb1__1\(5),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \msb1__1\(13),
I3 => \_carry_n_4\,
I4 => L1,
I5 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_146_n_0\
);
\z[30]_INST_0_i_147\: unisim.vcomponents.LUT6
generic map(
INIT => X"77CF44CC77CF77CF"
)
port map (
I0 => \msb1__1\(9),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \msb1__1\(1),
I3 => \z[30]_INST_0_i_194_n_0\,
I4 => \z[30]_INST_0_i_170_n_0\,
I5 => \msb1__1\(17),
O => \z[30]_INST_0_i_147_n_0\
);
\z[30]_INST_0_i_148\: unisim.vcomponents.LUT6
generic map(
INIT => X"7757555777F7FFF7"
)
port map (
I0 => \z[30]_INST_0_i_194_n_0\,
I1 => \msb1__1\(15),
I2 => \_carry_n_5\,
I3 => L1,
I4 => L1_carry_i_17_n_0,
I5 => \msb1__1\(7),
O => \z[30]_INST_0_i_148_n_0\
);
\z[30]_INST_0_i_149\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00FFFF47474747"
)
port map (
I0 => \msb1__1\(19),
I1 => \z[30]_INST_0_i_194_n_0\,
I2 => \msb1__1\(3),
I3 => \z[30]_INST_0_i_170_n_0\,
I4 => \msb1__1\(11),
I5 => \z[30]_INST_0_i_169_n_0\,
O => \z[30]_INST_0_i_149_n_0\
);
\z[30]_INST_0_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[30]_INST_0_i_60_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[30]_INST_0_i_61_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_62_n_0\,
O => \z[30]_INST_0_i_15_n_0\
);
\z[30]_INST_0_i_150\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFBBA088"
)
port map (
I0 => \z[30]_INST_0_i_133_n_0\,
I1 => \_carry_n_6\,
I2 => L1_carry_i_16_n_0,
I3 => L1,
I4 => \z[30]_INST_0_i_166_n_0\,
O => \z[30]_INST_0_i_150_n_0\
);
\z[30]_INST_0_i_151\: unisim.vcomponents.LUT5
generic map(
INIT => X"F5DD0511"
)
port map (
I0 => \z[30]_INST_0_i_163_n_0\,
I1 => \_carry_n_6\,
I2 => L1_carry_i_16_n_0,
I3 => L1,
I4 => \z[30]_INST_0_i_135_n_0\,
O => \z[30]_INST_0_i_151_n_0\
);
\z[30]_INST_0_i_152\: unisim.vcomponents.LUT5
generic map(
INIT => X"B888B8BB"
)
port map (
I0 => \z[30]_INST_0_i_219_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_211_n_0\,
I3 => L1_carry_i_17_n_0,
I4 => \z[30]_INST_0_i_212_n_0\,
O => \z[30]_INST_0_i_152_n_0\
);
\z[30]_INST_0_i_153\: unisim.vcomponents.LUT6
generic map(
INIT => X"505FC0C0505FCFCF"
)
port map (
I0 => \z[30]_INST_0_i_203_n_0\,
I1 => \z[30]_INST_0_i_220_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_178_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_214_n_0\,
O => \z[30]_INST_0_i_153_n_0\
);
\z[30]_INST_0_i_154\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \z[30]_INST_0_i_221_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_182_n_0\,
I3 => L1_carry_i_17_n_0,
I4 => \z[30]_INST_0_i_215_n_0\,
O => \z[30]_INST_0_i_154_n_0\
);
\z[30]_INST_0_i_155\: unisim.vcomponents.LUT5
generic map(
INIT => X"B888B8BB"
)
port map (
I0 => \z[30]_INST_0_i_222_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_216_n_0\,
I3 => L1_carry_i_17_n_0,
I4 => \z[30]_INST_0_i_217_n_0\,
O => \z[30]_INST_0_i_155_n_0\
);
\z[30]_INST_0_i_156\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFBBA088"
)
port map (
I0 => \z[30]_INST_0_i_146_n_0\,
I1 => \_carry_n_6\,
I2 => L1_carry_i_16_n_0,
I3 => L1,
I4 => \z[30]_INST_0_i_147_n_0\,
O => \z[30]_INST_0_i_156_n_0\
);
\z[30]_INST_0_i_157\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFBBA088"
)
port map (
I0 => \z[30]_INST_0_i_134_n_0\,
I1 => \_carry_n_6\,
I2 => L1_carry_i_16_n_0,
I3 => L1,
I4 => \z[30]_INST_0_i_135_n_0\,
O => \z[30]_INST_0_i_157_n_0\
);
\z[30]_INST_0_i_158\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \z[30]_INST_0_i_223_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_203_n_0\,
I3 => L1_carry_i_17_n_0,
I4 => \z[30]_INST_0_i_220_n_0\,
O => \z[30]_INST_0_i_158_n_0\
);
\z[30]_INST_0_i_159\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_224_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_219_n_0\,
O => \z[30]_INST_0_i_159_n_0\
);
\z[30]_INST_0_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"115F1F5F"
)
port map (
I0 => \z[30]_INST_0_i_63_n_0\,
I1 => \z[30]_INST_0_i_64_n_0\,
I2 => \z[30]_INST_0_i_65_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_66_n_0\,
O => \z[30]_INST_0_i_16_n_0\
);
\z[30]_INST_0_i_160\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_225_n_0\,
I1 => \z[30]_INST_0_i_222_n_0\,
I2 => \_carry_i_10_n_0\,
I3 => \z[30]_INST_0_i_221_n_0\,
I4 => L1_carry_i_16_n_0,
I5 => \z[30]_INST_0_i_226_n_0\,
O => \z[30]_INST_0_i_160_n_0\
);
\z[30]_INST_0_i_161\: unisim.vcomponents.LUT5
generic map(
INIT => X"B888B8BB"
)
port map (
I0 => \z[30]_INST_0_i_166_n_0\,
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \z[30]_INST_0_i_227_n_0\,
I3 => \z[30]_INST_0_i_169_n_0\,
I4 => \z[30]_INST_0_i_228_n_0\,
O => \z[30]_INST_0_i_161_n_0\
);
\z[30]_INST_0_i_162\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \msb1__1\(14),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \msb1__1\(6),
I3 => \z[30]_INST_0_i_170_n_0\,
I4 => \msb1__1\(22),
O => \z[30]_INST_0_i_162_n_0\
);
\z[30]_INST_0_i_163\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \msb1__1\(10),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \msb1__1\(2),
I3 => \z[30]_INST_0_i_170_n_0\,
I4 => \msb1__1\(18),
O => \z[30]_INST_0_i_163_n_0\
);
\z[30]_INST_0_i_164\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_223_n_0\,
I1 => \z[30]_INST_0_i_229_n_0\,
I2 => \_carry_i_10_n_0\,
I3 => \z[30]_INST_0_i_219_n_0\,
I4 => L1_carry_i_16_n_0,
I5 => \z[30]_INST_0_i_230_n_0\,
O => \z[30]_INST_0_i_164_n_0\
);
\z[30]_INST_0_i_165\: unisim.vcomponents.LUT5
generic map(
INIT => X"47CC47FF"
)
port map (
I0 => \msb1__1\(13),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \msb1__1\(21),
I3 => \z[30]_INST_0_i_194_n_0\,
I4 => \msb1__1\(5),
O => \z[30]_INST_0_i_165_n_0\
);
\z[30]_INST_0_i_166\: unisim.vcomponents.LUT6
generic map(
INIT => X"4447CCCF4447FFFF"
)
port map (
I0 => \msb1__1\(8),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \z[30]_INST_0_i_170_n_0\,
I3 => \msb1__1\(16),
I4 => \z[30]_INST_0_i_194_n_0\,
I5 => \msb1__1\(0),
O => \z[30]_INST_0_i_166_n_0\
);
\z[30]_INST_0_i_167\: unisim.vcomponents.LUT6
generic map(
INIT => X"B0BFB0B0B0BFBFBF"
)
port map (
I0 => \z[30]_INST_0_i_170_n_0\,
I1 => \msb1__1\(12),
I2 => \z[30]_INST_0_i_169_n_0\,
I3 => \msb1__1\(20),
I4 => \z[30]_INST_0_i_194_n_0\,
I5 => \msb1__1\(4),
O => \z[30]_INST_0_i_167_n_0\
);
\z[30]_INST_0_i_168\: unisim.vcomponents.LUT6
generic map(
INIT => X"7477FFFF74770000"
)
port map (
I0 => \z[30]_INST_0_i_217_n_0\,
I1 => L1_carry_i_17_n_0,
I2 => L1_carry_i_14_n_0,
I3 => \z[30]_INST_0_i_231_n_0\,
I4 => L1_carry_i_16_n_0,
I5 => \z[30]_INST_0_i_222_n_0\,
O => \z[30]_INST_0_i_168_n_0\
);
\z[30]_INST_0_i_169\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA6FFFFAAA60000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1,
I5 => \_carry_n_5\,
O => \z[30]_INST_0_i_169_n_0\
);
\z[30]_INST_0_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0DDD0D0000DD0D"
)
port map (
I0 => \z[30]_INST_0_i_43_n_0\,
I1 => \z[30]_INST_0_i_67_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_68_n_0\,
I4 => L1,
I5 => \z[30]_INST_0_i_69_n_0\,
O => \z[30]_INST_0_i_17_n_0\
);
\z[30]_INST_0_i_170\: unisim.vcomponents.LUT6
generic map(
INIT => X"9A55FFFF9A550000"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => \z[30]_INST_0_i_232_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => L1_carry_i_9_n_0,
I4 => L1,
I5 => \_carry_n_4\,
O => \z[30]_INST_0_i_170_n_0\
);
\z[30]_INST_0_i_171\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF7FFF7FFF70FF7F"
)
port map (
I0 => \z[30]_INST_0_i_194_n_0\,
I1 => \msb1__1\(0),
I2 => \z[30]_INST_0_i_118_n_0\,
I3 => \z[30]_INST_0_i_169_n_0\,
I4 => \msb1__1\(4),
I5 => \z[30]_INST_0_i_170_n_0\,
O => \z[30]_INST_0_i_171_n_0\
);
\z[30]_INST_0_i_172\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4FFF7FF"
)
port map (
I0 => \msb1__1\(2),
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \z[30]_INST_0_i_169_n_0\,
I3 => \z[30]_INST_0_i_194_n_0\,
I4 => \msb1__1\(6),
O => \z[30]_INST_0_i_172_n_0\
);
\z[30]_INST_0_i_173\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(29),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(13),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(45),
O => \z[30]_INST_0_i_173_n_0\
);
\z[30]_INST_0_i_174\: unisim.vcomponents.LUT4
generic map(
INIT => X"B080"
)
port map (
I0 => \msb1__1\(37),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(21),
O => \z[30]_INST_0_i_174_n_0\
);
\z[30]_INST_0_i_175\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(25),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(9),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(41),
O => \z[30]_INST_0_i_175_n_0\
);
\z[30]_INST_0_i_176\: unisim.vcomponents.LUT4
generic map(
INIT => X"B080"
)
port map (
I0 => \msb1__1\(33),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(17),
O => \z[30]_INST_0_i_176_n_0\
);
\z[30]_INST_0_i_177\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(27),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(11),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(43),
O => \z[30]_INST_0_i_177_n_0\
);
\z[30]_INST_0_i_178\: unisim.vcomponents.LUT4
generic map(
INIT => X"88C0"
)
port map (
I0 => \msb1__1\(19),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(35),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_178_n_0\
);
\z[30]_INST_0_i_179\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(23),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(7),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(39),
O => \z[30]_INST_0_i_179_n_0\
);
\z[30]_INST_0_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0DDD0D0000DD0D"
)
port map (
I0 => \z[30]_INST_0_i_43_n_0\,
I1 => \z[30]_INST_0_i_68_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_70_n_0\,
I4 => L1,
I5 => \z[30]_INST_0_i_71_n_0\,
O => \z[30]_INST_0_i_18_n_0\
);
\z[30]_INST_0_i_180\: unisim.vcomponents.LUT5
generic map(
INIT => X"ACACF000"
)
port map (
I0 => \msb1__1\(15),
I1 => \msb1__1\(47),
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(31),
I4 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_180_n_0\
);
\z[30]_INST_0_i_181\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(30),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(14),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(46),
O => \z[30]_INST_0_i_181_n_0\
);
\z[30]_INST_0_i_182\: unisim.vcomponents.LUT4
generic map(
INIT => X"88C0"
)
port map (
I0 => \msb1__1\(22),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(38),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_182_n_0\
);
\z[30]_INST_0_i_183\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(26),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(10),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(42),
O => \z[30]_INST_0_i_183_n_0\
);
\z[30]_INST_0_i_184\: unisim.vcomponents.LUT4
generic map(
INIT => X"88C0"
)
port map (
I0 => \msb1__1\(18),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(34),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_184_n_0\
);
\z[30]_INST_0_i_185\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(28),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(12),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(44),
O => \z[30]_INST_0_i_185_n_0\
);
\z[30]_INST_0_i_186\: unisim.vcomponents.LUT4
generic map(
INIT => X"B080"
)
port map (
I0 => \msb1__1\(36),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(20),
O => \z[30]_INST_0_i_186_n_0\
);
\z[30]_INST_0_i_187\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(24),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(8),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(40),
O => \z[30]_INST_0_i_187_n_0\
);
\z[30]_INST_0_i_188\: unisim.vcomponents.LUT4
generic map(
INIT => X"88C0"
)
port map (
I0 => \msb1__1\(16),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(32),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_188_n_0\
);
\z[30]_INST_0_i_189\: unisim.vcomponents.LUT6
generic map(
INIT => X"BFFFFFFFBFFFBFBF"
)
port map (
I0 => \z[30]_INST_0_i_118_n_0\,
I1 => \msb1__1\(2),
I2 => \z[30]_INST_0_i_194_n_0\,
I3 => L1_carry_i_17_n_0,
I4 => L1,
I5 => \_carry_n_5\,
O => \z[30]_INST_0_i_189_n_0\
);
\z[30]_INST_0_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0DDD0D0000DD0D"
)
port map (
I0 => \z[30]_INST_0_i_57_n_0\,
I1 => \z[30]_INST_0_i_72_n_0\,
I2 => \z[30]_INST_0_i_43_n_0\,
I3 => \z[30]_INST_0_i_70_n_0\,
I4 => L1,
I5 => \z[30]_INST_0_i_73_n_0\,
O => \z[30]_INST_0_i_19_n_0\
);
\z[30]_INST_0_i_190\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(22),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(6),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(38),
O => \z[30]_INST_0_i_190_n_0\
);
\z[30]_INST_0_i_191\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(20),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(4),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(36),
O => \z[30]_INST_0_i_191_n_0\
);
\z[30]_INST_0_i_192\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(21),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(5),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(37),
O => \z[30]_INST_0_i_192_n_0\
);
\z[30]_INST_0_i_193\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(19),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(3),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(35),
O => \z[30]_INST_0_i_193_n_0\
);
\z[30]_INST_0_i_194\: unisim.vcomponents.LUT6
generic map(
INIT => X"5DA200005DA2FFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => \z[30]_INST_0_i_232_n_0\,
I3 => L1_carry_i_12_n_0,
I4 => L1,
I5 => \_carry_n_4\,
O => \z[30]_INST_0_i_194_n_0\
);
\z[30]_INST_0_i_195\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(18),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(2),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(34),
O => \z[30]_INST_0_i_195_n_0\
);
\z[30]_INST_0_i_196\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(16),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(0),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(32),
O => \z[30]_INST_0_i_196_n_0\
);
\z[30]_INST_0_i_197\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(17),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(1),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(33),
O => \z[30]_INST_0_i_197_n_0\
);
\z[30]_INST_0_i_198\: unisim.vcomponents.LUT5
generic map(
INIT => X"555DAAA2"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
O => \z[30]_INST_0_i_198_n_0\
);
\z[30]_INST_0_i_199\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \_carry__2_n_4\,
I1 => \_carry__3_n_4\,
I2 => \_carry__4_n_4\,
I3 => \_carry__5_n_5\,
I4 => \z[30]_INST_0_i_233_n_0\,
O => \z[30]_INST_0_i_199_n_0\
);
\z[30]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFB"
)
port map (
I0 => \z[30]_INST_0_i_11_n_0\,
I1 => sel0(10),
I2 => \z[30]_INST_0_i_13_n_0\,
I3 => \z[30]_INST_0_i_14_n_0\,
I4 => \z[30]_INST_0_i_15_n_0\,
I5 => \z[30]_INST_0_i_16_n_0\,
O => \z[30]_INST_0_i_2_n_0\
);
\z[30]_INST_0_i_20\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0DDD0D0000DD0D"
)
port map (
I0 => \z[30]_INST_0_i_43_n_0\,
I1 => \z[30]_INST_0_i_72_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_59_n_0\,
I4 => L1,
I5 => \z[30]_INST_0_i_74_n_0\,
O => \z[30]_INST_0_i_20_n_0\
);
\z[30]_INST_0_i_200\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \_carry__1_n_4\,
I1 => \_carry__6_n_6\,
I2 => \_carry__0_n_7\,
I3 => \_carry__4_n_5\,
I4 => \z[30]_INST_0_i_234_n_0\,
O => \z[30]_INST_0_i_200_n_0\
);
\z[30]_INST_0_i_201\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \_carry__2_n_5\,
I1 => \_carry__6_n_7\,
I2 => \_carry__0_n_4\,
I3 => \_carry__5_n_7\,
I4 => \z[30]_INST_0_i_235_n_0\,
O => \z[30]_INST_0_i_201_n_0\
);
\z[30]_INST_0_i_202\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(41),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(25),
O => \z[30]_INST_0_i_202_n_0\
);
\z[30]_INST_0_i_203\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(39),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(23),
O => \z[30]_INST_0_i_203_n_0\
);
\z[30]_INST_0_i_204\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(42),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(26),
O => \z[30]_INST_0_i_204_n_0\
);
\z[30]_INST_0_i_205\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(40),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(24),
O => \z[30]_INST_0_i_205_n_0\
);
\z[30]_INST_0_i_206\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF3FFFFFFF3FAFAF"
)
port map (
I0 => \_carry_n_5\,
I1 => L1_carry_i_17_n_0,
I2 => \msb1__1\(5),
I3 => L1_carry_i_14_n_0,
I4 => L1,
I5 => \_carry_n_4\,
O => \z[30]_INST_0_i_206_n_0\
);
\z[30]_INST_0_i_207\: unisim.vcomponents.LUT6
generic map(
INIT => X"4747FF47FFFFFF47"
)
port map (
I0 => \msb1__1\(1),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \msb1__1\(9),
I3 => \_carry_n_4\,
I4 => L1,
I5 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_207_n_0\
);
\z[30]_INST_0_i_208\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFCF44FFFFCF77"
)
port map (
I0 => \msb1__1\(7),
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \msb1__1\(3),
I3 => \z[30]_INST_0_i_169_n_0\,
I4 => \z[30]_INST_0_i_170_n_0\,
I5 => \msb1__1\(11),
O => \z[30]_INST_0_i_208_n_0\
);
\z[30]_INST_0_i_209\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF3FFFFFFF3FAFAF"
)
port map (
I0 => \_carry_n_5\,
I1 => L1_carry_i_17_n_0,
I2 => \msb1__1\(4),
I3 => L1_carry_i_14_n_0,
I4 => L1,
I5 => \_carry_n_4\,
O => \z[30]_INST_0_i_209_n_0\
);
\z[30]_INST_0_i_21\: unisim.vcomponents.LUT6
generic map(
INIT => X"101010FF10101010"
)
port map (
I0 => \z[30]_INST_0_i_75_n_0\,
I1 => \z[30]_INST_0_i_76_n_0\,
I2 => \z[30]_INST_0_i_77_n_0\,
I3 => \z[30]_INST_0_i_78_n_0\,
I4 => \z[30]_INST_0_i_79_n_0\,
I5 => \z[30]_INST_0_i_80_n_0\,
O => \z[30]_INST_0_i_21_n_0\
);
\z[30]_INST_0_i_210\: unisim.vcomponents.LUT6
generic map(
INIT => X"CF44CF77FFFFFFFF"
)
port map (
I0 => \msb1__1\(6),
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \msb1__1\(2),
I3 => \z[30]_INST_0_i_169_n_0\,
I4 => \msb1__1\(10),
I5 => \z[30]_INST_0_i_194_n_0\,
O => \z[30]_INST_0_i_210_n_0\
);
\z[30]_INST_0_i_211\: unisim.vcomponents.LUT4
generic map(
INIT => X"773F"
)
port map (
I0 => \msb1__1\(21),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(37),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_211_n_0\
);
\z[30]_INST_0_i_212\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(45),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(29),
O => \z[30]_INST_0_i_212_n_0\
);
\z[30]_INST_0_i_213\: unisim.vcomponents.LUT4
generic map(
INIT => X"773F"
)
port map (
I0 => \msb1__1\(17),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(33),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_213_n_0\
);
\z[30]_INST_0_i_214\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(43),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(27),
O => \z[30]_INST_0_i_214_n_0\
);
\z[30]_INST_0_i_215\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F5F"
)
port map (
I0 => \msb1__1\(46),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(30),
O => \z[30]_INST_0_i_215_n_0\
);
\z[30]_INST_0_i_216\: unisim.vcomponents.LUT4
generic map(
INIT => X"773F"
)
port map (
I0 => \msb1__1\(20),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(36),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_216_n_0\
);
\z[30]_INST_0_i_217\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(44),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(28),
O => \z[30]_INST_0_i_217_n_0\
);
\z[30]_INST_0_i_218\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF444F4FFF777F7"
)
port map (
I0 => \msb1__1\(3),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \_carry_n_4\,
I3 => L1,
I4 => L1_carry_i_14_n_0,
I5 => \msb1__1\(11),
O => \z[30]_INST_0_i_218_n_0\
);
\z[30]_INST_0_i_219\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F103F1FFFFFFFFF"
)
port map (
I0 => \msb1__1\(25),
I1 => \msb1__1\(41),
I2 => L1_carry_i_17_n_0,
I3 => L1_carry_i_14_n_0,
I4 => \msb1__1\(33),
I5 => L1_carry_i_15_n_0,
O => \z[30]_INST_0_i_219_n_0\
);
\z[30]_INST_0_i_22\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0DDD0D0000DD0D"
)
port map (
I0 => \z[30]_INST_0_i_43_n_0\,
I1 => \z[30]_INST_0_i_81_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_82_n_0\,
I4 => L1,
I5 => \z[30]_INST_0_i_83_n_0\,
O => \z[30]_INST_0_i_22_n_0\
);
\z[30]_INST_0_i_220\: unisim.vcomponents.LUT4
generic map(
INIT => X"3777"
)
port map (
I0 => \msb1__1\(47),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(31),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_220_n_0\
);
\z[30]_INST_0_i_221\: unisim.vcomponents.LUT6
generic map(
INIT => X"103F1F3FFFFFFFFF"
)
port map (
I0 => \msb1__1\(26),
I1 => \msb1__1\(42),
I2 => L1_carry_i_17_n_0,
I3 => \z[30]_INST_0_i_198_n_0\,
I4 => \msb1__1\(34),
I5 => L1_carry_i_15_n_0,
O => \z[30]_INST_0_i_221_n_0\
);
\z[30]_INST_0_i_222\: unisim.vcomponents.LUT6
generic map(
INIT => X"103F1F3FFFFFFFFF"
)
port map (
I0 => \msb1__1\(24),
I1 => \msb1__1\(40),
I2 => L1_carry_i_17_n_0,
I3 => \z[30]_INST_0_i_198_n_0\,
I4 => \msb1__1\(32),
I5 => L1_carry_i_15_n_0,
O => \z[30]_INST_0_i_222_n_0\
);
\z[30]_INST_0_i_223\: unisim.vcomponents.LUT6
generic map(
INIT => X"103F1F3FFFFFFFFF"
)
port map (
I0 => \msb1__1\(27),
I1 => \msb1__1\(43),
I2 => L1_carry_i_17_n_0,
I3 => \z[30]_INST_0_i_198_n_0\,
I4 => \msb1__1\(35),
I5 => L1_carry_i_15_n_0,
O => \z[30]_INST_0_i_223_n_0\
);
\z[30]_INST_0_i_224\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F103F1FFFFFFFFF"
)
port map (
I0 => \msb1__1\(29),
I1 => \msb1__1\(45),
I2 => L1_carry_i_17_n_0,
I3 => L1_carry_i_14_n_0,
I4 => \msb1__1\(37),
I5 => L1_carry_i_15_n_0,
O => \z[30]_INST_0_i_224_n_0\
);
\z[30]_INST_0_i_225\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F103F1FFFFFFFFF"
)
port map (
I0 => \msb1__1\(28),
I1 => \msb1__1\(44),
I2 => L1_carry_i_17_n_0,
I3 => L1_carry_i_14_n_0,
I4 => \msb1__1\(36),
I5 => L1_carry_i_15_n_0,
O => \z[30]_INST_0_i_225_n_0\
);
\z[30]_INST_0_i_226\: unisim.vcomponents.LUT6
generic map(
INIT => X"E0E0E0E0E0EFEFEF"
)
port map (
I0 => \z[30]_INST_0_i_236_n_0\,
I1 => \z[30]_INST_0_i_237_n_0\,
I2 => L1_carry_i_17_n_0,
I3 => \msb1__1\(46),
I4 => L1_carry_i_15_n_0,
I5 => \z[30]_INST_0_i_238_n_0\,
O => \z[30]_INST_0_i_226_n_0\
);
\z[30]_INST_0_i_227\: unisim.vcomponents.LUT4
generic map(
INIT => X"E2FF"
)
port map (
I0 => \_carry_n_4\,
I1 => L1,
I2 => L1_carry_i_14_n_0,
I3 => \msb1__1\(12),
O => \z[30]_INST_0_i_227_n_0\
);
\z[30]_INST_0_i_228\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFBA808A"
)
port map (
I0 => \msb1__1\(20),
I1 => \z[30]_INST_0_i_198_n_0\,
I2 => L1,
I3 => \_carry_n_4\,
I4 => \msb1__1\(4),
O => \z[30]_INST_0_i_228_n_0\
);
\z[30]_INST_0_i_229\: unisim.vcomponents.LUT6
generic map(
INIT => X"10105050101F5F5F"
)
port map (
I0 => \z[30]_INST_0_i_239_n_0\,
I1 => \msb1__1\(39),
I2 => L1_carry_i_17_n_0,
I3 => \msb1__1\(47),
I4 => L1_carry_i_15_n_0,
I5 => \z[30]_INST_0_i_240_n_0\,
O => \z[30]_INST_0_i_229_n_0\
);
\z[30]_INST_0_i_230\: unisim.vcomponents.LUT6
generic map(
INIT => X"50503030505F3F3F"
)
port map (
I0 => \z[30]_INST_0_i_241_n_0\,
I1 => \z[30]_INST_0_i_242_n_0\,
I2 => L1_carry_i_17_n_0,
I3 => \z[30]_INST_0_i_243_n_0\,
I4 => \z[30]_INST_0_i_198_n_0\,
I5 => \z[30]_INST_0_i_244_n_0\,
O => \z[30]_INST_0_i_230_n_0\
);
\z[30]_INST_0_i_231\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => L1_carry_i_15_n_0,
I1 => \msb1__1\(36),
O => \z[30]_INST_0_i_231_n_0\
);
\z[30]_INST_0_i_232\: unisim.vcomponents.LUT6
generic map(
INIT => X"AEAEAEAEFFFFFFAE"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_29_n_0,
I2 => L1_carry_i_28_n_0,
I3 => \z[30]_INST_0_i_245_n_0\,
I4 => L1_carry_i_25_n_0,
I5 => L1_carry_i_24_n_0,
O => \z[30]_INST_0_i_232_n_0\
);
\z[30]_INST_0_i_233\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \_carry__2_n_6\,
I1 => \_carry__1_n_6\,
I2 => \_carry__3_n_6\,
I3 => \_carry__1_n_7\,
O => \z[30]_INST_0_i_233_n_0\
);
\z[30]_INST_0_i_234\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \_carry__2_n_7\,
I1 => L1,
I2 => \_carry__3_n_5\,
I3 => \_carry__1_n_5\,
O => \z[30]_INST_0_i_234_n_0\
);
\z[30]_INST_0_i_235\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \_carry__5_n_4\,
I1 => \_carry__3_n_7\,
I2 => \_carry__4_n_6\,
I3 => \_carry__4_n_7\,
O => \z[30]_INST_0_i_235_n_0\
);
\z[30]_INST_0_i_236\: unisim.vcomponents.LUT6
generic map(
INIT => X"C3CC333341441111"
)
port map (
I0 => \msb1__1\(38),
I1 => L1_carry_i_12_n_0,
I2 => \z[30]_INST_0_i_232_n_0\,
I3 => \_carry_i_1_n_0\,
I4 => L1_carry_i_9_n_0,
I5 => L1_carry_i_13_n_0,
O => \z[30]_INST_0_i_236_n_0\
);
\z[30]_INST_0_i_237\: unisim.vcomponents.LUT6
generic map(
INIT => X"343344441C11CCCC"
)
port map (
I0 => \msb1__1\(22),
I1 => L1_carry_i_12_n_0,
I2 => \z[30]_INST_0_i_232_n_0\,
I3 => \_carry_i_1_n_0\,
I4 => L1_carry_i_9_n_0,
I5 => L1_carry_i_13_n_0,
O => \z[30]_INST_0_i_237_n_0\
);
\z[30]_INST_0_i_238\: unisim.vcomponents.LUT6
generic map(
INIT => X"0808880820200020"
)
port map (
I0 => \msb1__1\(30),
I1 => L1_carry_i_13_n_0,
I2 => L1_carry_i_9_n_0,
I3 => \_carry_i_1_n_0\,
I4 => \z[30]_INST_0_i_232_n_0\,
I5 => L1_carry_i_12_n_0,
O => \z[30]_INST_0_i_238_n_0\
);
\z[30]_INST_0_i_239\: unisim.vcomponents.LUT6
generic map(
INIT => X"0808880820200020"
)
port map (
I0 => \msb1__1\(23),
I1 => L1_carry_i_13_n_0,
I2 => L1_carry_i_9_n_0,
I3 => \_carry_i_1_n_0\,
I4 => \z[30]_INST_0_i_232_n_0\,
I5 => L1_carry_i_12_n_0,
O => \z[30]_INST_0_i_239_n_0\
);
\z[30]_INST_0_i_240\: unisim.vcomponents.LUT6
generic map(
INIT => X"0800888820220000"
)
port map (
I0 => \msb1__1\(31),
I1 => L1_carry_i_12_n_0,
I2 => \z[30]_INST_0_i_232_n_0\,
I3 => \_carry_i_1_n_0\,
I4 => L1_carry_i_9_n_0,
I5 => L1_carry_i_13_n_0,
O => \z[30]_INST_0_i_240_n_0\
);
\z[30]_INST_0_i_241\: unisim.vcomponents.LUT6
generic map(
INIT => X"66A6555500000000"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => L1_carry_i_9_n_0,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_232_n_0\,
I4 => L1_carry_i_12_n_0,
I5 => \msb1__1\(21),
O => \z[30]_INST_0_i_241_n_0\
);
\z[30]_INST_0_i_242\: unisim.vcomponents.LUT6
generic map(
INIT => X"66A6555500000000"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => L1_carry_i_9_n_0,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_232_n_0\,
I4 => L1_carry_i_12_n_0,
I5 => \msb1__1\(37),
O => \z[30]_INST_0_i_242_n_0\
);
\z[30]_INST_0_i_243\: unisim.vcomponents.LUT6
generic map(
INIT => X"66A6555500000000"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => L1_carry_i_9_n_0,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_232_n_0\,
I4 => L1_carry_i_12_n_0,
I5 => \msb1__1\(29),
O => \z[30]_INST_0_i_243_n_0\
);
\z[30]_INST_0_i_244\: unisim.vcomponents.LUT6
generic map(
INIT => X"66A6555500000000"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => L1_carry_i_9_n_0,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_232_n_0\,
I4 => L1_carry_i_12_n_0,
I5 => \msb1__1\(45),
O => \z[30]_INST_0_i_244_n_0\
);
\z[30]_INST_0_i_245\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFF5D5"
)
port map (
I0 => L1_carry_i_27_n_0,
I1 => \msb1__1\(32),
I2 => \z[30]_INST_0_i_246_n_0\,
I3 => \msb1__1\(33),
I4 => \msb1__1\(36),
I5 => \msb1__1\(37),
O => \z[30]_INST_0_i_245_n_0\
);
\z[30]_INST_0_i_246\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(35),
I1 => \msb1__1\(34),
O => \z[30]_INST_0_i_246_n_0\
);
\z[30]_INST_0_i_29\: unisim.vcomponents.LUT6
generic map(
INIT => X"4700FFFF47004700"
)
port map (
I0 => \z[30]_INST_0_i_94_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_96_n_0\,
I3 => \z[30]_INST_0_i_43_n_0\,
I4 => \z[30]_INST_0_i_97_n_0\,
I5 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_29_n_0\
);
\z[30]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \z[30]_INST_0_i_17_n_0\,
I1 => \z[30]_INST_0_i_18_n_0\,
I2 => \z[30]_INST_0_i_19_n_0\,
I3 => \z[30]_INST_0_i_20_n_0\,
I4 => \z[30]_INST_0_i_21_n_0\,
I5 => \z[30]_INST_0_i_22_n_0\,
O => \z[30]_INST_0_i_3_n_0\
);
\z[30]_INST_0_i_30\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_98_n_0\,
I1 => \z[30]_INST_0_i_99_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_100_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_101_n_0\,
O => \z[30]_INST_0_i_30_n_0\
);
\z[30]_INST_0_i_31\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_102_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_103_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_31_n_0\
);
\z[30]_INST_0_i_32\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_104_n_0\,
I1 => \z[30]_INST_0_i_105_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_99_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_106_n_0\,
O => \z[30]_INST_0_i_32_n_0\
);
\z[30]_INST_0_i_33\: unisim.vcomponents.LUT6
generic map(
INIT => X"47FF474700FF0000"
)
port map (
I0 => \z[30]_INST_0_i_107_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_94_n_0\,
I3 => \z[30]_INST_0_i_97_n_0\,
I4 => \z[30]_INST_0_i_43_n_0\,
I5 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_33_n_0\
);
\z[30]_INST_0_i_34\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_101_n_0\,
I1 => \z[30]_INST_0_i_104_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_98_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_99_n_0\,
O => \z[30]_INST_0_i_34_n_0\
);
\z[30]_INST_0_i_35\: unisim.vcomponents.LUT6
generic map(
INIT => X"4700FFFF47004700"
)
port map (
I0 => \z[30]_INST_0_i_107_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_94_n_0\,
I3 => \z[30]_INST_0_i_43_n_0\,
I4 => \z[30]_INST_0_i_102_n_0\,
I5 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_35_n_0\
);
\z[30]_INST_0_i_36\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_99_n_0\,
I1 => \z[30]_INST_0_i_106_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_101_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_104_n_0\,
O => \z[30]_INST_0_i_36_n_0\
);
\z[30]_INST_0_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_106_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_108_n_0\,
O => \z[30]_INST_0_i_37_n_0\
);
\z[30]_INST_0_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_104_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_105_n_0\,
O => \z[30]_INST_0_i_38_n_0\
);
\z[30]_INST_0_i_39\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_103_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_109_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_39_n_0\
);
\z[30]_INST_0_i_40\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[30]_INST_0_i_110_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_111_n_0\,
I3 => L1_carry_i_16_n_0,
I4 => \z[30]_INST_0_i_112_n_0\,
O => \z[30]_INST_0_i_40_n_0\
);
\z[30]_INST_0_i_41\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[30]_INST_0_i_108_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_113_n_0\,
I3 => L1_carry_i_16_n_0,
I4 => \z[30]_INST_0_i_114_n_0\,
O => \z[30]_INST_0_i_41_n_0\
);
\z[30]_INST_0_i_42\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFD8"
)
port map (
I0 => L1,
I1 => L1_carry_i_16_n_0,
I2 => \_carry_n_6\,
I3 => \z[30]_INST_0_i_115_n_0\,
I4 => \z[30]_INST_0_i_95_n_0\,
O => \z[30]_INST_0_i_42_n_0\
);
\z[30]_INST_0_i_43\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \_carry_i_1_n_0\,
I1 => \z[30]_INST_0_i_116_n_0\,
O => \z[30]_INST_0_i_43_n_0\
);
\z[30]_INST_0_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_105_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_110_n_0\,
O => \z[30]_INST_0_i_44_n_0\
);
\z[30]_INST_0_i_45\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000040F00000404"
)
port map (
I0 => \z[30]_INST_0_i_117_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_95_n_0\,
I3 => \z[30]_INST_0_i_115_n_0\,
I4 => \z[30]_INST_0_i_118_n_0\,
I5 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_45_n_0\
);
\z[30]_INST_0_i_46\: unisim.vcomponents.LUT5
generic map(
INIT => X"10FF1010"
)
port map (
I0 => \z[30]_INST_0_i_95_n_0\,
I1 => \z[30]_INST_0_i_119_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_109_n_0\,
I4 => \z[30]_INST_0_i_43_n_0\,
O => \z[30]_INST_0_i_46_n_0\
);
\z[30]_INST_0_i_47\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_120_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_121_n_0\,
O => \z[30]_INST_0_i_47_n_0\
);
\z[30]_INST_0_i_48\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_122_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_123_n_0\,
O => \z[30]_INST_0_i_48_n_0\
);
\z[30]_INST_0_i_49\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_124_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_125_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_49_n_0\
);
\z[30]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"115F1F5F"
)
port map (
I0 => \z[30]_INST_0_i_29_n_0\,
I1 => \z[30]_INST_0_i_30_n_0\,
I2 => \z[30]_INST_0_i_31_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_32_n_0\,
O => \z[30]_INST_0_i_5_n_0\
);
\z[30]_INST_0_i_50\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_123_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_100_n_0\,
O => \z[30]_INST_0_i_50_n_0\
);
\z[30]_INST_0_i_51\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_125_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_126_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_51_n_0\
);
\z[30]_INST_0_i_52\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_126_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_127_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_52_n_0\
);
\z[30]_INST_0_i_53\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_121_n_0\,
I1 => \z[30]_INST_0_i_98_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_123_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_100_n_0\,
O => \z[30]_INST_0_i_53_n_0\
);
\z[30]_INST_0_i_54\: unisim.vcomponents.LUT6
generic map(
INIT => X"47FF474700FF0000"
)
port map (
I0 => \z[30]_INST_0_i_94_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_96_n_0\,
I3 => \z[30]_INST_0_i_127_n_0\,
I4 => \z[30]_INST_0_i_43_n_0\,
I5 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_54_n_0\
);
\z[30]_INST_0_i_55\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_100_n_0\,
I1 => \z[30]_INST_0_i_101_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_121_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_98_n_0\,
O => \z[30]_INST_0_i_55_n_0\
);
\z[30]_INST_0_i_56\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_128_n_0\,
I1 => \z[30]_INST_0_i_129_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_130_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_131_n_0\,
O => \z[30]_INST_0_i_56_n_0\
);
\z[30]_INST_0_i_57\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \_carry_i_1_n_0\,
I1 => \z[30]_INST_0_i_116_n_0\,
O => \z[30]_INST_0_i_57_n_0\
);
\z[30]_INST_0_i_58\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_132_n_0\,
I1 => \z[30]_INST_0_i_133_n_0\,
I2 => \z[30]_INST_0_i_95_n_0\,
I3 => \z[30]_INST_0_i_134_n_0\,
I4 => \z[30]_INST_0_i_118_n_0\,
I5 => \z[30]_INST_0_i_135_n_0\,
O => \z[30]_INST_0_i_58_n_0\
);
\z[30]_INST_0_i_59\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_136_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_137_n_0\,
O => \z[30]_INST_0_i_59_n_0\
);
\z[30]_INST_0_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"115F1F5F"
)
port map (
I0 => \z[30]_INST_0_i_33_n_0\,
I1 => \z[30]_INST_0_i_34_n_0\,
I2 => \z[30]_INST_0_i_35_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_36_n_0\,
O => \z[30]_INST_0_i_6_n_0\
);
\z[30]_INST_0_i_60\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \z[30]_INST_0_i_138_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_139_n_0\,
I3 => \_carry_i_10_n_0\,
I4 => \z[30]_INST_0_i_122_n_0\,
O => \z[30]_INST_0_i_60_n_0\
);
\z[30]_INST_0_i_61\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \z[30]_INST_0_i_140_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_141_n_0\,
I3 => \_carry_i_10_n_0\,
I4 => \z[30]_INST_0_i_142_n_0\,
O => \z[30]_INST_0_i_61_n_0\
);
\z[30]_INST_0_i_62\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_58_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_143_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_62_n_0\
);
\z[30]_INST_0_i_63\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_143_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_144_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_63_n_0\
);
\z[30]_INST_0_i_64\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_142_n_0\,
I1 => \z[30]_INST_0_i_120_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_145_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_122_n_0\,
O => \z[30]_INST_0_i_64_n_0\
);
\z[30]_INST_0_i_65\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_144_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_124_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_65_n_0\
);
\z[30]_INST_0_i_66\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_122_n_0\,
I1 => \z[30]_INST_0_i_123_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_142_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_120_n_0\,
O => \z[30]_INST_0_i_66_n_0\
);
\z[30]_INST_0_i_67\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_146_n_0\,
I1 => \z[30]_INST_0_i_147_n_0\,
I2 => \z[30]_INST_0_i_95_n_0\,
I3 => \z[30]_INST_0_i_148_n_0\,
I4 => \z[30]_INST_0_i_118_n_0\,
I5 => \z[30]_INST_0_i_149_n_0\,
O => \z[30]_INST_0_i_67_n_0\
);
\z[30]_INST_0_i_68\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_150_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_151_n_0\,
O => \z[30]_INST_0_i_68_n_0\
);
\z[30]_INST_0_i_69\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_152_n_0\,
I1 => \z[30]_INST_0_i_153_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_154_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_155_n_0\,
O => \z[30]_INST_0_i_69_n_0\
);
\z[30]_INST_0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_37_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_38_n_0\,
I4 => \z[30]_INST_0_i_39_n_0\,
O => sel0(3)
);
\z[30]_INST_0_i_70\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_137_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_156_n_0\,
O => \z[30]_INST_0_i_70_n_0\
);
\z[30]_INST_0_i_71\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_155_n_0\,
I1 => \z[30]_INST_0_i_130_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_152_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_153_n_0\,
O => \z[30]_INST_0_i_71_n_0\
);
\z[30]_INST_0_i_72\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_157_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_150_n_0\,
O => \z[30]_INST_0_i_72_n_0\
);
\z[30]_INST_0_i_73\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_153_n_0\,
I1 => \z[30]_INST_0_i_128_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_155_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_130_n_0\,
O => \z[30]_INST_0_i_73_n_0\
);
\z[30]_INST_0_i_74\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_130_n_0\,
I1 => \z[30]_INST_0_i_131_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_153_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_128_n_0\,
O => \z[30]_INST_0_i_74_n_0\
);
\z[30]_INST_0_i_75\: unisim.vcomponents.LUT6
generic map(
INIT => X"000002A2AAAA02A2"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_158_n_0\,
I2 => \_carry_i_10_n_0\,
I3 => \z[30]_INST_0_i_159_n_0\,
I4 => \_carry_i_1_n_0\,
I5 => \z[30]_INST_0_i_160_n_0\,
O => \z[30]_INST_0_i_75_n_0\
);
\z[30]_INST_0_i_76\: unisim.vcomponents.LUT6
generic map(
INIT => X"4C4C4C4040404C40"
)
port map (
I0 => \z[30]_INST_0_i_161_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_95_n_0\,
I3 => \z[30]_INST_0_i_162_n_0\,
I4 => \z[30]_INST_0_i_118_n_0\,
I5 => \z[30]_INST_0_i_163_n_0\,
O => \z[30]_INST_0_i_76_n_0\
);
\z[30]_INST_0_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \z[30]_INST_0_i_81_n_0\,
I1 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_77_n_0\
);
\z[30]_INST_0_i_78\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_164_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_155_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_154_n_0\,
O => \z[30]_INST_0_i_78_n_0\
);
\z[30]_INST_0_i_79\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \z[30]_INST_0_i_57_n_0\,
I1 => \z[30]_INST_0_i_67_n_0\,
O => \z[30]_INST_0_i_79_n_0\
);
\z[30]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"8A80FFFF8A808A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_40_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_41_n_0\,
I4 => \z[30]_INST_0_i_42_n_0\,
I5 => \z[30]_INST_0_i_43_n_0\,
O => sel0(0)
);
\z[30]_INST_0_i_80\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \z[30]_INST_0_i_82_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
O => \z[30]_INST_0_i_80_n_0\
);
\z[30]_INST_0_i_81\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_148_n_0\,
I1 => \z[30]_INST_0_i_149_n_0\,
I2 => \z[30]_INST_0_i_95_n_0\,
I3 => \z[30]_INST_0_i_147_n_0\,
I4 => \z[30]_INST_0_i_118_n_0\,
I5 => \z[30]_INST_0_i_165_n_0\,
O => \z[30]_INST_0_i_81_n_0\
);
\z[30]_INST_0_i_82\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFC05F5FCFC05050"
)
port map (
I0 => \z[30]_INST_0_i_163_n_0\,
I1 => \z[30]_INST_0_i_135_n_0\,
I2 => \z[30]_INST_0_i_95_n_0\,
I3 => \z[30]_INST_0_i_166_n_0\,
I4 => \z[30]_INST_0_i_118_n_0\,
I5 => \z[30]_INST_0_i_167_n_0\,
O => \z[30]_INST_0_i_82_n_0\
);
\z[30]_INST_0_i_83\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_158_n_0\,
I1 => \z[30]_INST_0_i_152_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_168_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_154_n_0\,
O => \z[30]_INST_0_i_83_n_0\
);
\z[30]_INST_0_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[30]_INST_0_i_41_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[30]_INST_0_i_44_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_45_n_0\,
O => \z[30]_INST_0_i_9_n_0\
);
\z[30]_INST_0_i_94\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF4F7"
)
port map (
I0 => \msb1__1\(1),
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \z[30]_INST_0_i_169_n_0\,
I3 => \msb1__1\(5),
I4 => \z[30]_INST_0_i_170_n_0\,
O => \z[30]_INST_0_i_94_n_0\
);
\z[30]_INST_0_i_95\: unisim.vcomponents.LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => \_carry_n_7\,
I1 => \_carry_i_10_n_0\,
I2 => L1,
O => \z[30]_INST_0_i_95_n_0\
);
\z[30]_INST_0_i_96\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF4F7"
)
port map (
I0 => \msb1__1\(3),
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \z[30]_INST_0_i_170_n_0\,
I3 => \msb1__1\(7),
I4 => \z[30]_INST_0_i_169_n_0\,
O => \z[30]_INST_0_i_96_n_0\
);
\z[30]_INST_0_i_97\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_171_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_172_n_0\,
O => \z[30]_INST_0_i_97_n_0\
);
\z[30]_INST_0_i_98\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_173_n_0\,
I1 => \z[30]_INST_0_i_174_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_175_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_176_n_0\,
O => \z[30]_INST_0_i_98_n_0\
);
\z[30]_INST_0_i_99\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_177_n_0\,
I1 => \z[30]_INST_0_i_178_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_179_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_180_n_0\,
O => \z[30]_INST_0_i_99_n_0\
);
\z[3]_INST_0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \z[3]_INST_0_i_1_n_0\,
CO(2) => \z[3]_INST_0_i_1_n_1\,
CO(1) => \z[3]_INST_0_i_1_n_2\,
CO(0) => \z[3]_INST_0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => sel0(0),
O(3 downto 0) => z_mantissa(3 downto 0),
S(3) => \z[3]_INST_0_i_2_n_0\,
S(2) => \z[3]_INST_0_i_3_n_0\,
S(1) => sel0(1),
S(0) => \z[3]_INST_0_i_5_n_0\
);
\z[3]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_37_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_38_n_0\,
I4 => \z[30]_INST_0_i_39_n_0\,
O => \z[3]_INST_0_i_2_n_0\
);
\z[3]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_44_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_37_n_0\,
I4 => \z[30]_INST_0_i_46_n_0\,
O => \z[3]_INST_0_i_3_n_0\
);
\z[3]_INST_0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_9_n_0\,
O => sel0(1)
);
\z[3]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAA9AA"
)
port map (
I0 => sel0(0),
I1 => \z[30]_INST_0_i_3_n_0\,
I2 => \z[3]_INST_0_i_6_n_0\,
I3 => \z[3]_INST_0_i_7_n_0\,
I4 => \z[3]_INST_0_i_8_n_0\,
I5 => \z[3]_INST_0_i_9_n_0\,
O => \z[3]_INST_0_i_5_n_0\
);
\z[3]_INST_0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => sel0(0),
I1 => sel0(2),
I2 => \z[7]_INST_0_i_8_n_0\,
I3 => \z[7]_INST_0_i_6_n_0\,
O => \z[3]_INST_0_i_6_n_0\
);
\z[3]_INST_0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => \z[7]_INST_0_i_9_n_0\,
I1 => sel0(10),
I2 => \z[30]_INST_0_i_11_n_0\,
I3 => \z[30]_INST_0_i_15_n_0\,
O => \z[3]_INST_0_i_7_n_0\
);
\z[3]_INST_0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => \z[15]_INST_0_i_7_n_0\,
I1 => \z[15]_INST_0_i_6_n_0\,
I2 => sel0(3),
I3 => \z[7]_INST_0_i_7_n_0\,
O => \z[3]_INST_0_i_8_n_0\
);
\z[3]_INST_0_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \z[30]_INST_0_i_9_n_0\,
I1 => \z[11]_INST_0_i_6_n_0\,
I2 => \z[11]_INST_0_i_7_n_0\,
I3 => \z[30]_INST_0_i_14_n_0\,
O => \z[3]_INST_0_i_9_n_0\
);
\z[7]_INST_0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \z[3]_INST_0_i_1_n_0\,
CO(3) => \z[7]_INST_0_i_1_n_0\,
CO(2) => \z[7]_INST_0_i_1_n_1\,
CO(1) => \z[7]_INST_0_i_1_n_2\,
CO(0) => \z[7]_INST_0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => z_mantissa(7 downto 4),
S(3 downto 0) => sel0(7 downto 4)
);
\z[7]_INST_0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_98_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_99_n_0\,
O => \z[7]_INST_0_i_10_n_0\
);
\z[7]_INST_0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_101_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_104_n_0\,
O => \z[7]_INST_0_i_11_n_0\
);
\z[7]_INST_0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_99_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_106_n_0\,
O => \z[7]_INST_0_i_12_n_0\
);
\z[7]_INST_0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[7]_INST_0_i_6_n_0\,
O => sel0(7)
);
\z[7]_INST_0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[7]_INST_0_i_7_n_0\,
O => sel0(6)
);
\z[7]_INST_0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[7]_INST_0_i_8_n_0\,
O => sel0(5)
);
\z[7]_INST_0_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[7]_INST_0_i_9_n_0\,
O => sel0(4)
);
\z[7]_INST_0_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[7]_INST_0_i_10_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[11]_INST_0_i_9_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_29_n_0\,
O => \z[7]_INST_0_i_6_n_0\
);
\z[7]_INST_0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[7]_INST_0_i_11_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[7]_INST_0_i_10_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_33_n_0\,
O => \z[7]_INST_0_i_7_n_0\
);
\z[7]_INST_0_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[7]_INST_0_i_12_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[7]_INST_0_i_11_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_35_n_0\,
O => \z[7]_INST_0_i_8_n_0\
);
\z[7]_INST_0_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[30]_INST_0_i_38_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[7]_INST_0_i_12_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_31_n_0\,
O => \z[7]_INST_0_i_9_n_0\
);
\z_exponent0__0_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \z_exponent0__0_carry_n_0\,
CO(2) => \z_exponent0__0_carry_n_1\,
CO(1) => \z_exponent0__0_carry_n_2\,
CO(0) => \z_exponent0__0_carry_n_3\,
CYINIT => '1',
DI(3) => \z_exponent0__0_carry_i_1_n_0\,
DI(2) => \z_exponent0__0_carry_i_2_n_0\,
DI(1) => \z_exponent0__0_carry_i_3_n_0\,
DI(0) => '1',
O(3 downto 0) => data0(3 downto 0),
S(3) => \z_exponent0__0_carry_i_4_n_0\,
S(2) => \z_exponent0__0_carry_i_5_n_0\,
S(1) => \z_exponent0__0_carry_i_6_n_0\,
S(0) => \z_exponent0__0_carry_i_7_n_0\
);
\z_exponent0__0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \z_exponent0__0_carry_n_0\,
CO(3) => \NLW_z_exponent0__0_carry__0_CO_UNCONNECTED\(3),
CO(2) => \z_exponent0__0_carry__0_n_1\,
CO(1) => \z_exponent0__0_carry__0_n_2\,
CO(0) => \z_exponent0__0_carry__0_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \z_exponent0__0_carry__0_i_1_n_0\,
DI(1) => \z_exponent0__0_carry__0_i_2_n_0\,
DI(0) => \z_exponent0__0_carry__0_i_3_n_0\,
O(3 downto 0) => data0(7 downto 4),
S(3) => \z_exponent0__0_carry__0_i_4_n_0\,
S(2) => \z_exponent0__0_carry__0_i_5_n_0\,
S(1) => \z_exponent0__0_carry__0_i_6_n_0\,
S(0) => \z_exponent0__0_carry__0_i_7_n_0\
);
\z_exponent0__0_carry__0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFA9A900"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => \z_exponent0__0_carry__0_i_8_n_0\,
I2 => L1_carry_i_12_n_0,
I3 => y(28),
I4 => x(28),
O => \z_exponent0__0_carry__0_i_1_n_0\
);
\z_exponent0__0_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F990"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => \z_exponent0__0_carry__0_i_8_n_0\,
I2 => y(27),
I3 => x(27),
O => \z_exponent0__0_carry__0_i_2_n_0\
);
\z_exponent0__0_carry__0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF1E1E00"
)
port map (
I0 => L1_carry_i_10_n_0,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_9_n_0,
I3 => y(26),
I4 => x(26),
O => \z_exponent0__0_carry__0_i_3_n_0\
);
\z_exponent0__0_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6999699969999996"
)
port map (
I0 => x(30),
I1 => y(30),
I2 => x(29),
I3 => y(29),
I4 => \msb1__1\(47),
I5 => \msb1__1\(46),
O => \z_exponent0__0_carry__0_i_4_n_0\
);
\z_exponent0__0_carry__0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"96969669"
)
port map (
I0 => \z_exponent0__0_carry__0_i_1_n_0\,
I1 => y(29),
I2 => x(29),
I3 => \msb1__1\(46),
I4 => \msb1__1\(47),
O => \z_exponent0__0_carry__0_i_5_n_0\
);
\z_exponent0__0_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"56A9A956A95656A9"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => \z_exponent0__0_carry__0_i_8_n_0\,
I2 => L1_carry_i_12_n_0,
I3 => \z_exponent0__0_carry__0_i_2_n_0\,
I4 => y(28),
I5 => x(28),
O => \z_exponent0__0_carry__0_i_6_n_0\
);
\z_exponent0__0_carry__0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => \z_exponent0__0_carry__0_i_8_n_0\,
I2 => \z_exponent0__0_carry__0_i_3_n_0\,
I3 => x(27),
I4 => y(27),
O => \z_exponent0__0_carry__0_i_7_n_0\
);
\z_exponent0__0_carry__0_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => L1_carry_i_10_n_0,
I2 => L1_carry_i_11_n_0,
O => \z_exponent0__0_carry__0_i_8_n_0\
);
\z_exponent0__0_carry_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F660"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_10_n_0,
I2 => y(25),
I3 => x(25),
O => \z_exponent0__0_carry_i_1_n_0\
);
\z_exponent0__0_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y(24),
I1 => x(24),
I2 => L1_carry_i_10_n_0,
O => \z_exponent0__0_carry_i_2_n_0\
);
\z_exponent0__0_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => x(23),
I1 => y(23),
I2 => \_carry_i_1_n_0\,
O => \z_exponent0__0_carry_i_3_n_0\
);
\z_exponent0__0_carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"E11E1EE11EE1E11E"
)
port map (
I0 => L1_carry_i_10_n_0,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_9_n_0,
I3 => \z_exponent0__0_carry_i_1_n_0\,
I4 => y(26),
I5 => x(26),
O => \z_exponent0__0_carry_i_4_n_0\
);
\z_exponent0__0_carry_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_10_n_0,
I2 => \z_exponent0__0_carry_i_2_n_0\,
I3 => y(25),
I4 => x(25),
O => \z_exponent0__0_carry_i_5_n_0\
);
\z_exponent0__0_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y(24),
I1 => L1_carry_i_10_n_0,
I2 => x(24),
I3 => \z_exponent0__0_carry_i_3_n_0\,
O => \z_exponent0__0_carry_i_6_n_0\
);
\z_exponent0__0_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => x(23),
I1 => y(23),
I2 => \_carry_i_1_n_0\,
O => \z_exponent0__0_carry_i_7_n_0\
);
z_exponent1_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => z_exponent1_carry_n_0,
CO(2) => z_exponent1_carry_n_1,
CO(1) => z_exponent1_carry_n_2,
CO(0) => z_exponent1_carry_n_3,
CYINIT => '0',
DI(3) => \z_exponent0__0_carry_i_1_n_0\,
DI(2) => \z_exponent0__0_carry_i_2_n_0\,
DI(1) => \z_exponent1_carry_i_1__0_n_0\,
DI(0) => x(23),
O(3 downto 0) => data1(3 downto 0),
S(3) => \z_exponent1_carry_i_2__0_n_0\,
S(2) => \z_exponent1_carry_i_3__0_n_0\,
S(1) => z_exponent1_carry_i_4_n_0,
S(0) => z_exponent1_carry_i_5_n_0
);
\z_exponent1_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => z_exponent1_carry_n_0,
CO(3) => \NLW_z_exponent1_carry__0_CO_UNCONNECTED\(3),
CO(2) => \z_exponent1_carry__0_n_1\,
CO(1) => \z_exponent1_carry__0_n_2\,
CO(0) => \z_exponent1_carry__0_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \z_exponent0__0_carry__0_i_1_n_0\,
DI(1) => \z_exponent0__0_carry__0_i_2_n_0\,
DI(0) => \z_exponent0__0_carry__0_i_3_n_0\,
O(3 downto 0) => data1(7 downto 4),
S(3) => z_exponent1_carry_i_1_n_0,
S(2) => z_exponent1_carry_i_2_n_0,
S(1) => z_exponent1_carry_i_3_n_0,
S(0) => \z_exponent1_carry_i_4__0_n_0\
);
z_exponent1_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"6999699969999996"
)
port map (
I0 => x(30),
I1 => y(30),
I2 => x(29),
I3 => y(29),
I4 => \msb1__1\(47),
I5 => \msb1__1\(46),
O => z_exponent1_carry_i_1_n_0
);
\z_exponent1_carry_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => y(23),
I1 => \_carry_i_1_n_0\,
O => \z_exponent1_carry_i_1__0_n_0\
);
z_exponent1_carry_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"96969669"
)
port map (
I0 => \z_exponent0__0_carry__0_i_1_n_0\,
I1 => y(29),
I2 => x(29),
I3 => \msb1__1\(46),
I4 => \msb1__1\(47),
O => z_exponent1_carry_i_2_n_0
);
\z_exponent1_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"E11E1EE11EE1E11E"
)
port map (
I0 => L1_carry_i_10_n_0,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_9_n_0,
I3 => \z_exponent0__0_carry_i_1_n_0\,
I4 => y(26),
I5 => x(26),
O => \z_exponent1_carry_i_2__0_n_0\
);
z_exponent1_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"56A9A956A95656A9"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => \z_exponent0__0_carry__0_i_8_n_0\,
I2 => L1_carry_i_12_n_0,
I3 => \z_exponent0__0_carry__0_i_2_n_0\,
I4 => y(28),
I5 => x(28),
O => z_exponent1_carry_i_3_n_0
);
\z_exponent1_carry_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_10_n_0,
I2 => y(25),
I3 => x(25),
I4 => \z_exponent0__0_carry_i_2_n_0\,
O => \z_exponent1_carry_i_3__0_n_0\
);
z_exponent1_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y(24),
I1 => x(24),
I2 => L1_carry_i_10_n_0,
I3 => \z_exponent1_carry_i_1__0_n_0\,
O => z_exponent1_carry_i_4_n_0
);
\z_exponent1_carry_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => \z_exponent0__0_carry__0_i_8_n_0\,
I2 => y(27),
I3 => x(27),
I4 => \z_exponent0__0_carry__0_i_3_n_0\,
O => \z_exponent1_carry_i_4__0_n_0\
);
z_exponent1_carry_i_5: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => y(23),
I1 => \_carry_i_1_n_0\,
I2 => x(23),
O => z_exponent1_carry_i_5_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity affine_block_ieee754_fp_multiplier_1_2 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of affine_block_ieee754_fp_multiplier_1_2 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of affine_block_ieee754_fp_multiplier_1_2 : entity is "affine_block_ieee754_fp_multiplier_0_0,ieee754_fp_multiplier,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of affine_block_ieee754_fp_multiplier_1_2 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of affine_block_ieee754_fp_multiplier_1_2 : entity is "ieee754_fp_multiplier,Vivado 2016.4";
end affine_block_ieee754_fp_multiplier_1_2;
architecture STRUCTURE of affine_block_ieee754_fp_multiplier_1_2 is
signal \z[30]_INST_0_i_23_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_24_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_25_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_26_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_27_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_28_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_84_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_85_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_86_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_87_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_88_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_89_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_90_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_91_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_92_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_93_n_0\ : STD_LOGIC;
signal z_mantissa : STD_LOGIC_VECTOR ( 22 downto 0 );
begin
U0: entity work.affine_block_ieee754_fp_multiplier_1_2_ieee754_fp_multiplier
port map (
x(30 downto 0) => x(30 downto 0),
y(30 downto 0) => y(30 downto 0),
\y_11__s_port_\ => \z[30]_INST_0_i_4_n_0\,
z(7 downto 0) => z(30 downto 23),
z_mantissa(22 downto 0) => z_mantissa(22 downto 0)
);
\z[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(0),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(0)
);
\z[10]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(10),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(10)
);
\z[11]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(11),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(11)
);
\z[12]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(12),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(12)
);
\z[13]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(13),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(13)
);
\z[14]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(14),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(14)
);
\z[15]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(15),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(15)
);
\z[16]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(16),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(16)
);
\z[17]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(17),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(17)
);
\z[18]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(18),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(18)
);
\z[19]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(19),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(19)
);
\z[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(1),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(1)
);
\z[20]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(20),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(20)
);
\z[21]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(21),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(21)
);
\z[22]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(22),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(22)
);
\z[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(2),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(2)
);
\z[30]_INST_0_i_23\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => x(29),
I1 => x(4),
I2 => x(11),
I3 => x(13),
I4 => \z[30]_INST_0_i_84_n_0\,
O => \z[30]_INST_0_i_23_n_0\
);
\z[30]_INST_0_i_24\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => x(25),
I1 => x(20),
I2 => x(15),
I3 => x(22),
I4 => \z[30]_INST_0_i_85_n_0\,
O => \z[30]_INST_0_i_24_n_0\
);
\z[30]_INST_0_i_25\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \z[30]_INST_0_i_86_n_0\,
I1 => \z[30]_INST_0_i_87_n_0\,
I2 => \z[30]_INST_0_i_88_n_0\,
I3 => x(24),
I4 => x(10),
I5 => x(2),
O => \z[30]_INST_0_i_25_n_0\
);
\z[30]_INST_0_i_26\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => y(30),
I1 => y(5),
I2 => y(0),
I3 => y(1),
I4 => \z[30]_INST_0_i_89_n_0\,
O => \z[30]_INST_0_i_26_n_0\
);
\z[30]_INST_0_i_27\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => y(29),
I1 => y(18),
I2 => y(2),
I3 => y(10),
I4 => \z[30]_INST_0_i_90_n_0\,
O => \z[30]_INST_0_i_27_n_0\
);
\z[30]_INST_0_i_28\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \z[30]_INST_0_i_91_n_0\,
I1 => \z[30]_INST_0_i_92_n_0\,
I2 => \z[30]_INST_0_i_93_n_0\,
I3 => y(12),
I4 => y(20),
I5 => y(4),
O => \z[30]_INST_0_i_28_n_0\
);
\z[30]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"101010FF10101010"
)
port map (
I0 => \z[30]_INST_0_i_23_n_0\,
I1 => \z[30]_INST_0_i_24_n_0\,
I2 => \z[30]_INST_0_i_25_n_0\,
I3 => \z[30]_INST_0_i_26_n_0\,
I4 => \z[30]_INST_0_i_27_n_0\,
I5 => \z[30]_INST_0_i_28_n_0\,
O => \z[30]_INST_0_i_4_n_0\
);
\z[30]_INST_0_i_84\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => x(9),
I1 => x(3),
I2 => x(17),
I3 => x(7),
O => \z[30]_INST_0_i_84_n_0\
);
\z[30]_INST_0_i_85\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => x(18),
I1 => x(30),
I2 => x(21),
I3 => x(6),
O => \z[30]_INST_0_i_85_n_0\
);
\z[30]_INST_0_i_86\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => x(14),
I1 => x(12),
I2 => x(8),
I3 => x(27),
O => \z[30]_INST_0_i_86_n_0\
);
\z[30]_INST_0_i_87\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => x(28),
I1 => x(23),
I2 => x(19),
I3 => x(1),
O => \z[30]_INST_0_i_87_n_0\
);
\z[30]_INST_0_i_88\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => x(0),
I1 => x(26),
I2 => x(16),
I3 => x(5),
O => \z[30]_INST_0_i_88_n_0\
);
\z[30]_INST_0_i_89\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => y(14),
I1 => y(8),
I2 => y(24),
I3 => y(27),
O => \z[30]_INST_0_i_89_n_0\
);
\z[30]_INST_0_i_90\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => y(7),
I1 => y(26),
I2 => y(17),
I3 => y(6),
O => \z[30]_INST_0_i_90_n_0\
);
\z[30]_INST_0_i_91\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => y(21),
I1 => y(15),
I2 => y(22),
I3 => y(23),
O => \z[30]_INST_0_i_91_n_0\
);
\z[30]_INST_0_i_92\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => y(19),
I1 => y(28),
I2 => y(9),
I3 => y(3),
O => \z[30]_INST_0_i_92_n_0\
);
\z[30]_INST_0_i_93\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => y(16),
I1 => y(25),
I2 => y(13),
I3 => y(11),
O => \z[30]_INST_0_i_93_n_0\
);
\z[31]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y(31),
I1 => x(31),
O => z(31)
);
\z[3]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(3),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(3)
);
\z[4]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(4),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(4)
);
\z[5]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(5),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(5)
);
\z[6]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(6),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(6)
);
\z[7]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(7),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(7)
);
\z[8]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(8),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(8)
);
\z[9]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(9),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(9)
);
end STRUCTURE;
| mit | fc2c907348ba280885f5e98cdebbef19 | 0.486968 | 2.258208 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_rgb888_to_g8_1_0/synth/system_rgb888_to_g8_1_0.vhd | 2 | 3,886 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:rgb888_to_g8:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_rgb888_to_g8_1_0 IS
PORT (
clk : IN STD_LOGIC;
rgb888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
g8 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END system_rgb888_to_g8_1_0;
ARCHITECTURE system_rgb888_to_g8_1_0_arch OF system_rgb888_to_g8_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rgb888_to_g8_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT rgb888_to_g8 IS
PORT (
clk : IN STD_LOGIC;
rgb888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
g8 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT rgb888_to_g8;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_rgb888_to_g8_1_0_arch: ARCHITECTURE IS "rgb888_to_g8,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_rgb888_to_g8_1_0_arch : ARCHITECTURE IS "system_rgb888_to_g8_1_0,rgb888_to_g8,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_rgb888_to_g8_1_0_arch: ARCHITECTURE IS "system_rgb888_to_g8_1_0,rgb888_to_g8,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=rgb888_to_g8,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : rgb888_to_g8
PORT MAP (
clk => clk,
rgb888 => rgb888,
g8 => g8
);
END system_rgb888_to_g8_1_0_arch;
| mit | 677198cbc642d84764756bb2bb2ec304 | 0.738549 | 3.621622 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/hdl/system_wrapper.vhd | 1 | 2,444 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Mon Jun 05 08:32:55 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system_wrapper.bd
--Design : system_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_wrapper is
port (
clk_100 : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
enable_nm : in STD_LOGIC;
hdmi_clk : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hsync : in STD_LOGIC;
pclk : in STD_LOGIC;
ready : out STD_LOGIC;
reset : in STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
vsync : in STD_LOGIC;
xclk : out STD_LOGIC
);
end system_wrapper;
architecture STRUCTURE of system_wrapper is
component system is
port (
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC;
ready : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
xclk : out STD_LOGIC;
reset : in STD_LOGIC;
pclk : in STD_LOGIC;
clk_100 : in STD_LOGIC;
enable_nm : in STD_LOGIC
);
end component system;
begin
system_i: component system
port map (
clk_100 => clk_100,
data(7 downto 0) => data(7 downto 0),
enable_nm => enable_nm,
hdmi_clk => hdmi_clk,
hdmi_d(15 downto 0) => hdmi_d(15 downto 0),
hdmi_de => hdmi_de,
hdmi_hsync => hdmi_hsync,
hdmi_scl => hdmi_scl,
hdmi_sda => hdmi_sda,
hdmi_vsync => hdmi_vsync,
hsync => hsync,
pclk => pclk,
ready => ready,
reset => reset,
sioc => sioc,
siod => siod,
vsync => vsync,
xclk => xclk
);
end STRUCTURE;
| mit | 4ba97342a25b59f14251d4d407e14c4e | 0.565057 | 3.54717 | false | false | false | false |
loa-org/loa-hdl | modules/motor_control/tb/comparator_module_tb.vhd | 2 | 2,906 | -------------------------------------------------------------------------------
-- Title : Testbench for design "comparator_module"
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.motor_control_pkg.all;
-------------------------------------------------------------------------------
entity comparator_module_tb is
end comparator_module_tb;
-------------------------------------------------------------------------------
architecture tb of comparator_module_tb is
-- component generics
constant BASE_ADDRESS : positive := 16#0100#;
constant CHANNELS : positive := 3;
-- component ports
signal value : comparator_values_type(CHANNELS-1 downto 0) := (others => (others => '0'));
signal overflow : std_logic_vector(CHANNELS-1 downto 0);
signal bus_o : busdevice_out_type;
signal bus_i : busdevice_in_type :=
(addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
signal clk : std_logic := '0';
begin
-- component instantiation
DUT : comparator_module
generic map (
BASE_ADDRESS => BASE_ADDRESS,
CHANNELS => CHANNELS)
port map (
value_p => value,
overflow_p => overflow,
bus_o => bus_o,
bus_i => bus_i,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
bus_waveform : process
begin
wait for 100 ns;
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0100", bus_i.addr'length)));
bus_i.data <= x"00f0";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait for 30 US;
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0100", bus_i.addr'length)));
bus_i.data <= x"000f";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait for 100 US;
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0100", bus_i.addr'length)));
bus_i.data <= x"010f";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
end process;
-- Generate different values
process
begin
wait for 20 US;
value(0) <= "0000010000";
wait for 30 US;
value(0) <= "0000000000";
wait for 50 US;
value(0) <= "0000010000";
wait for 100 US;
value(0) <= "0100000000";
end process;
end tb;
| bsd-3-clause | e47f7997a7895da0eeb8a0c955654e1b | 0.46903 | 4.047354 | false | false | false | false |
loa-org/loa-hdl | modules/signalprocessing/tb/real_tb.vhd | 2 | 1,411 | -------------------------------------------------------------------------------
-- Title : Testbench for integer-to-real conversion
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Finding a bug in gtkwave in displaying real values.
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity real_tb is
end entity real_tb;
architecture tb of real_tb is
signal clk : std_logic := '0';
signal s0 : std_logic_vector(15 downto 0) := (others => '0');
signal s1 : signed(15 downto 0) := (others => '0');
signal s2 : integer := 0;
signal s3 : real := 0.0;
begin -- architecture tb
-- clock gen
clk <= not clk after 10 ns;
process (clk) is
variable cnt : integer := 0;
begin -- process
if rising_edge(clk) then -- rising clock edge
s0 <= std_logic_vector(to_unsigned(cnt, 16));
cnt := cnt + 1;
end if;
end process;
s1 <= signed(s0);
s2 <= to_integer(s1);
s3 <= real(s2);
end architecture tb;
| bsd-3-clause | 1f64fbeca1fd0132bcb97c3436f8d0c7 | 0.428774 | 4.395639 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_sync_ref_1_0/system_vga_sync_ref_1_0_sim_netlist.vhdl | 1 | 70,090 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue May 30 22:29:13 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_sync_ref_1_0/system_vga_sync_ref_1_0_sim_netlist.vhdl
-- Design : system_vga_sync_ref_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_ref_1_0_vga_sync_ref is
port (
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
start : out STD_LOGIC;
active : out STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
vsync : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_sync_ref_1_0_vga_sync_ref : entity is "vga_sync_ref";
end system_vga_sync_ref_1_0_vga_sync_ref;
architecture STRUCTURE of system_vga_sync_ref_1_0_vga_sync_ref is
signal \^active\ : STD_LOGIC;
signal active_i_1_n_0 : STD_LOGIC;
signal active_i_2_n_0 : STD_LOGIC;
signal counter : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \counter[12]_i_3_n_0\ : STD_LOGIC;
signal \counter[12]_i_4_n_0\ : STD_LOGIC;
signal \counter[12]_i_5_n_0\ : STD_LOGIC;
signal \counter[12]_i_6_n_0\ : STD_LOGIC;
signal \counter[16]_i_3_n_0\ : STD_LOGIC;
signal \counter[16]_i_4_n_0\ : STD_LOGIC;
signal \counter[16]_i_5_n_0\ : STD_LOGIC;
signal \counter[16]_i_6_n_0\ : STD_LOGIC;
signal \counter[20]_i_3_n_0\ : STD_LOGIC;
signal \counter[20]_i_4_n_0\ : STD_LOGIC;
signal \counter[20]_i_5_n_0\ : STD_LOGIC;
signal \counter[20]_i_6_n_0\ : STD_LOGIC;
signal \counter[24]_i_3_n_0\ : STD_LOGIC;
signal \counter[24]_i_4_n_0\ : STD_LOGIC;
signal \counter[24]_i_5_n_0\ : STD_LOGIC;
signal \counter[24]_i_6_n_0\ : STD_LOGIC;
signal \counter[28]_i_3_n_0\ : STD_LOGIC;
signal \counter[28]_i_4_n_0\ : STD_LOGIC;
signal \counter[28]_i_5_n_0\ : STD_LOGIC;
signal \counter[28]_i_6_n_0\ : STD_LOGIC;
signal \counter[31]_i_10_n_0\ : STD_LOGIC;
signal \counter[31]_i_11_n_0\ : STD_LOGIC;
signal \counter[31]_i_12_n_0\ : STD_LOGIC;
signal \counter[31]_i_13_n_0\ : STD_LOGIC;
signal \counter[31]_i_14_n_0\ : STD_LOGIC;
signal \counter[31]_i_15_n_0\ : STD_LOGIC;
signal \counter[31]_i_16_n_0\ : STD_LOGIC;
signal \counter[31]_i_17_n_0\ : STD_LOGIC;
signal \counter[31]_i_18_n_0\ : STD_LOGIC;
signal \counter[31]_i_19_n_0\ : STD_LOGIC;
signal \counter[31]_i_1_n_0\ : STD_LOGIC;
signal \counter[31]_i_2_n_0\ : STD_LOGIC;
signal \counter[31]_i_4_n_0\ : STD_LOGIC;
signal \counter[31]_i_6_n_0\ : STD_LOGIC;
signal \counter[31]_i_7_n_0\ : STD_LOGIC;
signal \counter[31]_i_8_n_0\ : STD_LOGIC;
signal \counter[31]_i_9_n_0\ : STD_LOGIC;
signal \counter[4]_i_3_n_0\ : STD_LOGIC;
signal \counter[4]_i_4_n_0\ : STD_LOGIC;
signal \counter[4]_i_5_n_0\ : STD_LOGIC;
signal \counter[4]_i_6_n_0\ : STD_LOGIC;
signal \counter[8]_i_3_n_0\ : STD_LOGIC;
signal \counter[8]_i_4_n_0\ : STD_LOGIC;
signal \counter[8]_i_5_n_0\ : STD_LOGIC;
signal \counter[8]_i_6_n_0\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_2\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_3\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_5\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_6\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_7\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_7\ : STD_LOGIC;
signal \h_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_2_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_5_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_6_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_7_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_8_n_0\ : STD_LOGIC;
signal \h_count_reg_reg__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_2_in : STD_LOGIC_VECTOR ( 31 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^start\ : STD_LOGIC;
signal start_i_1_n_0 : STD_LOGIC;
signal start_i_2_n_0 : STD_LOGIC;
signal start_i_3_n_0 : STD_LOGIC;
signal start_i_4_n_0 : STD_LOGIC;
signal start_i_5_n_0 : STD_LOGIC;
signal start_i_6_n_0 : STD_LOGIC;
signal \state[0]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_10_n_0\ : STD_LOGIC;
signal \state[1]_i_11_n_0\ : STD_LOGIC;
signal \state[1]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
signal \state[1]_i_4_n_0\ : STD_LOGIC;
signal \state[1]_i_5_n_0\ : STD_LOGIC;
signal \state[1]_i_6_n_0\ : STD_LOGIC;
signal \state[1]_i_7_n_0\ : STD_LOGIC;
signal \state[1]_i_8_n_0\ : STD_LOGIC;
signal \state[1]_i_9_n_0\ : STD_LOGIC;
signal \state_reg_n_0_[0]\ : STD_LOGIC;
signal \state_reg_n_0_[1]\ : STD_LOGIC;
signal \v_count_reg[9]_i_10_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_3_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_5_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_6_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_7_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_8_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_9_n_0\ : STD_LOGIC;
signal \v_count_reg_reg__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \NLW_counter_reg[31]_i_5_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_counter_reg[31]_i_5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \counter[0]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \counter[31]_i_15\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \counter[31]_i_18\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \h_count_reg[0]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \h_count_reg[1]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \h_count_reg[2]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \h_count_reg[3]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \h_count_reg[4]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[7]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[8]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_7\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_8\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of start_i_3 : label is "soft_lutpair10";
attribute SOFT_HLUTNM of start_i_4 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of start_i_6 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \state[1]_i_10\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \v_count_reg[0]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \v_count_reg[1]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \v_count_reg[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[3]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[4]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \v_count_reg[7]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \v_count_reg[8]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_5\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_6\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_7\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_8\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_9\ : label is "soft_lutpair8";
begin
active <= \^active\;
start <= \^start\;
active_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000002FFFE"
)
port map (
I0 => \^active\,
I1 => active_i_2_n_0,
I2 => \v_count_reg[9]_i_1_n_0\,
I3 => start_i_2_n_0,
I4 => \state_reg_n_0_[0]\,
I5 => \counter[31]_i_1_n_0\,
O => active_i_1_n_0
);
active_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => counter(25),
I2 => counter(26),
I3 => counter(24),
I4 => \v_count_reg[9]_i_5_n_0\,
I5 => \counter[31]_i_7_n_0\,
O => active_i_2_n_0
);
active_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => active_i_1_n_0,
Q => \^active\,
R => '0'
);
\counter[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => counter(0),
O => p_2_in(0)
);
\counter[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[12]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(10)
);
\counter[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[12]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(11)
);
\counter[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[12]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(12)
);
\counter[12]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(12),
O => \counter[12]_i_3_n_0\
);
\counter[12]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(11),
O => \counter[12]_i_4_n_0\
);
\counter[12]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(10),
O => \counter[12]_i_5_n_0\
);
\counter[12]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(9),
O => \counter[12]_i_6_n_0\
);
\counter[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[16]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(13)
);
\counter[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[16]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(14)
);
\counter[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[16]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(15)
);
\counter[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[16]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(16)
);
\counter[16]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(16),
O => \counter[16]_i_3_n_0\
);
\counter[16]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(15),
O => \counter[16]_i_4_n_0\
);
\counter[16]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(14),
O => \counter[16]_i_5_n_0\
);
\counter[16]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(13),
O => \counter[16]_i_6_n_0\
);
\counter[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[20]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(17)
);
\counter[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[20]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(18)
);
\counter[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[20]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(19)
);
\counter[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[4]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(1)
);
\counter[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[20]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(20)
);
\counter[20]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(20),
O => \counter[20]_i_3_n_0\
);
\counter[20]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(19),
O => \counter[20]_i_4_n_0\
);
\counter[20]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(18),
O => \counter[20]_i_5_n_0\
);
\counter[20]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(17),
O => \counter[20]_i_6_n_0\
);
\counter[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[24]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(21)
);
\counter[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[24]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(22)
);
\counter[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[24]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(23)
);
\counter[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[24]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(24)
);
\counter[24]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(24),
O => \counter[24]_i_3_n_0\
);
\counter[24]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(23),
O => \counter[24]_i_4_n_0\
);
\counter[24]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(22),
O => \counter[24]_i_5_n_0\
);
\counter[24]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(21),
O => \counter[24]_i_6_n_0\
);
\counter[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[28]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(25)
);
\counter[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[28]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(26)
);
\counter[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[28]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(27)
);
\counter[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[28]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(28)
);
\counter[28]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(28),
O => \counter[28]_i_3_n_0\
);
\counter[28]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(27),
O => \counter[28]_i_4_n_0\
);
\counter[28]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(26),
O => \counter[28]_i_5_n_0\
);
\counter[28]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(25),
O => \counter[28]_i_6_n_0\
);
\counter[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[31]_i_5_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(29)
);
\counter[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[4]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(2)
);
\counter[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[31]_i_5_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(30)
);
\counter[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => vsync,
I1 => rst,
O => \counter[31]_i_1_n_0\
);
\counter[31]_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => counter(24),
I1 => counter(26),
I2 => counter(25),
O => \counter[31]_i_10_n_0\
);
\counter[31]_i_11\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(31),
O => \counter[31]_i_11_n_0\
);
\counter[31]_i_12\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(30),
O => \counter[31]_i_12_n_0\
);
\counter[31]_i_13\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(29),
O => \counter[31]_i_13_n_0\
);
\counter[31]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => counter(17),
I1 => counter(16),
I2 => counter(19),
I3 => counter(18),
I4 => \v_count_reg[9]_i_10_n_0\,
I5 => \counter[31]_i_10_n_0\,
O => \counter[31]_i_14_n_0\
);
\counter[31]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => counter(31),
I1 => counter(30),
I2 => counter(29),
O => \counter[31]_i_15_n_0\
);
\counter[31]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF7FFFFFFFFFFF"
)
port map (
I0 => counter(2),
I1 => counter(1),
I2 => counter(0),
I3 => counter(3),
I4 => \state_reg_n_0_[1]\,
I5 => \state_reg_n_0_[0]\,
O => \counter[31]_i_16_n_0\
);
\counter[31]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"DFFF"
)
port map (
I0 => counter(4),
I1 => counter(8),
I2 => counter(6),
I3 => counter(5),
O => \counter[31]_i_17_n_0\
);
\counter[31]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => counter(10),
I1 => counter(11),
O => \counter[31]_i_18_n_0\
);
\counter[31]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(15),
I1 => counter(14),
I2 => counter(13),
I3 => counter(12),
O => \counter[31]_i_19_n_0\
);
\counter[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \state_reg_n_0_[0]\,
I1 => \state_reg_n_0_[1]\,
O => \counter[31]_i_2_n_0\
);
\counter[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"4440404044404440"
)
port map (
I0 => \counter[31]_i_4_n_0\,
I1 => \counter_reg[31]_i_5_n_5\,
I2 => \counter[31]_i_6_n_0\,
I3 => \counter[31]_i_7_n_0\,
I4 => \counter[31]_i_8_n_0\,
I5 => \counter[31]_i_9_n_0\,
O => p_2_in(31)
);
\counter[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => start_i_5_n_0,
I2 => start_i_4_n_0,
I3 => \v_count_reg[9]_i_5_n_0\,
I4 => start_i_3_n_0,
I5 => \counter[31]_i_10_n_0\,
O => \counter[31]_i_4_n_0\
);
\counter[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFEFEFEFF"
)
port map (
I0 => \counter[31]_i_14_n_0\,
I1 => counter(28),
I2 => counter(27),
I3 => \state_reg_n_0_[1]\,
I4 => \state_reg_n_0_[0]\,
I5 => \counter[31]_i_15_n_0\,
O => \counter[31]_i_6_n_0\
);
\counter[31]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFEFF"
)
port map (
I0 => \counter[31]_i_16_n_0\,
I1 => \counter[31]_i_17_n_0\,
I2 => counter(7),
I3 => counter(9),
I4 => \counter[31]_i_18_n_0\,
I5 => \counter[31]_i_19_n_0\,
O => \counter[31]_i_7_n_0\
);
\counter[31]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFBFFF"
)
port map (
I0 => \h_count_reg[9]_i_5_n_0\,
I1 => counter(3),
I2 => counter(0),
I3 => counter(7),
I4 => counter(6),
I5 => \h_count_reg[9]_i_2_n_0\,
O => \counter[31]_i_8_n_0\
);
\counter[31]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \counter[31]_i_19_n_0\,
I1 => counter(10),
I2 => counter(11),
I3 => counter(8),
I4 => counter(9),
O => \counter[31]_i_9_n_0\
);
\counter[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[4]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(3)
);
\counter[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[4]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(4)
);
\counter[4]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(4),
O => \counter[4]_i_3_n_0\
);
\counter[4]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(3),
O => \counter[4]_i_4_n_0\
);
\counter[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(2),
O => \counter[4]_i_5_n_0\
);
\counter[4]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(1),
O => \counter[4]_i_6_n_0\
);
\counter[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[8]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(5)
);
\counter[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[8]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(6)
);
\counter[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[8]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(7)
);
\counter[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[8]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(8)
);
\counter[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(8),
O => \counter[8]_i_3_n_0\
);
\counter[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(7),
O => \counter[8]_i_4_n_0\
);
\counter[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(6),
O => \counter[8]_i_5_n_0\
);
\counter[8]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(5),
O => \counter[8]_i_6_n_0\
);
\counter[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[12]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(9)
);
\counter_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(0),
Q => counter(0),
R => \counter[31]_i_1_n_0\
);
\counter_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(10),
Q => counter(10),
R => \counter[31]_i_1_n_0\
);
\counter_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(11),
Q => counter(11),
R => \counter[31]_i_1_n_0\
);
\counter_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(12),
Q => counter(12),
R => \counter[31]_i_1_n_0\
);
\counter_reg[12]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[8]_i_2_n_0\,
CO(3) => \counter_reg[12]_i_2_n_0\,
CO(2) => \counter_reg[12]_i_2_n_1\,
CO(1) => \counter_reg[12]_i_2_n_2\,
CO(0) => \counter_reg[12]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[12]_i_2_n_4\,
O(2) => \counter_reg[12]_i_2_n_5\,
O(1) => \counter_reg[12]_i_2_n_6\,
O(0) => \counter_reg[12]_i_2_n_7\,
S(3) => \counter[12]_i_3_n_0\,
S(2) => \counter[12]_i_4_n_0\,
S(1) => \counter[12]_i_5_n_0\,
S(0) => \counter[12]_i_6_n_0\
);
\counter_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(13),
Q => counter(13),
R => \counter[31]_i_1_n_0\
);
\counter_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(14),
Q => counter(14),
R => \counter[31]_i_1_n_0\
);
\counter_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(15),
Q => counter(15),
R => \counter[31]_i_1_n_0\
);
\counter_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(16),
Q => counter(16),
R => \counter[31]_i_1_n_0\
);
\counter_reg[16]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[12]_i_2_n_0\,
CO(3) => \counter_reg[16]_i_2_n_0\,
CO(2) => \counter_reg[16]_i_2_n_1\,
CO(1) => \counter_reg[16]_i_2_n_2\,
CO(0) => \counter_reg[16]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[16]_i_2_n_4\,
O(2) => \counter_reg[16]_i_2_n_5\,
O(1) => \counter_reg[16]_i_2_n_6\,
O(0) => \counter_reg[16]_i_2_n_7\,
S(3) => \counter[16]_i_3_n_0\,
S(2) => \counter[16]_i_4_n_0\,
S(1) => \counter[16]_i_5_n_0\,
S(0) => \counter[16]_i_6_n_0\
);
\counter_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(17),
Q => counter(17),
R => \counter[31]_i_1_n_0\
);
\counter_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(18),
Q => counter(18),
R => \counter[31]_i_1_n_0\
);
\counter_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(19),
Q => counter(19),
R => \counter[31]_i_1_n_0\
);
\counter_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(1),
Q => counter(1),
R => \counter[31]_i_1_n_0\
);
\counter_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(20),
Q => counter(20),
R => \counter[31]_i_1_n_0\
);
\counter_reg[20]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[16]_i_2_n_0\,
CO(3) => \counter_reg[20]_i_2_n_0\,
CO(2) => \counter_reg[20]_i_2_n_1\,
CO(1) => \counter_reg[20]_i_2_n_2\,
CO(0) => \counter_reg[20]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[20]_i_2_n_4\,
O(2) => \counter_reg[20]_i_2_n_5\,
O(1) => \counter_reg[20]_i_2_n_6\,
O(0) => \counter_reg[20]_i_2_n_7\,
S(3) => \counter[20]_i_3_n_0\,
S(2) => \counter[20]_i_4_n_0\,
S(1) => \counter[20]_i_5_n_0\,
S(0) => \counter[20]_i_6_n_0\
);
\counter_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(21),
Q => counter(21),
R => \counter[31]_i_1_n_0\
);
\counter_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(22),
Q => counter(22),
R => \counter[31]_i_1_n_0\
);
\counter_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(23),
Q => counter(23),
R => \counter[31]_i_1_n_0\
);
\counter_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(24),
Q => counter(24),
R => \counter[31]_i_1_n_0\
);
\counter_reg[24]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[20]_i_2_n_0\,
CO(3) => \counter_reg[24]_i_2_n_0\,
CO(2) => \counter_reg[24]_i_2_n_1\,
CO(1) => \counter_reg[24]_i_2_n_2\,
CO(0) => \counter_reg[24]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[24]_i_2_n_4\,
O(2) => \counter_reg[24]_i_2_n_5\,
O(1) => \counter_reg[24]_i_2_n_6\,
O(0) => \counter_reg[24]_i_2_n_7\,
S(3) => \counter[24]_i_3_n_0\,
S(2) => \counter[24]_i_4_n_0\,
S(1) => \counter[24]_i_5_n_0\,
S(0) => \counter[24]_i_6_n_0\
);
\counter_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(25),
Q => counter(25),
R => \counter[31]_i_1_n_0\
);
\counter_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(26),
Q => counter(26),
R => \counter[31]_i_1_n_0\
);
\counter_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(27),
Q => counter(27),
R => \counter[31]_i_1_n_0\
);
\counter_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(28),
Q => counter(28),
R => \counter[31]_i_1_n_0\
);
\counter_reg[28]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[24]_i_2_n_0\,
CO(3) => \counter_reg[28]_i_2_n_0\,
CO(2) => \counter_reg[28]_i_2_n_1\,
CO(1) => \counter_reg[28]_i_2_n_2\,
CO(0) => \counter_reg[28]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[28]_i_2_n_4\,
O(2) => \counter_reg[28]_i_2_n_5\,
O(1) => \counter_reg[28]_i_2_n_6\,
O(0) => \counter_reg[28]_i_2_n_7\,
S(3) => \counter[28]_i_3_n_0\,
S(2) => \counter[28]_i_4_n_0\,
S(1) => \counter[28]_i_5_n_0\,
S(0) => \counter[28]_i_6_n_0\
);
\counter_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(29),
Q => counter(29),
R => \counter[31]_i_1_n_0\
);
\counter_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(2),
Q => counter(2),
R => \counter[31]_i_1_n_0\
);
\counter_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(30),
Q => counter(30),
R => \counter[31]_i_1_n_0\
);
\counter_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(31),
Q => counter(31),
R => \counter[31]_i_1_n_0\
);
\counter_reg[31]_i_5\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[28]_i_2_n_0\,
CO(3 downto 2) => \NLW_counter_reg[31]_i_5_CO_UNCONNECTED\(3 downto 2),
CO(1) => \counter_reg[31]_i_5_n_2\,
CO(0) => \counter_reg[31]_i_5_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_counter_reg[31]_i_5_O_UNCONNECTED\(3),
O(2) => \counter_reg[31]_i_5_n_5\,
O(1) => \counter_reg[31]_i_5_n_6\,
O(0) => \counter_reg[31]_i_5_n_7\,
S(3) => '0',
S(2) => \counter[31]_i_11_n_0\,
S(1) => \counter[31]_i_12_n_0\,
S(0) => \counter[31]_i_13_n_0\
);
\counter_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(3),
Q => counter(3),
R => \counter[31]_i_1_n_0\
);
\counter_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(4),
Q => counter(4),
R => \counter[31]_i_1_n_0\
);
\counter_reg[4]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \counter_reg[4]_i_2_n_0\,
CO(2) => \counter_reg[4]_i_2_n_1\,
CO(1) => \counter_reg[4]_i_2_n_2\,
CO(0) => \counter_reg[4]_i_2_n_3\,
CYINIT => counter(0),
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[4]_i_2_n_4\,
O(2) => \counter_reg[4]_i_2_n_5\,
O(1) => \counter_reg[4]_i_2_n_6\,
O(0) => \counter_reg[4]_i_2_n_7\,
S(3) => \counter[4]_i_3_n_0\,
S(2) => \counter[4]_i_4_n_0\,
S(1) => \counter[4]_i_5_n_0\,
S(0) => \counter[4]_i_6_n_0\
);
\counter_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(5),
Q => counter(5),
R => \counter[31]_i_1_n_0\
);
\counter_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(6),
Q => counter(6),
R => \counter[31]_i_1_n_0\
);
\counter_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(7),
Q => counter(7),
R => \counter[31]_i_1_n_0\
);
\counter_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(8),
Q => counter(8),
R => \counter[31]_i_1_n_0\
);
\counter_reg[8]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[4]_i_2_n_0\,
CO(3) => \counter_reg[8]_i_2_n_0\,
CO(2) => \counter_reg[8]_i_2_n_1\,
CO(1) => \counter_reg[8]_i_2_n_2\,
CO(0) => \counter_reg[8]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[8]_i_2_n_4\,
O(2) => \counter_reg[8]_i_2_n_5\,
O(1) => \counter_reg[8]_i_2_n_6\,
O(0) => \counter_reg[8]_i_2_n_7\,
S(3) => \counter[8]_i_3_n_0\,
S(2) => \counter[8]_i_4_n_0\,
S(1) => \counter[8]_i_5_n_0\,
S(0) => \counter[8]_i_6_n_0\
);
\counter_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(9),
Q => counter(9),
R => \counter[31]_i_1_n_0\
);
\h_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \h_count_reg_reg__0\(0),
O => \plusOp__0\(0)
);
\h_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \h_count_reg_reg__0\(0),
I1 => \h_count_reg_reg__0\(1),
O => \plusOp__0\(1)
);
\h_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \h_count_reg_reg__0\(2),
I1 => \h_count_reg_reg__0\(0),
I2 => \h_count_reg_reg__0\(1),
O => \plusOp__0\(2)
);
\h_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \h_count_reg_reg__0\(3),
I1 => \h_count_reg_reg__0\(1),
I2 => \h_count_reg_reg__0\(0),
I3 => \h_count_reg_reg__0\(2),
O => \plusOp__0\(3)
);
\h_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \h_count_reg_reg__0\(2),
I1 => \h_count_reg_reg__0\(0),
I2 => \h_count_reg_reg__0\(1),
I3 => \h_count_reg_reg__0\(3),
I4 => \h_count_reg_reg__0\(4),
O => \plusOp__0\(4)
);
\h_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \h_count_reg_reg__0\(5),
I1 => \h_count_reg_reg__0\(2),
I2 => \h_count_reg_reg__0\(0),
I3 => \h_count_reg_reg__0\(1),
I4 => \h_count_reg_reg__0\(3),
I5 => \h_count_reg_reg__0\(4),
O => \plusOp__0\(5)
);
\h_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \h_count_reg_reg__0\(6),
I1 => \h_count_reg[9]_i_7_n_0\,
I2 => \h_count_reg_reg__0\(5),
O => \plusOp__0\(6)
);
\h_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \h_count_reg_reg__0\(7),
I1 => \h_count_reg_reg__0\(5),
I2 => \h_count_reg[9]_i_7_n_0\,
I3 => \h_count_reg_reg__0\(6),
O => \plusOp__0\(7)
);
\h_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \h_count_reg_reg__0\(8),
I1 => \h_count_reg_reg__0\(6),
I2 => \h_count_reg[9]_i_7_n_0\,
I3 => \h_count_reg_reg__0\(5),
I4 => \h_count_reg_reg__0\(7),
O => \plusOp__0\(8)
);
\h_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDDDFDDDDDDDDD"
)
port map (
I0 => rst,
I1 => vsync,
I2 => \counter[31]_i_9_n_0\,
I3 => \h_count_reg[9]_i_4_n_0\,
I4 => \h_count_reg[9]_i_5_n_0\,
I5 => \h_count_reg[9]_i_6_n_0\,
O => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg[9]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \state_reg_n_0_[0]\,
I1 => \state_reg_n_0_[1]\,
O => \h_count_reg[9]_i_2_n_0\
);
\h_count_reg[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \h_count_reg_reg__0\(9),
I1 => \h_count_reg_reg__0\(7),
I2 => \h_count_reg_reg__0\(5),
I3 => \h_count_reg[9]_i_7_n_0\,
I4 => \h_count_reg_reg__0\(6),
I5 => \h_count_reg_reg__0\(8),
O => \plusOp__0\(9)
);
\h_count_reg[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FDFFFFFFFFFFFFFF"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => \state_reg_n_0_[0]\,
I2 => counter(6),
I3 => counter(7),
I4 => counter(0),
I5 => counter(3),
O => \h_count_reg[9]_i_4_n_0\
);
\h_count_reg[9]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => counter(1),
I1 => counter(2),
I2 => counter(4),
I3 => counter(5),
O => \h_count_reg[9]_i_5_n_0\
);
\h_count_reg[9]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \v_count_reg[9]_i_5_n_0\,
I1 => counter(24),
I2 => counter(26),
I3 => counter(25),
I4 => \v_count_reg[9]_i_10_n_0\,
I5 => \h_count_reg[9]_i_8_n_0\,
O => \h_count_reg[9]_i_6_n_0\
);
\h_count_reg[9]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => \h_count_reg_reg__0\(4),
I1 => \h_count_reg_reg__0\(3),
I2 => \h_count_reg_reg__0\(1),
I3 => \h_count_reg_reg__0\(0),
I4 => \h_count_reg_reg__0\(2),
O => \h_count_reg[9]_i_7_n_0\
);
\h_count_reg[9]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(17),
I1 => counter(16),
I2 => counter(19),
I3 => counter(18),
O => \h_count_reg[9]_i_8_n_0\
);
\h_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(0),
Q => \h_count_reg_reg__0\(0),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(1),
Q => \h_count_reg_reg__0\(1),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(2),
Q => \h_count_reg_reg__0\(2),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(3),
Q => \h_count_reg_reg__0\(3),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(4),
Q => \h_count_reg_reg__0\(4),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(5),
Q => \h_count_reg_reg__0\(5),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(6),
Q => \h_count_reg_reg__0\(6),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(7),
Q => \h_count_reg_reg__0\(7),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(8),
Q => \h_count_reg_reg__0\(8),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(9),
Q => \h_count_reg_reg__0\(9),
R => \h_count_reg[9]_i_1_n_0\
);
start_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000220E0000"
)
port map (
I0 => \^start\,
I1 => start_i_2_n_0,
I2 => \state_reg_n_0_[0]\,
I3 => \state_reg_n_0_[1]\,
I4 => rst,
I5 => vsync,
O => start_i_1_n_0
);
start_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \h_count_reg[9]_i_6_n_0\,
I1 => start_i_3_n_0,
I2 => start_i_4_n_0,
I3 => start_i_5_n_0,
O => start_i_2_n_0
);
start_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(15),
I1 => counter(14),
I2 => counter(4),
I3 => counter(6),
O => start_i_3_n_0
);
start_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => counter(3),
I1 => counter(1),
I2 => counter(2),
I3 => counter(11),
I4 => start_i_6_n_0,
O => start_i_4_n_0
);
start_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF7"
)
port map (
I0 => counter(5),
I1 => counter(13),
I2 => counter(8),
I3 => counter(9),
I4 => \state_reg_n_0_[1]\,
I5 => \state_reg_n_0_[0]\,
O => start_i_5_n_0
);
start_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => counter(7),
I1 => counter(0),
I2 => counter(10),
I3 => counter(12),
O => start_i_6_n_0
);
start_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => start_i_1_n_0,
Q => \^start\,
R => '0'
);
\state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FE560000"
)
port map (
I0 => \state_reg_n_0_[0]\,
I1 => \state[1]_i_2_n_0\,
I2 => start_i_2_n_0,
I3 => \state_reg_n_0_[1]\,
I4 => rst,
I5 => vsync,
O => \state[0]_i_1_n_0\
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000E6E2"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => \state[1]_i_2_n_0\,
I2 => \state[1]_i_3_n_0\,
I3 => \state_reg_n_0_[0]\,
I4 => \state[1]_i_4_n_0\,
O => \state[1]_i_1_n_0\
);
\state[1]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => counter(2),
I1 => counter(1),
O => \state[1]_i_10_n_0\
);
\state[1]_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => counter(27),
I1 => counter(28),
O => \state[1]_i_11_n_0\
);
\state[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444F44444444"
)
port map (
I0 => \counter[31]_i_7_n_0\,
I1 => \h_count_reg[9]_i_6_n_0\,
I2 => \state[1]_i_5_n_0\,
I3 => \state[1]_i_6_n_0\,
I4 => \v_count_reg[9]_i_4_n_0\,
I5 => \state[1]_i_7_n_0\,
O => \state[1]_i_2_n_0\
);
\state[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => \v_count_reg[9]_i_7_n_0\,
I1 => \v_count_reg_reg__0\(9),
I2 => \v_count_reg_reg__0\(6),
I3 => \v_count_reg_reg__0\(5),
I4 => \v_count_reg_reg__0\(7),
I5 => \v_count_reg_reg__0\(8),
O => \state[1]_i_3_n_0\
);
\state[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAABAAAAAAAA"
)
port map (
I0 => \counter[31]_i_1_n_0\,
I1 => \state[1]_i_8_n_0\,
I2 => \state[1]_i_9_n_0\,
I3 => \state[1]_i_6_n_0\,
I4 => start_i_4_n_0,
I5 => \state[1]_i_7_n_0\,
O => \state[1]_i_4_n_0\
);
\state[1]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFB"
)
port map (
I0 => \state[1]_i_10_n_0\,
I1 => counter(7),
I2 => counter(5),
I3 => \h_count_reg[9]_i_2_n_0\,
I4 => \state[1]_i_9_n_0\,
I5 => \v_count_reg[9]_i_9_n_0\,
O => \state[1]_i_5_n_0\
);
\state[1]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => counter(25),
I1 => counter(26),
I2 => \state[1]_i_11_n_0\,
I3 => counter(16),
I4 => counter(31),
I5 => \v_count_reg[9]_i_8_n_0\,
O => \state[1]_i_6_n_0\
);
\state[1]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => counter(18),
I1 => counter(17),
I2 => counter(19),
I3 => \v_count_reg[9]_i_10_n_0\,
I4 => counter(24),
O => \state[1]_i_7_n_0\
);
\state[1]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF7"
)
port map (
I0 => counter(13),
I1 => counter(5),
I2 => \state_reg_n_0_[0]\,
I3 => \state_reg_n_0_[1]\,
I4 => counter(9),
I5 => counter(14),
O => \state[1]_i_8_n_0\
);
\state[1]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(30),
I1 => counter(29),
I2 => counter(4),
I3 => counter(8),
O => \state[1]_i_9_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \state[0]_i_1_n_0\,
Q => \state_reg_n_0_[0]\,
R => '0'
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \state[1]_i_1_n_0\,
Q => \state_reg_n_0_[1]\,
R => '0'
);
\v_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \v_count_reg_reg__0\(0),
O => plusOp(0)
);
\v_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \v_count_reg_reg__0\(0),
I1 => \v_count_reg_reg__0\(1),
O => plusOp(1)
);
\v_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \v_count_reg_reg__0\(2),
I1 => \v_count_reg_reg__0\(0),
I2 => \v_count_reg_reg__0\(1),
O => plusOp(2)
);
\v_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \v_count_reg_reg__0\(3),
I1 => \v_count_reg_reg__0\(1),
I2 => \v_count_reg_reg__0\(0),
I3 => \v_count_reg_reg__0\(2),
O => plusOp(3)
);
\v_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \v_count_reg_reg__0\(4),
I1 => \v_count_reg_reg__0\(2),
I2 => \v_count_reg_reg__0\(0),
I3 => \v_count_reg_reg__0\(1),
I4 => \v_count_reg_reg__0\(3),
O => plusOp(4)
);
\v_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \v_count_reg_reg__0\(5),
I1 => \v_count_reg_reg__0\(3),
I2 => \v_count_reg_reg__0\(1),
I3 => \v_count_reg_reg__0\(0),
I4 => \v_count_reg_reg__0\(2),
I5 => \v_count_reg_reg__0\(4),
O => plusOp(5)
);
\v_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \v_count_reg_reg__0\(6),
I1 => \v_count_reg[9]_i_7_n_0\,
I2 => \v_count_reg_reg__0\(5),
O => plusOp(6)
);
\v_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \v_count_reg_reg__0\(7),
I1 => \v_count_reg_reg__0\(5),
I2 => \v_count_reg[9]_i_7_n_0\,
I3 => \v_count_reg_reg__0\(6),
O => plusOp(7)
);
\v_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A6AAAAAA"
)
port map (
I0 => \v_count_reg_reg__0\(8),
I1 => \v_count_reg_reg__0\(6),
I2 => \v_count_reg[9]_i_7_n_0\,
I3 => \v_count_reg_reg__0\(5),
I4 => \v_count_reg_reg__0\(7),
O => plusOp(8)
);
\v_count_reg[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \v_count_reg[9]_i_3_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \v_count_reg[9]_i_5_n_0\,
I3 => \v_count_reg[9]_i_6_n_0\,
I4 => \state[1]_i_3_n_0\,
O => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg[9]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(21),
I1 => counter(20),
I2 => counter(23),
I3 => counter(22),
O => \v_count_reg[9]_i_10_n_0\
);
\v_count_reg[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA6AAAAAAAAAAA"
)
port map (
I0 => \v_count_reg_reg__0\(9),
I1 => \v_count_reg_reg__0\(7),
I2 => \v_count_reg_reg__0\(8),
I3 => \v_count_reg_reg__0\(6),
I4 => \v_count_reg[9]_i_7_n_0\,
I5 => \v_count_reg_reg__0\(5),
O => plusOp(9)
);
\v_count_reg[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFB"
)
port map (
I0 => \v_count_reg[9]_i_8_n_0\,
I1 => counter(7),
I2 => counter(8),
I3 => \h_count_reg[9]_i_5_n_0\,
I4 => \v_count_reg[9]_i_9_n_0\,
I5 => \counter[31]_i_10_n_0\,
O => \v_count_reg[9]_i_3_n_0\
);
\v_count_reg[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => counter(11),
I1 => counter(10),
I2 => counter(9),
I3 => counter(14),
I4 => counter(12),
I5 => counter(13),
O => \v_count_reg[9]_i_4_n_0\
);
\v_count_reg[9]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => counter(28),
I1 => counter(27),
I2 => counter(29),
I3 => counter(30),
I4 => counter(31),
O => \v_count_reg[9]_i_5_n_0\
);
\v_count_reg[9]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \v_count_reg[9]_i_10_n_0\,
I1 => counter(18),
I2 => counter(19),
I3 => counter(16),
I4 => counter(17),
O => \v_count_reg[9]_i_6_n_0\
);
\v_count_reg[9]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \v_count_reg_reg__0\(3),
I1 => \v_count_reg_reg__0\(1),
I2 => \v_count_reg_reg__0\(0),
I3 => \v_count_reg_reg__0\(2),
I4 => \v_count_reg_reg__0\(4),
O => \v_count_reg[9]_i_7_n_0\
);
\v_count_reg[9]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => counter(6),
I1 => counter(15),
O => \v_count_reg[9]_i_8_n_0\
);
\v_count_reg[9]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF7F"
)
port map (
I0 => counter(3),
I1 => counter(0),
I2 => \state_reg_n_0_[1]\,
I3 => \state_reg_n_0_[0]\,
O => \v_count_reg[9]_i_9_n_0\
);
\v_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(0),
Q => \v_count_reg_reg__0\(0),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(1),
Q => \v_count_reg_reg__0\(1),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(2),
Q => \v_count_reg_reg__0\(2),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(3),
Q => \v_count_reg_reg__0\(3),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(4),
Q => \v_count_reg_reg__0\(4),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(5),
Q => \v_count_reg_reg__0\(5),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(6),
Q => \v_count_reg_reg__0\(6),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(7),
Q => \v_count_reg_reg__0\(7),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(8),
Q => \v_count_reg_reg__0\(8),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(9),
Q => \v_count_reg_reg__0\(9),
R => \counter[31]_i_1_n_0\
);
\xaddr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(0),
Q => xaddr(0),
R => '0'
);
\xaddr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(1),
Q => xaddr(1),
R => '0'
);
\xaddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(2),
Q => xaddr(2),
R => '0'
);
\xaddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(3),
Q => xaddr(3),
R => '0'
);
\xaddr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(4),
Q => xaddr(4),
R => '0'
);
\xaddr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(5),
Q => xaddr(5),
R => '0'
);
\xaddr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(6),
Q => xaddr(6),
R => '0'
);
\xaddr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(7),
Q => xaddr(7),
R => '0'
);
\xaddr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(8),
Q => xaddr(8),
R => '0'
);
\xaddr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(9),
Q => xaddr(9),
R => '0'
);
\yaddr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(0),
Q => yaddr(0),
R => '0'
);
\yaddr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(1),
Q => yaddr(1),
R => '0'
);
\yaddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(2),
Q => yaddr(2),
R => '0'
);
\yaddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(3),
Q => yaddr(3),
R => '0'
);
\yaddr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(4),
Q => yaddr(4),
R => '0'
);
\yaddr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(5),
Q => yaddr(5),
R => '0'
);
\yaddr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(6),
Q => yaddr(6),
R => '0'
);
\yaddr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(7),
Q => yaddr(7),
R => '0'
);
\yaddr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(8),
Q => yaddr(8),
R => '0'
);
\yaddr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(9),
Q => yaddr(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_ref_1_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
start : out STD_LOGIC;
active : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_sync_ref_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_sync_ref_1_0 : entity is "system_vga_sync_ref_1_0,vga_sync_ref,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_sync_ref_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_sync_ref_1_0 : entity is "vga_sync_ref,Vivado 2016.4";
end system_vga_sync_ref_1_0;
architecture STRUCTURE of system_vga_sync_ref_1_0 is
begin
U0: entity work.system_vga_sync_ref_1_0_vga_sync_ref
port map (
active => active,
clk => clk,
rst => rst,
start => start,
vsync => vsync,
xaddr(9 downto 0) => xaddr(9 downto 0),
yaddr(9 downto 0) => yaddr(9 downto 0)
);
end STRUCTURE;
| mit | 30d6da251d16f43bdd0e186bb5964d78 | 0.486104 | 2.524583 | false | false | false | false |
olofk/libstorage | rtl/vhdl/suv/fifo_generic.vhd | 1 | 2,596 | --
-- FIFO. Part of libstorage
--
-- Copyright (C) 2015 Olof Kindgren <[email protected]>
--
-- Permission to use, copy, modify, and/or distribute this software for any
-- purpose with or without fee is hereby granted, provided that the above
-- copyright notice and this permission notice appear in all copies.
--
-- THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-- WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-- ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-- WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-- ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-- OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
--
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
library libstorage_1;
use libstorage_1.libstorage_pkg.all;
entity fifo_generic is
generic (
DEPTH : positive);
port (
clk : in std_ulogic;
rst : in std_ulogic;
rd_en_i : in std_ulogic;
rd_data_o : out std_ulogic_vector;
full_o : out std_ulogic;
wr_en_i : in std_ulogic;
wr_data_i : in std_ulogic_vector;
empty_o : out std_ulogic);
end entity fifo_generic;
architecture rtl of fifo_generic is
constant ADDR_WIDTH : natural := clog2(DEPTH);
signal wr_addr : unsigned(ADDR_WIDTH downto 0) := (others => '0');
signal rd_addr : unsigned(ADDR_WIDTH downto 0) := (others => '0');
signal full_or_empty : std_ulogic;
signal empty_not_full : std_ulogic;
begin
full_o <= full_or_empty and not empty_not_full;
empty_o <= full_or_empty and empty_not_full;
empty_not_full <= (wr_addr(ADDR_WIDTH) ?= rd_addr(ADDR_WIDTH));
full_or_empty <= (wr_addr(ADDR_WIDTH-1 downto 0) ?= rd_addr(ADDR_WIDTH-1 downto 0));
p_main: process (clk) is
begin
if rising_edge(clk) then
if wr_en_i then
wr_addr <= wr_addr + 1;
end if;
if rd_en_i then
rd_addr <= rd_addr + 1;
end if;
if rst then
wr_addr <= (others => '0');
rd_addr <= (others => '0');
end if;
end if;
end process p_main;
dpram: entity libstorage_1.dpram_generic
generic map (
DEPTH => DEPTH)
port map (
clk => clk,
rd_en_i => rd_en_i,
rd_addr_i => rd_addr(ADDR_WIDTH-1 downto 0),
rd_data_o => rd_data_o,
wr_en_i => wr_en_i,
wr_addr_i => wr_addr(ADDR_WIDTH-1 downto 0),
wr_data_i => wr_data_i);
end architecture rtl;
| isc | 4d17757610f098e93fdbc93789c5780e | 0.642142 | 3.277778 | false | false | false | false |
sbourdeauducq/dspunit | rtl/dsp_cmdregs.vhd | 2 | 10,901 | -- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.dspalu_pac.all;
use work.dspunit_pac.all;
-------------------------------------------------------------------------------
entity dsp_cmdregs is
port (
clk : in std_logic;
clk_cpu : in std_logic;
reset : in std_logic;
op_done : in std_logic;
addr_cmdreg : in std_logic_vector((cmdreg_addr_width - 1) downto 0);
data_in_cmdreg : in std_logic_vector((cmdreg_data_width - 1) downto 0);
wr_en_cmdreg : in std_logic;
data_out_cmdreg : out std_logic_vector((cmdreg_data_width - 1) downto 0);
offset_0 : out unsigned((cmdreg_width - 1) downto 0);
offset_1 : out unsigned((cmdreg_width - 1) downto 0);
offset_2 : out unsigned((cmdreg_width - 1) downto 0);
length0 : out std_logic_vector((cmdreg_data_width - 1) downto 0);
length1 : out std_logic_vector((cmdreg_data_width - 1) downto 0);
length2 : out std_logic_vector((cmdreg_data_width - 1) downto 0);
opflag_select : out std_logic_vector((opflag_width - 1) downto 0);
opcode_select : out std_logic_vector((opcode_width - 1) downto 0);
irq : out std_logic;
debug : out std_logic_vector(15 downto 0)
);
end dsp_cmdregs;
--=----------------------------------------------------------------------------
architecture archi_dsp_cmdregs of dsp_cmdregs is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
constant c_refresh_cmdreg_length : integer := 10;
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
component dsp_cmdpipe
port (
reset : in std_logic;
clk : in std_logic;
cmd_out : out t_dsp_cmdregs;
read : in std_logic;
empty : out std_logic;
cmd_in : in t_dsp_cmdregs;
write : in std_logic;
full : out std_logic
);
end component;
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_dsp_cmdregs : t_dsp_cmdregs;
signal s_dsp_cmdregs_buf : t_dsp_cmdregs;
signal s_dsp_cmdpipe_out : t_dsp_cmdregs;
signal s_dsp_bus : t_dsp_bus;
signal s_dsp_bus_conv_circ : t_dsp_bus;
signal s_op_conv_circ_en : std_logic;
signal s_opflag_select_inreg : std_logic_vector((opflag_width - 1) downto 0);
signal s_opcode_select_inreg : std_logic_vector((opcode_width - 1) downto 0);
signal s_op_run_resync : std_logic;
signal s_op_run_sync : std_logic;
signal s_op_done_sync : std_logic;
signal s_op_done_resync : std_logic;
signal s_lut_out : std_logic_vector((lut_out_width - 1) downto 0);
signal s_load_pipe : std_logic;
signal s_status_reg : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_read : std_logic;
signal s_empty : std_logic;
signal s_write : std_logic;
signal s_full : std_logic;
signal s_run_flag : std_logic;
signal s_pipe_loaded : std_logic;
signal s_op_run : std_logic;
signal s_op_done_irq : std_logic;
signal s_empty_irq : std_logic;
signal s_current_sr : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_empty_reg : std_logic;
signal s_op_done_reg : std_logic;
signal s_empty_ie : std_logic;
signal s_op_done_ie : std_logic;
begin -- archs_dsp_cmdregs
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
dsp_cmdpipe_1 : dsp_cmdpipe
port map (
reset => reset,
clk => clk_cpu,
cmd_out => s_dsp_cmdpipe_out,
read => s_read,
empty => s_empty,
cmd_in => s_dsp_cmdregs_buf,
write => s_write,
full => s_full);
--=---------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Register bank accessible from controler
-------------------------------------------------------------------------------
p_cmdreg_buf : process (clk_cpu, reset)
begin -- process p_cmdreg_buf
if reset = '0' then
s_dsp_cmdregs_buf <= dsp_cmdregs_init;
elsif rising_edge(clk_cpu) then -- rising clock edge
if(wr_en_cmdreg = '1') then
s_dsp_cmdregs_buf(conv_integer(addr_cmdreg)) <= data_in_cmdreg;
else
s_dsp_cmdregs_buf(DSPADDR_SR) <= s_status_reg;
end if;
data_out_cmdreg <= s_dsp_cmdregs_buf(conv_integer(addr_cmdreg));
end if;
end process p_cmdreg_buf;
-------------------------------------------------------------------------------
-- Bits of status register (readable from cpu)
-------------------------------------------------------------------------------
s_status_reg(DSP_SRBIT_LOADED) <= s_full;
s_status_reg(DSP_SRBIT_DONE) <= s_op_done_resync;
s_status_reg(DSP_SRBIT_RUN) <= s_run_flag and (not s_load_pipe);
s_run_flag <= s_dsp_cmdregs_buf(DSPADDR_SR)(DSP_SRBIT_RUN);
s_status_reg(DSP_SRBIT_DONE_IE) <= s_dsp_cmdregs_buf(DSPADDR_SR)(DSP_SRBIT_DONE_IE);
s_status_reg(DSP_SRBIT_EMPTY_IE) <= s_dsp_cmdregs_buf(DSPADDR_SR)(DSP_SRBIT_EMPTY_IE);
s_status_reg(DSP_SRBIT_DONE_IF) <= s_op_done_irq;
s_status_reg(DSP_SRBIT_EMPTY_IF) <= s_empty_irq;
s_status_reg(cmdreg_width - 1 downto DSP_SRBIT_UNUSED) <= (others => '0');
s_op_done_irq <= '1' when op_done = '1' and s_op_done_reg = '0' else s_dsp_cmdregs_buf(DSPADDR_SR)(DSP_SRBIT_DONE_IF);
s_empty_irq <= '1' when s_empty = '1' and s_empty_reg = '0' else s_dsp_cmdregs_buf(DSPADDR_SR)(DSP_SRBIT_EMPTY_IF);
s_empty_ie <= s_status_reg(DSP_SRBIT_EMPTY_IE);
s_op_done_ie <= s_current_sr(DSP_SRBIT_DONE_IE);
irq <= (s_empty and s_empty_ie) or (op_done and s_op_done_ie);
p_irq : process (clk_cpu)
begin -- process p_irq
if rising_edge(clk_cpu) then -- rising clock edge
s_op_done_reg <= op_done;
s_empty_reg <= s_empty;
end if;
end process p_irq;
-------------------------------------------------------------------------------
-- Control injection of datas in pipe
-------------------------------------------------------------------------------
p_ctrl_pipe : process (clk_cpu)
begin -- process p_cmdreg_buf
if rising_edge(clk_cpu) then -- rising clock edge
if s_load_pipe = '1' then
s_write <= '1';
s_pipe_loaded <= '1';
elsif s_run_flag = '0' then
s_pipe_loaded <= '0';
s_write <= '0';
else
s_write <= '0';
end if;
end if;
end process p_ctrl_pipe;
s_load_pipe <= s_run_flag and (not s_pipe_loaded) and (not s_full);
-------------------------------------------------------------------------------
-- Control the pipe output
-------------------------------------------------------------------------------
p_pipe_out : process (clk_cpu, reset)
begin -- process p_pipe_out
if reset = '0' then
s_op_run <= '0';
elsif rising_edge(clk_cpu) then -- rising clock edge
if s_op_done_resync = '1' then
s_op_run <= '0';
s_read <= '0';
elsif s_op_run = '0' and s_empty = '0' then
s_read <= '1';
s_op_run <= '1';
s_dsp_cmdregs <= s_dsp_cmdpipe_out;
else
s_read <= '0';
end if;
s_op_done_sync <= op_done;
s_op_done_resync <= s_op_done_sync;
end if;
end process p_pipe_out;
-------------------------------------------------------------------------------
-- Synchronization of command signals to the dspunit clock
-------------------------------------------------------------------------------
p_synccmd : process (clk)
begin -- process p_synccmd
if rising_edge(clk) then -- rising clock edge
s_op_run_sync <= s_op_run;
s_op_run_resync <= s_op_run_sync;
-- cmdregs can be considered as stable when s_op_run_resync='1'
if s_op_run_resync = '1' then
s_opcode_select_inreg <= s_dsp_cmdregs(DSPADDR_OPCODE)((opcode_width - 1) downto 0);
s_opflag_select_inreg <= s_dsp_cmdregs(DSPADDR_OPCODE)((opflag_width + opcode_width - 1) downto (opcode_width));
else
s_opcode_select_inreg <= (others => '0');
s_opflag_select_inreg <= (others => '0');
end if;
opcode_select <= s_opcode_select_inreg;
opflag_select <= s_opflag_select_inreg;
offset_0 <= unsigned(s_dsp_cmdregs(DSPADDR_STARTADDR0));
offset_1 <= unsigned(s_dsp_cmdregs(DSPADDR_STARTADDR1));
offset_2 <= unsigned(s_dsp_cmdregs(DSPADDR_STARTADDR2));
length0 <= s_dsp_cmdregs(DSPADDR_LENGTH0);
length1 <= s_dsp_cmdregs(DSPADDR_LENGTH1);
length2 <= s_dsp_cmdregs(DSPADDR_LENGTH2);
end if;
end process p_synccmd;
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
debug <= s_dsp_cmdregs(DSPADDR_SR);
s_current_sr <= s_dsp_cmdregs(DSPADDR_SR);
end archi_dsp_cmdregs;
-------------------------------------------------------------------------------
| gpl-3.0 | 8468f5b77b481ba15c69a2094d67451b | 0.481515 | 3.806215 | false | false | false | false |
loa-org/loa-hdl | modules/encoder/tb/hall_sensor_decoder_tb.vhd | 2 | 4,424 | -------------------------------------------------------------------------------
-- Title : Testbench for design "hall_sensor_decoder"
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.hall_sensor_decoder_pkg.all;
use work.motor_control_pkg.all;
-------------------------------------------------------------------------------
entity hall_sensor_decoder_tb is
end hall_sensor_decoder_tb;
-------------------------------------------------------------------------------
architecture tb of hall_sensor_decoder_tb is
type input_type is record
a : std_logic;
b : std_logic;
c : std_logic;
end record;
type expect_type is record
step : std_logic;
dir : std_logic;
error : std_logic;
end record;
type stimulus_type is record
input : input_type;
expect : expect_type;
end record;
type stimuli_type is array (natural range <>) of stimulus_type;
constant stimuli : stimuli_type := (
-- A B C step dir error
(input => ('0', '0', '1'), expect => ('0', '-', '0')),
(input => ('1', '0', '1'), expect => ('1', '-', '0')),
(input => ('1', '0', '0'), expect => ('1', '1', '0')),
(input => ('1', '0', '0'), expect => ('0', '-', '0')),
(input => ('1', '1', '0'), expect => ('1', '1', '0')),
(input => ('0', '1', '0'), expect => ('1', '1', '0')),
(input => ('0', '1', '1'), expect => ('1', '1', '0')),
(input => ('0', '0', '1'), expect => ('1', '1', '0')),
(input => ('1', '0', '1'), expect => ('1', '1', '0')),
(input => ('1', '0', '1'), expect => ('0', '-', '0')),
(input => ('0', '0', '1'), expect => ('1', '0', '0')),
(input => ('0', '1', '1'), expect => ('1', '0', '0')),
(input => ('0', '1', '0'), expect => ('1', '0', '0')),
(input => ('1', '1', '0'), expect => ('1', '0', '0')),
(input => ('1', '1', '0'), expect => ('0', '-', '0')),
(input => ('0', '1', '0'), expect => ('1', '1', '0')),
(input => ('1', '1', '0'), expect => ('1', '0', '0')),
(input => ('0', '1', '0'), expect => ('1', '1', '0')),
(input => ('0', '1', '1'), expect => ('1', '1', '0')),
(input => ('0', '0', '1'), expect => ('1', '1', '0')),
(input => ('1', '0', '1'), expect => ('1', '1', '0')),
(input => ('1', '1', '1'), expect => ('0', '-', '1')),
(input => ('0', '1', '1'), expect => ('0', '-', '0')),
(input => ('0', '1', '0'), expect => ('1', '0', '0')),
(input => ('1', '1', '0'), expect => ('1', '0', '0')),
(input => ('0', '0', '0'), expect => ('0', '-', '1')),
(input => ('1', '0', '1'), expect => ('0', '0', '0'))
);
-- component ports
signal abc : hall_sensor_type := (a => '0', b => '0', c => '0');
signal step : std_logic;
signal dir : std_logic;
signal error : std_logic;
-- clock
signal clk : std_logic := '1';
begin
-- component instantiation
DUT : hall_sensor_decoder
port map (
hall_sensor_p => abc,
step_p => step,
dir_p => dir,
error_p => error,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
wave : process
begin
wait for 20 ns;
for i in stimuli'left to (stimuli'right + 2) loop
wait until rising_edge(clk);
if i <= stimuli'right then
abc.a <= stimuli(i).input.a;
abc.b <= stimuli(i).input.b;
abc.c <= stimuli(i).input.c;
else
abc.a <= '0';
abc.b <= '0';
abc.c <= '1';
end if;
if i > (stimuli'left + 2) then
-- values are active at the output after two clock cycles
assert (step = stimuli(i-2).expect.step) report "Wrong value for 'step'" severity note;
if not (stimuli(i-2).expect.dir = '-') then
assert (dir = stimuli(i-2).expect.dir) report "Wrong value for 'dir'" severity note;
end if;
assert (error = stimuli(i-2).expect.error) report "Wrong value for 'error'" severity note;
end if;
end loop; -- i
end process wave;
end tb;
| bsd-3-clause | 3df3e51b9646da7e10f9689fcc609bec | 0.403255 | 3.387443 | false | false | false | false |
loa-org/loa-hdl | modules/encoder/hdl/encoder_module.vhd | 2 | 3,216 | -------------------------------------------------------------------------------
-- Title : Encoder Module
-- Project : Loa
-------------------------------------------------------------------------------
-- Platform : Spartan 3
-------------------------------------------------------------------------------
-- Description: Connectes a quadrature decoder with a 16-bit counter to
-- the internal bus system.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.encoder_module_pkg.all;
use work.quadrature_decoder_pkg.all;
use work.up_down_counter_pkg.all;
-------------------------------------------------------------------------------
entity encoder_module is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#
);
port (
encoder_p : in encoder_type;
index_p : in std_logic; -- index can be used to reset the
-- counter, set to '0' if not used
load_p : in std_logic; -- Save the current encoder value in a
-- buffer register
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
clk : in std_logic
);
end encoder_module;
-------------------------------------------------------------------------------
architecture behavioral of encoder_module is
type encoder_module_type is record
counter : std_logic_vector(15 downto 0);
data_out : std_logic_vector(15 downto 0);
end record;
signal r, rin : encoder_module_type := (data_out => (others => '0'),
counter => (others => '0'));
signal step : std_logic := '0';
signal up_down : std_logic := '0'; -- Direction for the counter ('1' = up, '0' = down)
signal decode_error : std_logic; -- Decoding Error (A and B lines changes at the same time), currently not used
signal counter : std_logic_vector(15 downto 0);
begin
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
comb_proc : process(bus_i, counter, load_p, r)
variable v : encoder_module_type;
begin
v := r;
v.data_out := (others => '0');
-- Load counter into own buffer
if load_p = '1' then
v.counter := counter;
end if;
-- Check Bus Address
if bus_i.addr = std_logic_vector(to_unsigned(BASE_ADDRESS, 15)) then
if bus_i.we = '1' then
-- TODO
elsif bus_i.re = '1' then
v.data_out := r.counter;
end if;
end if;
rin <= v;
end process comb_proc;
bus_o.data <= r.data_out;
decoder : quadrature_decoder
port map (
encoder_p => encoder_p,
step_p => step,
dir_p => up_down,
error_p => decode_error,
clk => clk);
up_down_counter_1 : up_down_counter
generic map (
WIDTH => 16)
port map (
clk_en_p => step,
up_down_p => up_down,
value_p => counter,
reset => '0',
clk => clk);
end behavioral;
| bsd-3-clause | 4d5cf210d5cb968d345a53295f920193 | 0.471082 | 4.102041 | false | false | false | false |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/niosII_system.vhd | 1 | 877,260 | -- niosII_system.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:30
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosII_system is
port (
clk_clk : in std_logic := '0'; -- clk.clk
reset_reset_n : in std_logic := '0'; -- reset.reset_n
green_leds_external_connection_export : out std_logic_vector(7 downto 0); -- green_leds_external_connection.export
switches_external_connection_export : in std_logic_vector(7 downto 0) := (others => '0'); -- switches_external_connection.export
sdram_0_wire_addr : out std_logic_vector(11 downto 0); -- sdram_0_wire.addr
sdram_0_wire_ba : out std_logic_vector(1 downto 0); -- .ba
sdram_0_wire_cas_n : out std_logic; -- .cas_n
sdram_0_wire_cke : out std_logic; -- .cke
sdram_0_wire_cs_n : out std_logic; -- .cs_n
sdram_0_wire_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
sdram_0_wire_dqm : out std_logic_vector(1 downto 0); -- .dqm
sdram_0_wire_ras_n : out std_logic; -- .ras_n
sdram_0_wire_we_n : out std_logic; -- .we_n
sram_0_external_interface_DQ : inout std_logic_vector(15 downto 0) := (others => '0'); -- sram_0_external_interface.DQ
sram_0_external_interface_ADDR : out std_logic_vector(17 downto 0); -- .ADDR
sram_0_external_interface_LB_N : out std_logic; -- .LB_N
sram_0_external_interface_UB_N : out std_logic; -- .UB_N
sram_0_external_interface_CE_N : out std_logic; -- .CE_N
sram_0_external_interface_OE_N : out std_logic; -- .OE_N
sram_0_external_interface_WE_N : out std_logic; -- .WE_N
altpll_0_c0_clk : out std_logic; -- altpll_0_c0.clk
usb_0_external_interface_INT1 : in std_logic := '0'; -- usb_0_external_interface.INT1
usb_0_external_interface_DATA : inout std_logic_vector(15 downto 0) := (others => '0'); -- .DATA
usb_0_external_interface_RST_N : out std_logic; -- .RST_N
usb_0_external_interface_ADDR : out std_logic_vector(1 downto 0); -- .ADDR
usb_0_external_interface_CS_N : out std_logic; -- .CS_N
usb_0_external_interface_RD_N : out std_logic; -- .RD_N
usb_0_external_interface_WR_N : out std_logic; -- .WR_N
usb_0_external_interface_INT0 : in std_logic := '0'; -- .INT0
rs232_0_external_interface_RXD : in std_logic := '0'; -- rs232_0_external_interface.RXD
rs232_0_external_interface_TXD : out std_logic; -- .TXD
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_read_n_out : out std_logic_vector(0 downto 0); -- tristate_conduit_bridge_0_out.generic_tristate_controller_0_tcm_read_n_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_data_out : inout std_logic_vector(7 downto 0) := (others => '0'); -- .generic_tristate_controller_0_tcm_data_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_chipselect_n_out : out std_logic_vector(0 downto 0); -- .generic_tristate_controller_0_tcm_chipselect_n_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_write_n_out : out std_logic_vector(0 downto 0); -- .generic_tristate_controller_0_tcm_write_n_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_byteenable_out : out std_logic_vector(0 downto 0); -- .generic_tristate_controller_0_tcm_byteenable_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_begintransfer_out : out std_logic_vector(0 downto 0); -- .generic_tristate_controller_0_tcm_begintransfer_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_address_out : out std_logic_vector(21 downto 0) -- .generic_tristate_controller_0_tcm_address_out
);
end entity niosII_system;
architecture rtl of niosII_system is
component niosII_system_nios2_qsys_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
d_address : out std_logic_vector(24 downto 0); -- address
d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
d_read : out std_logic; -- read
d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
d_waitrequest : in std_logic := 'X'; -- waitrequest
d_write : out std_logic; -- write
d_writedata : out std_logic_vector(31 downto 0); -- writedata
jtag_debug_module_debugaccess_to_roms : out std_logic; -- debugaccess
i_address : out std_logic_vector(24 downto 0); -- address
i_read : out std_logic; -- read
i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
i_waitrequest : in std_logic := 'X'; -- waitrequest
d_irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
jtag_debug_module_resetrequest : out std_logic; -- reset
jtag_debug_module_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
jtag_debug_module_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
jtag_debug_module_debugaccess : in std_logic := 'X'; -- debugaccess
jtag_debug_module_read : in std_logic := 'X'; -- read
jtag_debug_module_readdata : out std_logic_vector(31 downto 0); -- readdata
jtag_debug_module_waitrequest : out std_logic; -- waitrequest
jtag_debug_module_write : in std_logic := 'X'; -- write
jtag_debug_module_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
no_ci_readra : out std_logic -- readra
);
end component niosII_system_nios2_qsys_0;
component niosII_system_onchip_memory2_0 is
port (
clk : in std_logic := 'X'; -- clk
address : in std_logic_vector(11 downto 0) := (others => 'X'); -- address
clken : in std_logic := 'X'; -- clken
chipselect : in std_logic := 'X'; -- chipselect
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
reset : in std_logic := 'X'; -- reset
reset_req : in std_logic := 'X' -- reset_req
);
end component niosII_system_onchip_memory2_0;
component niosII_system_sysid_qsys_0 is
port (
clock : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
readdata : out std_logic_vector(31 downto 0); -- readdata
address : in std_logic := 'X' -- address
);
end component niosII_system_sysid_qsys_0;
component niosII_system_jtag_uart_0 is
port (
clk : in std_logic := 'X'; -- clk
rst_n : in std_logic := 'X'; -- reset_n
av_chipselect : in std_logic := 'X'; -- chipselect
av_address : in std_logic := 'X'; -- address
av_read_n : in std_logic := 'X'; -- read_n
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_write_n : in std_logic := 'X'; -- write_n
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_waitrequest : out std_logic; -- waitrequest
av_irq : out std_logic -- irq
);
end component niosII_system_jtag_uart_0;
component niosII_system_green_leds is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0); -- readdata
out_port : out std_logic_vector(7 downto 0) -- export
);
end component niosII_system_green_leds;
component niosII_system_switches is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
in_port : in std_logic_vector(7 downto 0) := (others => 'X') -- export
);
end component niosII_system_switches;
component niosII_system_altpll_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
c0 : out std_logic; -- clk
c1 : out std_logic; -- clk
areset : in std_logic := 'X'; -- export
locked : out std_logic; -- export
phasedone : out std_logic -- export
);
end component niosII_system_altpll_0;
component niosII_system_sdram_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
az_addr : in std_logic_vector(21 downto 0) := (others => 'X'); -- address
az_be_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable_n
az_cs : in std_logic := 'X'; -- chipselect
az_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
az_rd_n : in std_logic := 'X'; -- read_n
az_wr_n : in std_logic := 'X'; -- write_n
za_data : out std_logic_vector(15 downto 0); -- readdata
za_valid : out std_logic; -- readdatavalid
za_waitrequest : out std_logic; -- waitrequest
zs_addr : out std_logic_vector(11 downto 0); -- export
zs_ba : out std_logic_vector(1 downto 0); -- export
zs_cas_n : out std_logic; -- export
zs_cke : out std_logic; -- export
zs_cs_n : out std_logic; -- export
zs_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- export
zs_dqm : out std_logic_vector(1 downto 0); -- export
zs_ras_n : out std_logic; -- export
zs_we_n : out std_logic -- export
);
end component niosII_system_sdram_0;
component niosII_system_sram_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
SRAM_DQ : inout std_logic_vector(15 downto 0) := (others => 'X'); -- export
SRAM_ADDR : out std_logic_vector(17 downto 0); -- export
SRAM_LB_N : out std_logic; -- export
SRAM_UB_N : out std_logic; -- export
SRAM_CE_N : out std_logic; -- export
SRAM_OE_N : out std_logic; -- export
SRAM_WE_N : out std_logic; -- export
address : in std_logic_vector(17 downto 0) := (others => 'X'); -- address
byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(15 downto 0); -- readdata
readdatavalid : out std_logic -- readdatavalid
);
end component niosII_system_sram_0;
component niosII_system_timer_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(15 downto 0); -- readdata
chipselect : in std_logic := 'X'; -- chipselect
write_n : in std_logic := 'X'; -- write_n
irq : out std_logic -- irq
);
end component niosII_system_timer_0;
component niosII_system_usb_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
chipselect : in std_logic := 'X'; -- chipselect
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(15 downto 0); -- readdata
irq : out std_logic; -- irq
OTG_INT1 : in std_logic := 'X'; -- export
OTG_DATA : inout std_logic_vector(15 downto 0) := (others => 'X'); -- export
OTG_RST_N : out std_logic; -- export
OTG_ADDR : out std_logic_vector(1 downto 0); -- export
OTG_CS_N : out std_logic; -- export
OTG_RD_N : out std_logic; -- export
OTG_WR_N : out std_logic; -- export
OTG_INT0 : in std_logic := 'X' -- export
);
end component niosII_system_usb_0;
component niosII_system_rs232_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
address : in std_logic := 'X'; -- address
chipselect : in std_logic := 'X'; -- chipselect
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(31 downto 0); -- readdata
irq : out std_logic; -- irq
UART_RXD : in std_logic := 'X'; -- export
UART_TXD : out std_logic -- export
);
end component niosII_system_rs232_0;
component niosII_system_generic_tristate_controller_0 is
generic (
TCM_ADDRESS_W : integer := 30;
TCM_DATA_W : integer := 32;
TCM_BYTEENABLE_W : integer := 4;
TCM_READ_WAIT : integer := 1;
TCM_WRITE_WAIT : integer := 0;
TCM_SETUP_WAIT : integer := 0;
TCM_DATA_HOLD : integer := 0;
TCM_TURNAROUND_TIME : integer := 2;
TCM_TIMING_UNITS : integer := 1;
TCM_READLATENCY : integer := 2;
TCM_SYMBOLS_PER_WORD : integer := 4;
USE_READDATA : integer := 1;
USE_WRITEDATA : integer := 1;
USE_READ : integer := 1;
USE_WRITE : integer := 1;
USE_BYTEENABLE : integer := 1;
USE_CHIPSELECT : integer := 0;
USE_LOCK : integer := 0;
USE_ADDRESS : integer := 1;
USE_WAITREQUEST : integer := 0;
USE_WRITEBYTEENABLE : integer := 0;
USE_OUTPUTENABLE : integer := 0;
USE_RESETREQUEST : integer := 0;
USE_IRQ : integer := 0;
USE_RESET_OUTPUT : integer := 0;
ACTIVE_LOW_READ : integer := 0;
ACTIVE_LOW_LOCK : integer := 0;
ACTIVE_LOW_WRITE : integer := 0;
ACTIVE_LOW_CHIPSELECT : integer := 0;
ACTIVE_LOW_BYTEENABLE : integer := 0;
ACTIVE_LOW_OUTPUTENABLE : integer := 0;
ACTIVE_LOW_WRITEBYTEENABLE : integer := 0;
ACTIVE_LOW_WAITREQUEST : integer := 0;
ACTIVE_LOW_BEGINTRANSFER : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0
);
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset : in std_logic := 'X'; -- reset
uas_address : in std_logic_vector(21 downto 0) := (others => 'X'); -- address
uas_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount
uas_read : in std_logic := 'X'; -- read
uas_write : in std_logic := 'X'; -- write
uas_waitrequest : out std_logic; -- waitrequest
uas_readdatavalid : out std_logic; -- readdatavalid
uas_byteenable : in std_logic_vector(0 downto 0) := (others => 'X'); -- byteenable
uas_readdata : out std_logic_vector(7 downto 0); -- readdata
uas_writedata : in std_logic_vector(7 downto 0) := (others => 'X'); -- writedata
uas_lock : in std_logic := 'X'; -- lock
uas_debugaccess : in std_logic := 'X'; -- debugaccess
tcm_write_n_out : out std_logic; -- write_n_out
tcm_read_n_out : out std_logic; -- read_n_out
tcm_begintransfer_out : out std_logic; -- begintransfer_out
tcm_chipselect_n_out : out std_logic; -- chipselect_n_out
tcm_request : out std_logic; -- request
tcm_grant : in std_logic := 'X'; -- grant
tcm_address_out : out std_logic_vector(21 downto 0); -- address_out
tcm_byteenable_out : out std_logic; -- byteenable_out
tcm_data_out : out std_logic_vector(7 downto 0); -- data_out
tcm_data_outen : out std_logic; -- data_outen
tcm_data_in : in std_logic_vector(7 downto 0) := (others => 'X') -- data_in
);
end component niosII_system_generic_tristate_controller_0;
component niosII_system_tristate_conduit_bridge_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
request : in std_logic := 'X'; -- request
grant : out std_logic; -- grant
tcs_generic_tristate_controller_0_tcm_read_n_out : in std_logic_vector(0 downto 0) := (others => 'X'); -- generic_tristate_controller_0_tcm_read_n_out_out
tcs_generic_tristate_controller_0_tcm_data_out : in std_logic_vector(7 downto 0) := (others => 'X'); -- generic_tristate_controller_0_tcm_data_out_out
tcs_generic_tristate_controller_0_tcm_data_outen : in std_logic := 'X'; -- generic_tristate_controller_0_tcm_data_out_outen
tcs_generic_tristate_controller_0_tcm_data_in : out std_logic_vector(7 downto 0); -- generic_tristate_controller_0_tcm_data_out_in
tcs_generic_tristate_controller_0_tcm_chipselect_n_out : in std_logic_vector(0 downto 0) := (others => 'X'); -- generic_tristate_controller_0_tcm_chipselect_n_out_out
tcs_generic_tristate_controller_0_tcm_write_n_out : in std_logic_vector(0 downto 0) := (others => 'X'); -- generic_tristate_controller_0_tcm_write_n_out_out
tcs_generic_tristate_controller_0_tcm_byteenable_out : in std_logic_vector(0 downto 0) := (others => 'X'); -- generic_tristate_controller_0_tcm_byteenable_out_out
tcs_generic_tristate_controller_0_tcm_begintransfer_out : in std_logic_vector(0 downto 0) := (others => 'X'); -- generic_tristate_controller_0_tcm_begintransfer_out_out
tcs_generic_tristate_controller_0_tcm_address_out : in std_logic_vector(21 downto 0) := (others => 'X'); -- generic_tristate_controller_0_tcm_address_out_out
generic_tristate_controller_0_tcm_read_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_read_n_out
generic_tristate_controller_0_tcm_data_out : inout std_logic_vector(7 downto 0) := (others => 'X'); -- generic_tristate_controller_0_tcm_data_out
generic_tristate_controller_0_tcm_chipselect_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_chipselect_n_out
generic_tristate_controller_0_tcm_write_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_write_n_out
generic_tristate_controller_0_tcm_byteenable_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_byteenable_out
generic_tristate_controller_0_tcm_begintransfer_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_begintransfer_out
generic_tristate_controller_0_tcm_address_out : out std_logic_vector(21 downto 0) -- generic_tristate_controller_0_tcm_address_out
);
end component niosII_system_tristate_conduit_bridge_0;
component niosII_system_tristate_conduit_pin_sharer_0 is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset : in std_logic := 'X'; -- reset
request : out std_logic; -- request
grant : in std_logic := 'X'; -- grant
generic_tristate_controller_0_tcm_byteenable_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_byteenable_out_out
generic_tristate_controller_0_tcm_address_out : out std_logic_vector(21 downto 0); -- generic_tristate_controller_0_tcm_address_out_out
generic_tristate_controller_0_tcm_read_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_read_n_out_out
generic_tristate_controller_0_tcm_write_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_write_n_out_out
generic_tristate_controller_0_tcm_data_out : out std_logic_vector(7 downto 0); -- generic_tristate_controller_0_tcm_data_out_out
generic_tristate_controller_0_tcm_data_in : in std_logic_vector(7 downto 0) := (others => 'X'); -- generic_tristate_controller_0_tcm_data_out_in
generic_tristate_controller_0_tcm_data_outen : out std_logic; -- generic_tristate_controller_0_tcm_data_out_outen
generic_tristate_controller_0_tcm_chipselect_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_chipselect_n_out_out
generic_tristate_controller_0_tcm_begintransfer_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_begintransfer_out_out
tcs0_request : in std_logic := 'X'; -- request
tcs0_grant : out std_logic; -- grant
tcs0_byteenable_out : in std_logic_vector(0 downto 0) := (others => 'X'); -- byteenable_out
tcs0_address_out : in std_logic_vector(21 downto 0) := (others => 'X'); -- address_out
tcs0_read_n_out : in std_logic_vector(0 downto 0) := (others => 'X'); -- read_n_out
tcs0_write_n_out : in std_logic_vector(0 downto 0) := (others => 'X'); -- write_n_out
tcs0_data_out : in std_logic_vector(7 downto 0) := (others => 'X'); -- data_out
tcs0_data_in : out std_logic_vector(7 downto 0); -- data_in
tcs0_data_outen : in std_logic := 'X'; -- data_outen
tcs0_chipselect_n_out : in std_logic_vector(0 downto 0) := (others => 'X'); -- chipselect_n_out
tcs0_begintransfer_out : in std_logic_vector(0 downto 0) := (others => 'X') -- begintransfer_out
);
end component niosII_system_tristate_conduit_pin_sharer_0;
component altera_merlin_master_agent is
generic (
PKT_PROTECTION_H : integer := 80;
PKT_PROTECTION_L : integer := 80;
PKT_BEGIN_BURST : integer := 81;
PKT_BURSTWRAP_H : integer := 79;
PKT_BURSTWRAP_L : integer := 77;
PKT_BURST_SIZE_H : integer := 86;
PKT_BURST_SIZE_L : integer := 84;
PKT_BURST_TYPE_H : integer := 94;
PKT_BURST_TYPE_L : integer := 93;
PKT_BYTE_CNT_H : integer := 76;
PKT_BYTE_CNT_L : integer := 74;
PKT_ADDR_H : integer := 73;
PKT_ADDR_L : integer := 42;
PKT_TRANS_COMPRESSED_READ : integer := 41;
PKT_TRANS_POSTED : integer := 40;
PKT_TRANS_WRITE : integer := 39;
PKT_TRANS_READ : integer := 38;
PKT_TRANS_LOCK : integer := 82;
PKT_TRANS_EXCLUSIVE : integer := 83;
PKT_DATA_H : integer := 37;
PKT_DATA_L : integer := 6;
PKT_BYTEEN_H : integer := 5;
PKT_BYTEEN_L : integer := 2;
PKT_SRC_ID_H : integer := 1;
PKT_SRC_ID_L : integer := 1;
PKT_DEST_ID_H : integer := 0;
PKT_DEST_ID_L : integer := 0;
PKT_THREAD_ID_H : integer := 88;
PKT_THREAD_ID_L : integer := 87;
PKT_CACHE_H : integer := 92;
PKT_CACHE_L : integer := 89;
PKT_DATA_SIDEBAND_H : integer := 105;
PKT_DATA_SIDEBAND_L : integer := 98;
PKT_QOS_H : integer := 109;
PKT_QOS_L : integer := 106;
PKT_ADDR_SIDEBAND_H : integer := 97;
PKT_ADDR_SIDEBAND_L : integer := 93;
PKT_RESPONSE_STATUS_H : integer := 111;
PKT_RESPONSE_STATUS_L : integer := 110;
ST_DATA_W : integer := 112;
ST_CHANNEL_W : integer := 1;
AV_BURSTCOUNT_W : integer := 3;
SUPPRESS_0_BYTEEN_RSP : integer := 1;
ID : integer := 1;
BURSTWRAP_VALUE : integer := 4;
CACHE_VALUE : integer := 0;
SECURE_ACCESS_BIT : integer := 1;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
av_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
av_write : in std_logic := 'X'; -- write
av_read : in std_logic := 'X'; -- read
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_waitrequest : out std_logic; -- waitrequest
av_readdatavalid : out std_logic; -- readdatavalid
av_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
av_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
av_debugaccess : in std_logic := 'X'; -- debugaccess
av_lock : in std_logic := 'X'; -- lock
cp_valid : out std_logic; -- valid
cp_data : out std_logic_vector(99 downto 0); -- data
cp_startofpacket : out std_logic; -- startofpacket
cp_endofpacket : out std_logic; -- endofpacket
cp_ready : in std_logic := 'X'; -- ready
rp_valid : in std_logic := 'X'; -- valid
rp_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
rp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rp_startofpacket : in std_logic := 'X'; -- startofpacket
rp_endofpacket : in std_logic := 'X'; -- endofpacket
rp_ready : out std_logic; -- ready
av_response : out std_logic_vector(1 downto 0); -- response
av_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
av_writeresponsevalid : out std_logic -- writeresponsevalid
);
end component altera_merlin_master_agent;
component niosII_system_addr_router is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(99 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component niosII_system_addr_router;
component niosII_system_addr_router_001 is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(99 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component niosII_system_addr_router_001;
component niosII_system_id_router is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(99 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component niosII_system_id_router;
component niosII_system_id_router_001 is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(81 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(81 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component niosII_system_id_router_001;
component niosII_system_id_router_004 is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(72 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(72 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component niosII_system_id_router_004;
component niosII_system_id_router_005 is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(99 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component niosII_system_id_router_005;
component niosII_system_cmd_xbar_demux is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink_ready : out std_logic; -- ready
sink_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid
src0_ready : in std_logic := 'X'; -- ready
src0_valid : out std_logic; -- valid
src0_data : out std_logic_vector(99 downto 0); -- data
src0_channel : out std_logic_vector(12 downto 0); -- channel
src0_startofpacket : out std_logic; -- startofpacket
src0_endofpacket : out std_logic; -- endofpacket
src1_ready : in std_logic := 'X'; -- ready
src1_valid : out std_logic; -- valid
src1_data : out std_logic_vector(99 downto 0); -- data
src1_channel : out std_logic_vector(12 downto 0); -- channel
src1_startofpacket : out std_logic; -- startofpacket
src1_endofpacket : out std_logic; -- endofpacket
src2_ready : in std_logic := 'X'; -- ready
src2_valid : out std_logic; -- valid
src2_data : out std_logic_vector(99 downto 0); -- data
src2_channel : out std_logic_vector(12 downto 0); -- channel
src2_startofpacket : out std_logic; -- startofpacket
src2_endofpacket : out std_logic; -- endofpacket
src3_ready : in std_logic := 'X'; -- ready
src3_valid : out std_logic; -- valid
src3_data : out std_logic_vector(99 downto 0); -- data
src3_channel : out std_logic_vector(12 downto 0); -- channel
src3_startofpacket : out std_logic; -- startofpacket
src3_endofpacket : out std_logic; -- endofpacket
src4_ready : in std_logic := 'X'; -- ready
src4_valid : out std_logic; -- valid
src4_data : out std_logic_vector(99 downto 0); -- data
src4_channel : out std_logic_vector(12 downto 0); -- channel
src4_startofpacket : out std_logic; -- startofpacket
src4_endofpacket : out std_logic -- endofpacket
);
end component niosII_system_cmd_xbar_demux;
component niosII_system_cmd_xbar_demux_001 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink_ready : out std_logic; -- ready
sink_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid
src0_ready : in std_logic := 'X'; -- ready
src0_valid : out std_logic; -- valid
src0_data : out std_logic_vector(99 downto 0); -- data
src0_channel : out std_logic_vector(12 downto 0); -- channel
src0_startofpacket : out std_logic; -- startofpacket
src0_endofpacket : out std_logic; -- endofpacket
src1_ready : in std_logic := 'X'; -- ready
src1_valid : out std_logic; -- valid
src1_data : out std_logic_vector(99 downto 0); -- data
src1_channel : out std_logic_vector(12 downto 0); -- channel
src1_startofpacket : out std_logic; -- startofpacket
src1_endofpacket : out std_logic; -- endofpacket
src2_ready : in std_logic := 'X'; -- ready
src2_valid : out std_logic; -- valid
src2_data : out std_logic_vector(99 downto 0); -- data
src2_channel : out std_logic_vector(12 downto 0); -- channel
src2_startofpacket : out std_logic; -- startofpacket
src2_endofpacket : out std_logic; -- endofpacket
src3_ready : in std_logic := 'X'; -- ready
src3_valid : out std_logic; -- valid
src3_data : out std_logic_vector(99 downto 0); -- data
src3_channel : out std_logic_vector(12 downto 0); -- channel
src3_startofpacket : out std_logic; -- startofpacket
src3_endofpacket : out std_logic; -- endofpacket
src4_ready : in std_logic := 'X'; -- ready
src4_valid : out std_logic; -- valid
src4_data : out std_logic_vector(99 downto 0); -- data
src4_channel : out std_logic_vector(12 downto 0); -- channel
src4_startofpacket : out std_logic; -- startofpacket
src4_endofpacket : out std_logic; -- endofpacket
src5_ready : in std_logic := 'X'; -- ready
src5_valid : out std_logic; -- valid
src5_data : out std_logic_vector(99 downto 0); -- data
src5_channel : out std_logic_vector(12 downto 0); -- channel
src5_startofpacket : out std_logic; -- startofpacket
src5_endofpacket : out std_logic; -- endofpacket
src6_ready : in std_logic := 'X'; -- ready
src6_valid : out std_logic; -- valid
src6_data : out std_logic_vector(99 downto 0); -- data
src6_channel : out std_logic_vector(12 downto 0); -- channel
src6_startofpacket : out std_logic; -- startofpacket
src6_endofpacket : out std_logic; -- endofpacket
src7_ready : in std_logic := 'X'; -- ready
src7_valid : out std_logic; -- valid
src7_data : out std_logic_vector(99 downto 0); -- data
src7_channel : out std_logic_vector(12 downto 0); -- channel
src7_startofpacket : out std_logic; -- startofpacket
src7_endofpacket : out std_logic; -- endofpacket
src8_ready : in std_logic := 'X'; -- ready
src8_valid : out std_logic; -- valid
src8_data : out std_logic_vector(99 downto 0); -- data
src8_channel : out std_logic_vector(12 downto 0); -- channel
src8_startofpacket : out std_logic; -- startofpacket
src8_endofpacket : out std_logic; -- endofpacket
src9_ready : in std_logic := 'X'; -- ready
src9_valid : out std_logic; -- valid
src9_data : out std_logic_vector(99 downto 0); -- data
src9_channel : out std_logic_vector(12 downto 0); -- channel
src9_startofpacket : out std_logic; -- startofpacket
src9_endofpacket : out std_logic; -- endofpacket
src10_ready : in std_logic := 'X'; -- ready
src10_valid : out std_logic; -- valid
src10_data : out std_logic_vector(99 downto 0); -- data
src10_channel : out std_logic_vector(12 downto 0); -- channel
src10_startofpacket : out std_logic; -- startofpacket
src10_endofpacket : out std_logic; -- endofpacket
src11_ready : in std_logic := 'X'; -- ready
src11_valid : out std_logic; -- valid
src11_data : out std_logic_vector(99 downto 0); -- data
src11_channel : out std_logic_vector(12 downto 0); -- channel
src11_startofpacket : out std_logic; -- startofpacket
src11_endofpacket : out std_logic; -- endofpacket
src12_ready : in std_logic := 'X'; -- ready
src12_valid : out std_logic; -- valid
src12_data : out std_logic_vector(99 downto 0); -- data
src12_channel : out std_logic_vector(12 downto 0); -- channel
src12_startofpacket : out std_logic; -- startofpacket
src12_endofpacket : out std_logic -- endofpacket
);
end component niosII_system_cmd_xbar_demux_001;
component niosII_system_cmd_xbar_mux is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(99 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic; -- endofpacket
sink0_ready : out std_logic; -- ready
sink0_valid : in std_logic := 'X'; -- valid
sink0_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink0_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink1_ready : out std_logic; -- ready
sink1_valid : in std_logic := 'X'; -- valid
sink1_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink1_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink1_startofpacket : in std_logic := 'X'; -- startofpacket
sink1_endofpacket : in std_logic := 'X' -- endofpacket
);
end component niosII_system_cmd_xbar_mux;
component niosII_system_rsp_xbar_demux is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink_ready : out std_logic; -- ready
sink_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid
src0_ready : in std_logic := 'X'; -- ready
src0_valid : out std_logic; -- valid
src0_data : out std_logic_vector(99 downto 0); -- data
src0_channel : out std_logic_vector(12 downto 0); -- channel
src0_startofpacket : out std_logic; -- startofpacket
src0_endofpacket : out std_logic; -- endofpacket
src1_ready : in std_logic := 'X'; -- ready
src1_valid : out std_logic; -- valid
src1_data : out std_logic_vector(99 downto 0); -- data
src1_channel : out std_logic_vector(12 downto 0); -- channel
src1_startofpacket : out std_logic; -- startofpacket
src1_endofpacket : out std_logic -- endofpacket
);
end component niosII_system_rsp_xbar_demux;
component niosII_system_rsp_xbar_demux_005 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink_ready : out std_logic; -- ready
sink_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid
src0_ready : in std_logic := 'X'; -- ready
src0_valid : out std_logic; -- valid
src0_data : out std_logic_vector(99 downto 0); -- data
src0_channel : out std_logic_vector(12 downto 0); -- channel
src0_startofpacket : out std_logic; -- startofpacket
src0_endofpacket : out std_logic -- endofpacket
);
end component niosII_system_rsp_xbar_demux_005;
component niosII_system_rsp_xbar_mux is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(99 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic; -- endofpacket
sink0_ready : out std_logic; -- ready
sink0_valid : in std_logic := 'X'; -- valid
sink0_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink0_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink1_ready : out std_logic; -- ready
sink1_valid : in std_logic := 'X'; -- valid
sink1_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink1_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink1_startofpacket : in std_logic := 'X'; -- startofpacket
sink1_endofpacket : in std_logic := 'X'; -- endofpacket
sink2_ready : out std_logic; -- ready
sink2_valid : in std_logic := 'X'; -- valid
sink2_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink2_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink2_startofpacket : in std_logic := 'X'; -- startofpacket
sink2_endofpacket : in std_logic := 'X'; -- endofpacket
sink3_ready : out std_logic; -- ready
sink3_valid : in std_logic := 'X'; -- valid
sink3_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink3_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink3_startofpacket : in std_logic := 'X'; -- startofpacket
sink3_endofpacket : in std_logic := 'X'; -- endofpacket
sink4_ready : out std_logic; -- ready
sink4_valid : in std_logic := 'X'; -- valid
sink4_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink4_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink4_startofpacket : in std_logic := 'X'; -- startofpacket
sink4_endofpacket : in std_logic := 'X' -- endofpacket
);
end component niosII_system_rsp_xbar_mux;
component niosII_system_rsp_xbar_mux_001 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(99 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic; -- endofpacket
sink0_ready : out std_logic; -- ready
sink0_valid : in std_logic := 'X'; -- valid
sink0_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink0_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink1_ready : out std_logic; -- ready
sink1_valid : in std_logic := 'X'; -- valid
sink1_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink1_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink1_startofpacket : in std_logic := 'X'; -- startofpacket
sink1_endofpacket : in std_logic := 'X'; -- endofpacket
sink2_ready : out std_logic; -- ready
sink2_valid : in std_logic := 'X'; -- valid
sink2_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink2_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink2_startofpacket : in std_logic := 'X'; -- startofpacket
sink2_endofpacket : in std_logic := 'X'; -- endofpacket
sink3_ready : out std_logic; -- ready
sink3_valid : in std_logic := 'X'; -- valid
sink3_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink3_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink3_startofpacket : in std_logic := 'X'; -- startofpacket
sink3_endofpacket : in std_logic := 'X'; -- endofpacket
sink4_ready : out std_logic; -- ready
sink4_valid : in std_logic := 'X'; -- valid
sink4_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink4_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink4_startofpacket : in std_logic := 'X'; -- startofpacket
sink4_endofpacket : in std_logic := 'X'; -- endofpacket
sink5_ready : out std_logic; -- ready
sink5_valid : in std_logic := 'X'; -- valid
sink5_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink5_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink5_startofpacket : in std_logic := 'X'; -- startofpacket
sink5_endofpacket : in std_logic := 'X'; -- endofpacket
sink6_ready : out std_logic; -- ready
sink6_valid : in std_logic := 'X'; -- valid
sink6_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink6_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink6_startofpacket : in std_logic := 'X'; -- startofpacket
sink6_endofpacket : in std_logic := 'X'; -- endofpacket
sink7_ready : out std_logic; -- ready
sink7_valid : in std_logic := 'X'; -- valid
sink7_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink7_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink7_startofpacket : in std_logic := 'X'; -- startofpacket
sink7_endofpacket : in std_logic := 'X'; -- endofpacket
sink8_ready : out std_logic; -- ready
sink8_valid : in std_logic := 'X'; -- valid
sink8_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink8_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink8_startofpacket : in std_logic := 'X'; -- startofpacket
sink8_endofpacket : in std_logic := 'X'; -- endofpacket
sink9_ready : out std_logic; -- ready
sink9_valid : in std_logic := 'X'; -- valid
sink9_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink9_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink9_startofpacket : in std_logic := 'X'; -- startofpacket
sink9_endofpacket : in std_logic := 'X'; -- endofpacket
sink10_ready : out std_logic; -- ready
sink10_valid : in std_logic := 'X'; -- valid
sink10_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink10_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink10_startofpacket : in std_logic := 'X'; -- startofpacket
sink10_endofpacket : in std_logic := 'X'; -- endofpacket
sink11_ready : out std_logic; -- ready
sink11_valid : in std_logic := 'X'; -- valid
sink11_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink11_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink11_startofpacket : in std_logic := 'X'; -- startofpacket
sink11_endofpacket : in std_logic := 'X'; -- endofpacket
sink12_ready : out std_logic; -- ready
sink12_valid : in std_logic := 'X'; -- valid
sink12_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink12_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink12_startofpacket : in std_logic := 'X'; -- startofpacket
sink12_endofpacket : in std_logic := 'X' -- endofpacket
);
end component niosII_system_rsp_xbar_mux_001;
component altera_avalon_st_handshake_clock_crosser is
generic (
DATA_WIDTH : integer := 8;
BITS_PER_SYMBOL : integer := 8;
USE_PACKETS : integer := 0;
USE_CHANNEL : integer := 0;
CHANNEL_WIDTH : integer := 1;
USE_ERROR : integer := 0;
ERROR_WIDTH : integer := 1;
VALID_SYNC_DEPTH : integer := 2;
READY_SYNC_DEPTH : integer := 2;
USE_OUTPUT_PIPELINE : integer := 1
);
port (
in_clk : in std_logic := 'X'; -- clk
in_reset : in std_logic := 'X'; -- reset
out_clk : in std_logic := 'X'; -- clk
out_reset : in std_logic := 'X'; -- reset
in_ready : out std_logic; -- ready
in_valid : in std_logic := 'X'; -- valid
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
in_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
out_ready : in std_logic := 'X'; -- ready
out_valid : out std_logic; -- valid
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic; -- endofpacket
out_channel : out std_logic_vector(12 downto 0); -- channel
out_data : out std_logic_vector(99 downto 0); -- data
in_empty : in std_logic := 'X'; -- empty
in_error : in std_logic := 'X'; -- error
out_empty : out std_logic; -- empty
out_error : out std_logic -- error
);
end component altera_avalon_st_handshake_clock_crosser;
component niosII_system_irq_mapper is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
receiver0_irq : in std_logic := 'X'; -- irq
receiver1_irq : in std_logic := 'X'; -- irq
receiver2_irq : in std_logic := 'X'; -- irq
receiver3_irq : in std_logic := 'X'; -- irq
sender_irq : out std_logic_vector(31 downto 0) -- irq
);
end component niosII_system_irq_mapper;
component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 3;
USE_MEMORY_BLOCKS : integer := 1;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(100 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_data : out std_logic_vector(100 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic; -- endofpacket
csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
csr_read : in std_logic := 'X'; -- read
csr_write : in std_logic := 'X'; -- write
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
almost_full_data : out std_logic; -- data
almost_empty_data : out std_logic; -- data
in_empty : in std_logic := 'X'; -- empty
out_empty : out std_logic; -- empty
in_error : in std_logic := 'X'; -- error
out_error : out std_logic; -- error
in_channel : in std_logic := 'X'; -- channel
out_channel : out std_logic -- channel
);
end component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo;
component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 3;
USE_MEMORY_BLOCKS : integer := 1;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(82 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_data : out std_logic_vector(82 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic; -- endofpacket
csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
csr_read : in std_logic := 'X'; -- read
csr_write : in std_logic := 'X'; -- write
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
almost_full_data : out std_logic; -- data
almost_empty_data : out std_logic; -- data
in_empty : in std_logic := 'X'; -- empty
out_empty : out std_logic; -- empty
in_error : in std_logic := 'X'; -- error
out_error : out std_logic; -- error
in_channel : in std_logic := 'X'; -- channel
out_channel : out std_logic -- channel
);
end component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo;
component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 3;
USE_MEMORY_BLOCKS : integer := 1;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(17 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
out_data : out std_logic_vector(17 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
csr_read : in std_logic := 'X'; -- read
csr_write : in std_logic := 'X'; -- write
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
almost_full_data : out std_logic; -- data
almost_empty_data : out std_logic; -- data
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic; -- endofpacket
in_empty : in std_logic := 'X'; -- empty
out_empty : out std_logic; -- empty
in_error : in std_logic := 'X'; -- error
out_error : out std_logic; -- error
in_channel : in std_logic := 'X'; -- channel
out_channel : out std_logic -- channel
);
end component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo;
component niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 3;
USE_MEMORY_BLOCKS : integer := 1;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(73 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_data : out std_logic_vector(73 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic; -- endofpacket
csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
csr_read : in std_logic := 'X'; -- read
csr_write : in std_logic := 'X'; -- write
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
almost_full_data : out std_logic; -- data
almost_empty_data : out std_logic; -- data
in_empty : in std_logic := 'X'; -- empty
out_empty : out std_logic; -- empty
in_error : in std_logic := 'X'; -- error
out_error : out std_logic; -- error
in_channel : in std_logic := 'X'; -- channel
out_channel : out std_logic -- channel
);
end component niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo;
component niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 3;
USE_MEMORY_BLOCKS : integer := 1;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(9 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
out_data : out std_logic_vector(9 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
csr_read : in std_logic := 'X'; -- read
csr_write : in std_logic := 'X'; -- write
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
almost_full_data : out std_logic; -- data
almost_empty_data : out std_logic; -- data
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic; -- endofpacket
in_empty : in std_logic := 'X'; -- empty
out_empty : out std_logic; -- empty
in_error : in std_logic := 'X'; -- error
out_error : out std_logic; -- error
in_channel : in std_logic := 'X'; -- channel
out_channel : out std_logic -- channel
);
end component niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo;
component niosii_system_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 3;
USE_MEMORY_BLOCKS : integer := 1;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(33 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
out_data : out std_logic_vector(33 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
csr_read : in std_logic := 'X'; -- read
csr_write : in std_logic := 'X'; -- write
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
almost_full_data : out std_logic; -- data
almost_empty_data : out std_logic; -- data
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic; -- endofpacket
in_empty : in std_logic := 'X'; -- empty
out_empty : out std_logic; -- empty
in_error : in std_logic := 'X'; -- error
out_error : out std_logic; -- error
in_channel : in std_logic := 'X'; -- channel
out_channel : out std_logic -- channel
);
end component niosii_system_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo;
component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent is
generic (
PKT_DATA_H : integer := 31;
PKT_DATA_L : integer := 0;
PKT_BEGIN_BURST : integer := 81;
PKT_SYMBOL_W : integer := 8;
PKT_BYTEEN_H : integer := 71;
PKT_BYTEEN_L : integer := 68;
PKT_ADDR_H : integer := 63;
PKT_ADDR_L : integer := 32;
PKT_TRANS_COMPRESSED_READ : integer := 67;
PKT_TRANS_POSTED : integer := 66;
PKT_TRANS_WRITE : integer := 65;
PKT_TRANS_READ : integer := 64;
PKT_TRANS_LOCK : integer := 87;
PKT_SRC_ID_H : integer := 74;
PKT_SRC_ID_L : integer := 72;
PKT_DEST_ID_H : integer := 77;
PKT_DEST_ID_L : integer := 75;
PKT_BURSTWRAP_H : integer := 85;
PKT_BURSTWRAP_L : integer := 82;
PKT_BYTE_CNT_H : integer := 81;
PKT_BYTE_CNT_L : integer := 78;
PKT_PROTECTION_H : integer := 86;
PKT_PROTECTION_L : integer := 86;
PKT_RESPONSE_STATUS_H : integer := 89;
PKT_RESPONSE_STATUS_L : integer := 88;
PKT_BURST_SIZE_H : integer := 92;
PKT_BURST_SIZE_L : integer := 90;
ST_CHANNEL_W : integer := 8;
ST_DATA_W : integer := 93;
AVS_BURSTCOUNT_W : integer := 4;
SUPPRESS_0_BYTEEN_CMD : integer := 1;
PREVENT_FIFO_OVERFLOW : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(99 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(100 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(100 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(33 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(33 downto 0); -- data
m0_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
m0_writeresponserequest : out std_logic; -- writeresponserequest
m0_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent;
component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent is
generic (
PKT_DATA_H : integer := 31;
PKT_DATA_L : integer := 0;
PKT_BEGIN_BURST : integer := 81;
PKT_SYMBOL_W : integer := 8;
PKT_BYTEEN_H : integer := 71;
PKT_BYTEEN_L : integer := 68;
PKT_ADDR_H : integer := 63;
PKT_ADDR_L : integer := 32;
PKT_TRANS_COMPRESSED_READ : integer := 67;
PKT_TRANS_POSTED : integer := 66;
PKT_TRANS_WRITE : integer := 65;
PKT_TRANS_READ : integer := 64;
PKT_TRANS_LOCK : integer := 87;
PKT_SRC_ID_H : integer := 74;
PKT_SRC_ID_L : integer := 72;
PKT_DEST_ID_H : integer := 77;
PKT_DEST_ID_L : integer := 75;
PKT_BURSTWRAP_H : integer := 85;
PKT_BURSTWRAP_L : integer := 82;
PKT_BYTE_CNT_H : integer := 81;
PKT_BYTE_CNT_L : integer := 78;
PKT_PROTECTION_H : integer := 86;
PKT_PROTECTION_L : integer := 86;
PKT_RESPONSE_STATUS_H : integer := 89;
PKT_RESPONSE_STATUS_L : integer := 88;
PKT_BURST_SIZE_H : integer := 92;
PKT_BURST_SIZE_L : integer := 90;
ST_CHANNEL_W : integer := 8;
ST_DATA_W : integer := 93;
AVS_BURSTCOUNT_W : integer := 4;
SUPPRESS_0_BYTEEN_CMD : integer := 1;
PREVENT_FIFO_OVERFLOW : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic_vector(1 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(1 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(15 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(81 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(81 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(82 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(82 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(17 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(17 downto 0); -- data
m0_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
m0_writeresponserequest : out std_logic; -- writeresponserequest
m0_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent;
component niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent is
generic (
PKT_DATA_H : integer := 31;
PKT_DATA_L : integer := 0;
PKT_BEGIN_BURST : integer := 81;
PKT_SYMBOL_W : integer := 8;
PKT_BYTEEN_H : integer := 71;
PKT_BYTEEN_L : integer := 68;
PKT_ADDR_H : integer := 63;
PKT_ADDR_L : integer := 32;
PKT_TRANS_COMPRESSED_READ : integer := 67;
PKT_TRANS_POSTED : integer := 66;
PKT_TRANS_WRITE : integer := 65;
PKT_TRANS_READ : integer := 64;
PKT_TRANS_LOCK : integer := 87;
PKT_SRC_ID_H : integer := 74;
PKT_SRC_ID_L : integer := 72;
PKT_DEST_ID_H : integer := 77;
PKT_DEST_ID_L : integer := 75;
PKT_BURSTWRAP_H : integer := 85;
PKT_BURSTWRAP_L : integer := 82;
PKT_BYTE_CNT_H : integer := 81;
PKT_BYTE_CNT_L : integer := 78;
PKT_PROTECTION_H : integer := 86;
PKT_PROTECTION_L : integer := 86;
PKT_RESPONSE_STATUS_H : integer := 89;
PKT_RESPONSE_STATUS_L : integer := 88;
PKT_BURST_SIZE_H : integer := 92;
PKT_BURST_SIZE_L : integer := 90;
ST_CHANNEL_W : integer := 8;
ST_DATA_W : integer := 93;
AVS_BURSTCOUNT_W : integer := 4;
SUPPRESS_0_BYTEEN_CMD : integer := 1;
PREVENT_FIFO_OVERFLOW : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic_vector(0 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(0 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(7 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(72 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(72 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(73 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(73 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(9 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(9 downto 0); -- data
m0_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
m0_writeresponserequest : out std_logic; -- writeresponserequest
m0_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent;
component niosii_system_width_adapter is
generic (
IN_PKT_ADDR_H : integer := 60;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 63;
IN_PKT_BYTE_CNT_L : integer := 61;
IN_PKT_TRANS_COMPRESSED_READ : integer := 65;
IN_PKT_BURSTWRAP_H : integer := 67;
IN_PKT_BURSTWRAP_L : integer := 66;
IN_PKT_BURST_SIZE_H : integer := 70;
IN_PKT_BURST_SIZE_L : integer := 68;
IN_PKT_RESPONSE_STATUS_H : integer := 72;
IN_PKT_RESPONSE_STATUS_L : integer := 71;
IN_PKT_TRANS_EXCLUSIVE : integer := 73;
IN_PKT_BURST_TYPE_H : integer := 75;
IN_PKT_BURST_TYPE_L : integer := 74;
IN_ST_DATA_W : integer := 76;
OUT_PKT_ADDR_H : integer := 60;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 63;
OUT_PKT_BYTE_CNT_L : integer := 61;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 65;
OUT_PKT_BURST_SIZE_H : integer := 68;
OUT_PKT_BURST_SIZE_L : integer := 66;
OUT_PKT_RESPONSE_STATUS_H : integer := 70;
OUT_PKT_RESPONSE_STATUS_L : integer := 69;
OUT_PKT_TRANS_EXCLUSIVE : integer := 71;
OUT_PKT_BURST_TYPE_H : integer := 73;
OUT_PKT_BURST_TYPE_L : integer := 72;
OUT_ST_DATA_W : integer := 74;
ST_CHANNEL_W : integer := 32;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(81 downto 0); -- data
out_channel : out std_logic_vector(12 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data
);
end component niosii_system_width_adapter;
component niosii_system_width_adapter_001 is
generic (
IN_PKT_ADDR_H : integer := 60;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 63;
IN_PKT_BYTE_CNT_L : integer := 61;
IN_PKT_TRANS_COMPRESSED_READ : integer := 65;
IN_PKT_BURSTWRAP_H : integer := 67;
IN_PKT_BURSTWRAP_L : integer := 66;
IN_PKT_BURST_SIZE_H : integer := 70;
IN_PKT_BURST_SIZE_L : integer := 68;
IN_PKT_RESPONSE_STATUS_H : integer := 72;
IN_PKT_RESPONSE_STATUS_L : integer := 71;
IN_PKT_TRANS_EXCLUSIVE : integer := 73;
IN_PKT_BURST_TYPE_H : integer := 75;
IN_PKT_BURST_TYPE_L : integer := 74;
IN_ST_DATA_W : integer := 76;
OUT_PKT_ADDR_H : integer := 60;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 63;
OUT_PKT_BYTE_CNT_L : integer := 61;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 65;
OUT_PKT_BURST_SIZE_H : integer := 68;
OUT_PKT_BURST_SIZE_L : integer := 66;
OUT_PKT_RESPONSE_STATUS_H : integer := 70;
OUT_PKT_RESPONSE_STATUS_L : integer := 69;
OUT_PKT_TRANS_EXCLUSIVE : integer := 71;
OUT_PKT_BURST_TYPE_H : integer := 73;
OUT_PKT_BURST_TYPE_L : integer := 72;
OUT_ST_DATA_W : integer := 74;
ST_CHANNEL_W : integer := 32;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(81 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(99 downto 0); -- data
out_channel : out std_logic_vector(12 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data
);
end component niosii_system_width_adapter_001;
component niosii_system_width_adapter_004 is
generic (
IN_PKT_ADDR_H : integer := 60;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 63;
IN_PKT_BYTE_CNT_L : integer := 61;
IN_PKT_TRANS_COMPRESSED_READ : integer := 65;
IN_PKT_BURSTWRAP_H : integer := 67;
IN_PKT_BURSTWRAP_L : integer := 66;
IN_PKT_BURST_SIZE_H : integer := 70;
IN_PKT_BURST_SIZE_L : integer := 68;
IN_PKT_RESPONSE_STATUS_H : integer := 72;
IN_PKT_RESPONSE_STATUS_L : integer := 71;
IN_PKT_TRANS_EXCLUSIVE : integer := 73;
IN_PKT_BURST_TYPE_H : integer := 75;
IN_PKT_BURST_TYPE_L : integer := 74;
IN_ST_DATA_W : integer := 76;
OUT_PKT_ADDR_H : integer := 60;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 63;
OUT_PKT_BYTE_CNT_L : integer := 61;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 65;
OUT_PKT_BURST_SIZE_H : integer := 68;
OUT_PKT_BURST_SIZE_L : integer := 66;
OUT_PKT_RESPONSE_STATUS_H : integer := 70;
OUT_PKT_RESPONSE_STATUS_L : integer := 69;
OUT_PKT_TRANS_EXCLUSIVE : integer := 71;
OUT_PKT_BURST_TYPE_H : integer := 73;
OUT_PKT_BURST_TYPE_L : integer := 72;
OUT_ST_DATA_W : integer := 74;
ST_CHANNEL_W : integer := 32;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(72 downto 0); -- data
out_channel : out std_logic_vector(12 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data
);
end component niosii_system_width_adapter_004;
component niosii_system_width_adapter_005 is
generic (
IN_PKT_ADDR_H : integer := 60;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 63;
IN_PKT_BYTE_CNT_L : integer := 61;
IN_PKT_TRANS_COMPRESSED_READ : integer := 65;
IN_PKT_BURSTWRAP_H : integer := 67;
IN_PKT_BURSTWRAP_L : integer := 66;
IN_PKT_BURST_SIZE_H : integer := 70;
IN_PKT_BURST_SIZE_L : integer := 68;
IN_PKT_RESPONSE_STATUS_H : integer := 72;
IN_PKT_RESPONSE_STATUS_L : integer := 71;
IN_PKT_TRANS_EXCLUSIVE : integer := 73;
IN_PKT_BURST_TYPE_H : integer := 75;
IN_PKT_BURST_TYPE_L : integer := 74;
IN_ST_DATA_W : integer := 76;
OUT_PKT_ADDR_H : integer := 60;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 63;
OUT_PKT_BYTE_CNT_L : integer := 61;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 65;
OUT_PKT_BURST_SIZE_H : integer := 68;
OUT_PKT_BURST_SIZE_L : integer := 66;
OUT_PKT_RESPONSE_STATUS_H : integer := 70;
OUT_PKT_RESPONSE_STATUS_L : integer := 69;
OUT_PKT_TRANS_EXCLUSIVE : integer := 71;
OUT_PKT_BURST_TYPE_H : integer := 73;
OUT_PKT_BURST_TYPE_L : integer := 72;
OUT_ST_DATA_W : integer := 74;
ST_CHANNEL_W : integer := 32;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(72 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(99 downto 0); -- data
out_channel : out std_logic_vector(12 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data
);
end component niosii_system_width_adapter_005;
component niosii_system_nios2_qsys_0_instruction_master_translator is
generic (
AV_ADDRESS_W : integer := 32;
AV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 38;
UAV_BURSTCOUNT_W : integer := 10;
USE_READ : integer := 1;
USE_WRITE : integer := 1;
USE_BEGINBURSTTRANSFER : integer := 0;
USE_BEGINTRANSFER : integer := 0;
USE_CHIPSELECT : integer := 0;
USE_BURSTCOUNT : integer := 1;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_LINEWRAPBURSTS : integer := 0;
AV_REGISTERINCOMINGSIGNALS : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : out std_logic_vector(24 downto 0); -- address
uav_burstcount : out std_logic_vector(2 downto 0); -- burstcount
uav_read : out std_logic; -- read
uav_write : out std_logic; -- write
uav_waitrequest : in std_logic := 'X'; -- waitrequest
uav_readdatavalid : in std_logic := 'X'; -- readdatavalid
uav_byteenable : out std_logic_vector(3 downto 0); -- byteenable
uav_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
uav_writedata : out std_logic_vector(31 downto 0); -- writedata
uav_lock : out std_logic; -- lock
uav_debugaccess : out std_logic; -- debugaccess
av_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
av_waitrequest : out std_logic; -- waitrequest
av_read : in std_logic := 'X'; -- read
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount
av_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
av_beginbursttransfer : in std_logic := 'X'; -- beginbursttransfer
av_begintransfer : in std_logic := 'X'; -- begintransfer
av_chipselect : in std_logic := 'X'; -- chipselect
av_readdatavalid : out std_logic; -- readdatavalid
av_write : in std_logic := 'X'; -- write
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_lock : in std_logic := 'X'; -- lock
av_debugaccess : in std_logic := 'X'; -- debugaccess
uav_clken : out std_logic; -- clken
av_clken : in std_logic := 'X'; -- clken
uav_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
av_response : out std_logic_vector(1 downto 0); -- response
uav_writeresponserequest : out std_logic; -- writeresponserequest
uav_writeresponsevalid : in std_logic := 'X'; -- writeresponsevalid
av_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
av_writeresponsevalid : out std_logic -- writeresponsevalid
);
end component niosii_system_nios2_qsys_0_instruction_master_translator;
component niosii_system_nios2_qsys_0_data_master_translator is
generic (
AV_ADDRESS_W : integer := 32;
AV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 38;
UAV_BURSTCOUNT_W : integer := 10;
USE_READ : integer := 1;
USE_WRITE : integer := 1;
USE_BEGINBURSTTRANSFER : integer := 0;
USE_BEGINTRANSFER : integer := 0;
USE_CHIPSELECT : integer := 0;
USE_BURSTCOUNT : integer := 1;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_LINEWRAPBURSTS : integer := 0;
AV_REGISTERINCOMINGSIGNALS : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : out std_logic_vector(24 downto 0); -- address
uav_burstcount : out std_logic_vector(2 downto 0); -- burstcount
uav_read : out std_logic; -- read
uav_write : out std_logic; -- write
uav_waitrequest : in std_logic := 'X'; -- waitrequest
uav_readdatavalid : in std_logic := 'X'; -- readdatavalid
uav_byteenable : out std_logic_vector(3 downto 0); -- byteenable
uav_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
uav_writedata : out std_logic_vector(31 downto 0); -- writedata
uav_lock : out std_logic; -- lock
uav_debugaccess : out std_logic; -- debugaccess
av_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
av_waitrequest : out std_logic; -- waitrequest
av_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
av_read : in std_logic := 'X'; -- read
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_write : in std_logic := 'X'; -- write
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_debugaccess : in std_logic := 'X'; -- debugaccess
av_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount
av_beginbursttransfer : in std_logic := 'X'; -- beginbursttransfer
av_begintransfer : in std_logic := 'X'; -- begintransfer
av_chipselect : in std_logic := 'X'; -- chipselect
av_readdatavalid : out std_logic; -- readdatavalid
av_lock : in std_logic := 'X'; -- lock
uav_clken : out std_logic; -- clken
av_clken : in std_logic := 'X'; -- clken
uav_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
av_response : out std_logic_vector(1 downto 0); -- response
uav_writeresponserequest : out std_logic; -- writeresponserequest
uav_writeresponsevalid : in std_logic := 'X'; -- writeresponsevalid
av_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
av_writeresponsevalid : out std_logic -- writeresponsevalid
);
end component niosii_system_nios2_qsys_0_data_master_translator;
component niosii_system_burst_adapter is
generic (
PKT_ADDR_H : integer := 79;
PKT_ADDR_L : integer := 48;
PKT_BEGIN_BURST : integer := 81;
PKT_BYTE_CNT_H : integer := 5;
PKT_BYTE_CNT_L : integer := 0;
PKT_BYTEEN_H : integer := 83;
PKT_BYTEEN_L : integer := 80;
PKT_BURST_SIZE_H : integer := 86;
PKT_BURST_SIZE_L : integer := 84;
PKT_BURST_TYPE_H : integer := 88;
PKT_BURST_TYPE_L : integer := 87;
PKT_BURSTWRAP_H : integer := 11;
PKT_BURSTWRAP_L : integer := 6;
PKT_TRANS_COMPRESSED_READ : integer := 14;
PKT_TRANS_WRITE : integer := 13;
PKT_TRANS_READ : integer := 12;
OUT_NARROW_SIZE : integer := 0;
IN_NARROW_SIZE : integer := 0;
OUT_FIXED : integer := 0;
OUT_COMPLETE_WRAP : integer := 0;
ST_DATA_W : integer := 89;
ST_CHANNEL_W : integer := 8;
OUT_BYTE_CNT_H : integer := 5;
OUT_BURSTWRAP_H : integer := 11;
COMPRESSED_READ_SUPPORT : integer := 1;
BYTEENABLE_SYNTHESIS : integer := 0;
PIPE_INPUTS : integer := 0;
NO_WRAP_SUPPORT : integer := 0;
BURSTWRAP_CONST_MASK : integer := 0;
BURSTWRAP_CONST_VALUE : integer := -1
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink0_valid : in std_logic := 'X'; -- valid
sink0_data : in std_logic_vector(81 downto 0) := (others => 'X'); -- data
sink0_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink0_ready : out std_logic; -- ready
source0_valid : out std_logic; -- valid
source0_data : out std_logic_vector(81 downto 0); -- data
source0_channel : out std_logic_vector(12 downto 0); -- channel
source0_startofpacket : out std_logic; -- startofpacket
source0_endofpacket : out std_logic; -- endofpacket
source0_ready : in std_logic := 'X' -- ready
);
end component niosii_system_burst_adapter;
component niosii_system_burst_adapter_002 is
generic (
PKT_ADDR_H : integer := 79;
PKT_ADDR_L : integer := 48;
PKT_BEGIN_BURST : integer := 81;
PKT_BYTE_CNT_H : integer := 5;
PKT_BYTE_CNT_L : integer := 0;
PKT_BYTEEN_H : integer := 83;
PKT_BYTEEN_L : integer := 80;
PKT_BURST_SIZE_H : integer := 86;
PKT_BURST_SIZE_L : integer := 84;
PKT_BURST_TYPE_H : integer := 88;
PKT_BURST_TYPE_L : integer := 87;
PKT_BURSTWRAP_H : integer := 11;
PKT_BURSTWRAP_L : integer := 6;
PKT_TRANS_COMPRESSED_READ : integer := 14;
PKT_TRANS_WRITE : integer := 13;
PKT_TRANS_READ : integer := 12;
OUT_NARROW_SIZE : integer := 0;
IN_NARROW_SIZE : integer := 0;
OUT_FIXED : integer := 0;
OUT_COMPLETE_WRAP : integer := 0;
ST_DATA_W : integer := 89;
ST_CHANNEL_W : integer := 8;
OUT_BYTE_CNT_H : integer := 5;
OUT_BURSTWRAP_H : integer := 11;
COMPRESSED_READ_SUPPORT : integer := 1;
BYTEENABLE_SYNTHESIS : integer := 0;
PIPE_INPUTS : integer := 0;
NO_WRAP_SUPPORT : integer := 0;
BURSTWRAP_CONST_MASK : integer := 0;
BURSTWRAP_CONST_VALUE : integer := -1
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink0_valid : in std_logic := 'X'; -- valid
sink0_data : in std_logic_vector(72 downto 0) := (others => 'X'); -- data
sink0_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink0_ready : out std_logic; -- ready
source0_valid : out std_logic; -- valid
source0_data : out std_logic_vector(72 downto 0); -- data
source0_channel : out std_logic_vector(12 downto 0); -- channel
source0_startofpacket : out std_logic; -- startofpacket
source0_endofpacket : out std_logic; -- endofpacket
source0_ready : in std_logic := 'X' -- ready
);
end component niosii_system_burst_adapter_002;
component niosii_system_nios2_qsys_0_jtag_debug_module_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(8 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_debugaccess : out std_logic; -- debugaccess
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component niosii_system_nios2_qsys_0_jtag_debug_module_translator;
component niosii_system_sdram_0_s1_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(15 downto 0); -- readdata
uav_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(21 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(15 downto 0); -- writedata
av_byteenable : out std_logic_vector(1 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_chipselect : out std_logic; -- chipselect
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_writebyteenable : out std_logic_vector(1 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component niosii_system_sdram_0_s1_translator;
component niosii_system_onchip_memory2_0_s1_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(11 downto 0); -- address
av_write : out std_logic; -- write
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
av_read : out std_logic; -- read
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component niosii_system_onchip_memory2_0_s1_translator;
component niosii_system_sram_0_avalon_sram_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(15 downto 0); -- readdata
uav_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(17 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(15 downto 0); -- writedata
av_byteenable : out std_logic_vector(1 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(1 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component niosii_system_sram_0_avalon_sram_slave_translator;
component niosii_system_generic_tristate_controller_0_uas_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(0 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(7 downto 0); -- readdata
uav_writedata : in std_logic_vector(7 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(21 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(7 downto 0); -- writedata
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_lock : out std_logic; -- lock
av_debugaccess : out std_logic; -- debugaccess
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component niosii_system_generic_tristate_controller_0_uas_translator;
component niosii_system_jtag_uart_0_avalon_jtag_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(0 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_chipselect : out std_logic; -- chipselect
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component niosii_system_jtag_uart_0_avalon_jtag_slave_translator;
component niosii_system_sysid_qsys_0_control_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(0 downto 0); -- address
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component niosii_system_sysid_qsys_0_control_slave_translator;
component niosii_system_green_leds_s1_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(1 downto 0); -- address
av_write : out std_logic; -- write
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_chipselect : out std_logic; -- chipselect
av_read : out std_logic; -- read
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component niosii_system_green_leds_s1_translator;
component niosii_system_switches_s1_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(1 downto 0); -- address
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component niosii_system_switches_s1_translator;
component niosii_system_altpll_0_pll_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(1 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component niosii_system_altpll_0_pll_slave_translator;
component niosii_system_timer_0_s1_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(2 downto 0); -- address
av_write : out std_logic; -- write
av_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(15 downto 0); -- writedata
av_chipselect : out std_logic; -- chipselect
av_read : out std_logic; -- read
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component niosii_system_timer_0_s1_translator;
component niosii_system_usb_0_avalon_usb_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(1 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(15 downto 0); -- writedata
av_chipselect : out std_logic; -- chipselect
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component niosii_system_usb_0_avalon_usb_slave_translator;
component niosii_system_rs232_0_avalon_rs232_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(0 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_chipselect : out std_logic; -- chipselect
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component niosii_system_rs232_0_avalon_rs232_slave_translator;
component niosii_system_rst_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
reset_in1 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_in3 : in std_logic := 'X'; -- reset
reset_in4 : in std_logic := 'X'; -- reset
reset_in5 : in std_logic := 'X'; -- reset
reset_in6 : in std_logic := 'X'; -- reset
reset_in7 : in std_logic := 'X'; -- reset
reset_in8 : in std_logic := 'X'; -- reset
reset_in9 : in std_logic := 'X'; -- reset
reset_in10 : in std_logic := 'X'; -- reset
reset_in11 : in std_logic := 'X'; -- reset
reset_in12 : in std_logic := 'X'; -- reset
reset_in13 : in std_logic := 'X'; -- reset
reset_in14 : in std_logic := 'X'; -- reset
reset_in15 : in std_logic := 'X' -- reset
);
end component niosii_system_rst_controller;
component niosii_system_rst_controller_001 is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
reset_in1 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_in3 : in std_logic := 'X'; -- reset
reset_in4 : in std_logic := 'X'; -- reset
reset_in5 : in std_logic := 'X'; -- reset
reset_in6 : in std_logic := 'X'; -- reset
reset_in7 : in std_logic := 'X'; -- reset
reset_in8 : in std_logic := 'X'; -- reset
reset_in9 : in std_logic := 'X'; -- reset
reset_in10 : in std_logic := 'X'; -- reset
reset_in11 : in std_logic := 'X'; -- reset
reset_in12 : in std_logic := 'X'; -- reset
reset_in13 : in std_logic := 'X'; -- reset
reset_in14 : in std_logic := 'X'; -- reset
reset_in15 : in std_logic := 'X' -- reset
);
end component niosii_system_rst_controller_001;
signal altpll_0_c1_clk : std_logic; -- altpll_0:c1 -> [addr_router:clk, addr_router_001:clk, burst_adapter:clk, burst_adapter_001:clk, burst_adapter_002:clk, cmd_xbar_demux:clk, cmd_xbar_demux_001:clk, cmd_xbar_mux:clk, cmd_xbar_mux_001:clk, cmd_xbar_mux_002:clk, cmd_xbar_mux_003:clk, cmd_xbar_mux_004:clk, crosser:in_clk, crosser_001:out_clk, generic_tristate_controller_0:clk_clk, generic_tristate_controller_0_uas_translator:clk, generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:clk, generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo:clk, generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, green_leds:clk, green_leds_s1_translator:clk, green_leds_s1_translator_avalon_universal_slave_0_agent:clk, green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, id_router:clk, id_router_001:clk, id_router_002:clk, id_router_003:clk, id_router_004:clk, id_router_005:clk, id_router_006:clk, id_router_007:clk, id_router_008:clk, id_router_010:clk, id_router_011:clk, id_router_012:clk, irq_mapper:clk, jtag_uart_0:clk, jtag_uart_0_avalon_jtag_slave_translator:clk, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:clk, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, nios2_qsys_0:clk, nios2_qsys_0_data_master_translator:clk, nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:clk, nios2_qsys_0_instruction_master_translator:clk, nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:clk, nios2_qsys_0_jtag_debug_module_translator:clk, nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:clk, nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, onchip_memory2_0:clk, onchip_memory2_0_s1_translator:clk, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:clk, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, rs232_0:clk, rs232_0_avalon_rs232_slave_translator:clk, rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:clk, rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, rsp_xbar_demux:clk, rsp_xbar_demux_001:clk, rsp_xbar_demux_002:clk, rsp_xbar_demux_003:clk, rsp_xbar_demux_004:clk, rsp_xbar_demux_005:clk, rsp_xbar_demux_006:clk, rsp_xbar_demux_007:clk, rsp_xbar_demux_008:clk, rsp_xbar_demux_010:clk, rsp_xbar_demux_011:clk, rsp_xbar_demux_012:clk, rsp_xbar_mux:clk, rsp_xbar_mux_001:clk, rst_controller:clk, sdram_0:clk, sdram_0_s1_translator:clk, sdram_0_s1_translator_avalon_universal_slave_0_agent:clk, sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:clk, sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, sram_0:clk, sram_0_avalon_sram_slave_translator:clk, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:clk, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:clk, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, switches:clk, switches_s1_translator:clk, switches_s1_translator_avalon_universal_slave_0_agent:clk, switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, sysid_qsys_0:clock, sysid_qsys_0_control_slave_translator:clk, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:clk, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, timer_0:clk, timer_0_s1_translator:clk, timer_0_s1_translator_avalon_universal_slave_0_agent:clk, timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, tristate_conduit_bridge_0:clk, tristate_conduit_pin_sharer_0:clk_clk, usb_0:clk, usb_0_avalon_usb_slave_translator:clk, usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:clk, usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, width_adapter:clk, width_adapter_001:clk, width_adapter_002:clk, width_adapter_003:clk, width_adapter_004:clk, width_adapter_005:clk]
signal generic_tristate_controller_0_tcm_chipselect_n_out : std_logic; -- generic_tristate_controller_0:tcm_chipselect_n_out -> tristate_conduit_pin_sharer_0:tcs0_chipselect_n_out
signal generic_tristate_controller_0_tcm_grant : std_logic; -- tristate_conduit_pin_sharer_0:tcs0_grant -> generic_tristate_controller_0:tcm_grant
signal generic_tristate_controller_0_tcm_data_outen : std_logic; -- generic_tristate_controller_0:tcm_data_outen -> tristate_conduit_pin_sharer_0:tcs0_data_outen
signal generic_tristate_controller_0_tcm_byteenable_out : std_logic; -- generic_tristate_controller_0:tcm_byteenable_out -> tristate_conduit_pin_sharer_0:tcs0_byteenable_out
signal generic_tristate_controller_0_tcm_request : std_logic; -- generic_tristate_controller_0:tcm_request -> tristate_conduit_pin_sharer_0:tcs0_request
signal generic_tristate_controller_0_tcm_begintransfer_out : std_logic; -- generic_tristate_controller_0:tcm_begintransfer_out -> tristate_conduit_pin_sharer_0:tcs0_begintransfer_out
signal generic_tristate_controller_0_tcm_data_out : std_logic_vector(7 downto 0); -- generic_tristate_controller_0:tcm_data_out -> tristate_conduit_pin_sharer_0:tcs0_data_out
signal generic_tristate_controller_0_tcm_write_n_out : std_logic; -- generic_tristate_controller_0:tcm_write_n_out -> tristate_conduit_pin_sharer_0:tcs0_write_n_out
signal generic_tristate_controller_0_tcm_address_out : std_logic_vector(21 downto 0); -- generic_tristate_controller_0:tcm_address_out -> tristate_conduit_pin_sharer_0:tcs0_address_out
signal generic_tristate_controller_0_tcm_data_in : std_logic_vector(7 downto 0); -- tristate_conduit_pin_sharer_0:tcs0_data_in -> generic_tristate_controller_0:tcm_data_in
signal generic_tristate_controller_0_tcm_read_n_out : std_logic; -- generic_tristate_controller_0:tcm_read_n_out -> tristate_conduit_pin_sharer_0:tcs0_read_n_out
signal tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_read_n_out_out : std_logic_vector(0 downto 0); -- tristate_conduit_pin_sharer_0:generic_tristate_controller_0_tcm_read_n_out -> tristate_conduit_bridge_0:tcs_generic_tristate_controller_0_tcm_read_n_out
signal tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_byteenable_out_out : std_logic_vector(0 downto 0); -- tristate_conduit_pin_sharer_0:generic_tristate_controller_0_tcm_byteenable_out -> tristate_conduit_bridge_0:tcs_generic_tristate_controller_0_tcm_byteenable_out
signal tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_begintransfer_out_out : std_logic_vector(0 downto 0); -- tristate_conduit_pin_sharer_0:generic_tristate_controller_0_tcm_begintransfer_out -> tristate_conduit_bridge_0:tcs_generic_tristate_controller_0_tcm_begintransfer_out
signal tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_write_n_out_out : std_logic_vector(0 downto 0); -- tristate_conduit_pin_sharer_0:generic_tristate_controller_0_tcm_write_n_out -> tristate_conduit_bridge_0:tcs_generic_tristate_controller_0_tcm_write_n_out
signal tristate_conduit_pin_sharer_0_tcm_grant : std_logic; -- tristate_conduit_bridge_0:grant -> tristate_conduit_pin_sharer_0:grant
signal tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_data_out_in : std_logic_vector(7 downto 0); -- tristate_conduit_bridge_0:tcs_generic_tristate_controller_0_tcm_data_in -> tristate_conduit_pin_sharer_0:generic_tristate_controller_0_tcm_data_in
signal tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_data_out_out : std_logic_vector(7 downto 0); -- tristate_conduit_pin_sharer_0:generic_tristate_controller_0_tcm_data_out -> tristate_conduit_bridge_0:tcs_generic_tristate_controller_0_tcm_data_out
signal tristate_conduit_pin_sharer_0_tcm_request : std_logic; -- tristate_conduit_pin_sharer_0:request -> tristate_conduit_bridge_0:request
signal tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_chipselect_n_out_out : std_logic_vector(0 downto 0); -- tristate_conduit_pin_sharer_0:generic_tristate_controller_0_tcm_chipselect_n_out -> tristate_conduit_bridge_0:tcs_generic_tristate_controller_0_tcm_chipselect_n_out
signal tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_data_out_outen : std_logic; -- tristate_conduit_pin_sharer_0:generic_tristate_controller_0_tcm_data_outen -> tristate_conduit_bridge_0:tcs_generic_tristate_controller_0_tcm_data_outen
signal tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_address_out_out : std_logic_vector(21 downto 0); -- tristate_conduit_pin_sharer_0:generic_tristate_controller_0_tcm_address_out -> tristate_conduit_bridge_0:tcs_generic_tristate_controller_0_tcm_address_out
signal nios2_qsys_0_instruction_master_waitrequest : std_logic; -- nios2_qsys_0_instruction_master_translator:av_waitrequest -> nios2_qsys_0:i_waitrequest
signal nios2_qsys_0_instruction_master_address : std_logic_vector(24 downto 0); -- nios2_qsys_0:i_address -> nios2_qsys_0_instruction_master_translator:av_address
signal nios2_qsys_0_instruction_master_read : std_logic; -- nios2_qsys_0:i_read -> nios2_qsys_0_instruction_master_translator:av_read
signal nios2_qsys_0_instruction_master_readdata : std_logic_vector(31 downto 0); -- nios2_qsys_0_instruction_master_translator:av_readdata -> nios2_qsys_0:i_readdata
signal nios2_qsys_0_data_master_waitrequest : std_logic; -- nios2_qsys_0_data_master_translator:av_waitrequest -> nios2_qsys_0:d_waitrequest
signal nios2_qsys_0_data_master_writedata : std_logic_vector(31 downto 0); -- nios2_qsys_0:d_writedata -> nios2_qsys_0_data_master_translator:av_writedata
signal nios2_qsys_0_data_master_address : std_logic_vector(24 downto 0); -- nios2_qsys_0:d_address -> nios2_qsys_0_data_master_translator:av_address
signal nios2_qsys_0_data_master_write : std_logic; -- nios2_qsys_0:d_write -> nios2_qsys_0_data_master_translator:av_write
signal nios2_qsys_0_data_master_read : std_logic; -- nios2_qsys_0:d_read -> nios2_qsys_0_data_master_translator:av_read
signal nios2_qsys_0_data_master_readdata : std_logic_vector(31 downto 0); -- nios2_qsys_0_data_master_translator:av_readdata -> nios2_qsys_0:d_readdata
signal nios2_qsys_0_data_master_debugaccess : std_logic; -- nios2_qsys_0:jtag_debug_module_debugaccess_to_roms -> nios2_qsys_0_data_master_translator:av_debugaccess
signal nios2_qsys_0_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2_qsys_0:d_byteenable -> nios2_qsys_0_data_master_translator:av_byteenable
signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest : std_logic; -- nios2_qsys_0:jtag_debug_module_waitrequest -> nios2_qsys_0_jtag_debug_module_translator:av_waitrequest
signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- nios2_qsys_0_jtag_debug_module_translator:av_writedata -> nios2_qsys_0:jtag_debug_module_writedata
signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_address : std_logic_vector(8 downto 0); -- nios2_qsys_0_jtag_debug_module_translator:av_address -> nios2_qsys_0:jtag_debug_module_address
signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_write : std_logic; -- nios2_qsys_0_jtag_debug_module_translator:av_write -> nios2_qsys_0:jtag_debug_module_write
signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_read : std_logic; -- nios2_qsys_0_jtag_debug_module_translator:av_read -> nios2_qsys_0:jtag_debug_module_read
signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- nios2_qsys_0:jtag_debug_module_readdata -> nios2_qsys_0_jtag_debug_module_translator:av_readdata
signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess : std_logic; -- nios2_qsys_0_jtag_debug_module_translator:av_debugaccess -> nios2_qsys_0:jtag_debug_module_debugaccess
signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- nios2_qsys_0_jtag_debug_module_translator:av_byteenable -> nios2_qsys_0:jtag_debug_module_byteenable
signal sdram_0_s1_translator_avalon_anti_slave_0_waitrequest : std_logic; -- sdram_0:za_waitrequest -> sdram_0_s1_translator:av_waitrequest
signal sdram_0_s1_translator_avalon_anti_slave_0_writedata : std_logic_vector(15 downto 0); -- sdram_0_s1_translator:av_writedata -> sdram_0:az_data
signal sdram_0_s1_translator_avalon_anti_slave_0_address : std_logic_vector(21 downto 0); -- sdram_0_s1_translator:av_address -> sdram_0:az_addr
signal sdram_0_s1_translator_avalon_anti_slave_0_chipselect : std_logic; -- sdram_0_s1_translator:av_chipselect -> sdram_0:az_cs
signal sdram_0_s1_translator_avalon_anti_slave_0_write : std_logic; -- sdram_0_s1_translator:av_write -> sdram_0_s1_translator_avalon_anti_slave_0_write:in
signal sdram_0_s1_translator_avalon_anti_slave_0_read : std_logic; -- sdram_0_s1_translator:av_read -> sdram_0_s1_translator_avalon_anti_slave_0_read:in
signal sdram_0_s1_translator_avalon_anti_slave_0_readdata : std_logic_vector(15 downto 0); -- sdram_0:za_data -> sdram_0_s1_translator:av_readdata
signal sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid : std_logic; -- sdram_0:za_valid -> sdram_0_s1_translator:av_readdatavalid
signal sdram_0_s1_translator_avalon_anti_slave_0_byteenable : std_logic_vector(1 downto 0); -- sdram_0_s1_translator:av_byteenable -> sdram_0_s1_translator_avalon_anti_slave_0_byteenable:in
signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- onchip_memory2_0_s1_translator:av_writedata -> onchip_memory2_0:writedata
signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_address : std_logic_vector(11 downto 0); -- onchip_memory2_0_s1_translator:av_address -> onchip_memory2_0:address
signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_chipselect : std_logic; -- onchip_memory2_0_s1_translator:av_chipselect -> onchip_memory2_0:chipselect
signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_clken : std_logic; -- onchip_memory2_0_s1_translator:av_clken -> onchip_memory2_0:clken
signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_write : std_logic; -- onchip_memory2_0_s1_translator:av_write -> onchip_memory2_0:write
signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0:readdata -> onchip_memory2_0_s1_translator:av_readdata
signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- onchip_memory2_0_s1_translator:av_byteenable -> onchip_memory2_0:byteenable
signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(15 downto 0); -- sram_0_avalon_sram_slave_translator:av_writedata -> sram_0:writedata
signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_address : std_logic_vector(17 downto 0); -- sram_0_avalon_sram_slave_translator:av_address -> sram_0:address
signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_write : std_logic; -- sram_0_avalon_sram_slave_translator:av_write -> sram_0:write
signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_read : std_logic; -- sram_0_avalon_sram_slave_translator:av_read -> sram_0:read
signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(15 downto 0); -- sram_0:readdata -> sram_0_avalon_sram_slave_translator:av_readdata
signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdatavalid : std_logic; -- sram_0:readdatavalid -> sram_0_avalon_sram_slave_translator:av_readdatavalid
signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable : std_logic_vector(1 downto 0); -- sram_0_avalon_sram_slave_translator:av_byteenable -> sram_0:byteenable
signal generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_waitrequest : std_logic; -- generic_tristate_controller_0:uas_waitrequest -> generic_tristate_controller_0_uas_translator:av_waitrequest
signal generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_burstcount : std_logic_vector(0 downto 0); -- generic_tristate_controller_0_uas_translator:av_burstcount -> generic_tristate_controller_0:uas_burstcount
signal generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_writedata : std_logic_vector(7 downto 0); -- generic_tristate_controller_0_uas_translator:av_writedata -> generic_tristate_controller_0:uas_writedata
signal generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_address : std_logic_vector(21 downto 0); -- generic_tristate_controller_0_uas_translator:av_address -> generic_tristate_controller_0:uas_address
signal generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_lock : std_logic; -- generic_tristate_controller_0_uas_translator:av_lock -> generic_tristate_controller_0:uas_lock
signal generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_write : std_logic; -- generic_tristate_controller_0_uas_translator:av_write -> generic_tristate_controller_0:uas_write
signal generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_read : std_logic; -- generic_tristate_controller_0_uas_translator:av_read -> generic_tristate_controller_0:uas_read
signal generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_readdata : std_logic_vector(7 downto 0); -- generic_tristate_controller_0:uas_readdata -> generic_tristate_controller_0_uas_translator:av_readdata
signal generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_debugaccess : std_logic; -- generic_tristate_controller_0_uas_translator:av_debugaccess -> generic_tristate_controller_0:uas_debugaccess
signal generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_readdatavalid : std_logic; -- generic_tristate_controller_0:uas_readdatavalid -> generic_tristate_controller_0_uas_translator:av_readdatavalid
signal generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_byteenable : std_logic_vector(0 downto 0); -- generic_tristate_controller_0_uas_translator:av_byteenable -> generic_tristate_controller_0:uas_byteenable
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest : std_logic; -- jtag_uart_0:av_waitrequest -> jtag_uart_0_avalon_jtag_slave_translator:av_waitrequest
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator:av_writedata -> jtag_uart_0:av_writedata
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address : std_logic_vector(0 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator:av_address -> jtag_uart_0:av_address
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator:av_chipselect -> jtag_uart_0:av_chipselect
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator:av_write -> jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write:in
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator:av_read -> jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read:in
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- jtag_uart_0:av_readdata -> jtag_uart_0_avalon_jtag_slave_translator:av_readdata
signal sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_address : std_logic_vector(0 downto 0); -- sysid_qsys_0_control_slave_translator:av_address -> sysid_qsys_0:address
signal sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- sysid_qsys_0:readdata -> sysid_qsys_0_control_slave_translator:av_readdata
signal green_leds_s1_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- green_leds_s1_translator:av_writedata -> green_leds:writedata
signal green_leds_s1_translator_avalon_anti_slave_0_address : std_logic_vector(1 downto 0); -- green_leds_s1_translator:av_address -> green_leds:address
signal green_leds_s1_translator_avalon_anti_slave_0_chipselect : std_logic; -- green_leds_s1_translator:av_chipselect -> green_leds:chipselect
signal green_leds_s1_translator_avalon_anti_slave_0_write : std_logic; -- green_leds_s1_translator:av_write -> green_leds_s1_translator_avalon_anti_slave_0_write:in
signal green_leds_s1_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- green_leds:readdata -> green_leds_s1_translator:av_readdata
signal switches_s1_translator_avalon_anti_slave_0_address : std_logic_vector(1 downto 0); -- switches_s1_translator:av_address -> switches:address
signal switches_s1_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- switches:readdata -> switches_s1_translator:av_readdata
signal altpll_0_pll_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- altpll_0_pll_slave_translator:av_writedata -> altpll_0:writedata
signal altpll_0_pll_slave_translator_avalon_anti_slave_0_address : std_logic_vector(1 downto 0); -- altpll_0_pll_slave_translator:av_address -> altpll_0:address
signal altpll_0_pll_slave_translator_avalon_anti_slave_0_write : std_logic; -- altpll_0_pll_slave_translator:av_write -> altpll_0:write
signal altpll_0_pll_slave_translator_avalon_anti_slave_0_read : std_logic; -- altpll_0_pll_slave_translator:av_read -> altpll_0:read
signal altpll_0_pll_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- altpll_0:readdata -> altpll_0_pll_slave_translator:av_readdata
signal timer_0_s1_translator_avalon_anti_slave_0_writedata : std_logic_vector(15 downto 0); -- timer_0_s1_translator:av_writedata -> timer_0:writedata
signal timer_0_s1_translator_avalon_anti_slave_0_address : std_logic_vector(2 downto 0); -- timer_0_s1_translator:av_address -> timer_0:address
signal timer_0_s1_translator_avalon_anti_slave_0_chipselect : std_logic; -- timer_0_s1_translator:av_chipselect -> timer_0:chipselect
signal timer_0_s1_translator_avalon_anti_slave_0_write : std_logic; -- timer_0_s1_translator:av_write -> timer_0_s1_translator_avalon_anti_slave_0_write:in
signal timer_0_s1_translator_avalon_anti_slave_0_readdata : std_logic_vector(15 downto 0); -- timer_0:readdata -> timer_0_s1_translator:av_readdata
signal usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(15 downto 0); -- usb_0_avalon_usb_slave_translator:av_writedata -> usb_0:writedata
signal usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_address : std_logic_vector(1 downto 0); -- usb_0_avalon_usb_slave_translator:av_address -> usb_0:address
signal usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_chipselect : std_logic; -- usb_0_avalon_usb_slave_translator:av_chipselect -> usb_0:chipselect
signal usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_write : std_logic; -- usb_0_avalon_usb_slave_translator:av_write -> usb_0:write
signal usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_read : std_logic; -- usb_0_avalon_usb_slave_translator:av_read -> usb_0:read
signal usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(15 downto 0); -- usb_0:readdata -> usb_0_avalon_usb_slave_translator:av_readdata
signal rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- rs232_0_avalon_rs232_slave_translator:av_writedata -> rs232_0:writedata
signal rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_address : std_logic_vector(0 downto 0); -- rs232_0_avalon_rs232_slave_translator:av_address -> rs232_0:address
signal rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_chipselect : std_logic; -- rs232_0_avalon_rs232_slave_translator:av_chipselect -> rs232_0:chipselect
signal rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_write : std_logic; -- rs232_0_avalon_rs232_slave_translator:av_write -> rs232_0:write
signal rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_read : std_logic; -- rs232_0_avalon_rs232_slave_translator:av_read -> rs232_0:read
signal rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- rs232_0:readdata -> rs232_0_avalon_rs232_slave_translator:av_readdata
signal rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- rs232_0_avalon_rs232_slave_translator:av_byteenable -> rs232_0:byteenable
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest : std_logic; -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_qsys_0_instruction_master_translator:uav_waitrequest
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount : std_logic_vector(2 downto 0); -- nios2_qsys_0_instruction_master_translator:uav_burstcount -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata : std_logic_vector(31 downto 0); -- nios2_qsys_0_instruction_master_translator:uav_writedata -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_writedata
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address : std_logic_vector(24 downto 0); -- nios2_qsys_0_instruction_master_translator:uav_address -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_address
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock : std_logic; -- nios2_qsys_0_instruction_master_translator:uav_lock -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_lock
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write : std_logic; -- nios2_qsys_0_instruction_master_translator:uav_write -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_write
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read : std_logic; -- nios2_qsys_0_instruction_master_translator:uav_read -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_read
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata : std_logic_vector(31 downto 0); -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_qsys_0_instruction_master_translator:uav_readdata
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess : std_logic; -- nios2_qsys_0_instruction_master_translator:uav_debugaccess -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable : std_logic_vector(3 downto 0); -- nios2_qsys_0_instruction_master_translator:uav_byteenable -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid : std_logic; -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_qsys_0_instruction_master_translator:uav_readdatavalid
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest : std_logic; -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_qsys_0_data_master_translator:uav_waitrequest
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount : std_logic_vector(2 downto 0); -- nios2_qsys_0_data_master_translator:uav_burstcount -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_burstcount
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata : std_logic_vector(31 downto 0); -- nios2_qsys_0_data_master_translator:uav_writedata -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_writedata
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_address : std_logic_vector(24 downto 0); -- nios2_qsys_0_data_master_translator:uav_address -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_address
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock : std_logic; -- nios2_qsys_0_data_master_translator:uav_lock -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_lock
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_write : std_logic; -- nios2_qsys_0_data_master_translator:uav_write -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_write
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_read : std_logic; -- nios2_qsys_0_data_master_translator:uav_read -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_read
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata : std_logic_vector(31 downto 0); -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_qsys_0_data_master_translator:uav_readdata
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess : std_logic; -- nios2_qsys_0_data_master_translator:uav_debugaccess -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_debugaccess
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable : std_logic_vector(3 downto 0); -- nios2_qsys_0_data_master_translator:uav_byteenable -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_byteenable
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid : std_logic; -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_qsys_0_data_master_translator:uav_readdatavalid
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- nios2_qsys_0_jtag_debug_module_translator:uav_waitrequest -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_burstcount -> nios2_qsys_0_jtag_debug_module_translator:uav_burstcount
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_writedata -> nios2_qsys_0_jtag_debug_module_translator:uav_writedata
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_address -> nios2_qsys_0_jtag_debug_module_translator:uav_address
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_write -> nios2_qsys_0_jtag_debug_module_translator:uav_write
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_lock -> nios2_qsys_0_jtag_debug_module_translator:uav_lock
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_read -> nios2_qsys_0_jtag_debug_module_translator:uav_read
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- nios2_qsys_0_jtag_debug_module_translator:uav_readdata -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdata
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- nios2_qsys_0_jtag_debug_module_translator:uav_readdatavalid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_debugaccess -> nios2_qsys_0_jtag_debug_module_translator:uav_debugaccess
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_byteenable -> nios2_qsys_0_jtag_debug_module_translator:uav_byteenable
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_valid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_data -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_ready
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_data
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_ready -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- sdram_0_s1_translator:uav_waitrequest -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(1 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> sdram_0_s1_translator:uav_burstcount
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(15 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> sdram_0_s1_translator:uav_writedata
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> sdram_0_s1_translator:uav_address
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> sdram_0_s1_translator:uav_write
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> sdram_0_s1_translator:uav_lock
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> sdram_0_s1_translator:uav_read
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(15 downto 0); -- sdram_0_s1_translator:uav_readdata -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- sdram_0_s1_translator:uav_readdatavalid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sdram_0_s1_translator:uav_debugaccess
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(1 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> sdram_0_s1_translator:uav_byteenable
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(82 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(82 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(17 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data : std_logic_vector(17 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- onchip_memory2_0_s1_translator:uav_waitrequest -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> onchip_memory2_0_s1_translator:uav_burstcount
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> onchip_memory2_0_s1_translator:uav_writedata
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> onchip_memory2_0_s1_translator:uav_address
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> onchip_memory2_0_s1_translator:uav_write
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> onchip_memory2_0_s1_translator:uav_lock
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> onchip_memory2_0_s1_translator:uav_read
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0_s1_translator:uav_readdata -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- onchip_memory2_0_s1_translator:uav_readdatavalid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> onchip_memory2_0_s1_translator:uav_debugaccess
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> onchip_memory2_0_s1_translator:uav_byteenable
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- sram_0_avalon_sram_slave_translator:uav_waitrequest -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(1 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> sram_0_avalon_sram_slave_translator:uav_burstcount
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(15 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> sram_0_avalon_sram_slave_translator:uav_writedata
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_address -> sram_0_avalon_sram_slave_translator:uav_address
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_write -> sram_0_avalon_sram_slave_translator:uav_write
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_lock -> sram_0_avalon_sram_slave_translator:uav_lock
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_read -> sram_0_avalon_sram_slave_translator:uav_read
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(15 downto 0); -- sram_0_avalon_sram_slave_translator:uav_readdata -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- sram_0_avalon_sram_slave_translator:uav_readdatavalid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sram_0_avalon_sram_slave_translator:uav_debugaccess
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(1 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> sram_0_avalon_sram_slave_translator:uav_byteenable
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(82 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(82 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(17 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data : std_logic_vector(17 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- generic_tristate_controller_0_uas_translator:uav_waitrequest -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(0 downto 0); -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:m0_burstcount -> generic_tristate_controller_0_uas_translator:uav_burstcount
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(7 downto 0); -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:m0_writedata -> generic_tristate_controller_0_uas_translator:uav_writedata
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:m0_address -> generic_tristate_controller_0_uas_translator:uav_address
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:m0_write -> generic_tristate_controller_0_uas_translator:uav_write
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:m0_lock -> generic_tristate_controller_0_uas_translator:uav_lock
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:m0_read -> generic_tristate_controller_0_uas_translator:uav_read
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(7 downto 0); -- generic_tristate_controller_0_uas_translator:uav_readdata -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:m0_readdata
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- generic_tristate_controller_0_uas_translator:uav_readdatavalid -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:m0_debugaccess -> generic_tristate_controller_0_uas_translator:uav_debugaccess
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(0 downto 0); -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:m0_byteenable -> generic_tristate_controller_0_uas_translator:uav_byteenable
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rf_source_valid -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(73 downto 0); -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rf_source_data -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rf_source_ready
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(73 downto 0); -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rf_sink_data
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rf_sink_ready -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(9 downto 0); -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data : std_logic_vector(9 downto 0); -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> jtag_uart_0_avalon_jtag_slave_translator:uav_burstcount
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> jtag_uart_0_avalon_jtag_slave_translator:uav_writedata
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_address -> jtag_uart_0_avalon_jtag_slave_translator:uav_address
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_write -> jtag_uart_0_avalon_jtag_slave_translator:uav_write
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_lock -> jtag_uart_0_avalon_jtag_slave_translator:uav_lock
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_read -> jtag_uart_0_avalon_jtag_slave_translator:uav_read
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> jtag_uart_0_avalon_jtag_slave_translator:uav_debugaccess
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> jtag_uart_0_avalon_jtag_slave_translator:uav_byteenable
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- sysid_qsys_0_control_slave_translator:uav_waitrequest -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> sysid_qsys_0_control_slave_translator:uav_burstcount
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> sysid_qsys_0_control_slave_translator:uav_writedata
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> sysid_qsys_0_control_slave_translator:uav_address
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> sysid_qsys_0_control_slave_translator:uav_write
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> sysid_qsys_0_control_slave_translator:uav_lock
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> sysid_qsys_0_control_slave_translator:uav_read
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- sysid_qsys_0_control_slave_translator:uav_readdata -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- sysid_qsys_0_control_slave_translator:uav_readdatavalid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sysid_qsys_0_control_slave_translator:uav_debugaccess
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> sysid_qsys_0_control_slave_translator:uav_byteenable
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- green_leds_s1_translator:uav_waitrequest -> green_leds_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> green_leds_s1_translator:uav_burstcount
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> green_leds_s1_translator:uav_writedata
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_address -> green_leds_s1_translator:uav_address
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_write -> green_leds_s1_translator:uav_write
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_lock -> green_leds_s1_translator:uav_lock
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_read -> green_leds_s1_translator:uav_read
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- green_leds_s1_translator:uav_readdata -> green_leds_s1_translator_avalon_universal_slave_0_agent:m0_readdata
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- green_leds_s1_translator:uav_readdatavalid -> green_leds_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> green_leds_s1_translator:uav_debugaccess
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> green_leds_s1_translator:uav_byteenable
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- switches_s1_translator:uav_waitrequest -> switches_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- switches_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> switches_s1_translator:uav_burstcount
signal switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- switches_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> switches_s1_translator:uav_writedata
signal switches_s1_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- switches_s1_translator_avalon_universal_slave_0_agent:m0_address -> switches_s1_translator:uav_address
signal switches_s1_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:m0_write -> switches_s1_translator:uav_write
signal switches_s1_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:m0_lock -> switches_s1_translator:uav_lock
signal switches_s1_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:m0_read -> switches_s1_translator:uav_read
signal switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- switches_s1_translator:uav_readdata -> switches_s1_translator_avalon_universal_slave_0_agent:m0_readdata
signal switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- switches_s1_translator:uav_readdatavalid -> switches_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> switches_s1_translator:uav_debugaccess
signal switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- switches_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> switches_s1_translator:uav_byteenable
signal switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- switches_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
signal switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
signal switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- altpll_0_pll_slave_translator:uav_waitrequest -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> altpll_0_pll_slave_translator:uav_burstcount
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> altpll_0_pll_slave_translator:uav_writedata
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_address -> altpll_0_pll_slave_translator:uav_address
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_write -> altpll_0_pll_slave_translator:uav_write
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_lock -> altpll_0_pll_slave_translator:uav_lock
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_read -> altpll_0_pll_slave_translator:uav_read
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- altpll_0_pll_slave_translator:uav_readdata -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- altpll_0_pll_slave_translator:uav_readdatavalid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> altpll_0_pll_slave_translator:uav_debugaccess
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> altpll_0_pll_slave_translator:uav_byteenable
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data : std_logic_vector(33 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- timer_0_s1_translator:uav_waitrequest -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> timer_0_s1_translator:uav_burstcount
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> timer_0_s1_translator:uav_writedata
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> timer_0_s1_translator:uav_address
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> timer_0_s1_translator:uav_write
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> timer_0_s1_translator:uav_lock
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> timer_0_s1_translator:uav_read
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- timer_0_s1_translator:uav_readdata -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- timer_0_s1_translator:uav_readdatavalid -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> timer_0_s1_translator:uav_debugaccess
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> timer_0_s1_translator:uav_byteenable
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- usb_0_avalon_usb_slave_translator:uav_waitrequest -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> usb_0_avalon_usb_slave_translator:uav_burstcount
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> usb_0_avalon_usb_slave_translator:uav_writedata
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_address -> usb_0_avalon_usb_slave_translator:uav_address
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_write -> usb_0_avalon_usb_slave_translator:uav_write
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_lock -> usb_0_avalon_usb_slave_translator:uav_lock
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_read -> usb_0_avalon_usb_slave_translator:uav_read
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- usb_0_avalon_usb_slave_translator:uav_readdata -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- usb_0_avalon_usb_slave_translator:uav_readdatavalid -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> usb_0_avalon_usb_slave_translator:uav_debugaccess
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> usb_0_avalon_usb_slave_translator:uav_byteenable
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- rs232_0_avalon_rs232_slave_translator:uav_waitrequest -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> rs232_0_avalon_rs232_slave_translator:uav_burstcount
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> rs232_0_avalon_rs232_slave_translator:uav_writedata
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_address -> rs232_0_avalon_rs232_slave_translator:uav_address
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_write -> rs232_0_avalon_rs232_slave_translator:uav_write
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_lock -> rs232_0_avalon_rs232_slave_translator:uav_lock
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_read -> rs232_0_avalon_rs232_slave_translator:uav_read
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- rs232_0_avalon_rs232_slave_translator:uav_readdata -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- rs232_0_avalon_rs232_slave_translator:uav_readdatavalid -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> rs232_0_avalon_rs232_slave_translator:uav_debugaccess
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> rs232_0_avalon_rs232_slave_translator:uav_byteenable
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket : std_logic; -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_valid : std_logic; -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket : std_logic; -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_data : std_logic_vector(99 downto 0); -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_ready : std_logic; -- addr_router:sink_ready -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_ready
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket : std_logic; -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_valid : std_logic; -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket : std_logic; -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_data : std_logic_vector(99 downto 0); -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_ready : std_logic; -- addr_router_001:sink_ready -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_ready
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router:sink_ready -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_ready
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(81 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_001:sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_ready
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_002:sink_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_ready
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(81 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_003:sink_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(72 downto 0); -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_004:sink_ready -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rp_ready
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_005:sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_006:sink_endofpacket
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_006:sink_valid
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_006:sink_startofpacket
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_006:sink_data
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_006:sink_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_007:sink_endofpacket
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_007:sink_valid
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_007:sink_startofpacket
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_007:sink_data
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_007:sink_ready -> green_leds_s1_translator_avalon_universal_slave_0_agent:rp_ready
signal switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_008:sink_endofpacket
signal switches_s1_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_008:sink_valid
signal switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_008:sink_startofpacket
signal switches_s1_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- switches_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_008:sink_data
signal switches_s1_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_008:sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rp_ready
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_009:sink_endofpacket
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_009:sink_valid
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_009:sink_startofpacket
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_009:sink_data
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_009:sink_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_010:sink_endofpacket
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_010:sink_valid
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_010:sink_startofpacket
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_010:sink_data
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_010:sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rp_ready
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_011:sink_endofpacket
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_011:sink_valid
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_011:sink_startofpacket
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_011:sink_data
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_011:sink_ready -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_012:sink_endofpacket
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_012:sink_valid
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_012:sink_startofpacket
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_012:sink_data
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_012:sink_ready -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal burst_adapter_source0_endofpacket : std_logic; -- burst_adapter:source0_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal burst_adapter_source0_valid : std_logic; -- burst_adapter:source0_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_valid
signal burst_adapter_source0_startofpacket : std_logic; -- burst_adapter:source0_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal burst_adapter_source0_data : std_logic_vector(81 downto 0); -- burst_adapter:source0_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_data
signal burst_adapter_source0_ready : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter:source0_ready
signal burst_adapter_source0_channel : std_logic_vector(12 downto 0); -- burst_adapter:source0_channel -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_channel
signal burst_adapter_001_source0_endofpacket : std_logic; -- burst_adapter_001:source0_endofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal burst_adapter_001_source0_valid : std_logic; -- burst_adapter_001:source0_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal burst_adapter_001_source0_startofpacket : std_logic; -- burst_adapter_001:source0_startofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal burst_adapter_001_source0_data : std_logic_vector(81 downto 0); -- burst_adapter_001:source0_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_data
signal burst_adapter_001_source0_ready : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter_001:source0_ready
signal burst_adapter_001_source0_channel : std_logic_vector(12 downto 0); -- burst_adapter_001:source0_channel -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal burst_adapter_002_source0_endofpacket : std_logic; -- burst_adapter_002:source0_endofpacket -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal burst_adapter_002_source0_valid : std_logic; -- burst_adapter_002:source0_valid -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:cp_valid
signal burst_adapter_002_source0_startofpacket : std_logic; -- burst_adapter_002:source0_startofpacket -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal burst_adapter_002_source0_data : std_logic_vector(72 downto 0); -- burst_adapter_002:source0_data -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:cp_data
signal burst_adapter_002_source0_ready : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter_002:source0_ready
signal burst_adapter_002_source0_channel : std_logic_vector(12 downto 0); -- burst_adapter_002:source0_channel -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:cp_channel
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [addr_router:reset, addr_router_001:reset, burst_adapter:reset, burst_adapter_001:reset, burst_adapter_002:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_mux:reset, cmd_xbar_mux_001:reset, cmd_xbar_mux_002:reset, cmd_xbar_mux_003:reset, cmd_xbar_mux_004:reset, crosser:in_reset, crosser_001:out_reset, generic_tristate_controller_0:reset_reset, generic_tristate_controller_0_uas_translator:reset, generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:reset, generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo:reset, generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, green_leds_s1_translator:reset, green_leds_s1_translator_avalon_universal_slave_0_agent:reset, green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_004:reset, id_router_005:reset, id_router_006:reset, id_router_007:reset, id_router_008:reset, id_router_010:reset, id_router_011:reset, id_router_012:reset, irq_mapper:reset, jtag_uart_0_avalon_jtag_slave_translator:reset, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:reset, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, nios2_qsys_0_data_master_translator:reset, nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:reset, nios2_qsys_0_instruction_master_translator:reset, nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:reset, nios2_qsys_0_jtag_debug_module_translator:reset, nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:reset, nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, onchip_memory2_0:reset, onchip_memory2_0_s1_translator:reset, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:reset, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rs232_0:reset, rs232_0_avalon_rs232_slave_translator:reset, rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:reset, rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_demux_006:reset, rsp_xbar_demux_007:reset, rsp_xbar_demux_008:reset, rsp_xbar_demux_010:reset, rsp_xbar_demux_011:reset, rsp_xbar_demux_012:reset, rsp_xbar_mux:reset, rsp_xbar_mux_001:reset, rst_controller_reset_out_reset:in, sdram_0_s1_translator:reset, sdram_0_s1_translator_avalon_universal_slave_0_agent:reset, sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:reset, sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sram_0:reset, sram_0_avalon_sram_slave_translator:reset, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:reset, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:reset, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, switches_s1_translator:reset, switches_s1_translator_avalon_universal_slave_0_agent:reset, switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sysid_qsys_0_control_slave_translator:reset, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:reset, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, timer_0_s1_translator:reset, timer_0_s1_translator_avalon_universal_slave_0_agent:reset, timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, tristate_conduit_bridge_0:reset, tristate_conduit_pin_sharer_0:reset_reset, usb_0:reset, usb_0_avalon_usb_slave_translator:reset, usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:reset, usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, width_adapter:reset, width_adapter_001:reset, width_adapter_002:reset, width_adapter_003:reset, width_adapter_004:reset, width_adapter_005:reset]
signal rst_controller_reset_out_reset_req : std_logic; -- rst_controller:reset_req -> onchip_memory2_0:reset_req
signal nios2_qsys_0_jtag_debug_module_reset_reset : std_logic; -- nios2_qsys_0:jtag_debug_module_resetrequest -> [rst_controller:reset_in1, rst_controller_001:reset_in1]
signal rst_controller_001_reset_out_reset : std_logic; -- rst_controller_001:reset_out -> [altpll_0:reset, altpll_0_pll_slave_translator:reset, altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:reset, altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:reset, altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, crosser:out_reset, crosser_001:in_reset, id_router_009:reset, rsp_xbar_demux_009:reset]
signal cmd_xbar_demux_src0_endofpacket : std_logic; -- cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket
signal cmd_xbar_demux_src0_valid : std_logic; -- cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid
signal cmd_xbar_demux_src0_startofpacket : std_logic; -- cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket
signal cmd_xbar_demux_src0_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data
signal cmd_xbar_demux_src0_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel
signal cmd_xbar_demux_src0_ready : std_logic; -- cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready
signal cmd_xbar_demux_src1_endofpacket : std_logic; -- cmd_xbar_demux:src1_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket
signal cmd_xbar_demux_src1_valid : std_logic; -- cmd_xbar_demux:src1_valid -> cmd_xbar_mux_001:sink0_valid
signal cmd_xbar_demux_src1_startofpacket : std_logic; -- cmd_xbar_demux:src1_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket
signal cmd_xbar_demux_src1_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux:src1_data -> cmd_xbar_mux_001:sink0_data
signal cmd_xbar_demux_src1_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux:src1_channel -> cmd_xbar_mux_001:sink0_channel
signal cmd_xbar_demux_src1_ready : std_logic; -- cmd_xbar_mux_001:sink0_ready -> cmd_xbar_demux:src1_ready
signal cmd_xbar_demux_src2_endofpacket : std_logic; -- cmd_xbar_demux:src2_endofpacket -> cmd_xbar_mux_002:sink0_endofpacket
signal cmd_xbar_demux_src2_valid : std_logic; -- cmd_xbar_demux:src2_valid -> cmd_xbar_mux_002:sink0_valid
signal cmd_xbar_demux_src2_startofpacket : std_logic; -- cmd_xbar_demux:src2_startofpacket -> cmd_xbar_mux_002:sink0_startofpacket
signal cmd_xbar_demux_src2_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux:src2_data -> cmd_xbar_mux_002:sink0_data
signal cmd_xbar_demux_src2_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux:src2_channel -> cmd_xbar_mux_002:sink0_channel
signal cmd_xbar_demux_src2_ready : std_logic; -- cmd_xbar_mux_002:sink0_ready -> cmd_xbar_demux:src2_ready
signal cmd_xbar_demux_src3_endofpacket : std_logic; -- cmd_xbar_demux:src3_endofpacket -> cmd_xbar_mux_003:sink0_endofpacket
signal cmd_xbar_demux_src3_valid : std_logic; -- cmd_xbar_demux:src3_valid -> cmd_xbar_mux_003:sink0_valid
signal cmd_xbar_demux_src3_startofpacket : std_logic; -- cmd_xbar_demux:src3_startofpacket -> cmd_xbar_mux_003:sink0_startofpacket
signal cmd_xbar_demux_src3_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux:src3_data -> cmd_xbar_mux_003:sink0_data
signal cmd_xbar_demux_src3_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux:src3_channel -> cmd_xbar_mux_003:sink0_channel
signal cmd_xbar_demux_src3_ready : std_logic; -- cmd_xbar_mux_003:sink0_ready -> cmd_xbar_demux:src3_ready
signal cmd_xbar_demux_src4_endofpacket : std_logic; -- cmd_xbar_demux:src4_endofpacket -> cmd_xbar_mux_004:sink0_endofpacket
signal cmd_xbar_demux_src4_valid : std_logic; -- cmd_xbar_demux:src4_valid -> cmd_xbar_mux_004:sink0_valid
signal cmd_xbar_demux_src4_startofpacket : std_logic; -- cmd_xbar_demux:src4_startofpacket -> cmd_xbar_mux_004:sink0_startofpacket
signal cmd_xbar_demux_src4_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux:src4_data -> cmd_xbar_mux_004:sink0_data
signal cmd_xbar_demux_src4_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux:src4_channel -> cmd_xbar_mux_004:sink0_channel
signal cmd_xbar_demux_src4_ready : std_logic; -- cmd_xbar_mux_004:sink0_ready -> cmd_xbar_demux:src4_ready
signal cmd_xbar_demux_001_src0_endofpacket : std_logic; -- cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket
signal cmd_xbar_demux_001_src0_valid : std_logic; -- cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid
signal cmd_xbar_demux_001_src0_startofpacket : std_logic; -- cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket
signal cmd_xbar_demux_001_src0_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data
signal cmd_xbar_demux_001_src0_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel
signal cmd_xbar_demux_001_src0_ready : std_logic; -- cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready
signal cmd_xbar_demux_001_src1_endofpacket : std_logic; -- cmd_xbar_demux_001:src1_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket
signal cmd_xbar_demux_001_src1_valid : std_logic; -- cmd_xbar_demux_001:src1_valid -> cmd_xbar_mux_001:sink1_valid
signal cmd_xbar_demux_001_src1_startofpacket : std_logic; -- cmd_xbar_demux_001:src1_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket
signal cmd_xbar_demux_001_src1_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src1_data -> cmd_xbar_mux_001:sink1_data
signal cmd_xbar_demux_001_src1_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src1_channel -> cmd_xbar_mux_001:sink1_channel
signal cmd_xbar_demux_001_src1_ready : std_logic; -- cmd_xbar_mux_001:sink1_ready -> cmd_xbar_demux_001:src1_ready
signal cmd_xbar_demux_001_src2_endofpacket : std_logic; -- cmd_xbar_demux_001:src2_endofpacket -> cmd_xbar_mux_002:sink1_endofpacket
signal cmd_xbar_demux_001_src2_valid : std_logic; -- cmd_xbar_demux_001:src2_valid -> cmd_xbar_mux_002:sink1_valid
signal cmd_xbar_demux_001_src2_startofpacket : std_logic; -- cmd_xbar_demux_001:src2_startofpacket -> cmd_xbar_mux_002:sink1_startofpacket
signal cmd_xbar_demux_001_src2_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src2_data -> cmd_xbar_mux_002:sink1_data
signal cmd_xbar_demux_001_src2_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src2_channel -> cmd_xbar_mux_002:sink1_channel
signal cmd_xbar_demux_001_src2_ready : std_logic; -- cmd_xbar_mux_002:sink1_ready -> cmd_xbar_demux_001:src2_ready
signal cmd_xbar_demux_001_src3_endofpacket : std_logic; -- cmd_xbar_demux_001:src3_endofpacket -> cmd_xbar_mux_003:sink1_endofpacket
signal cmd_xbar_demux_001_src3_valid : std_logic; -- cmd_xbar_demux_001:src3_valid -> cmd_xbar_mux_003:sink1_valid
signal cmd_xbar_demux_001_src3_startofpacket : std_logic; -- cmd_xbar_demux_001:src3_startofpacket -> cmd_xbar_mux_003:sink1_startofpacket
signal cmd_xbar_demux_001_src3_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src3_data -> cmd_xbar_mux_003:sink1_data
signal cmd_xbar_demux_001_src3_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src3_channel -> cmd_xbar_mux_003:sink1_channel
signal cmd_xbar_demux_001_src3_ready : std_logic; -- cmd_xbar_mux_003:sink1_ready -> cmd_xbar_demux_001:src3_ready
signal cmd_xbar_demux_001_src4_endofpacket : std_logic; -- cmd_xbar_demux_001:src4_endofpacket -> cmd_xbar_mux_004:sink1_endofpacket
signal cmd_xbar_demux_001_src4_valid : std_logic; -- cmd_xbar_demux_001:src4_valid -> cmd_xbar_mux_004:sink1_valid
signal cmd_xbar_demux_001_src4_startofpacket : std_logic; -- cmd_xbar_demux_001:src4_startofpacket -> cmd_xbar_mux_004:sink1_startofpacket
signal cmd_xbar_demux_001_src4_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src4_data -> cmd_xbar_mux_004:sink1_data
signal cmd_xbar_demux_001_src4_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src4_channel -> cmd_xbar_mux_004:sink1_channel
signal cmd_xbar_demux_001_src4_ready : std_logic; -- cmd_xbar_mux_004:sink1_ready -> cmd_xbar_demux_001:src4_ready
signal cmd_xbar_demux_001_src5_endofpacket : std_logic; -- cmd_xbar_demux_001:src5_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_demux_001_src5_valid : std_logic; -- cmd_xbar_demux_001:src5_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_demux_001_src5_startofpacket : std_logic; -- cmd_xbar_demux_001:src5_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_demux_001_src5_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src5_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_demux_001_src5_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src5_channel -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_demux_001_src6_endofpacket : std_logic; -- cmd_xbar_demux_001:src6_endofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_demux_001_src6_valid : std_logic; -- cmd_xbar_demux_001:src6_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_demux_001_src6_startofpacket : std_logic; -- cmd_xbar_demux_001:src6_startofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_demux_001_src6_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src6_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_demux_001_src6_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src6_channel -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_demux_001_src7_endofpacket : std_logic; -- cmd_xbar_demux_001:src7_endofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_demux_001_src7_valid : std_logic; -- cmd_xbar_demux_001:src7_valid -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_demux_001_src7_startofpacket : std_logic; -- cmd_xbar_demux_001:src7_startofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_demux_001_src7_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src7_data -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_demux_001_src7_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src7_channel -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_demux_001_src8_endofpacket : std_logic; -- cmd_xbar_demux_001:src8_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_demux_001_src8_valid : std_logic; -- cmd_xbar_demux_001:src8_valid -> switches_s1_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_demux_001_src8_startofpacket : std_logic; -- cmd_xbar_demux_001:src8_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_demux_001_src8_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src8_data -> switches_s1_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_demux_001_src8_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src8_channel -> switches_s1_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_demux_001_src10_endofpacket : std_logic; -- cmd_xbar_demux_001:src10_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_demux_001_src10_valid : std_logic; -- cmd_xbar_demux_001:src10_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_demux_001_src10_startofpacket : std_logic; -- cmd_xbar_demux_001:src10_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_demux_001_src10_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src10_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_demux_001_src10_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src10_channel -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_demux_001_src11_endofpacket : std_logic; -- cmd_xbar_demux_001:src11_endofpacket -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_demux_001_src11_valid : std_logic; -- cmd_xbar_demux_001:src11_valid -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_demux_001_src11_startofpacket : std_logic; -- cmd_xbar_demux_001:src11_startofpacket -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_demux_001_src11_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src11_data -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_demux_001_src11_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src11_channel -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_demux_001_src12_endofpacket : std_logic; -- cmd_xbar_demux_001:src12_endofpacket -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_demux_001_src12_valid : std_logic; -- cmd_xbar_demux_001:src12_valid -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_demux_001_src12_startofpacket : std_logic; -- cmd_xbar_demux_001:src12_startofpacket -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_demux_001_src12_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src12_data -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_demux_001_src12_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src12_channel -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal rsp_xbar_demux_src0_endofpacket : std_logic; -- rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket
signal rsp_xbar_demux_src0_valid : std_logic; -- rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid
signal rsp_xbar_demux_src0_startofpacket : std_logic; -- rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket
signal rsp_xbar_demux_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data
signal rsp_xbar_demux_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel
signal rsp_xbar_demux_src0_ready : std_logic; -- rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready
signal rsp_xbar_demux_src1_endofpacket : std_logic; -- rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket
signal rsp_xbar_demux_src1_valid : std_logic; -- rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid
signal rsp_xbar_demux_src1_startofpacket : std_logic; -- rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket
signal rsp_xbar_demux_src1_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data
signal rsp_xbar_demux_src1_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel
signal rsp_xbar_demux_src1_ready : std_logic; -- rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready
signal rsp_xbar_demux_001_src0_endofpacket : std_logic; -- rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket
signal rsp_xbar_demux_001_src0_valid : std_logic; -- rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid
signal rsp_xbar_demux_001_src0_startofpacket : std_logic; -- rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket
signal rsp_xbar_demux_001_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data
signal rsp_xbar_demux_001_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel
signal rsp_xbar_demux_001_src0_ready : std_logic; -- rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready
signal rsp_xbar_demux_001_src1_endofpacket : std_logic; -- rsp_xbar_demux_001:src1_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket
signal rsp_xbar_demux_001_src1_valid : std_logic; -- rsp_xbar_demux_001:src1_valid -> rsp_xbar_mux_001:sink1_valid
signal rsp_xbar_demux_001_src1_startofpacket : std_logic; -- rsp_xbar_demux_001:src1_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket
signal rsp_xbar_demux_001_src1_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_001:src1_data -> rsp_xbar_mux_001:sink1_data
signal rsp_xbar_demux_001_src1_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_001:src1_channel -> rsp_xbar_mux_001:sink1_channel
signal rsp_xbar_demux_001_src1_ready : std_logic; -- rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_001:src1_ready
signal rsp_xbar_demux_002_src0_endofpacket : std_logic; -- rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux:sink2_endofpacket
signal rsp_xbar_demux_002_src0_valid : std_logic; -- rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux:sink2_valid
signal rsp_xbar_demux_002_src0_startofpacket : std_logic; -- rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux:sink2_startofpacket
signal rsp_xbar_demux_002_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_002:src0_data -> rsp_xbar_mux:sink2_data
signal rsp_xbar_demux_002_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux:sink2_channel
signal rsp_xbar_demux_002_src0_ready : std_logic; -- rsp_xbar_mux:sink2_ready -> rsp_xbar_demux_002:src0_ready
signal rsp_xbar_demux_002_src1_endofpacket : std_logic; -- rsp_xbar_demux_002:src1_endofpacket -> rsp_xbar_mux_001:sink2_endofpacket
signal rsp_xbar_demux_002_src1_valid : std_logic; -- rsp_xbar_demux_002:src1_valid -> rsp_xbar_mux_001:sink2_valid
signal rsp_xbar_demux_002_src1_startofpacket : std_logic; -- rsp_xbar_demux_002:src1_startofpacket -> rsp_xbar_mux_001:sink2_startofpacket
signal rsp_xbar_demux_002_src1_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_002:src1_data -> rsp_xbar_mux_001:sink2_data
signal rsp_xbar_demux_002_src1_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_002:src1_channel -> rsp_xbar_mux_001:sink2_channel
signal rsp_xbar_demux_002_src1_ready : std_logic; -- rsp_xbar_mux_001:sink2_ready -> rsp_xbar_demux_002:src1_ready
signal rsp_xbar_demux_003_src0_endofpacket : std_logic; -- rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux:sink3_endofpacket
signal rsp_xbar_demux_003_src0_valid : std_logic; -- rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux:sink3_valid
signal rsp_xbar_demux_003_src0_startofpacket : std_logic; -- rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux:sink3_startofpacket
signal rsp_xbar_demux_003_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_003:src0_data -> rsp_xbar_mux:sink3_data
signal rsp_xbar_demux_003_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux:sink3_channel
signal rsp_xbar_demux_003_src0_ready : std_logic; -- rsp_xbar_mux:sink3_ready -> rsp_xbar_demux_003:src0_ready
signal rsp_xbar_demux_003_src1_endofpacket : std_logic; -- rsp_xbar_demux_003:src1_endofpacket -> rsp_xbar_mux_001:sink3_endofpacket
signal rsp_xbar_demux_003_src1_valid : std_logic; -- rsp_xbar_demux_003:src1_valid -> rsp_xbar_mux_001:sink3_valid
signal rsp_xbar_demux_003_src1_startofpacket : std_logic; -- rsp_xbar_demux_003:src1_startofpacket -> rsp_xbar_mux_001:sink3_startofpacket
signal rsp_xbar_demux_003_src1_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_003:src1_data -> rsp_xbar_mux_001:sink3_data
signal rsp_xbar_demux_003_src1_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_003:src1_channel -> rsp_xbar_mux_001:sink3_channel
signal rsp_xbar_demux_003_src1_ready : std_logic; -- rsp_xbar_mux_001:sink3_ready -> rsp_xbar_demux_003:src1_ready
signal rsp_xbar_demux_004_src0_endofpacket : std_logic; -- rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux:sink4_endofpacket
signal rsp_xbar_demux_004_src0_valid : std_logic; -- rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux:sink4_valid
signal rsp_xbar_demux_004_src0_startofpacket : std_logic; -- rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux:sink4_startofpacket
signal rsp_xbar_demux_004_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_004:src0_data -> rsp_xbar_mux:sink4_data
signal rsp_xbar_demux_004_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux:sink4_channel
signal rsp_xbar_demux_004_src0_ready : std_logic; -- rsp_xbar_mux:sink4_ready -> rsp_xbar_demux_004:src0_ready
signal rsp_xbar_demux_004_src1_endofpacket : std_logic; -- rsp_xbar_demux_004:src1_endofpacket -> rsp_xbar_mux_001:sink4_endofpacket
signal rsp_xbar_demux_004_src1_valid : std_logic; -- rsp_xbar_demux_004:src1_valid -> rsp_xbar_mux_001:sink4_valid
signal rsp_xbar_demux_004_src1_startofpacket : std_logic; -- rsp_xbar_demux_004:src1_startofpacket -> rsp_xbar_mux_001:sink4_startofpacket
signal rsp_xbar_demux_004_src1_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_004:src1_data -> rsp_xbar_mux_001:sink4_data
signal rsp_xbar_demux_004_src1_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_004:src1_channel -> rsp_xbar_mux_001:sink4_channel
signal rsp_xbar_demux_004_src1_ready : std_logic; -- rsp_xbar_mux_001:sink4_ready -> rsp_xbar_demux_004:src1_ready
signal rsp_xbar_demux_005_src0_endofpacket : std_logic; -- rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux_001:sink5_endofpacket
signal rsp_xbar_demux_005_src0_valid : std_logic; -- rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux_001:sink5_valid
signal rsp_xbar_demux_005_src0_startofpacket : std_logic; -- rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux_001:sink5_startofpacket
signal rsp_xbar_demux_005_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_005:src0_data -> rsp_xbar_mux_001:sink5_data
signal rsp_xbar_demux_005_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux_001:sink5_channel
signal rsp_xbar_demux_005_src0_ready : std_logic; -- rsp_xbar_mux_001:sink5_ready -> rsp_xbar_demux_005:src0_ready
signal rsp_xbar_demux_006_src0_endofpacket : std_logic; -- rsp_xbar_demux_006:src0_endofpacket -> rsp_xbar_mux_001:sink6_endofpacket
signal rsp_xbar_demux_006_src0_valid : std_logic; -- rsp_xbar_demux_006:src0_valid -> rsp_xbar_mux_001:sink6_valid
signal rsp_xbar_demux_006_src0_startofpacket : std_logic; -- rsp_xbar_demux_006:src0_startofpacket -> rsp_xbar_mux_001:sink6_startofpacket
signal rsp_xbar_demux_006_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_006:src0_data -> rsp_xbar_mux_001:sink6_data
signal rsp_xbar_demux_006_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_006:src0_channel -> rsp_xbar_mux_001:sink6_channel
signal rsp_xbar_demux_006_src0_ready : std_logic; -- rsp_xbar_mux_001:sink6_ready -> rsp_xbar_demux_006:src0_ready
signal rsp_xbar_demux_007_src0_endofpacket : std_logic; -- rsp_xbar_demux_007:src0_endofpacket -> rsp_xbar_mux_001:sink7_endofpacket
signal rsp_xbar_demux_007_src0_valid : std_logic; -- rsp_xbar_demux_007:src0_valid -> rsp_xbar_mux_001:sink7_valid
signal rsp_xbar_demux_007_src0_startofpacket : std_logic; -- rsp_xbar_demux_007:src0_startofpacket -> rsp_xbar_mux_001:sink7_startofpacket
signal rsp_xbar_demux_007_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_007:src0_data -> rsp_xbar_mux_001:sink7_data
signal rsp_xbar_demux_007_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_007:src0_channel -> rsp_xbar_mux_001:sink7_channel
signal rsp_xbar_demux_007_src0_ready : std_logic; -- rsp_xbar_mux_001:sink7_ready -> rsp_xbar_demux_007:src0_ready
signal rsp_xbar_demux_008_src0_endofpacket : std_logic; -- rsp_xbar_demux_008:src0_endofpacket -> rsp_xbar_mux_001:sink8_endofpacket
signal rsp_xbar_demux_008_src0_valid : std_logic; -- rsp_xbar_demux_008:src0_valid -> rsp_xbar_mux_001:sink8_valid
signal rsp_xbar_demux_008_src0_startofpacket : std_logic; -- rsp_xbar_demux_008:src0_startofpacket -> rsp_xbar_mux_001:sink8_startofpacket
signal rsp_xbar_demux_008_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_008:src0_data -> rsp_xbar_mux_001:sink8_data
signal rsp_xbar_demux_008_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_008:src0_channel -> rsp_xbar_mux_001:sink8_channel
signal rsp_xbar_demux_008_src0_ready : std_logic; -- rsp_xbar_mux_001:sink8_ready -> rsp_xbar_demux_008:src0_ready
signal rsp_xbar_demux_010_src0_endofpacket : std_logic; -- rsp_xbar_demux_010:src0_endofpacket -> rsp_xbar_mux_001:sink10_endofpacket
signal rsp_xbar_demux_010_src0_valid : std_logic; -- rsp_xbar_demux_010:src0_valid -> rsp_xbar_mux_001:sink10_valid
signal rsp_xbar_demux_010_src0_startofpacket : std_logic; -- rsp_xbar_demux_010:src0_startofpacket -> rsp_xbar_mux_001:sink10_startofpacket
signal rsp_xbar_demux_010_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_010:src0_data -> rsp_xbar_mux_001:sink10_data
signal rsp_xbar_demux_010_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_010:src0_channel -> rsp_xbar_mux_001:sink10_channel
signal rsp_xbar_demux_010_src0_ready : std_logic; -- rsp_xbar_mux_001:sink10_ready -> rsp_xbar_demux_010:src0_ready
signal rsp_xbar_demux_011_src0_endofpacket : std_logic; -- rsp_xbar_demux_011:src0_endofpacket -> rsp_xbar_mux_001:sink11_endofpacket
signal rsp_xbar_demux_011_src0_valid : std_logic; -- rsp_xbar_demux_011:src0_valid -> rsp_xbar_mux_001:sink11_valid
signal rsp_xbar_demux_011_src0_startofpacket : std_logic; -- rsp_xbar_demux_011:src0_startofpacket -> rsp_xbar_mux_001:sink11_startofpacket
signal rsp_xbar_demux_011_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_011:src0_data -> rsp_xbar_mux_001:sink11_data
signal rsp_xbar_demux_011_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_011:src0_channel -> rsp_xbar_mux_001:sink11_channel
signal rsp_xbar_demux_011_src0_ready : std_logic; -- rsp_xbar_mux_001:sink11_ready -> rsp_xbar_demux_011:src0_ready
signal rsp_xbar_demux_012_src0_endofpacket : std_logic; -- rsp_xbar_demux_012:src0_endofpacket -> rsp_xbar_mux_001:sink12_endofpacket
signal rsp_xbar_demux_012_src0_valid : std_logic; -- rsp_xbar_demux_012:src0_valid -> rsp_xbar_mux_001:sink12_valid
signal rsp_xbar_demux_012_src0_startofpacket : std_logic; -- rsp_xbar_demux_012:src0_startofpacket -> rsp_xbar_mux_001:sink12_startofpacket
signal rsp_xbar_demux_012_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_012:src0_data -> rsp_xbar_mux_001:sink12_data
signal rsp_xbar_demux_012_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_012:src0_channel -> rsp_xbar_mux_001:sink12_channel
signal rsp_xbar_demux_012_src0_ready : std_logic; -- rsp_xbar_mux_001:sink12_ready -> rsp_xbar_demux_012:src0_ready
signal addr_router_src_endofpacket : std_logic; -- addr_router:src_endofpacket -> cmd_xbar_demux:sink_endofpacket
signal addr_router_src_valid : std_logic; -- addr_router:src_valid -> cmd_xbar_demux:sink_valid
signal addr_router_src_startofpacket : std_logic; -- addr_router:src_startofpacket -> cmd_xbar_demux:sink_startofpacket
signal addr_router_src_data : std_logic_vector(99 downto 0); -- addr_router:src_data -> cmd_xbar_demux:sink_data
signal addr_router_src_channel : std_logic_vector(12 downto 0); -- addr_router:src_channel -> cmd_xbar_demux:sink_channel
signal addr_router_src_ready : std_logic; -- cmd_xbar_demux:sink_ready -> addr_router:src_ready
signal rsp_xbar_mux_src_endofpacket : std_logic; -- rsp_xbar_mux:src_endofpacket -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket
signal rsp_xbar_mux_src_valid : std_logic; -- rsp_xbar_mux:src_valid -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_valid
signal rsp_xbar_mux_src_startofpacket : std_logic; -- rsp_xbar_mux:src_startofpacket -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket
signal rsp_xbar_mux_src_data : std_logic_vector(99 downto 0); -- rsp_xbar_mux:src_data -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_data
signal rsp_xbar_mux_src_channel : std_logic_vector(12 downto 0); -- rsp_xbar_mux:src_channel -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_channel
signal rsp_xbar_mux_src_ready : std_logic; -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux:src_ready
signal addr_router_001_src_endofpacket : std_logic; -- addr_router_001:src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
signal addr_router_001_src_valid : std_logic; -- addr_router_001:src_valid -> cmd_xbar_demux_001:sink_valid
signal addr_router_001_src_startofpacket : std_logic; -- addr_router_001:src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
signal addr_router_001_src_data : std_logic_vector(99 downto 0); -- addr_router_001:src_data -> cmd_xbar_demux_001:sink_data
signal addr_router_001_src_channel : std_logic_vector(12 downto 0); -- addr_router_001:src_channel -> cmd_xbar_demux_001:sink_channel
signal addr_router_001_src_ready : std_logic; -- cmd_xbar_demux_001:sink_ready -> addr_router_001:src_ready
signal rsp_xbar_mux_001_src_endofpacket : std_logic; -- rsp_xbar_mux_001:src_endofpacket -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket
signal rsp_xbar_mux_001_src_valid : std_logic; -- rsp_xbar_mux_001:src_valid -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_valid
signal rsp_xbar_mux_001_src_startofpacket : std_logic; -- rsp_xbar_mux_001:src_startofpacket -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket
signal rsp_xbar_mux_001_src_data : std_logic_vector(99 downto 0); -- rsp_xbar_mux_001:src_data -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_data
signal rsp_xbar_mux_001_src_channel : std_logic_vector(12 downto 0); -- rsp_xbar_mux_001:src_channel -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_channel
signal rsp_xbar_mux_001_src_ready : std_logic; -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux_001:src_ready
signal cmd_xbar_mux_src_endofpacket : std_logic; -- cmd_xbar_mux:src_endofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_mux_src_valid : std_logic; -- cmd_xbar_mux:src_valid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_mux_src_startofpacket : std_logic; -- cmd_xbar_mux:src_startofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_mux_src_data : std_logic_vector(99 downto 0); -- cmd_xbar_mux:src_data -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_mux_src_channel : std_logic_vector(12 downto 0); -- cmd_xbar_mux:src_channel -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_mux_src_ready : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux:src_ready
signal id_router_src_endofpacket : std_logic; -- id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket
signal id_router_src_valid : std_logic; -- id_router:src_valid -> rsp_xbar_demux:sink_valid
signal id_router_src_startofpacket : std_logic; -- id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket
signal id_router_src_data : std_logic_vector(99 downto 0); -- id_router:src_data -> rsp_xbar_demux:sink_data
signal id_router_src_channel : std_logic_vector(12 downto 0); -- id_router:src_channel -> rsp_xbar_demux:sink_channel
signal id_router_src_ready : std_logic; -- rsp_xbar_demux:sink_ready -> id_router:src_ready
signal cmd_xbar_mux_002_src_endofpacket : std_logic; -- cmd_xbar_mux_002:src_endofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_mux_002_src_valid : std_logic; -- cmd_xbar_mux_002:src_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_mux_002_src_startofpacket : std_logic; -- cmd_xbar_mux_002:src_startofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_mux_002_src_data : std_logic_vector(99 downto 0); -- cmd_xbar_mux_002:src_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_mux_002_src_channel : std_logic_vector(12 downto 0); -- cmd_xbar_mux_002:src_channel -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_mux_002_src_ready : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_002:src_ready
signal id_router_002_src_endofpacket : std_logic; -- id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket
signal id_router_002_src_valid : std_logic; -- id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid
signal id_router_002_src_startofpacket : std_logic; -- id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket
signal id_router_002_src_data : std_logic_vector(99 downto 0); -- id_router_002:src_data -> rsp_xbar_demux_002:sink_data
signal id_router_002_src_channel : std_logic_vector(12 downto 0); -- id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel
signal id_router_002_src_ready : std_logic; -- rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready
signal cmd_xbar_demux_001_src5_ready : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src5_ready
signal id_router_005_src_endofpacket : std_logic; -- id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket
signal id_router_005_src_valid : std_logic; -- id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid
signal id_router_005_src_startofpacket : std_logic; -- id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket
signal id_router_005_src_data : std_logic_vector(99 downto 0); -- id_router_005:src_data -> rsp_xbar_demux_005:sink_data
signal id_router_005_src_channel : std_logic_vector(12 downto 0); -- id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel
signal id_router_005_src_ready : std_logic; -- rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready
signal cmd_xbar_demux_001_src6_ready : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src6_ready
signal id_router_006_src_endofpacket : std_logic; -- id_router_006:src_endofpacket -> rsp_xbar_demux_006:sink_endofpacket
signal id_router_006_src_valid : std_logic; -- id_router_006:src_valid -> rsp_xbar_demux_006:sink_valid
signal id_router_006_src_startofpacket : std_logic; -- id_router_006:src_startofpacket -> rsp_xbar_demux_006:sink_startofpacket
signal id_router_006_src_data : std_logic_vector(99 downto 0); -- id_router_006:src_data -> rsp_xbar_demux_006:sink_data
signal id_router_006_src_channel : std_logic_vector(12 downto 0); -- id_router_006:src_channel -> rsp_xbar_demux_006:sink_channel
signal id_router_006_src_ready : std_logic; -- rsp_xbar_demux_006:sink_ready -> id_router_006:src_ready
signal cmd_xbar_demux_001_src7_ready : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src7_ready
signal id_router_007_src_endofpacket : std_logic; -- id_router_007:src_endofpacket -> rsp_xbar_demux_007:sink_endofpacket
signal id_router_007_src_valid : std_logic; -- id_router_007:src_valid -> rsp_xbar_demux_007:sink_valid
signal id_router_007_src_startofpacket : std_logic; -- id_router_007:src_startofpacket -> rsp_xbar_demux_007:sink_startofpacket
signal id_router_007_src_data : std_logic_vector(99 downto 0); -- id_router_007:src_data -> rsp_xbar_demux_007:sink_data
signal id_router_007_src_channel : std_logic_vector(12 downto 0); -- id_router_007:src_channel -> rsp_xbar_demux_007:sink_channel
signal id_router_007_src_ready : std_logic; -- rsp_xbar_demux_007:sink_ready -> id_router_007:src_ready
signal cmd_xbar_demux_001_src8_ready : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src8_ready
signal id_router_008_src_endofpacket : std_logic; -- id_router_008:src_endofpacket -> rsp_xbar_demux_008:sink_endofpacket
signal id_router_008_src_valid : std_logic; -- id_router_008:src_valid -> rsp_xbar_demux_008:sink_valid
signal id_router_008_src_startofpacket : std_logic; -- id_router_008:src_startofpacket -> rsp_xbar_demux_008:sink_startofpacket
signal id_router_008_src_data : std_logic_vector(99 downto 0); -- id_router_008:src_data -> rsp_xbar_demux_008:sink_data
signal id_router_008_src_channel : std_logic_vector(12 downto 0); -- id_router_008:src_channel -> rsp_xbar_demux_008:sink_channel
signal id_router_008_src_ready : std_logic; -- rsp_xbar_demux_008:sink_ready -> id_router_008:src_ready
signal crosser_out_ready : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_ready -> crosser:out_ready
signal id_router_009_src_endofpacket : std_logic; -- id_router_009:src_endofpacket -> rsp_xbar_demux_009:sink_endofpacket
signal id_router_009_src_valid : std_logic; -- id_router_009:src_valid -> rsp_xbar_demux_009:sink_valid
signal id_router_009_src_startofpacket : std_logic; -- id_router_009:src_startofpacket -> rsp_xbar_demux_009:sink_startofpacket
signal id_router_009_src_data : std_logic_vector(99 downto 0); -- id_router_009:src_data -> rsp_xbar_demux_009:sink_data
signal id_router_009_src_channel : std_logic_vector(12 downto 0); -- id_router_009:src_channel -> rsp_xbar_demux_009:sink_channel
signal id_router_009_src_ready : std_logic; -- rsp_xbar_demux_009:sink_ready -> id_router_009:src_ready
signal cmd_xbar_demux_001_src10_ready : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src10_ready
signal id_router_010_src_endofpacket : std_logic; -- id_router_010:src_endofpacket -> rsp_xbar_demux_010:sink_endofpacket
signal id_router_010_src_valid : std_logic; -- id_router_010:src_valid -> rsp_xbar_demux_010:sink_valid
signal id_router_010_src_startofpacket : std_logic; -- id_router_010:src_startofpacket -> rsp_xbar_demux_010:sink_startofpacket
signal id_router_010_src_data : std_logic_vector(99 downto 0); -- id_router_010:src_data -> rsp_xbar_demux_010:sink_data
signal id_router_010_src_channel : std_logic_vector(12 downto 0); -- id_router_010:src_channel -> rsp_xbar_demux_010:sink_channel
signal id_router_010_src_ready : std_logic; -- rsp_xbar_demux_010:sink_ready -> id_router_010:src_ready
signal cmd_xbar_demux_001_src11_ready : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src11_ready
signal id_router_011_src_endofpacket : std_logic; -- id_router_011:src_endofpacket -> rsp_xbar_demux_011:sink_endofpacket
signal id_router_011_src_valid : std_logic; -- id_router_011:src_valid -> rsp_xbar_demux_011:sink_valid
signal id_router_011_src_startofpacket : std_logic; -- id_router_011:src_startofpacket -> rsp_xbar_demux_011:sink_startofpacket
signal id_router_011_src_data : std_logic_vector(99 downto 0); -- id_router_011:src_data -> rsp_xbar_demux_011:sink_data
signal id_router_011_src_channel : std_logic_vector(12 downto 0); -- id_router_011:src_channel -> rsp_xbar_demux_011:sink_channel
signal id_router_011_src_ready : std_logic; -- rsp_xbar_demux_011:sink_ready -> id_router_011:src_ready
signal cmd_xbar_demux_001_src12_ready : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src12_ready
signal id_router_012_src_endofpacket : std_logic; -- id_router_012:src_endofpacket -> rsp_xbar_demux_012:sink_endofpacket
signal id_router_012_src_valid : std_logic; -- id_router_012:src_valid -> rsp_xbar_demux_012:sink_valid
signal id_router_012_src_startofpacket : std_logic; -- id_router_012:src_startofpacket -> rsp_xbar_demux_012:sink_startofpacket
signal id_router_012_src_data : std_logic_vector(99 downto 0); -- id_router_012:src_data -> rsp_xbar_demux_012:sink_data
signal id_router_012_src_channel : std_logic_vector(12 downto 0); -- id_router_012:src_channel -> rsp_xbar_demux_012:sink_channel
signal id_router_012_src_ready : std_logic; -- rsp_xbar_demux_012:sink_ready -> id_router_012:src_ready
signal cmd_xbar_mux_001_src_endofpacket : std_logic; -- cmd_xbar_mux_001:src_endofpacket -> width_adapter:in_endofpacket
signal cmd_xbar_mux_001_src_valid : std_logic; -- cmd_xbar_mux_001:src_valid -> width_adapter:in_valid
signal cmd_xbar_mux_001_src_startofpacket : std_logic; -- cmd_xbar_mux_001:src_startofpacket -> width_adapter:in_startofpacket
signal cmd_xbar_mux_001_src_data : std_logic_vector(99 downto 0); -- cmd_xbar_mux_001:src_data -> width_adapter:in_data
signal cmd_xbar_mux_001_src_channel : std_logic_vector(12 downto 0); -- cmd_xbar_mux_001:src_channel -> width_adapter:in_channel
signal cmd_xbar_mux_001_src_ready : std_logic; -- width_adapter:in_ready -> cmd_xbar_mux_001:src_ready
signal width_adapter_src_endofpacket : std_logic; -- width_adapter:out_endofpacket -> burst_adapter:sink0_endofpacket
signal width_adapter_src_valid : std_logic; -- width_adapter:out_valid -> burst_adapter:sink0_valid
signal width_adapter_src_startofpacket : std_logic; -- width_adapter:out_startofpacket -> burst_adapter:sink0_startofpacket
signal width_adapter_src_data : std_logic_vector(81 downto 0); -- width_adapter:out_data -> burst_adapter:sink0_data
signal width_adapter_src_ready : std_logic; -- burst_adapter:sink0_ready -> width_adapter:out_ready
signal width_adapter_src_channel : std_logic_vector(12 downto 0); -- width_adapter:out_channel -> burst_adapter:sink0_channel
signal id_router_001_src_endofpacket : std_logic; -- id_router_001:src_endofpacket -> width_adapter_001:in_endofpacket
signal id_router_001_src_valid : std_logic; -- id_router_001:src_valid -> width_adapter_001:in_valid
signal id_router_001_src_startofpacket : std_logic; -- id_router_001:src_startofpacket -> width_adapter_001:in_startofpacket
signal id_router_001_src_data : std_logic_vector(81 downto 0); -- id_router_001:src_data -> width_adapter_001:in_data
signal id_router_001_src_channel : std_logic_vector(12 downto 0); -- id_router_001:src_channel -> width_adapter_001:in_channel
signal id_router_001_src_ready : std_logic; -- width_adapter_001:in_ready -> id_router_001:src_ready
signal width_adapter_001_src_endofpacket : std_logic; -- width_adapter_001:out_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
signal width_adapter_001_src_valid : std_logic; -- width_adapter_001:out_valid -> rsp_xbar_demux_001:sink_valid
signal width_adapter_001_src_startofpacket : std_logic; -- width_adapter_001:out_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
signal width_adapter_001_src_data : std_logic_vector(99 downto 0); -- width_adapter_001:out_data -> rsp_xbar_demux_001:sink_data
signal width_adapter_001_src_ready : std_logic; -- rsp_xbar_demux_001:sink_ready -> width_adapter_001:out_ready
signal width_adapter_001_src_channel : std_logic_vector(12 downto 0); -- width_adapter_001:out_channel -> rsp_xbar_demux_001:sink_channel
signal cmd_xbar_mux_003_src_endofpacket : std_logic; -- cmd_xbar_mux_003:src_endofpacket -> width_adapter_002:in_endofpacket
signal cmd_xbar_mux_003_src_valid : std_logic; -- cmd_xbar_mux_003:src_valid -> width_adapter_002:in_valid
signal cmd_xbar_mux_003_src_startofpacket : std_logic; -- cmd_xbar_mux_003:src_startofpacket -> width_adapter_002:in_startofpacket
signal cmd_xbar_mux_003_src_data : std_logic_vector(99 downto 0); -- cmd_xbar_mux_003:src_data -> width_adapter_002:in_data
signal cmd_xbar_mux_003_src_channel : std_logic_vector(12 downto 0); -- cmd_xbar_mux_003:src_channel -> width_adapter_002:in_channel
signal cmd_xbar_mux_003_src_ready : std_logic; -- width_adapter_002:in_ready -> cmd_xbar_mux_003:src_ready
signal width_adapter_002_src_endofpacket : std_logic; -- width_adapter_002:out_endofpacket -> burst_adapter_001:sink0_endofpacket
signal width_adapter_002_src_valid : std_logic; -- width_adapter_002:out_valid -> burst_adapter_001:sink0_valid
signal width_adapter_002_src_startofpacket : std_logic; -- width_adapter_002:out_startofpacket -> burst_adapter_001:sink0_startofpacket
signal width_adapter_002_src_data : std_logic_vector(81 downto 0); -- width_adapter_002:out_data -> burst_adapter_001:sink0_data
signal width_adapter_002_src_ready : std_logic; -- burst_adapter_001:sink0_ready -> width_adapter_002:out_ready
signal width_adapter_002_src_channel : std_logic_vector(12 downto 0); -- width_adapter_002:out_channel -> burst_adapter_001:sink0_channel
signal id_router_003_src_endofpacket : std_logic; -- id_router_003:src_endofpacket -> width_adapter_003:in_endofpacket
signal id_router_003_src_valid : std_logic; -- id_router_003:src_valid -> width_adapter_003:in_valid
signal id_router_003_src_startofpacket : std_logic; -- id_router_003:src_startofpacket -> width_adapter_003:in_startofpacket
signal id_router_003_src_data : std_logic_vector(81 downto 0); -- id_router_003:src_data -> width_adapter_003:in_data
signal id_router_003_src_channel : std_logic_vector(12 downto 0); -- id_router_003:src_channel -> width_adapter_003:in_channel
signal id_router_003_src_ready : std_logic; -- width_adapter_003:in_ready -> id_router_003:src_ready
signal width_adapter_003_src_endofpacket : std_logic; -- width_adapter_003:out_endofpacket -> rsp_xbar_demux_003:sink_endofpacket
signal width_adapter_003_src_valid : std_logic; -- width_adapter_003:out_valid -> rsp_xbar_demux_003:sink_valid
signal width_adapter_003_src_startofpacket : std_logic; -- width_adapter_003:out_startofpacket -> rsp_xbar_demux_003:sink_startofpacket
signal width_adapter_003_src_data : std_logic_vector(99 downto 0); -- width_adapter_003:out_data -> rsp_xbar_demux_003:sink_data
signal width_adapter_003_src_ready : std_logic; -- rsp_xbar_demux_003:sink_ready -> width_adapter_003:out_ready
signal width_adapter_003_src_channel : std_logic_vector(12 downto 0); -- width_adapter_003:out_channel -> rsp_xbar_demux_003:sink_channel
signal cmd_xbar_mux_004_src_endofpacket : std_logic; -- cmd_xbar_mux_004:src_endofpacket -> width_adapter_004:in_endofpacket
signal cmd_xbar_mux_004_src_valid : std_logic; -- cmd_xbar_mux_004:src_valid -> width_adapter_004:in_valid
signal cmd_xbar_mux_004_src_startofpacket : std_logic; -- cmd_xbar_mux_004:src_startofpacket -> width_adapter_004:in_startofpacket
signal cmd_xbar_mux_004_src_data : std_logic_vector(99 downto 0); -- cmd_xbar_mux_004:src_data -> width_adapter_004:in_data
signal cmd_xbar_mux_004_src_channel : std_logic_vector(12 downto 0); -- cmd_xbar_mux_004:src_channel -> width_adapter_004:in_channel
signal cmd_xbar_mux_004_src_ready : std_logic; -- width_adapter_004:in_ready -> cmd_xbar_mux_004:src_ready
signal width_adapter_004_src_endofpacket : std_logic; -- width_adapter_004:out_endofpacket -> burst_adapter_002:sink0_endofpacket
signal width_adapter_004_src_valid : std_logic; -- width_adapter_004:out_valid -> burst_adapter_002:sink0_valid
signal width_adapter_004_src_startofpacket : std_logic; -- width_adapter_004:out_startofpacket -> burst_adapter_002:sink0_startofpacket
signal width_adapter_004_src_data : std_logic_vector(72 downto 0); -- width_adapter_004:out_data -> burst_adapter_002:sink0_data
signal width_adapter_004_src_ready : std_logic; -- burst_adapter_002:sink0_ready -> width_adapter_004:out_ready
signal width_adapter_004_src_channel : std_logic_vector(12 downto 0); -- width_adapter_004:out_channel -> burst_adapter_002:sink0_channel
signal id_router_004_src_endofpacket : std_logic; -- id_router_004:src_endofpacket -> width_adapter_005:in_endofpacket
signal id_router_004_src_valid : std_logic; -- id_router_004:src_valid -> width_adapter_005:in_valid
signal id_router_004_src_startofpacket : std_logic; -- id_router_004:src_startofpacket -> width_adapter_005:in_startofpacket
signal id_router_004_src_data : std_logic_vector(72 downto 0); -- id_router_004:src_data -> width_adapter_005:in_data
signal id_router_004_src_channel : std_logic_vector(12 downto 0); -- id_router_004:src_channel -> width_adapter_005:in_channel
signal id_router_004_src_ready : std_logic; -- width_adapter_005:in_ready -> id_router_004:src_ready
signal width_adapter_005_src_endofpacket : std_logic; -- width_adapter_005:out_endofpacket -> rsp_xbar_demux_004:sink_endofpacket
signal width_adapter_005_src_valid : std_logic; -- width_adapter_005:out_valid -> rsp_xbar_demux_004:sink_valid
signal width_adapter_005_src_startofpacket : std_logic; -- width_adapter_005:out_startofpacket -> rsp_xbar_demux_004:sink_startofpacket
signal width_adapter_005_src_data : std_logic_vector(99 downto 0); -- width_adapter_005:out_data -> rsp_xbar_demux_004:sink_data
signal width_adapter_005_src_ready : std_logic; -- rsp_xbar_demux_004:sink_ready -> width_adapter_005:out_ready
signal width_adapter_005_src_channel : std_logic_vector(12 downto 0); -- width_adapter_005:out_channel -> rsp_xbar_demux_004:sink_channel
signal crosser_out_endofpacket : std_logic; -- crosser:out_endofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal crosser_out_valid : std_logic; -- crosser:out_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal crosser_out_startofpacket : std_logic; -- crosser:out_startofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal crosser_out_data : std_logic_vector(99 downto 0); -- crosser:out_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_data
signal crosser_out_channel : std_logic_vector(12 downto 0); -- crosser:out_channel -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_demux_001_src9_endofpacket : std_logic; -- cmd_xbar_demux_001:src9_endofpacket -> crosser:in_endofpacket
signal cmd_xbar_demux_001_src9_valid : std_logic; -- cmd_xbar_demux_001:src9_valid -> crosser:in_valid
signal cmd_xbar_demux_001_src9_startofpacket : std_logic; -- cmd_xbar_demux_001:src9_startofpacket -> crosser:in_startofpacket
signal cmd_xbar_demux_001_src9_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src9_data -> crosser:in_data
signal cmd_xbar_demux_001_src9_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src9_channel -> crosser:in_channel
signal cmd_xbar_demux_001_src9_ready : std_logic; -- crosser:in_ready -> cmd_xbar_demux_001:src9_ready
signal crosser_001_out_endofpacket : std_logic; -- crosser_001:out_endofpacket -> rsp_xbar_mux_001:sink9_endofpacket
signal crosser_001_out_valid : std_logic; -- crosser_001:out_valid -> rsp_xbar_mux_001:sink9_valid
signal crosser_001_out_startofpacket : std_logic; -- crosser_001:out_startofpacket -> rsp_xbar_mux_001:sink9_startofpacket
signal crosser_001_out_data : std_logic_vector(99 downto 0); -- crosser_001:out_data -> rsp_xbar_mux_001:sink9_data
signal crosser_001_out_channel : std_logic_vector(12 downto 0); -- crosser_001:out_channel -> rsp_xbar_mux_001:sink9_channel
signal crosser_001_out_ready : std_logic; -- rsp_xbar_mux_001:sink9_ready -> crosser_001:out_ready
signal rsp_xbar_demux_009_src0_endofpacket : std_logic; -- rsp_xbar_demux_009:src0_endofpacket -> crosser_001:in_endofpacket
signal rsp_xbar_demux_009_src0_valid : std_logic; -- rsp_xbar_demux_009:src0_valid -> crosser_001:in_valid
signal rsp_xbar_demux_009_src0_startofpacket : std_logic; -- rsp_xbar_demux_009:src0_startofpacket -> crosser_001:in_startofpacket
signal rsp_xbar_demux_009_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_009:src0_data -> crosser_001:in_data
signal rsp_xbar_demux_009_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_009:src0_channel -> crosser_001:in_channel
signal rsp_xbar_demux_009_src0_ready : std_logic; -- crosser_001:in_ready -> rsp_xbar_demux_009:src0_ready
signal irq_mapper_receiver0_irq : std_logic; -- timer_0:irq -> irq_mapper:receiver0_irq
signal irq_mapper_receiver1_irq : std_logic; -- jtag_uart_0:av_irq -> irq_mapper:receiver1_irq
signal irq_mapper_receiver2_irq : std_logic; -- usb_0:irq -> irq_mapper:receiver2_irq
signal irq_mapper_receiver3_irq : std_logic; -- rs232_0:irq -> irq_mapper:receiver3_irq
signal nios2_qsys_0_d_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2_qsys_0:d_irq
signal reset_reset_n_ports_inv : std_logic; -- reset_reset_n:inv -> [rst_controller:reset_in0, rst_controller_001:reset_in0]
signal sdram_0_s1_translator_avalon_anti_slave_0_write_ports_inv : std_logic; -- sdram_0_s1_translator_avalon_anti_slave_0_write:inv -> sdram_0:az_wr_n
signal sdram_0_s1_translator_avalon_anti_slave_0_read_ports_inv : std_logic; -- sdram_0_s1_translator_avalon_anti_slave_0_read:inv -> sdram_0:az_rd_n
signal sdram_0_s1_translator_avalon_anti_slave_0_byteenable_ports_inv : std_logic_vector(1 downto 0); -- sdram_0_s1_translator_avalon_anti_slave_0_byteenable:inv -> sdram_0:az_be_n
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write_ports_inv : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write:inv -> jtag_uart_0:av_write_n
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read_ports_inv : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read:inv -> jtag_uart_0:av_read_n
signal green_leds_s1_translator_avalon_anti_slave_0_write_ports_inv : std_logic; -- green_leds_s1_translator_avalon_anti_slave_0_write:inv -> green_leds:write_n
signal timer_0_s1_translator_avalon_anti_slave_0_write_ports_inv : std_logic; -- timer_0_s1_translator_avalon_anti_slave_0_write:inv -> timer_0:write_n
signal rst_controller_reset_out_reset_ports_inv : std_logic; -- rst_controller_reset_out_reset:inv -> [green_leds:reset_n, jtag_uart_0:rst_n, nios2_qsys_0:reset_n, sdram_0:reset_n, switches:reset_n, sysid_qsys_0:reset_n, timer_0:reset_n]
begin
nios2_qsys_0 : component niosII_system_nios2_qsys_0
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset_n.reset_n
d_address => nios2_qsys_0_data_master_address, -- data_master.address
d_byteenable => nios2_qsys_0_data_master_byteenable, -- .byteenable
d_read => nios2_qsys_0_data_master_read, -- .read
d_readdata => nios2_qsys_0_data_master_readdata, -- .readdata
d_waitrequest => nios2_qsys_0_data_master_waitrequest, -- .waitrequest
d_write => nios2_qsys_0_data_master_write, -- .write
d_writedata => nios2_qsys_0_data_master_writedata, -- .writedata
jtag_debug_module_debugaccess_to_roms => nios2_qsys_0_data_master_debugaccess, -- .debugaccess
i_address => nios2_qsys_0_instruction_master_address, -- instruction_master.address
i_read => nios2_qsys_0_instruction_master_read, -- .read
i_readdata => nios2_qsys_0_instruction_master_readdata, -- .readdata
i_waitrequest => nios2_qsys_0_instruction_master_waitrequest, -- .waitrequest
d_irq => nios2_qsys_0_d_irq_irq, -- d_irq.irq
jtag_debug_module_resetrequest => nios2_qsys_0_jtag_debug_module_reset_reset, -- jtag_debug_module_reset.reset
jtag_debug_module_address => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_address, -- jtag_debug_module.address
jtag_debug_module_byteenable => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_byteenable, -- .byteenable
jtag_debug_module_debugaccess => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess, -- .debugaccess
jtag_debug_module_read => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_read, -- .read
jtag_debug_module_readdata => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_readdata, -- .readdata
jtag_debug_module_waitrequest => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
jtag_debug_module_write => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_write, -- .write
jtag_debug_module_writedata => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_writedata, -- .writedata
no_ci_readra => open -- custom_instruction_master.readra
);
onchip_memory2_0 : component niosII_system_onchip_memory2_0
port map (
clk => altpll_0_c1_clk, -- clk1.clk
address => onchip_memory2_0_s1_translator_avalon_anti_slave_0_address, -- s1.address
clken => onchip_memory2_0_s1_translator_avalon_anti_slave_0_clken, -- .clken
chipselect => onchip_memory2_0_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
write => onchip_memory2_0_s1_translator_avalon_anti_slave_0_write, -- .write
readdata => onchip_memory2_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
writedata => onchip_memory2_0_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
byteenable => onchip_memory2_0_s1_translator_avalon_anti_slave_0_byteenable, -- .byteenable
reset => rst_controller_reset_out_reset, -- reset1.reset
reset_req => rst_controller_reset_out_reset_req -- .reset_req
);
sysid_qsys_0 : component niosII_system_sysid_qsys_0
port map (
clock => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
readdata => sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_readdata, -- control_slave.readdata
address => sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_address(0) -- .address
);
jtag_uart_0 : component niosII_system_jtag_uart_0
port map (
clk => altpll_0_c1_clk, -- clk.clk
rst_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
av_chipselect => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect, -- avalon_jtag_slave.chipselect
av_address => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address(0), -- .address
av_read_n => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read_ports_inv, -- .read_n
av_readdata => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_write_n => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write_ports_inv, -- .write_n
av_writedata => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_waitrequest => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_irq => irq_mapper_receiver1_irq -- irq.irq
);
green_leds : component niosII_system_green_leds
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => green_leds_s1_translator_avalon_anti_slave_0_address, -- s1.address
write_n => green_leds_s1_translator_avalon_anti_slave_0_write_ports_inv, -- .write_n
writedata => green_leds_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
chipselect => green_leds_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
readdata => green_leds_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
out_port => green_leds_external_connection_export -- external_connection.export
);
switches : component niosII_system_switches
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => switches_s1_translator_avalon_anti_slave_0_address, -- s1.address
readdata => switches_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
in_port => switches_external_connection_export -- external_connection.export
);
altpll_0 : component niosII_system_altpll_0
port map (
clk => clk_clk, -- inclk_interface.clk
reset => rst_controller_001_reset_out_reset, -- inclk_interface_reset.reset
read => altpll_0_pll_slave_translator_avalon_anti_slave_0_read, -- pll_slave.read
write => altpll_0_pll_slave_translator_avalon_anti_slave_0_write, -- .write
address => altpll_0_pll_slave_translator_avalon_anti_slave_0_address, -- .address
readdata => altpll_0_pll_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
writedata => altpll_0_pll_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
c0 => altpll_0_c0_clk, -- c0.clk
c1 => altpll_0_c1_clk, -- c1.clk
areset => open, -- areset_conduit.export
locked => open, -- locked_conduit.export
phasedone => open -- phasedone_conduit.export
);
sdram_0 : component niosII_system_sdram_0
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
az_addr => sdram_0_s1_translator_avalon_anti_slave_0_address, -- s1.address
az_be_n => sdram_0_s1_translator_avalon_anti_slave_0_byteenable_ports_inv, -- .byteenable_n
az_cs => sdram_0_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
az_data => sdram_0_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
az_rd_n => sdram_0_s1_translator_avalon_anti_slave_0_read_ports_inv, -- .read_n
az_wr_n => sdram_0_s1_translator_avalon_anti_slave_0_write_ports_inv, -- .write_n
za_data => sdram_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
za_valid => sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid, -- .readdatavalid
za_waitrequest => sdram_0_s1_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
zs_addr => sdram_0_wire_addr, -- wire.export
zs_ba => sdram_0_wire_ba, -- .export
zs_cas_n => sdram_0_wire_cas_n, -- .export
zs_cke => sdram_0_wire_cke, -- .export
zs_cs_n => sdram_0_wire_cs_n, -- .export
zs_dq => sdram_0_wire_dq, -- .export
zs_dqm => sdram_0_wire_dqm, -- .export
zs_ras_n => sdram_0_wire_ras_n, -- .export
zs_we_n => sdram_0_wire_we_n -- .export
);
sram_0 : component niosII_system_sram_0
port map (
clk => altpll_0_c1_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
SRAM_DQ => sram_0_external_interface_DQ, -- external_interface.export
SRAM_ADDR => sram_0_external_interface_ADDR, -- .export
SRAM_LB_N => sram_0_external_interface_LB_N, -- .export
SRAM_UB_N => sram_0_external_interface_UB_N, -- .export
SRAM_CE_N => sram_0_external_interface_CE_N, -- .export
SRAM_OE_N => sram_0_external_interface_OE_N, -- .export
SRAM_WE_N => sram_0_external_interface_WE_N, -- .export
address => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_address, -- avalon_sram_slave.address
byteenable => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
read => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_read, -- .read
write => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_write, -- .write
writedata => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
readdata => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
readdatavalid => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdatavalid -- .readdatavalid
);
timer_0 : component niosII_system_timer_0
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => timer_0_s1_translator_avalon_anti_slave_0_address, -- s1.address
writedata => timer_0_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
readdata => timer_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
chipselect => timer_0_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
write_n => timer_0_s1_translator_avalon_anti_slave_0_write_ports_inv, -- .write_n
irq => irq_mapper_receiver0_irq -- irq.irq
);
usb_0 : component niosII_system_usb_0
port map (
clk => altpll_0_c1_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
address => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_address, -- avalon_usb_slave.address
chipselect => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_chipselect, -- .chipselect
read => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_read, -- .read
write => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_write, -- .write
writedata => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
readdata => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
irq => irq_mapper_receiver2_irq, -- interrupt.irq
OTG_INT1 => usb_0_external_interface_INT1, -- external_interface.export
OTG_DATA => usb_0_external_interface_DATA, -- .export
OTG_RST_N => usb_0_external_interface_RST_N, -- .export
OTG_ADDR => usb_0_external_interface_ADDR, -- .export
OTG_CS_N => usb_0_external_interface_CS_N, -- .export
OTG_RD_N => usb_0_external_interface_RD_N, -- .export
OTG_WR_N => usb_0_external_interface_WR_N, -- .export
OTG_INT0 => usb_0_external_interface_INT0 -- .export
);
rs232_0 : component niosII_system_rs232_0
port map (
clk => altpll_0_c1_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
address => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_address(0), -- avalon_rs232_slave.address
chipselect => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_chipselect, -- .chipselect
byteenable => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
read => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_read, -- .read
write => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_write, -- .write
writedata => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
readdata => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
irq => irq_mapper_receiver3_irq, -- interrupt.irq
UART_RXD => rs232_0_external_interface_RXD, -- external_interface.export
UART_TXD => rs232_0_external_interface_TXD -- .export
);
generic_tristate_controller_0 : component niosII_system_generic_tristate_controller_0
generic map (
TCM_ADDRESS_W => 22,
TCM_DATA_W => 8,
TCM_BYTEENABLE_W => 1,
TCM_READ_WAIT => 160,
TCM_WRITE_WAIT => 160,
TCM_SETUP_WAIT => 40,
TCM_DATA_HOLD => 40,
TCM_TURNAROUND_TIME => 2,
TCM_TIMING_UNITS => 0,
TCM_READLATENCY => 2,
TCM_SYMBOLS_PER_WORD => 1,
USE_READDATA => 1,
USE_WRITEDATA => 1,
USE_READ => 1,
USE_WRITE => 1,
USE_BYTEENABLE => 1,
USE_CHIPSELECT => 1,
USE_LOCK => 0,
USE_ADDRESS => 1,
USE_WAITREQUEST => 0,
USE_WRITEBYTEENABLE => 0,
USE_OUTPUTENABLE => 0,
USE_RESETREQUEST => 0,
USE_IRQ => 0,
USE_RESET_OUTPUT => 0,
ACTIVE_LOW_READ => 1,
ACTIVE_LOW_LOCK => 0,
ACTIVE_LOW_WRITE => 1,
ACTIVE_LOW_CHIPSELECT => 1,
ACTIVE_LOW_BYTEENABLE => 0,
ACTIVE_LOW_OUTPUTENABLE => 0,
ACTIVE_LOW_WRITEBYTEENABLE => 0,
ACTIVE_LOW_WAITREQUEST => 0,
ACTIVE_LOW_BEGINTRANSFER => 0,
CHIPSELECT_THROUGH_READLATENCY => 0
)
port map (
clk_clk => altpll_0_c1_clk, -- clk.clk
reset_reset => rst_controller_reset_out_reset, -- reset.reset
uas_address => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_address, -- uas.address
uas_burstcount => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_burstcount, -- .burstcount
uas_read => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_read, -- .read
uas_write => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_write, -- .write
uas_waitrequest => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
uas_readdatavalid => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_readdatavalid, -- .readdatavalid
uas_byteenable => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_byteenable, -- .byteenable
uas_readdata => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_readdata, -- .readdata
uas_writedata => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_writedata, -- .writedata
uas_lock => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_lock, -- .lock
uas_debugaccess => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_debugaccess, -- .debugaccess
tcm_write_n_out => generic_tristate_controller_0_tcm_write_n_out, -- tcm.write_n_out
tcm_read_n_out => generic_tristate_controller_0_tcm_read_n_out, -- .read_n_out
tcm_begintransfer_out => generic_tristate_controller_0_tcm_begintransfer_out, -- .begintransfer_out
tcm_chipselect_n_out => generic_tristate_controller_0_tcm_chipselect_n_out, -- .chipselect_n_out
tcm_request => generic_tristate_controller_0_tcm_request, -- .request
tcm_grant => generic_tristate_controller_0_tcm_grant, -- .grant
tcm_address_out => generic_tristate_controller_0_tcm_address_out, -- .address_out
tcm_byteenable_out => generic_tristate_controller_0_tcm_byteenable_out, -- .byteenable_out
tcm_data_out => generic_tristate_controller_0_tcm_data_out, -- .data_out
tcm_data_outen => generic_tristate_controller_0_tcm_data_outen, -- .data_outen
tcm_data_in => generic_tristate_controller_0_tcm_data_in -- .data_in
);
tristate_conduit_bridge_0 : component niosII_system_tristate_conduit_bridge_0
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
request => tristate_conduit_pin_sharer_0_tcm_request, -- tcs.request
grant => tristate_conduit_pin_sharer_0_tcm_grant, -- .grant
tcs_generic_tristate_controller_0_tcm_read_n_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_read_n_out_out, -- .generic_tristate_controller_0_tcm_read_n_out_out
tcs_generic_tristate_controller_0_tcm_data_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_data_out_out, -- .generic_tristate_controller_0_tcm_data_out_out
tcs_generic_tristate_controller_0_tcm_data_outen => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_data_out_outen, -- .generic_tristate_controller_0_tcm_data_out_outen
tcs_generic_tristate_controller_0_tcm_data_in => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_data_out_in, -- .generic_tristate_controller_0_tcm_data_out_in
tcs_generic_tristate_controller_0_tcm_chipselect_n_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_chipselect_n_out_out, -- .generic_tristate_controller_0_tcm_chipselect_n_out_out
tcs_generic_tristate_controller_0_tcm_write_n_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_write_n_out_out, -- .generic_tristate_controller_0_tcm_write_n_out_out
tcs_generic_tristate_controller_0_tcm_byteenable_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_byteenable_out_out, -- .generic_tristate_controller_0_tcm_byteenable_out_out
tcs_generic_tristate_controller_0_tcm_begintransfer_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_begintransfer_out_out, -- .generic_tristate_controller_0_tcm_begintransfer_out_out
tcs_generic_tristate_controller_0_tcm_address_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_address_out_out, -- .generic_tristate_controller_0_tcm_address_out_out
generic_tristate_controller_0_tcm_read_n_out => tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_read_n_out, -- out.generic_tristate_controller_0_tcm_read_n_out
generic_tristate_controller_0_tcm_data_out => tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_data_out, -- .generic_tristate_controller_0_tcm_data_out
generic_tristate_controller_0_tcm_chipselect_n_out => tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_chipselect_n_out, -- .generic_tristate_controller_0_tcm_chipselect_n_out
generic_tristate_controller_0_tcm_write_n_out => tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_write_n_out, -- .generic_tristate_controller_0_tcm_write_n_out
generic_tristate_controller_0_tcm_byteenable_out => tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_byteenable_out, -- .generic_tristate_controller_0_tcm_byteenable_out
generic_tristate_controller_0_tcm_begintransfer_out => tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_begintransfer_out, -- .generic_tristate_controller_0_tcm_begintransfer_out
generic_tristate_controller_0_tcm_address_out => tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_address_out -- .generic_tristate_controller_0_tcm_address_out
);
tristate_conduit_pin_sharer_0 : component niosII_system_tristate_conduit_pin_sharer_0
port map (
clk_clk => altpll_0_c1_clk, -- clk.clk
reset_reset => rst_controller_reset_out_reset, -- reset.reset
request => tristate_conduit_pin_sharer_0_tcm_request, -- tcm.request
grant => tristate_conduit_pin_sharer_0_tcm_grant, -- .grant
generic_tristate_controller_0_tcm_byteenable_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_byteenable_out_out, -- .generic_tristate_controller_0_tcm_byteenable_out_out
generic_tristate_controller_0_tcm_address_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_address_out_out, -- .generic_tristate_controller_0_tcm_address_out_out
generic_tristate_controller_0_tcm_read_n_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_read_n_out_out, -- .generic_tristate_controller_0_tcm_read_n_out_out
generic_tristate_controller_0_tcm_write_n_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_write_n_out_out, -- .generic_tristate_controller_0_tcm_write_n_out_out
generic_tristate_controller_0_tcm_data_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_data_out_out, -- .generic_tristate_controller_0_tcm_data_out_out
generic_tristate_controller_0_tcm_data_in => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_data_out_in, -- .generic_tristate_controller_0_tcm_data_out_in
generic_tristate_controller_0_tcm_data_outen => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_data_out_outen, -- .generic_tristate_controller_0_tcm_data_out_outen
generic_tristate_controller_0_tcm_chipselect_n_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_chipselect_n_out_out, -- .generic_tristate_controller_0_tcm_chipselect_n_out_out
generic_tristate_controller_0_tcm_begintransfer_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_begintransfer_out_out, -- .generic_tristate_controller_0_tcm_begintransfer_out_out
tcs0_request => generic_tristate_controller_0_tcm_request, -- tcs0.request
tcs0_grant => generic_tristate_controller_0_tcm_grant, -- .grant
tcs0_byteenable_out(0) => generic_tristate_controller_0_tcm_byteenable_out, -- .byteenable_out
tcs0_address_out => generic_tristate_controller_0_tcm_address_out, -- .address_out
tcs0_read_n_out(0) => generic_tristate_controller_0_tcm_read_n_out, -- .read_n_out
tcs0_write_n_out(0) => generic_tristate_controller_0_tcm_write_n_out, -- .write_n_out
tcs0_data_out => generic_tristate_controller_0_tcm_data_out, -- .data_out
tcs0_data_in => generic_tristate_controller_0_tcm_data_in, -- .data_in
tcs0_data_outen => generic_tristate_controller_0_tcm_data_outen, -- .data_outen
tcs0_chipselect_n_out(0) => generic_tristate_controller_0_tcm_chipselect_n_out, -- .chipselect_n_out
tcs0_begintransfer_out(0) => generic_tristate_controller_0_tcm_begintransfer_out -- .begintransfer_out
);
nios2_qsys_0_instruction_master_translator : component niosii_system_nios2_qsys_0_instruction_master_translator
generic map (
AV_ADDRESS_W => 25,
AV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
USE_READ => 1,
USE_WRITE => 0,
USE_BEGINBURSTTRANSFER => 0,
USE_BEGINTRANSFER => 0,
USE_CHIPSELECT => 0,
USE_BURSTCOUNT => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 1,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_LINEWRAPBURSTS => 1,
AV_REGISTERINCOMINGSIGNALS => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address, -- avalon_universal_master_0.address
uav_burstcount => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
uav_read => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read, -- .read
uav_write => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write, -- .write
uav_waitrequest => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
uav_readdatavalid => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
uav_byteenable => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
uav_readdata => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata, -- .readdata
uav_writedata => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata, -- .writedata
uav_lock => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock, -- .lock
uav_debugaccess => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_address => nios2_qsys_0_instruction_master_address, -- avalon_anti_master_0.address
av_waitrequest => nios2_qsys_0_instruction_master_waitrequest, -- .waitrequest
av_read => nios2_qsys_0_instruction_master_read, -- .read
av_readdata => nios2_qsys_0_instruction_master_readdata, -- .readdata
av_burstcount => "1", -- (terminated)
av_byteenable => "1111", -- (terminated)
av_beginbursttransfer => '0', -- (terminated)
av_begintransfer => '0', -- (terminated)
av_chipselect => '0', -- (terminated)
av_readdatavalid => open, -- (terminated)
av_write => '0', -- (terminated)
av_writedata => "00000000000000000000000000000000", -- (terminated)
av_lock => '0', -- (terminated)
av_debugaccess => '0', -- (terminated)
uav_clken => open, -- (terminated)
av_clken => '1', -- (terminated)
uav_response => "00", -- (terminated)
av_response => open, -- (terminated)
uav_writeresponserequest => open, -- (terminated)
uav_writeresponsevalid => '0', -- (terminated)
av_writeresponserequest => '0', -- (terminated)
av_writeresponsevalid => open -- (terminated)
);
nios2_qsys_0_data_master_translator : component niosii_system_nios2_qsys_0_data_master_translator
generic map (
AV_ADDRESS_W => 25,
AV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
USE_READ => 1,
USE_WRITE => 1,
USE_BEGINBURSTTRANSFER => 0,
USE_BEGINTRANSFER => 0,
USE_CHIPSELECT => 0,
USE_BURSTCOUNT => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 1,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_LINEWRAPBURSTS => 0,
AV_REGISTERINCOMINGSIGNALS => 1
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => nios2_qsys_0_data_master_translator_avalon_universal_master_0_address, -- avalon_universal_master_0.address
uav_burstcount => nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
uav_read => nios2_qsys_0_data_master_translator_avalon_universal_master_0_read, -- .read
uav_write => nios2_qsys_0_data_master_translator_avalon_universal_master_0_write, -- .write
uav_waitrequest => nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
uav_readdatavalid => nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
uav_byteenable => nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
uav_readdata => nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata, -- .readdata
uav_writedata => nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata, -- .writedata
uav_lock => nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock, -- .lock
uav_debugaccess => nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_address => nios2_qsys_0_data_master_address, -- avalon_anti_master_0.address
av_waitrequest => nios2_qsys_0_data_master_waitrequest, -- .waitrequest
av_byteenable => nios2_qsys_0_data_master_byteenable, -- .byteenable
av_read => nios2_qsys_0_data_master_read, -- .read
av_readdata => nios2_qsys_0_data_master_readdata, -- .readdata
av_write => nios2_qsys_0_data_master_write, -- .write
av_writedata => nios2_qsys_0_data_master_writedata, -- .writedata
av_debugaccess => nios2_qsys_0_data_master_debugaccess, -- .debugaccess
av_burstcount => "1", -- (terminated)
av_beginbursttransfer => '0', -- (terminated)
av_begintransfer => '0', -- (terminated)
av_chipselect => '0', -- (terminated)
av_readdatavalid => open, -- (terminated)
av_lock => '0', -- (terminated)
uav_clken => open, -- (terminated)
av_clken => '1', -- (terminated)
uav_response => "00", -- (terminated)
av_response => open, -- (terminated)
uav_writeresponserequest => open, -- (terminated)
uav_writeresponsevalid => '0', -- (terminated)
av_writeresponserequest => '0', -- (terminated)
av_writeresponsevalid => open -- (terminated)
);
nios2_qsys_0_jtag_debug_module_translator : component niosii_system_nios2_qsys_0_jtag_debug_module_translator
generic map (
AV_ADDRESS_W => 9,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_write, -- .write
av_read => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_read, -- .read
av_readdata => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_waitrequest => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_debugaccess => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess, -- .debugaccess
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
sdram_0_s1_translator : component niosii_system_sdram_0_s1_translator
generic map (
AV_ADDRESS_W => 22,
AV_DATA_W => 16,
UAV_DATA_W => 16,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 2,
UAV_BYTEENABLE_W => 2,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 2,
AV_READLATENCY => 0,
USE_READDATAVALID => 1,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 2,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => sdram_0_s1_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => sdram_0_s1_translator_avalon_anti_slave_0_write, -- .write
av_read => sdram_0_s1_translator_avalon_anti_slave_0_read, -- .read
av_readdata => sdram_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => sdram_0_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => sdram_0_s1_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_readdatavalid => sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid, -- .readdatavalid
av_waitrequest => sdram_0_s1_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_chipselect => sdram_0_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
onchip_memory2_0_s1_translator : component niosii_system_onchip_memory2_0_s1_translator
generic map (
AV_ADDRESS_W => 12,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 1,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 0,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => onchip_memory2_0_s1_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => onchip_memory2_0_s1_translator_avalon_anti_slave_0_write, -- .write
av_readdata => onchip_memory2_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => onchip_memory2_0_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => onchip_memory2_0_s1_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_chipselect => onchip_memory2_0_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
av_clken => onchip_memory2_0_s1_translator_avalon_anti_slave_0_clken, -- .clken
av_read => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
sram_0_avalon_sram_slave_translator : component niosii_system_sram_0_avalon_sram_slave_translator
generic map (
AV_ADDRESS_W => 18,
AV_DATA_W => 16,
UAV_DATA_W => 16,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 2,
UAV_BYTEENABLE_W => 2,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 2,
AV_READLATENCY => 0,
USE_READDATAVALID => 1,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 2,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 0,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_write, -- .write
av_read => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_read, -- .read
av_readdata => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_readdatavalid => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdatavalid, -- .readdatavalid
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
generic_tristate_controller_0_uas_translator : component niosii_system_generic_tristate_controller_0_uas_translator
generic map (
AV_ADDRESS_W => 22,
AV_DATA_W => 8,
UAV_DATA_W => 8,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 1,
UAV_BYTEENABLE_W => 1,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 1,
AV_READLATENCY => 0,
USE_READDATAVALID => 1,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 1,
AV_ADDRESS_SYMBOLS => 1,
AV_BURSTCOUNT_SYMBOLS => 1,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 0,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_write, -- .write
av_read => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_read, -- .read
av_readdata => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_writedata, -- .writedata
av_burstcount => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_burstcount, -- .burstcount
av_byteenable => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_readdatavalid => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_readdatavalid, -- .readdatavalid
av_waitrequest => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_lock => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_lock, -- .lock
av_debugaccess => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_debugaccess, -- .debugaccess
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_writebyteenable => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
jtag_uart_0_avalon_jtag_slave_translator : component niosii_system_jtag_uart_0_avalon_jtag_slave_translator
generic map (
AV_ADDRESS_W => 1,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 1,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write, -- .write
av_read => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read, -- .read
av_readdata => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_waitrequest => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_chipselect => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect, -- .chipselect
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
sysid_qsys_0_control_slave_translator : component niosii_system_sysid_qsys_0_control_slave_translator
generic map (
AV_ADDRESS_W => 1,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_readdata => sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_write => open, -- (terminated)
av_read => open, -- (terminated)
av_writedata => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
green_leds_s1_translator : component niosii_system_green_leds_s1_translator
generic map (
AV_ADDRESS_W => 2,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 1,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => green_leds_s1_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => green_leds_s1_translator_avalon_anti_slave_0_write, -- .write
av_readdata => green_leds_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => green_leds_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
av_chipselect => green_leds_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
av_read => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
switches_s1_translator : component niosii_system_switches_s1_translator
generic map (
AV_ADDRESS_W => 2,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 1,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => switches_s1_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => switches_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => switches_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => switches_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => switches_s1_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_readdata => switches_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
av_write => open, -- (terminated)
av_read => open, -- (terminated)
av_writedata => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
altpll_0_pll_slave_translator : component niosii_system_altpll_0_pll_slave_translator
generic map (
AV_ADDRESS_W => 2,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 0,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- reset.reset
uav_address => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => altpll_0_pll_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => altpll_0_pll_slave_translator_avalon_anti_slave_0_write, -- .write
av_read => altpll_0_pll_slave_translator_avalon_anti_slave_0_read, -- .read
av_readdata => altpll_0_pll_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => altpll_0_pll_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
timer_0_s1_translator : component niosii_system_timer_0_s1_translator
generic map (
AV_ADDRESS_W => 3,
AV_DATA_W => 16,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 1,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => timer_0_s1_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => timer_0_s1_translator_avalon_anti_slave_0_write, -- .write
av_readdata => timer_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => timer_0_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
av_chipselect => timer_0_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
av_read => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
usb_0_avalon_usb_slave_translator : component niosii_system_usb_0_avalon_usb_slave_translator
generic map (
AV_ADDRESS_W => 2,
AV_DATA_W => 16,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 1,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 5,
AV_WRITE_WAIT_CYCLES => 5,
AV_SETUP_WAIT_CYCLES => 5,
AV_DATA_HOLD_CYCLES => 5
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_write, -- .write
av_read => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_read, -- .read
av_readdata => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_chipselect => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_chipselect, -- .chipselect
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
rs232_0_avalon_rs232_slave_translator : component niosii_system_rs232_0_avalon_rs232_slave_translator
generic map (
AV_ADDRESS_W => 1,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 1,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 0,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_write, -- .write
av_read => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_read, -- .read
av_readdata => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_chipselect => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_chipselect, -- .chipselect
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent : component altera_merlin_master_agent
generic map (
PKT_PROTECTION_H => 93,
PKT_PROTECTION_L => 91,
PKT_BEGIN_BURST => 80,
PKT_BURSTWRAP_H => 72,
PKT_BURSTWRAP_L => 70,
PKT_BURST_SIZE_H => 75,
PKT_BURST_SIZE_L => 73,
PKT_BURST_TYPE_H => 77,
PKT_BURST_TYPE_L => 76,
PKT_BYTE_CNT_H => 69,
PKT_BYTE_CNT_L => 67,
PKT_ADDR_H => 60,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 61,
PKT_TRANS_POSTED => 62,
PKT_TRANS_WRITE => 63,
PKT_TRANS_READ => 64,
PKT_TRANS_LOCK => 65,
PKT_TRANS_EXCLUSIVE => 66,
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_SRC_ID_H => 85,
PKT_SRC_ID_L => 82,
PKT_DEST_ID_H => 89,
PKT_DEST_ID_L => 86,
PKT_THREAD_ID_H => 90,
PKT_THREAD_ID_L => 90,
PKT_CACHE_H => 97,
PKT_CACHE_L => 94,
PKT_DATA_SIDEBAND_H => 79,
PKT_DATA_SIDEBAND_L => 79,
PKT_QOS_H => 81,
PKT_QOS_L => 81,
PKT_ADDR_SIDEBAND_H => 78,
PKT_ADDR_SIDEBAND_L => 78,
PKT_RESPONSE_STATUS_H => 99,
PKT_RESPONSE_STATUS_L => 98,
ST_DATA_W => 100,
ST_CHANNEL_W => 13,
AV_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_RSP => 0,
ID => 1,
BURSTWRAP_VALUE => 3,
CACHE_VALUE => 0,
SECURE_ACCESS_BIT => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
av_address => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address, -- av.address
av_write => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write, -- .write
av_read => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read, -- .read
av_writedata => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata, -- .writedata
av_readdata => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata, -- .readdata
av_waitrequest => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
av_readdatavalid => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
av_byteenable => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
av_burstcount => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
av_debugaccess => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_lock => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock, -- .lock
cp_valid => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_valid, -- cp.valid
cp_data => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
cp_startofpacket => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
cp_endofpacket => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
cp_ready => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_ready, -- .ready
rp_valid => rsp_xbar_mux_src_valid, -- rp.valid
rp_data => rsp_xbar_mux_src_data, -- .data
rp_channel => rsp_xbar_mux_src_channel, -- .channel
rp_startofpacket => rsp_xbar_mux_src_startofpacket, -- .startofpacket
rp_endofpacket => rsp_xbar_mux_src_endofpacket, -- .endofpacket
rp_ready => rsp_xbar_mux_src_ready, -- .ready
av_response => open, -- (terminated)
av_writeresponserequest => '0', -- (terminated)
av_writeresponsevalid => open -- (terminated)
);
nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent : component altera_merlin_master_agent
generic map (
PKT_PROTECTION_H => 93,
PKT_PROTECTION_L => 91,
PKT_BEGIN_BURST => 80,
PKT_BURSTWRAP_H => 72,
PKT_BURSTWRAP_L => 70,
PKT_BURST_SIZE_H => 75,
PKT_BURST_SIZE_L => 73,
PKT_BURST_TYPE_H => 77,
PKT_BURST_TYPE_L => 76,
PKT_BYTE_CNT_H => 69,
PKT_BYTE_CNT_L => 67,
PKT_ADDR_H => 60,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 61,
PKT_TRANS_POSTED => 62,
PKT_TRANS_WRITE => 63,
PKT_TRANS_READ => 64,
PKT_TRANS_LOCK => 65,
PKT_TRANS_EXCLUSIVE => 66,
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_SRC_ID_H => 85,
PKT_SRC_ID_L => 82,
PKT_DEST_ID_H => 89,
PKT_DEST_ID_L => 86,
PKT_THREAD_ID_H => 90,
PKT_THREAD_ID_L => 90,
PKT_CACHE_H => 97,
PKT_CACHE_L => 94,
PKT_DATA_SIDEBAND_H => 79,
PKT_DATA_SIDEBAND_L => 79,
PKT_QOS_H => 81,
PKT_QOS_L => 81,
PKT_ADDR_SIDEBAND_H => 78,
PKT_ADDR_SIDEBAND_L => 78,
PKT_RESPONSE_STATUS_H => 99,
PKT_RESPONSE_STATUS_L => 98,
ST_DATA_W => 100,
ST_CHANNEL_W => 13,
AV_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_RSP => 0,
ID => 0,
BURSTWRAP_VALUE => 7,
CACHE_VALUE => 0,
SECURE_ACCESS_BIT => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
av_address => nios2_qsys_0_data_master_translator_avalon_universal_master_0_address, -- av.address
av_write => nios2_qsys_0_data_master_translator_avalon_universal_master_0_write, -- .write
av_read => nios2_qsys_0_data_master_translator_avalon_universal_master_0_read, -- .read
av_writedata => nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata, -- .writedata
av_readdata => nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata, -- .readdata
av_waitrequest => nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
av_readdatavalid => nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
av_byteenable => nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
av_burstcount => nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
av_debugaccess => nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_lock => nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock, -- .lock
cp_valid => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_valid, -- cp.valid
cp_data => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
cp_startofpacket => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
cp_endofpacket => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
cp_ready => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_ready, -- .ready
rp_valid => rsp_xbar_mux_001_src_valid, -- rp.valid
rp_data => rsp_xbar_mux_001_src_data, -- .data
rp_channel => rsp_xbar_mux_001_src_channel, -- .channel
rp_startofpacket => rsp_xbar_mux_001_src_startofpacket, -- .startofpacket
rp_endofpacket => rsp_xbar_mux_001_src_endofpacket, -- .endofpacket
rp_ready => rsp_xbar_mux_001_src_ready, -- .ready
av_response => open, -- (terminated)
av_writeresponserequest => '0', -- (terminated)
av_writeresponsevalid => open -- (terminated)
);
nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 80,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 60,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 61,
PKT_TRANS_POSTED => 62,
PKT_TRANS_WRITE => 63,
PKT_TRANS_READ => 64,
PKT_TRANS_LOCK => 65,
PKT_SRC_ID_H => 85,
PKT_SRC_ID_L => 82,
PKT_DEST_ID_H => 89,
PKT_DEST_ID_L => 86,
PKT_BURSTWRAP_H => 72,
PKT_BURSTWRAP_L => 70,
PKT_BYTE_CNT_H => 69,
PKT_BYTE_CNT_L => 67,
PKT_PROTECTION_H => 93,
PKT_PROTECTION_L => 91,
PKT_RESPONSE_STATUS_H => 99,
PKT_RESPONSE_STATUS_L => 98,
PKT_BURST_SIZE_H => 75,
PKT_BURST_SIZE_L => 73,
ST_CHANNEL_W => 13,
ST_DATA_W => 100,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_mux_src_ready, -- cp.ready
cp_valid => cmd_xbar_mux_src_valid, -- .valid
cp_data => cmd_xbar_mux_src_data, -- .data
cp_startofpacket => cmd_xbar_mux_src_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_mux_src_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_mux_src_channel, -- .channel
rf_sink_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 101,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
sdram_0_s1_translator_avalon_universal_slave_0_agent : component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent
generic map (
PKT_DATA_H => 15,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 62,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 17,
PKT_BYTEEN_L => 16,
PKT_ADDR_H => 42,
PKT_ADDR_L => 18,
PKT_TRANS_COMPRESSED_READ => 43,
PKT_TRANS_POSTED => 44,
PKT_TRANS_WRITE => 45,
PKT_TRANS_READ => 46,
PKT_TRANS_LOCK => 47,
PKT_SRC_ID_H => 67,
PKT_SRC_ID_L => 64,
PKT_DEST_ID_H => 71,
PKT_DEST_ID_L => 68,
PKT_BURSTWRAP_H => 54,
PKT_BURSTWRAP_L => 52,
PKT_BYTE_CNT_H => 51,
PKT_BYTE_CNT_L => 49,
PKT_PROTECTION_H => 75,
PKT_PROTECTION_L => 73,
PKT_RESPONSE_STATUS_H => 81,
PKT_RESPONSE_STATUS_L => 80,
PKT_BURST_SIZE_H => 57,
PKT_BURST_SIZE_L => 55,
ST_CHANNEL_W => 13,
ST_DATA_W => 82,
AVS_BURSTCOUNT_W => 2,
SUPPRESS_0_BYTEEN_CMD => 1,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => burst_adapter_source0_ready, -- cp.ready
cp_valid => burst_adapter_source0_valid, -- .valid
cp_data => burst_adapter_source0_data, -- .data
cp_startofpacket => burst_adapter_source0_startofpacket, -- .startofpacket
cp_endofpacket => burst_adapter_source0_endofpacket, -- .endofpacket
cp_channel => burst_adapter_source0_channel, -- .channel
rf_sink_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid, -- .valid
rdata_fifo_sink_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data, -- .data
rdata_fifo_src_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 83,
FIFO_DEPTH => 8,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo : component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 18,
FIFO_DEPTH => 8,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 0,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 3,
USE_MEMORY_BLOCKS => 1,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- in.data
in_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
in_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- .ready
out_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data, -- out.data
out_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid, -- .valid
out_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready, -- .ready
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_startofpacket => '0', -- (terminated)
in_endofpacket => '0', -- (terminated)
out_startofpacket => open, -- (terminated)
out_endofpacket => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 80,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 60,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 61,
PKT_TRANS_POSTED => 62,
PKT_TRANS_WRITE => 63,
PKT_TRANS_READ => 64,
PKT_TRANS_LOCK => 65,
PKT_SRC_ID_H => 85,
PKT_SRC_ID_L => 82,
PKT_DEST_ID_H => 89,
PKT_DEST_ID_L => 86,
PKT_BURSTWRAP_H => 72,
PKT_BURSTWRAP_L => 70,
PKT_BYTE_CNT_H => 69,
PKT_BYTE_CNT_L => 67,
PKT_PROTECTION_H => 93,
PKT_PROTECTION_L => 91,
PKT_RESPONSE_STATUS_H => 99,
PKT_RESPONSE_STATUS_L => 98,
PKT_BURST_SIZE_H => 75,
PKT_BURST_SIZE_L => 73,
ST_CHANNEL_W => 13,
ST_DATA_W => 100,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_mux_002_src_ready, -- cp.ready
cp_valid => cmd_xbar_mux_002_src_valid, -- .valid
cp_data => cmd_xbar_mux_002_src_data, -- .data
cp_startofpacket => cmd_xbar_mux_002_src_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_mux_002_src_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_mux_002_src_channel, -- .channel
rf_sink_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 101,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent : component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent
generic map (
PKT_DATA_H => 15,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 62,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 17,
PKT_BYTEEN_L => 16,
PKT_ADDR_H => 42,
PKT_ADDR_L => 18,
PKT_TRANS_COMPRESSED_READ => 43,
PKT_TRANS_POSTED => 44,
PKT_TRANS_WRITE => 45,
PKT_TRANS_READ => 46,
PKT_TRANS_LOCK => 47,
PKT_SRC_ID_H => 67,
PKT_SRC_ID_L => 64,
PKT_DEST_ID_H => 71,
PKT_DEST_ID_L => 68,
PKT_BURSTWRAP_H => 54,
PKT_BURSTWRAP_L => 52,
PKT_BYTE_CNT_H => 51,
PKT_BYTE_CNT_L => 49,
PKT_PROTECTION_H => 75,
PKT_PROTECTION_L => 73,
PKT_RESPONSE_STATUS_H => 81,
PKT_RESPONSE_STATUS_L => 80,
PKT_BURST_SIZE_H => 57,
PKT_BURST_SIZE_L => 55,
ST_CHANNEL_W => 13,
ST_DATA_W => 82,
AVS_BURSTCOUNT_W => 2,
SUPPRESS_0_BYTEEN_CMD => 1,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => burst_adapter_001_source0_ready, -- cp.ready
cp_valid => burst_adapter_001_source0_valid, -- .valid
cp_data => burst_adapter_001_source0_data, -- .data
cp_startofpacket => burst_adapter_001_source0_startofpacket, -- .startofpacket
cp_endofpacket => burst_adapter_001_source0_endofpacket, -- .endofpacket
cp_channel => burst_adapter_001_source0_channel, -- .channel
rf_sink_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid, -- .valid
rdata_fifo_sink_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data, -- .data
rdata_fifo_src_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 83,
FIFO_DEPTH => 3,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo : component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 18,
FIFO_DEPTH => 3,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 0,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 0,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- in.data
in_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
in_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- .ready
out_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data, -- out.data
out_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid, -- .valid
out_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready, -- .ready
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_startofpacket => '0', -- (terminated)
in_endofpacket => '0', -- (terminated)
out_startofpacket => open, -- (terminated)
out_endofpacket => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent : component niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent
generic map (
PKT_DATA_H => 7,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 53,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 8,
PKT_BYTEEN_L => 8,
PKT_ADDR_H => 33,
PKT_ADDR_L => 9,
PKT_TRANS_COMPRESSED_READ => 34,
PKT_TRANS_POSTED => 35,
PKT_TRANS_WRITE => 36,
PKT_TRANS_READ => 37,
PKT_TRANS_LOCK => 38,
PKT_SRC_ID_H => 58,
PKT_SRC_ID_L => 55,
PKT_DEST_ID_H => 62,
PKT_DEST_ID_L => 59,
PKT_BURSTWRAP_H => 45,
PKT_BURSTWRAP_L => 43,
PKT_BYTE_CNT_H => 42,
PKT_BYTE_CNT_L => 40,
PKT_PROTECTION_H => 66,
PKT_PROTECTION_L => 64,
PKT_RESPONSE_STATUS_H => 72,
PKT_RESPONSE_STATUS_L => 71,
PKT_BURST_SIZE_H => 48,
PKT_BURST_SIZE_L => 46,
ST_CHANNEL_W => 13,
ST_DATA_W => 73,
AVS_BURSTCOUNT_W => 1,
SUPPRESS_0_BYTEEN_CMD => 1,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => burst_adapter_002_source0_ready, -- cp.ready
cp_valid => burst_adapter_002_source0_valid, -- .valid
cp_data => burst_adapter_002_source0_data, -- .data
cp_startofpacket => burst_adapter_002_source0_startofpacket, -- .startofpacket
cp_endofpacket => burst_adapter_002_source0_endofpacket, -- .endofpacket
cp_channel => burst_adapter_002_source0_channel, -- .channel
rf_sink_ready => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid, -- .valid
rdata_fifo_sink_data => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data, -- .data
rdata_fifo_src_ready => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 74,
FIFO_DEPTH => 4,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo : component niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 10,
FIFO_DEPTH => 4,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 0,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 0,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- in.data
in_valid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
in_ready => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- .ready
out_data => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data, -- out.data
out_valid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid, -- .valid
out_ready => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready, -- .ready
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_startofpacket => '0', -- (terminated)
in_endofpacket => '0', -- (terminated)
out_startofpacket => open, -- (terminated)
out_endofpacket => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 80,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 60,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 61,
PKT_TRANS_POSTED => 62,
PKT_TRANS_WRITE => 63,
PKT_TRANS_READ => 64,
PKT_TRANS_LOCK => 65,
PKT_SRC_ID_H => 85,
PKT_SRC_ID_L => 82,
PKT_DEST_ID_H => 89,
PKT_DEST_ID_L => 86,
PKT_BURSTWRAP_H => 72,
PKT_BURSTWRAP_L => 70,
PKT_BYTE_CNT_H => 69,
PKT_BYTE_CNT_L => 67,
PKT_PROTECTION_H => 93,
PKT_PROTECTION_L => 91,
PKT_RESPONSE_STATUS_H => 99,
PKT_RESPONSE_STATUS_L => 98,
PKT_BURST_SIZE_H => 75,
PKT_BURST_SIZE_L => 73,
ST_CHANNEL_W => 13,
ST_DATA_W => 100,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_demux_001_src5_ready, -- cp.ready
cp_valid => cmd_xbar_demux_001_src5_valid, -- .valid
cp_data => cmd_xbar_demux_001_src5_data, -- .data
cp_startofpacket => cmd_xbar_demux_001_src5_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_demux_001_src5_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_demux_001_src5_channel, -- .channel
rf_sink_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 101,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 80,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 60,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 61,
PKT_TRANS_POSTED => 62,
PKT_TRANS_WRITE => 63,
PKT_TRANS_READ => 64,
PKT_TRANS_LOCK => 65,
PKT_SRC_ID_H => 85,
PKT_SRC_ID_L => 82,
PKT_DEST_ID_H => 89,
PKT_DEST_ID_L => 86,
PKT_BURSTWRAP_H => 72,
PKT_BURSTWRAP_L => 70,
PKT_BYTE_CNT_H => 69,
PKT_BYTE_CNT_L => 67,
PKT_PROTECTION_H => 93,
PKT_PROTECTION_L => 91,
PKT_RESPONSE_STATUS_H => 99,
PKT_RESPONSE_STATUS_L => 98,
PKT_BURST_SIZE_H => 75,
PKT_BURST_SIZE_L => 73,
ST_CHANNEL_W => 13,
ST_DATA_W => 100,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_demux_001_src6_ready, -- cp.ready
cp_valid => cmd_xbar_demux_001_src6_valid, -- .valid
cp_data => cmd_xbar_demux_001_src6_data, -- .data
cp_startofpacket => cmd_xbar_demux_001_src6_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_demux_001_src6_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_demux_001_src6_channel, -- .channel
rf_sink_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 101,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
green_leds_s1_translator_avalon_universal_slave_0_agent : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 80,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 60,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 61,
PKT_TRANS_POSTED => 62,
PKT_TRANS_WRITE => 63,
PKT_TRANS_READ => 64,
PKT_TRANS_LOCK => 65,
PKT_SRC_ID_H => 85,
PKT_SRC_ID_L => 82,
PKT_DEST_ID_H => 89,
PKT_DEST_ID_L => 86,
PKT_BURSTWRAP_H => 72,
PKT_BURSTWRAP_L => 70,
PKT_BYTE_CNT_H => 69,
PKT_BYTE_CNT_L => 67,
PKT_PROTECTION_H => 93,
PKT_PROTECTION_L => 91,
PKT_RESPONSE_STATUS_H => 99,
PKT_RESPONSE_STATUS_L => 98,
PKT_BURST_SIZE_H => 75,
PKT_BURST_SIZE_L => 73,
ST_CHANNEL_W => 13,
ST_DATA_W => 100,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_demux_001_src7_ready, -- cp.ready
cp_valid => cmd_xbar_demux_001_src7_valid, -- .valid
cp_data => cmd_xbar_demux_001_src7_data, -- .data
cp_startofpacket => cmd_xbar_demux_001_src7_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_demux_001_src7_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_demux_001_src7_channel, -- .channel
rf_sink_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 101,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
switches_s1_translator_avalon_universal_slave_0_agent : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 80,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 60,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 61,
PKT_TRANS_POSTED => 62,
PKT_TRANS_WRITE => 63,
PKT_TRANS_READ => 64,
PKT_TRANS_LOCK => 65,
PKT_SRC_ID_H => 85,
PKT_SRC_ID_L => 82,
PKT_DEST_ID_H => 89,
PKT_DEST_ID_L => 86,
PKT_BURSTWRAP_H => 72,
PKT_BURSTWRAP_L => 70,
PKT_BYTE_CNT_H => 69,
PKT_BYTE_CNT_L => 67,
PKT_PROTECTION_H => 93,
PKT_PROTECTION_L => 91,
PKT_RESPONSE_STATUS_H => 99,
PKT_RESPONSE_STATUS_L => 98,
PKT_BURST_SIZE_H => 75,
PKT_BURST_SIZE_L => 73,
ST_CHANNEL_W => 13,
ST_DATA_W => 100,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => switches_s1_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => switches_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => switches_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => switches_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => switches_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => switches_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => switches_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_demux_001_src8_ready, -- cp.ready
cp_valid => cmd_xbar_demux_001_src8_valid, -- .valid
cp_data => cmd_xbar_demux_001_src8_data, -- .data
cp_startofpacket => cmd_xbar_demux_001_src8_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_demux_001_src8_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_demux_001_src8_channel, -- .channel
rf_sink_ready => switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 101,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
altpll_0_pll_slave_translator_avalon_universal_slave_0_agent : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 80,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 60,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 61,
PKT_TRANS_POSTED => 62,
PKT_TRANS_WRITE => 63,
PKT_TRANS_READ => 64,
PKT_TRANS_LOCK => 65,
PKT_SRC_ID_H => 85,
PKT_SRC_ID_L => 82,
PKT_DEST_ID_H => 89,
PKT_DEST_ID_L => 86,
PKT_BURSTWRAP_H => 72,
PKT_BURSTWRAP_L => 70,
PKT_BYTE_CNT_H => 69,
PKT_BYTE_CNT_L => 67,
PKT_PROTECTION_H => 93,
PKT_PROTECTION_L => 91,
PKT_RESPONSE_STATUS_H => 99,
PKT_RESPONSE_STATUS_L => 98,
PKT_BURST_SIZE_H => 75,
PKT_BURST_SIZE_L => 73,
ST_CHANNEL_W => 13,
ST_DATA_W => 100,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
m0_address => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => crosser_out_ready, -- cp.ready
cp_valid => crosser_out_valid, -- .valid
cp_data => crosser_out_data, -- .data
cp_startofpacket => crosser_out_startofpacket, -- .startofpacket
cp_endofpacket => crosser_out_endofpacket, -- .endofpacket
cp_channel => crosser_out_channel, -- .channel
rf_sink_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid, -- .valid
rdata_fifo_sink_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data, -- .data
rdata_fifo_src_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 101,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo : component niosii_system_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 34,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 0,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 0,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- in.data
in_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
in_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- .ready
out_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data, -- out.data
out_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid, -- .valid
out_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready, -- .ready
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_startofpacket => '0', -- (terminated)
in_endofpacket => '0', -- (terminated)
out_startofpacket => open, -- (terminated)
out_endofpacket => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
timer_0_s1_translator_avalon_universal_slave_0_agent : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 80,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 60,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 61,
PKT_TRANS_POSTED => 62,
PKT_TRANS_WRITE => 63,
PKT_TRANS_READ => 64,
PKT_TRANS_LOCK => 65,
PKT_SRC_ID_H => 85,
PKT_SRC_ID_L => 82,
PKT_DEST_ID_H => 89,
PKT_DEST_ID_L => 86,
PKT_BURSTWRAP_H => 72,
PKT_BURSTWRAP_L => 70,
PKT_BYTE_CNT_H => 69,
PKT_BYTE_CNT_L => 67,
PKT_PROTECTION_H => 93,
PKT_PROTECTION_L => 91,
PKT_RESPONSE_STATUS_H => 99,
PKT_RESPONSE_STATUS_L => 98,
PKT_BURST_SIZE_H => 75,
PKT_BURST_SIZE_L => 73,
ST_CHANNEL_W => 13,
ST_DATA_W => 100,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_demux_001_src10_ready, -- cp.ready
cp_valid => cmd_xbar_demux_001_src10_valid, -- .valid
cp_data => cmd_xbar_demux_001_src10_data, -- .data
cp_startofpacket => cmd_xbar_demux_001_src10_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_demux_001_src10_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_demux_001_src10_channel, -- .channel
rf_sink_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 101,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 80,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 60,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 61,
PKT_TRANS_POSTED => 62,
PKT_TRANS_WRITE => 63,
PKT_TRANS_READ => 64,
PKT_TRANS_LOCK => 65,
PKT_SRC_ID_H => 85,
PKT_SRC_ID_L => 82,
PKT_DEST_ID_H => 89,
PKT_DEST_ID_L => 86,
PKT_BURSTWRAP_H => 72,
PKT_BURSTWRAP_L => 70,
PKT_BYTE_CNT_H => 69,
PKT_BYTE_CNT_L => 67,
PKT_PROTECTION_H => 93,
PKT_PROTECTION_L => 91,
PKT_RESPONSE_STATUS_H => 99,
PKT_RESPONSE_STATUS_L => 98,
PKT_BURST_SIZE_H => 75,
PKT_BURST_SIZE_L => 73,
ST_CHANNEL_W => 13,
ST_DATA_W => 100,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_demux_001_src11_ready, -- cp.ready
cp_valid => cmd_xbar_demux_001_src11_valid, -- .valid
cp_data => cmd_xbar_demux_001_src11_data, -- .data
cp_startofpacket => cmd_xbar_demux_001_src11_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_demux_001_src11_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_demux_001_src11_channel, -- .channel
rf_sink_ready => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 101,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 80,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 60,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 61,
PKT_TRANS_POSTED => 62,
PKT_TRANS_WRITE => 63,
PKT_TRANS_READ => 64,
PKT_TRANS_LOCK => 65,
PKT_SRC_ID_H => 85,
PKT_SRC_ID_L => 82,
PKT_DEST_ID_H => 89,
PKT_DEST_ID_L => 86,
PKT_BURSTWRAP_H => 72,
PKT_BURSTWRAP_L => 70,
PKT_BYTE_CNT_H => 69,
PKT_BYTE_CNT_L => 67,
PKT_PROTECTION_H => 93,
PKT_PROTECTION_L => 91,
PKT_RESPONSE_STATUS_H => 99,
PKT_RESPONSE_STATUS_L => 98,
PKT_BURST_SIZE_H => 75,
PKT_BURST_SIZE_L => 73,
ST_CHANNEL_W => 13,
ST_DATA_W => 100,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_demux_001_src12_ready, -- cp.ready
cp_valid => cmd_xbar_demux_001_src12_valid, -- .valid
cp_data => cmd_xbar_demux_001_src12_data, -- .data
cp_startofpacket => cmd_xbar_demux_001_src12_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_demux_001_src12_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_demux_001_src12_channel, -- .channel
rf_sink_ready => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 101,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
addr_router : component niosII_system_addr_router
port map (
sink_ready => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_ready, -- sink.ready
sink_valid => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_valid, -- .valid
sink_data => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
sink_startofpacket => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
sink_endofpacket => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => addr_router_src_ready, -- src.ready
src_valid => addr_router_src_valid, -- .valid
src_data => addr_router_src_data, -- .data
src_channel => addr_router_src_channel, -- .channel
src_startofpacket => addr_router_src_startofpacket, -- .startofpacket
src_endofpacket => addr_router_src_endofpacket -- .endofpacket
);
addr_router_001 : component niosII_system_addr_router_001
port map (
sink_ready => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_ready, -- sink.ready
sink_valid => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_valid, -- .valid
sink_data => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
sink_startofpacket => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
sink_endofpacket => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => addr_router_001_src_ready, -- src.ready
src_valid => addr_router_001_src_valid, -- .valid
src_data => addr_router_001_src_data, -- .data
src_channel => addr_router_001_src_channel, -- .channel
src_startofpacket => addr_router_001_src_startofpacket, -- .startofpacket
src_endofpacket => addr_router_001_src_endofpacket -- .endofpacket
);
id_router : component niosII_system_id_router
port map (
sink_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_src_ready, -- src.ready
src_valid => id_router_src_valid, -- .valid
src_data => id_router_src_data, -- .data
src_channel => id_router_src_channel, -- .channel
src_startofpacket => id_router_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_src_endofpacket -- .endofpacket
);
id_router_001 : component niosII_system_id_router_001
port map (
sink_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_001_src_ready, -- src.ready
src_valid => id_router_001_src_valid, -- .valid
src_data => id_router_001_src_data, -- .data
src_channel => id_router_001_src_channel, -- .channel
src_startofpacket => id_router_001_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_001_src_endofpacket -- .endofpacket
);
id_router_002 : component niosII_system_id_router
port map (
sink_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_002_src_ready, -- src.ready
src_valid => id_router_002_src_valid, -- .valid
src_data => id_router_002_src_data, -- .data
src_channel => id_router_002_src_channel, -- .channel
src_startofpacket => id_router_002_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_002_src_endofpacket -- .endofpacket
);
id_router_003 : component niosII_system_id_router_001
port map (
sink_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_003_src_ready, -- src.ready
src_valid => id_router_003_src_valid, -- .valid
src_data => id_router_003_src_data, -- .data
src_channel => id_router_003_src_channel, -- .channel
src_startofpacket => id_router_003_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_003_src_endofpacket -- .endofpacket
);
id_router_004 : component niosII_system_id_router_004
port map (
sink_ready => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_004_src_ready, -- src.ready
src_valid => id_router_004_src_valid, -- .valid
src_data => id_router_004_src_data, -- .data
src_channel => id_router_004_src_channel, -- .channel
src_startofpacket => id_router_004_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_004_src_endofpacket -- .endofpacket
);
id_router_005 : component niosII_system_id_router_005
port map (
sink_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_005_src_ready, -- src.ready
src_valid => id_router_005_src_valid, -- .valid
src_data => id_router_005_src_data, -- .data
src_channel => id_router_005_src_channel, -- .channel
src_startofpacket => id_router_005_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_005_src_endofpacket -- .endofpacket
);
id_router_006 : component niosII_system_id_router_005
port map (
sink_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_006_src_ready, -- src.ready
src_valid => id_router_006_src_valid, -- .valid
src_data => id_router_006_src_data, -- .data
src_channel => id_router_006_src_channel, -- .channel
src_startofpacket => id_router_006_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_006_src_endofpacket -- .endofpacket
);
id_router_007 : component niosII_system_id_router_005
port map (
sink_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_007_src_ready, -- src.ready
src_valid => id_router_007_src_valid, -- .valid
src_data => id_router_007_src_data, -- .data
src_channel => id_router_007_src_channel, -- .channel
src_startofpacket => id_router_007_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_007_src_endofpacket -- .endofpacket
);
id_router_008 : component niosII_system_id_router_005
port map (
sink_ready => switches_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => switches_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => switches_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_008_src_ready, -- src.ready
src_valid => id_router_008_src_valid, -- .valid
src_data => id_router_008_src_data, -- .data
src_channel => id_router_008_src_channel, -- .channel
src_startofpacket => id_router_008_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_008_src_endofpacket -- .endofpacket
);
id_router_009 : component niosII_system_id_router_005
port map (
sink_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => clk_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
src_ready => id_router_009_src_ready, -- src.ready
src_valid => id_router_009_src_valid, -- .valid
src_data => id_router_009_src_data, -- .data
src_channel => id_router_009_src_channel, -- .channel
src_startofpacket => id_router_009_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_009_src_endofpacket -- .endofpacket
);
id_router_010 : component niosII_system_id_router_005
port map (
sink_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_010_src_ready, -- src.ready
src_valid => id_router_010_src_valid, -- .valid
src_data => id_router_010_src_data, -- .data
src_channel => id_router_010_src_channel, -- .channel
src_startofpacket => id_router_010_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_010_src_endofpacket -- .endofpacket
);
id_router_011 : component niosII_system_id_router_005
port map (
sink_ready => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_011_src_ready, -- src.ready
src_valid => id_router_011_src_valid, -- .valid
src_data => id_router_011_src_data, -- .data
src_channel => id_router_011_src_channel, -- .channel
src_startofpacket => id_router_011_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_011_src_endofpacket -- .endofpacket
);
id_router_012 : component niosII_system_id_router_005
port map (
sink_ready => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_012_src_ready, -- src.ready
src_valid => id_router_012_src_valid, -- .valid
src_data => id_router_012_src_data, -- .data
src_channel => id_router_012_src_channel, -- .channel
src_startofpacket => id_router_012_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_012_src_endofpacket -- .endofpacket
);
burst_adapter : component niosii_system_burst_adapter
generic map (
PKT_ADDR_H => 42,
PKT_ADDR_L => 18,
PKT_BEGIN_BURST => 62,
PKT_BYTE_CNT_H => 51,
PKT_BYTE_CNT_L => 49,
PKT_BYTEEN_H => 17,
PKT_BYTEEN_L => 16,
PKT_BURST_SIZE_H => 57,
PKT_BURST_SIZE_L => 55,
PKT_BURST_TYPE_H => 59,
PKT_BURST_TYPE_L => 58,
PKT_BURSTWRAP_H => 54,
PKT_BURSTWRAP_L => 52,
PKT_TRANS_COMPRESSED_READ => 43,
PKT_TRANS_WRITE => 45,
PKT_TRANS_READ => 46,
OUT_NARROW_SIZE => 0,
IN_NARROW_SIZE => 0,
OUT_FIXED => 0,
OUT_COMPLETE_WRAP => 0,
ST_DATA_W => 82,
ST_CHANNEL_W => 13,
OUT_BYTE_CNT_H => 50,
OUT_BURSTWRAP_H => 54,
COMPRESSED_READ_SUPPORT => 0,
BYTEENABLE_SYNTHESIS => 1,
PIPE_INPUTS => 0,
NO_WRAP_SUPPORT => 0,
BURSTWRAP_CONST_MASK => 3,
BURSTWRAP_CONST_VALUE => 3
)
port map (
clk => altpll_0_c1_clk, -- cr0.clk
reset => rst_controller_reset_out_reset, -- cr0_reset.reset
sink0_valid => width_adapter_src_valid, -- sink0.valid
sink0_data => width_adapter_src_data, -- .data
sink0_channel => width_adapter_src_channel, -- .channel
sink0_startofpacket => width_adapter_src_startofpacket, -- .startofpacket
sink0_endofpacket => width_adapter_src_endofpacket, -- .endofpacket
sink0_ready => width_adapter_src_ready, -- .ready
source0_valid => burst_adapter_source0_valid, -- source0.valid
source0_data => burst_adapter_source0_data, -- .data
source0_channel => burst_adapter_source0_channel, -- .channel
source0_startofpacket => burst_adapter_source0_startofpacket, -- .startofpacket
source0_endofpacket => burst_adapter_source0_endofpacket, -- .endofpacket
source0_ready => burst_adapter_source0_ready -- .ready
);
burst_adapter_001 : component niosii_system_burst_adapter
generic map (
PKT_ADDR_H => 42,
PKT_ADDR_L => 18,
PKT_BEGIN_BURST => 62,
PKT_BYTE_CNT_H => 51,
PKT_BYTE_CNT_L => 49,
PKT_BYTEEN_H => 17,
PKT_BYTEEN_L => 16,
PKT_BURST_SIZE_H => 57,
PKT_BURST_SIZE_L => 55,
PKT_BURST_TYPE_H => 59,
PKT_BURST_TYPE_L => 58,
PKT_BURSTWRAP_H => 54,
PKT_BURSTWRAP_L => 52,
PKT_TRANS_COMPRESSED_READ => 43,
PKT_TRANS_WRITE => 45,
PKT_TRANS_READ => 46,
OUT_NARROW_SIZE => 0,
IN_NARROW_SIZE => 0,
OUT_FIXED => 0,
OUT_COMPLETE_WRAP => 0,
ST_DATA_W => 82,
ST_CHANNEL_W => 13,
OUT_BYTE_CNT_H => 50,
OUT_BURSTWRAP_H => 54,
COMPRESSED_READ_SUPPORT => 0,
BYTEENABLE_SYNTHESIS => 1,
PIPE_INPUTS => 0,
NO_WRAP_SUPPORT => 0,
BURSTWRAP_CONST_MASK => 3,
BURSTWRAP_CONST_VALUE => 3
)
port map (
clk => altpll_0_c1_clk, -- cr0.clk
reset => rst_controller_reset_out_reset, -- cr0_reset.reset
sink0_valid => width_adapter_002_src_valid, -- sink0.valid
sink0_data => width_adapter_002_src_data, -- .data
sink0_channel => width_adapter_002_src_channel, -- .channel
sink0_startofpacket => width_adapter_002_src_startofpacket, -- .startofpacket
sink0_endofpacket => width_adapter_002_src_endofpacket, -- .endofpacket
sink0_ready => width_adapter_002_src_ready, -- .ready
source0_valid => burst_adapter_001_source0_valid, -- source0.valid
source0_data => burst_adapter_001_source0_data, -- .data
source0_channel => burst_adapter_001_source0_channel, -- .channel
source0_startofpacket => burst_adapter_001_source0_startofpacket, -- .startofpacket
source0_endofpacket => burst_adapter_001_source0_endofpacket, -- .endofpacket
source0_ready => burst_adapter_001_source0_ready -- .ready
);
burst_adapter_002 : component niosii_system_burst_adapter_002
generic map (
PKT_ADDR_H => 33,
PKT_ADDR_L => 9,
PKT_BEGIN_BURST => 53,
PKT_BYTE_CNT_H => 42,
PKT_BYTE_CNT_L => 40,
PKT_BYTEEN_H => 8,
PKT_BYTEEN_L => 8,
PKT_BURST_SIZE_H => 48,
PKT_BURST_SIZE_L => 46,
PKT_BURST_TYPE_H => 50,
PKT_BURST_TYPE_L => 49,
PKT_BURSTWRAP_H => 45,
PKT_BURSTWRAP_L => 43,
PKT_TRANS_COMPRESSED_READ => 34,
PKT_TRANS_WRITE => 36,
PKT_TRANS_READ => 37,
OUT_NARROW_SIZE => 0,
IN_NARROW_SIZE => 0,
OUT_FIXED => 0,
OUT_COMPLETE_WRAP => 0,
ST_DATA_W => 73,
ST_CHANNEL_W => 13,
OUT_BYTE_CNT_H => 40,
OUT_BURSTWRAP_H => 45,
COMPRESSED_READ_SUPPORT => 0,
BYTEENABLE_SYNTHESIS => 1,
PIPE_INPUTS => 0,
NO_WRAP_SUPPORT => 0,
BURSTWRAP_CONST_MASK => 3,
BURSTWRAP_CONST_VALUE => 3
)
port map (
clk => altpll_0_c1_clk, -- cr0.clk
reset => rst_controller_reset_out_reset, -- cr0_reset.reset
sink0_valid => width_adapter_004_src_valid, -- sink0.valid
sink0_data => width_adapter_004_src_data, -- .data
sink0_channel => width_adapter_004_src_channel, -- .channel
sink0_startofpacket => width_adapter_004_src_startofpacket, -- .startofpacket
sink0_endofpacket => width_adapter_004_src_endofpacket, -- .endofpacket
sink0_ready => width_adapter_004_src_ready, -- .ready
source0_valid => burst_adapter_002_source0_valid, -- source0.valid
source0_data => burst_adapter_002_source0_data, -- .data
source0_channel => burst_adapter_002_source0_channel, -- .channel
source0_startofpacket => burst_adapter_002_source0_startofpacket, -- .startofpacket
source0_endofpacket => burst_adapter_002_source0_endofpacket, -- .endofpacket
source0_ready => burst_adapter_002_source0_ready -- .ready
);
rst_controller : component niosii_system_rst_controller
generic map (
NUM_RESET_INPUTS => 2,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 1
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
reset_in1 => nios2_qsys_0_jtag_debug_module_reset_reset, -- reset_in1.reset
clk => altpll_0_c1_clk, -- clk.clk
reset_out => rst_controller_reset_out_reset, -- reset_out.reset
reset_req => rst_controller_reset_out_reset_req, -- .reset_req
reset_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_in15 => '0' -- (terminated)
);
rst_controller_001 : component niosii_system_rst_controller_001
generic map (
NUM_RESET_INPUTS => 2,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
reset_in1 => nios2_qsys_0_jtag_debug_module_reset_reset, -- reset_in1.reset
clk => clk_clk, -- clk.clk
reset_out => rst_controller_001_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_in15 => '0' -- (terminated)
);
cmd_xbar_demux : component niosII_system_cmd_xbar_demux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => addr_router_src_ready, -- sink.ready
sink_channel => addr_router_src_channel, -- .channel
sink_data => addr_router_src_data, -- .data
sink_startofpacket => addr_router_src_startofpacket, -- .startofpacket
sink_endofpacket => addr_router_src_endofpacket, -- .endofpacket
sink_valid(0) => addr_router_src_valid, -- .valid
src0_ready => cmd_xbar_demux_src0_ready, -- src0.ready
src0_valid => cmd_xbar_demux_src0_valid, -- .valid
src0_data => cmd_xbar_demux_src0_data, -- .data
src0_channel => cmd_xbar_demux_src0_channel, -- .channel
src0_startofpacket => cmd_xbar_demux_src0_startofpacket, -- .startofpacket
src0_endofpacket => cmd_xbar_demux_src0_endofpacket, -- .endofpacket
src1_ready => cmd_xbar_demux_src1_ready, -- src1.ready
src1_valid => cmd_xbar_demux_src1_valid, -- .valid
src1_data => cmd_xbar_demux_src1_data, -- .data
src1_channel => cmd_xbar_demux_src1_channel, -- .channel
src1_startofpacket => cmd_xbar_demux_src1_startofpacket, -- .startofpacket
src1_endofpacket => cmd_xbar_demux_src1_endofpacket, -- .endofpacket
src2_ready => cmd_xbar_demux_src2_ready, -- src2.ready
src2_valid => cmd_xbar_demux_src2_valid, -- .valid
src2_data => cmd_xbar_demux_src2_data, -- .data
src2_channel => cmd_xbar_demux_src2_channel, -- .channel
src2_startofpacket => cmd_xbar_demux_src2_startofpacket, -- .startofpacket
src2_endofpacket => cmd_xbar_demux_src2_endofpacket, -- .endofpacket
src3_ready => cmd_xbar_demux_src3_ready, -- src3.ready
src3_valid => cmd_xbar_demux_src3_valid, -- .valid
src3_data => cmd_xbar_demux_src3_data, -- .data
src3_channel => cmd_xbar_demux_src3_channel, -- .channel
src3_startofpacket => cmd_xbar_demux_src3_startofpacket, -- .startofpacket
src3_endofpacket => cmd_xbar_demux_src3_endofpacket, -- .endofpacket
src4_ready => cmd_xbar_demux_src4_ready, -- src4.ready
src4_valid => cmd_xbar_demux_src4_valid, -- .valid
src4_data => cmd_xbar_demux_src4_data, -- .data
src4_channel => cmd_xbar_demux_src4_channel, -- .channel
src4_startofpacket => cmd_xbar_demux_src4_startofpacket, -- .startofpacket
src4_endofpacket => cmd_xbar_demux_src4_endofpacket -- .endofpacket
);
cmd_xbar_demux_001 : component niosII_system_cmd_xbar_demux_001
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => addr_router_001_src_ready, -- sink.ready
sink_channel => addr_router_001_src_channel, -- .channel
sink_data => addr_router_001_src_data, -- .data
sink_startofpacket => addr_router_001_src_startofpacket, -- .startofpacket
sink_endofpacket => addr_router_001_src_endofpacket, -- .endofpacket
sink_valid(0) => addr_router_001_src_valid, -- .valid
src0_ready => cmd_xbar_demux_001_src0_ready, -- src0.ready
src0_valid => cmd_xbar_demux_001_src0_valid, -- .valid
src0_data => cmd_xbar_demux_001_src0_data, -- .data
src0_channel => cmd_xbar_demux_001_src0_channel, -- .channel
src0_startofpacket => cmd_xbar_demux_001_src0_startofpacket, -- .startofpacket
src0_endofpacket => cmd_xbar_demux_001_src0_endofpacket, -- .endofpacket
src1_ready => cmd_xbar_demux_001_src1_ready, -- src1.ready
src1_valid => cmd_xbar_demux_001_src1_valid, -- .valid
src1_data => cmd_xbar_demux_001_src1_data, -- .data
src1_channel => cmd_xbar_demux_001_src1_channel, -- .channel
src1_startofpacket => cmd_xbar_demux_001_src1_startofpacket, -- .startofpacket
src1_endofpacket => cmd_xbar_demux_001_src1_endofpacket, -- .endofpacket
src2_ready => cmd_xbar_demux_001_src2_ready, -- src2.ready
src2_valid => cmd_xbar_demux_001_src2_valid, -- .valid
src2_data => cmd_xbar_demux_001_src2_data, -- .data
src2_channel => cmd_xbar_demux_001_src2_channel, -- .channel
src2_startofpacket => cmd_xbar_demux_001_src2_startofpacket, -- .startofpacket
src2_endofpacket => cmd_xbar_demux_001_src2_endofpacket, -- .endofpacket
src3_ready => cmd_xbar_demux_001_src3_ready, -- src3.ready
src3_valid => cmd_xbar_demux_001_src3_valid, -- .valid
src3_data => cmd_xbar_demux_001_src3_data, -- .data
src3_channel => cmd_xbar_demux_001_src3_channel, -- .channel
src3_startofpacket => cmd_xbar_demux_001_src3_startofpacket, -- .startofpacket
src3_endofpacket => cmd_xbar_demux_001_src3_endofpacket, -- .endofpacket
src4_ready => cmd_xbar_demux_001_src4_ready, -- src4.ready
src4_valid => cmd_xbar_demux_001_src4_valid, -- .valid
src4_data => cmd_xbar_demux_001_src4_data, -- .data
src4_channel => cmd_xbar_demux_001_src4_channel, -- .channel
src4_startofpacket => cmd_xbar_demux_001_src4_startofpacket, -- .startofpacket
src4_endofpacket => cmd_xbar_demux_001_src4_endofpacket, -- .endofpacket
src5_ready => cmd_xbar_demux_001_src5_ready, -- src5.ready
src5_valid => cmd_xbar_demux_001_src5_valid, -- .valid
src5_data => cmd_xbar_demux_001_src5_data, -- .data
src5_channel => cmd_xbar_demux_001_src5_channel, -- .channel
src5_startofpacket => cmd_xbar_demux_001_src5_startofpacket, -- .startofpacket
src5_endofpacket => cmd_xbar_demux_001_src5_endofpacket, -- .endofpacket
src6_ready => cmd_xbar_demux_001_src6_ready, -- src6.ready
src6_valid => cmd_xbar_demux_001_src6_valid, -- .valid
src6_data => cmd_xbar_demux_001_src6_data, -- .data
src6_channel => cmd_xbar_demux_001_src6_channel, -- .channel
src6_startofpacket => cmd_xbar_demux_001_src6_startofpacket, -- .startofpacket
src6_endofpacket => cmd_xbar_demux_001_src6_endofpacket, -- .endofpacket
src7_ready => cmd_xbar_demux_001_src7_ready, -- src7.ready
src7_valid => cmd_xbar_demux_001_src7_valid, -- .valid
src7_data => cmd_xbar_demux_001_src7_data, -- .data
src7_channel => cmd_xbar_demux_001_src7_channel, -- .channel
src7_startofpacket => cmd_xbar_demux_001_src7_startofpacket, -- .startofpacket
src7_endofpacket => cmd_xbar_demux_001_src7_endofpacket, -- .endofpacket
src8_ready => cmd_xbar_demux_001_src8_ready, -- src8.ready
src8_valid => cmd_xbar_demux_001_src8_valid, -- .valid
src8_data => cmd_xbar_demux_001_src8_data, -- .data
src8_channel => cmd_xbar_demux_001_src8_channel, -- .channel
src8_startofpacket => cmd_xbar_demux_001_src8_startofpacket, -- .startofpacket
src8_endofpacket => cmd_xbar_demux_001_src8_endofpacket, -- .endofpacket
src9_ready => cmd_xbar_demux_001_src9_ready, -- src9.ready
src9_valid => cmd_xbar_demux_001_src9_valid, -- .valid
src9_data => cmd_xbar_demux_001_src9_data, -- .data
src9_channel => cmd_xbar_demux_001_src9_channel, -- .channel
src9_startofpacket => cmd_xbar_demux_001_src9_startofpacket, -- .startofpacket
src9_endofpacket => cmd_xbar_demux_001_src9_endofpacket, -- .endofpacket
src10_ready => cmd_xbar_demux_001_src10_ready, -- src10.ready
src10_valid => cmd_xbar_demux_001_src10_valid, -- .valid
src10_data => cmd_xbar_demux_001_src10_data, -- .data
src10_channel => cmd_xbar_demux_001_src10_channel, -- .channel
src10_startofpacket => cmd_xbar_demux_001_src10_startofpacket, -- .startofpacket
src10_endofpacket => cmd_xbar_demux_001_src10_endofpacket, -- .endofpacket
src11_ready => cmd_xbar_demux_001_src11_ready, -- src11.ready
src11_valid => cmd_xbar_demux_001_src11_valid, -- .valid
src11_data => cmd_xbar_demux_001_src11_data, -- .data
src11_channel => cmd_xbar_demux_001_src11_channel, -- .channel
src11_startofpacket => cmd_xbar_demux_001_src11_startofpacket, -- .startofpacket
src11_endofpacket => cmd_xbar_demux_001_src11_endofpacket, -- .endofpacket
src12_ready => cmd_xbar_demux_001_src12_ready, -- src12.ready
src12_valid => cmd_xbar_demux_001_src12_valid, -- .valid
src12_data => cmd_xbar_demux_001_src12_data, -- .data
src12_channel => cmd_xbar_demux_001_src12_channel, -- .channel
src12_startofpacket => cmd_xbar_demux_001_src12_startofpacket, -- .startofpacket
src12_endofpacket => cmd_xbar_demux_001_src12_endofpacket -- .endofpacket
);
cmd_xbar_mux : component niosII_system_cmd_xbar_mux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => cmd_xbar_mux_src_ready, -- src.ready
src_valid => cmd_xbar_mux_src_valid, -- .valid
src_data => cmd_xbar_mux_src_data, -- .data
src_channel => cmd_xbar_mux_src_channel, -- .channel
src_startofpacket => cmd_xbar_mux_src_startofpacket, -- .startofpacket
src_endofpacket => cmd_xbar_mux_src_endofpacket, -- .endofpacket
sink0_ready => cmd_xbar_demux_src0_ready, -- sink0.ready
sink0_valid => cmd_xbar_demux_src0_valid, -- .valid
sink0_channel => cmd_xbar_demux_src0_channel, -- .channel
sink0_data => cmd_xbar_demux_src0_data, -- .data
sink0_startofpacket => cmd_xbar_demux_src0_startofpacket, -- .startofpacket
sink0_endofpacket => cmd_xbar_demux_src0_endofpacket, -- .endofpacket
sink1_ready => cmd_xbar_demux_001_src0_ready, -- sink1.ready
sink1_valid => cmd_xbar_demux_001_src0_valid, -- .valid
sink1_channel => cmd_xbar_demux_001_src0_channel, -- .channel
sink1_data => cmd_xbar_demux_001_src0_data, -- .data
sink1_startofpacket => cmd_xbar_demux_001_src0_startofpacket, -- .startofpacket
sink1_endofpacket => cmd_xbar_demux_001_src0_endofpacket -- .endofpacket
);
cmd_xbar_mux_001 : component niosII_system_cmd_xbar_mux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => cmd_xbar_mux_001_src_ready, -- src.ready
src_valid => cmd_xbar_mux_001_src_valid, -- .valid
src_data => cmd_xbar_mux_001_src_data, -- .data
src_channel => cmd_xbar_mux_001_src_channel, -- .channel
src_startofpacket => cmd_xbar_mux_001_src_startofpacket, -- .startofpacket
src_endofpacket => cmd_xbar_mux_001_src_endofpacket, -- .endofpacket
sink0_ready => cmd_xbar_demux_src1_ready, -- sink0.ready
sink0_valid => cmd_xbar_demux_src1_valid, -- .valid
sink0_channel => cmd_xbar_demux_src1_channel, -- .channel
sink0_data => cmd_xbar_demux_src1_data, -- .data
sink0_startofpacket => cmd_xbar_demux_src1_startofpacket, -- .startofpacket
sink0_endofpacket => cmd_xbar_demux_src1_endofpacket, -- .endofpacket
sink1_ready => cmd_xbar_demux_001_src1_ready, -- sink1.ready
sink1_valid => cmd_xbar_demux_001_src1_valid, -- .valid
sink1_channel => cmd_xbar_demux_001_src1_channel, -- .channel
sink1_data => cmd_xbar_demux_001_src1_data, -- .data
sink1_startofpacket => cmd_xbar_demux_001_src1_startofpacket, -- .startofpacket
sink1_endofpacket => cmd_xbar_demux_001_src1_endofpacket -- .endofpacket
);
cmd_xbar_mux_002 : component niosII_system_cmd_xbar_mux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => cmd_xbar_mux_002_src_ready, -- src.ready
src_valid => cmd_xbar_mux_002_src_valid, -- .valid
src_data => cmd_xbar_mux_002_src_data, -- .data
src_channel => cmd_xbar_mux_002_src_channel, -- .channel
src_startofpacket => cmd_xbar_mux_002_src_startofpacket, -- .startofpacket
src_endofpacket => cmd_xbar_mux_002_src_endofpacket, -- .endofpacket
sink0_ready => cmd_xbar_demux_src2_ready, -- sink0.ready
sink0_valid => cmd_xbar_demux_src2_valid, -- .valid
sink0_channel => cmd_xbar_demux_src2_channel, -- .channel
sink0_data => cmd_xbar_demux_src2_data, -- .data
sink0_startofpacket => cmd_xbar_demux_src2_startofpacket, -- .startofpacket
sink0_endofpacket => cmd_xbar_demux_src2_endofpacket, -- .endofpacket
sink1_ready => cmd_xbar_demux_001_src2_ready, -- sink1.ready
sink1_valid => cmd_xbar_demux_001_src2_valid, -- .valid
sink1_channel => cmd_xbar_demux_001_src2_channel, -- .channel
sink1_data => cmd_xbar_demux_001_src2_data, -- .data
sink1_startofpacket => cmd_xbar_demux_001_src2_startofpacket, -- .startofpacket
sink1_endofpacket => cmd_xbar_demux_001_src2_endofpacket -- .endofpacket
);
cmd_xbar_mux_003 : component niosII_system_cmd_xbar_mux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => cmd_xbar_mux_003_src_ready, -- src.ready
src_valid => cmd_xbar_mux_003_src_valid, -- .valid
src_data => cmd_xbar_mux_003_src_data, -- .data
src_channel => cmd_xbar_mux_003_src_channel, -- .channel
src_startofpacket => cmd_xbar_mux_003_src_startofpacket, -- .startofpacket
src_endofpacket => cmd_xbar_mux_003_src_endofpacket, -- .endofpacket
sink0_ready => cmd_xbar_demux_src3_ready, -- sink0.ready
sink0_valid => cmd_xbar_demux_src3_valid, -- .valid
sink0_channel => cmd_xbar_demux_src3_channel, -- .channel
sink0_data => cmd_xbar_demux_src3_data, -- .data
sink0_startofpacket => cmd_xbar_demux_src3_startofpacket, -- .startofpacket
sink0_endofpacket => cmd_xbar_demux_src3_endofpacket, -- .endofpacket
sink1_ready => cmd_xbar_demux_001_src3_ready, -- sink1.ready
sink1_valid => cmd_xbar_demux_001_src3_valid, -- .valid
sink1_channel => cmd_xbar_demux_001_src3_channel, -- .channel
sink1_data => cmd_xbar_demux_001_src3_data, -- .data
sink1_startofpacket => cmd_xbar_demux_001_src3_startofpacket, -- .startofpacket
sink1_endofpacket => cmd_xbar_demux_001_src3_endofpacket -- .endofpacket
);
cmd_xbar_mux_004 : component niosII_system_cmd_xbar_mux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => cmd_xbar_mux_004_src_ready, -- src.ready
src_valid => cmd_xbar_mux_004_src_valid, -- .valid
src_data => cmd_xbar_mux_004_src_data, -- .data
src_channel => cmd_xbar_mux_004_src_channel, -- .channel
src_startofpacket => cmd_xbar_mux_004_src_startofpacket, -- .startofpacket
src_endofpacket => cmd_xbar_mux_004_src_endofpacket, -- .endofpacket
sink0_ready => cmd_xbar_demux_src4_ready, -- sink0.ready
sink0_valid => cmd_xbar_demux_src4_valid, -- .valid
sink0_channel => cmd_xbar_demux_src4_channel, -- .channel
sink0_data => cmd_xbar_demux_src4_data, -- .data
sink0_startofpacket => cmd_xbar_demux_src4_startofpacket, -- .startofpacket
sink0_endofpacket => cmd_xbar_demux_src4_endofpacket, -- .endofpacket
sink1_ready => cmd_xbar_demux_001_src4_ready, -- sink1.ready
sink1_valid => cmd_xbar_demux_001_src4_valid, -- .valid
sink1_channel => cmd_xbar_demux_001_src4_channel, -- .channel
sink1_data => cmd_xbar_demux_001_src4_data, -- .data
sink1_startofpacket => cmd_xbar_demux_001_src4_startofpacket, -- .startofpacket
sink1_endofpacket => cmd_xbar_demux_001_src4_endofpacket -- .endofpacket
);
rsp_xbar_demux : component niosII_system_rsp_xbar_demux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_src_ready, -- sink.ready
sink_channel => id_router_src_channel, -- .channel
sink_data => id_router_src_data, -- .data
sink_startofpacket => id_router_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_src_valid, -- .valid
src0_ready => rsp_xbar_demux_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_src0_valid, -- .valid
src0_data => rsp_xbar_demux_src0_data, -- .data
src0_channel => rsp_xbar_demux_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_src0_endofpacket, -- .endofpacket
src1_ready => rsp_xbar_demux_src1_ready, -- src1.ready
src1_valid => rsp_xbar_demux_src1_valid, -- .valid
src1_data => rsp_xbar_demux_src1_data, -- .data
src1_channel => rsp_xbar_demux_src1_channel, -- .channel
src1_startofpacket => rsp_xbar_demux_src1_startofpacket, -- .startofpacket
src1_endofpacket => rsp_xbar_demux_src1_endofpacket -- .endofpacket
);
rsp_xbar_demux_001 : component niosII_system_rsp_xbar_demux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_001_src_ready, -- sink.ready
sink_channel => width_adapter_001_src_channel, -- .channel
sink_data => width_adapter_001_src_data, -- .data
sink_startofpacket => width_adapter_001_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_001_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_001_src_valid, -- .valid
src0_ready => rsp_xbar_demux_001_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_001_src0_valid, -- .valid
src0_data => rsp_xbar_demux_001_src0_data, -- .data
src0_channel => rsp_xbar_demux_001_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_001_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_001_src0_endofpacket, -- .endofpacket
src1_ready => rsp_xbar_demux_001_src1_ready, -- src1.ready
src1_valid => rsp_xbar_demux_001_src1_valid, -- .valid
src1_data => rsp_xbar_demux_001_src1_data, -- .data
src1_channel => rsp_xbar_demux_001_src1_channel, -- .channel
src1_startofpacket => rsp_xbar_demux_001_src1_startofpacket, -- .startofpacket
src1_endofpacket => rsp_xbar_demux_001_src1_endofpacket -- .endofpacket
);
rsp_xbar_demux_002 : component niosII_system_rsp_xbar_demux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_002_src_ready, -- sink.ready
sink_channel => id_router_002_src_channel, -- .channel
sink_data => id_router_002_src_data, -- .data
sink_startofpacket => id_router_002_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_002_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_002_src_valid, -- .valid
src0_ready => rsp_xbar_demux_002_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_002_src0_valid, -- .valid
src0_data => rsp_xbar_demux_002_src0_data, -- .data
src0_channel => rsp_xbar_demux_002_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_002_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_002_src0_endofpacket, -- .endofpacket
src1_ready => rsp_xbar_demux_002_src1_ready, -- src1.ready
src1_valid => rsp_xbar_demux_002_src1_valid, -- .valid
src1_data => rsp_xbar_demux_002_src1_data, -- .data
src1_channel => rsp_xbar_demux_002_src1_channel, -- .channel
src1_startofpacket => rsp_xbar_demux_002_src1_startofpacket, -- .startofpacket
src1_endofpacket => rsp_xbar_demux_002_src1_endofpacket -- .endofpacket
);
rsp_xbar_demux_003 : component niosII_system_rsp_xbar_demux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_003_src_ready, -- sink.ready
sink_channel => width_adapter_003_src_channel, -- .channel
sink_data => width_adapter_003_src_data, -- .data
sink_startofpacket => width_adapter_003_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_003_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_003_src_valid, -- .valid
src0_ready => rsp_xbar_demux_003_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_003_src0_valid, -- .valid
src0_data => rsp_xbar_demux_003_src0_data, -- .data
src0_channel => rsp_xbar_demux_003_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_003_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_003_src0_endofpacket, -- .endofpacket
src1_ready => rsp_xbar_demux_003_src1_ready, -- src1.ready
src1_valid => rsp_xbar_demux_003_src1_valid, -- .valid
src1_data => rsp_xbar_demux_003_src1_data, -- .data
src1_channel => rsp_xbar_demux_003_src1_channel, -- .channel
src1_startofpacket => rsp_xbar_demux_003_src1_startofpacket, -- .startofpacket
src1_endofpacket => rsp_xbar_demux_003_src1_endofpacket -- .endofpacket
);
rsp_xbar_demux_004 : component niosII_system_rsp_xbar_demux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_005_src_ready, -- sink.ready
sink_channel => width_adapter_005_src_channel, -- .channel
sink_data => width_adapter_005_src_data, -- .data
sink_startofpacket => width_adapter_005_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_005_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_005_src_valid, -- .valid
src0_ready => rsp_xbar_demux_004_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_004_src0_valid, -- .valid
src0_data => rsp_xbar_demux_004_src0_data, -- .data
src0_channel => rsp_xbar_demux_004_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_004_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_004_src0_endofpacket, -- .endofpacket
src1_ready => rsp_xbar_demux_004_src1_ready, -- src1.ready
src1_valid => rsp_xbar_demux_004_src1_valid, -- .valid
src1_data => rsp_xbar_demux_004_src1_data, -- .data
src1_channel => rsp_xbar_demux_004_src1_channel, -- .channel
src1_startofpacket => rsp_xbar_demux_004_src1_startofpacket, -- .startofpacket
src1_endofpacket => rsp_xbar_demux_004_src1_endofpacket -- .endofpacket
);
rsp_xbar_demux_005 : component niosII_system_rsp_xbar_demux_005
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_005_src_ready, -- sink.ready
sink_channel => id_router_005_src_channel, -- .channel
sink_data => id_router_005_src_data, -- .data
sink_startofpacket => id_router_005_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_005_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_005_src_valid, -- .valid
src0_ready => rsp_xbar_demux_005_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_005_src0_valid, -- .valid
src0_data => rsp_xbar_demux_005_src0_data, -- .data
src0_channel => rsp_xbar_demux_005_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_005_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_005_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_006 : component niosII_system_rsp_xbar_demux_005
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_006_src_ready, -- sink.ready
sink_channel => id_router_006_src_channel, -- .channel
sink_data => id_router_006_src_data, -- .data
sink_startofpacket => id_router_006_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_006_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_006_src_valid, -- .valid
src0_ready => rsp_xbar_demux_006_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_006_src0_valid, -- .valid
src0_data => rsp_xbar_demux_006_src0_data, -- .data
src0_channel => rsp_xbar_demux_006_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_006_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_006_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_007 : component niosII_system_rsp_xbar_demux_005
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_007_src_ready, -- sink.ready
sink_channel => id_router_007_src_channel, -- .channel
sink_data => id_router_007_src_data, -- .data
sink_startofpacket => id_router_007_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_007_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_007_src_valid, -- .valid
src0_ready => rsp_xbar_demux_007_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_007_src0_valid, -- .valid
src0_data => rsp_xbar_demux_007_src0_data, -- .data
src0_channel => rsp_xbar_demux_007_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_007_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_007_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_008 : component niosII_system_rsp_xbar_demux_005
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_008_src_ready, -- sink.ready
sink_channel => id_router_008_src_channel, -- .channel
sink_data => id_router_008_src_data, -- .data
sink_startofpacket => id_router_008_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_008_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_008_src_valid, -- .valid
src0_ready => rsp_xbar_demux_008_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_008_src0_valid, -- .valid
src0_data => rsp_xbar_demux_008_src0_data, -- .data
src0_channel => rsp_xbar_demux_008_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_008_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_008_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_009 : component niosII_system_rsp_xbar_demux_005
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_009_src_ready, -- sink.ready
sink_channel => id_router_009_src_channel, -- .channel
sink_data => id_router_009_src_data, -- .data
sink_startofpacket => id_router_009_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_009_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_009_src_valid, -- .valid
src0_ready => rsp_xbar_demux_009_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_009_src0_valid, -- .valid
src0_data => rsp_xbar_demux_009_src0_data, -- .data
src0_channel => rsp_xbar_demux_009_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_009_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_009_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_010 : component niosII_system_rsp_xbar_demux_005
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_010_src_ready, -- sink.ready
sink_channel => id_router_010_src_channel, -- .channel
sink_data => id_router_010_src_data, -- .data
sink_startofpacket => id_router_010_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_010_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_010_src_valid, -- .valid
src0_ready => rsp_xbar_demux_010_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_010_src0_valid, -- .valid
src0_data => rsp_xbar_demux_010_src0_data, -- .data
src0_channel => rsp_xbar_demux_010_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_010_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_010_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_011 : component niosII_system_rsp_xbar_demux_005
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_011_src_ready, -- sink.ready
sink_channel => id_router_011_src_channel, -- .channel
sink_data => id_router_011_src_data, -- .data
sink_startofpacket => id_router_011_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_011_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_011_src_valid, -- .valid
src0_ready => rsp_xbar_demux_011_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_011_src0_valid, -- .valid
src0_data => rsp_xbar_demux_011_src0_data, -- .data
src0_channel => rsp_xbar_demux_011_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_011_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_011_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_012 : component niosII_system_rsp_xbar_demux_005
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_012_src_ready, -- sink.ready
sink_channel => id_router_012_src_channel, -- .channel
sink_data => id_router_012_src_data, -- .data
sink_startofpacket => id_router_012_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_012_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_012_src_valid, -- .valid
src0_ready => rsp_xbar_demux_012_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_012_src0_valid, -- .valid
src0_data => rsp_xbar_demux_012_src0_data, -- .data
src0_channel => rsp_xbar_demux_012_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_012_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_012_src0_endofpacket -- .endofpacket
);
rsp_xbar_mux : component niosII_system_rsp_xbar_mux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => rsp_xbar_mux_src_ready, -- src.ready
src_valid => rsp_xbar_mux_src_valid, -- .valid
src_data => rsp_xbar_mux_src_data, -- .data
src_channel => rsp_xbar_mux_src_channel, -- .channel
src_startofpacket => rsp_xbar_mux_src_startofpacket, -- .startofpacket
src_endofpacket => rsp_xbar_mux_src_endofpacket, -- .endofpacket
sink0_ready => rsp_xbar_demux_src0_ready, -- sink0.ready
sink0_valid => rsp_xbar_demux_src0_valid, -- .valid
sink0_channel => rsp_xbar_demux_src0_channel, -- .channel
sink0_data => rsp_xbar_demux_src0_data, -- .data
sink0_startofpacket => rsp_xbar_demux_src0_startofpacket, -- .startofpacket
sink0_endofpacket => rsp_xbar_demux_src0_endofpacket, -- .endofpacket
sink1_ready => rsp_xbar_demux_001_src0_ready, -- sink1.ready
sink1_valid => rsp_xbar_demux_001_src0_valid, -- .valid
sink1_channel => rsp_xbar_demux_001_src0_channel, -- .channel
sink1_data => rsp_xbar_demux_001_src0_data, -- .data
sink1_startofpacket => rsp_xbar_demux_001_src0_startofpacket, -- .startofpacket
sink1_endofpacket => rsp_xbar_demux_001_src0_endofpacket, -- .endofpacket
sink2_ready => rsp_xbar_demux_002_src0_ready, -- sink2.ready
sink2_valid => rsp_xbar_demux_002_src0_valid, -- .valid
sink2_channel => rsp_xbar_demux_002_src0_channel, -- .channel
sink2_data => rsp_xbar_demux_002_src0_data, -- .data
sink2_startofpacket => rsp_xbar_demux_002_src0_startofpacket, -- .startofpacket
sink2_endofpacket => rsp_xbar_demux_002_src0_endofpacket, -- .endofpacket
sink3_ready => rsp_xbar_demux_003_src0_ready, -- sink3.ready
sink3_valid => rsp_xbar_demux_003_src0_valid, -- .valid
sink3_channel => rsp_xbar_demux_003_src0_channel, -- .channel
sink3_data => rsp_xbar_demux_003_src0_data, -- .data
sink3_startofpacket => rsp_xbar_demux_003_src0_startofpacket, -- .startofpacket
sink3_endofpacket => rsp_xbar_demux_003_src0_endofpacket, -- .endofpacket
sink4_ready => rsp_xbar_demux_004_src0_ready, -- sink4.ready
sink4_valid => rsp_xbar_demux_004_src0_valid, -- .valid
sink4_channel => rsp_xbar_demux_004_src0_channel, -- .channel
sink4_data => rsp_xbar_demux_004_src0_data, -- .data
sink4_startofpacket => rsp_xbar_demux_004_src0_startofpacket, -- .startofpacket
sink4_endofpacket => rsp_xbar_demux_004_src0_endofpacket -- .endofpacket
);
rsp_xbar_mux_001 : component niosII_system_rsp_xbar_mux_001
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => rsp_xbar_mux_001_src_ready, -- src.ready
src_valid => rsp_xbar_mux_001_src_valid, -- .valid
src_data => rsp_xbar_mux_001_src_data, -- .data
src_channel => rsp_xbar_mux_001_src_channel, -- .channel
src_startofpacket => rsp_xbar_mux_001_src_startofpacket, -- .startofpacket
src_endofpacket => rsp_xbar_mux_001_src_endofpacket, -- .endofpacket
sink0_ready => rsp_xbar_demux_src1_ready, -- sink0.ready
sink0_valid => rsp_xbar_demux_src1_valid, -- .valid
sink0_channel => rsp_xbar_demux_src1_channel, -- .channel
sink0_data => rsp_xbar_demux_src1_data, -- .data
sink0_startofpacket => rsp_xbar_demux_src1_startofpacket, -- .startofpacket
sink0_endofpacket => rsp_xbar_demux_src1_endofpacket, -- .endofpacket
sink1_ready => rsp_xbar_demux_001_src1_ready, -- sink1.ready
sink1_valid => rsp_xbar_demux_001_src1_valid, -- .valid
sink1_channel => rsp_xbar_demux_001_src1_channel, -- .channel
sink1_data => rsp_xbar_demux_001_src1_data, -- .data
sink1_startofpacket => rsp_xbar_demux_001_src1_startofpacket, -- .startofpacket
sink1_endofpacket => rsp_xbar_demux_001_src1_endofpacket, -- .endofpacket
sink2_ready => rsp_xbar_demux_002_src1_ready, -- sink2.ready
sink2_valid => rsp_xbar_demux_002_src1_valid, -- .valid
sink2_channel => rsp_xbar_demux_002_src1_channel, -- .channel
sink2_data => rsp_xbar_demux_002_src1_data, -- .data
sink2_startofpacket => rsp_xbar_demux_002_src1_startofpacket, -- .startofpacket
sink2_endofpacket => rsp_xbar_demux_002_src1_endofpacket, -- .endofpacket
sink3_ready => rsp_xbar_demux_003_src1_ready, -- sink3.ready
sink3_valid => rsp_xbar_demux_003_src1_valid, -- .valid
sink3_channel => rsp_xbar_demux_003_src1_channel, -- .channel
sink3_data => rsp_xbar_demux_003_src1_data, -- .data
sink3_startofpacket => rsp_xbar_demux_003_src1_startofpacket, -- .startofpacket
sink3_endofpacket => rsp_xbar_demux_003_src1_endofpacket, -- .endofpacket
sink4_ready => rsp_xbar_demux_004_src1_ready, -- sink4.ready
sink4_valid => rsp_xbar_demux_004_src1_valid, -- .valid
sink4_channel => rsp_xbar_demux_004_src1_channel, -- .channel
sink4_data => rsp_xbar_demux_004_src1_data, -- .data
sink4_startofpacket => rsp_xbar_demux_004_src1_startofpacket, -- .startofpacket
sink4_endofpacket => rsp_xbar_demux_004_src1_endofpacket, -- .endofpacket
sink5_ready => rsp_xbar_demux_005_src0_ready, -- sink5.ready
sink5_valid => rsp_xbar_demux_005_src0_valid, -- .valid
sink5_channel => rsp_xbar_demux_005_src0_channel, -- .channel
sink5_data => rsp_xbar_demux_005_src0_data, -- .data
sink5_startofpacket => rsp_xbar_demux_005_src0_startofpacket, -- .startofpacket
sink5_endofpacket => rsp_xbar_demux_005_src0_endofpacket, -- .endofpacket
sink6_ready => rsp_xbar_demux_006_src0_ready, -- sink6.ready
sink6_valid => rsp_xbar_demux_006_src0_valid, -- .valid
sink6_channel => rsp_xbar_demux_006_src0_channel, -- .channel
sink6_data => rsp_xbar_demux_006_src0_data, -- .data
sink6_startofpacket => rsp_xbar_demux_006_src0_startofpacket, -- .startofpacket
sink6_endofpacket => rsp_xbar_demux_006_src0_endofpacket, -- .endofpacket
sink7_ready => rsp_xbar_demux_007_src0_ready, -- sink7.ready
sink7_valid => rsp_xbar_demux_007_src0_valid, -- .valid
sink7_channel => rsp_xbar_demux_007_src0_channel, -- .channel
sink7_data => rsp_xbar_demux_007_src0_data, -- .data
sink7_startofpacket => rsp_xbar_demux_007_src0_startofpacket, -- .startofpacket
sink7_endofpacket => rsp_xbar_demux_007_src0_endofpacket, -- .endofpacket
sink8_ready => rsp_xbar_demux_008_src0_ready, -- sink8.ready
sink8_valid => rsp_xbar_demux_008_src0_valid, -- .valid
sink8_channel => rsp_xbar_demux_008_src0_channel, -- .channel
sink8_data => rsp_xbar_demux_008_src0_data, -- .data
sink8_startofpacket => rsp_xbar_demux_008_src0_startofpacket, -- .startofpacket
sink8_endofpacket => rsp_xbar_demux_008_src0_endofpacket, -- .endofpacket
sink9_ready => crosser_001_out_ready, -- sink9.ready
sink9_valid => crosser_001_out_valid, -- .valid
sink9_channel => crosser_001_out_channel, -- .channel
sink9_data => crosser_001_out_data, -- .data
sink9_startofpacket => crosser_001_out_startofpacket, -- .startofpacket
sink9_endofpacket => crosser_001_out_endofpacket, -- .endofpacket
sink10_ready => rsp_xbar_demux_010_src0_ready, -- sink10.ready
sink10_valid => rsp_xbar_demux_010_src0_valid, -- .valid
sink10_channel => rsp_xbar_demux_010_src0_channel, -- .channel
sink10_data => rsp_xbar_demux_010_src0_data, -- .data
sink10_startofpacket => rsp_xbar_demux_010_src0_startofpacket, -- .startofpacket
sink10_endofpacket => rsp_xbar_demux_010_src0_endofpacket, -- .endofpacket
sink11_ready => rsp_xbar_demux_011_src0_ready, -- sink11.ready
sink11_valid => rsp_xbar_demux_011_src0_valid, -- .valid
sink11_channel => rsp_xbar_demux_011_src0_channel, -- .channel
sink11_data => rsp_xbar_demux_011_src0_data, -- .data
sink11_startofpacket => rsp_xbar_demux_011_src0_startofpacket, -- .startofpacket
sink11_endofpacket => rsp_xbar_demux_011_src0_endofpacket, -- .endofpacket
sink12_ready => rsp_xbar_demux_012_src0_ready, -- sink12.ready
sink12_valid => rsp_xbar_demux_012_src0_valid, -- .valid
sink12_channel => rsp_xbar_demux_012_src0_channel, -- .channel
sink12_data => rsp_xbar_demux_012_src0_data, -- .data
sink12_startofpacket => rsp_xbar_demux_012_src0_startofpacket, -- .startofpacket
sink12_endofpacket => rsp_xbar_demux_012_src0_endofpacket -- .endofpacket
);
width_adapter : component niosii_system_width_adapter
generic map (
IN_PKT_ADDR_H => 60,
IN_PKT_ADDR_L => 36,
IN_PKT_DATA_H => 31,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 35,
IN_PKT_BYTEEN_L => 32,
IN_PKT_BYTE_CNT_H => 69,
IN_PKT_BYTE_CNT_L => 67,
IN_PKT_TRANS_COMPRESSED_READ => 61,
IN_PKT_BURSTWRAP_H => 72,
IN_PKT_BURSTWRAP_L => 70,
IN_PKT_BURST_SIZE_H => 75,
IN_PKT_BURST_SIZE_L => 73,
IN_PKT_RESPONSE_STATUS_H => 99,
IN_PKT_RESPONSE_STATUS_L => 98,
IN_PKT_TRANS_EXCLUSIVE => 66,
IN_PKT_BURST_TYPE_H => 77,
IN_PKT_BURST_TYPE_L => 76,
IN_ST_DATA_W => 100,
OUT_PKT_ADDR_H => 42,
OUT_PKT_ADDR_L => 18,
OUT_PKT_DATA_H => 15,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 17,
OUT_PKT_BYTEEN_L => 16,
OUT_PKT_BYTE_CNT_H => 51,
OUT_PKT_BYTE_CNT_L => 49,
OUT_PKT_TRANS_COMPRESSED_READ => 43,
OUT_PKT_BURST_SIZE_H => 57,
OUT_PKT_BURST_SIZE_L => 55,
OUT_PKT_RESPONSE_STATUS_H => 81,
OUT_PKT_RESPONSE_STATUS_L => 80,
OUT_PKT_TRANS_EXCLUSIVE => 48,
OUT_PKT_BURST_TYPE_H => 59,
OUT_PKT_BURST_TYPE_L => 58,
OUT_ST_DATA_W => 82,
ST_CHANNEL_W => 13,
OPTIMIZE_FOR_RSP => 0,
RESPONSE_PATH => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_mux_001_src_valid, -- sink.valid
in_channel => cmd_xbar_mux_001_src_channel, -- .channel
in_startofpacket => cmd_xbar_mux_001_src_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_mux_001_src_endofpacket, -- .endofpacket
in_ready => cmd_xbar_mux_001_src_ready, -- .ready
in_data => cmd_xbar_mux_001_src_data, -- .data
out_endofpacket => width_adapter_src_endofpacket, -- src.endofpacket
out_data => width_adapter_src_data, -- .data
out_channel => width_adapter_src_channel, -- .channel
out_valid => width_adapter_src_valid, -- .valid
out_ready => width_adapter_src_ready, -- .ready
out_startofpacket => width_adapter_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_001 : component niosii_system_width_adapter_001
generic map (
IN_PKT_ADDR_H => 42,
IN_PKT_ADDR_L => 18,
IN_PKT_DATA_H => 15,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 17,
IN_PKT_BYTEEN_L => 16,
IN_PKT_BYTE_CNT_H => 51,
IN_PKT_BYTE_CNT_L => 49,
IN_PKT_TRANS_COMPRESSED_READ => 43,
IN_PKT_BURSTWRAP_H => 54,
IN_PKT_BURSTWRAP_L => 52,
IN_PKT_BURST_SIZE_H => 57,
IN_PKT_BURST_SIZE_L => 55,
IN_PKT_RESPONSE_STATUS_H => 81,
IN_PKT_RESPONSE_STATUS_L => 80,
IN_PKT_TRANS_EXCLUSIVE => 48,
IN_PKT_BURST_TYPE_H => 59,
IN_PKT_BURST_TYPE_L => 58,
IN_ST_DATA_W => 82,
OUT_PKT_ADDR_H => 60,
OUT_PKT_ADDR_L => 36,
OUT_PKT_DATA_H => 31,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 35,
OUT_PKT_BYTEEN_L => 32,
OUT_PKT_BYTE_CNT_H => 69,
OUT_PKT_BYTE_CNT_L => 67,
OUT_PKT_TRANS_COMPRESSED_READ => 61,
OUT_PKT_BURST_SIZE_H => 75,
OUT_PKT_BURST_SIZE_L => 73,
OUT_PKT_RESPONSE_STATUS_H => 99,
OUT_PKT_RESPONSE_STATUS_L => 98,
OUT_PKT_TRANS_EXCLUSIVE => 66,
OUT_PKT_BURST_TYPE_H => 77,
OUT_PKT_BURST_TYPE_L => 76,
OUT_ST_DATA_W => 100,
ST_CHANNEL_W => 13,
OPTIMIZE_FOR_RSP => 1,
RESPONSE_PATH => 1
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_valid => id_router_001_src_valid, -- sink.valid
in_channel => id_router_001_src_channel, -- .channel
in_startofpacket => id_router_001_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_001_src_endofpacket, -- .endofpacket
in_ready => id_router_001_src_ready, -- .ready
in_data => id_router_001_src_data, -- .data
out_endofpacket => width_adapter_001_src_endofpacket, -- src.endofpacket
out_data => width_adapter_001_src_data, -- .data
out_channel => width_adapter_001_src_channel, -- .channel
out_valid => width_adapter_001_src_valid, -- .valid
out_ready => width_adapter_001_src_ready, -- .ready
out_startofpacket => width_adapter_001_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_002 : component niosii_system_width_adapter
generic map (
IN_PKT_ADDR_H => 60,
IN_PKT_ADDR_L => 36,
IN_PKT_DATA_H => 31,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 35,
IN_PKT_BYTEEN_L => 32,
IN_PKT_BYTE_CNT_H => 69,
IN_PKT_BYTE_CNT_L => 67,
IN_PKT_TRANS_COMPRESSED_READ => 61,
IN_PKT_BURSTWRAP_H => 72,
IN_PKT_BURSTWRAP_L => 70,
IN_PKT_BURST_SIZE_H => 75,
IN_PKT_BURST_SIZE_L => 73,
IN_PKT_RESPONSE_STATUS_H => 99,
IN_PKT_RESPONSE_STATUS_L => 98,
IN_PKT_TRANS_EXCLUSIVE => 66,
IN_PKT_BURST_TYPE_H => 77,
IN_PKT_BURST_TYPE_L => 76,
IN_ST_DATA_W => 100,
OUT_PKT_ADDR_H => 42,
OUT_PKT_ADDR_L => 18,
OUT_PKT_DATA_H => 15,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 17,
OUT_PKT_BYTEEN_L => 16,
OUT_PKT_BYTE_CNT_H => 51,
OUT_PKT_BYTE_CNT_L => 49,
OUT_PKT_TRANS_COMPRESSED_READ => 43,
OUT_PKT_BURST_SIZE_H => 57,
OUT_PKT_BURST_SIZE_L => 55,
OUT_PKT_RESPONSE_STATUS_H => 81,
OUT_PKT_RESPONSE_STATUS_L => 80,
OUT_PKT_TRANS_EXCLUSIVE => 48,
OUT_PKT_BURST_TYPE_H => 59,
OUT_PKT_BURST_TYPE_L => 58,
OUT_ST_DATA_W => 82,
ST_CHANNEL_W => 13,
OPTIMIZE_FOR_RSP => 0,
RESPONSE_PATH => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_mux_003_src_valid, -- sink.valid
in_channel => cmd_xbar_mux_003_src_channel, -- .channel
in_startofpacket => cmd_xbar_mux_003_src_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_mux_003_src_endofpacket, -- .endofpacket
in_ready => cmd_xbar_mux_003_src_ready, -- .ready
in_data => cmd_xbar_mux_003_src_data, -- .data
out_endofpacket => width_adapter_002_src_endofpacket, -- src.endofpacket
out_data => width_adapter_002_src_data, -- .data
out_channel => width_adapter_002_src_channel, -- .channel
out_valid => width_adapter_002_src_valid, -- .valid
out_ready => width_adapter_002_src_ready, -- .ready
out_startofpacket => width_adapter_002_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_003 : component niosii_system_width_adapter_001
generic map (
IN_PKT_ADDR_H => 42,
IN_PKT_ADDR_L => 18,
IN_PKT_DATA_H => 15,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 17,
IN_PKT_BYTEEN_L => 16,
IN_PKT_BYTE_CNT_H => 51,
IN_PKT_BYTE_CNT_L => 49,
IN_PKT_TRANS_COMPRESSED_READ => 43,
IN_PKT_BURSTWRAP_H => 54,
IN_PKT_BURSTWRAP_L => 52,
IN_PKT_BURST_SIZE_H => 57,
IN_PKT_BURST_SIZE_L => 55,
IN_PKT_RESPONSE_STATUS_H => 81,
IN_PKT_RESPONSE_STATUS_L => 80,
IN_PKT_TRANS_EXCLUSIVE => 48,
IN_PKT_BURST_TYPE_H => 59,
IN_PKT_BURST_TYPE_L => 58,
IN_ST_DATA_W => 82,
OUT_PKT_ADDR_H => 60,
OUT_PKT_ADDR_L => 36,
OUT_PKT_DATA_H => 31,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 35,
OUT_PKT_BYTEEN_L => 32,
OUT_PKT_BYTE_CNT_H => 69,
OUT_PKT_BYTE_CNT_L => 67,
OUT_PKT_TRANS_COMPRESSED_READ => 61,
OUT_PKT_BURST_SIZE_H => 75,
OUT_PKT_BURST_SIZE_L => 73,
OUT_PKT_RESPONSE_STATUS_H => 99,
OUT_PKT_RESPONSE_STATUS_L => 98,
OUT_PKT_TRANS_EXCLUSIVE => 66,
OUT_PKT_BURST_TYPE_H => 77,
OUT_PKT_BURST_TYPE_L => 76,
OUT_ST_DATA_W => 100,
ST_CHANNEL_W => 13,
OPTIMIZE_FOR_RSP => 1,
RESPONSE_PATH => 1
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_valid => id_router_003_src_valid, -- sink.valid
in_channel => id_router_003_src_channel, -- .channel
in_startofpacket => id_router_003_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_003_src_endofpacket, -- .endofpacket
in_ready => id_router_003_src_ready, -- .ready
in_data => id_router_003_src_data, -- .data
out_endofpacket => width_adapter_003_src_endofpacket, -- src.endofpacket
out_data => width_adapter_003_src_data, -- .data
out_channel => width_adapter_003_src_channel, -- .channel
out_valid => width_adapter_003_src_valid, -- .valid
out_ready => width_adapter_003_src_ready, -- .ready
out_startofpacket => width_adapter_003_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_004 : component niosii_system_width_adapter_004
generic map (
IN_PKT_ADDR_H => 60,
IN_PKT_ADDR_L => 36,
IN_PKT_DATA_H => 31,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 35,
IN_PKT_BYTEEN_L => 32,
IN_PKT_BYTE_CNT_H => 69,
IN_PKT_BYTE_CNT_L => 67,
IN_PKT_TRANS_COMPRESSED_READ => 61,
IN_PKT_BURSTWRAP_H => 72,
IN_PKT_BURSTWRAP_L => 70,
IN_PKT_BURST_SIZE_H => 75,
IN_PKT_BURST_SIZE_L => 73,
IN_PKT_RESPONSE_STATUS_H => 99,
IN_PKT_RESPONSE_STATUS_L => 98,
IN_PKT_TRANS_EXCLUSIVE => 66,
IN_PKT_BURST_TYPE_H => 77,
IN_PKT_BURST_TYPE_L => 76,
IN_ST_DATA_W => 100,
OUT_PKT_ADDR_H => 33,
OUT_PKT_ADDR_L => 9,
OUT_PKT_DATA_H => 7,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 8,
OUT_PKT_BYTEEN_L => 8,
OUT_PKT_BYTE_CNT_H => 42,
OUT_PKT_BYTE_CNT_L => 40,
OUT_PKT_TRANS_COMPRESSED_READ => 34,
OUT_PKT_BURST_SIZE_H => 48,
OUT_PKT_BURST_SIZE_L => 46,
OUT_PKT_RESPONSE_STATUS_H => 72,
OUT_PKT_RESPONSE_STATUS_L => 71,
OUT_PKT_TRANS_EXCLUSIVE => 39,
OUT_PKT_BURST_TYPE_H => 50,
OUT_PKT_BURST_TYPE_L => 49,
OUT_ST_DATA_W => 73,
ST_CHANNEL_W => 13,
OPTIMIZE_FOR_RSP => 0,
RESPONSE_PATH => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_mux_004_src_valid, -- sink.valid
in_channel => cmd_xbar_mux_004_src_channel, -- .channel
in_startofpacket => cmd_xbar_mux_004_src_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_mux_004_src_endofpacket, -- .endofpacket
in_ready => cmd_xbar_mux_004_src_ready, -- .ready
in_data => cmd_xbar_mux_004_src_data, -- .data
out_endofpacket => width_adapter_004_src_endofpacket, -- src.endofpacket
out_data => width_adapter_004_src_data, -- .data
out_channel => width_adapter_004_src_channel, -- .channel
out_valid => width_adapter_004_src_valid, -- .valid
out_ready => width_adapter_004_src_ready, -- .ready
out_startofpacket => width_adapter_004_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_005 : component niosii_system_width_adapter_005
generic map (
IN_PKT_ADDR_H => 33,
IN_PKT_ADDR_L => 9,
IN_PKT_DATA_H => 7,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 8,
IN_PKT_BYTEEN_L => 8,
IN_PKT_BYTE_CNT_H => 42,
IN_PKT_BYTE_CNT_L => 40,
IN_PKT_TRANS_COMPRESSED_READ => 34,
IN_PKT_BURSTWRAP_H => 45,
IN_PKT_BURSTWRAP_L => 43,
IN_PKT_BURST_SIZE_H => 48,
IN_PKT_BURST_SIZE_L => 46,
IN_PKT_RESPONSE_STATUS_H => 72,
IN_PKT_RESPONSE_STATUS_L => 71,
IN_PKT_TRANS_EXCLUSIVE => 39,
IN_PKT_BURST_TYPE_H => 50,
IN_PKT_BURST_TYPE_L => 49,
IN_ST_DATA_W => 73,
OUT_PKT_ADDR_H => 60,
OUT_PKT_ADDR_L => 36,
OUT_PKT_DATA_H => 31,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 35,
OUT_PKT_BYTEEN_L => 32,
OUT_PKT_BYTE_CNT_H => 69,
OUT_PKT_BYTE_CNT_L => 67,
OUT_PKT_TRANS_COMPRESSED_READ => 61,
OUT_PKT_BURST_SIZE_H => 75,
OUT_PKT_BURST_SIZE_L => 73,
OUT_PKT_RESPONSE_STATUS_H => 99,
OUT_PKT_RESPONSE_STATUS_L => 98,
OUT_PKT_TRANS_EXCLUSIVE => 66,
OUT_PKT_BURST_TYPE_H => 77,
OUT_PKT_BURST_TYPE_L => 76,
OUT_ST_DATA_W => 100,
ST_CHANNEL_W => 13,
OPTIMIZE_FOR_RSP => 1,
RESPONSE_PATH => 1
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_valid => id_router_004_src_valid, -- sink.valid
in_channel => id_router_004_src_channel, -- .channel
in_startofpacket => id_router_004_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_004_src_endofpacket, -- .endofpacket
in_ready => id_router_004_src_ready, -- .ready
in_data => id_router_004_src_data, -- .data
out_endofpacket => width_adapter_005_src_endofpacket, -- src.endofpacket
out_data => width_adapter_005_src_data, -- .data
out_channel => width_adapter_005_src_channel, -- .channel
out_valid => width_adapter_005_src_valid, -- .valid
out_ready => width_adapter_005_src_ready, -- .ready
out_startofpacket => width_adapter_005_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
crosser : component altera_avalon_st_handshake_clock_crosser
generic map (
DATA_WIDTH => 100,
BITS_PER_SYMBOL => 100,
USE_PACKETS => 1,
USE_CHANNEL => 1,
CHANNEL_WIDTH => 13,
USE_ERROR => 0,
ERROR_WIDTH => 1,
VALID_SYNC_DEPTH => 2,
READY_SYNC_DEPTH => 2,
USE_OUTPUT_PIPELINE => 0
)
port map (
in_clk => altpll_0_c1_clk, -- in_clk.clk
in_reset => rst_controller_reset_out_reset, -- in_clk_reset.reset
out_clk => clk_clk, -- out_clk.clk
out_reset => rst_controller_001_reset_out_reset, -- out_clk_reset.reset
in_ready => cmd_xbar_demux_001_src9_ready, -- in.ready
in_valid => cmd_xbar_demux_001_src9_valid, -- .valid
in_startofpacket => cmd_xbar_demux_001_src9_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_demux_001_src9_endofpacket, -- .endofpacket
in_channel => cmd_xbar_demux_001_src9_channel, -- .channel
in_data => cmd_xbar_demux_001_src9_data, -- .data
out_ready => crosser_out_ready, -- out.ready
out_valid => crosser_out_valid, -- .valid
out_startofpacket => crosser_out_startofpacket, -- .startofpacket
out_endofpacket => crosser_out_endofpacket, -- .endofpacket
out_channel => crosser_out_channel, -- .channel
out_data => crosser_out_data, -- .data
in_empty => '0', -- (terminated)
in_error => '0', -- (terminated)
out_empty => open, -- (terminated)
out_error => open -- (terminated)
);
crosser_001 : component altera_avalon_st_handshake_clock_crosser
generic map (
DATA_WIDTH => 100,
BITS_PER_SYMBOL => 100,
USE_PACKETS => 1,
USE_CHANNEL => 1,
CHANNEL_WIDTH => 13,
USE_ERROR => 0,
ERROR_WIDTH => 1,
VALID_SYNC_DEPTH => 2,
READY_SYNC_DEPTH => 2,
USE_OUTPUT_PIPELINE => 0
)
port map (
in_clk => clk_clk, -- in_clk.clk
in_reset => rst_controller_001_reset_out_reset, -- in_clk_reset.reset
out_clk => altpll_0_c1_clk, -- out_clk.clk
out_reset => rst_controller_reset_out_reset, -- out_clk_reset.reset
in_ready => rsp_xbar_demux_009_src0_ready, -- in.ready
in_valid => rsp_xbar_demux_009_src0_valid, -- .valid
in_startofpacket => rsp_xbar_demux_009_src0_startofpacket, -- .startofpacket
in_endofpacket => rsp_xbar_demux_009_src0_endofpacket, -- .endofpacket
in_channel => rsp_xbar_demux_009_src0_channel, -- .channel
in_data => rsp_xbar_demux_009_src0_data, -- .data
out_ready => crosser_001_out_ready, -- out.ready
out_valid => crosser_001_out_valid, -- .valid
out_startofpacket => crosser_001_out_startofpacket, -- .startofpacket
out_endofpacket => crosser_001_out_endofpacket, -- .endofpacket
out_channel => crosser_001_out_channel, -- .channel
out_data => crosser_001_out_data, -- .data
in_empty => '0', -- (terminated)
in_error => '0', -- (terminated)
out_empty => open, -- (terminated)
out_error => open -- (terminated)
);
irq_mapper : component niosII_system_irq_mapper
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
receiver0_irq => irq_mapper_receiver0_irq, -- receiver0.irq
receiver1_irq => irq_mapper_receiver1_irq, -- receiver1.irq
receiver2_irq => irq_mapper_receiver2_irq, -- receiver2.irq
receiver3_irq => irq_mapper_receiver3_irq, -- receiver3.irq
sender_irq => nios2_qsys_0_d_irq_irq -- sender.irq
);
reset_reset_n_ports_inv <= not reset_reset_n;
sdram_0_s1_translator_avalon_anti_slave_0_write_ports_inv <= not sdram_0_s1_translator_avalon_anti_slave_0_write;
sdram_0_s1_translator_avalon_anti_slave_0_read_ports_inv <= not sdram_0_s1_translator_avalon_anti_slave_0_read;
sdram_0_s1_translator_avalon_anti_slave_0_byteenable_ports_inv <= not sdram_0_s1_translator_avalon_anti_slave_0_byteenable;
jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write_ports_inv <= not jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write;
jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read_ports_inv <= not jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read;
green_leds_s1_translator_avalon_anti_slave_0_write_ports_inv <= not green_leds_s1_translator_avalon_anti_slave_0_write;
timer_0_s1_translator_avalon_anti_slave_0_write_ports_inv <= not timer_0_s1_translator_avalon_anti_slave_0_write;
rst_controller_reset_out_reset_ports_inv <= not rst_controller_reset_out_reset;
end architecture rtl; -- of niosII_system
| apache-2.0 | d4534bef850d9c8a5941ee5c59f344b1 | 0.484825 | 4.055212 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/dma_example/dma_example.srcs/sources_1/bd/system/hdl/system.vhd | 1 | 210,264 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Wed May 31 20:09:35 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system.bd
--Design : system
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_1TEAG88 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arid : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awid : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
M_AXI_rid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
M_AXI_wid : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m00_couplers_imp_1TEAG88;
architecture STRUCTURE of m00_couplers_imp_1TEAG88 is
component system_auto_pc_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component system_auto_pc_1;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC;
signal auto_pc_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal auto_pc_to_m00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal auto_pc_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal auto_pc_to_m00_couplers_RLAST : STD_LOGIC;
signal auto_pc_to_m00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal auto_pc_to_m00_couplers_WID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_WLAST : STD_LOGIC;
signal auto_pc_to_m00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_pc_to_m00_couplers_WVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal m00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal m00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal m00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal m00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_m00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= auto_pc_to_m00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_pc_to_m00_couplers_ARCACHE(3 downto 0);
M_AXI_arid(1 downto 0) <= auto_pc_to_m00_couplers_ARID(1 downto 0);
M_AXI_arlen(3 downto 0) <= auto_pc_to_m00_couplers_ARLEN(3 downto 0);
M_AXI_arlock(1 downto 0) <= auto_pc_to_m00_couplers_ARLOCK(1 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_m00_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_pc_to_m00_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_pc_to_m00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_pc_to_m00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_m00_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= auto_pc_to_m00_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= auto_pc_to_m00_couplers_AWCACHE(3 downto 0);
M_AXI_awid(1 downto 0) <= auto_pc_to_m00_couplers_AWID(1 downto 0);
M_AXI_awlen(3 downto 0) <= auto_pc_to_m00_couplers_AWLEN(3 downto 0);
M_AXI_awlock(1 downto 0) <= auto_pc_to_m00_couplers_AWLOCK(1 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_m00_couplers_AWPROT(2 downto 0);
M_AXI_awqos(3 downto 0) <= auto_pc_to_m00_couplers_AWQOS(3 downto 0);
M_AXI_awsize(2 downto 0) <= auto_pc_to_m00_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= auto_pc_to_m00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_m00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_m00_couplers_RREADY;
M_AXI_wdata(63 downto 0) <= auto_pc_to_m00_couplers_WDATA(63 downto 0);
M_AXI_wid(1 downto 0) <= auto_pc_to_m00_couplers_WID(1 downto 0);
M_AXI_wlast <= auto_pc_to_m00_couplers_WLAST;
M_AXI_wstrb(7 downto 0) <= auto_pc_to_m00_couplers_WSTRB(7 downto 0);
M_AXI_wvalid <= auto_pc_to_m00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1 <= S_ARESETN;
S_AXI_arready <= m00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= m00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(1 downto 0) <= m00_couplers_to_auto_pc_BID(1 downto 0);
S_AXI_bresp(1 downto 0) <= m00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= m00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(63 downto 0) <= m00_couplers_to_auto_pc_RDATA(63 downto 0);
S_AXI_rid(1 downto 0) <= m00_couplers_to_auto_pc_RID(1 downto 0);
S_AXI_rlast <= m00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= m00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= m00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= m00_couplers_to_auto_pc_WREADY;
auto_pc_to_m00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_m00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_m00_couplers_BID(5 downto 0) <= M_AXI_bid(5 downto 0);
auto_pc_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_m00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_m00_couplers_RDATA(63 downto 0) <= M_AXI_rdata(63 downto 0);
auto_pc_to_m00_couplers_RID(5 downto 0) <= M_AXI_rid(5 downto 0);
auto_pc_to_m00_couplers_RLAST <= M_AXI_rlast;
auto_pc_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_m00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_m00_couplers_WREADY <= M_AXI_wready;
m00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
m00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
m00_couplers_to_auto_pc_ARID(1 downto 0) <= S_AXI_arid(1 downto 0);
m00_couplers_to_auto_pc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
m00_couplers_to_auto_pc_ARLOCK(0) <= S_AXI_arlock(0);
m00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
m00_couplers_to_auto_pc_ARREGION(3 downto 0) <= S_AXI_arregion(3 downto 0);
m00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
m00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
m00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
m00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
m00_couplers_to_auto_pc_AWID(1 downto 0) <= S_AXI_awid(1 downto 0);
m00_couplers_to_auto_pc_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
m00_couplers_to_auto_pc_AWLOCK(0) <= S_AXI_awlock(0);
m00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
m00_couplers_to_auto_pc_AWREGION(3 downto 0) <= S_AXI_awregion(3 downto 0);
m00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
m00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
m00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
m00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
m00_couplers_to_auto_pc_WDATA(63 downto 0) <= S_AXI_wdata(63 downto 0);
m00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
m00_couplers_to_auto_pc_WSTRB(7 downto 0) <= S_AXI_wstrb(7 downto 0);
m00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component system_auto_pc_1
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1,
m_axi_araddr(31 downto 0) => auto_pc_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => auto_pc_to_m00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_pc_to_m00_couplers_ARCACHE(3 downto 0),
m_axi_arid(1 downto 0) => auto_pc_to_m00_couplers_ARID(1 downto 0),
m_axi_arlen(3 downto 0) => auto_pc_to_m00_couplers_ARLEN(3 downto 0),
m_axi_arlock(1 downto 0) => auto_pc_to_m00_couplers_ARLOCK(1 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_pc_to_m00_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_pc_to_m00_couplers_ARREADY,
m_axi_arsize(2 downto 0) => auto_pc_to_m00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_pc_to_m00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => auto_pc_to_m00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => auto_pc_to_m00_couplers_AWCACHE(3 downto 0),
m_axi_awid(1 downto 0) => auto_pc_to_m00_couplers_AWID(1 downto 0),
m_axi_awlen(3 downto 0) => auto_pc_to_m00_couplers_AWLEN(3 downto 0),
m_axi_awlock(1 downto 0) => auto_pc_to_m00_couplers_AWLOCK(1 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => auto_pc_to_m00_couplers_AWQOS(3 downto 0),
m_axi_awready => auto_pc_to_m00_couplers_AWREADY,
m_axi_awsize(2 downto 0) => auto_pc_to_m00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid => auto_pc_to_m00_couplers_AWVALID,
m_axi_bid(1 downto 0) => auto_pc_to_m00_couplers_BID(1 downto 0),
m_axi_bready => auto_pc_to_m00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_m00_couplers_BVALID,
m_axi_rdata(63 downto 0) => auto_pc_to_m00_couplers_RDATA(63 downto 0),
m_axi_rid(1 downto 0) => auto_pc_to_m00_couplers_RID(1 downto 0),
m_axi_rlast => auto_pc_to_m00_couplers_RLAST,
m_axi_rready => auto_pc_to_m00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_m00_couplers_RVALID,
m_axi_wdata(63 downto 0) => auto_pc_to_m00_couplers_WDATA(63 downto 0),
m_axi_wid(1 downto 0) => auto_pc_to_m00_couplers_WID(1 downto 0),
m_axi_wlast => auto_pc_to_m00_couplers_WLAST,
m_axi_wready => auto_pc_to_m00_couplers_WREADY,
m_axi_wstrb(7 downto 0) => auto_pc_to_m00_couplers_WSTRB(7 downto 0),
m_axi_wvalid => auto_pc_to_m00_couplers_WVALID,
s_axi_araddr(31 downto 0) => m00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => m00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => m00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(1 downto 0) => m00_couplers_to_auto_pc_ARID(1 downto 0),
s_axi_arlen(7 downto 0) => m00_couplers_to_auto_pc_ARLEN(7 downto 0),
s_axi_arlock(0) => m00_couplers_to_auto_pc_ARLOCK(0),
s_axi_arprot(2 downto 0) => m00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => m00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => m00_couplers_to_auto_pc_ARREADY,
s_axi_arregion(3 downto 0) => m00_couplers_to_auto_pc_ARREGION(3 downto 0),
s_axi_arsize(2 downto 0) => m00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => m00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => m00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => m00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => m00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(1 downto 0) => m00_couplers_to_auto_pc_AWID(1 downto 0),
s_axi_awlen(7 downto 0) => m00_couplers_to_auto_pc_AWLEN(7 downto 0),
s_axi_awlock(0) => m00_couplers_to_auto_pc_AWLOCK(0),
s_axi_awprot(2 downto 0) => m00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => m00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => m00_couplers_to_auto_pc_AWREADY,
s_axi_awregion(3 downto 0) => m00_couplers_to_auto_pc_AWREGION(3 downto 0),
s_axi_awsize(2 downto 0) => m00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => m00_couplers_to_auto_pc_AWVALID,
s_axi_bid(1 downto 0) => m00_couplers_to_auto_pc_BID(1 downto 0),
s_axi_bready => m00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => m00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => m00_couplers_to_auto_pc_BVALID,
s_axi_rdata(63 downto 0) => m00_couplers_to_auto_pc_RDATA(63 downto 0),
s_axi_rid(1 downto 0) => m00_couplers_to_auto_pc_RID(1 downto 0),
s_axi_rlast => m00_couplers_to_auto_pc_RLAST,
s_axi_rready => m00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => m00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => m00_couplers_to_auto_pc_RVALID,
s_axi_wdata(63 downto 0) => m00_couplers_to_auto_pc_WDATA(63 downto 0),
s_axi_wlast => m00_couplers_to_auto_pc_WLAST,
s_axi_wready => m00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(7 downto 0) => m00_couplers_to_auto_pc_WSTRB(7 downto 0),
s_axi_wvalid => m00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_11SE3QO is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_11SE3QO;
architecture STRUCTURE of s00_couplers_imp_11SE3QO is
component system_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component system_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC;
signal NLW_auto_pc_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_auto_pc_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_auto_pc_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1 <= S_ARESETN;
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_pc_WREADY;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0);
s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0);
s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component system_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1,
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => NLW_auto_pc_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => NLW_auto_pc_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awready => auto_pc_to_s00_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID,
m_axi_bready => auto_pc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => NLW_auto_pc_m_axi_wstrb_UNCONNECTED(3 downto 0),
m_axi_wvalid => auto_pc_to_s00_couplers_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0),
s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0),
s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_pc_AWREADY,
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => s00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0),
s_axi_wlast => s00_couplers_to_auto_pc_WLAST,
s_axi_wready => s00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_1P403ZT is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_1P403ZT;
architecture STRUCTURE of s00_couplers_imp_1P403ZT is
component system_auto_us_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component system_auto_us_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC;
signal auto_us_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_us_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_us_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_us_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_us_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_us_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_us_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_us_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_us_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_us_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_us_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_us_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_us_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal auto_us_to_s00_couplers_RLAST : STD_LOGIC;
signal auto_us_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_us_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_us_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal auto_us_to_s00_couplers_WLAST : STD_LOGIC;
signal auto_us_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_us_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_us_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_us_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_us_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_us_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_us_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_auto_us_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_us_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_us_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_us_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_us_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_us_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_us_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_us_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_auto_us_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_us_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_us_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_us_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_us_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_us_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_us_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_us_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_us_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_us_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_us_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_us_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_us_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_us_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_us_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_us_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_us_WVALID : STD_LOGIC;
signal NLW_auto_us_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_auto_us_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_AXI_araddr(31 downto 0) <= auto_us_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= auto_us_to_s00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_us_to_s00_couplers_ARCACHE(3 downto 0);
M_AXI_arlen(7 downto 0) <= auto_us_to_s00_couplers_ARLEN(7 downto 0);
M_AXI_arlock(0) <= auto_us_to_s00_couplers_ARLOCK(0);
M_AXI_arprot(2 downto 0) <= auto_us_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_us_to_s00_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_us_to_s00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_us_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_us_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= auto_us_to_s00_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= auto_us_to_s00_couplers_AWCACHE(3 downto 0);
M_AXI_awlen(7 downto 0) <= auto_us_to_s00_couplers_AWLEN(7 downto 0);
M_AXI_awlock(0) <= auto_us_to_s00_couplers_AWLOCK(0);
M_AXI_awprot(2 downto 0) <= auto_us_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awqos(3 downto 0) <= auto_us_to_s00_couplers_AWQOS(3 downto 0);
M_AXI_awsize(2 downto 0) <= auto_us_to_s00_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= auto_us_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_us_to_s00_couplers_BREADY;
M_AXI_rready <= auto_us_to_s00_couplers_RREADY;
M_AXI_wdata(63 downto 0) <= auto_us_to_s00_couplers_WDATA(63 downto 0);
M_AXI_wlast <= auto_us_to_s00_couplers_WLAST;
M_AXI_wstrb(7 downto 0) <= auto_us_to_s00_couplers_WSTRB(7 downto 0);
M_AXI_wvalid <= auto_us_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1 <= S_ARESETN;
S_AXI_arready <= s00_couplers_to_auto_us_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_us_AWREADY;
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_us_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_us_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_us_RDATA(31 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_us_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_us_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_us_RVALID;
S_AXI_wready <= s00_couplers_to_auto_us_WREADY;
auto_us_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_us_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_us_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_us_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_us_to_s00_couplers_RDATA(63 downto 0) <= M_AXI_rdata(63 downto 0);
auto_us_to_s00_couplers_RLAST <= M_AXI_rlast;
auto_us_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_us_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_us_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_us_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_us_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_us_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_us_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s00_couplers_to_auto_us_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_us_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_us_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_us_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_us_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_us_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_us_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
s00_couplers_to_auto_us_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_us_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_us_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_us_BREADY <= S_AXI_bready;
s00_couplers_to_auto_us_RREADY <= S_AXI_rready;
s00_couplers_to_auto_us_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_us_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_us_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_us_WVALID <= S_AXI_wvalid;
auto_us: component system_auto_us_0
port map (
m_axi_araddr(31 downto 0) => auto_us_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => auto_us_to_s00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_us_to_s00_couplers_ARCACHE(3 downto 0),
m_axi_arlen(7 downto 0) => auto_us_to_s00_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => auto_us_to_s00_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => auto_us_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_us_to_s00_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_us_to_s00_couplers_ARREADY,
m_axi_arregion(3 downto 0) => NLW_auto_us_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => auto_us_to_s00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_us_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_us_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => auto_us_to_s00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => auto_us_to_s00_couplers_AWCACHE(3 downto 0),
m_axi_awlen(7 downto 0) => auto_us_to_s00_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => auto_us_to_s00_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => auto_us_to_s00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => auto_us_to_s00_couplers_AWQOS(3 downto 0),
m_axi_awready => auto_us_to_s00_couplers_AWREADY,
m_axi_awregion(3 downto 0) => NLW_auto_us_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => auto_us_to_s00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid => auto_us_to_s00_couplers_AWVALID,
m_axi_bready => auto_us_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_us_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_us_to_s00_couplers_BVALID,
m_axi_rdata(63 downto 0) => auto_us_to_s00_couplers_RDATA(63 downto 0),
m_axi_rlast => auto_us_to_s00_couplers_RLAST,
m_axi_rready => auto_us_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_us_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_us_to_s00_couplers_RVALID,
m_axi_wdata(63 downto 0) => auto_us_to_s00_couplers_WDATA(63 downto 0),
m_axi_wlast => auto_us_to_s00_couplers_WLAST,
m_axi_wready => auto_us_to_s00_couplers_WREADY,
m_axi_wstrb(7 downto 0) => auto_us_to_s00_couplers_WSTRB(7 downto 0),
m_axi_wvalid => auto_us_to_s00_couplers_WVALID,
s_axi_aclk => S_ACLK_1,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_us_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_us_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_us_ARCACHE(3 downto 0),
s_axi_aresetn => S_ARESETN_1,
s_axi_arlen(7 downto 0) => s00_couplers_to_auto_us_ARLEN(7 downto 0),
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_us_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => s00_couplers_to_auto_us_ARREADY,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_us_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_us_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_us_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_us_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_us_AWCACHE(3 downto 0),
s_axi_awlen(7 downto 0) => s00_couplers_to_auto_us_AWLEN(7 downto 0),
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_us_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => s00_couplers_to_auto_us_AWREADY,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_us_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_us_AWVALID,
s_axi_bready => s00_couplers_to_auto_us_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_us_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_us_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_us_RDATA(31 downto 0),
s_axi_rlast => s00_couplers_to_auto_us_RLAST,
s_axi_rready => s00_couplers_to_auto_us_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_us_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_us_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_us_WDATA(31 downto 0),
s_axi_wlast => s00_couplers_to_auto_us_WLAST,
s_axi_wready => s00_couplers_to_auto_us_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_us_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_us_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s01_couplers_imp_VQ497S is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC
);
end s01_couplers_imp_VQ497S;
architecture STRUCTURE of s01_couplers_imp_VQ497S is
component system_auto_us_1 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component system_auto_us_1;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC;
signal auto_us_to_s01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_us_to_s01_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s01_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s01_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_us_to_s01_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_us_to_s01_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s01_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s01_couplers_ARREADY : STD_LOGIC;
signal auto_us_to_s01_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s01_couplers_ARVALID : STD_LOGIC;
signal auto_us_to_s01_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal auto_us_to_s01_couplers_RLAST : STD_LOGIC;
signal auto_us_to_s01_couplers_RREADY : STD_LOGIC;
signal auto_us_to_s01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s01_couplers_RVALID : STD_LOGIC;
signal s01_couplers_to_auto_us_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_auto_us_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_auto_us_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_auto_us_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_auto_us_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_auto_us_ARREADY : STD_LOGIC;
signal s01_couplers_to_auto_us_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_auto_us_ARVALID : STD_LOGIC;
signal s01_couplers_to_auto_us_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_auto_us_RLAST : STD_LOGIC;
signal s01_couplers_to_auto_us_RREADY : STD_LOGIC;
signal s01_couplers_to_auto_us_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_auto_us_RVALID : STD_LOGIC;
signal NLW_auto_us_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_AXI_araddr(31 downto 0) <= auto_us_to_s01_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= auto_us_to_s01_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_us_to_s01_couplers_ARCACHE(3 downto 0);
M_AXI_arlen(7 downto 0) <= auto_us_to_s01_couplers_ARLEN(7 downto 0);
M_AXI_arlock(0) <= auto_us_to_s01_couplers_ARLOCK(0);
M_AXI_arprot(2 downto 0) <= auto_us_to_s01_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_us_to_s01_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_us_to_s01_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_us_to_s01_couplers_ARVALID;
M_AXI_rready <= auto_us_to_s01_couplers_RREADY;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1 <= S_ARESETN;
S_AXI_arready <= s01_couplers_to_auto_us_ARREADY;
S_AXI_rdata(31 downto 0) <= s01_couplers_to_auto_us_RDATA(31 downto 0);
S_AXI_rlast <= s01_couplers_to_auto_us_RLAST;
S_AXI_rresp(1 downto 0) <= s01_couplers_to_auto_us_RRESP(1 downto 0);
S_AXI_rvalid <= s01_couplers_to_auto_us_RVALID;
auto_us_to_s01_couplers_ARREADY <= M_AXI_arready;
auto_us_to_s01_couplers_RDATA(63 downto 0) <= M_AXI_rdata(63 downto 0);
auto_us_to_s01_couplers_RLAST <= M_AXI_rlast;
auto_us_to_s01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_us_to_s01_couplers_RVALID <= M_AXI_rvalid;
s01_couplers_to_auto_us_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s01_couplers_to_auto_us_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s01_couplers_to_auto_us_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s01_couplers_to_auto_us_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s01_couplers_to_auto_us_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s01_couplers_to_auto_us_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s01_couplers_to_auto_us_ARVALID <= S_AXI_arvalid;
s01_couplers_to_auto_us_RREADY <= S_AXI_rready;
auto_us: component system_auto_us_1
port map (
m_axi_araddr(31 downto 0) => auto_us_to_s01_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => auto_us_to_s01_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_us_to_s01_couplers_ARCACHE(3 downto 0),
m_axi_arlen(7 downto 0) => auto_us_to_s01_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => auto_us_to_s01_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => auto_us_to_s01_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_us_to_s01_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_us_to_s01_couplers_ARREADY,
m_axi_arregion(3 downto 0) => NLW_auto_us_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => auto_us_to_s01_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_us_to_s01_couplers_ARVALID,
m_axi_rdata(63 downto 0) => auto_us_to_s01_couplers_RDATA(63 downto 0),
m_axi_rlast => auto_us_to_s01_couplers_RLAST,
m_axi_rready => auto_us_to_s01_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_us_to_s01_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_us_to_s01_couplers_RVALID,
s_axi_aclk => S_ACLK_1,
s_axi_araddr(31 downto 0) => s01_couplers_to_auto_us_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s01_couplers_to_auto_us_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s01_couplers_to_auto_us_ARCACHE(3 downto 0),
s_axi_aresetn => S_ARESETN_1,
s_axi_arlen(7 downto 0) => s01_couplers_to_auto_us_ARLEN(7 downto 0),
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => s01_couplers_to_auto_us_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => s01_couplers_to_auto_us_ARREADY,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s01_couplers_to_auto_us_ARSIZE(2 downto 0),
s_axi_arvalid => s01_couplers_to_auto_us_ARVALID,
s_axi_rdata(31 downto 0) => s01_couplers_to_auto_us_RDATA(31 downto 0),
s_axi_rlast => s01_couplers_to_auto_us_RLAST,
s_axi_rready => s01_couplers_to_auto_us_RREADY,
s_axi_rresp(1 downto 0) => s01_couplers_to_auto_us_RRESP(1 downto 0),
s_axi_rvalid => s01_couplers_to_auto_us_RVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s02_couplers_imp_PF7596 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s02_couplers_imp_PF7596;
architecture STRUCTURE of s02_couplers_imp_PF7596 is
component system_auto_us_2 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC
);
end component system_auto_us_2;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC;
signal auto_us_to_s02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_us_to_s02_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s02_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s02_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_us_to_s02_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_us_to_s02_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s02_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s02_couplers_AWREADY : STD_LOGIC;
signal auto_us_to_s02_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s02_couplers_AWVALID : STD_LOGIC;
signal auto_us_to_s02_couplers_BREADY : STD_LOGIC;
signal auto_us_to_s02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s02_couplers_BVALID : STD_LOGIC;
signal auto_us_to_s02_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal auto_us_to_s02_couplers_WLAST : STD_LOGIC;
signal auto_us_to_s02_couplers_WREADY : STD_LOGIC;
signal auto_us_to_s02_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_us_to_s02_couplers_WVALID : STD_LOGIC;
signal s02_couplers_to_auto_us_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_auto_us_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_auto_us_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_auto_us_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s02_couplers_to_auto_us_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_auto_us_AWREADY : STD_LOGIC;
signal s02_couplers_to_auto_us_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_auto_us_AWVALID : STD_LOGIC;
signal s02_couplers_to_auto_us_BREADY : STD_LOGIC;
signal s02_couplers_to_auto_us_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_auto_us_BVALID : STD_LOGIC;
signal s02_couplers_to_auto_us_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_auto_us_WLAST : STD_LOGIC;
signal s02_couplers_to_auto_us_WREADY : STD_LOGIC;
signal s02_couplers_to_auto_us_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_auto_us_WVALID : STD_LOGIC;
signal NLW_auto_us_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_AXI_awaddr(31 downto 0) <= auto_us_to_s02_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= auto_us_to_s02_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= auto_us_to_s02_couplers_AWCACHE(3 downto 0);
M_AXI_awlen(7 downto 0) <= auto_us_to_s02_couplers_AWLEN(7 downto 0);
M_AXI_awlock(0) <= auto_us_to_s02_couplers_AWLOCK(0);
M_AXI_awprot(2 downto 0) <= auto_us_to_s02_couplers_AWPROT(2 downto 0);
M_AXI_awqos(3 downto 0) <= auto_us_to_s02_couplers_AWQOS(3 downto 0);
M_AXI_awsize(2 downto 0) <= auto_us_to_s02_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= auto_us_to_s02_couplers_AWVALID;
M_AXI_bready <= auto_us_to_s02_couplers_BREADY;
M_AXI_wdata(63 downto 0) <= auto_us_to_s02_couplers_WDATA(63 downto 0);
M_AXI_wlast <= auto_us_to_s02_couplers_WLAST;
M_AXI_wstrb(7 downto 0) <= auto_us_to_s02_couplers_WSTRB(7 downto 0);
M_AXI_wvalid <= auto_us_to_s02_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1 <= S_ARESETN;
S_AXI_awready <= s02_couplers_to_auto_us_AWREADY;
S_AXI_bresp(1 downto 0) <= s02_couplers_to_auto_us_BRESP(1 downto 0);
S_AXI_bvalid <= s02_couplers_to_auto_us_BVALID;
S_AXI_wready <= s02_couplers_to_auto_us_WREADY;
auto_us_to_s02_couplers_AWREADY <= M_AXI_awready;
auto_us_to_s02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_us_to_s02_couplers_BVALID <= M_AXI_bvalid;
auto_us_to_s02_couplers_WREADY <= M_AXI_wready;
s02_couplers_to_auto_us_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s02_couplers_to_auto_us_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s02_couplers_to_auto_us_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s02_couplers_to_auto_us_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
s02_couplers_to_auto_us_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s02_couplers_to_auto_us_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s02_couplers_to_auto_us_AWVALID <= S_AXI_awvalid;
s02_couplers_to_auto_us_BREADY <= S_AXI_bready;
s02_couplers_to_auto_us_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s02_couplers_to_auto_us_WLAST <= S_AXI_wlast;
s02_couplers_to_auto_us_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s02_couplers_to_auto_us_WVALID <= S_AXI_wvalid;
auto_us: component system_auto_us_2
port map (
m_axi_awaddr(31 downto 0) => auto_us_to_s02_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => auto_us_to_s02_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => auto_us_to_s02_couplers_AWCACHE(3 downto 0),
m_axi_awlen(7 downto 0) => auto_us_to_s02_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => auto_us_to_s02_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => auto_us_to_s02_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => auto_us_to_s02_couplers_AWQOS(3 downto 0),
m_axi_awready => auto_us_to_s02_couplers_AWREADY,
m_axi_awregion(3 downto 0) => NLW_auto_us_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => auto_us_to_s02_couplers_AWSIZE(2 downto 0),
m_axi_awvalid => auto_us_to_s02_couplers_AWVALID,
m_axi_bready => auto_us_to_s02_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_us_to_s02_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_us_to_s02_couplers_BVALID,
m_axi_wdata(63 downto 0) => auto_us_to_s02_couplers_WDATA(63 downto 0),
m_axi_wlast => auto_us_to_s02_couplers_WLAST,
m_axi_wready => auto_us_to_s02_couplers_WREADY,
m_axi_wstrb(7 downto 0) => auto_us_to_s02_couplers_WSTRB(7 downto 0),
m_axi_wvalid => auto_us_to_s02_couplers_WVALID,
s_axi_aclk => S_ACLK_1,
s_axi_aresetn => S_ARESETN_1,
s_axi_awaddr(31 downto 0) => s02_couplers_to_auto_us_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s02_couplers_to_auto_us_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s02_couplers_to_auto_us_AWCACHE(3 downto 0),
s_axi_awlen(7 downto 0) => s02_couplers_to_auto_us_AWLEN(7 downto 0),
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => s02_couplers_to_auto_us_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => s02_couplers_to_auto_us_AWREADY,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => s02_couplers_to_auto_us_AWSIZE(2 downto 0),
s_axi_awvalid => s02_couplers_to_auto_us_AWVALID,
s_axi_bready => s02_couplers_to_auto_us_BREADY,
s_axi_bresp(1 downto 0) => s02_couplers_to_auto_us_BRESP(1 downto 0),
s_axi_bvalid => s02_couplers_to_auto_us_BVALID,
s_axi_wdata(31 downto 0) => s02_couplers_to_auto_us_WDATA(31 downto 0),
s_axi_wlast => s02_couplers_to_auto_us_WLAST,
s_axi_wready => s02_couplers_to_auto_us_WREADY,
s_axi_wstrb(3 downto 0) => s02_couplers_to_auto_us_WSTRB(3 downto 0),
s_axi_wvalid => s02_couplers_to_auto_us_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_mem_intercon_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC;
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC;
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arid : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awid : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
M00_AXI_rid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M00_AXI_rlast : in STD_LOGIC;
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
M00_AXI_wid : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_wlast : out STD_LOGIC;
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC;
S01_ACLK : in STD_LOGIC;
S01_ARESETN : in STD_LOGIC;
S01_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S01_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_arready : out STD_LOGIC;
S01_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_arvalid : in STD_LOGIC;
S01_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_rlast : out STD_LOGIC;
S01_AXI_rready : in STD_LOGIC;
S01_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_rvalid : out STD_LOGIC;
S02_ACLK : in STD_LOGIC;
S02_ARESETN : in STD_LOGIC;
S02_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S02_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S02_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_awready : out STD_LOGIC;
S02_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_awvalid : in STD_LOGIC;
S02_AXI_bready : in STD_LOGIC;
S02_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_bvalid : out STD_LOGIC;
S02_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S02_AXI_wlast : in STD_LOGIC;
S02_AXI_wready : out STD_LOGIC;
S02_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_wvalid : in STD_LOGIC
);
end system_axi_mem_intercon_0;
architecture STRUCTURE of system_axi_mem_intercon_0 is
component system_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 95 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 191 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 95 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 191 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component system_xbar_0;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC;
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC;
signal S01_ACLK_1 : STD_LOGIC;
signal S01_ARESETN_1 : STD_LOGIC;
signal S02_ACLK_1 : STD_LOGIC;
signal S02_ARESETN_1 : STD_LOGIC;
signal axi_mem_intercon_ACLK_net : STD_LOGIC;
signal axi_mem_intercon_ARESETN_net : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARREADY : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARVALID : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWREADY : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWVALID : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_BREADY : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_BVALID : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RLAST : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_RREADY : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RVALID : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_WLAST : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_WREADY : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_WVALID : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARREADY : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARVALID : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s01_couplers_RLAST : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_RREADY : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s01_couplers_RVALID : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s02_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s02_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s02_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s02_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s02_couplers_AWREADY : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s02_couplers_AWVALID : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_BREADY : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s02_couplers_BVALID : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s02_couplers_WLAST : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_WREADY : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s02_couplers_WVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m00_couplers_to_axi_mem_intercon_BREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_BVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RLAST : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal m00_couplers_to_axi_mem_intercon_WID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_WLAST : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_axi_mem_intercon_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_xbar_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_xbar_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s00_couplers_to_xbar_BREADY : STD_LOGIC;
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal s00_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC;
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal s00_couplers_to_xbar_WLAST : STD_LOGIC;
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC;
signal s01_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_xbar_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s01_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 127 downto 64 );
signal s01_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_RREADY : STD_LOGIC;
signal s01_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 3 downto 2 );
signal s01_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal s02_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_xbar_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_xbar_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_xbar_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s02_couplers_to_xbar_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s02_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_xbar_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s02_couplers_to_xbar_BREADY : STD_LOGIC;
signal s02_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 5 downto 4 );
signal s02_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal s02_couplers_to_xbar_WLAST : STD_LOGIC;
signal s02_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s02_couplers_to_xbar_WVALID : STD_LOGIC;
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m00_couplers_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m00_couplers_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC;
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal xbar_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RLAST : STD_LOGIC;
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC;
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal xbar_to_m00_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC;
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_xbar_s_axi_arready_UNCONNECTED : STD_LOGIC_VECTOR ( 2 to 2 );
signal NLW_xbar_s_axi_awready_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_xbar_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_xbar_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_xbar_s_axi_bvalid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_xbar_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 191 downto 128 );
signal NLW_xbar_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_xbar_s_axi_rlast_UNCONNECTED : STD_LOGIC_VECTOR ( 2 to 2 );
signal NLW_xbar_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 4 );
signal NLW_xbar_s_axi_rvalid_UNCONNECTED : STD_LOGIC_VECTOR ( 2 to 2 );
signal NLW_xbar_s_axi_wready_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1 <= M00_ARESETN;
M00_AXI_araddr(31 downto 0) <= m00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0);
M00_AXI_arburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0);
M00_AXI_arcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0);
M00_AXI_arid(1 downto 0) <= m00_couplers_to_axi_mem_intercon_ARID(1 downto 0);
M00_AXI_arlen(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0);
M00_AXI_arlock(1 downto 0) <= m00_couplers_to_axi_mem_intercon_ARLOCK(1 downto 0);
M00_AXI_arprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0);
M00_AXI_arqos(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0);
M00_AXI_arsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0);
M00_AXI_arvalid <= m00_couplers_to_axi_mem_intercon_ARVALID;
M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0);
M00_AXI_awburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0);
M00_AXI_awcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0);
M00_AXI_awid(1 downto 0) <= m00_couplers_to_axi_mem_intercon_AWID(1 downto 0);
M00_AXI_awlen(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0);
M00_AXI_awlock(1 downto 0) <= m00_couplers_to_axi_mem_intercon_AWLOCK(1 downto 0);
M00_AXI_awprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0);
M00_AXI_awqos(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0);
M00_AXI_awsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0);
M00_AXI_awvalid <= m00_couplers_to_axi_mem_intercon_AWVALID;
M00_AXI_bready <= m00_couplers_to_axi_mem_intercon_BREADY;
M00_AXI_rready <= m00_couplers_to_axi_mem_intercon_RREADY;
M00_AXI_wdata(63 downto 0) <= m00_couplers_to_axi_mem_intercon_WDATA(63 downto 0);
M00_AXI_wid(1 downto 0) <= m00_couplers_to_axi_mem_intercon_WID(1 downto 0);
M00_AXI_wlast <= m00_couplers_to_axi_mem_intercon_WLAST;
M00_AXI_wstrb(7 downto 0) <= m00_couplers_to_axi_mem_intercon_WSTRB(7 downto 0);
M00_AXI_wvalid <= m00_couplers_to_axi_mem_intercon_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1 <= S00_ARESETN;
S00_AXI_arready <= axi_mem_intercon_to_s00_couplers_ARREADY;
S00_AXI_awready <= axi_mem_intercon_to_s00_couplers_AWREADY;
S00_AXI_bresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= axi_mem_intercon_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rlast <= axi_mem_intercon_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= axi_mem_intercon_to_s00_couplers_RVALID;
S00_AXI_wready <= axi_mem_intercon_to_s00_couplers_WREADY;
S01_ACLK_1 <= S01_ACLK;
S01_ARESETN_1 <= S01_ARESETN;
S01_AXI_arready <= axi_mem_intercon_to_s01_couplers_ARREADY;
S01_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s01_couplers_RDATA(31 downto 0);
S01_AXI_rlast <= axi_mem_intercon_to_s01_couplers_RLAST;
S01_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s01_couplers_RRESP(1 downto 0);
S01_AXI_rvalid <= axi_mem_intercon_to_s01_couplers_RVALID;
S02_ACLK_1 <= S02_ACLK;
S02_ARESETN_1 <= S02_ARESETN;
S02_AXI_awready <= axi_mem_intercon_to_s02_couplers_AWREADY;
S02_AXI_bresp(1 downto 0) <= axi_mem_intercon_to_s02_couplers_BRESP(1 downto 0);
S02_AXI_bvalid <= axi_mem_intercon_to_s02_couplers_BVALID;
S02_AXI_wready <= axi_mem_intercon_to_s02_couplers_WREADY;
axi_mem_intercon_ACLK_net <= ACLK;
axi_mem_intercon_ARESETN_net <= ARESETN;
axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
axi_mem_intercon_to_s00_couplers_ARLEN(7 downto 0) <= S00_AXI_arlen(7 downto 0);
axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
axi_mem_intercon_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
axi_mem_intercon_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
axi_mem_intercon_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
axi_mem_intercon_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
axi_mem_intercon_to_s00_couplers_AWLEN(7 downto 0) <= S00_AXI_awlen(7 downto 0);
axi_mem_intercon_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
axi_mem_intercon_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
axi_mem_intercon_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
axi_mem_intercon_to_s00_couplers_BREADY <= S00_AXI_bready;
axi_mem_intercon_to_s00_couplers_RREADY <= S00_AXI_rready;
axi_mem_intercon_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
axi_mem_intercon_to_s00_couplers_WLAST <= S00_AXI_wlast;
axi_mem_intercon_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
axi_mem_intercon_to_s00_couplers_WVALID <= S00_AXI_wvalid;
axi_mem_intercon_to_s01_couplers_ARADDR(31 downto 0) <= S01_AXI_araddr(31 downto 0);
axi_mem_intercon_to_s01_couplers_ARBURST(1 downto 0) <= S01_AXI_arburst(1 downto 0);
axi_mem_intercon_to_s01_couplers_ARCACHE(3 downto 0) <= S01_AXI_arcache(3 downto 0);
axi_mem_intercon_to_s01_couplers_ARLEN(7 downto 0) <= S01_AXI_arlen(7 downto 0);
axi_mem_intercon_to_s01_couplers_ARPROT(2 downto 0) <= S01_AXI_arprot(2 downto 0);
axi_mem_intercon_to_s01_couplers_ARSIZE(2 downto 0) <= S01_AXI_arsize(2 downto 0);
axi_mem_intercon_to_s01_couplers_ARVALID <= S01_AXI_arvalid;
axi_mem_intercon_to_s01_couplers_RREADY <= S01_AXI_rready;
axi_mem_intercon_to_s02_couplers_AWADDR(31 downto 0) <= S02_AXI_awaddr(31 downto 0);
axi_mem_intercon_to_s02_couplers_AWBURST(1 downto 0) <= S02_AXI_awburst(1 downto 0);
axi_mem_intercon_to_s02_couplers_AWCACHE(3 downto 0) <= S02_AXI_awcache(3 downto 0);
axi_mem_intercon_to_s02_couplers_AWLEN(7 downto 0) <= S02_AXI_awlen(7 downto 0);
axi_mem_intercon_to_s02_couplers_AWPROT(2 downto 0) <= S02_AXI_awprot(2 downto 0);
axi_mem_intercon_to_s02_couplers_AWSIZE(2 downto 0) <= S02_AXI_awsize(2 downto 0);
axi_mem_intercon_to_s02_couplers_AWVALID <= S02_AXI_awvalid;
axi_mem_intercon_to_s02_couplers_BREADY <= S02_AXI_bready;
axi_mem_intercon_to_s02_couplers_WDATA(31 downto 0) <= S02_AXI_wdata(31 downto 0);
axi_mem_intercon_to_s02_couplers_WLAST <= S02_AXI_wlast;
axi_mem_intercon_to_s02_couplers_WSTRB(3 downto 0) <= S02_AXI_wstrb(3 downto 0);
axi_mem_intercon_to_s02_couplers_WVALID <= S02_AXI_wvalid;
m00_couplers_to_axi_mem_intercon_ARREADY <= M00_AXI_arready;
m00_couplers_to_axi_mem_intercon_AWREADY <= M00_AXI_awready;
m00_couplers_to_axi_mem_intercon_BID(5 downto 0) <= M00_AXI_bid(5 downto 0);
m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_axi_mem_intercon_BVALID <= M00_AXI_bvalid;
m00_couplers_to_axi_mem_intercon_RDATA(63 downto 0) <= M00_AXI_rdata(63 downto 0);
m00_couplers_to_axi_mem_intercon_RID(5 downto 0) <= M00_AXI_rid(5 downto 0);
m00_couplers_to_axi_mem_intercon_RLAST <= M00_AXI_rlast;
m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_axi_mem_intercon_RVALID <= M00_AXI_rvalid;
m00_couplers_to_axi_mem_intercon_WREADY <= M00_AXI_wready;
m00_couplers: entity work.m00_couplers_imp_1TEAG88
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN => M00_ARESETN_1,
M_AXI_araddr(31 downto 0) => m00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0),
M_AXI_arid(1 downto 0) => m00_couplers_to_axi_mem_intercon_ARID(1 downto 0),
M_AXI_arlen(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0),
M_AXI_arlock(1 downto 0) => m00_couplers_to_axi_mem_intercon_ARLOCK(1 downto 0),
M_AXI_arprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0),
M_AXI_arready => m00_couplers_to_axi_mem_intercon_ARREADY,
M_AXI_arsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0),
M_AXI_arvalid => m00_couplers_to_axi_mem_intercon_ARVALID,
M_AXI_awaddr(31 downto 0) => m00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0),
M_AXI_awid(1 downto 0) => m00_couplers_to_axi_mem_intercon_AWID(1 downto 0),
M_AXI_awlen(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0),
M_AXI_awlock(1 downto 0) => m00_couplers_to_axi_mem_intercon_AWLOCK(1 downto 0),
M_AXI_awprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0),
M_AXI_awqos(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0),
M_AXI_awready => m00_couplers_to_axi_mem_intercon_AWREADY,
M_AXI_awsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0),
M_AXI_awvalid => m00_couplers_to_axi_mem_intercon_AWVALID,
M_AXI_bid(5 downto 0) => m00_couplers_to_axi_mem_intercon_BID(5 downto 0),
M_AXI_bready => m00_couplers_to_axi_mem_intercon_BREADY,
M_AXI_bresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0),
M_AXI_bvalid => m00_couplers_to_axi_mem_intercon_BVALID,
M_AXI_rdata(63 downto 0) => m00_couplers_to_axi_mem_intercon_RDATA(63 downto 0),
M_AXI_rid(5 downto 0) => m00_couplers_to_axi_mem_intercon_RID(5 downto 0),
M_AXI_rlast => m00_couplers_to_axi_mem_intercon_RLAST,
M_AXI_rready => m00_couplers_to_axi_mem_intercon_RREADY,
M_AXI_rresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0),
M_AXI_rvalid => m00_couplers_to_axi_mem_intercon_RVALID,
M_AXI_wdata(63 downto 0) => m00_couplers_to_axi_mem_intercon_WDATA(63 downto 0),
M_AXI_wid(1 downto 0) => m00_couplers_to_axi_mem_intercon_WID(1 downto 0),
M_AXI_wlast => m00_couplers_to_axi_mem_intercon_WLAST,
M_AXI_wready => m00_couplers_to_axi_mem_intercon_WREADY,
M_AXI_wstrb(7 downto 0) => m00_couplers_to_axi_mem_intercon_WSTRB(7 downto 0),
M_AXI_wvalid => m00_couplers_to_axi_mem_intercon_WVALID,
S_ACLK => axi_mem_intercon_ACLK_net,
S_ARESETN => axi_mem_intercon_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(1 downto 0) => xbar_to_m00_couplers_ARID(1 downto 0),
S_AXI_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
S_AXI_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
S_AXI_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0),
S_AXI_arready => xbar_to_m00_couplers_ARREADY,
S_AXI_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0),
S_AXI_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(1 downto 0) => xbar_to_m00_couplers_AWID(1 downto 0),
S_AXI_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
S_AXI_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
S_AXI_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0),
S_AXI_awready => xbar_to_m00_couplers_AWREADY,
S_AXI_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0),
S_AXI_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bid(1 downto 0) => xbar_to_m00_couplers_BID(1 downto 0),
S_AXI_bready => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m00_couplers_BVALID,
S_AXI_rdata(63 downto 0) => xbar_to_m00_couplers_RDATA(63 downto 0),
S_AXI_rid(1 downto 0) => xbar_to_m00_couplers_RID(1 downto 0),
S_AXI_rlast => xbar_to_m00_couplers_RLAST,
S_AXI_rready => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m00_couplers_RVALID,
S_AXI_wdata(63 downto 0) => xbar_to_m00_couplers_WDATA(63 downto 0),
S_AXI_wlast => xbar_to_m00_couplers_WLAST(0),
S_AXI_wready => xbar_to_m00_couplers_WREADY,
S_AXI_wstrb(7 downto 0) => xbar_to_m00_couplers_WSTRB(7 downto 0),
S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0)
);
s00_couplers: entity work.s00_couplers_imp_1P403ZT
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN => axi_mem_intercon_ARESETN_net,
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
M_AXI_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
M_AXI_arlock(0) => s00_couplers_to_xbar_ARLOCK(0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => s00_couplers_to_xbar_ARQOS(3 downto 0),
M_AXI_arready => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
M_AXI_arvalid => s00_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => s00_couplers_to_xbar_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => s00_couplers_to_xbar_AWCACHE(3 downto 0),
M_AXI_awlen(7 downto 0) => s00_couplers_to_xbar_AWLEN(7 downto 0),
M_AXI_awlock(0) => s00_couplers_to_xbar_AWLOCK(0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awqos(3 downto 0) => s00_couplers_to_xbar_AWQOS(3 downto 0),
M_AXI_awready => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awsize(2 downto 0) => s00_couplers_to_xbar_AWSIZE(2 downto 0),
M_AXI_awvalid => s00_couplers_to_xbar_AWVALID,
M_AXI_bready => s00_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(63 downto 0) => s00_couplers_to_xbar_RDATA(63 downto 0),
M_AXI_rlast => s00_couplers_to_xbar_RLAST(0),
M_AXI_rready => s00_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(63 downto 0) => s00_couplers_to_xbar_WDATA(63 downto 0),
M_AXI_wlast => s00_couplers_to_xbar_WLAST,
M_AXI_wready => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(7 downto 0) => s00_couplers_to_xbar_WSTRB(7 downto 0),
M_AXI_wvalid => s00_couplers_to_xbar_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN => S00_ARESETN_1,
S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arlen(7 downto 0) => axi_mem_intercon_to_s00_couplers_ARLEN(7 downto 0),
S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arready => axi_mem_intercon_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => axi_mem_intercon_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awlen(7 downto 0) => axi_mem_intercon_to_s00_couplers_AWLEN(7 downto 0),
S_AXI_awprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awready => axi_mem_intercon_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => axi_mem_intercon_to_s00_couplers_AWVALID,
S_AXI_bready => axi_mem_intercon_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => axi_mem_intercon_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rlast => axi_mem_intercon_to_s00_couplers_RLAST,
S_AXI_rready => axi_mem_intercon_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => axi_mem_intercon_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wlast => axi_mem_intercon_to_s00_couplers_WLAST,
S_AXI_wready => axi_mem_intercon_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => axi_mem_intercon_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => axi_mem_intercon_to_s00_couplers_WVALID
);
s01_couplers: entity work.s01_couplers_imp_VQ497S
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN => axi_mem_intercon_ARESETN_net,
M_AXI_araddr(31 downto 0) => s01_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s01_couplers_to_xbar_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s01_couplers_to_xbar_ARCACHE(3 downto 0),
M_AXI_arlen(7 downto 0) => s01_couplers_to_xbar_ARLEN(7 downto 0),
M_AXI_arlock(0) => s01_couplers_to_xbar_ARLOCK(0),
M_AXI_arprot(2 downto 0) => s01_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => s01_couplers_to_xbar_ARQOS(3 downto 0),
M_AXI_arready => s01_couplers_to_xbar_ARREADY(1),
M_AXI_arsize(2 downto 0) => s01_couplers_to_xbar_ARSIZE(2 downto 0),
M_AXI_arvalid => s01_couplers_to_xbar_ARVALID,
M_AXI_rdata(63 downto 0) => s01_couplers_to_xbar_RDATA(127 downto 64),
M_AXI_rlast => s01_couplers_to_xbar_RLAST(1),
M_AXI_rready => s01_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s01_couplers_to_xbar_RRESP(3 downto 2),
M_AXI_rvalid => s01_couplers_to_xbar_RVALID(1),
S_ACLK => S01_ACLK_1,
S_ARESETN => S01_ARESETN_1,
S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s01_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s01_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s01_couplers_ARCACHE(3 downto 0),
S_AXI_arlen(7 downto 0) => axi_mem_intercon_to_s01_couplers_ARLEN(7 downto 0),
S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s01_couplers_ARPROT(2 downto 0),
S_AXI_arready => axi_mem_intercon_to_s01_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s01_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => axi_mem_intercon_to_s01_couplers_ARVALID,
S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s01_couplers_RDATA(31 downto 0),
S_AXI_rlast => axi_mem_intercon_to_s01_couplers_RLAST,
S_AXI_rready => axi_mem_intercon_to_s01_couplers_RREADY,
S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s01_couplers_RRESP(1 downto 0),
S_AXI_rvalid => axi_mem_intercon_to_s01_couplers_RVALID
);
s02_couplers: entity work.s02_couplers_imp_PF7596
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN => axi_mem_intercon_ARESETN_net,
M_AXI_awaddr(31 downto 0) => s02_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => s02_couplers_to_xbar_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => s02_couplers_to_xbar_AWCACHE(3 downto 0),
M_AXI_awlen(7 downto 0) => s02_couplers_to_xbar_AWLEN(7 downto 0),
M_AXI_awlock(0) => s02_couplers_to_xbar_AWLOCK(0),
M_AXI_awprot(2 downto 0) => s02_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awqos(3 downto 0) => s02_couplers_to_xbar_AWQOS(3 downto 0),
M_AXI_awready => s02_couplers_to_xbar_AWREADY(2),
M_AXI_awsize(2 downto 0) => s02_couplers_to_xbar_AWSIZE(2 downto 0),
M_AXI_awvalid => s02_couplers_to_xbar_AWVALID,
M_AXI_bready => s02_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s02_couplers_to_xbar_BRESP(5 downto 4),
M_AXI_bvalid => s02_couplers_to_xbar_BVALID(2),
M_AXI_wdata(63 downto 0) => s02_couplers_to_xbar_WDATA(63 downto 0),
M_AXI_wlast => s02_couplers_to_xbar_WLAST,
M_AXI_wready => s02_couplers_to_xbar_WREADY(2),
M_AXI_wstrb(7 downto 0) => s02_couplers_to_xbar_WSTRB(7 downto 0),
M_AXI_wvalid => s02_couplers_to_xbar_WVALID,
S_ACLK => S02_ACLK_1,
S_ARESETN => S02_ARESETN_1,
S_AXI_awaddr(31 downto 0) => axi_mem_intercon_to_s02_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => axi_mem_intercon_to_s02_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => axi_mem_intercon_to_s02_couplers_AWCACHE(3 downto 0),
S_AXI_awlen(7 downto 0) => axi_mem_intercon_to_s02_couplers_AWLEN(7 downto 0),
S_AXI_awprot(2 downto 0) => axi_mem_intercon_to_s02_couplers_AWPROT(2 downto 0),
S_AXI_awready => axi_mem_intercon_to_s02_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => axi_mem_intercon_to_s02_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => axi_mem_intercon_to_s02_couplers_AWVALID,
S_AXI_bready => axi_mem_intercon_to_s02_couplers_BREADY,
S_AXI_bresp(1 downto 0) => axi_mem_intercon_to_s02_couplers_BRESP(1 downto 0),
S_AXI_bvalid => axi_mem_intercon_to_s02_couplers_BVALID,
S_AXI_wdata(31 downto 0) => axi_mem_intercon_to_s02_couplers_WDATA(31 downto 0),
S_AXI_wlast => axi_mem_intercon_to_s02_couplers_WLAST,
S_AXI_wready => axi_mem_intercon_to_s02_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => axi_mem_intercon_to_s02_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => axi_mem_intercon_to_s02_couplers_WVALID
);
xbar: component system_xbar_0
port map (
aclk => axi_mem_intercon_ACLK_net,
aresetn => axi_mem_intercon_ARESETN_net,
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
m_axi_arid(1 downto 0) => xbar_to_m00_couplers_ARID(1 downto 0),
m_axi_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0),
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY,
m_axi_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0),
m_axi_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
m_axi_awid(1 downto 0) => xbar_to_m00_couplers_AWID(1 downto 0),
m_axi_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0),
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY,
m_axi_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0),
m_axi_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bid(1 downto 0) => xbar_to_m00_couplers_BID(1 downto 0),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID,
m_axi_rdata(63 downto 0) => xbar_to_m00_couplers_RDATA(63 downto 0),
m_axi_rid(1 downto 0) => xbar_to_m00_couplers_RID(1 downto 0),
m_axi_rlast(0) => xbar_to_m00_couplers_RLAST,
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID,
m_axi_wdata(63 downto 0) => xbar_to_m00_couplers_WDATA(63 downto 0),
m_axi_wlast(0) => xbar_to_m00_couplers_WLAST(0),
m_axi_wready(0) => xbar_to_m00_couplers_WREADY,
m_axi_wstrb(7 downto 0) => xbar_to_m00_couplers_WSTRB(7 downto 0),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(95 downto 64) => B"00000000000000000000000000000000",
s_axi_araddr(63 downto 32) => s01_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arburst(5 downto 4) => B"00",
s_axi_arburst(3 downto 2) => s01_couplers_to_xbar_ARBURST(1 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
s_axi_arcache(11 downto 8) => B"0000",
s_axi_arcache(7 downto 4) => s01_couplers_to_xbar_ARCACHE(3 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
s_axi_arid(5 downto 0) => B"000000",
s_axi_arlen(23 downto 16) => B"00000000",
s_axi_arlen(15 downto 8) => s01_couplers_to_xbar_ARLEN(7 downto 0),
s_axi_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
s_axi_arlock(2) => '0',
s_axi_arlock(1) => s01_couplers_to_xbar_ARLOCK(0),
s_axi_arlock(0) => s00_couplers_to_xbar_ARLOCK(0),
s_axi_arprot(8 downto 6) => B"000",
s_axi_arprot(5 downto 3) => s01_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arqos(11 downto 8) => B"0000",
s_axi_arqos(7 downto 4) => s01_couplers_to_xbar_ARQOS(3 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_xbar_ARQOS(3 downto 0),
s_axi_arready(2) => NLW_xbar_s_axi_arready_UNCONNECTED(2),
s_axi_arready(1) => s01_couplers_to_xbar_ARREADY(1),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arsize(8 downto 6) => B"000",
s_axi_arsize(5 downto 3) => s01_couplers_to_xbar_ARSIZE(2 downto 0),
s_axi_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
s_axi_arvalid(2) => '0',
s_axi_arvalid(1) => s01_couplers_to_xbar_ARVALID,
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID,
s_axi_awaddr(95 downto 64) => s02_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awaddr(63 downto 32) => B"00000000000000000000000000000000",
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awburst(5 downto 4) => s02_couplers_to_xbar_AWBURST(1 downto 0),
s_axi_awburst(3 downto 2) => B"00",
s_axi_awburst(1 downto 0) => s00_couplers_to_xbar_AWBURST(1 downto 0),
s_axi_awcache(11 downto 8) => s02_couplers_to_xbar_AWCACHE(3 downto 0),
s_axi_awcache(7 downto 4) => B"0000",
s_axi_awcache(3 downto 0) => s00_couplers_to_xbar_AWCACHE(3 downto 0),
s_axi_awid(5 downto 0) => B"000000",
s_axi_awlen(23 downto 16) => s02_couplers_to_xbar_AWLEN(7 downto 0),
s_axi_awlen(15 downto 8) => B"00000000",
s_axi_awlen(7 downto 0) => s00_couplers_to_xbar_AWLEN(7 downto 0),
s_axi_awlock(2) => s02_couplers_to_xbar_AWLOCK(0),
s_axi_awlock(1) => '0',
s_axi_awlock(0) => s00_couplers_to_xbar_AWLOCK(0),
s_axi_awprot(8 downto 6) => s02_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awprot(5 downto 3) => B"000",
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awqos(11 downto 8) => s02_couplers_to_xbar_AWQOS(3 downto 0),
s_axi_awqos(7 downto 4) => B"0000",
s_axi_awqos(3 downto 0) => s00_couplers_to_xbar_AWQOS(3 downto 0),
s_axi_awready(2) => s02_couplers_to_xbar_AWREADY(2),
s_axi_awready(1) => NLW_xbar_s_axi_awready_UNCONNECTED(1),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awsize(8 downto 6) => s02_couplers_to_xbar_AWSIZE(2 downto 0),
s_axi_awsize(5 downto 3) => B"000",
s_axi_awsize(2 downto 0) => s00_couplers_to_xbar_AWSIZE(2 downto 0),
s_axi_awvalid(2) => s02_couplers_to_xbar_AWVALID,
s_axi_awvalid(1) => '0',
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID,
s_axi_bid(5 downto 0) => NLW_xbar_s_axi_bid_UNCONNECTED(5 downto 0),
s_axi_bready(2) => s02_couplers_to_xbar_BREADY,
s_axi_bready(1) => '0',
s_axi_bready(0) => s00_couplers_to_xbar_BREADY,
s_axi_bresp(5 downto 4) => s02_couplers_to_xbar_BRESP(5 downto 4),
s_axi_bresp(3 downto 2) => NLW_xbar_s_axi_bresp_UNCONNECTED(3 downto 2),
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(2) => s02_couplers_to_xbar_BVALID(2),
s_axi_bvalid(1) => NLW_xbar_s_axi_bvalid_UNCONNECTED(1),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(191 downto 128) => NLW_xbar_s_axi_rdata_UNCONNECTED(191 downto 128),
s_axi_rdata(127 downto 64) => s01_couplers_to_xbar_RDATA(127 downto 64),
s_axi_rdata(63 downto 0) => s00_couplers_to_xbar_RDATA(63 downto 0),
s_axi_rid(5 downto 0) => NLW_xbar_s_axi_rid_UNCONNECTED(5 downto 0),
s_axi_rlast(2) => NLW_xbar_s_axi_rlast_UNCONNECTED(2),
s_axi_rlast(1) => s01_couplers_to_xbar_RLAST(1),
s_axi_rlast(0) => s00_couplers_to_xbar_RLAST(0),
s_axi_rready(2) => '0',
s_axi_rready(1) => s01_couplers_to_xbar_RREADY,
s_axi_rready(0) => s00_couplers_to_xbar_RREADY,
s_axi_rresp(5 downto 4) => NLW_xbar_s_axi_rresp_UNCONNECTED(5 downto 4),
s_axi_rresp(3 downto 2) => s01_couplers_to_xbar_RRESP(3 downto 2),
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(2) => NLW_xbar_s_axi_rvalid_UNCONNECTED(2),
s_axi_rvalid(1) => s01_couplers_to_xbar_RVALID(1),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(191 downto 128) => s02_couplers_to_xbar_WDATA(63 downto 0),
s_axi_wdata(127 downto 64) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wdata(63 downto 0) => s00_couplers_to_xbar_WDATA(63 downto 0),
s_axi_wlast(2) => s02_couplers_to_xbar_WLAST,
s_axi_wlast(1) => '1',
s_axi_wlast(0) => s00_couplers_to_xbar_WLAST,
s_axi_wready(2) => s02_couplers_to_xbar_WREADY(2),
s_axi_wready(1) => NLW_xbar_s_axi_wready_UNCONNECTED(1),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(23 downto 16) => s02_couplers_to_xbar_WSTRB(7 downto 0),
s_axi_wstrb(15 downto 8) => B"11111111",
s_axi_wstrb(7 downto 0) => s00_couplers_to_xbar_WSTRB(7 downto 0),
s_axi_wvalid(2) => s02_couplers_to_xbar_WVALID,
s_axi_wvalid(1) => '0',
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ps7_0_axi_periph_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC;
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC;
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end system_ps7_0_axi_periph_0;
architecture STRUCTURE of system_ps7_0_axi_periph_0 is
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC;
signal ps7_0_axi_periph_ACLK_net : STD_LOGIC;
signal ps7_0_axi_periph_ARESETN_net : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_RLAST : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_WLAST : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_ps7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_ps7_0_axi_periph_ARREADY : STD_LOGIC;
signal s00_couplers_to_ps7_0_axi_periph_ARVALID : STD_LOGIC;
signal s00_couplers_to_ps7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_ps7_0_axi_periph_AWREADY : STD_LOGIC;
signal s00_couplers_to_ps7_0_axi_periph_AWVALID : STD_LOGIC;
signal s00_couplers_to_ps7_0_axi_periph_BREADY : STD_LOGIC;
signal s00_couplers_to_ps7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_ps7_0_axi_periph_BVALID : STD_LOGIC;
signal s00_couplers_to_ps7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_ps7_0_axi_periph_RREADY : STD_LOGIC;
signal s00_couplers_to_ps7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_ps7_0_axi_periph_RVALID : STD_LOGIC;
signal s00_couplers_to_ps7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_ps7_0_axi_periph_WREADY : STD_LOGIC;
signal s00_couplers_to_ps7_0_axi_periph_WVALID : STD_LOGIC;
begin
M00_AXI_araddr(31 downto 0) <= s00_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0);
M00_AXI_arvalid <= s00_couplers_to_ps7_0_axi_periph_ARVALID;
M00_AXI_awaddr(31 downto 0) <= s00_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0);
M00_AXI_awvalid <= s00_couplers_to_ps7_0_axi_periph_AWVALID;
M00_AXI_bready <= s00_couplers_to_ps7_0_axi_periph_BREADY;
M00_AXI_rready <= s00_couplers_to_ps7_0_axi_periph_RREADY;
M00_AXI_wdata(31 downto 0) <= s00_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0);
M00_AXI_wvalid <= s00_couplers_to_ps7_0_axi_periph_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1 <= S00_ARESETN;
S00_AXI_arready <= ps7_0_axi_periph_to_s00_couplers_ARREADY;
S00_AXI_awready <= ps7_0_axi_periph_to_s00_couplers_AWREADY;
S00_AXI_bid(11 downto 0) <= ps7_0_axi_periph_to_s00_couplers_BID(11 downto 0);
S00_AXI_bresp(1 downto 0) <= ps7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= ps7_0_axi_periph_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= ps7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(11 downto 0) <= ps7_0_axi_periph_to_s00_couplers_RID(11 downto 0);
S00_AXI_rlast <= ps7_0_axi_periph_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= ps7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= ps7_0_axi_periph_to_s00_couplers_RVALID;
S00_AXI_wready <= ps7_0_axi_periph_to_s00_couplers_WREADY;
ps7_0_axi_periph_ACLK_net <= M00_ACLK;
ps7_0_axi_periph_ARESETN_net <= M00_ARESETN;
ps7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
ps7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
ps7_0_axi_periph_to_s00_couplers_BREADY <= S00_AXI_bready;
ps7_0_axi_periph_to_s00_couplers_RREADY <= S00_AXI_rready;
ps7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
ps7_0_axi_periph_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0);
ps7_0_axi_periph_to_s00_couplers_WLAST <= S00_AXI_wlast;
ps7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_WVALID <= S00_AXI_wvalid;
s00_couplers_to_ps7_0_axi_periph_ARREADY <= M00_AXI_arready;
s00_couplers_to_ps7_0_axi_periph_AWREADY <= M00_AXI_awready;
s00_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
s00_couplers_to_ps7_0_axi_periph_BVALID <= M00_AXI_bvalid;
s00_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
s00_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
s00_couplers_to_ps7_0_axi_periph_RVALID <= M00_AXI_rvalid;
s00_couplers_to_ps7_0_axi_periph_WREADY <= M00_AXI_wready;
s00_couplers: entity work.s00_couplers_imp_11SE3QO
port map (
M_ACLK => ps7_0_axi_periph_ACLK_net,
M_ARESETN => ps7_0_axi_periph_ARESETN_net,
M_AXI_araddr(31 downto 0) => s00_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => s00_couplers_to_ps7_0_axi_periph_ARREADY,
M_AXI_arvalid => s00_couplers_to_ps7_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => s00_couplers_to_ps7_0_axi_periph_AWREADY,
M_AXI_awvalid => s00_couplers_to_ps7_0_axi_periph_AWVALID,
M_AXI_bready => s00_couplers_to_ps7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_ps7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => s00_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => s00_couplers_to_ps7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_ps7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => s00_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => s00_couplers_to_ps7_0_axi_periph_WREADY,
M_AXI_wvalid => s00_couplers_to_ps7_0_axi_periph_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN => S00_ARESETN_1,
S_AXI_araddr(31 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARID(11 downto 0),
S_AXI_arlen(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0),
S_AXI_arlock(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0),
S_AXI_arprot(2 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => ps7_0_axi_periph_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => ps7_0_axi_periph_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWID(11 downto 0),
S_AXI_awlen(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0),
S_AXI_awlock(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0),
S_AXI_awprot(2 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => ps7_0_axi_periph_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => ps7_0_axi_periph_to_s00_couplers_AWVALID,
S_AXI_bid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_BID(11 downto 0),
S_AXI_bready => ps7_0_axi_periph_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => ps7_0_axi_periph_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => ps7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_RID(11 downto 0),
S_AXI_rlast => ps7_0_axi_periph_to_s00_couplers_RLAST,
S_AXI_rready => ps7_0_axi_periph_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => ps7_0_axi_periph_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => ps7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_WID(11 downto 0),
S_AXI_wlast => ps7_0_axi_periph_to_s00_couplers_WLAST,
S_AXI_wready => ps7_0_axi_periph_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => ps7_0_axi_periph_to_s00_couplers_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of system : entity is "system,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=18,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=7,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=4,da_ps7_cnt=1,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system : entity is "system.hwdef";
end system;
architecture STRUCTURE of system is
component system_processing_system7_0_0 is
port (
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component system_processing_system7_0_0;
component system_axi_dma_0_0 is
port (
s_axi_lite_aclk : in STD_LOGIC;
m_axi_sg_aclk : in STD_LOGIC;
m_axi_mm2s_aclk : in STD_LOGIC;
m_axi_s2mm_aclk : in STD_LOGIC;
axi_resetn : in STD_LOGIC;
s_axi_lite_awvalid : in STD_LOGIC;
s_axi_lite_awready : out STD_LOGIC;
s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_wvalid : in STD_LOGIC;
s_axi_lite_wready : out STD_LOGIC;
s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_lite_bvalid : out STD_LOGIC;
s_axi_lite_bready : in STD_LOGIC;
s_axi_lite_arvalid : in STD_LOGIC;
s_axi_lite_arready : out STD_LOGIC;
s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_rvalid : out STD_LOGIC;
s_axi_lite_rready : in STD_LOGIC;
s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_sg_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_sg_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_sg_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_sg_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_sg_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_sg_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_sg_awvalid : out STD_LOGIC;
m_axi_sg_awready : in STD_LOGIC;
m_axi_sg_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_sg_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_sg_wlast : out STD_LOGIC;
m_axi_sg_wvalid : out STD_LOGIC;
m_axi_sg_wready : in STD_LOGIC;
m_axi_sg_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_sg_bvalid : in STD_LOGIC;
m_axi_sg_bready : out STD_LOGIC;
m_axi_sg_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_sg_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_sg_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_sg_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_sg_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_sg_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_sg_arvalid : out STD_LOGIC;
m_axi_sg_arready : in STD_LOGIC;
m_axi_sg_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_sg_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_sg_rlast : in STD_LOGIC;
m_axi_sg_rvalid : in STD_LOGIC;
m_axi_sg_rready : out STD_LOGIC;
m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_mm2s_arvalid : out STD_LOGIC;
m_axi_mm2s_arready : in STD_LOGIC;
m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_rlast : in STD_LOGIC;
m_axi_mm2s_rvalid : in STD_LOGIC;
m_axi_mm2s_rready : out STD_LOGIC;
mm2s_prmry_reset_out_n : out STD_LOGIC;
m_axis_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_mm2s_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_mm2s_tvalid : out STD_LOGIC;
m_axis_mm2s_tready : in STD_LOGIC;
m_axis_mm2s_tlast : out STD_LOGIC;
m_axi_s2mm_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_s2mm_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_awvalid : out STD_LOGIC;
m_axi_s2mm_awready : in STD_LOGIC;
m_axi_s2mm_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_wlast : out STD_LOGIC;
m_axi_s2mm_wvalid : out STD_LOGIC;
m_axi_s2mm_wready : in STD_LOGIC;
m_axi_s2mm_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_bvalid : in STD_LOGIC;
m_axi_s2mm_bready : out STD_LOGIC;
s2mm_prmry_reset_out_n : out STD_LOGIC;
s_axis_s2mm_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_s2mm_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_s2mm_tvalid : in STD_LOGIC;
s_axis_s2mm_tready : out STD_LOGIC;
s_axis_s2mm_tlast : in STD_LOGIC;
mm2s_introut : out STD_LOGIC;
s2mm_introut : out STD_LOGIC
);
end component system_axi_dma_0_0;
component system_rst_ps7_0_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component system_rst_ps7_0_100M_0;
component system_axis_data_fifo_0_0 is
port (
s_axis_aresetn : in STD_LOGIC;
s_axis_aclk : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tlast : in STD_LOGIC;
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tlast : out STD_LOGIC;
axis_data_count : out STD_LOGIC_VECTOR ( 31 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 31 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component system_axis_data_fifo_0_0;
component system_xlconcat_0_0 is
port (
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component system_xlconcat_0_0;
signal axi_dma_0_M_AXIS_MM2S_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXIS_MM2S_TKEEP : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_0_M_AXIS_MM2S_TLAST : STD_LOGIC;
signal axi_dma_0_M_AXIS_MM2S_TREADY : STD_LOGIC;
signal axi_dma_0_M_AXIS_MM2S_TVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_MM2S_RLAST : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_RREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_MM2S_RVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_S2MM_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_S2MM_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_0_M_AXI_S2MM_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_0_M_AXI_S2MM_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_S2MM_AWREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_S2MM_AWVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_BREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_S2MM_BVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_S2MM_WLAST : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_WREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_0_M_AXI_S2MM_WVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_SG_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_SG_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_SG_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_0_M_AXI_SG_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_0_M_AXI_SG_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_SG_ARREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_SG_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_SG_ARVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_SG_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_SG_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_SG_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_0_M_AXI_SG_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_0_M_AXI_SG_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_SG_AWREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_SG_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_SG_AWVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_SG_BREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_SG_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_SG_BVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_SG_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_SG_RLAST : STD_LOGIC;
signal axi_dma_0_M_AXI_SG_RREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_SG_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_SG_RVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_SG_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_SG_WLAST : STD_LOGIC;
signal axi_dma_0_M_AXI_SG_WREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_SG_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_0_M_AXI_SG_WVALID : STD_LOGIC;
signal axi_dma_0_mm2s_introut : STD_LOGIC;
signal axi_dma_0_s2mm_introut : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal axi_mem_intercon_M00_AXI_BREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_BVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal axi_mem_intercon_M00_AXI_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal axi_mem_intercon_M00_AXI_RLAST : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_RVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal axi_mem_intercon_M00_AXI_WID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_WLAST : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_M00_AXI_WVALID : STD_LOGIC;
signal axis_data_fifo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_data_fifo_0_M_AXIS_TKEEP : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axis_data_fifo_0_M_AXIS_TLAST : STD_LOGIC;
signal axis_data_fifo_0_M_AXIS_TREADY : STD_LOGIC;
signal axis_data_fifo_0_M_AXIS_TVALID : STD_LOGIC;
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC;
signal rst_ps7_0_100M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_ps7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal xlconcat_0_dout : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_axi_dma_0_mm2s_prmry_reset_out_n_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_0_s2mm_prmry_reset_out_n_UNCONNECTED : STD_LOGIC;
signal NLW_axis_data_fifo_0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axis_data_fifo_0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axis_data_fifo_0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_rst_ps7_0_100M_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_rst_ps7_0_100M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_ps7_0_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
begin
axi_dma_0: component system_axi_dma_0_0
port map (
axi_resetn => rst_ps7_0_100M_peripheral_aresetn(0),
m_axi_mm2s_aclk => processing_system7_0_FCLK_CLK0,
m_axi_mm2s_araddr(31 downto 0) => axi_dma_0_M_AXI_MM2S_ARADDR(31 downto 0),
m_axi_mm2s_arburst(1 downto 0) => axi_dma_0_M_AXI_MM2S_ARBURST(1 downto 0),
m_axi_mm2s_arcache(3 downto 0) => axi_dma_0_M_AXI_MM2S_ARCACHE(3 downto 0),
m_axi_mm2s_arlen(7 downto 0) => axi_dma_0_M_AXI_MM2S_ARLEN(7 downto 0),
m_axi_mm2s_arprot(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARPROT(2 downto 0),
m_axi_mm2s_arready => axi_dma_0_M_AXI_MM2S_ARREADY,
m_axi_mm2s_arsize(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARSIZE(2 downto 0),
m_axi_mm2s_arvalid => axi_dma_0_M_AXI_MM2S_ARVALID,
m_axi_mm2s_rdata(31 downto 0) => axi_dma_0_M_AXI_MM2S_RDATA(31 downto 0),
m_axi_mm2s_rlast => axi_dma_0_M_AXI_MM2S_RLAST,
m_axi_mm2s_rready => axi_dma_0_M_AXI_MM2S_RREADY,
m_axi_mm2s_rresp(1 downto 0) => axi_dma_0_M_AXI_MM2S_RRESP(1 downto 0),
m_axi_mm2s_rvalid => axi_dma_0_M_AXI_MM2S_RVALID,
m_axi_s2mm_aclk => processing_system7_0_FCLK_CLK0,
m_axi_s2mm_awaddr(31 downto 0) => axi_dma_0_M_AXI_S2MM_AWADDR(31 downto 0),
m_axi_s2mm_awburst(1 downto 0) => axi_dma_0_M_AXI_S2MM_AWBURST(1 downto 0),
m_axi_s2mm_awcache(3 downto 0) => axi_dma_0_M_AXI_S2MM_AWCACHE(3 downto 0),
m_axi_s2mm_awlen(7 downto 0) => axi_dma_0_M_AXI_S2MM_AWLEN(7 downto 0),
m_axi_s2mm_awprot(2 downto 0) => axi_dma_0_M_AXI_S2MM_AWPROT(2 downto 0),
m_axi_s2mm_awready => axi_dma_0_M_AXI_S2MM_AWREADY,
m_axi_s2mm_awsize(2 downto 0) => axi_dma_0_M_AXI_S2MM_AWSIZE(2 downto 0),
m_axi_s2mm_awvalid => axi_dma_0_M_AXI_S2MM_AWVALID,
m_axi_s2mm_bready => axi_dma_0_M_AXI_S2MM_BREADY,
m_axi_s2mm_bresp(1 downto 0) => axi_dma_0_M_AXI_S2MM_BRESP(1 downto 0),
m_axi_s2mm_bvalid => axi_dma_0_M_AXI_S2MM_BVALID,
m_axi_s2mm_wdata(31 downto 0) => axi_dma_0_M_AXI_S2MM_WDATA(31 downto 0),
m_axi_s2mm_wlast => axi_dma_0_M_AXI_S2MM_WLAST,
m_axi_s2mm_wready => axi_dma_0_M_AXI_S2MM_WREADY,
m_axi_s2mm_wstrb(3 downto 0) => axi_dma_0_M_AXI_S2MM_WSTRB(3 downto 0),
m_axi_s2mm_wvalid => axi_dma_0_M_AXI_S2MM_WVALID,
m_axi_sg_aclk => processing_system7_0_FCLK_CLK0,
m_axi_sg_araddr(31 downto 0) => axi_dma_0_M_AXI_SG_ARADDR(31 downto 0),
m_axi_sg_arburst(1 downto 0) => axi_dma_0_M_AXI_SG_ARBURST(1 downto 0),
m_axi_sg_arcache(3 downto 0) => axi_dma_0_M_AXI_SG_ARCACHE(3 downto 0),
m_axi_sg_arlen(7 downto 0) => axi_dma_0_M_AXI_SG_ARLEN(7 downto 0),
m_axi_sg_arprot(2 downto 0) => axi_dma_0_M_AXI_SG_ARPROT(2 downto 0),
m_axi_sg_arready => axi_dma_0_M_AXI_SG_ARREADY,
m_axi_sg_arsize(2 downto 0) => axi_dma_0_M_AXI_SG_ARSIZE(2 downto 0),
m_axi_sg_arvalid => axi_dma_0_M_AXI_SG_ARVALID,
m_axi_sg_awaddr(31 downto 0) => axi_dma_0_M_AXI_SG_AWADDR(31 downto 0),
m_axi_sg_awburst(1 downto 0) => axi_dma_0_M_AXI_SG_AWBURST(1 downto 0),
m_axi_sg_awcache(3 downto 0) => axi_dma_0_M_AXI_SG_AWCACHE(3 downto 0),
m_axi_sg_awlen(7 downto 0) => axi_dma_0_M_AXI_SG_AWLEN(7 downto 0),
m_axi_sg_awprot(2 downto 0) => axi_dma_0_M_AXI_SG_AWPROT(2 downto 0),
m_axi_sg_awready => axi_dma_0_M_AXI_SG_AWREADY,
m_axi_sg_awsize(2 downto 0) => axi_dma_0_M_AXI_SG_AWSIZE(2 downto 0),
m_axi_sg_awvalid => axi_dma_0_M_AXI_SG_AWVALID,
m_axi_sg_bready => axi_dma_0_M_AXI_SG_BREADY,
m_axi_sg_bresp(1 downto 0) => axi_dma_0_M_AXI_SG_BRESP(1 downto 0),
m_axi_sg_bvalid => axi_dma_0_M_AXI_SG_BVALID,
m_axi_sg_rdata(31 downto 0) => axi_dma_0_M_AXI_SG_RDATA(31 downto 0),
m_axi_sg_rlast => axi_dma_0_M_AXI_SG_RLAST,
m_axi_sg_rready => axi_dma_0_M_AXI_SG_RREADY,
m_axi_sg_rresp(1 downto 0) => axi_dma_0_M_AXI_SG_RRESP(1 downto 0),
m_axi_sg_rvalid => axi_dma_0_M_AXI_SG_RVALID,
m_axi_sg_wdata(31 downto 0) => axi_dma_0_M_AXI_SG_WDATA(31 downto 0),
m_axi_sg_wlast => axi_dma_0_M_AXI_SG_WLAST,
m_axi_sg_wready => axi_dma_0_M_AXI_SG_WREADY,
m_axi_sg_wstrb(3 downto 0) => axi_dma_0_M_AXI_SG_WSTRB(3 downto 0),
m_axi_sg_wvalid => axi_dma_0_M_AXI_SG_WVALID,
m_axis_mm2s_tdata(31 downto 0) => axi_dma_0_M_AXIS_MM2S_TDATA(31 downto 0),
m_axis_mm2s_tkeep(3 downto 0) => axi_dma_0_M_AXIS_MM2S_TKEEP(3 downto 0),
m_axis_mm2s_tlast => axi_dma_0_M_AXIS_MM2S_TLAST,
m_axis_mm2s_tready => axi_dma_0_M_AXIS_MM2S_TREADY,
m_axis_mm2s_tvalid => axi_dma_0_M_AXIS_MM2S_TVALID,
mm2s_introut => axi_dma_0_mm2s_introut,
mm2s_prmry_reset_out_n => NLW_axi_dma_0_mm2s_prmry_reset_out_n_UNCONNECTED,
s2mm_introut => axi_dma_0_s2mm_introut,
s2mm_prmry_reset_out_n => NLW_axi_dma_0_s2mm_prmry_reset_out_n_UNCONNECTED,
s_axi_lite_aclk => processing_system7_0_FCLK_CLK0,
s_axi_lite_araddr(9 downto 0) => ps7_0_axi_periph_M00_AXI_ARADDR(9 downto 0),
s_axi_lite_arready => ps7_0_axi_periph_M00_AXI_ARREADY,
s_axi_lite_arvalid => ps7_0_axi_periph_M00_AXI_ARVALID,
s_axi_lite_awaddr(9 downto 0) => ps7_0_axi_periph_M00_AXI_AWADDR(9 downto 0),
s_axi_lite_awready => ps7_0_axi_periph_M00_AXI_AWREADY,
s_axi_lite_awvalid => ps7_0_axi_periph_M00_AXI_AWVALID,
s_axi_lite_bready => ps7_0_axi_periph_M00_AXI_BREADY,
s_axi_lite_bresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
s_axi_lite_bvalid => ps7_0_axi_periph_M00_AXI_BVALID,
s_axi_lite_rdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
s_axi_lite_rready => ps7_0_axi_periph_M00_AXI_RREADY,
s_axi_lite_rresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
s_axi_lite_rvalid => ps7_0_axi_periph_M00_AXI_RVALID,
s_axi_lite_wdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
s_axi_lite_wready => ps7_0_axi_periph_M00_AXI_WREADY,
s_axi_lite_wvalid => ps7_0_axi_periph_M00_AXI_WVALID,
s_axis_s2mm_tdata(31 downto 0) => axis_data_fifo_0_M_AXIS_TDATA(31 downto 0),
s_axis_s2mm_tkeep(3 downto 0) => axis_data_fifo_0_M_AXIS_TKEEP(3 downto 0),
s_axis_s2mm_tlast => axis_data_fifo_0_M_AXIS_TLAST,
s_axis_s2mm_tready => axis_data_fifo_0_M_AXIS_TREADY,
s_axis_s2mm_tvalid => axis_data_fifo_0_M_AXIS_TVALID
);
axi_mem_intercon: entity work.system_axi_mem_intercon_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN => rst_ps7_0_100M_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arburst(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
M00_AXI_arcache(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
M00_AXI_arid(1 downto 0) => axi_mem_intercon_M00_AXI_ARID(1 downto 0),
M00_AXI_arlen(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0),
M00_AXI_arlock(1 downto 0) => axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0),
M00_AXI_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arqos(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0),
M00_AXI_arready => axi_mem_intercon_M00_AXI_ARREADY,
M00_AXI_arsize(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
M00_AXI_arvalid => axi_mem_intercon_M00_AXI_ARVALID,
M00_AXI_awaddr(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awburst(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
M00_AXI_awcache(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
M00_AXI_awid(1 downto 0) => axi_mem_intercon_M00_AXI_AWID(1 downto 0),
M00_AXI_awlen(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0),
M00_AXI_awlock(1 downto 0) => axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0),
M00_AXI_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awqos(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0),
M00_AXI_awready => axi_mem_intercon_M00_AXI_AWREADY,
M00_AXI_awsize(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
M00_AXI_awvalid => axi_mem_intercon_M00_AXI_AWVALID,
M00_AXI_bid(5 downto 0) => axi_mem_intercon_M00_AXI_BID(5 downto 0),
M00_AXI_bready => axi_mem_intercon_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => axi_mem_intercon_M00_AXI_BVALID,
M00_AXI_rdata(63 downto 0) => axi_mem_intercon_M00_AXI_RDATA(63 downto 0),
M00_AXI_rid(5 downto 0) => axi_mem_intercon_M00_AXI_RID(5 downto 0),
M00_AXI_rlast => axi_mem_intercon_M00_AXI_RLAST,
M00_AXI_rready => axi_mem_intercon_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => axi_mem_intercon_M00_AXI_RVALID,
M00_AXI_wdata(63 downto 0) => axi_mem_intercon_M00_AXI_WDATA(63 downto 0),
M00_AXI_wid(1 downto 0) => axi_mem_intercon_M00_AXI_WID(1 downto 0),
M00_AXI_wlast => axi_mem_intercon_M00_AXI_WLAST,
M00_AXI_wready => axi_mem_intercon_M00_AXI_WREADY,
M00_AXI_wstrb(7 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(7 downto 0),
M00_AXI_wvalid => axi_mem_intercon_M00_AXI_WVALID,
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => axi_dma_0_M_AXI_SG_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => axi_dma_0_M_AXI_SG_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => axi_dma_0_M_AXI_SG_ARCACHE(3 downto 0),
S00_AXI_arlen(7 downto 0) => axi_dma_0_M_AXI_SG_ARLEN(7 downto 0),
S00_AXI_arprot(2 downto 0) => axi_dma_0_M_AXI_SG_ARPROT(2 downto 0),
S00_AXI_arready => axi_dma_0_M_AXI_SG_ARREADY,
S00_AXI_arsize(2 downto 0) => axi_dma_0_M_AXI_SG_ARSIZE(2 downto 0),
S00_AXI_arvalid => axi_dma_0_M_AXI_SG_ARVALID,
S00_AXI_awaddr(31 downto 0) => axi_dma_0_M_AXI_SG_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => axi_dma_0_M_AXI_SG_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => axi_dma_0_M_AXI_SG_AWCACHE(3 downto 0),
S00_AXI_awlen(7 downto 0) => axi_dma_0_M_AXI_SG_AWLEN(7 downto 0),
S00_AXI_awprot(2 downto 0) => axi_dma_0_M_AXI_SG_AWPROT(2 downto 0),
S00_AXI_awready => axi_dma_0_M_AXI_SG_AWREADY,
S00_AXI_awsize(2 downto 0) => axi_dma_0_M_AXI_SG_AWSIZE(2 downto 0),
S00_AXI_awvalid => axi_dma_0_M_AXI_SG_AWVALID,
S00_AXI_bready => axi_dma_0_M_AXI_SG_BREADY,
S00_AXI_bresp(1 downto 0) => axi_dma_0_M_AXI_SG_BRESP(1 downto 0),
S00_AXI_bvalid => axi_dma_0_M_AXI_SG_BVALID,
S00_AXI_rdata(31 downto 0) => axi_dma_0_M_AXI_SG_RDATA(31 downto 0),
S00_AXI_rlast => axi_dma_0_M_AXI_SG_RLAST,
S00_AXI_rready => axi_dma_0_M_AXI_SG_RREADY,
S00_AXI_rresp(1 downto 0) => axi_dma_0_M_AXI_SG_RRESP(1 downto 0),
S00_AXI_rvalid => axi_dma_0_M_AXI_SG_RVALID,
S00_AXI_wdata(31 downto 0) => axi_dma_0_M_AXI_SG_WDATA(31 downto 0),
S00_AXI_wlast => axi_dma_0_M_AXI_SG_WLAST,
S00_AXI_wready => axi_dma_0_M_AXI_SG_WREADY,
S00_AXI_wstrb(3 downto 0) => axi_dma_0_M_AXI_SG_WSTRB(3 downto 0),
S00_AXI_wvalid => axi_dma_0_M_AXI_SG_WVALID,
S01_ACLK => processing_system7_0_FCLK_CLK0,
S01_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
S01_AXI_araddr(31 downto 0) => axi_dma_0_M_AXI_MM2S_ARADDR(31 downto 0),
S01_AXI_arburst(1 downto 0) => axi_dma_0_M_AXI_MM2S_ARBURST(1 downto 0),
S01_AXI_arcache(3 downto 0) => axi_dma_0_M_AXI_MM2S_ARCACHE(3 downto 0),
S01_AXI_arlen(7 downto 0) => axi_dma_0_M_AXI_MM2S_ARLEN(7 downto 0),
S01_AXI_arprot(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARPROT(2 downto 0),
S01_AXI_arready => axi_dma_0_M_AXI_MM2S_ARREADY,
S01_AXI_arsize(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARSIZE(2 downto 0),
S01_AXI_arvalid => axi_dma_0_M_AXI_MM2S_ARVALID,
S01_AXI_rdata(31 downto 0) => axi_dma_0_M_AXI_MM2S_RDATA(31 downto 0),
S01_AXI_rlast => axi_dma_0_M_AXI_MM2S_RLAST,
S01_AXI_rready => axi_dma_0_M_AXI_MM2S_RREADY,
S01_AXI_rresp(1 downto 0) => axi_dma_0_M_AXI_MM2S_RRESP(1 downto 0),
S01_AXI_rvalid => axi_dma_0_M_AXI_MM2S_RVALID,
S02_ACLK => processing_system7_0_FCLK_CLK0,
S02_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
S02_AXI_awaddr(31 downto 0) => axi_dma_0_M_AXI_S2MM_AWADDR(31 downto 0),
S02_AXI_awburst(1 downto 0) => axi_dma_0_M_AXI_S2MM_AWBURST(1 downto 0),
S02_AXI_awcache(3 downto 0) => axi_dma_0_M_AXI_S2MM_AWCACHE(3 downto 0),
S02_AXI_awlen(7 downto 0) => axi_dma_0_M_AXI_S2MM_AWLEN(7 downto 0),
S02_AXI_awprot(2 downto 0) => axi_dma_0_M_AXI_S2MM_AWPROT(2 downto 0),
S02_AXI_awready => axi_dma_0_M_AXI_S2MM_AWREADY,
S02_AXI_awsize(2 downto 0) => axi_dma_0_M_AXI_S2MM_AWSIZE(2 downto 0),
S02_AXI_awvalid => axi_dma_0_M_AXI_S2MM_AWVALID,
S02_AXI_bready => axi_dma_0_M_AXI_S2MM_BREADY,
S02_AXI_bresp(1 downto 0) => axi_dma_0_M_AXI_S2MM_BRESP(1 downto 0),
S02_AXI_bvalid => axi_dma_0_M_AXI_S2MM_BVALID,
S02_AXI_wdata(31 downto 0) => axi_dma_0_M_AXI_S2MM_WDATA(31 downto 0),
S02_AXI_wlast => axi_dma_0_M_AXI_S2MM_WLAST,
S02_AXI_wready => axi_dma_0_M_AXI_S2MM_WREADY,
S02_AXI_wstrb(3 downto 0) => axi_dma_0_M_AXI_S2MM_WSTRB(3 downto 0),
S02_AXI_wvalid => axi_dma_0_M_AXI_S2MM_WVALID
);
axis_data_fifo_0: component system_axis_data_fifo_0_0
port map (
axis_data_count(31 downto 0) => NLW_axis_data_fifo_0_axis_data_count_UNCONNECTED(31 downto 0),
axis_rd_data_count(31 downto 0) => NLW_axis_data_fifo_0_axis_rd_data_count_UNCONNECTED(31 downto 0),
axis_wr_data_count(31 downto 0) => NLW_axis_data_fifo_0_axis_wr_data_count_UNCONNECTED(31 downto 0),
m_axis_tdata(31 downto 0) => axis_data_fifo_0_M_AXIS_TDATA(31 downto 0),
m_axis_tkeep(3 downto 0) => axis_data_fifo_0_M_AXIS_TKEEP(3 downto 0),
m_axis_tlast => axis_data_fifo_0_M_AXIS_TLAST,
m_axis_tready => axis_data_fifo_0_M_AXIS_TREADY,
m_axis_tvalid => axis_data_fifo_0_M_AXIS_TVALID,
s_axis_aclk => processing_system7_0_FCLK_CLK0,
s_axis_aresetn => rst_ps7_0_100M_peripheral_aresetn(0),
s_axis_tdata(31 downto 0) => axi_dma_0_M_AXIS_MM2S_TDATA(31 downto 0),
s_axis_tkeep(3 downto 0) => axi_dma_0_M_AXIS_MM2S_TKEEP(3 downto 0),
s_axis_tlast => axi_dma_0_M_AXIS_MM2S_TLAST,
s_axis_tready => axi_dma_0_M_AXIS_MM2S_TREADY,
s_axis_tvalid => axi_dma_0_M_AXIS_MM2S_TVALID
);
processing_system7_0: component system_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
IRQ_F2P(1 downto 0) => xlconcat_0_dout(1 downto 0),
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => processing_system7_0_M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => processing_system7_0_M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => processing_system7_0_M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => processing_system7_0_M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => processing_system7_0_M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => processing_system7_0_M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => processing_system7_0_M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => processing_system7_0_M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => processing_system7_0_M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => processing_system7_0_M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => processing_system7_0_M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => processing_system7_0_M_AXI_GP0_WVALID,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
S_AXI_HP0_ACLK => processing_system7_0_FCLK_CLK0,
S_AXI_HP0_ARADDR(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0),
S_AXI_HP0_ARBURST(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
S_AXI_HP0_ARCACHE(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
S_AXI_HP0_ARID(5 downto 2) => B"0000",
S_AXI_HP0_ARID(1 downto 0) => axi_mem_intercon_M00_AXI_ARID(1 downto 0),
S_AXI_HP0_ARLEN(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0),
S_AXI_HP0_ARLOCK(1 downto 0) => axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0),
S_AXI_HP0_ARPROT(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
S_AXI_HP0_ARQOS(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0),
S_AXI_HP0_ARREADY => axi_mem_intercon_M00_AXI_ARREADY,
S_AXI_HP0_ARSIZE(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
S_AXI_HP0_ARVALID => axi_mem_intercon_M00_AXI_ARVALID,
S_AXI_HP0_AWADDR(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0),
S_AXI_HP0_AWBURST(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
S_AXI_HP0_AWCACHE(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
S_AXI_HP0_AWID(5 downto 2) => B"0000",
S_AXI_HP0_AWID(1 downto 0) => axi_mem_intercon_M00_AXI_AWID(1 downto 0),
S_AXI_HP0_AWLEN(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0),
S_AXI_HP0_AWLOCK(1 downto 0) => axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0),
S_AXI_HP0_AWPROT(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
S_AXI_HP0_AWQOS(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0),
S_AXI_HP0_AWREADY => axi_mem_intercon_M00_AXI_AWREADY,
S_AXI_HP0_AWSIZE(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
S_AXI_HP0_AWVALID => axi_mem_intercon_M00_AXI_AWVALID,
S_AXI_HP0_BID(5 downto 0) => axi_mem_intercon_M00_AXI_BID(5 downto 0),
S_AXI_HP0_BREADY => axi_mem_intercon_M00_AXI_BREADY,
S_AXI_HP0_BRESP(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
S_AXI_HP0_BVALID => axi_mem_intercon_M00_AXI_BVALID,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => axi_mem_intercon_M00_AXI_RDATA(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => axi_mem_intercon_M00_AXI_RID(5 downto 0),
S_AXI_HP0_RLAST => axi_mem_intercon_M00_AXI_RLAST,
S_AXI_HP0_RREADY => axi_mem_intercon_M00_AXI_RREADY,
S_AXI_HP0_RRESP(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
S_AXI_HP0_RVALID => axi_mem_intercon_M00_AXI_RVALID,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => axi_mem_intercon_M00_AXI_WDATA(63 downto 0),
S_AXI_HP0_WID(5 downto 2) => B"0000",
S_AXI_HP0_WID(1 downto 0) => axi_mem_intercon_M00_AXI_WID(1 downto 0),
S_AXI_HP0_WLAST => axi_mem_intercon_M00_AXI_WLAST,
S_AXI_HP0_WREADY => axi_mem_intercon_M00_AXI_WREADY,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(7 downto 0),
S_AXI_HP0_WVALID => axi_mem_intercon_M00_AXI_WVALID,
TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => '0',
USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
);
ps7_0_axi_periph: entity work.system_ps7_0_axi_periph_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN => rst_ps7_0_100M_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => ps7_0_axi_periph_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arready => ps7_0_axi_periph_M00_AXI_ARREADY,
M00_AXI_arvalid => ps7_0_axi_periph_M00_AXI_ARVALID,
M00_AXI_awaddr(31 downto 0) => ps7_0_axi_periph_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awready => ps7_0_axi_periph_M00_AXI_AWREADY,
M00_AXI_awvalid => ps7_0_axi_periph_M00_AXI_AWVALID,
M00_AXI_bready => ps7_0_axi_periph_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => ps7_0_axi_periph_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready => ps7_0_axi_periph_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => ps7_0_axi_periph_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready => ps7_0_axi_periph_M00_AXI_WREADY,
M00_AXI_wvalid => ps7_0_axi_periph_M00_AXI_WVALID,
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY,
S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID,
S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY,
S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID,
S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY,
S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID,
S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST,
S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY,
S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID,
S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST,
S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY,
S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID
);
rst_ps7_0_100M: component system_rst_ps7_0_100M_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_rst_ps7_0_100M_bus_struct_reset_UNCONNECTED(0),
dcm_locked => '1',
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => rst_ps7_0_100M_interconnect_aresetn(0),
mb_debug_sys_rst => '0',
mb_reset => NLW_rst_ps7_0_100M_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => rst_ps7_0_100M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_ps7_0_100M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => processing_system7_0_FCLK_CLK0
);
xlconcat_0: component system_xlconcat_0_0
port map (
In0(0) => axi_dma_0_mm2s_introut,
In1(0) => axi_dma_0_s2mm_introut,
dout(1 downto 0) => xlconcat_0_dout(1 downto 0)
);
end STRUCTURE;
| mit | 8b6300bae222391da34d7f8a6be9c158 | 0.667318 | 2.758574 | false | false | false | false |
loa-org/loa-hdl | modules/onewire/hdl/onewire_cfg_pkg.vhd | 1 | 2,104 | -------------------------------------------------------------------------------
-- Title : Onewire Master Configuration Package
-------------------------------------------------------------------------------
-- Author : [email protected]
-------------------------------------------------------------------------------
-- Created : 2014-12-13
-------------------------------------------------------------------------------
-- Copyright (c) 2014, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.onewire_pkg.all;
package onewire_cfg_pkg is
-- Onewire bus timing, taken from DS18B20 datasheet
-- literal values are for 50MHz system clock
constant bus_reset_cycles : integer := 24000;
constant bus_reset_wait_for_response : integer := 4500;
constant bus_write_zero : integer := 4000;
constant bus_write_zero_gap : integer := 1000;
constant bus_write_one : integer := 100;
constant bus_write_one_gap : integer := 4900;
constant bus_read_pulse : integer := 100;
constant bus_read_delay : integer := 550;
constant bus_read_gap : integer := 4350;
-- fine xst doesn't support physical constants
--constant clk_period : time := 20 ns;
--constant bus_reset_cycles : integer := 480 us / clk_period;
--constant bus_reset_wait_for_response : integer := 90 us / clk_period;
--constant bus_write_zero : integer := 80 us / clk_period;
--constant bus_write_zero_gap : integer := 20 us / clk_period;
--constant bus_write_one : integer := 2 us / clk_period;
--constant bus_write_one_gap : integer := 98 us / clk_period;
--constant bus_read_pulse : integer := 2 us / clk_period;
--constant bus_read_delay : integer := 11 us / clk_period;
--constant bus_read_gap : integer := 87 us / clk_period;
end onewire_cfg_pkg;
| bsd-3-clause | 19680fdb3dd729787e598a4070e0bcb9 | 0.555133 | 4.2334 | false | false | false | false |
loa-org/loa-hdl | modules/encoder/hdl/quadrature_decoder.vhd | 2 | 3,569 | -------------------------------------------------------------------------------
-- Title : Quadrature Decoder
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Company : Roboterclub Aachen e.V.
-------------------------------------------------------------------------------
-- Description:
--
-- ___ ___ ___ ___
-- A ___| |___| |_______| |___|
-- ___ ___ ___ ___
-- B _____| |___| |___| |___| |_
--
-- step_p 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
-- dir_p 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.encoder_module_pkg.all;
package quadrature_decoder_pkg is
component quadrature_decoder
port (
encoder_p : in encoder_type;
step_p : out std_logic;
dir_p : out std_logic;
error_p : out std_logic;
clk : in std_logic);
end component;
end quadrature_decoder_pkg;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.encoder_module_pkg.all;
entity quadrature_decoder is
port (
encoder_p : in encoder_type;
step_p : out std_logic; -- detected step_p ('1' for one clock cycle)
dir_p : out std_logic; -- count direction (1 = up, 0 = down)
error_p : out std_logic; -- illegal transition (two bits change at the same time)
clk : in std_logic -- system clock
);
end quadrature_decoder;
architecture behavioral of quadrature_decoder is
signal a_buf : std_logic_vector(1 downto 0) := "00";
signal b_buf : std_logic_vector(1 downto 0) := "00";
begin
-- edge detection
process
begin
wait until rising_edge(clk);
a_buf <= a_buf(0) & encoder_p.a;
b_buf <= b_buf(0) & encoder_p.b;
end process;
-- signal decoding
comb : process(a_buf, b_buf)
variable state : std_logic_vector(3 downto 0);
begin
state := a_buf(0) & b_buf(0) & a_buf(1) & b_buf(1);
case state is
-- step_p = a_buf(0) xor a_buf(1) xor b_buf(0) xor b_buf(1)
-- dir_p = not (a_buf(0) xor b_buf(1))
-- new -> old
when "0000" => step_p <= '0'; dir_p <= '0'; error_p <= '0';
when "0001" => step_p <= '1'; dir_p <= '1'; error_p <= '0';
when "0010" => step_p <= '1'; dir_p <= '0'; error_p <= '0';
when "0011" => step_p <= '0'; dir_p <= '1'; error_p <= '1';
when "0100" => step_p <= '1'; dir_p <= '0'; error_p <= '0';
when "0101" => step_p <= '0'; dir_p <= '1'; error_p <= '0';
when "0110" => step_p <= '0'; dir_p <= '0'; error_p <= '1';
when "0111" => step_p <= '1'; dir_p <= '1'; error_p <= '0';
when "1000" => step_p <= '1'; dir_p <= '1'; error_p <= '0';
when "1001" => step_p <= '0'; dir_p <= '0'; error_p <= '1';
when "1010" => step_p <= '0'; dir_p <= '1'; error_p <= '0';
when "1011" => step_p <= '1'; dir_p <= '0'; error_p <= '0';
when "1100" => step_p <= '0'; dir_p <= '1'; error_p <= '1';
when "1101" => step_p <= '1'; dir_p <= '0'; error_p <= '0';
when "1110" => step_p <= '1'; dir_p <= '1'; error_p <= '0';
when "1111" => step_p <= '0'; dir_p <= '0'; error_p <= '0';
when others => step_p <= '0'; dir_p <= '1'; error_p <= '1';
end case;
end process;
end behavioral;
| bsd-3-clause | 7be2994f677a5d97762a1414637e46bb | 0.434015 | 3.206649 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_vga_color_test_0_0/system_vga_color_test_0_0_sim_netlist.vhdl | 1 | 24,990 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 08:27:08 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_vga_color_test_0_0/system_vga_color_test_0_0_sim_netlist.vhdl
-- Design : system_vga_color_test_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_color_test_0_0_vga_color_test is
port (
rgb : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
xaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
clk_25 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_color_test_0_0_vga_color_test : entity is "vga_color_test";
end system_vga_color_test_0_0_vga_color_test;
architecture STRUCTURE of system_vga_color_test_0_0_vga_color_test is
signal \rgb[13]_i_1_n_0\ : STD_LOGIC;
signal \rgb[14]_i_1_n_0\ : STD_LOGIC;
signal \rgb[14]_i_2_n_0\ : STD_LOGIC;
signal \rgb[14]_i_3_n_0\ : STD_LOGIC;
signal \rgb[14]_i_4_n_0\ : STD_LOGIC;
signal \rgb[14]_i_5_n_0\ : STD_LOGIC;
signal \rgb[14]_i_6_n_0\ : STD_LOGIC;
signal \rgb[15]_i_1_n_0\ : STD_LOGIC;
signal \rgb[15]_i_2_n_0\ : STD_LOGIC;
signal \rgb[15]_i_3_n_0\ : STD_LOGIC;
signal \rgb[15]_i_4_n_0\ : STD_LOGIC;
signal \rgb[15]_i_5_n_0\ : STD_LOGIC;
signal \rgb[15]_i_6_n_0\ : STD_LOGIC;
signal \rgb[15]_i_7_n_0\ : STD_LOGIC;
signal \rgb[21]_i_1_n_0\ : STD_LOGIC;
signal \rgb[22]_i_10_n_0\ : STD_LOGIC;
signal \rgb[22]_i_11_n_0\ : STD_LOGIC;
signal \rgb[22]_i_1_n_0\ : STD_LOGIC;
signal \rgb[22]_i_2_n_0\ : STD_LOGIC;
signal \rgb[22]_i_3_n_0\ : STD_LOGIC;
signal \rgb[22]_i_4_n_0\ : STD_LOGIC;
signal \rgb[22]_i_5_n_0\ : STD_LOGIC;
signal \rgb[22]_i_6_n_0\ : STD_LOGIC;
signal \rgb[22]_i_7_n_0\ : STD_LOGIC;
signal \rgb[22]_i_8_n_0\ : STD_LOGIC;
signal \rgb[22]_i_9_n_0\ : STD_LOGIC;
signal \rgb[23]_i_10_n_0\ : STD_LOGIC;
signal \rgb[23]_i_11_n_0\ : STD_LOGIC;
signal \rgb[23]_i_12_n_0\ : STD_LOGIC;
signal \rgb[23]_i_13_n_0\ : STD_LOGIC;
signal \rgb[23]_i_14_n_0\ : STD_LOGIC;
signal \rgb[23]_i_15_n_0\ : STD_LOGIC;
signal \rgb[23]_i_16_n_0\ : STD_LOGIC;
signal \rgb[23]_i_17_n_0\ : STD_LOGIC;
signal \rgb[23]_i_18_n_0\ : STD_LOGIC;
signal \rgb[23]_i_1_n_0\ : STD_LOGIC;
signal \rgb[23]_i_2_n_0\ : STD_LOGIC;
signal \rgb[23]_i_3_n_0\ : STD_LOGIC;
signal \rgb[23]_i_4_n_0\ : STD_LOGIC;
signal \rgb[23]_i_5_n_0\ : STD_LOGIC;
signal \rgb[23]_i_6_n_0\ : STD_LOGIC;
signal \rgb[23]_i_7_n_0\ : STD_LOGIC;
signal \rgb[23]_i_8_n_0\ : STD_LOGIC;
signal \rgb[23]_i_9_n_0\ : STD_LOGIC;
signal \rgb[4]_i_1_n_0\ : STD_LOGIC;
signal \rgb[4]_i_2_n_0\ : STD_LOGIC;
signal \rgb[5]_i_1_n_0\ : STD_LOGIC;
signal \rgb[5]_i_2_n_0\ : STD_LOGIC;
signal \rgb[6]_i_1_n_0\ : STD_LOGIC;
signal \rgb[6]_i_2_n_0\ : STD_LOGIC;
signal \rgb[6]_i_3_n_0\ : STD_LOGIC;
signal \rgb[6]_i_4_n_0\ : STD_LOGIC;
signal \rgb[6]_i_5_n_0\ : STD_LOGIC;
signal \rgb[7]_i_1_n_0\ : STD_LOGIC;
signal \rgb[7]_i_2_n_0\ : STD_LOGIC;
signal \rgb[7]_i_3_n_0\ : STD_LOGIC;
signal \rgb[7]_i_4_n_0\ : STD_LOGIC;
signal \rgb[7]_i_5_n_0\ : STD_LOGIC;
signal \rgb[7]_i_6_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \rgb[14]_i_3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rgb[14]_i_5\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \rgb[15]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \rgb[15]_i_3\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \rgb[15]_i_5\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \rgb[15]_i_6\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \rgb[15]_i_7\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rgb[22]_i_10\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rgb[22]_i_11\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \rgb[23]_i_10\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rgb[23]_i_11\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \rgb[23]_i_14\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \rgb[23]_i_15\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \rgb[23]_i_17\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \rgb[23]_i_18\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \rgb[23]_i_6\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rgb[5]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \rgb[6]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rgb[6]_i_4\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \rgb[6]_i_5\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \rgb[7]_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rgb[7]_i_4\ : label is "soft_lutpair5";
begin
\rgb[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"5555FF02"
)
port map (
I0 => \rgb[15]_i_4_n_0\,
I1 => \rgb[14]_i_2_n_0\,
I2 => \rgb[14]_i_3_n_0\,
I3 => \rgb[22]_i_2_n_0\,
I4 => \rgb[23]_i_6_n_0\,
O => \rgb[13]_i_1_n_0\
);
\rgb[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555555FFFFFF02"
)
port map (
I0 => \rgb[15]_i_4_n_0\,
I1 => \rgb[14]_i_2_n_0\,
I2 => \rgb[14]_i_3_n_0\,
I3 => \rgb[22]_i_3_n_0\,
I4 => \rgb[22]_i_2_n_0\,
I5 => \rgb[23]_i_6_n_0\,
O => \rgb[14]_i_1_n_0\
);
\rgb[14]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"02F20202"
)
port map (
I0 => \rgb[14]_i_4_n_0\,
I1 => \rgb[23]_i_11_n_0\,
I2 => xaddr(9),
I3 => \rgb[14]_i_5_n_0\,
I4 => \rgb[23]_i_10_n_0\,
O => \rgb[14]_i_2_n_0\
);
\rgb[14]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb[14]_i_6_n_0\,
I1 => yaddr(6),
O => \rgb[14]_i_3_n_0\
);
\rgb[14]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFEFEFEFEFEEE"
)
port map (
I0 => xaddr(4),
I1 => xaddr(5),
I2 => xaddr(3),
I3 => xaddr(0),
I4 => xaddr(1),
I5 => xaddr(2),
O => \rgb[14]_i_4_n_0\
);
\rgb[14]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFF8"
)
port map (
I0 => xaddr(2),
I1 => xaddr(5),
I2 => xaddr(7),
I3 => xaddr(6),
I4 => xaddr(8),
O => \rgb[14]_i_5_n_0\
);
\rgb[14]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A888A888A8888888"
)
port map (
I0 => yaddr(5),
I1 => yaddr(4),
I2 => yaddr(2),
I3 => yaddr(3),
I4 => yaddr(1),
I5 => yaddr(0),
O => \rgb[14]_i_6_n_0\
);
\rgb[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFF55455545"
)
port map (
I0 => \rgb[23]_i_4_n_0\,
I1 => \rgb[22]_i_2_n_0\,
I2 => \rgb[15]_i_2_n_0\,
I3 => \rgb[15]_i_3_n_0\,
I4 => \rgb[15]_i_4_n_0\,
I5 => \rgb[23]_i_6_n_0\,
O => \rgb[15]_i_1_n_0\
);
\rgb[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \rgb[22]_i_8_n_0\,
I1 => \rgb[23]_i_12_n_0\,
O => \rgb[15]_i_2_n_0\
);
\rgb[15]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA88888"
)
port map (
I0 => \rgb[14]_i_3_n_0\,
I1 => xaddr(9),
I2 => xaddr(6),
I3 => xaddr(7),
I4 => xaddr(8),
O => \rgb[15]_i_3_n_0\
);
\rgb[15]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"ECEEEEEEECECECEC"
)
port map (
I0 => xaddr(8),
I1 => xaddr(9),
I2 => xaddr(7),
I3 => \rgb[15]_i_5_n_0\,
I4 => \rgb[15]_i_6_n_0\,
I5 => \rgb[15]_i_7_n_0\,
O => \rgb[15]_i_4_n_0\
);
\rgb[15]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"1F"
)
port map (
I0 => xaddr(0),
I1 => xaddr(1),
I2 => xaddr(2),
O => \rgb[15]_i_5_n_0\
);
\rgb[15]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => xaddr(5),
I1 => xaddr(4),
O => \rgb[15]_i_6_n_0\
);
\rgb[15]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8880"
)
port map (
I0 => xaddr(6),
I1 => xaddr(5),
I2 => xaddr(4),
I3 => xaddr(3),
O => \rgb[15]_i_7_n_0\
);
\rgb[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFBF0FB"
)
port map (
I0 => \rgb[22]_i_2_n_0\,
I1 => \rgb[22]_i_4_n_0\,
I2 => \rgb[23]_i_2_n_0\,
I3 => \rgb[23]_i_6_n_0\,
I4 => \rgb[23]_i_7_n_0\,
O => \rgb[21]_i_1_n_0\
);
\rgb[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEFFF00FFEF"
)
port map (
I0 => \rgb[22]_i_2_n_0\,
I1 => \rgb[22]_i_3_n_0\,
I2 => \rgb[22]_i_4_n_0\,
I3 => \rgb[23]_i_2_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[23]_i_7_n_0\,
O => \rgb[22]_i_1_n_0\
);
\rgb[22]_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => xaddr(9),
I1 => xaddr(6),
I2 => xaddr(7),
O => \rgb[22]_i_10_n_0\
);
\rgb[22]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"0070"
)
port map (
I0 => xaddr(3),
I1 => xaddr(4),
I2 => xaddr(8),
I3 => xaddr(5),
O => \rgb[22]_i_11_n_0\
);
\rgb[22]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAABABAB"
)
port map (
I0 => \rgb[22]_i_5_n_0\,
I1 => xaddr(8),
I2 => xaddr(9),
I3 => xaddr(6),
I4 => xaddr(7),
I5 => \rgb[22]_i_6_n_0\,
O => \rgb[22]_i_2_n_0\
);
\rgb[22]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000FD0000"
)
port map (
I0 => \rgb[23]_i_15_n_0\,
I1 => xaddr(4),
I2 => xaddr(5),
I3 => \rgb[22]_i_7_n_0\,
I4 => xaddr(9),
I5 => \rgb[22]_i_6_n_0\,
O => \rgb[22]_i_3_n_0\
);
\rgb[22]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFAE"
)
port map (
I0 => \rgb[23]_i_7_n_0\,
I1 => \rgb[22]_i_8_n_0\,
I2 => \rgb[23]_i_8_n_0\,
I3 => \rgb[14]_i_3_n_0\,
O => \rgb[22]_i_4_n_0\
);
\rgb[22]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000200030003"
)
port map (
I0 => \rgb[15]_i_5_n_0\,
I1 => xaddr(9),
I2 => xaddr(8),
I3 => xaddr(5),
I4 => xaddr(3),
I5 => xaddr(4),
O => \rgb[22]_i_5_n_0\
);
\rgb[22]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"111111111111111F"
)
port map (
I0 => \rgb[14]_i_6_n_0\,
I1 => yaddr(6),
I2 => \rgb[22]_i_9_n_0\,
I3 => xaddr(7),
I4 => xaddr(8),
I5 => xaddr(9),
O => \rgb[22]_i_6_n_0\
);
\rgb[22]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFEFEFFFFFFFF"
)
port map (
I0 => xaddr(8),
I1 => xaddr(6),
I2 => xaddr(7),
I3 => xaddr(5),
I4 => xaddr(2),
I5 => \rgb[23]_i_10_n_0\,
O => \rgb[22]_i_7_n_0\
);
\rgb[22]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"5515551555151515"
)
port map (
I0 => \rgb[23]_i_14_n_0\,
I1 => \rgb[22]_i_10_n_0\,
I2 => \rgb[22]_i_11_n_0\,
I3 => xaddr(4),
I4 => xaddr(1),
I5 => xaddr(2),
O => \rgb[22]_i_8_n_0\
);
\rgb[22]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCC000088800000"
)
port map (
I0 => xaddr(3),
I1 => xaddr(6),
I2 => xaddr(2),
I3 => xaddr(1),
I4 => xaddr(5),
I5 => xaddr(4),
O => \rgb[22]_i_9_n_0\
);
\rgb[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAAEAAAEAAAE"
)
port map (
I0 => \rgb[23]_i_2_n_0\,
I1 => \rgb[23]_i_3_n_0\,
I2 => \rgb[23]_i_4_n_0\,
I3 => \rgb[23]_i_5_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[23]_i_7_n_0\,
O => \rgb[23]_i_1_n_0\
);
\rgb[23]_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"1F"
)
port map (
I0 => xaddr(3),
I1 => xaddr(4),
I2 => xaddr(5),
O => \rgb[23]_i_10_n_0\
);
\rgb[23]_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => xaddr(8),
I1 => xaddr(6),
I2 => xaddr(7),
O => \rgb[23]_i_11_n_0\
);
\rgb[23]_i_12\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => yaddr(6),
I1 => \rgb[14]_i_6_n_0\,
O => \rgb[23]_i_12_n_0\
);
\rgb[23]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"0515555515155555"
)
port map (
I0 => \rgb[23]_i_18_n_0\,
I1 => xaddr(4),
I2 => xaddr(5),
I3 => \rgb[23]_i_17_n_0\,
I4 => xaddr(6),
I5 => xaddr(3),
O => \rgb[23]_i_13_n_0\
);
\rgb[23]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => xaddr(9),
I1 => xaddr(8),
O => \rgb[23]_i_14_n_0\
);
\rgb[23]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"15"
)
port map (
I0 => xaddr(3),
I1 => xaddr(1),
I2 => xaddr(2),
O => \rgb[23]_i_15_n_0\
);
\rgb[23]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => xaddr(7),
I1 => xaddr(6),
O => \rgb[23]_i_16_n_0\
);
\rgb[23]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => xaddr(2),
I1 => xaddr(1),
O => \rgb[23]_i_17_n_0\
);
\rgb[23]_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => xaddr(7),
I1 => xaddr(8),
I2 => xaddr(9),
O => \rgb[23]_i_18_n_0\
);
\rgb[23]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000022222"
)
port map (
I0 => \rgb[15]_i_4_n_0\,
I1 => yaddr(6),
I2 => yaddr(4),
I3 => yaddr(3),
I4 => yaddr(5),
I5 => \rgb[23]_i_8_n_0\,
O => \rgb[23]_i_2_n_0\
);
\rgb[23]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAFFFB"
)
port map (
I0 => \rgb[14]_i_3_n_0\,
I1 => \rgb[15]_i_4_n_0\,
I2 => \rgb[23]_i_9_n_0\,
I3 => xaddr(9),
I4 => \rgb[23]_i_7_n_0\,
O => \rgb[23]_i_3_n_0\
);
\rgb[23]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004440"
)
port map (
I0 => xaddr(9),
I1 => \rgb[23]_i_9_n_0\,
I2 => \rgb[23]_i_10_n_0\,
I3 => \rgb[23]_i_11_n_0\,
I4 => \rgb[23]_i_12_n_0\,
O => \rgb[23]_i_4_n_0\
);
\rgb[23]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0057FFFF00570057"
)
port map (
I0 => yaddr(5),
I1 => yaddr(3),
I2 => yaddr(4),
I3 => yaddr(6),
I4 => \rgb[23]_i_12_n_0\,
I5 => \rgb[23]_i_13_n_0\,
O => \rgb[23]_i_5_n_0\
);
\rgb[23]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"0155"
)
port map (
I0 => yaddr(6),
I1 => yaddr(4),
I2 => yaddr(3),
I3 => yaddr(5),
O => \rgb[23]_i_6_n_0\
);
\rgb[23]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"40CC44CC44CC44CC"
)
port map (
I0 => xaddr(6),
I1 => \rgb[23]_i_14_n_0\,
I2 => \rgb[23]_i_15_n_0\,
I3 => xaddr(7),
I4 => xaddr(4),
I5 => xaddr(5),
O => \rgb[23]_i_7_n_0\
);
\rgb[23]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFD500000000"
)
port map (
I0 => \rgb[23]_i_10_n_0\,
I1 => xaddr(2),
I2 => xaddr(5),
I3 => \rgb[23]_i_16_n_0\,
I4 => xaddr(8),
I5 => xaddr(9),
O => \rgb[23]_i_8_n_0\
);
\rgb[23]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFFFE0"
)
port map (
I0 => \rgb[23]_i_17_n_0\,
I1 => xaddr(0),
I2 => xaddr(3),
I3 => xaddr(5),
I4 => xaddr(4),
I5 => \rgb[23]_i_11_n_0\,
O => \rgb[23]_i_9_n_0\
);
\rgb[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"04770404"
)
port map (
I0 => \rgb[6]_i_2_n_0\,
I1 => \rgb[23]_i_6_n_0\,
I2 => \rgb[23]_i_7_n_0\,
I3 => \rgb[4]_i_2_n_0\,
I4 => \rgb[5]_i_2_n_0\,
O => \rgb[4]_i_1_n_0\
);
\rgb[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF2F2FFFFF202F"
)
port map (
I0 => \rgb[22]_i_8_n_0\,
I1 => \rgb[15]_i_4_n_0\,
I2 => \rgb[23]_i_12_n_0\,
I3 => \rgb[6]_i_5_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[23]_i_13_n_0\,
O => \rgb[4]_i_2_n_0\
);
\rgb[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAFEAAAAAAAA"
)
port map (
I0 => \rgb[7]_i_4_n_0\,
I1 => \rgb[15]_i_2_n_0\,
I2 => \rgb[15]_i_4_n_0\,
I3 => \rgb[15]_i_3_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[5]_i_2_n_0\,
O => \rgb[5]_i_1_n_0\
);
\rgb[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F7F0F7F"
)
port map (
I0 => \rgb[14]_i_2_n_0\,
I1 => \rgb[22]_i_8_n_0\,
I2 => \rgb[23]_i_12_n_0\,
I3 => \rgb[23]_i_7_n_0\,
I4 => \rgb[7]_i_3_n_0\,
O => \rgb[5]_i_2_n_0\
);
\rgb[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000F000FFFFF0045"
)
port map (
I0 => \rgb[14]_i_3_n_0\,
I1 => \rgb[7]_i_3_n_0\,
I2 => \rgb[23]_i_7_n_0\,
I3 => \rgb[6]_i_2_n_0\,
I4 => \rgb[6]_i_3_n_0\,
I5 => \rgb[23]_i_6_n_0\,
O => \rgb[6]_i_1_n_0\
);
\rgb[6]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => \rgb[14]_i_2_n_0\,
I1 => \rgb[22]_i_8_n_0\,
I2 => \rgb[7]_i_6_n_0\,
O => \rgb[6]_i_2_n_0\
);
\rgb[6]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00FF0002"
)
port map (
I0 => xaddr(9),
I1 => \rgb[22]_i_7_n_0\,
I2 => \rgb[6]_i_4_n_0\,
I3 => \rgb[22]_i_6_n_0\,
I4 => \rgb[6]_i_5_n_0\,
O => \rgb[6]_i_3_n_0\
);
\rgb[6]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000007"
)
port map (
I0 => xaddr(2),
I1 => xaddr(1),
I2 => xaddr(3),
I3 => xaddr(4),
I4 => xaddr(5),
O => \rgb[6]_i_4_n_0\
);
\rgb[6]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"0057"
)
port map (
I0 => xaddr(8),
I1 => xaddr(7),
I2 => xaddr(6),
I3 => xaddr(9),
O => \rgb[6]_i_5_n_0\
);
\rgb[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000222A"
)
port map (
I0 => \rgb[7]_i_3_n_0\,
I1 => yaddr(5),
I2 => yaddr(3),
I3 => yaddr(4),
I4 => yaddr(6),
O => \rgb[7]_i_1_n_0\
);
\rgb[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF000000FB"
)
port map (
I0 => \rgb[7]_i_3_n_0\,
I1 => \rgb[23]_i_7_n_0\,
I2 => \rgb[14]_i_3_n_0\,
I3 => \rgb[23]_i_4_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[7]_i_4_n_0\,
O => \rgb[7]_i_2_n_0\
);
\rgb[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000000D"
)
port map (
I0 => xaddr(6),
I1 => \rgb[7]_i_5_n_0\,
I2 => xaddr(9),
I3 => xaddr(8),
I4 => xaddr(7),
O => \rgb[7]_i_3_n_0\
);
\rgb[7]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000444"
)
port map (
I0 => \rgb[23]_i_7_n_0\,
I1 => \rgb[23]_i_6_n_0\,
I2 => \rgb[7]_i_6_n_0\,
I3 => \rgb[22]_i_8_n_0\,
I4 => \rgb[14]_i_2_n_0\,
O => \rgb[7]_i_4_n_0\
);
\rgb[7]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"1515155515155555"
)
port map (
I0 => xaddr(5),
I1 => xaddr(3),
I2 => xaddr(4),
I3 => xaddr(0),
I4 => xaddr(2),
I5 => xaddr(1),
O => \rgb[7]_i_5_n_0\
);
\rgb[7]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000007F55"
)
port map (
I0 => \rgb[15]_i_7_n_0\,
I1 => xaddr(4),
I2 => xaddr(5),
I3 => \rgb[15]_i_5_n_0\,
I4 => xaddr(7),
I5 => xaddr(9),
O => \rgb[7]_i_6_n_0\
);
\rgb_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[13]_i_1_n_0\,
Q => rgb(4),
R => '0'
);
\rgb_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[14]_i_1_n_0\,
Q => rgb(5),
R => '0'
);
\rgb_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[15]_i_1_n_0\,
Q => rgb(6),
R => '0'
);
\rgb_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[21]_i_1_n_0\,
Q => rgb(7),
R => '0'
);
\rgb_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[22]_i_1_n_0\,
Q => rgb(8),
R => '0'
);
\rgb_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[23]_i_1_n_0\,
Q => rgb(9),
R => '0'
);
\rgb_reg[4]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => '1',
D => \rgb[4]_i_1_n_0\,
Q => rgb(0),
S => \rgb[7]_i_1_n_0\
);
\rgb_reg[5]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => '1',
D => \rgb[5]_i_1_n_0\,
Q => rgb(1),
S => \rgb[7]_i_1_n_0\
);
\rgb_reg[6]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => '1',
D => \rgb[6]_i_1_n_0\,
Q => rgb(2),
S => \rgb[7]_i_1_n_0\
);
\rgb_reg[7]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => '1',
D => \rgb[7]_i_2_n_0\,
Q => rgb(3),
S => \rgb[7]_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_color_test_0_0 is
port (
clk_25 : in STD_LOGIC;
xaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_color_test_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_color_test_0_0 : entity is "system_vga_color_test_0_0,vga_color_test,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_color_test_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_color_test_0_0 : entity is "vga_color_test,Vivado 2016.4";
end system_vga_color_test_0_0;
architecture STRUCTURE of system_vga_color_test_0_0 is
signal \^rgb\ : STD_LOGIC_VECTOR ( 23 downto 3 );
begin
rgb(23 downto 22) <= \^rgb\(23 downto 22);
rgb(21) <= \^rgb\(20);
rgb(20) <= \^rgb\(20);
rgb(19) <= \^rgb\(20);
rgb(18) <= \^rgb\(20);
rgb(17) <= \^rgb\(20);
rgb(16) <= \^rgb\(20);
rgb(15 downto 14) <= \^rgb\(15 downto 14);
rgb(13) <= \^rgb\(12);
rgb(12) <= \^rgb\(12);
rgb(11) <= \^rgb\(12);
rgb(10) <= \^rgb\(12);
rgb(9) <= \^rgb\(12);
rgb(8) <= \^rgb\(12);
rgb(7 downto 5) <= \^rgb\(7 downto 5);
rgb(4) <= \^rgb\(3);
rgb(3) <= \^rgb\(3);
rgb(2) <= \^rgb\(3);
rgb(1) <= \^rgb\(3);
rgb(0) <= \^rgb\(3);
U0: entity work.system_vga_color_test_0_0_vga_color_test
port map (
clk_25 => clk_25,
rgb(9 downto 8) => \^rgb\(23 downto 22),
rgb(7) => \^rgb\(20),
rgb(6 downto 5) => \^rgb\(15 downto 14),
rgb(4) => \^rgb\(12),
rgb(3 downto 1) => \^rgb\(7 downto 5),
rgb(0) => \^rgb\(3),
xaddr(9 downto 0) => xaddr(9 downto 0),
yaddr(6 downto 0) => yaddr(9 downto 3)
);
end STRUCTURE;
| mit | faa141afba9009095c2420c0545f3546 | 0.478191 | 2.486567 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_to_uint_0_0/affine_block_ieee754_fp_to_uint_0_0_sim_netlist.vhdl | 1 | 59,879 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 20 13:52:57 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top affine_block_ieee754_fp_to_uint_0_0 -prefix
-- affine_block_ieee754_fp_to_uint_0_0_ affine_block_ieee754_fp_to_uint_0_1_sim_netlist.vhdl
-- Design : affine_block_ieee754_fp_to_uint_0_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity affine_block_ieee754_fp_to_uint_0_0_ieee754_fp_to_uint is
port (
y : out STD_LOGIC_VECTOR ( 9 downto 0 );
\y_8__s_port_\ : out STD_LOGIC;
x : in STD_LOGIC_VECTOR ( 17 downto 0 );
\x[20]\ : in STD_LOGIC;
\x[25]\ : in STD_LOGIC;
\x_7__s_port_\ : in STD_LOGIC;
\x[22]\ : in STD_LOGIC;
\x[21]\ : in STD_LOGIC;
\x[22]_0\ : in STD_LOGIC;
\x[21]_0\ : in STD_LOGIC;
\x[27]\ : in STD_LOGIC;
\x[25]_0\ : in STD_LOGIC;
\x[22]_1\ : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 2 downto 0 );
\x[25]_1\ : in STD_LOGIC;
\x[25]_2\ : in STD_LOGIC;
\x[23]\ : in STD_LOGIC;
\x[27]_0\ : in STD_LOGIC;
\x[24]\ : in STD_LOGIC;
\x[30]\ : in STD_LOGIC;
\x[25]_3\ : in STD_LOGIC;
\x[24]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\x[24]_1\ : in STD_LOGIC;
\x[25]_4\ : in STD_LOGIC
);
end affine_block_ieee754_fp_to_uint_0_0_ieee754_fp_to_uint;
architecture STRUCTURE of affine_block_ieee754_fp_to_uint_0_0_ieee754_fp_to_uint is
signal \x_7__s_net_1\ : STD_LOGIC;
signal y2 : STD_LOGIC;
signal \y2_carry__0_n_0\ : STD_LOGIC;
signal \y2_carry__0_n_1\ : STD_LOGIC;
signal \y2_carry__0_n_2\ : STD_LOGIC;
signal \y2_carry__0_n_3\ : STD_LOGIC;
signal \y2_carry__1_n_0\ : STD_LOGIC;
signal \y2_carry__1_n_1\ : STD_LOGIC;
signal \y2_carry__1_n_2\ : STD_LOGIC;
signal \y2_carry__1_n_3\ : STD_LOGIC;
signal \y2_carry__2_n_1\ : STD_LOGIC;
signal \y2_carry__2_n_2\ : STD_LOGIC;
signal \y2_carry__2_n_3\ : STD_LOGIC;
signal \y2_carry_i_1__1_n_0\ : STD_LOGIC;
signal \y2_carry_i_1__2_n_0\ : STD_LOGIC;
signal y2_carry_i_1_n_0 : STD_LOGIC;
signal \y2_carry_i_2__0_n_0\ : STD_LOGIC;
signal \y2_carry_i_2__1_n_0\ : STD_LOGIC;
signal \y2_carry_i_2__2_n_0\ : STD_LOGIC;
signal y2_carry_i_2_n_0 : STD_LOGIC;
signal \y2_carry_i_3__0_n_0\ : STD_LOGIC;
signal \y2_carry_i_3__1_n_0\ : STD_LOGIC;
signal \y2_carry_i_3__2_n_0\ : STD_LOGIC;
signal y2_carry_i_3_n_0 : STD_LOGIC;
signal \y2_carry_i_4__0_n_0\ : STD_LOGIC;
signal \y2_carry_i_4__1_n_0\ : STD_LOGIC;
signal \y2_carry_i_4__2_n_0\ : STD_LOGIC;
signal y2_carry_i_4_n_0 : STD_LOGIC;
signal \y2_carry_i_5__0_n_0\ : STD_LOGIC;
signal y2_carry_i_5_n_0 : STD_LOGIC;
signal y2_carry_i_6_n_0 : STD_LOGIC;
signal y2_carry_i_7_n_0 : STD_LOGIC;
signal y2_carry_i_8_n_0 : STD_LOGIC;
signal y2_carry_n_0 : STD_LOGIC;
signal y2_carry_n_1 : STD_LOGIC;
signal y2_carry_n_2 : STD_LOGIC;
signal y2_carry_n_3 : STD_LOGIC;
signal y3 : STD_LOGIC_VECTOR ( 31 to 31 );
signal \y[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[2]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[2]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[3]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[4]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[4]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[5]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[5]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[6]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[6]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_15_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[8]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[8]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[8]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_12_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_14_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \y_8__s_net_1\ : STD_LOGIC;
signal NLW_y2_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y2_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y2_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y2_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of y2_carry_i_9 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \y[3]_INST_0_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \y[4]_INST_0_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \y[5]_INST_0_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \y[6]_INST_0_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \y[7]_INST_0_i_3\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \y[9]_INST_0_i_10\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \y[9]_INST_0_i_9\ : label is "soft_lutpair0";
begin
\x_7__s_net_1\ <= \x_7__s_port_\;
\y_8__s_port_\ <= \y_8__s_net_1\;
y2_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => y2_carry_n_0,
CO(2) => y2_carry_n_1,
CO(1) => y2_carry_n_2,
CO(0) => y2_carry_n_3,
CYINIT => '1',
DI(3) => y2_carry_i_1_n_0,
DI(2) => y2_carry_i_2_n_0,
DI(1) => y2_carry_i_3_n_0,
DI(0) => y2_carry_i_4_n_0,
O(3 downto 0) => NLW_y2_carry_O_UNCONNECTED(3 downto 0),
S(3) => y2_carry_i_5_n_0,
S(2) => y2_carry_i_6_n_0,
S(1) => y2_carry_i_7_n_0,
S(0) => y2_carry_i_8_n_0
);
\y2_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => y2_carry_n_0,
CO(3) => \y2_carry__0_n_0\,
CO(2) => \y2_carry__0_n_1\,
CO(1) => \y2_carry__0_n_2\,
CO(0) => \y2_carry__0_n_3\,
CYINIT => '0',
DI(3) => y3(31),
DI(2) => y3(31),
DI(1) => y3(31),
DI(0) => '1',
O(3 downto 0) => \NLW_y2_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \y2_carry_i_2__2_n_0\,
S(2) => \y2_carry_i_3__2_n_0\,
S(1) => \y2_carry_i_4__2_n_0\,
S(0) => \y2_carry_i_5__0_n_0\
);
\y2_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \y2_carry__0_n_0\,
CO(3) => \y2_carry__1_n_0\,
CO(2) => \y2_carry__1_n_1\,
CO(1) => \y2_carry__1_n_2\,
CO(0) => \y2_carry__1_n_3\,
CYINIT => '0',
DI(3) => y3(31),
DI(2) => y3(31),
DI(1) => y3(31),
DI(0) => y3(31),
O(3 downto 0) => \NLW_y2_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \y2_carry_i_1__2_n_0\,
S(2) => \y2_carry_i_2__1_n_0\,
S(1) => \y2_carry_i_3__1_n_0\,
S(0) => \y2_carry_i_4__1_n_0\
);
\y2_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \y2_carry__1_n_0\,
CO(3) => y2,
CO(2) => \y2_carry__2_n_1\,
CO(1) => \y2_carry__2_n_2\,
CO(0) => \y2_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => y3(31),
DI(1) => y3(31),
DI(0) => y3(31),
O(3 downto 0) => \NLW_y2_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \y2_carry_i_1__1_n_0\,
S(2) => \y2_carry_i_2__0_n_0\,
S(1) => \y2_carry_i_3__0_n_0\,
S(0) => \y2_carry_i_4__0_n_0\
);
y2_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFEAA0155FFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => y2_carry_i_1_n_0
);
\y2_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFEAA00000000"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => y3(31)
);
\y2_carry_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_1__1_n_0\
);
\y2_carry_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_1__2_n_0\
);
y2_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFAAAA9555"
)
port map (
I0 => x(14),
I1 => x(12),
I2 => x(11),
I3 => x(10),
I4 => x(13),
I5 => x(15),
O => y2_carry_i_2_n_0
);
\y2_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_2__0_n_0\
);
\y2_carry_i_2__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_2__1_n_0\
);
\y2_carry_i_2__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_2__2_n_0\
);
y2_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"EABF"
)
port map (
I0 => x(13),
I1 => x(10),
I2 => x(11),
I3 => x(12),
O => y2_carry_i_3_n_0
);
\y2_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_3__0_n_0\
);
\y2_carry_i_3__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_3__1_n_0\
);
\y2_carry_i_3__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_3__2_n_0\
);
y2_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => x(10),
I1 => x(11),
O => y2_carry_i_4_n_0
);
\y2_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_4__0_n_0\
);
\y2_carry_i_4__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_4__1_n_0\
);
\y2_carry_i_4__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_4__2_n_0\
);
y2_carry_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444442424222"
)
port map (
I0 => x(17),
I1 => x(16),
I2 => x(14),
I3 => \y_8__s_net_1\,
I4 => x(13),
I5 => x(15),
O => y2_carry_i_5_n_0
);
\y2_carry_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_5__0_n_0\
);
y2_carry_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"0111111154444444"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => x(10),
I3 => x(11),
I4 => x(12),
I5 => x(14),
O => y2_carry_i_6_n_0
);
y2_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"006A"
)
port map (
I0 => x(12),
I1 => x(11),
I2 => x(10),
I3 => x(13),
O => y2_carry_i_7_n_0
);
y2_carry_i_8: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => x(11),
I1 => x(10),
O => y2_carry_i_8_n_0
);
y2_carry_i_9: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => x(12),
I1 => x(11),
I2 => x(10),
O => \y_8__s_net_1\
);
\y[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4540FFFF45404540"
)
port map (
I0 => \y[7]_INST_0_i_3_n_0\,
I1 => \x[25]_0\,
I2 => x(10),
I3 => \x[22]_1\,
I4 => \y[0]_INST_0_i_2_n_0\,
I5 => \y[7]_INST_0_i_5_n_0\,
O => y(0)
);
\y[0]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFB"
)
port map (
I0 => \y[2]_INST_0_i_4_n_0\,
I1 => x(0),
I2 => x(10),
I3 => y2,
I4 => O(0),
O => \y[0]_INST_0_i_2_n_0\
);
\y[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4540FFFF45404540"
)
port map (
I0 => \y[7]_INST_0_i_3_n_0\,
I1 => \x[27]\,
I2 => x(10),
I3 => \x[25]_0\,
I4 => \y[1]_INST_0_i_2_n_0\,
I5 => \y[9]_INST_0_i_4_n_0\,
O => y(1)
);
\y[1]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF4F7FFFFFFFF"
)
port map (
I0 => x(0),
I1 => x(10),
I2 => \y[9]_INST_0_i_10_n_0\,
I3 => x(1),
I4 => \y[9]_INST_0_i_8_n_0\,
I5 => \y[9]_INST_0_i_9_n_0\,
O => \y[1]_INST_0_i_2_n_0\
);
\y[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4540FFFF45404540"
)
port map (
I0 => \y[7]_INST_0_i_3_n_0\,
I1 => \x[21]_0\,
I2 => x(10),
I3 => \x[27]\,
I4 => \y[2]_INST_0_i_2_n_0\,
I5 => \y[7]_INST_0_i_5_n_0\,
O => y(2)
);
\y[2]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFCFAAAA"
)
port map (
I0 => \y[3]_INST_0_i_4_n_0\,
I1 => \y[9]_INST_0_i_10_n_0\,
I2 => x(1),
I3 => \y[2]_INST_0_i_4_n_0\,
I4 => x(10),
I5 => y2,
O => \y[2]_INST_0_i_2_n_0\
);
\y[2]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"CFFFCAFA"
)
port map (
I0 => O(2),
I1 => \x[25]_4\,
I2 => y2,
I3 => \x[25]_3\,
I4 => O(1),
O => \y[2]_INST_0_i_4_n_0\
);
\y[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4540FFFF45404540"
)
port map (
I0 => \y[7]_INST_0_i_3_n_0\,
I1 => \x[22]_0\,
I2 => x(10),
I3 => \x[21]_0\,
I4 => \y[3]_INST_0_i_2_n_0\,
I5 => \y[7]_INST_0_i_5_n_0\,
O => y(3)
);
\y[3]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFCA"
)
port map (
I0 => \y[4]_INST_0_i_4_n_0\,
I1 => \y[3]_INST_0_i_4_n_0\,
I2 => x(10),
I3 => y2,
O => \y[3]_INST_0_i_2_n_0\
);
\y[3]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF4FFF7F"
)
port map (
I0 => x(0),
I1 => \y[9]_INST_0_i_10_n_0\,
I2 => \y[9]_INST_0_i_9_n_0\,
I3 => \y[9]_INST_0_i_8_n_0\,
I4 => x(2),
O => \y[3]_INST_0_i_4_n_0\
);
\y[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4540FFFF45404540"
)
port map (
I0 => \y[7]_INST_0_i_3_n_0\,
I1 => \x[21]\,
I2 => x(10),
I3 => \x[22]_0\,
I4 => \y[4]_INST_0_i_2_n_0\,
I5 => \y[7]_INST_0_i_5_n_0\,
O => y(4)
);
\y[4]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFCA"
)
port map (
I0 => \y[5]_INST_0_i_4_n_0\,
I1 => \y[4]_INST_0_i_4_n_0\,
I2 => x(10),
I3 => y2,
O => \y[4]_INST_0_i_2_n_0\
);
\y[4]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF4FFF7F"
)
port map (
I0 => x(1),
I1 => \y[9]_INST_0_i_10_n_0\,
I2 => \y[9]_INST_0_i_9_n_0\,
I3 => \y[9]_INST_0_i_8_n_0\,
I4 => x(3),
O => \y[4]_INST_0_i_4_n_0\
);
\y[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"1510FFFF15101510"
)
port map (
I0 => \y[7]_INST_0_i_3_n_0\,
I1 => \x[22]\,
I2 => x(10),
I3 => \x[21]\,
I4 => \y[5]_INST_0_i_2_n_0\,
I5 => \y[7]_INST_0_i_5_n_0\,
O => y(5)
);
\y[5]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFCA"
)
port map (
I0 => \y[6]_INST_0_i_4_n_0\,
I1 => \y[5]_INST_0_i_4_n_0\,
I2 => x(10),
I3 => y2,
O => \y[5]_INST_0_i_2_n_0\
);
\y[5]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF47CCFFFF47FF"
)
port map (
I0 => x(2),
I1 => \y[9]_INST_0_i_10_n_0\,
I2 => x(4),
I3 => \y[9]_INST_0_i_9_n_0\,
I4 => \y[9]_INST_0_i_8_n_0\,
I5 => x(0),
O => \y[5]_INST_0_i_4_n_0\
);
\y[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0047FFFF00470047"
)
port map (
I0 => \x_7__s_net_1\,
I1 => x(10),
I2 => \x[22]\,
I3 => \y[7]_INST_0_i_3_n_0\,
I4 => \y[6]_INST_0_i_2_n_0\,
I5 => \y[7]_INST_0_i_5_n_0\,
O => y(6)
);
\y[6]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFCA"
)
port map (
I0 => \y[7]_INST_0_i_10_n_0\,
I1 => \y[6]_INST_0_i_4_n_0\,
I2 => x(10),
I3 => y2,
O => \y[6]_INST_0_i_2_n_0\
);
\y[6]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF47CCFFFF47FF"
)
port map (
I0 => x(3),
I1 => \y[9]_INST_0_i_10_n_0\,
I2 => x(5),
I3 => \y[9]_INST_0_i_9_n_0\,
I4 => \y[9]_INST_0_i_8_n_0\,
I5 => x(1),
O => \y[6]_INST_0_i_4_n_0\
);
\y[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0047FFFF00470047"
)
port map (
I0 => \x[20]\,
I1 => x(10),
I2 => \x_7__s_net_1\,
I3 => \y[7]_INST_0_i_3_n_0\,
I4 => \y[7]_INST_0_i_4_n_0\,
I5 => \y[7]_INST_0_i_5_n_0\,
O => y(7)
);
\y[7]_INST_0_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF47FFFFFF4700"
)
port map (
I0 => x(4),
I1 => \y[9]_INST_0_i_9_n_0\,
I2 => x(0),
I3 => \y[9]_INST_0_i_10_n_0\,
I4 => \y[9]_INST_0_i_8_n_0\,
I5 => \y[7]_INST_0_i_15_n_0\,
O => \y[7]_INST_0_i_10_n_0\
);
\y[7]_INST_0_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"50115FDD"
)
port map (
I0 => x(6),
I1 => O(1),
I2 => \x[25]_3\,
I3 => y2,
I4 => x(2),
O => \y[7]_INST_0_i_15_n_0\
);
\y[7]_INST_0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \x[23]\,
I1 => y2,
O => \y[7]_INST_0_i_3_n_0\
);
\y[7]_INST_0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFCA"
)
port map (
I0 => \y[8]_INST_0_i_2_n_0\,
I1 => \y[7]_INST_0_i_10_n_0\,
I2 => x(10),
I3 => y2,
O => \y[7]_INST_0_i_4_n_0\
);
\y[7]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"4040404040405F40"
)
port map (
I0 => \x[23]\,
I1 => \x[27]_0\,
I2 => y2,
I3 => \x[24]\,
I4 => \y[9]_INST_0_i_14_n_0\,
I5 => \x[30]\,
O => \y[7]_INST_0_i_5_n_0\
);
\y[8]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"BABFAAAA"
)
port map (
I0 => \y[8]_INST_0_i_1_n_0\,
I1 => \y[8]_INST_0_i_2_n_0\,
I2 => x(10),
I3 => \y[9]_INST_0_i_2_n_0\,
I4 => \y[9]_INST_0_i_4_n_0\,
O => y(8)
);
\y[8]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4501"
)
port map (
I0 => \y[7]_INST_0_i_3_n_0\,
I1 => x(10),
I2 => \x[20]\,
I3 => \x[25]\,
O => \y[8]_INST_0_i_1_n_0\
);
\y[8]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF4700FFFF47FF"
)
port map (
I0 => x(5),
I1 => \y[9]_INST_0_i_9_n_0\,
I2 => x(1),
I3 => \y[9]_INST_0_i_10_n_0\,
I4 => \y[9]_INST_0_i_8_n_0\,
I5 => \y[8]_INST_0_i_3_n_0\,
O => \y[8]_INST_0_i_2_n_0\
);
\y[8]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFEEA022"
)
port map (
I0 => x(7),
I1 => O(1),
I2 => \x[25]_3\,
I3 => y2,
I4 => x(3),
O => \y[8]_INST_0_i_3_n_0\
);
\y[9]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"BABFAAAA"
)
port map (
I0 => \y[9]_INST_0_i_1_n_0\,
I1 => \y[9]_INST_0_i_2_n_0\,
I2 => x(10),
I3 => \y[9]_INST_0_i_3_n_0\,
I4 => \y[9]_INST_0_i_4_n_0\,
O => y(9)
);
\y[9]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000E2EEE222"
)
port map (
I0 => \x[25]\,
I1 => x(10),
I2 => \x[25]_1\,
I3 => x(11),
I4 => \x[25]_2\,
I5 => \y[7]_INST_0_i_3_n_0\,
O => \y[9]_INST_0_i_1_n_0\
);
\y[9]_INST_0_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"9F90"
)
port map (
I0 => x(11),
I1 => x(10),
I2 => y2,
I3 => O(0),
O => \y[9]_INST_0_i_10_n_0\
);
\y[9]_INST_0_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"5533FF0F"
)
port map (
I0 => x(0),
I1 => x(8),
I2 => x(4),
I3 => \y[9]_INST_0_i_8_n_0\,
I4 => \y[9]_INST_0_i_9_n_0\,
O => \y[9]_INST_0_i_11_n_0\
);
\y[9]_INST_0_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"5353F0FF"
)
port map (
I0 => x(1),
I1 => x(9),
I2 => \y[9]_INST_0_i_8_n_0\,
I3 => x(5),
I4 => \y[9]_INST_0_i_9_n_0\,
O => \y[9]_INST_0_i_12_n_0\
);
\y[9]_INST_0_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => y2,
I1 => \x[24]_0\(1),
I2 => \x[24]_0\(0),
I3 => \x[24]_0\(2),
I4 => \x[24]_1\,
O => \y[9]_INST_0_i_14_n_0\
);
\y[9]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABFBFFFFABFB0000"
)
port map (
I0 => \y[9]_INST_0_i_8_n_0\,
I1 => x(2),
I2 => \y[9]_INST_0_i_9_n_0\,
I3 => x(6),
I4 => \y[9]_INST_0_i_10_n_0\,
I5 => \y[9]_INST_0_i_11_n_0\,
O => \y[9]_INST_0_i_2_n_0\
);
\y[9]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABFBFFFFABFB0000"
)
port map (
I0 => \y[9]_INST_0_i_8_n_0\,
I1 => x(3),
I2 => \y[9]_INST_0_i_9_n_0\,
I3 => x(7),
I4 => \y[9]_INST_0_i_10_n_0\,
I5 => \y[9]_INST_0_i_12_n_0\,
O => \y[9]_INST_0_i_3_n_0\
);
\y[9]_INST_0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \x[24]\,
I1 => \y[9]_INST_0_i_14_n_0\,
I2 => \x[30]\,
O => \y[9]_INST_0_i_4_n_0\
);
\y[9]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAFFFF6AAA0000"
)
port map (
I0 => x(13),
I1 => x(10),
I2 => x(11),
I3 => x(12),
I4 => y2,
I5 => O(2),
O => \y[9]_INST_0_i_8_n_0\
);
\y[9]_INST_0_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"3FC05555"
)
port map (
I0 => O(1),
I1 => x(11),
I2 => x(10),
I3 => x(12),
I4 => y2,
O => \y[9]_INST_0_i_9_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity affine_block_ieee754_fp_to_uint_0_0 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of affine_block_ieee754_fp_to_uint_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of affine_block_ieee754_fp_to_uint_0_0 : entity is "affine_block_ieee754_fp_to_uint_0_1,ieee754_fp_to_uint,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of affine_block_ieee754_fp_to_uint_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of affine_block_ieee754_fp_to_uint_0_0 : entity is "ieee754_fp_to_uint,Vivado 2016.4";
end affine_block_ieee754_fp_to_uint_0_0;
architecture STRUCTURE of affine_block_ieee754_fp_to_uint_0_0 is
signal U0_n_10 : STD_LOGIC;
signal y4 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \y[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[0]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[0]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[0]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[0]_INST_0_i_5_n_1\ : STD_LOGIC;
signal \y[0]_INST_0_i_5_n_2\ : STD_LOGIC;
signal \y[0]_INST_0_i_5_n_3\ : STD_LOGIC;
signal \y[0]_INST_0_i_5_n_4\ : STD_LOGIC;
signal \y[0]_INST_0_i_5_n_5\ : STD_LOGIC;
signal \y[0]_INST_0_i_5_n_6\ : STD_LOGIC;
signal \y[0]_INST_0_i_5_n_7\ : STD_LOGIC;
signal \y[0]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \y[0]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \y[0]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \y[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[1]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[1]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[2]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[2]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[3]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[3]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[4]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[4]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[5]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[5]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[6]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[6]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[6]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_12_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_13_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_14_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_13_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_15_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_16_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_17_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_18_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_19_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_20_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_20_n_1\ : STD_LOGIC;
signal \y[9]_INST_0_i_20_n_2\ : STD_LOGIC;
signal \y[9]_INST_0_i_20_n_3\ : STD_LOGIC;
signal \y[9]_INST_0_i_20_n_4\ : STD_LOGIC;
signal \y[9]_INST_0_i_20_n_5\ : STD_LOGIC;
signal \y[9]_INST_0_i_20_n_6\ : STD_LOGIC;
signal \y[9]_INST_0_i_20_n_7\ : STD_LOGIC;
signal \y[9]_INST_0_i_21_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_21_n_1\ : STD_LOGIC;
signal \y[9]_INST_0_i_21_n_2\ : STD_LOGIC;
signal \y[9]_INST_0_i_21_n_3\ : STD_LOGIC;
signal \y[9]_INST_0_i_21_n_4\ : STD_LOGIC;
signal \y[9]_INST_0_i_21_n_5\ : STD_LOGIC;
signal \y[9]_INST_0_i_21_n_6\ : STD_LOGIC;
signal \y[9]_INST_0_i_21_n_7\ : STD_LOGIC;
signal \y[9]_INST_0_i_22_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_22_n_1\ : STD_LOGIC;
signal \y[9]_INST_0_i_22_n_2\ : STD_LOGIC;
signal \y[9]_INST_0_i_22_n_3\ : STD_LOGIC;
signal \y[9]_INST_0_i_22_n_4\ : STD_LOGIC;
signal \y[9]_INST_0_i_22_n_5\ : STD_LOGIC;
signal \y[9]_INST_0_i_22_n_6\ : STD_LOGIC;
signal \y[9]_INST_0_i_22_n_7\ : STD_LOGIC;
signal \y[9]_INST_0_i_23_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_24_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_25_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_25_n_1\ : STD_LOGIC;
signal \y[9]_INST_0_i_25_n_2\ : STD_LOGIC;
signal \y[9]_INST_0_i_25_n_3\ : STD_LOGIC;
signal \y[9]_INST_0_i_25_n_4\ : STD_LOGIC;
signal \y[9]_INST_0_i_25_n_5\ : STD_LOGIC;
signal \y[9]_INST_0_i_25_n_6\ : STD_LOGIC;
signal \y[9]_INST_0_i_25_n_7\ : STD_LOGIC;
signal \y[9]_INST_0_i_26_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_27_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_27_n_1\ : STD_LOGIC;
signal \y[9]_INST_0_i_27_n_2\ : STD_LOGIC;
signal \y[9]_INST_0_i_27_n_3\ : STD_LOGIC;
signal \y[9]_INST_0_i_27_n_4\ : STD_LOGIC;
signal \y[9]_INST_0_i_27_n_5\ : STD_LOGIC;
signal \y[9]_INST_0_i_27_n_6\ : STD_LOGIC;
signal \y[9]_INST_0_i_27_n_7\ : STD_LOGIC;
signal \y[9]_INST_0_i_28_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_28_n_1\ : STD_LOGIC;
signal \y[9]_INST_0_i_28_n_2\ : STD_LOGIC;
signal \y[9]_INST_0_i_28_n_3\ : STD_LOGIC;
signal \y[9]_INST_0_i_28_n_4\ : STD_LOGIC;
signal \y[9]_INST_0_i_28_n_5\ : STD_LOGIC;
signal \y[9]_INST_0_i_28_n_6\ : STD_LOGIC;
signal \y[9]_INST_0_i_28_n_7\ : STD_LOGIC;
signal \y[9]_INST_0_i_29_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_30_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_31_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_32_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_33_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_34_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_35_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_36_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_37_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_38_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_39_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_40_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_41_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_42_n_3\ : STD_LOGIC;
signal \y[9]_INST_0_i_42_n_6\ : STD_LOGIC;
signal \y[9]_INST_0_i_42_n_7\ : STD_LOGIC;
signal \y[9]_INST_0_i_43_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_44_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_45_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_46_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_47_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_48_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_49_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_50_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_51_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_52_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_53_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_54_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_55_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_56_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \NLW_y[9]_INST_0_i_42_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y[9]_INST_0_i_42_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \y[0]_INST_0_i_4\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \y[1]_INST_0_i_3\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \y[2]_INST_0_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \y[2]_INST_0_i_3\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \y[2]_INST_0_i_5\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \y[3]_INST_0_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \y[4]_INST_0_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \y[5]_INST_0_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \y[6]_INST_0_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \y[7]_INST_0_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \y[7]_INST_0_i_11\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \y[7]_INST_0_i_12\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \y[7]_INST_0_i_13\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \y[7]_INST_0_i_2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \y[9]_INST_0_i_17\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \y[9]_INST_0_i_18\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \y[9]_INST_0_i_19\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \y[9]_INST_0_i_5\ : label is "soft_lutpair9";
begin
U0: entity work.affine_block_ieee754_fp_to_uint_0_0_ieee754_fp_to_uint
port map (
O(2) => \y[0]_INST_0_i_5_n_5\,
O(1) => \y[0]_INST_0_i_5_n_6\,
O(0) => \y[0]_INST_0_i_5_n_7\,
x(17 downto 10) => x(30 downto 23),
x(9 downto 0) => x(9 downto 0),
\x[20]\ => \y[7]_INST_0_i_1_n_0\,
\x[21]\ => \y[5]_INST_0_i_1_n_0\,
\x[21]_0\ => \y[3]_INST_0_i_1_n_0\,
\x[22]\ => \y[6]_INST_0_i_1_n_0\,
\x[22]_0\ => \y[4]_INST_0_i_1_n_0\,
\x[22]_1\ => \y[0]_INST_0_i_1_n_0\,
\x[23]\ => \y[7]_INST_0_i_9_n_0\,
\x[24]\ => \y[9]_INST_0_i_13_n_0\,
\x[24]_0\(2) => \y[9]_INST_0_i_25_n_4\,
\x[24]_0\(1) => \y[9]_INST_0_i_25_n_5\,
\x[24]_0\(0) => \y[9]_INST_0_i_25_n_7\,
\x[24]_1\ => \y[9]_INST_0_i_26_n_0\,
\x[25]\ => \y[9]_INST_0_i_5_n_0\,
\x[25]_0\ => \y[1]_INST_0_i_1_n_0\,
\x[25]_1\ => \y[9]_INST_0_i_6_n_0\,
\x[25]_2\ => \y[9]_INST_0_i_7_n_0\,
\x[25]_3\ => \y[9]_INST_0_i_17_n_0\,
\x[25]_4\ => \y[9]_INST_0_i_18_n_0\,
\x[27]\ => \y[2]_INST_0_i_1_n_0\,
\x[27]_0\ => \y[7]_INST_0_i_11_n_0\,
\x[30]\ => \y[9]_INST_0_i_15_n_0\,
\x_7__s_port_\ => \y[7]_INST_0_i_2_n_0\,
y(9 downto 0) => y(9 downto 0),
\y_8__s_port_\ => U0_n_10
);
\y[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFB8B8FF00B8B800"
)
port map (
I0 => \y[0]_INST_0_i_3_n_0\,
I1 => x(25),
I2 => \y[0]_INST_0_i_4_n_0\,
I3 => x(23),
I4 => x(24),
I5 => \y[2]_INST_0_i_3_n_0\,
O => \y[0]_INST_0_i_1_n_0\
);
\y[0]_INST_0_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => x(23),
I1 => x(24),
O => y4(1)
);
\y[0]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => x(8),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => x(0),
I3 => \y[7]_INST_0_i_11_n_0\,
I4 => x(16),
O => \y[0]_INST_0_i_3_n_0\
);
\y[0]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => x(12),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => x(4),
I3 => \y[7]_INST_0_i_11_n_0\,
I4 => x(20),
O => \y[0]_INST_0_i_4_n_0\
);
\y[0]_INST_0_i_5\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y[0]_INST_0_i_5_n_0\,
CO(2) => \y[0]_INST_0_i_5_n_1\,
CO(1) => \y[0]_INST_0_i_5_n_2\,
CO(0) => \y[0]_INST_0_i_5_n_3\,
CYINIT => y4(0),
DI(3 downto 0) => B"0000",
O(3) => \y[0]_INST_0_i_5_n_4\,
O(2) => \y[0]_INST_0_i_5_n_5\,
O(1) => \y[0]_INST_0_i_5_n_6\,
O(0) => \y[0]_INST_0_i_5_n_7\,
S(3) => \y[0]_INST_0_i_7_n_0\,
S(2) => \y[0]_INST_0_i_8_n_0\,
S(1) => \y[0]_INST_0_i_9_n_0\,
S(0) => y4(1)
);
\y[0]_INST_0_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => x(23),
O => y4(0)
);
\y[0]_INST_0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"1555EAAA"
)
port map (
I0 => x(26),
I1 => x(23),
I2 => x(24),
I3 => x(25),
I4 => x(27),
O => \y[0]_INST_0_i_7_n_0\
);
\y[0]_INST_0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"807F"
)
port map (
I0 => x(25),
I1 => x(24),
I2 => x(23),
I3 => x(26),
O => \y[0]_INST_0_i_8_n_0\
);
\y[0]_INST_0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => x(24),
I1 => x(23),
I2 => x(25),
O => \y[0]_INST_0_i_9_n_0\
);
\y[1]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFB8B8FF00B8B800"
)
port map (
I0 => \y[1]_INST_0_i_3_n_0\,
I1 => x(25),
I2 => \y[1]_INST_0_i_4_n_0\,
I3 => x(23),
I4 => x(24),
I5 => \y[3]_INST_0_i_3_n_0\,
O => \y[1]_INST_0_i_1_n_0\
);
\y[1]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => x(9),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => x(1),
I3 => \y[7]_INST_0_i_11_n_0\,
I4 => x(17),
O => \y[1]_INST_0_i_3_n_0\
);
\y[1]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => x(13),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => x(5),
I3 => \y[7]_INST_0_i_11_n_0\,
I4 => x(21),
O => \y[1]_INST_0_i_4_n_0\
);
\y[2]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EB28"
)
port map (
I0 => \y[2]_INST_0_i_3_n_0\,
I1 => x(23),
I2 => x(24),
I3 => \y[4]_INST_0_i_3_n_0\,
O => \y[2]_INST_0_i_1_n_0\
);
\y[2]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"EABF2A80"
)
port map (
I0 => \y[2]_INST_0_i_5_n_0\,
I1 => x(24),
I2 => x(23),
I3 => x(25),
I4 => \y[6]_INST_0_i_5_n_0\,
O => \y[2]_INST_0_i_3_n_0\
);
\y[2]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => x(10),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => x(2),
I3 => \y[7]_INST_0_i_11_n_0\,
I4 => x(18),
O => \y[2]_INST_0_i_5_n_0\
);
\y[3]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EB28"
)
port map (
I0 => \y[3]_INST_0_i_3_n_0\,
I1 => x(23),
I2 => x(24),
I3 => \y[5]_INST_0_i_3_n_0\,
O => \y[3]_INST_0_i_1_n_0\
);
\y[3]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAACF0FC00F"
)
port map (
I0 => \y[3]_INST_0_i_5_n_0\,
I1 => x(15),
I2 => \y[9]_INST_0_i_18_n_0\,
I3 => \y[7]_INST_0_i_11_n_0\,
I4 => x(7),
I5 => \y[9]_INST_0_i_17_n_0\,
O => \y[3]_INST_0_i_3_n_0\
);
\y[3]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => x(11),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => x(3),
I3 => \y[7]_INST_0_i_11_n_0\,
I4 => x(19),
O => \y[3]_INST_0_i_5_n_0\
);
\y[4]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EB28"
)
port map (
I0 => \y[4]_INST_0_i_3_n_0\,
I1 => x(23),
I2 => x(24),
I3 => \y[6]_INST_0_i_3_n_0\,
O => \y[4]_INST_0_i_1_n_0\
);
\y[4]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8BB8888B8888888"
)
port map (
I0 => \y[0]_INST_0_i_4_n_0\,
I1 => \y[9]_INST_0_i_17_n_0\,
I2 => x(16),
I3 => \y[9]_INST_0_i_18_n_0\,
I4 => \y[7]_INST_0_i_11_n_0\,
I5 => x(8),
O => \y[4]_INST_0_i_3_n_0\
);
\y[5]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7D41"
)
port map (
I0 => \y[7]_INST_0_i_8_n_0\,
I1 => x(23),
I2 => x(24),
I3 => \y[5]_INST_0_i_3_n_0\,
O => \y[5]_INST_0_i_1_n_0\
);
\y[5]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8888888B88888"
)
port map (
I0 => \y[1]_INST_0_i_4_n_0\,
I1 => \y[9]_INST_0_i_17_n_0\,
I2 => x(9),
I3 => \y[9]_INST_0_i_18_n_0\,
I4 => \y[7]_INST_0_i_11_n_0\,
I5 => x(17),
O => \y[5]_INST_0_i_3_n_0\
);
\y[6]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"82BE"
)
port map (
I0 => \y[7]_INST_0_i_6_n_0\,
I1 => x(23),
I2 => x(24),
I3 => \y[6]_INST_0_i_3_n_0\,
O => \y[6]_INST_0_i_1_n_0\
);
\y[6]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8888888B88888"
)
port map (
I0 => \y[6]_INST_0_i_5_n_0\,
I1 => \y[9]_INST_0_i_17_n_0\,
I2 => x(10),
I3 => \y[9]_INST_0_i_18_n_0\,
I4 => \y[7]_INST_0_i_11_n_0\,
I5 => x(18),
O => \y[6]_INST_0_i_3_n_0\
);
\y[6]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => x(14),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => x(6),
I3 => \y[7]_INST_0_i_11_n_0\,
I4 => x(22),
O => \y[6]_INST_0_i_5_n_0\
);
\y[7]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5CC5"
)
port map (
I0 => \y[9]_INST_0_i_7_n_0\,
I1 => \y[7]_INST_0_i_6_n_0\,
I2 => x(23),
I3 => x(24),
O => \y[7]_INST_0_i_1_n_0\
);
\y[7]_INST_0_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"1555EAAA"
)
port map (
I0 => x(26),
I1 => x(23),
I2 => x(24),
I3 => x(25),
I4 => x(27),
O => \y[7]_INST_0_i_11_n_0\
);
\y[7]_INST_0_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"E020"
)
port map (
I0 => x(12),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => \y[7]_INST_0_i_11_n_0\,
I3 => x(20),
O => \y[7]_INST_0_i_12_n_0\
);
\y[7]_INST_0_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"E020"
)
port map (
I0 => x(9),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => \y[7]_INST_0_i_11_n_0\,
I3 => x(17),
O => \y[7]_INST_0_i_13_n_0\
);
\y[7]_INST_0_i_14\: unisim.vcomponents.LUT4
generic map(
INIT => X"4C7C"
)
port map (
I0 => x(15),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => \y[7]_INST_0_i_11_n_0\,
I3 => x(7),
O => \y[7]_INST_0_i_14_n_0\
);
\y[7]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"5CC5"
)
port map (
I0 => \y[7]_INST_0_i_7_n_0\,
I1 => \y[7]_INST_0_i_8_n_0\,
I2 => x(23),
I3 => x(24),
O => \y[7]_INST_0_i_2_n_0\
);
\y[7]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F7F4F7F0000FFFF"
)
port map (
I0 => x(16),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => \y[7]_INST_0_i_11_n_0\,
I3 => x(8),
I4 => \y[7]_INST_0_i_12_n_0\,
I5 => \y[9]_INST_0_i_17_n_0\,
O => \y[7]_INST_0_i_6_n_0\
);
\y[7]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF0000B080B080"
)
port map (
I0 => x(21),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => \y[7]_INST_0_i_11_n_0\,
I3 => x(13),
I4 => \y[7]_INST_0_i_13_n_0\,
I5 => \y[9]_INST_0_i_17_n_0\,
O => \y[7]_INST_0_i_7_n_0\
);
\y[7]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF00001FDF1FDF"
)
port map (
I0 => x(11),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => \y[7]_INST_0_i_11_n_0\,
I3 => x(19),
I4 => \y[7]_INST_0_i_14_n_0\,
I5 => \y[9]_INST_0_i_17_n_0\,
O => \y[7]_INST_0_i_8_n_0\
);
\y[7]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBFFFFFFFFDDDDD"
)
port map (
I0 => x(30),
I1 => x(28),
I2 => x(26),
I3 => U0_n_10,
I4 => x(27),
I5 => x(29),
O => \y[7]_INST_0_i_9_n_0\
);
\y[9]_INST_0_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \y[9]_INST_0_i_20_n_4\,
I1 => \y[9]_INST_0_i_21_n_6\,
I2 => \y[9]_INST_0_i_20_n_6\,
I3 => \y[9]_INST_0_i_22_n_6\,
I4 => \y[9]_INST_0_i_23_n_0\,
I5 => \y[9]_INST_0_i_24_n_0\,
O => \y[9]_INST_0_i_13_n_0\
);
\y[9]_INST_0_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \y[9]_INST_0_i_27_n_7\,
I1 => \y[9]_INST_0_i_27_n_6\,
I2 => \y[9]_INST_0_i_28_n_6\,
I3 => \y[9]_INST_0_i_21_n_5\,
I4 => \y[9]_INST_0_i_29_n_0\,
O => \y[9]_INST_0_i_15_n_0\
);
\y[9]_INST_0_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"CACA0000FFF00000"
)
port map (
I0 => x(11),
I1 => x(19),
I2 => \y[9]_INST_0_i_18_n_0\,
I3 => x(15),
I4 => \y[7]_INST_0_i_11_n_0\,
I5 => \y[9]_INST_0_i_17_n_0\,
O => \y[9]_INST_0_i_16_n_0\
);
\y[9]_INST_0_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => x(24),
I1 => x(23),
I2 => x(25),
O => \y[9]_INST_0_i_17_n_0\
);
\y[9]_INST_0_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => x(26),
I1 => x(23),
I2 => x(24),
I3 => x(25),
O => \y[9]_INST_0_i_18_n_0\
);
\y[9]_INST_0_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"E020"
)
port map (
I0 => x(10),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => \y[7]_INST_0_i_11_n_0\,
I3 => x(18),
O => \y[9]_INST_0_i_19_n_0\
);
\y[9]_INST_0_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \y[9]_INST_0_i_27_n_0\,
CO(3) => \y[9]_INST_0_i_20_n_0\,
CO(2) => \y[9]_INST_0_i_20_n_1\,
CO(1) => \y[9]_INST_0_i_20_n_2\,
CO(0) => \y[9]_INST_0_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y[9]_INST_0_i_20_n_4\,
O(2) => \y[9]_INST_0_i_20_n_5\,
O(1) => \y[9]_INST_0_i_20_n_6\,
O(0) => \y[9]_INST_0_i_20_n_7\,
S(3) => \y[9]_INST_0_i_30_n_0\,
S(2) => \y[9]_INST_0_i_31_n_0\,
S(1) => \y[9]_INST_0_i_32_n_0\,
S(0) => \y[9]_INST_0_i_33_n_0\
);
\y[9]_INST_0_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \y[9]_INST_0_i_28_n_0\,
CO(3) => \y[9]_INST_0_i_21_n_0\,
CO(2) => \y[9]_INST_0_i_21_n_1\,
CO(1) => \y[9]_INST_0_i_21_n_2\,
CO(0) => \y[9]_INST_0_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y[9]_INST_0_i_21_n_4\,
O(2) => \y[9]_INST_0_i_21_n_5\,
O(1) => \y[9]_INST_0_i_21_n_6\,
O(0) => \y[9]_INST_0_i_21_n_7\,
S(3) => \y[9]_INST_0_i_34_n_0\,
S(2) => \y[9]_INST_0_i_35_n_0\,
S(1) => \y[9]_INST_0_i_36_n_0\,
S(0) => \y[9]_INST_0_i_37_n_0\
);
\y[9]_INST_0_i_22\: unisim.vcomponents.CARRY4
port map (
CI => \y[9]_INST_0_i_20_n_0\,
CO(3) => \y[9]_INST_0_i_22_n_0\,
CO(2) => \y[9]_INST_0_i_22_n_1\,
CO(1) => \y[9]_INST_0_i_22_n_2\,
CO(0) => \y[9]_INST_0_i_22_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y[9]_INST_0_i_22_n_4\,
O(2) => \y[9]_INST_0_i_22_n_5\,
O(1) => \y[9]_INST_0_i_22_n_6\,
O(0) => \y[9]_INST_0_i_22_n_7\,
S(3) => \y[9]_INST_0_i_38_n_0\,
S(2) => \y[9]_INST_0_i_39_n_0\,
S(1) => \y[9]_INST_0_i_40_n_0\,
S(0) => \y[9]_INST_0_i_41_n_0\
);
\y[9]_INST_0_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \y[9]_INST_0_i_42_n_6\,
I1 => \y[9]_INST_0_i_22_n_4\,
I2 => \y[9]_INST_0_i_42_n_7\,
I3 => \y[9]_INST_0_i_25_n_6\,
O => \y[9]_INST_0_i_23_n_0\
);
\y[9]_INST_0_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \y[9]_INST_0_i_27_n_5\,
I1 => \y[0]_INST_0_i_5_n_4\,
I2 => \y[9]_INST_0_i_28_n_4\,
I3 => \y[9]_INST_0_i_22_n_5\,
O => \y[9]_INST_0_i_24_n_0\
);
\y[9]_INST_0_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \y[9]_INST_0_i_21_n_0\,
CO(3) => \y[9]_INST_0_i_25_n_0\,
CO(2) => \y[9]_INST_0_i_25_n_1\,
CO(1) => \y[9]_INST_0_i_25_n_2\,
CO(0) => \y[9]_INST_0_i_25_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y[9]_INST_0_i_25_n_4\,
O(2) => \y[9]_INST_0_i_25_n_5\,
O(1) => \y[9]_INST_0_i_25_n_6\,
O(0) => \y[9]_INST_0_i_25_n_7\,
S(3) => \y[9]_INST_0_i_43_n_0\,
S(2) => \y[9]_INST_0_i_44_n_0\,
S(1) => \y[9]_INST_0_i_45_n_0\,
S(0) => \y[9]_INST_0_i_46_n_0\
);
\y[9]_INST_0_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \y[9]_INST_0_i_20_n_7\,
I1 => \y[9]_INST_0_i_27_n_4\,
I2 => \y[9]_INST_0_i_28_n_5\,
I3 => \y[9]_INST_0_i_22_n_7\,
O => \y[9]_INST_0_i_26_n_0\
);
\y[9]_INST_0_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \y[0]_INST_0_i_5_n_0\,
CO(3) => \y[9]_INST_0_i_27_n_0\,
CO(2) => \y[9]_INST_0_i_27_n_1\,
CO(1) => \y[9]_INST_0_i_27_n_2\,
CO(0) => \y[9]_INST_0_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y[9]_INST_0_i_27_n_4\,
O(2) => \y[9]_INST_0_i_27_n_5\,
O(1) => \y[9]_INST_0_i_27_n_6\,
O(0) => \y[9]_INST_0_i_27_n_7\,
S(3) => \y[9]_INST_0_i_47_n_0\,
S(2) => \y[9]_INST_0_i_48_n_0\,
S(1) => \y[9]_INST_0_i_49_n_0\,
S(0) => \y[9]_INST_0_i_50_n_0\
);
\y[9]_INST_0_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \y[9]_INST_0_i_22_n_0\,
CO(3) => \y[9]_INST_0_i_28_n_0\,
CO(2) => \y[9]_INST_0_i_28_n_1\,
CO(1) => \y[9]_INST_0_i_28_n_2\,
CO(0) => \y[9]_INST_0_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y[9]_INST_0_i_28_n_4\,
O(2) => \y[9]_INST_0_i_28_n_5\,
O(1) => \y[9]_INST_0_i_28_n_6\,
O(0) => \y[9]_INST_0_i_28_n_7\,
S(3) => \y[9]_INST_0_i_51_n_0\,
S(2) => \y[9]_INST_0_i_52_n_0\,
S(1) => \y[9]_INST_0_i_53_n_0\,
S(0) => \y[9]_INST_0_i_54_n_0\
);
\y[9]_INST_0_i_29\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \y[9]_INST_0_i_28_n_7\,
I1 => \y[9]_INST_0_i_20_n_5\,
I2 => \y[9]_INST_0_i_21_n_4\,
I3 => \y[9]_INST_0_i_21_n_7\,
O => \y[9]_INST_0_i_29_n_0\
);
\y[9]_INST_0_i_30\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_30_n_0\
);
\y[9]_INST_0_i_31\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_31_n_0\
);
\y[9]_INST_0_i_32\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_32_n_0\
);
\y[9]_INST_0_i_33\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_33_n_0\
);
\y[9]_INST_0_i_34\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_34_n_0\
);
\y[9]_INST_0_i_35\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_35_n_0\
);
\y[9]_INST_0_i_36\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_36_n_0\
);
\y[9]_INST_0_i_37\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_37_n_0\
);
\y[9]_INST_0_i_38\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_38_n_0\
);
\y[9]_INST_0_i_39\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_39_n_0\
);
\y[9]_INST_0_i_40\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_40_n_0\
);
\y[9]_INST_0_i_41\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_41_n_0\
);
\y[9]_INST_0_i_42\: unisim.vcomponents.CARRY4
port map (
CI => \y[9]_INST_0_i_25_n_0\,
CO(3 downto 1) => \NLW_y[9]_INST_0_i_42_CO_UNCONNECTED\(3 downto 1),
CO(0) => \y[9]_INST_0_i_42_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y[9]_INST_0_i_42_O_UNCONNECTED\(3 downto 2),
O(1) => \y[9]_INST_0_i_42_n_6\,
O(0) => \y[9]_INST_0_i_42_n_7\,
S(3 downto 2) => B"00",
S(1) => \y[9]_INST_0_i_55_n_0\,
S(0) => \y[9]_INST_0_i_56_n_0\
);
\y[9]_INST_0_i_43\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_43_n_0\
);
\y[9]_INST_0_i_44\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_44_n_0\
);
\y[9]_INST_0_i_45\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_45_n_0\
);
\y[9]_INST_0_i_46\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_46_n_0\
);
\y[9]_INST_0_i_47\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_47_n_0\
);
\y[9]_INST_0_i_48\: unisim.vcomponents.LUT6
generic map(
INIT => X"00001115FFFFEEEA"
)
port map (
I0 => x(29),
I1 => x(27),
I2 => U0_n_10,
I3 => x(26),
I4 => x(28),
I5 => x(30),
O => \y[9]_INST_0_i_48_n_0\
);
\y[9]_INST_0_i_49\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAA9995"
)
port map (
I0 => x(29),
I1 => x(27),
I2 => U0_n_10,
I3 => x(26),
I4 => x(28),
O => \y[9]_INST_0_i_49_n_0\
);
\y[9]_INST_0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"EB28"
)
port map (
I0 => \y[7]_INST_0_i_7_n_0\,
I1 => x(23),
I2 => x(24),
I3 => \y[9]_INST_0_i_16_n_0\,
O => \y[9]_INST_0_i_5_n_0\
);
\y[9]_INST_0_i_50\: unisim.vcomponents.LUT6
generic map(
INIT => X"A999999955555555"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => x(23),
I3 => x(24),
I4 => x(25),
I5 => x(27),
O => \y[9]_INST_0_i_50_n_0\
);
\y[9]_INST_0_i_51\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_51_n_0\
);
\y[9]_INST_0_i_52\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_52_n_0\
);
\y[9]_INST_0_i_53\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_53_n_0\
);
\y[9]_INST_0_i_54\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_54_n_0\
);
\y[9]_INST_0_i_55\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_55_n_0\
);
\y[9]_INST_0_i_56\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_56_n_0\
);
\y[9]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"C0C00000AFA00000"
)
port map (
I0 => x(12),
I1 => x(20),
I2 => \y[9]_INST_0_i_17_n_0\,
I3 => x(16),
I4 => \y[7]_INST_0_i_11_n_0\,
I5 => \y[9]_INST_0_i_18_n_0\,
O => \y[9]_INST_0_i_6_n_0\
);
\y[9]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF0000B080B080"
)
port map (
I0 => x(22),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => \y[7]_INST_0_i_11_n_0\,
I3 => x(14),
I4 => \y[9]_INST_0_i_19_n_0\,
I5 => \y[9]_INST_0_i_17_n_0\,
O => \y[9]_INST_0_i_7_n_0\
);
end STRUCTURE;
| mit | c5ac6de6ba9172f0064c61930078ae5e | 0.458024 | 2.190001 | false | false | false | false |
loa-org/loa-hdl | modules/io/tb/shiftout_tb.vhd | 2 | 1,456 | -------------------------------------------------------------------------------
-- Title : Testbench for design "shiftout"
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Platform : Spartan 3
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.shiftout_pkg.all;
-------------------------------------------------------------------------------
entity shiftout_tb is
end shiftout_tb;
-------------------------------------------------------------------------------
architecture tb of shiftout_tb is
-- component ports
signal register_signal : shiftout_out_type;
signal value : std_logic_vector(7 downto 0) := (others => '0');
signal clk : std_logic := '0';
begin
-- component instantiation
shiftout_1: shiftout
port map (
register_p => register_signal,
value_p => value,
clk => clk);
-- clock generation
clk <= not clk after 10 NS;
waveform : process
begin
wait for 50 NS;
value <= x"23";
wait for 1 US;
value <= x"ff";
wait for 1 US;
value <= x"1f";
wait for 20 NS;
value <= x"f1";
end process waveform;
end tb;
| bsd-3-clause | b8385aad8cf68137abb01c52f3a313c0 | 0.399725 | 5.090909 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_pll_0_0/synth/system_vga_pll_0_0.vhd | 3 | 4,311 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_pll:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_pll_0_0 IS
PORT (
clk_100 : IN STD_LOGIC;
clk_50 : OUT STD_LOGIC;
clk_25 : OUT STD_LOGIC;
clk_12_5 : OUT STD_LOGIC;
clk_6_25 : OUT STD_LOGIC
);
END system_vga_pll_0_0;
ARCHITECTURE system_vga_pll_0_0_arch OF system_vga_pll_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_pll_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_pll IS
PORT (
clk_100 : IN STD_LOGIC;
clk_50 : OUT STD_LOGIC;
clk_25 : OUT STD_LOGIC;
clk_12_5 : OUT STD_LOGIC;
clk_6_25 : OUT STD_LOGIC
);
END COMPONENT vga_pll;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_pll_0_0_arch: ARCHITECTURE IS "vga_pll,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_pll_0_0_arch : ARCHITECTURE IS "system_vga_pll_0_0,vga_pll,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_pll_0_0_arch: ARCHITECTURE IS "system_vga_pll_0_0,vga_pll,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_pll,x_ipVersion=1.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk_100: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_100 CLK";
ATTRIBUTE X_INTERFACE_INFO OF clk_50: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_50 CLK";
ATTRIBUTE X_INTERFACE_INFO OF clk_25: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_25 CLK";
ATTRIBUTE X_INTERFACE_INFO OF clk_12_5: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_12_5 CLK";
ATTRIBUTE X_INTERFACE_INFO OF clk_6_25: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_6_25 CLK";
BEGIN
U0 : vga_pll
PORT MAP (
clk_100 => clk_100,
clk_50 => clk_50,
clk_25 => clk_25,
clk_12_5 => clk_12_5,
clk_6_25 => clk_6_25
);
END system_vga_pll_0_0_arch;
| mit | aed67e8f22a44ef42482460e2783a5e6 | 0.726514 | 3.601504 | false | false | false | false |
ashikpoojari/Hardware-Security | DES CryptoCore/src/ip.vhd | 2 | 1,294 | library ieee;
use ieee.std_logic_1164.all;
entity ip is port
(
ct : in std_logic_vector(1 TO 64);
l0x : out std_logic_vector(1 TO 32);
r0x : out std_logic_vector(1 TO 32)
);
end ip;
architecture behavior of ip is
begin
l0x(1)<=ct(58); l0x(2)<=ct(50); l0x(3)<=ct(42); l0x(4)<=ct(34); l0x(5)<=ct(26); l0x(6)<=ct(18); l0x(7)<=ct(10); l0x(8)<=ct(2);
l0x(9)<=ct(60); l0x(10)<=ct(52); l0x(11)<=ct(44); l0x(12)<=ct(36); l0x(13)<=ct(28); l0x(14)<=ct(20); l0x(15)<=ct(12); l0x(16)<=ct(4);
l0x(17)<=ct(62); l0x(18)<=ct(54); l0x(19)<=ct(46); l0x(20)<=ct(38); l0x(21)<=ct(30); l0x(22)<=ct(22); l0x(23)<=ct(14); l0x(24)<=ct(6);
l0x(25)<=ct(64); l0x(26)<=ct(56); l0x(27)<=ct(48); l0x(28)<=ct(40); l0x(29)<=ct(32); l0x(30)<=ct(24); l0x(31)<=ct(16); l0x(32)<=ct(8);
r0x(1)<=ct(57); r0x(2)<=ct(49); r0x(3)<=ct(41); r0x(4)<=ct(33); r0x(5)<=ct(25); r0x(6)<=ct(17); r0x(7)<=ct(9); r0x(8)<=ct(1);
r0x(9)<=ct(59); r0x(10)<=ct(51); r0x(11)<=ct(43); r0x(12)<=ct(35); r0x(13)<=ct(27); r0x(14)<=ct(19); r0x(15)<=ct(11); r0x(16)<=ct(3);
r0x(17)<=ct(61); r0x(18)<=ct(53); r0x(19)<=ct(45); r0x(20)<=ct(37); r0x(21)<=ct(29); r0x(22)<=ct(21); r0x(23)<=ct(13); r0x(24)<=ct(5);
r0x(25)<=ct(63); r0x(26)<=ct(55); r0x(27)<=ct(47); r0x(28)<=ct(39); r0x(29)<=ct(31); r0x(30)<=ct(23); r0x(31)<=ct(15); r0x(32)<=ct(7);
end behavior; | mit | 0b2ee1e5557ba859e180244410ae2c11 | 0.553323 | 1.760544 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/hdl/system_wrapper.vhd | 1 | 2,354 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Sat May 27 20:54:34 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system_wrapper.bd
--Design : system_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_wrapper is
port (
clk_100 : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
hdmi_clk : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hsync : in STD_LOGIC;
pclk : in STD_LOGIC;
ready : out STD_LOGIC;
reset : in STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
vsync : in STD_LOGIC;
xclk : out STD_LOGIC
);
end system_wrapper;
architecture STRUCTURE of system_wrapper is
component system is
port (
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC;
clk_100 : in STD_LOGIC;
ready : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
xclk : out STD_LOGIC;
reset : in STD_LOGIC;
pclk : in STD_LOGIC
);
end component system;
begin
system_i: component system
port map (
clk_100 => clk_100,
data(7 downto 0) => data(7 downto 0),
hdmi_clk => hdmi_clk,
hdmi_d(15 downto 0) => hdmi_d(15 downto 0),
hdmi_de => hdmi_de,
hdmi_hsync => hdmi_hsync,
hdmi_scl => hdmi_scl,
hdmi_sda => hdmi_sda,
hdmi_vsync => hdmi_vsync,
hsync => hsync,
pclk => pclk,
ready => ready,
reset => reset,
sioc => sioc,
siod => siod,
vsync => vsync,
xclk => xclk
);
end STRUCTURE;
| mit | 267892d31bc93151b834aa42b2a7d71d | 0.564571 | 3.566667 | false | false | false | false |
loa-org/loa-hdl | modules/imotor/tb/imotor_module_tb.vhd | 2 | 4,406 | -------------------------------------------------------------------------------
-- Title : Testbench for design "imotor_module"
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.bus_pkg.all;
use work.reg_file_pkg.all;
use work.imotor_module_pkg.all;
-------------------------------------------------------------------------------
entity imotor_module_tb is
end entity imotor_module_tb;
-------------------------------------------------------------------------------
architecture behavourial of imotor_module_tb is
-- component generics
constant BASE_ADDRESS : positive := 16#0100#;
constant MOTORS : positive := 2;
-- Component ports
signal tx_out : std_logic_vector(MOTORS-1 downto 0);
signal rx_in : std_logic_vector(MOTORS-1 downto 0) := (others => '1');
signal rx_in_can : std_logic_vector(MOTORS-1 downto 0); -- simulated signal on the CAN link
signal tx_busy_s : std_logic;
signal tx_data_s : std_logic_vector(7 downto 0) := (others => '0');
signal tx_empty_s : std_logic := '1';
signal tx_re_s : std_logic;
signal clk_tx_s : std_logic := '0';
signal bus_o : busdevice_out_type;
signal bus_i : busdevice_in_type :=
(addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
-- clock
signal clk : std_logic := '1';
begin -- architecture behavourial
-- component instantiation
-- MUT
imotor_module_1 : entity work.imotor_module
generic map (
BASE_ADDRESS => BASE_ADDRESS,
DATA_WORDS_READ => 3,
DATA_WORDS_SEND => 2,
MOTORS => MOTORS)
port map (
tx_out_p => tx_out,
rx_in_p => rx_in_can,
bus_o => bus_o,
bus_i => bus_i,
clk => clk);
-- Simulates the answer of an iMotor
uart_tx_1 : entity work.uart_tx
port map (
txd_p => rx_in(0),
busy_p => tx_busy_s,
data_p => tx_data_s,
empty_p => tx_empty_s,
re_p => tx_re_s,
clk_tx_en => clk_tx_s,
clk => clk);
-- clock generation 50 MHz
clk <= not clk after 10 ns;
-- Generate a Tx bit clock
bitclock : process
begin
wait until rising_edge(clk);
clk_tx_s <= '1';
wait until rising_edge(clk);
clk_tx_s <= '0';
wait for 970 ns;
end process bitclock;
-- CAN simulation
can_sim : for ii in 0 to MOTORS-1 generate
rx_in_can(ii) <= '0' when rx_in(ii) = '0' or tx_out(ii) = '0' else '1';
end generate can_sim;
-- waveform generation
WaveGen_Proc : process
begin
wait until clk = '1';
-- Fill registers at simulation start
-- iMotor #0, PWM
writeWord(addr => 16#0100#, data => 16#2211#, bus_i => bus_i, clk => clk);
-- iMotor #0, CUR
writeWord(addr => 16#0101#, data => 16#4433#, bus_i => bus_i, clk => clk);
-- iMotor #1, PWM
writeWord(addr => 16#0102#, data => 16#6655#, bus_i => bus_i, clk => clk);
-- iMotor #1, CUR
writeWord(addr => 16#0103#, data => 16#8877#, bus_i => bus_i, clk => clk);
wait for 300 us;
tx_data_s <= x"51";
tx_empty_s <= '0';
wait until falling_edge(tx_re_s);
tx_empty_s <= '1';
tx_data_s <= x"aa";
tx_empty_s <= '0';
wait until falling_edge(tx_re_s);
tx_empty_s <= '1';
tx_data_s <= x"bb";
tx_empty_s <= '0';
wait until falling_edge(tx_re_s);
tx_empty_s <= '1';
tx_data_s <= x"cc";
tx_empty_s <= '0';
wait until falling_edge(tx_re_s);
tx_empty_s <= '1';
tx_data_s <= x"dd";
tx_empty_s <= '0';
wait until falling_edge(tx_re_s);
tx_empty_s <= '1';
tx_data_s <= x"a1";
tx_empty_s <= '0';
wait until falling_edge(tx_re_s);
tx_empty_s <= '1';
wait;
end process WaveGen_Proc;
end architecture behavourial;
| bsd-3-clause | 1ea3afa32f0ff91e4b8688c40d42b1f9 | 0.465048 | 3.54465 | false | false | false | false |
ashikpoojari/Hardware-Security | DES CryptoCore/src/pc1.vhd | 2 | 1,217 | library ieee;
use ieee.std_logic_1164.all;
entity pc1 is port
(
key : in std_logic_vector(1 TO 64);
c0x,d0x : out std_logic_vector(1 TO 28)
);
end pc1;
architecture behavior of pc1 is
signal XX : std_logic_vector(1 to 56);
begin
XX(1)<=key(57); XX(2)<=key(49); XX(3)<=key(41); XX(4)<=key(33); XX(5)<=key(25); XX(6)<=key(17);
XX(7)<=key(9); XX(8)<=key(1); XX(9)<=key(58); XX(10)<=key(50); XX(11)<=key(42); XX(12)<=key(34);
XX(13)<=key(26); XX(14)<=key(18); XX(15)<=key(10); XX(16)<=key(2); XX(17)<=key(59); XX(18)<=key(51);
XX(19)<=key(43); XX(20)<=key(35); XX(21)<=key(27); XX(22)<=key(19); XX(23)<=key(11); XX(24)<=key(3);
XX(25)<=key(60); XX(26)<=key(52); XX(27)<=key(44); XX(28)<=key(36); XX(29)<=key(63); XX(30)<=key(55);
XX(31)<=key(47); XX(32)<=key(39); XX(33)<=key(31); XX(34)<=key(23); XX(35)<=key(15); XX(36)<=key(7);
XX(37)<=key(62); XX(38)<=key(54); XX(39)<=key(46); XX(40)<=key(38); XX(41)<=key(30); XX(42)<=key(22);
XX(43)<=key(14); XX(44)<=key(6); XX(45)<=key(61); XX(46)<=key(53); XX(47)<=key(45); XX(48)<=key(37);
XX(49)<=key(29); XX(50)<=key(21); XX(51)<=key(13); XX(52)<=key(5);XX(53)<=key(28); XX(54)<=key(20);
XX(55)<=key(12); XX(56)<=key(4);
c0x<=XX(1 to 28); d0x<=XX(29 to 56);
end behavior;
| mit | c4f563b37307e14a17a248dda7fabf36 | 0.562038 | 2.120209 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/vga_color_test/vga_color_test.srcs/sources_1/new/vga_color_test.vhd | 8 | 3,633 | ----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: vga_color_test - Structural
-- Description: Generate a color test pattern
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_color_test is
generic(
H_SIZE : integer := 640;
V_SIZE : integer := 480
);
port(
clk_25 : in std_logic;
xaddr : in std_logic_vector(9 downto 0);
yaddr : in std_logic_vector(9 downto 0);
rgb : out std_logic_vector(23 downto 0)
);
end vga_color_test;
architecture Structural of vga_color_test is
constant WHITE : std_logic_vector(23 downto 0) := x"FFFFFF";
constant BLACK : std_logic_vector(23 downto 0) := x"000000";
constant YELLOW : std_logic_vector(23 downto 0) := x"FFFF00";
constant CYAN : std_logic_vector(23 downto 0) := x"00FFFF";
constant GREEN : std_logic_vector(23 downto 0) := x"00FF00";
constant PINK : std_logic_vector(23 downto 0) := x"FF00FF";
constant RED : std_logic_vector(23 downto 0) := x"FF0000";
constant BLUE : std_logic_vector(23 downto 0) := x"0000FF";
constant DARK_BLUE : std_logic_vector(23 downto 0) := x"0000A0";
constant GRAY : std_logic_vector(23 downto 0) := x"808080";
constant LIGHT_GRAY : std_logic_vector(23 downto 0) := x"C0C0C0";
constant PURPLE : std_logic_vector(23 downto 0) := x"8000FF";
begin
process(clk_25)
variable x,y : integer;
begin
if rising_edge(clk_25) then
x := to_integer(unsigned(xaddr));
y := to_integer(unsigned(yaddr));
if y < (V_SIZE*2)/3 then
if x < (H_SIZE)/7 then
rgb <= WHITE;
elsif x < (H_SIZE*2)/7 then
rgb <= YELLOW;
elsif x < (H_SIZE*3)/7 then
rgb <= CYAN;
elsif x < (H_SIZE*4)/7 then
rgb <= GREEN;
elsif x < (H_SIZE*5)/7 then
rgb <= PINK;
elsif x < (H_SIZE*6)/7 then
rgb <= RED;
else
rgb <= BLUE;
end if;
elsif y < (V_SIZE*3)/4 then
if x < (H_SIZE)/7 then
rgb <= BLUE;
elsif x < (H_SIZE*2)/7 then
rgb <= BLACK;
elsif x < (H_SIZE*3)/7 then
rgb <= PINK;
elsif x < (H_SIZE*4)/7 then
rgb <= GRAY;
elsif x < (H_SIZE*5)/7 then
rgb <= CYAN;
elsif x < (H_SIZE*6)/7 then
rgb <= GRAY;
else
rgb <= WHITE;
end if;
else
if x < (H_SIZE)/6 then
rgb <= DARK_BLUE;
elsif x < (H_SIZE*2)/6 then
rgb <= WHITE;
elsif x < (H_SIZE*3)/6 then
rgb <= PURPLE;
elsif x < (H_SIZE*5)/7 then
rgb <= GRAY;
elsif x < (H_SIZE*6)/7 - (H_SIZE*2)/21 then
rgb <= BLACK;
elsif x < (H_SIZE*6)/7 - (H_SIZE)/21 then
rgb <= GRAY;
elsif x < (H_SIZE*6)/7 then
rgb <= LIGHT_GRAY;
else
rgb <= GRAY;
end if;
end if;
end if;
end process;
end Structural;
| mit | 5c5c91d12b2ef14527a5a4b285a1ca46 | 0.439306 | 3.944625 | false | false | false | false |
loa-org/loa-hdl | modules/signalprocessing/tb/goertzel_pipelined_tb.vhd | 2 | 5,567 | -------------------------------------------------------------------------------
-- Title : Testbench for design "goertzel_pipelined"
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.signalprocessing_pkg.all;
-------------------------------------------------------------------------------
entity goertzel_pipelined_tb is
end goertzel_pipelined_tb;
-------------------------------------------------------------------------------
architecture tb of goertzel_pipelined_tb is
-- component generics
constant SAMPLES : natural := 250;
constant CHANNELS : natural := 12;
constant FREQUENCIES : natural := 2;
constant Q : natural := 13;
-- clock
signal clk : std_logic := '1';
-- calculate Goertzel Coefficient
-- TODO Calculate with math_real
--
-- Find two different frequencies in signal
--
-- +-< frequency
-- |
constant COEF0 : signed := to_signed(2732, CALC_WIDTH);
constant COEF1 : signed := to_signed(2532, CALC_WIDTH);
constant COEFS : goertzel_coefs_type(FREQUENCIES-1 downto 0) := (COEF1, COEF0);
-- component ports
signal inputs_s : goertzel_inputs_type(CHANNELS-1 downto 0) := (others => (others => '0'));
signal start_s : std_logic := '0';
signal results_s : goertzel_results_type(CHANNELS-1 downto 0, FREQUENCIES-1 downto 0) := (others => (others => (others => (others => '0'))));
signal done_s : std_logic := '0';
-- signal generation for testbench
signal PHASE0 : real := 0.0;
signal PHASE1 : real := 0.0;
signal PHASE2 : real := 0.0;
constant SCALE : real := 2.0**7 - 10.0;
constant OFFSET : real := 2.0**13;
constant FSAMPLE : real := 75000.0; -- Sample Frequency in Hertz
constant FSIGNAL0 : real := 16750.0; -- Signal Frequency in Hertz
constant FSIGNAL1 : real := 16700.0; -- Signal Frequency in Hertz
constant FSIGNAL2 : real := 16600.0; -- Signal Frequency in Hertz
signal PHASE_INCREMENT0 : real := 2.0 * 3.1415 * FSIGNAL0 / FSAMPLE;
signal PHASE_INCREMENT1 : real := 2.0 * 3.1415 * FSIGNAL1 / FSAMPLE;
signal PHASE_INCREMENT2 : real := 2.0 * 3.1415 * FSIGNAL2 / FSAMPLE;
-- debugging signal for goertzel
type goertzel_values_type is array (CHANNELS-1 downto 0, FREQUENCIES-1 downto 0) of real;
signal goertzel_values_s : goertzel_values_type := (others => (others => 0.0));
begin -- tb
goertzel_pipelined_1 : goertzel_pipelined
generic map (
Q => 13,
SAMPLES => SAMPLES,
CHANNELS => CHANNELS,
FREQUENCIES => FREQUENCIES)
port map (
coefs_p => COEFS,
inputs_p => inputs_s,
start_p => start_s,
results_p => results_s,
done_p => done_s,
clk => clk);
-- clock generation
clk <= not clk after 20 ns;
-- every 5 clock cycles a start_p signal from ADC
start_gen_proc : process
begin -- process start_gen_proc
start_s <= '0';
wait until clk = '1';
start_s <= '1';
wait until clk = '1';
start_s <= '0';
wait until clk = '1';
wait until clk = '1';
wait until clk = '1';
wait until clk = '1';
wait until clk = '1';
wait until clk = '1';
wait until clk = '1';
end process start_gen_proc;
-- Test signal waveform generation
WaveGen_Proc : process
begin
for n in 0 to 10000 loop
wait until start_s = '1';
-- signed values from three ADC channels
inputs_s(0) <= to_signed(integer(SCALE * sin(PHASE0)), INPUT_WIDTH);
inputs_s(1) <= to_signed(integer(SCALE * sin(PHASE1)), INPUT_WIDTH);
inputs_s(2) <= to_signed(integer(SCALE * sin(PHASE2)), INPUT_WIDTH);
PHASE0 <= PHASE0 + PHASE_INCREMENT0;
PHASE1 <= PHASE1 + PHASE_INCREMENT1;
PHASE2 <= PHASE2 + PHASE_INCREMENT2;
end loop;
-- end, do not repeat pattern
wait for 10 ms;
end process WaveGen_Proc;
-- Calculate Goertzel Value in this test bench. This will not be implemented
-- in VHDL. It is done in the processor in floating point.
GoertzelCheck_proc : process
variable d1 : real := 0.0;
variable d2 : real := 0.0;
variable c : real := 0.0;
begin -- process GoertzelCheck_proc
wait until done_s = '1';
-- new values are available in the result registers
-- convert results from Q-format to real
for ch in 0 to CHANNELS-1 loop
for fr in 0 to FREQUENCIES-1 loop
d1 := real(to_integer(results_s(ch, fr)(0))) / 2.0**(Q-2);
d2 := real(to_integer(results_s(ch, fr)(1))) / 2.0**(Q-2);
c := real(to_integer(coefs(fr))) / 2.0**Q;
-- calculate goertzel value
goertzel_values_s(ch, fr) <= d1**2 + d2**2 - (d2 * d1 * c);
end loop; -- fr
end loop; -- ch
end process GoertzelCheck_proc;
end tb;
| bsd-3-clause | ea6256c44607952528f5a94ff7631352 | 0.514999 | 3.928723 | false | false | false | false |
loa-org/loa-hdl | modules/signalprocessing/tb/goertzel_muxes_tb.vhd | 2 | 4,598 | -------------------------------------------------------------------------------
-- Title : Testbench for design "goertzel_muxes"
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.signalprocessing_pkg.all;
-------------------------------------------------------------------------------
entity goertzel_muxes_tb is
end entity goertzel_muxes_tb;
-------------------------------------------------------------------------------
architecture tb of goertzel_muxes_tb is
-- component generics
constant CHANNELS : positive := 12;
constant FREQUENCIES : positive := 5;
-- component ports
signal mux_delay1_p : std_logic := '0';
signal mux_delay2_p : std_logic := '0';
signal mux_coef : natural range FREQUENCIES-1 downto 0 := 0;
signal mux_input : natural range CHANNELS-1 downto 0 := 0;
signal bram_data : goertzel_result_type := (others => (others => '0'));
signal coefs_p : goertzel_coefs_type(FREQUENCIES-1 downto 0) := (others => (others => '0'));
signal inputs_p : goertzel_inputs_type(CHANNELS-1 downto 0) := (others => (others => '0'));
signal delay1_p : goertzel_data_type := (others => '0');
signal delay2_p : goertzel_data_type := (others => '0');
signal coef_p : goertzel_coef_type := (others => '0');
signal input_p : goertzel_input_type := (others => '0');
-- clock
signal Clk : std_logic := '1';
begin -- architecture tb
-- component instantiation
DUT : entity work.goertzel_muxes
generic map (
CHANNELS => CHANNELS,
FREQUENCIES => FREQUENCIES)
port map (
mux_delay1_p => mux_delay1_p,
mux_delay2_p => mux_delay2_p,
mux_coef => mux_coef,
mux_input => mux_input,
bram_data => bram_data,
coefs_p => coefs_p,
inputs_p => inputs_p,
delay1_p => delay1_p,
delay2_p => delay2_p,
coef_p => coef_p,
input_p => input_p);
-- clock generation
clk <= not clk after 10 ns;
bram_data(0) <= "110011001100110011";
bram_data(1) <= "101010101010101010";
stim : process
variable seed1, seed2 : positive;
variable Rand : real;
variable IRand : integer;
begin
for ii in 0 to CHANNELS-1 loop
-- Zufallszahl ziwschen 0 und 1
uniform(seed1, seed2, rand);
-- daraus ein Integer zwischen 0 und 2^14-1
irand := integer((rand* (2.0**14-1.0)));
inputs_p(ii) <= to_signed(irand, 14);
end loop; -- ii
for ii in 0 to FREQUENCIES-1 loop
-- Zufallszahl ziwschen 0 und 1
uniform(seed1, seed2, rand);
-- daraus ein Integer zwischen 0 und 2^14-1
irand := integer((rand* (2.0**14-1.0)));
coefs_p(ii) <= to_signed(irand, 18);
end loop; -- ii
-- do not repeat
wait for 10 ms;
end process;
-- waveform generation
WaveGen_Proc : process
begin
wait until clk = '0';
wait until clk = '0';
mux_delay1_p <= '1';
wait until clk = '0';
mux_delay1_p <= '0';
wait until clk = '0';
mux_delay2_p <= '1';
wait until clk = '0';
mux_delay2_p <= '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
-- all channels
for ii in 0 to CHANNELS-1 loop
mux_input <= ii;
wait until clk = '0';
end loop; -- ii
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
-- all coefs
for ii in 0 to FREQUENCIES-1 loop
mux_coef <= ii;
wait until clk = '0';
end loop; -- ii
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
-- do not repeat
wait for 10 ms;
end process WaveGen_Proc;
end architecture tb;
| bsd-3-clause | 978096edbc4a2b3fef301c7d5115fe66 | 0.457808 | 3.936644 | false | false | false | false |
pgavin/carpe | hdl/tech/inferred/div-rtl.vhdl | 1 | 1,540 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
architecture rtl of div is
begin
div : entity work.div_inferred(rtl)
generic map (
src1_bits => src1_bits,
src2_bits => src2_bits
)
port map (
unsgnd => unsgnd,
src1 => src1,
src2 => src2,
dbz => dbz,
overflow => overflow,
result => result
);
end;
| apache-2.0 | f8216bef65c0981221ab899d6c86c5d3 | 0.476623 | 5.202703 | false | false | false | false |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/niosii_system_burst_adapter_002.vhd | 1 | 8,673 | -- niosii_system_burst_adapter_002.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:31
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_burst_adapter_002 is
generic (
PKT_ADDR_H : integer := 33;
PKT_ADDR_L : integer := 9;
PKT_BEGIN_BURST : integer := 53;
PKT_BYTE_CNT_H : integer := 42;
PKT_BYTE_CNT_L : integer := 40;
PKT_BYTEEN_H : integer := 8;
PKT_BYTEEN_L : integer := 8;
PKT_BURST_SIZE_H : integer := 48;
PKT_BURST_SIZE_L : integer := 46;
PKT_BURST_TYPE_H : integer := 50;
PKT_BURST_TYPE_L : integer := 49;
PKT_BURSTWRAP_H : integer := 45;
PKT_BURSTWRAP_L : integer := 43;
PKT_TRANS_COMPRESSED_READ : integer := 34;
PKT_TRANS_WRITE : integer := 36;
PKT_TRANS_READ : integer := 37;
OUT_NARROW_SIZE : integer := 0;
IN_NARROW_SIZE : integer := 0;
OUT_FIXED : integer := 0;
OUT_COMPLETE_WRAP : integer := 0;
ST_DATA_W : integer := 73;
ST_CHANNEL_W : integer := 13;
OUT_BYTE_CNT_H : integer := 40;
OUT_BURSTWRAP_H : integer := 45;
COMPRESSED_READ_SUPPORT : integer := 0;
BYTEENABLE_SYNTHESIS : integer := 1;
PIPE_INPUTS : integer := 0;
NO_WRAP_SUPPORT : integer := 0;
BURSTWRAP_CONST_MASK : integer := 3;
BURSTWRAP_CONST_VALUE : integer := 3
);
port (
clk : in std_logic := '0'; -- cr0.clk
reset : in std_logic := '0'; -- cr0_reset.reset
sink0_valid : in std_logic := '0'; -- sink0.valid
sink0_data : in std_logic_vector(72 downto 0) := (others => '0'); -- .data
sink0_channel : in std_logic_vector(12 downto 0) := (others => '0'); -- .channel
sink0_startofpacket : in std_logic := '0'; -- .startofpacket
sink0_endofpacket : in std_logic := '0'; -- .endofpacket
sink0_ready : out std_logic; -- .ready
source0_valid : out std_logic; -- source0.valid
source0_data : out std_logic_vector(72 downto 0); -- .data
source0_channel : out std_logic_vector(12 downto 0); -- .channel
source0_startofpacket : out std_logic; -- .startofpacket
source0_endofpacket : out std_logic; -- .endofpacket
source0_ready : in std_logic := '0' -- .ready
);
end entity niosii_system_burst_adapter_002;
architecture rtl of niosii_system_burst_adapter_002 is
component altera_merlin_burst_adapter is
generic (
PKT_ADDR_H : integer := 79;
PKT_ADDR_L : integer := 48;
PKT_BEGIN_BURST : integer := 81;
PKT_BYTE_CNT_H : integer := 5;
PKT_BYTE_CNT_L : integer := 0;
PKT_BYTEEN_H : integer := 83;
PKT_BYTEEN_L : integer := 80;
PKT_BURST_SIZE_H : integer := 86;
PKT_BURST_SIZE_L : integer := 84;
PKT_BURST_TYPE_H : integer := 88;
PKT_BURST_TYPE_L : integer := 87;
PKT_BURSTWRAP_H : integer := 11;
PKT_BURSTWRAP_L : integer := 6;
PKT_TRANS_COMPRESSED_READ : integer := 14;
PKT_TRANS_WRITE : integer := 13;
PKT_TRANS_READ : integer := 12;
OUT_NARROW_SIZE : integer := 0;
IN_NARROW_SIZE : integer := 0;
OUT_FIXED : integer := 0;
OUT_COMPLETE_WRAP : integer := 0;
ST_DATA_W : integer := 89;
ST_CHANNEL_W : integer := 8;
OUT_BYTE_CNT_H : integer := 5;
OUT_BURSTWRAP_H : integer := 11;
COMPRESSED_READ_SUPPORT : integer := 1;
BYTEENABLE_SYNTHESIS : integer := 0;
PIPE_INPUTS : integer := 0;
NO_WRAP_SUPPORT : integer := 0;
BURSTWRAP_CONST_MASK : integer := 0;
BURSTWRAP_CONST_VALUE : integer := -1
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink0_valid : in std_logic := 'X'; -- valid
sink0_data : in std_logic_vector(72 downto 0) := (others => 'X'); -- data
sink0_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink0_ready : out std_logic; -- ready
source0_valid : out std_logic; -- valid
source0_data : out std_logic_vector(72 downto 0); -- data
source0_channel : out std_logic_vector(12 downto 0); -- channel
source0_startofpacket : out std_logic; -- startofpacket
source0_endofpacket : out std_logic; -- endofpacket
source0_ready : in std_logic := 'X' -- ready
);
end component altera_merlin_burst_adapter;
begin
pkt_trans_compressed_read_check : if PKT_TRANS_COMPRESSED_READ /= 34 generate
assert false report "Supplied generics do not match expected generics" severity Failure;
end generate;
burst_adapter_002 : component altera_merlin_burst_adapter
generic map (
PKT_ADDR_H => PKT_ADDR_H,
PKT_ADDR_L => PKT_ADDR_L,
PKT_BEGIN_BURST => PKT_BEGIN_BURST,
PKT_BYTE_CNT_H => PKT_BYTE_CNT_H,
PKT_BYTE_CNT_L => PKT_BYTE_CNT_L,
PKT_BYTEEN_H => PKT_BYTEEN_H,
PKT_BYTEEN_L => PKT_BYTEEN_L,
PKT_BURST_SIZE_H => PKT_BURST_SIZE_H,
PKT_BURST_SIZE_L => PKT_BURST_SIZE_L,
PKT_BURST_TYPE_H => PKT_BURST_TYPE_H,
PKT_BURST_TYPE_L => PKT_BURST_TYPE_L,
PKT_BURSTWRAP_H => PKT_BURSTWRAP_H,
PKT_BURSTWRAP_L => PKT_BURSTWRAP_L,
PKT_TRANS_COMPRESSED_READ => 34,
PKT_TRANS_WRITE => PKT_TRANS_WRITE,
PKT_TRANS_READ => PKT_TRANS_READ,
OUT_NARROW_SIZE => OUT_NARROW_SIZE,
IN_NARROW_SIZE => IN_NARROW_SIZE,
OUT_FIXED => OUT_FIXED,
OUT_COMPLETE_WRAP => OUT_COMPLETE_WRAP,
ST_DATA_W => ST_DATA_W,
ST_CHANNEL_W => ST_CHANNEL_W,
OUT_BYTE_CNT_H => OUT_BYTE_CNT_H,
OUT_BURSTWRAP_H => OUT_BURSTWRAP_H,
COMPRESSED_READ_SUPPORT => COMPRESSED_READ_SUPPORT,
BYTEENABLE_SYNTHESIS => BYTEENABLE_SYNTHESIS,
PIPE_INPUTS => PIPE_INPUTS,
NO_WRAP_SUPPORT => NO_WRAP_SUPPORT,
BURSTWRAP_CONST_MASK => BURSTWRAP_CONST_MASK,
BURSTWRAP_CONST_VALUE => BURSTWRAP_CONST_VALUE
)
port map (
clk => clk, -- cr0.clk
reset => reset, -- cr0_reset.reset
sink0_valid => sink0_valid, -- sink0.valid
sink0_data => sink0_data, -- .data
sink0_channel => sink0_channel, -- .channel
sink0_startofpacket => sink0_startofpacket, -- .startofpacket
sink0_endofpacket => sink0_endofpacket, -- .endofpacket
sink0_ready => sink0_ready, -- .ready
source0_valid => source0_valid, -- source0.valid
source0_data => source0_data, -- .data
source0_channel => source0_channel, -- .channel
source0_startofpacket => source0_startofpacket, -- .startofpacket
source0_endofpacket => source0_endofpacket, -- .endofpacket
source0_ready => source0_ready -- .ready
);
end architecture rtl; -- of niosii_system_burst_adapter_002
| apache-2.0 | 5337e6589ef9e03f452b5167dbc57dc0 | 0.473884 | 3.648717 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0_1/system_ov7670_controller_0_0_sim_netlist.vhdl | 1 | 70,948 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 07:03:52 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0_1/system_ov7670_controller_0_0_sim_netlist.vhdl
-- Design : system_ov7670_controller_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_i2c_sender is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
sioc : out STD_LOGIC;
p_0_in : out STD_LOGIC;
\busy_sr_reg[1]_0\ : out STD_LOGIC;
siod : out STD_LOGIC;
\busy_sr_reg[31]_0\ : in STD_LOGIC;
clk : in STD_LOGIC;
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
DOADO : in STD_LOGIC_VECTOR ( 15 downto 0 );
\busy_sr_reg[31]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_controller_0_0_i2c_sender : entity is "i2c_sender";
end system_ov7670_controller_0_0_i2c_sender;
architecture STRUCTURE of system_ov7670_controller_0_0_i2c_sender is
signal busy_sr0 : STD_LOGIC;
signal \busy_sr[0]_i_3_n_0\ : STD_LOGIC;
signal \busy_sr[0]_i_5_n_0\ : STD_LOGIC;
signal \busy_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[11]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[1]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[20]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[21]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[23]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[24]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[25]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[26]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[28]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[29]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[2]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \busy_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \^busy_sr_reg[1]_0\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[0]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \data_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \data_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \data_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[20]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[31]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \divider_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 6 );
signal \divider_reg__1\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^p_0_in\ : STD_LOGIC;
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_1_in_0 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sioc_i_1_n_0 : STD_LOGIC;
signal sioc_i_2_n_0 : STD_LOGIC;
signal sioc_i_3_n_0 : STD_LOGIC;
signal sioc_i_4_n_0 : STD_LOGIC;
signal sioc_i_5_n_0 : STD_LOGIC;
signal siod_INST_0_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \busy_sr[0]_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \busy_sr[0]_i_5\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \busy_sr[10]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[11]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[12]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[13]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[14]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[15]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[16]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[17]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[18]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[19]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \busy_sr[20]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[21]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[22]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[23]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[24]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[25]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[26]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \busy_sr[27]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[28]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[29]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[2]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[30]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \busy_sr[31]_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \busy_sr[3]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[4]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[5]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[6]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[7]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[8]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[9]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \data_sr[10]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[12]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[13]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[14]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_sr[15]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[16]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[17]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[18]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[19]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[31]_i_2\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \data_sr[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[4]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[5]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[6]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[7]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[8]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[9]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \divider[0]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[1]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \divider[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[6]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \divider[7]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of sioc_i_3 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of sioc_i_4 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of sioc_i_5 : label is "soft_lutpair3";
begin
\busy_sr_reg[1]_0\ <= \^busy_sr_reg[1]_0\;
p_0_in <= \^p_0_in\;
\busy_sr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
I2 => \divider_reg__0\(7),
I3 => \^p_0_in\,
I4 => \^busy_sr_reg[1]_0\,
I5 => p_1_in(0),
O => busy_sr0
);
\busy_sr[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \busy_sr[0]_i_3_n_0\
);
\busy_sr[0]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(3),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \busy_sr[0]_i_5_n_0\,
O => \^busy_sr_reg[1]_0\
);
\busy_sr[0]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \divider_reg__1\(5),
I1 => \divider_reg__1\(4),
I2 => \divider_reg__0\(7),
I3 => \divider_reg__0\(6),
O => \busy_sr[0]_i_5_n_0\
);
\busy_sr[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
O => \busy_sr[10]_i_1_n_0\
);
\busy_sr[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[10]\,
I1 => \^p_0_in\,
O => \busy_sr[11]_i_1_n_0\
);
\busy_sr[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
O => \busy_sr[12]_i_1_n_0\
);
\busy_sr[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
O => \busy_sr[13]_i_1_n_0\
);
\busy_sr[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
O => \busy_sr[14]_i_1_n_0\
);
\busy_sr[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
O => \busy_sr[15]_i_1_n_0\
);
\busy_sr[16]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
O => \busy_sr[16]_i_1_n_0\
);
\busy_sr[17]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
O => \busy_sr[17]_i_1_n_0\
);
\busy_sr[18]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
O => \busy_sr[18]_i_1_n_0\
);
\busy_sr[19]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
O => \busy_sr[19]_i_1_n_0\
);
\busy_sr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \^p_0_in\,
O => \busy_sr[1]_i_1_n_0\
);
\busy_sr[20]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(0),
I1 => \^p_0_in\,
O => \busy_sr[20]_i_1_n_0\
);
\busy_sr[21]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(1),
I1 => \^p_0_in\,
O => \busy_sr[21]_i_1_n_0\
);
\busy_sr[22]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[21]\,
I1 => \^p_0_in\,
O => \busy_sr[22]_i_1_n_0\
);
\busy_sr[23]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[22]\,
I1 => \^p_0_in\,
O => \busy_sr[23]_i_1_n_0\
);
\busy_sr[24]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[23]\,
I1 => \^p_0_in\,
O => \busy_sr[24]_i_1_n_0\
);
\busy_sr[25]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[24]\,
I1 => \^p_0_in\,
O => \busy_sr[25]_i_1_n_0\
);
\busy_sr[26]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[25]\,
I1 => \^p_0_in\,
O => \busy_sr[26]_i_1_n_0\
);
\busy_sr[27]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[26]\,
I1 => \^p_0_in\,
O => \busy_sr[27]_i_1_n_0\
);
\busy_sr[28]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[27]\,
I1 => \^p_0_in\,
O => \busy_sr[28]_i_1_n_0\
);
\busy_sr[29]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \^p_0_in\,
O => \busy_sr[29]_i_1_n_0\
);
\busy_sr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[1]\,
I1 => \^p_0_in\,
O => \busy_sr[2]_i_1_n_0\
);
\busy_sr[30]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \^p_0_in\,
O => \busy_sr[30]_i_1_n_0\
);
\busy_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"22222222A2222222"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
I3 => \divider_reg__0\(7),
I4 => \divider_reg__0\(6),
I5 => \busy_sr[0]_i_3_n_0\,
O => \busy_sr[31]_i_1_n_0\
);
\busy_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^p_0_in\,
I1 => \busy_sr_reg_n_0_[30]\,
O => \busy_sr[31]_i_2_n_0\
);
\busy_sr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
O => \busy_sr[3]_i_1_n_0\
);
\busy_sr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
O => \busy_sr[4]_i_1_n_0\
);
\busy_sr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
O => \busy_sr[5]_i_1_n_0\
);
\busy_sr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
O => \busy_sr[6]_i_1_n_0\
);
\busy_sr[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
O => \busy_sr[7]_i_1_n_0\
);
\busy_sr[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
O => \busy_sr[8]_i_1_n_0\
);
\busy_sr[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
O => \busy_sr[9]_i_1_n_0\
);
\busy_sr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => p_1_in(0),
Q => \busy_sr_reg_n_0_[0]\,
R => '0'
);
\busy_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[10]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[10]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[11]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[11]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[11]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[12]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[12]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[12]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[13]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[13]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[13]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[14]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[14]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[14]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[15]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[15]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[15]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[16]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[16]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[16]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[17]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[17]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[17]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[18]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[18]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[18]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[19]_i_1_n_0\,
Q => p_1_in_0(0),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[1]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[1]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[20]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[20]_i_1_n_0\,
Q => p_1_in_0(1),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[21]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[21]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[21]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[22]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[22]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[22]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[23]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[23]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[23]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[24]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[24]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[24]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[25]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[25]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[25]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[26]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[26]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[26]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[27]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[27]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[27]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[28]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[28]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[28]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[29]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[29]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[29]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[2]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[2]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[30]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[30]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[30]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[31]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[31]_i_2_n_0\,
Q => \^p_0_in\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[3]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[3]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[4]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[4]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[5]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[5]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[6]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[6]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[7]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[7]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[8]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[8]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[9]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[9]\,
S => \busy_sr[31]_i_1_n_0\
);
\data_sr[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
I2 => DOADO(7),
O => \data_sr[10]_i_1_n_0\
);
\data_sr[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
I2 => DOADO(8),
O => \data_sr[12]_i_1_n_0\
);
\data_sr[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
I2 => DOADO(9),
O => \data_sr[13]_i_1_n_0\
);
\data_sr[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
I2 => DOADO(10),
O => \data_sr[14]_i_1_n_0\
);
\data_sr[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
I2 => DOADO(11),
O => \data_sr[15]_i_1_n_0\
);
\data_sr[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
I2 => DOADO(12),
O => \data_sr[16]_i_1_n_0\
);
\data_sr[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
I2 => DOADO(13),
O => \data_sr[17]_i_1_n_0\
);
\data_sr[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
I2 => DOADO(14),
O => \data_sr[18]_i_1_n_0\
);
\data_sr[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
I2 => DOADO(15),
O => \data_sr[19]_i_1_n_0\
);
\data_sr[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[22]\,
I1 => \data_sr_reg_n_0_[21]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[22]_i_1_n_0\
);
\data_sr[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[27]\,
I1 => \data_sr_reg_n_0_[26]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[27]_i_1_n_0\
);
\data_sr[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
O => \data_sr[30]_i_1_n_0\
);
\data_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => \data_sr_reg_n_0_[30]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[31]_i_1_n_0\
);
\data_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \data_sr[31]_i_2_n_0\
);
\data_sr[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
I2 => DOADO(0),
O => \data_sr[3]_i_1_n_0\
);
\data_sr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
I2 => DOADO(1),
O => \data_sr[4]_i_1_n_0\
);
\data_sr[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
I2 => DOADO(2),
O => \data_sr[5]_i_1_n_0\
);
\data_sr[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
I2 => DOADO(3),
O => \data_sr[6]_i_1_n_0\
);
\data_sr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
I2 => DOADO(4),
O => \data_sr[7]_i_1_n_0\
);
\data_sr[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
I2 => DOADO(5),
O => \data_sr[8]_i_1_n_0\
);
\data_sr[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
I2 => DOADO(6),
O => \data_sr[9]_i_1_n_0\
);
\data_sr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[10]_i_1_n_0\,
Q => \data_sr_reg_n_0_[10]\,
R => '0'
);
\data_sr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[10]\,
Q => \data_sr_reg_n_0_[11]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[12]_i_1_n_0\,
Q => \data_sr_reg_n_0_[12]\,
R => '0'
);
\data_sr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[13]_i_1_n_0\,
Q => \data_sr_reg_n_0_[13]\,
R => '0'
);
\data_sr_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[14]_i_1_n_0\,
Q => \data_sr_reg_n_0_[14]\,
R => '0'
);
\data_sr_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[15]_i_1_n_0\,
Q => \data_sr_reg_n_0_[15]\,
R => '0'
);
\data_sr_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[16]_i_1_n_0\,
Q => \data_sr_reg_n_0_[16]\,
R => '0'
);
\data_sr_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[17]_i_1_n_0\,
Q => \data_sr_reg_n_0_[17]\,
R => '0'
);
\data_sr_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[18]_i_1_n_0\,
Q => \data_sr_reg_n_0_[18]\,
R => '0'
);
\data_sr_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[19]_i_1_n_0\,
Q => \data_sr_reg_n_0_[19]\,
R => '0'
);
\data_sr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \^p_0_in\,
Q => \data_sr_reg_n_0_[1]\,
R => '0'
);
\data_sr_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[19]\,
Q => \data_sr_reg_n_0_[20]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[20]\,
Q => \data_sr_reg_n_0_[21]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[22]_i_1_n_0\,
Q => \data_sr_reg_n_0_[22]\,
R => '0'
);
\data_sr_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[22]\,
Q => \data_sr_reg_n_0_[23]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[23]\,
Q => \data_sr_reg_n_0_[24]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[24]\,
Q => \data_sr_reg_n_0_[25]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[25]\,
Q => \data_sr_reg_n_0_[26]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[27]_i_1_n_0\,
Q => \data_sr_reg_n_0_[27]\,
R => '0'
);
\data_sr_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[27]\,
Q => \data_sr_reg_n_0_[28]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[28]\,
Q => \data_sr_reg_n_0_[29]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[1]\,
Q => \data_sr_reg_n_0_[2]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[29]\,
Q => \data_sr_reg_n_0_[30]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[31]_i_1_n_0\,
Q => \data_sr_reg_n_0_[31]\,
R => '0'
);
\data_sr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[3]_i_1_n_0\,
Q => \data_sr_reg_n_0_[3]\,
R => '0'
);
\data_sr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[4]_i_1_n_0\,
Q => \data_sr_reg_n_0_[4]\,
R => '0'
);
\data_sr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[5]_i_1_n_0\,
Q => \data_sr_reg_n_0_[5]\,
R => '0'
);
\data_sr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[6]_i_1_n_0\,
Q => \data_sr_reg_n_0_[6]\,
R => '0'
);
\data_sr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[7]_i_1_n_0\,
Q => \data_sr_reg_n_0_[7]\,
R => '0'
);
\data_sr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[8]_i_1_n_0\,
Q => \data_sr_reg_n_0_[8]\,
R => '0'
);
\data_sr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[9]_i_1_n_0\,
Q => \data_sr_reg_n_0_[9]\,
R => '0'
);
\divider[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \divider_reg__1\(0),
O => \p_0_in__0\(0)
);
\divider[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__1\(0),
I1 => \divider_reg__1\(1),
O => \p_0_in__0\(1)
);
\divider[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \divider_reg__1\(1),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(2),
O => \p_0_in__0\(2)
);
\divider[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(1),
I3 => \divider_reg__1\(3),
O => \p_0_in__0\(3)
);
\divider[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \divider_reg__1\(3),
I1 => \divider_reg__1\(1),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(2),
I4 => \divider_reg__1\(4),
O => \p_0_in__0\(4)
);
\divider[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \p_0_in__0\(5)
);
\divider[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \p_0_in__0\(6)
);
\divider[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \busy_sr[0]_i_3_n_0\,
I2 => \divider_reg__0\(7),
O => \p_0_in__0\(7)
);
\divider_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(0),
Q => \divider_reg__1\(0),
R => '0'
);
\divider_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(1),
Q => \divider_reg__1\(1),
R => '0'
);
\divider_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(2),
Q => \divider_reg__1\(2),
R => '0'
);
\divider_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(3),
Q => \divider_reg__1\(3),
R => '0'
);
\divider_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(4),
Q => \divider_reg__1\(4),
R => '0'
);
\divider_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(5),
Q => \divider_reg__1\(5),
R => '0'
);
\divider_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(6),
Q => \divider_reg__0\(6),
R => '0'
);
\divider_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(7),
Q => \divider_reg__0\(7),
R => '0'
);
sioc_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFCFFF8FFFFFFFF"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => sioc_i_2_n_0,
I2 => sioc_i_3_n_0,
I3 => \busy_sr_reg_n_0_[1]\,
I4 => sioc_i_4_n_0,
I5 => \^p_0_in\,
O => sioc_i_1_n_0
);
sioc_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \divider_reg__0\(7),
O => sioc_i_2_n_0
);
sioc_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"A222"
)
port map (
I0 => sioc_i_5_n_0,
I1 => \busy_sr_reg_n_0_[30]\,
I2 => \divider_reg__0\(6),
I3 => \^p_0_in\,
O => sioc_i_3_n_0
);
sioc_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \busy_sr_reg_n_0_[2]\,
I2 => \^p_0_in\,
I3 => \busy_sr_reg_n_0_[30]\,
O => sioc_i_4_n_0
);
sioc_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \busy_sr_reg_n_0_[1]\,
I2 => \busy_sr_reg_n_0_[29]\,
I3 => \busy_sr_reg_n_0_[2]\,
O => sioc_i_5_n_0
);
sioc_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => sioc_i_1_n_0,
Q => sioc,
R => '0'
);
siod_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => siod_INST_0_i_1_n_0,
O => siod
);
siod_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"B0BBB0BB0000B0BB"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \busy_sr_reg_n_0_[29]\,
I2 => p_1_in_0(0),
I3 => p_1_in_0(1),
I4 => \busy_sr_reg_n_0_[11]\,
I5 => \busy_sr_reg_n_0_[10]\,
O => siod_INST_0_i_1_n_0
);
taken_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \busy_sr_reg[31]_0\,
Q => E(0),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_ov7670_registers is
port (
DOADO : out STD_LOGIC_VECTOR ( 15 downto 0 );
\divider_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
config_finished : out STD_LOGIC;
taken_reg : out STD_LOGIC;
p_1_in : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\divider_reg[2]\ : in STD_LOGIC;
p_0_in : in STD_LOGIC;
resend : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_controller_0_0_ov7670_registers : entity is "ov7670_registers";
end system_ov7670_controller_0_0_ov7670_registers;
architecture STRUCTURE of system_ov7670_controller_0_0_ov7670_registers is
signal \^doado\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal address : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_rep[0]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[1]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[2]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[3]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[4]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[5]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[6]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_2_n_0\ : STD_LOGIC;
signal config_finished_INST_0_i_1_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_2_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_3_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_4_n_0 : STD_LOGIC;
signal NLW_sreg_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_sreg_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_sreg_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \address_reg[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg[7]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[7]\ : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \address_rep[1]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[2]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[3]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[4]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[6]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \address_rep[7]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \busy_sr[0]_i_2\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of config_finished_INST_0 : label is "soft_lutpair30";
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of sreg_reg : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of sreg_reg : label is "p0_d16";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of sreg_reg : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of sreg_reg : label is 4096;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of sreg_reg : label is "U0/Inst_ov7670_registers/sreg";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of sreg_reg : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of sreg_reg : label is 1023;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of sreg_reg : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of sreg_reg : label is 15;
begin
DOADO(15 downto 0) <= \^doado\(15 downto 0);
\address_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => \address_reg__0\(0),
R => resend
);
\address_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => \address_reg__0\(1),
R => resend
);
\address_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => \address_reg__0\(2),
R => resend
);
\address_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => \address_reg__0\(3),
R => resend
);
\address_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => \address_reg__0\(4),
R => resend
);
\address_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => \address_reg__0\(5),
R => resend
);
\address_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => \address_reg__0\(6),
R => resend
);
\address_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => \address_reg__0\(7),
R => resend
);
\address_reg_rep[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => address(0),
R => resend
);
\address_reg_rep[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => address(1),
R => resend
);
\address_reg_rep[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => address(2),
R => resend
);
\address_reg_rep[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => address(3),
R => resend
);
\address_reg_rep[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => address(4),
R => resend
);
\address_reg_rep[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => address(5),
R => resend
);
\address_reg_rep[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => address(6),
R => resend
);
\address_reg_rep[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => address(7),
R => resend
);
\address_rep[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \address_reg__0\(0),
O => \address_rep[0]_i_1_n_0\
);
\address_rep[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \address_reg__0\(0),
I1 => \address_reg__0\(1),
O => \address_rep[1]_i_1_n_0\
);
\address_rep[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \address_reg__0\(1),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(2),
O => \address_rep[2]_i_1_n_0\
);
\address_rep[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \address_reg__0\(2),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(1),
I3 => \address_reg__0\(3),
O => \address_rep[3]_i_1_n_0\
);
\address_rep[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \address_reg__0\(3),
I1 => \address_reg__0\(1),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(2),
I4 => \address_reg__0\(4),
O => \address_rep[4]_i_1_n_0\
);
\address_rep[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[5]_i_1_n_0\
);
\address_rep[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \address_rep[7]_i_2_n_0\,
I1 => \address_reg__0\(6),
O => \address_rep[6]_i_1_n_0\
);
\address_rep[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \address_reg__0\(6),
I1 => \address_rep[7]_i_2_n_0\,
I2 => \address_reg__0\(7),
O => \address_rep[7]_i_1_n_0\
);
\address_rep[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[7]_i_2_n_0\
);
\busy_sr[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FFFE"
)
port map (
I0 => config_finished_INST_0_i_4_n_0,
I1 => config_finished_INST_0_i_3_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_1_n_0,
I4 => p_0_in,
O => p_1_in(0)
);
config_finished_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
O => config_finished
);
config_finished_INST_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(5),
I1 => \^doado\(4),
I2 => \^doado\(7),
I3 => \^doado\(6),
O => config_finished_INST_0_i_1_n_0
);
config_finished_INST_0_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(1),
I1 => \^doado\(0),
I2 => \^doado\(3),
I3 => \^doado\(2),
O => config_finished_INST_0_i_2_n_0
);
config_finished_INST_0_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(13),
I1 => \^doado\(12),
I2 => \^doado\(15),
I3 => \^doado\(14),
O => config_finished_INST_0_i_3_n_0
);
config_finished_INST_0_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(9),
I1 => \^doado\(8),
I2 => \^doado\(11),
I3 => \^doado\(10),
O => config_finished_INST_0_i_4_n_0
);
\divider[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFE0000"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
I4 => \divider_reg[2]\,
I5 => p_0_in,
O => \divider_reg[7]\(0)
);
sreg_reg: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"53295217510C50344F4014383A04401004008C003E000C001100120412801280",
INIT_01 => X"229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440",
INIT_02 => X"90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(13 downto 12) => B"00",
ADDRARDADDR(11 downto 4) => address(7 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 0) => B"11111111111111",
CLKARDCLK => clk,
CLKBWRCLK => '0',
DIADI(15 downto 0) => B"1111111111111111",
DIBDI(15 downto 0) => B"1111111111111111",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"11",
DOADO(15 downto 0) => \^doado\(15 downto 0),
DOBDO(15 downto 0) => NLW_sreg_reg_DOBDO_UNCONNECTED(15 downto 0),
DOPADOP(1 downto 0) => NLW_sreg_reg_DOPADOP_UNCONNECTED(1 downto 0),
DOPBDOP(1 downto 0) => NLW_sreg_reg_DOPBDOP_UNCONNECTED(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"00",
WEBWE(3 downto 0) => B"0000"
);
taken_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055555554"
)
port map (
I0 => p_0_in,
I1 => config_finished_INST_0_i_1_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_3_n_0,
I4 => config_finished_INST_0_i_4_n_0,
I5 => \divider_reg[2]\,
O => taken_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_ov7670_controller is
port (
config_finished : out STD_LOGIC;
siod : out STD_LOGIC;
xclk : out STD_LOGIC;
sioc : out STD_LOGIC;
resend : in STD_LOGIC;
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_controller_0_0_ov7670_controller : entity is "ov7670_controller";
end system_ov7670_controller_0_0_ov7670_controller;
architecture STRUCTURE of system_ov7670_controller_0_0_ov7670_controller is
signal Inst_i2c_sender_n_3 : STD_LOGIC;
signal Inst_ov7670_registers_n_16 : STD_LOGIC;
signal Inst_ov7670_registers_n_18 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal sreg_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
signal sys_clk_i_1_n_0 : STD_LOGIC;
signal taken : STD_LOGIC;
signal \^xclk\ : STD_LOGIC;
begin
xclk <= \^xclk\;
Inst_i2c_sender: entity work.system_ov7670_controller_0_0_i2c_sender
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
\busy_sr_reg[1]_0\ => Inst_i2c_sender_n_3,
\busy_sr_reg[31]_0\ => Inst_ov7670_registers_n_18,
\busy_sr_reg[31]_1\(0) => Inst_ov7670_registers_n_16,
clk => clk,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
sioc => sioc,
siod => siod
);
Inst_ov7670_registers: entity work.system_ov7670_controller_0_0_ov7670_registers
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
clk => clk,
config_finished => config_finished,
\divider_reg[2]\ => Inst_i2c_sender_n_3,
\divider_reg[7]\(0) => Inst_ov7670_registers_n_16,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
resend => resend,
taken_reg => Inst_ov7670_registers_n_18
);
sys_clk_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^xclk\,
O => sys_clk_i_1_n_0
);
sys_clk_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => sys_clk_i_1_n_0,
Q => \^xclk\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0 is
port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_ov7670_controller_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_ov7670_controller_0_0 : entity is "system_ov7670_controller_0_0,ov7670_controller,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_ov7670_controller_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_ov7670_controller_0_0 : entity is "ov7670_controller,Vivado 2016.4";
end system_ov7670_controller_0_0;
architecture STRUCTURE of system_ov7670_controller_0_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
pwdn <= \<const0>\;
reset <= \<const1>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_ov7670_controller_0_0_ov7670_controller
port map (
clk => clk,
config_finished => config_finished,
resend => resend,
sioc => sioc,
siod => siod,
xclk => xclk
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
| mit | 0690c35aaf27cf9ab26531119b30a89c | 0.53277 | 2.812161 | false | false | false | false |
loa-org/loa-hdl | modules/servo/tb/servo_module_tb.vhd | 2 | 3,522 | -------------------------------------------------------------------------------
-- Title : Testbench for design "encoder_module"
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Platform : Spartan 3
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.servo_module_pkg.all;
use work.bus_pkg.all;
-------------------------------------------------------------------------------
entity servo_module_tb is
end servo_module_tb;
-------------------------------------------------------------------------------
architecture tb of servo_module_tb is
-- component generics
constant BASE_ADDRESS : positive := 16#0100#;
constant SERVO_COUNT : positive := 11;
-- component ports
signal servo : std_logic_vector(SERVO_COUNT-1 downto 0);
signal bus_o : busdevice_out_type;
signal bus_i : busdevice_in_type :=
(addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
signal clk : std_logic := '0';
begin
-- component instantiation
DUT : servo_module
generic map (
BASE_ADDRESS => BASE_ADDRESS,
SERVO_COUNT => SERVO_COUNT)
port map (
servo_p => servo,
bus_o => bus_o,
bus_i => bus_i,
clk => clk);
-- clock generation
clk <= not clk after 10 NS;
waveform : process
begin
wait for 20 NS;
for i in 0 to SERVO_COUNT-1 loop
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(
unsigned'(resize(x"0100", bus_i.addr'length)) + i);
bus_i.data <= x"7fff";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
end loop;
wait for 40 ns;
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(
unsigned'(resize(x"0102", bus_i.addr'length)));
bus_i.data <= x"ffff";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(
unsigned'(resize(x"0103", bus_i.addr'length)));
bus_i.data <= x"0002";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(
unsigned'(resize(x"0109", bus_i.addr'length)));
bus_i.data <= x"0000";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait until rising_edge(clk);
wait for 3000 US;
-- Change servo[1] during the signaling time. This change should become
-- active with the next periode.
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(
unsigned'(resize(x"0101", bus_i.addr'length)));
bus_i.data <= x"0000";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait until rising_edge(clk);
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(
unsigned'(resize(x"0109", bus_i.addr'length)));
bus_i.data <= x"7fff";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait until rising_edge(clk);
end process waveform;
end tb;
| bsd-3-clause | a7ed72af6833989c7c6e2fab317e1038 | 0.47615 | 3.766845 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/hdl/system_wrapper.vhd | 1 | 5,622 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Sun Apr 09 10:19:58 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system_wrapper.bd
--Design : system_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
config_finished_0 : out STD_LOGIC;
config_finished_1 : out STD_LOGIC;
data_0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
data_1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
gclk : out STD_LOGIC;
href_0 : in STD_LOGIC;
pclk_0 : in STD_LOGIC;
pclk_1 : in STD_LOGIC;
resend_0 : in STD_LOGIC;
resend_1 : in STD_LOGIC;
sioc_0 : out STD_LOGIC;
sioc_1 : out STD_LOGIC;
siod_0 : inout STD_LOGIC;
siod_1 : inout STD_LOGIC;
vga_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_g : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_hs : out STD_LOGIC;
vga_r : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_vs : out STD_LOGIC;
vsync_0 : in STD_LOGIC;
xclk_0 : out STD_LOGIC;
xclk_1 : out STD_LOGIC
);
end system_wrapper;
architecture STRUCTURE of system_wrapper is
component system is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
pclk_0 : in STD_LOGIC;
pclk_1 : in STD_LOGIC;
config_finished_0 : out STD_LOGIC;
sioc_0 : out STD_LOGIC;
siod_0 : inout STD_LOGIC;
xclk_0 : out STD_LOGIC;
xclk_1 : out STD_LOGIC;
config_finished_1 : out STD_LOGIC;
sioc_1 : out STD_LOGIC;
siod_1 : inout STD_LOGIC;
resend_0 : in STD_LOGIC;
resend_1 : in STD_LOGIC;
data_1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
data_0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
gclk : out STD_LOGIC;
vga_hs : out STD_LOGIC;
vga_vs : out STD_LOGIC;
vga_r : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_g : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
href_0 : in STD_LOGIC;
vsync_0 : in STD_LOGIC
);
end component system;
begin
system_i: component system
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
config_finished_0 => config_finished_0,
config_finished_1 => config_finished_1,
data_0(7 downto 0) => data_0(7 downto 0),
data_1(7 downto 0) => data_1(7 downto 0),
gclk => gclk,
href_0 => href_0,
pclk_0 => pclk_0,
pclk_1 => pclk_1,
resend_0 => resend_0,
resend_1 => resend_1,
sioc_0 => sioc_0,
sioc_1 => sioc_1,
siod_0 => siod_0,
siod_1 => siod_1,
vga_b(3 downto 0) => vga_b(3 downto 0),
vga_g(3 downto 0) => vga_g(3 downto 0),
vga_hs => vga_hs,
vga_r(3 downto 0) => vga_r(3 downto 0),
vga_vs => vga_vs,
vsync_0 => vsync_0,
xclk_0 => xclk_0,
xclk_1 => xclk_1
);
end STRUCTURE;
| mit | 772de10291864346cd251bd2921a128e | 0.577908 | 3.009636 | false | true | false | false |
pgavin/carpe | hdl/tech/dw/mul_dw-rtl.vhdl | 1 | 1,792 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library dware;
use dware.dwpackages.all;
use dware.dw_foundation_comp.all;
architecture rtl of mul_dw is
begin
mul : dw02_mult
generic map (a_width => src1_bits,
b_width => src2_bits,
num_stages => latency,
stall_mode => 0,
rst_mode => 0)
port map (clk => clk,
rstn => 'X',
en => 'X',
tc => not unsgnd,
a => src1,
b => src2,
product => result
);
end;
| apache-2.0 | a120341bfbdb3bf44a1c55640af1b79a | 0.462612 | 4.977778 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_vga_overlay_0_0/system_vga_overlay_0_0_sim_netlist.vhdl | 1 | 22,082 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu Jun 01 11:35:05 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_vga_overlay_0_0/system_vga_overlay_0_0_sim_netlist.vhdl
-- Design : system_vga_overlay_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_overlay_0_0_vga_overlay is
port (
rgb : out STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_1 : in STD_LOGIC_VECTOR ( 20 downto 0 );
clk : in STD_LOGIC;
rgb_0 : in STD_LOGIC_VECTOR ( 20 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_overlay_0_0_vga_overlay : entity is "vga_overlay";
end system_vga_overlay_0_0_vga_overlay;
architecture STRUCTURE of system_vga_overlay_0_0_vga_overlay is
signal b_0 : STD_LOGIC_VECTOR ( 6 downto 0 );
signal b_1 : STD_LOGIC_VECTOR ( 6 downto 0 );
signal g_0 : STD_LOGIC_VECTOR ( 6 downto 0 );
signal g_1 : STD_LOGIC_VECTOR ( 6 downto 0 );
signal r_0 : STD_LOGIC_VECTOR ( 6 downto 0 );
signal r_1 : STD_LOGIC_VECTOR ( 6 downto 0 );
signal rgb0 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal rgb00_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal rgb01_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \rgb[11]_i_2_n_0\ : STD_LOGIC;
signal \rgb[11]_i_3_n_0\ : STD_LOGIC;
signal \rgb[11]_i_4_n_0\ : STD_LOGIC;
signal \rgb[11]_i_5_n_0\ : STD_LOGIC;
signal \rgb[15]_i_2_n_0\ : STD_LOGIC;
signal \rgb[15]_i_3_n_0\ : STD_LOGIC;
signal \rgb[15]_i_4_n_0\ : STD_LOGIC;
signal \rgb[19]_i_2_n_0\ : STD_LOGIC;
signal \rgb[19]_i_3_n_0\ : STD_LOGIC;
signal \rgb[19]_i_4_n_0\ : STD_LOGIC;
signal \rgb[19]_i_5_n_0\ : STD_LOGIC;
signal \rgb[23]_i_2_n_0\ : STD_LOGIC;
signal \rgb[23]_i_3_n_0\ : STD_LOGIC;
signal \rgb[23]_i_4_n_0\ : STD_LOGIC;
signal \rgb[3]_i_2_n_0\ : STD_LOGIC;
signal \rgb[3]_i_3_n_0\ : STD_LOGIC;
signal \rgb[3]_i_4_n_0\ : STD_LOGIC;
signal \rgb[3]_i_5_n_0\ : STD_LOGIC;
signal \rgb[7]_i_2_n_0\ : STD_LOGIC;
signal \rgb[7]_i_3_n_0\ : STD_LOGIC;
signal \rgb[7]_i_4_n_0\ : STD_LOGIC;
signal \rgb_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \rgb_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \rgb_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \rgb_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \rgb_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \rgb_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \rgb_reg[19]_i_1_n_0\ : STD_LOGIC;
signal \rgb_reg[19]_i_1_n_1\ : STD_LOGIC;
signal \rgb_reg[19]_i_1_n_2\ : STD_LOGIC;
signal \rgb_reg[19]_i_1_n_3\ : STD_LOGIC;
signal \rgb_reg[23]_i_1_n_2\ : STD_LOGIC;
signal \rgb_reg[23]_i_1_n_3\ : STD_LOGIC;
signal \rgb_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \rgb_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \rgb_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \rgb_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \rgb_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \rgb_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \NLW_rgb_reg[15]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_rgb_reg[15]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_rgb_reg[23]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_rgb_reg[23]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_rgb_reg[7]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_rgb_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
\b_0_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(0),
Q => b_0(0),
R => '0'
);
\b_0_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(1),
Q => b_0(1),
R => '0'
);
\b_0_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(2),
Q => b_0(2),
R => '0'
);
\b_0_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(3),
Q => b_0(3),
R => '0'
);
\b_0_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(4),
Q => b_0(4),
R => '0'
);
\b_0_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(5),
Q => b_0(5),
R => '0'
);
\b_0_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(6),
Q => b_0(6),
R => '0'
);
\b_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(0),
Q => b_1(0),
R => '0'
);
\b_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(1),
Q => b_1(1),
R => '0'
);
\b_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(2),
Q => b_1(2),
R => '0'
);
\b_1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(3),
Q => b_1(3),
R => '0'
);
\b_1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(4),
Q => b_1(4),
R => '0'
);
\b_1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(5),
Q => b_1(5),
R => '0'
);
\b_1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(6),
Q => b_1(6),
R => '0'
);
\g_0_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(7),
Q => g_0(0),
R => '0'
);
\g_0_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(8),
Q => g_0(1),
R => '0'
);
\g_0_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(9),
Q => g_0(2),
R => '0'
);
\g_0_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(10),
Q => g_0(3),
R => '0'
);
\g_0_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(11),
Q => g_0(4),
R => '0'
);
\g_0_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(12),
Q => g_0(5),
R => '0'
);
\g_0_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(13),
Q => g_0(6),
R => '0'
);
\g_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(7),
Q => g_1(0),
R => '0'
);
\g_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(8),
Q => g_1(1),
R => '0'
);
\g_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(9),
Q => g_1(2),
R => '0'
);
\g_1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(10),
Q => g_1(3),
R => '0'
);
\g_1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(11),
Q => g_1(4),
R => '0'
);
\g_1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(12),
Q => g_1(5),
R => '0'
);
\g_1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(13),
Q => g_1(6),
R => '0'
);
\r_0_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(14),
Q => r_0(0),
R => '0'
);
\r_0_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(15),
Q => r_0(1),
R => '0'
);
\r_0_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(16),
Q => r_0(2),
R => '0'
);
\r_0_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(17),
Q => r_0(3),
R => '0'
);
\r_0_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(18),
Q => r_0(4),
R => '0'
);
\r_0_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(19),
Q => r_0(5),
R => '0'
);
\r_0_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(20),
Q => r_0(6),
R => '0'
);
\r_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(14),
Q => r_1(0),
R => '0'
);
\r_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(15),
Q => r_1(1),
R => '0'
);
\r_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(16),
Q => r_1(2),
R => '0'
);
\r_1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(17),
Q => r_1(3),
R => '0'
);
\r_1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(18),
Q => r_1(4),
R => '0'
);
\r_1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(19),
Q => r_1(5),
R => '0'
);
\r_1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(20),
Q => r_1(6),
R => '0'
);
\rgb[11]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => g_0(3),
I1 => g_1(3),
O => \rgb[11]_i_2_n_0\
);
\rgb[11]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => g_0(2),
I1 => g_1(2),
O => \rgb[11]_i_3_n_0\
);
\rgb[11]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => g_0(1),
I1 => g_1(1),
O => \rgb[11]_i_4_n_0\
);
\rgb[11]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => g_0(0),
I1 => g_1(0),
O => \rgb[11]_i_5_n_0\
);
\rgb[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => g_0(6),
I1 => g_1(6),
O => \rgb[15]_i_2_n_0\
);
\rgb[15]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => g_0(5),
I1 => g_1(5),
O => \rgb[15]_i_3_n_0\
);
\rgb[15]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => g_0(4),
I1 => g_1(4),
O => \rgb[15]_i_4_n_0\
);
\rgb[19]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => r_0(3),
I1 => r_1(3),
O => \rgb[19]_i_2_n_0\
);
\rgb[19]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => r_0(2),
I1 => r_1(2),
O => \rgb[19]_i_3_n_0\
);
\rgb[19]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => r_0(1),
I1 => r_1(1),
O => \rgb[19]_i_4_n_0\
);
\rgb[19]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => r_0(0),
I1 => r_1(0),
O => \rgb[19]_i_5_n_0\
);
\rgb[23]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => r_0(6),
I1 => r_1(6),
O => \rgb[23]_i_2_n_0\
);
\rgb[23]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => r_0(5),
I1 => r_1(5),
O => \rgb[23]_i_3_n_0\
);
\rgb[23]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => r_0(4),
I1 => r_1(4),
O => \rgb[23]_i_4_n_0\
);
\rgb[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => b_0(3),
I1 => b_1(3),
O => \rgb[3]_i_2_n_0\
);
\rgb[3]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => b_0(2),
I1 => b_1(2),
O => \rgb[3]_i_3_n_0\
);
\rgb[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => b_0(1),
I1 => b_1(1),
O => \rgb[3]_i_4_n_0\
);
\rgb[3]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => b_0(0),
I1 => b_1(0),
O => \rgb[3]_i_5_n_0\
);
\rgb[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => b_0(6),
I1 => b_1(6),
O => \rgb[7]_i_2_n_0\
);
\rgb[7]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => b_0(5),
I1 => b_1(5),
O => \rgb[7]_i_3_n_0\
);
\rgb[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => b_0(4),
I1 => b_1(4),
O => \rgb[7]_i_4_n_0\
);
\rgb_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb0(0),
Q => rgb(0),
R => '0'
);
\rgb_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb00_out(2),
Q => rgb(10),
R => '0'
);
\rgb_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb00_out(3),
Q => rgb(11),
R => '0'
);
\rgb_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_reg[11]_i_1_n_0\,
CO(2) => \rgb_reg[11]_i_1_n_1\,
CO(1) => \rgb_reg[11]_i_1_n_2\,
CO(0) => \rgb_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => g_0(3 downto 0),
O(3 downto 0) => rgb00_out(3 downto 0),
S(3) => \rgb[11]_i_2_n_0\,
S(2) => \rgb[11]_i_3_n_0\,
S(1) => \rgb[11]_i_4_n_0\,
S(0) => \rgb[11]_i_5_n_0\
);
\rgb_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb00_out(4),
Q => rgb(12),
R => '0'
);
\rgb_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb00_out(5),
Q => rgb(13),
R => '0'
);
\rgb_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb00_out(6),
Q => rgb(14),
R => '0'
);
\rgb_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb00_out(7),
Q => rgb(15),
R => '0'
);
\rgb_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_reg[11]_i_1_n_0\,
CO(3) => rgb00_out(7),
CO(2) => \NLW_rgb_reg[15]_i_1_CO_UNCONNECTED\(2),
CO(1) => \rgb_reg[15]_i_1_n_2\,
CO(0) => \rgb_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => g_0(6 downto 4),
O(3) => \NLW_rgb_reg[15]_i_1_O_UNCONNECTED\(3),
O(2 downto 0) => rgb00_out(6 downto 4),
S(3) => '1',
S(2) => \rgb[15]_i_2_n_0\,
S(1) => \rgb[15]_i_3_n_0\,
S(0) => \rgb[15]_i_4_n_0\
);
\rgb_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb01_out(0),
Q => rgb(16),
R => '0'
);
\rgb_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb01_out(1),
Q => rgb(17),
R => '0'
);
\rgb_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb01_out(2),
Q => rgb(18),
R => '0'
);
\rgb_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb01_out(3),
Q => rgb(19),
R => '0'
);
\rgb_reg[19]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_reg[19]_i_1_n_0\,
CO(2) => \rgb_reg[19]_i_1_n_1\,
CO(1) => \rgb_reg[19]_i_1_n_2\,
CO(0) => \rgb_reg[19]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => r_0(3 downto 0),
O(3 downto 0) => rgb01_out(3 downto 0),
S(3) => \rgb[19]_i_2_n_0\,
S(2) => \rgb[19]_i_3_n_0\,
S(1) => \rgb[19]_i_4_n_0\,
S(0) => \rgb[19]_i_5_n_0\
);
\rgb_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb0(1),
Q => rgb(1),
R => '0'
);
\rgb_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb01_out(4),
Q => rgb(20),
R => '0'
);
\rgb_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb01_out(5),
Q => rgb(21),
R => '0'
);
\rgb_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb01_out(6),
Q => rgb(22),
R => '0'
);
\rgb_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb01_out(7),
Q => rgb(23),
R => '0'
);
\rgb_reg[23]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_reg[19]_i_1_n_0\,
CO(3) => rgb01_out(7),
CO(2) => \NLW_rgb_reg[23]_i_1_CO_UNCONNECTED\(2),
CO(1) => \rgb_reg[23]_i_1_n_2\,
CO(0) => \rgb_reg[23]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => r_0(6 downto 4),
O(3) => \NLW_rgb_reg[23]_i_1_O_UNCONNECTED\(3),
O(2 downto 0) => rgb01_out(6 downto 4),
S(3) => '1',
S(2) => \rgb[23]_i_2_n_0\,
S(1) => \rgb[23]_i_3_n_0\,
S(0) => \rgb[23]_i_4_n_0\
);
\rgb_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb0(2),
Q => rgb(2),
R => '0'
);
\rgb_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb0(3),
Q => rgb(3),
R => '0'
);
\rgb_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_reg[3]_i_1_n_0\,
CO(2) => \rgb_reg[3]_i_1_n_1\,
CO(1) => \rgb_reg[3]_i_1_n_2\,
CO(0) => \rgb_reg[3]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => b_0(3 downto 0),
O(3 downto 0) => rgb0(3 downto 0),
S(3) => \rgb[3]_i_2_n_0\,
S(2) => \rgb[3]_i_3_n_0\,
S(1) => \rgb[3]_i_4_n_0\,
S(0) => \rgb[3]_i_5_n_0\
);
\rgb_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb0(4),
Q => rgb(4),
R => '0'
);
\rgb_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb0(5),
Q => rgb(5),
R => '0'
);
\rgb_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb0(6),
Q => rgb(6),
R => '0'
);
\rgb_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb0(7),
Q => rgb(7),
R => '0'
);
\rgb_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_reg[3]_i_1_n_0\,
CO(3) => rgb0(7),
CO(2) => \NLW_rgb_reg[7]_i_1_CO_UNCONNECTED\(2),
CO(1) => \rgb_reg[7]_i_1_n_2\,
CO(0) => \rgb_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => b_0(6 downto 4),
O(3) => \NLW_rgb_reg[7]_i_1_O_UNCONNECTED\(3),
O(2 downto 0) => rgb0(6 downto 4),
S(3) => '1',
S(2) => \rgb[7]_i_2_n_0\,
S(1) => \rgb[7]_i_3_n_0\,
S(0) => \rgb[7]_i_4_n_0\
);
\rgb_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb00_out(0),
Q => rgb(8),
R => '0'
);
\rgb_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb00_out(1),
Q => rgb(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_overlay_0_0 is
port (
clk : in STD_LOGIC;
rgb_0 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_1 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_overlay_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_overlay_0_0 : entity is "system_vga_overlay_0_0,vga_overlay,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_overlay_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_overlay_0_0 : entity is "vga_overlay,Vivado 2016.4";
end system_vga_overlay_0_0;
architecture STRUCTURE of system_vga_overlay_0_0 is
begin
U0: entity work.system_vga_overlay_0_0_vga_overlay
port map (
clk => clk,
rgb(23 downto 0) => rgb(23 downto 0),
rgb_0(20 downto 14) => rgb_0(23 downto 17),
rgb_0(13 downto 7) => rgb_0(15 downto 9),
rgb_0(6 downto 0) => rgb_0(7 downto 1),
rgb_1(20 downto 14) => rgb_1(23 downto 17),
rgb_1(13 downto 7) => rgb_1(15 downto 9),
rgb_1(6 downto 0) => rgb_1(7 downto 1)
);
end STRUCTURE;
| mit | df524c07d3a31693b1a4ece70ef10d6e | 0.444389 | 2.581784 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_1_0/synth/system_rgb565_to_rgb888_1_0.vhd | 1 | 3,795 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:rgb565_to_rgb888:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_rgb565_to_rgb888_1_0 IS
PORT (
rgb_565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rgb_888 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_rgb565_to_rgb888_1_0;
ARCHITECTURE system_rgb565_to_rgb888_1_0_arch OF system_rgb565_to_rgb888_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rgb565_to_rgb888_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT rgb565_to_rgb888 IS
PORT (
rgb_565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rgb_888 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT rgb565_to_rgb888;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_rgb565_to_rgb888_1_0_arch: ARCHITECTURE IS "rgb565_to_rgb888,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_rgb565_to_rgb888_1_0_arch : ARCHITECTURE IS "system_rgb565_to_rgb888_1_0,rgb565_to_rgb888,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_rgb565_to_rgb888_1_0_arch: ARCHITECTURE IS "system_rgb565_to_rgb888_1_0,rgb565_to_rgb888,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=rgb565_to_rgb888,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : rgb565_to_rgb888
PORT MAP (
rgb_565 => rgb_565,
rgb_888 => rgb_888
);
END system_rgb565_to_rgb888_1_0_arch;
| mit | 26f40a8c0add6ea4146fe23b1b32b306 | 0.74809 | 3.709677 | false | false | false | false |
ashikpoojari/Hardware-Security | DES CryptoCore/src/roundfunc.vhd | 2 | 2,695 | ----------------------------------------------------------------------------------
-- Company: Hardware Security
-- Designer: Vinayaka Jyothi
--
-- Create Date: 18:42:44 11/28/2016
-- Design Name: DES Round Function
-- Module Name: des_roundfunc - Structural
-- Project Name: DES Crypto Core
-- Target Devices: ANY FPGAs
-- Tool versions: ISE, Vivado
-- Description: Implements round function of DES - Complete Structural Modelling
-- The final outputs are swap left and right 32 bits using registers
-- User may want to just without using registers
--
-- Dependencies: Modules :-> XP- Expansion; DESXOR1,DESXOR2 - XOR; S1..S8 - S-Boxes;
-- PP - Permutation; REG32 - 32 bit register
-- Files :-> xp.vhd,desxor1.vhd,desxor2.vhd, s1.vhd...s8.vhd,pp.vhd
-- reg32.vhd
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity roundfunc is port
(
clk : in std_logic;
reset : in std_logic;
li,ri : in std_logic_vector(1 to 32); --- Left and right 32 bits in
k : in std_logic_vector(1 to 48); -- Round key
lo,ro : out std_logic_vector(1 to 32) --Left and right 32 bits out (After swapping)
);
end roundfunc;
architecture behaviour of roundfunc is
signal xp_to_xor : std_logic_vector(1 to 48);
signal b1x,b2x,b3x,b4x,b5x,b6x,b7x,b8x: std_logic_vector(1 to 6);
signal so1x,so2x,so3x,so4x,so5x,so6x,so7x,so8x: std_logic_vector(1 to 4);
signal ppo,r_toreg32,l_toreg32 : std_logic_vector(1 to 32);
begin
xpension: entity work.xp port map ( ri=>ri,e=>xp_to_xor );
des_xor1: entity work.desxor1 port map ( e=>xp_to_xor,k=>k,b1x=>b1x, b2x=>b2x, b3x=>b3x, b4x=>b4x, b5x=>b5x, b6x=>b6x,b7x=>b7x, b8x=>b8x);
s1a: entity work.s1 port map ( clk=>clk, b=>b1x, so=>so1x);
s2a: entity work.s2 port map ( clk=>clk, b=>b2x, so=>so2x);
s3a: entity work.s3 port map ( clk=>clk, b=>b3x, so=>so3x);
s4a: entity work.s4 port map ( clk=>clk, b=>b4x, so=>so4x);
s5a: entity work.s5 port map ( clk=>clk, b=>b5x, so=>so5x);
s6a: entity work.s6 port map ( clk=>clk, b=>b6x, so=>so6x);
s7a: entity work.s7 port map ( clk=>clk, b=>b7x, so=>so7x);
s8a: entity work.s8 port map ( clk=>clk, b=>b8x, so=>so8x);
pperm: entity work.pp port map ( so1x=>so1x, so2x=>so2x, so3x=>so3x, so4x=>so4x, so5x=>so5x, so6x=>so6x, so7x=>so7x, so8x=>so8x,
ppo=>ppo );
des_xor2: entity work.desxor2 port map ( d=>ppo,l=>li, q=>r_toreg32 );
l_toreg32<=ri;
register32_left: entity work.reg32 port map ( a=>l_toreg32, q=>lo,reset=>reset, clk=>clk );
register32_right: entity work.reg32 port map ( a=>r_toreg32, q=>ro,reset=>reset, clk=>clk );
end;
| mit | 0a148dd1f1fd36212dad859f0dfc5203 | 0.631911 | 2.606383 | false | false | false | false |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/niosii_system_sysid_qsys_0_control_slave_translator.vhd | 1 | 14,348 | -- niosii_system_sysid_qsys_0_control_slave_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:31
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_sysid_qsys_0_control_slave_translator is
generic (
AV_ADDRESS_W : integer := 1;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 25;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 0;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(24 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(0 downto 0); -- avalon_anti_slave_0.address
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_byteenable : out std_logic_vector(3 downto 0);
av_chipselect : out std_logic;
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_read : out std_logic;
av_readdatavalid : in std_logic := '0';
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_waitrequest : in std_logic := '0';
av_write : out std_logic;
av_writebyteenable : out std_logic_vector(3 downto 0);
av_writedata : out std_logic_vector(31 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity niosii_system_sysid_qsys_0_control_slave_translator;
architecture rtl of niosii_system_sysid_qsys_0_control_slave_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(0 downto 0); -- address
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
sysid_qsys_0_control_slave_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_readdata => av_readdata, -- .readdata
av_write => open, -- (terminated)
av_read => open, -- (terminated)
av_writedata => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of niosii_system_sysid_qsys_0_control_slave_translator
| apache-2.0 | c72c6b02884581b7ecfd64d374f533f1 | 0.437692 | 4.281707 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/rgb565_to_rgb888/rgb565_to_rgb888.srcs/sources_1/new/rgb565_to_rgb888.vhd | 6 | 1,494 | ----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: rgb565_to_rgb888 - Structural
-- Description: Convert 16-bit rgb565 to 24-bit rgb888
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity rgb565_to_rgb888 is
port(
clk: in std_logic;
rgb_565: in std_logic_vector(15 downto 0);
rgb_888: out std_logic_vector(23 downto 0)
);
end rgb565_to_rgb888;
architecture Structural of rgb565_to_rgb888 is
signal red, green, blue: std_logic_vector(7 downto 0) := "00000000";
begin
red(4 downto 0) <= rgb_565(15 downto 11);
green(5 downto 0) <= rgb_565(10 downto 5);
blue(4 downto 0) <= rgb_565(4 downto 0);
process(clk)
variable r_1, r_2, g_1, g_2, b_1, b_2: unsigned(7 downto 0);
begin
if rising_edge(clk) then
r_1 := unsigned(red) sll 3;
r_2 := unsigned(red) srl 2;
g_1 := unsigned(green) sll 2;
g_2 := unsigned(green) srl 4;
b_1 := unsigned(blue) sll 3;
b_2 := unsigned(blue) sll 2;
rgb_888(23 downto 16) <= std_logic_vector(r_1 or r_2);
rgb_888(15 downto 8) <= std_logic_vector(g_1 or g_2);
rgb_888(7 downto 0) <= std_logic_vector(b_1 or b_1);
end if;
end process;
end Structural;
| mit | 3ce381240bd187baa08d29b2c89ffc1f | 0.518072 | 3.434483 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/svd_2x2/svd_2x2.srcs/sources_1/ip/sqrt/demo_tb/tb_sqrt.vhd | 1 | 15,398 | --------------------------------------------------------------------------------
-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Description:
-- This is an example testbench for the CORDIC IP core.
-- The testbench has been generated by Vivado to accompany the IP core
-- instance you have generated.
--
-- This testbench is for demonstration purposes only. See note below for
-- instructions on how to use it with your core.
--
-- See the CORDIC product guide for further information
-- about this core.
--
--------------------------------------------------------------------------------
-- Using this testbench
--
-- This testbench instantiates your generated CORDIC core
-- instance named "sqrt".
--
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
-- documentation for details.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity tb_sqrt is
end tb_sqrt;
architecture tb of tb_sqrt is
-----------------------------------------------------------------------
-- Timing constants
-----------------------------------------------------------------------
constant CLOCK_PERIOD : time := 100 ns;
constant T_HOLD : time := 10 ns;
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
constant TEST_CYCLES : integer := 3000;
constant PHASE_CYCLES : integer := 1000;
-----------------------------------------------------------------------
-- DUT input signals
-----------------------------------------------------------------------
-- General inputs
signal aclk : std_logic := '0'; -- the master clock
-- Slave channel CARTESIAN inputs
signal s_axis_cartesian_tvalid : std_logic := '0'; -- TVALID for channel S_AXIS_CARTESIAN
signal s_axis_cartesian_tdata : std_logic_vector(15 downto 0) := (others => 'X'); -- TDATA for channel S_AXIS_CARTESIAN
-- Slave channel PHASE inputs
signal s_axis_phase_tvalid : std_logic := '0'; -- TVALID for channel S_AXIS_PHASE
signal s_axis_phase_tdata : std_logic_vector(15 downto 0) := (others => 'X'); -- TDATA for channel S_AXIS_PHASE
-----------------------------------------------------------------------
-- DUT output signals
-----------------------------------------------------------------------
-- Master channel DOUT outputs
signal m_axis_dout_tvalid : std_logic := '0'; -- TVALID for channel M_AXIS_DOUT
signal m_axis_dout_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- TDATA for channel M_AXIS_DOUT
-----------------------------------------------------------------------
-- Aliases for AXI channel TDATA fields
-- These are a convenience for viewing data in a simulator waveform viewer.
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
-- to prevent the simulator optimizing away these signals.
-----------------------------------------------------------------------
signal s_axis_cartesian_tdata_real : std_logic_vector(15 downto 0) := (others => '0');
signal s_axis_cartesian_tdata_imag : std_logic_vector(15 downto 0) := (others => '0');
signal s_axis_phase_tdata_real : std_logic_vector(15 downto 0) := (others => '0');
signal m_axis_dout_tdata_real : std_logic_vector(15 downto 0) := (others => '0');
signal m_axis_dout_tdata_imag : std_logic_vector(15 downto 0) := (others => '0');
signal m_axis_dout_tdata_phase : std_logic_vector(15 downto 0) := (others => '0');
-----------------------------------------------------------------------
-- Testbench signals
-----------------------------------------------------------------------
signal cycles : integer := 0; -- Clock cycle counter
-----------------------------------------------------------------------
-- Constants, types and functions to create input data
-- The CORDIC is fed two sinusoids exp(+/-jwt) of different frequencies and amplitudes:
-- channel CARTESIAN: exp(+jwt), frequency = clock / 30,
-- channel PHASE: exp(-jwt), frequency = clock / 32,
-----------------------------------------------------------------------
constant IP_CARTESIAN_DEPTH : integer := 30;
constant IP_CARTESIAN_WIDTH : integer := 16;
constant IP_CARTESIAN_SHIFT : integer := 3; -- bit shift for amplitude
constant IP_PHASE_DEPTH : integer := 32;
constant IP_PHASE_WIDTH : integer := 16;
constant IP_PHASE_SHIFT : integer := 0; -- no bit shift, max amplitude
type T_IP_INT_ENTRY is record
re : integer;
im : integer;
end record;
type T_IP_CARTESIAN_ENTRY is record
re : std_logic_vector(IP_CARTESIAN_WIDTH-1 downto 0);
im : std_logic_vector(IP_CARTESIAN_WIDTH-1 downto 0);
end record;
type T_IP_PHASE_ENTRY is record
re : std_logic_vector(IP_PHASE_WIDTH-1 downto 0);
end record;
type T_IP_CARTESIAN_TABLE is array (0 to IP_CARTESIAN_DEPTH-1) of T_IP_CARTESIAN_ENTRY;
type T_IP_PHASE_TABLE is array (0 to IP_PHASE_DEPTH-1) of T_IP_PHASE_ENTRY;
-- Common function to calculate sine and cosine values
function create_ip_entry(index, depth, width : integer) return T_IP_INT_ENTRY is
variable result : T_IP_INT_ENTRY;
variable theta : real;
variable limited_width : integer := width - 2;
begin
if limited_width > 30 then
limited_width := 30; --avoid integer overflow
end if;
theta := real(index) / real(depth) * 2.0 * MATH_PI;
result.re := integer(round(cos(theta) * real(2**limited_width)));
result.im := integer(round(sin(theta) * real(2**limited_width)));
return result;
end function create_ip_entry;
-- Use separate functions to calculate channel S_AXIS_CARTESIAN and S_AXIS_PHASE sinusoids as they return different types
function create_ip_cartesian_table return T_IP_CARTESIAN_TABLE is
variable result : T_IP_CARTESIAN_TABLE;
variable entry_int : T_IP_INT_ENTRY;
begin
for i in 0 to IP_CARTESIAN_DEPTH-1 loop
entry_int := create_ip_entry(i, IP_CARTESIAN_DEPTH, IP_CARTESIAN_WIDTH - IP_CARTESIAN_SHIFT);
result(i).re := std_logic_vector(to_signed(entry_int.re, IP_CARTESIAN_WIDTH));
result(i).im := std_logic_vector(to_signed(entry_int.im, IP_CARTESIAN_WIDTH));
end loop;
return result;
end function create_ip_cartesian_table;
function create_ip_phase_table return T_IP_PHASE_TABLE is
variable result : T_IP_PHASE_TABLE;
variable entry_int : T_IP_INT_ENTRY;
begin
for i in 0 to IP_PHASE_DEPTH-1 loop
entry_int := create_ip_entry(IP_PHASE_DEPTH-1-i, IP_PHASE_DEPTH, IP_PHASE_WIDTH - IP_PHASE_SHIFT); -- note rotation direction
result(i).re := std_logic_vector(to_signed(entry_int.re, IP_PHASE_WIDTH));
end loop;
return result;
end function create_ip_phase_table;
-- Call the functions to create the data
constant IP_CARTESIAN_DATA : T_IP_CARTESIAN_TABLE := create_ip_cartesian_table;
constant IP_PHASE_DATA : T_IP_PHASE_TABLE := create_ip_phase_table;
begin
-----------------------------------------------------------------------
-- Instantiate the DUT
-----------------------------------------------------------------------
dut : entity work.sqrt
port map (
aclk => aclk,
s_axis_cartesian_tvalid => s_axis_cartesian_tvalid,
s_axis_cartesian_tdata => s_axis_cartesian_tdata,
m_axis_dout_tvalid => m_axis_dout_tvalid,
m_axis_dout_tdata => m_axis_dout_tdata
);
-----------------------------------------------------------------------
-- Generate clock
-----------------------------------------------------------------------
clock_gen : process
begin
aclk <= '0';
wait for CLOCK_PERIOD;
loop
cycles <= cycles + 1;
aclk <= '0';
wait for CLOCK_PERIOD/2;
aclk <= '1';
wait for CLOCK_PERIOD/2;
if cycles >= TEST_CYCLES then
report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
wait;
end if;
end loop;
end process clock_gen;
-----------------------------------------------------------------------
-- Generate inputs
-----------------------------------------------------------------------
stimuli : process
variable ip_cartesian_index : integer := 0;
variable ip_phase_index : integer := 0;
variable cartesian_tvalid_nxt : std_logic := '0';
variable phase_tvalid_nxt : std_logic := '0';
variable phase2_cycles : integer := 1;
variable phase2_count : integer := 0;
constant PHASE2_LIMIT : integer := 30;
begin
-- Test is stopped in clock_gen process, use endless loop here
loop
-- Drive inputs T_HOLD time after rising edge of clock
wait until rising_edge(aclk);
wait for T_HOLD;
-- Drive AXI TVALID signals to demonstrate different types of operation
case cycles is -- do different types of operation at different phases of the test
when 0 to PHASE_CYCLES * 1 - 1 =>
-- Phase 1: inputs always valid, no missing input data
cartesian_tvalid_nxt := '1';
phase_tvalid_nxt := '1';
when PHASE_CYCLES * 1 to PHASE_CYCLES * 2 - 1 =>
-- Phase 2: deprive channel S_AXIS_CARTESIAN of valid transactions at an increasing rate
phase_tvalid_nxt := '1';
if phase2_count < phase2_cycles then
cartesian_tvalid_nxt := '0';
else
cartesian_tvalid_nxt := '1';
end if;
phase2_count := phase2_count + 1;
if phase2_count >= PHASE2_LIMIT then
phase2_count := 0;
phase2_cycles := phase2_cycles + 1;
end if;
when PHASE_CYCLES * 2 to PHASE_CYCLES * 3 - 1 =>
-- Phase 3: deprive channel S_AXIS_CARTESIAN of 1 out of 2 transactions, and channel S_AXIS_PHASE of 1 out of 3 transactions
if cycles mod 2 = 0 then
cartesian_tvalid_nxt := '0';
else
cartesian_tvalid_nxt := '1';
end if;
if cycles mod 3 = 0 then
phase_tvalid_nxt := '0';
else
phase_tvalid_nxt := '1';
end if;
when others =>
-- Test will stop imminently - do nothing
null;
end case;
-- Drive handshake signals with local variable values
s_axis_cartesian_tvalid <= cartesian_tvalid_nxt;
s_axis_phase_tvalid <= phase_tvalid_nxt;
-- Drive AXI slave channel CARTESIAN payload
-- Drive 'X's on payload signals when not valid
if cartesian_tvalid_nxt /= '1' then
s_axis_cartesian_tdata <= (others => 'X');
else
-- TDATA: Real and imaginary components are each 16 bits wide and byte-aligned at their LSBs
s_axis_cartesian_tdata(15 downto 0) <= IP_CARTESIAN_DATA(ip_cartesian_index).re;
end if;
-- Drive AXI slave channel PHASE payload
-- Drive 'X's on payload signals when not valid
if phase_tvalid_nxt /= '1' then
s_axis_phase_tdata <= (others => 'X');
else
-- TDATA: Real component is 16 bits wide and byte-aligned at its LSBs
s_axis_phase_tdata(15 downto 0) <= IP_PHASE_DATA(ip_phase_index).re;
end if;
-- Increment input data indices
if cartesian_tvalid_nxt = '1' then
ip_cartesian_index := ip_cartesian_index + 1;
if ip_cartesian_index = IP_CARTESIAN_DEPTH then
ip_cartesian_index := 0;
end if;
end if;
if phase_tvalid_nxt = '1' then
ip_phase_index := ip_phase_index + 1;
if ip_phase_index = IP_PHASE_DEPTH then
ip_phase_index := 0;
end if;
end if;
end loop;
end process stimuli;
-----------------------------------------------------------------------
-- Check outputs
-----------------------------------------------------------------------
check_outputs : process
variable check_ok : boolean := true;
begin
-- Check outputs T_STROBE time after rising edge of clock
wait until rising_edge(aclk);
wait for T_STROBE;
-- Do not check the output payload values, as this requires the behavioral model
-- which would make this demonstration testbench unwieldy.
-- Instead, check the protocol of the DOUT channel:
-- check that the payload is valid (not X) when TVALID is high
if m_axis_dout_tvalid = '1' then
if is_x(m_axis_dout_tdata) then
report "ERROR: m_axis_dout_tdata is invalid when m_axis_dout_tvalid is high" severity error;
check_ok := false;
end if;
end if;
assert check_ok
report "ERROR: terminating test with failures." severity failure;
end process check_outputs;
-----------------------------------------------------------------------
-- Assign TDATA fields to aliases, for easy simulator waveform viewing
-----------------------------------------------------------------------
s_axis_cartesian_tdata_real <= s_axis_cartesian_tdata(15 downto 0);
m_axis_dout_tdata_real <= m_axis_dout_tdata(15 downto 0);
end tb;
| mit | bd0f93b67489710ad39ee30b18d29f3a | 0.578192 | 4.257119 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/ieee754_fp_adder_subtractor/ieee754_fp_adder_subtractor.srcs/sources_1/new/ieee754_fp_adder_subtractor.vhd | 3 | 3,203 | ----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: ieee754_fp_adder_subtractor - Structural
-- Description: Adds/subtracts two IEEE-754 floating point numbers
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ieee754_fp_adder_subtractor is
port(
x : in std_logic_vector(31 downto 0);
y : in std_logic_vector(31 downto 0);
z : out std_logic_vector(31 downto 0)
);
end ieee754_fp_adder_subtractor;
architecture Structural of ieee754_fp_adder_subtractor is
signal x_sign, y_sign, z_sign : std_logic;
signal x_exponent, y_exponent, z_exponent : std_logic_vector(7 downto 0);
signal x_mantissa, y_mantissa : std_logic_vector(24 downto 0);
signal z_mantissa : std_logic_vector(22 downto 0);
begin
x_sign <= x(31);
y_sign <= y(31);
z(31) <= z_sign;
x_exponent <= x(30 downto 23);
y_exponent <= y(30 downto 23);
z(30 downto 23) <= z_exponent;
x_mantissa(24) <= '0';
x_mantissa(23) <= '1';
x_mantissa(22 downto 0) <= x(22 downto 0);
y_mantissa(24) <= '0';
y_mantissa(23) <= '1';
y_mantissa(22 downto 0) <= y(22 downto 0);
z(22 downto 0) <= z_mantissa;
process(x_sign, y_sign, x_exponent, y_exponent, x_mantissa, y_mantissa)
variable sign : std_logic := '0';
variable large_exp, small_exp, msb : integer;
variable sum, shifted_sum : unsigned(24 downto 0);
variable large_mant, small_mant: unsigned(24 downto 0);
begin
-- determine which is of greater magnitude: x or y
if unsigned(x_exponent) > unsigned(y_exponent) then
large_exp := to_integer(unsigned(x_exponent));
small_exp := to_integer(unsigned(y_exponent));
large_mant := unsigned(x_mantissa);
small_mant := unsigned(y_mantissa);
sign := x_sign;
else
large_exp := to_integer(unsigned(y_exponent));
small_exp := to_integer(unsigned(x_exponent));
large_mant := unsigned(y_mantissa);
small_mant := unsigned(x_mantissa);
sign := y_sign;
end if;
-- shift the smaller to match the larger, add if the signs match, subtract if not
if (x_sign xor y_sign) = '0' then
sum := large_mant + (small_mant srl (large_exp - small_exp));
else
sum := large_mant - (small_mant srl (large_exp - small_exp));
end if;
msb := 0;
-- shift back the result
for i in 0 to 24 loop
if sum(i) = '1' then
msb := i;
end if;
end loop;
shifted_sum := sum sll 23 - msb;
z_mantissa <= std_logic_vector(shifted_sum(22 downto 0));
z_exponent <= std_logic_vector(to_signed(large_exp, 8) - to_signed(23 - msb, 8));
-- if the result was zero, make the sign positive
if sum = "000000000000000000000000" then
sign := '0';
end if;
z_sign <= sign;
end process;
end Structural;
| mit | 1c6570e2912da425437cd8ba0054d4ea | 0.551983 | 3.715777 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_to_uint_0_1/affine_block_ieee754_fp_to_uint_0_1_sim_netlist.vhdl | 1 | 60,065 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 20 13:52:57 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_to_uint_0_1/affine_block_ieee754_fp_to_uint_0_1_sim_netlist.vhdl
-- Design : affine_block_ieee754_fp_to_uint_0_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity affine_block_ieee754_fp_to_uint_0_1_ieee754_fp_to_uint is
port (
y : out STD_LOGIC_VECTOR ( 9 downto 0 );
\y_8__s_port_\ : out STD_LOGIC;
x : in STD_LOGIC_VECTOR ( 17 downto 0 );
\x[20]\ : in STD_LOGIC;
\x[25]\ : in STD_LOGIC;
\x_7__s_port_\ : in STD_LOGIC;
\x[22]\ : in STD_LOGIC;
\x[21]\ : in STD_LOGIC;
\x[22]_0\ : in STD_LOGIC;
\x[21]_0\ : in STD_LOGIC;
\x[27]\ : in STD_LOGIC;
\x[25]_0\ : in STD_LOGIC;
\x[22]_1\ : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 2 downto 0 );
\x[25]_1\ : in STD_LOGIC;
\x[25]_2\ : in STD_LOGIC;
\x[23]\ : in STD_LOGIC;
\x[27]_0\ : in STD_LOGIC;
\x[24]\ : in STD_LOGIC;
\x[30]\ : in STD_LOGIC;
\x[25]_3\ : in STD_LOGIC;
\x[24]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\x[24]_1\ : in STD_LOGIC;
\x[25]_4\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of affine_block_ieee754_fp_to_uint_0_1_ieee754_fp_to_uint : entity is "ieee754_fp_to_uint";
end affine_block_ieee754_fp_to_uint_0_1_ieee754_fp_to_uint;
architecture STRUCTURE of affine_block_ieee754_fp_to_uint_0_1_ieee754_fp_to_uint is
signal \x_7__s_net_1\ : STD_LOGIC;
signal y2 : STD_LOGIC;
signal \y2_carry__0_n_0\ : STD_LOGIC;
signal \y2_carry__0_n_1\ : STD_LOGIC;
signal \y2_carry__0_n_2\ : STD_LOGIC;
signal \y2_carry__0_n_3\ : STD_LOGIC;
signal \y2_carry__1_n_0\ : STD_LOGIC;
signal \y2_carry__1_n_1\ : STD_LOGIC;
signal \y2_carry__1_n_2\ : STD_LOGIC;
signal \y2_carry__1_n_3\ : STD_LOGIC;
signal \y2_carry__2_n_1\ : STD_LOGIC;
signal \y2_carry__2_n_2\ : STD_LOGIC;
signal \y2_carry__2_n_3\ : STD_LOGIC;
signal \y2_carry_i_1__1_n_0\ : STD_LOGIC;
signal \y2_carry_i_1__2_n_0\ : STD_LOGIC;
signal y2_carry_i_1_n_0 : STD_LOGIC;
signal \y2_carry_i_2__0_n_0\ : STD_LOGIC;
signal \y2_carry_i_2__1_n_0\ : STD_LOGIC;
signal \y2_carry_i_2__2_n_0\ : STD_LOGIC;
signal y2_carry_i_2_n_0 : STD_LOGIC;
signal \y2_carry_i_3__0_n_0\ : STD_LOGIC;
signal \y2_carry_i_3__1_n_0\ : STD_LOGIC;
signal \y2_carry_i_3__2_n_0\ : STD_LOGIC;
signal y2_carry_i_3_n_0 : STD_LOGIC;
signal \y2_carry_i_4__0_n_0\ : STD_LOGIC;
signal \y2_carry_i_4__1_n_0\ : STD_LOGIC;
signal \y2_carry_i_4__2_n_0\ : STD_LOGIC;
signal y2_carry_i_4_n_0 : STD_LOGIC;
signal \y2_carry_i_5__0_n_0\ : STD_LOGIC;
signal y2_carry_i_5_n_0 : STD_LOGIC;
signal y2_carry_i_6_n_0 : STD_LOGIC;
signal y2_carry_i_7_n_0 : STD_LOGIC;
signal y2_carry_i_8_n_0 : STD_LOGIC;
signal y2_carry_n_0 : STD_LOGIC;
signal y2_carry_n_1 : STD_LOGIC;
signal y2_carry_n_2 : STD_LOGIC;
signal y2_carry_n_3 : STD_LOGIC;
signal y3 : STD_LOGIC_VECTOR ( 31 to 31 );
signal \y[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[2]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[2]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[3]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[4]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[4]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[5]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[5]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[6]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[6]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_15_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[8]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[8]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[8]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_12_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_14_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \y_8__s_net_1\ : STD_LOGIC;
signal NLW_y2_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y2_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y2_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y2_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of y2_carry_i_9 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \y[3]_INST_0_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \y[4]_INST_0_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \y[5]_INST_0_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \y[6]_INST_0_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \y[7]_INST_0_i_3\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \y[9]_INST_0_i_10\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \y[9]_INST_0_i_9\ : label is "soft_lutpair0";
begin
\x_7__s_net_1\ <= \x_7__s_port_\;
\y_8__s_port_\ <= \y_8__s_net_1\;
y2_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => y2_carry_n_0,
CO(2) => y2_carry_n_1,
CO(1) => y2_carry_n_2,
CO(0) => y2_carry_n_3,
CYINIT => '1',
DI(3) => y2_carry_i_1_n_0,
DI(2) => y2_carry_i_2_n_0,
DI(1) => y2_carry_i_3_n_0,
DI(0) => y2_carry_i_4_n_0,
O(3 downto 0) => NLW_y2_carry_O_UNCONNECTED(3 downto 0),
S(3) => y2_carry_i_5_n_0,
S(2) => y2_carry_i_6_n_0,
S(1) => y2_carry_i_7_n_0,
S(0) => y2_carry_i_8_n_0
);
\y2_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => y2_carry_n_0,
CO(3) => \y2_carry__0_n_0\,
CO(2) => \y2_carry__0_n_1\,
CO(1) => \y2_carry__0_n_2\,
CO(0) => \y2_carry__0_n_3\,
CYINIT => '0',
DI(3) => y3(31),
DI(2) => y3(31),
DI(1) => y3(31),
DI(0) => '1',
O(3 downto 0) => \NLW_y2_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \y2_carry_i_2__2_n_0\,
S(2) => \y2_carry_i_3__2_n_0\,
S(1) => \y2_carry_i_4__2_n_0\,
S(0) => \y2_carry_i_5__0_n_0\
);
\y2_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \y2_carry__0_n_0\,
CO(3) => \y2_carry__1_n_0\,
CO(2) => \y2_carry__1_n_1\,
CO(1) => \y2_carry__1_n_2\,
CO(0) => \y2_carry__1_n_3\,
CYINIT => '0',
DI(3) => y3(31),
DI(2) => y3(31),
DI(1) => y3(31),
DI(0) => y3(31),
O(3 downto 0) => \NLW_y2_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \y2_carry_i_1__2_n_0\,
S(2) => \y2_carry_i_2__1_n_0\,
S(1) => \y2_carry_i_3__1_n_0\,
S(0) => \y2_carry_i_4__1_n_0\
);
\y2_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \y2_carry__1_n_0\,
CO(3) => y2,
CO(2) => \y2_carry__2_n_1\,
CO(1) => \y2_carry__2_n_2\,
CO(0) => \y2_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => y3(31),
DI(1) => y3(31),
DI(0) => y3(31),
O(3 downto 0) => \NLW_y2_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \y2_carry_i_1__1_n_0\,
S(2) => \y2_carry_i_2__0_n_0\,
S(1) => \y2_carry_i_3__0_n_0\,
S(0) => \y2_carry_i_4__0_n_0\
);
y2_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFEAA0155FFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => y2_carry_i_1_n_0
);
\y2_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFEAA00000000"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => y3(31)
);
\y2_carry_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_1__1_n_0\
);
\y2_carry_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_1__2_n_0\
);
y2_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFAAAA9555"
)
port map (
I0 => x(14),
I1 => x(12),
I2 => x(11),
I3 => x(10),
I4 => x(13),
I5 => x(15),
O => y2_carry_i_2_n_0
);
\y2_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_2__0_n_0\
);
\y2_carry_i_2__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_2__1_n_0\
);
\y2_carry_i_2__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_2__2_n_0\
);
y2_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"EABF"
)
port map (
I0 => x(13),
I1 => x(10),
I2 => x(11),
I3 => x(12),
O => y2_carry_i_3_n_0
);
\y2_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_3__0_n_0\
);
\y2_carry_i_3__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_3__1_n_0\
);
\y2_carry_i_3__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_3__2_n_0\
);
y2_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => x(10),
I1 => x(11),
O => y2_carry_i_4_n_0
);
\y2_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_4__0_n_0\
);
\y2_carry_i_4__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_4__1_n_0\
);
\y2_carry_i_4__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_4__2_n_0\
);
y2_carry_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444442424222"
)
port map (
I0 => x(17),
I1 => x(16),
I2 => x(14),
I3 => \y_8__s_net_1\,
I4 => x(13),
I5 => x(15),
O => y2_carry_i_5_n_0
);
\y2_carry_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_5__0_n_0\
);
y2_carry_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"0111111154444444"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => x(10),
I3 => x(11),
I4 => x(12),
I5 => x(14),
O => y2_carry_i_6_n_0
);
y2_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"006A"
)
port map (
I0 => x(12),
I1 => x(11),
I2 => x(10),
I3 => x(13),
O => y2_carry_i_7_n_0
);
y2_carry_i_8: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => x(11),
I1 => x(10),
O => y2_carry_i_8_n_0
);
y2_carry_i_9: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => x(12),
I1 => x(11),
I2 => x(10),
O => \y_8__s_net_1\
);
\y[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4540FFFF45404540"
)
port map (
I0 => \y[7]_INST_0_i_3_n_0\,
I1 => \x[25]_0\,
I2 => x(10),
I3 => \x[22]_1\,
I4 => \y[0]_INST_0_i_2_n_0\,
I5 => \y[7]_INST_0_i_5_n_0\,
O => y(0)
);
\y[0]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFB"
)
port map (
I0 => \y[2]_INST_0_i_4_n_0\,
I1 => x(0),
I2 => x(10),
I3 => y2,
I4 => O(0),
O => \y[0]_INST_0_i_2_n_0\
);
\y[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4540FFFF45404540"
)
port map (
I0 => \y[7]_INST_0_i_3_n_0\,
I1 => \x[27]\,
I2 => x(10),
I3 => \x[25]_0\,
I4 => \y[1]_INST_0_i_2_n_0\,
I5 => \y[9]_INST_0_i_4_n_0\,
O => y(1)
);
\y[1]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF4F7FFFFFFFF"
)
port map (
I0 => x(0),
I1 => x(10),
I2 => \y[9]_INST_0_i_10_n_0\,
I3 => x(1),
I4 => \y[9]_INST_0_i_8_n_0\,
I5 => \y[9]_INST_0_i_9_n_0\,
O => \y[1]_INST_0_i_2_n_0\
);
\y[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4540FFFF45404540"
)
port map (
I0 => \y[7]_INST_0_i_3_n_0\,
I1 => \x[21]_0\,
I2 => x(10),
I3 => \x[27]\,
I4 => \y[2]_INST_0_i_2_n_0\,
I5 => \y[7]_INST_0_i_5_n_0\,
O => y(2)
);
\y[2]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFCFAAAA"
)
port map (
I0 => \y[3]_INST_0_i_4_n_0\,
I1 => \y[9]_INST_0_i_10_n_0\,
I2 => x(1),
I3 => \y[2]_INST_0_i_4_n_0\,
I4 => x(10),
I5 => y2,
O => \y[2]_INST_0_i_2_n_0\
);
\y[2]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"CFFFCAFA"
)
port map (
I0 => O(2),
I1 => \x[25]_4\,
I2 => y2,
I3 => \x[25]_3\,
I4 => O(1),
O => \y[2]_INST_0_i_4_n_0\
);
\y[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4540FFFF45404540"
)
port map (
I0 => \y[7]_INST_0_i_3_n_0\,
I1 => \x[22]_0\,
I2 => x(10),
I3 => \x[21]_0\,
I4 => \y[3]_INST_0_i_2_n_0\,
I5 => \y[7]_INST_0_i_5_n_0\,
O => y(3)
);
\y[3]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFCA"
)
port map (
I0 => \y[4]_INST_0_i_4_n_0\,
I1 => \y[3]_INST_0_i_4_n_0\,
I2 => x(10),
I3 => y2,
O => \y[3]_INST_0_i_2_n_0\
);
\y[3]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF4FFF7F"
)
port map (
I0 => x(0),
I1 => \y[9]_INST_0_i_10_n_0\,
I2 => \y[9]_INST_0_i_9_n_0\,
I3 => \y[9]_INST_0_i_8_n_0\,
I4 => x(2),
O => \y[3]_INST_0_i_4_n_0\
);
\y[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4540FFFF45404540"
)
port map (
I0 => \y[7]_INST_0_i_3_n_0\,
I1 => \x[21]\,
I2 => x(10),
I3 => \x[22]_0\,
I4 => \y[4]_INST_0_i_2_n_0\,
I5 => \y[7]_INST_0_i_5_n_0\,
O => y(4)
);
\y[4]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFCA"
)
port map (
I0 => \y[5]_INST_0_i_4_n_0\,
I1 => \y[4]_INST_0_i_4_n_0\,
I2 => x(10),
I3 => y2,
O => \y[4]_INST_0_i_2_n_0\
);
\y[4]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF4FFF7F"
)
port map (
I0 => x(1),
I1 => \y[9]_INST_0_i_10_n_0\,
I2 => \y[9]_INST_0_i_9_n_0\,
I3 => \y[9]_INST_0_i_8_n_0\,
I4 => x(3),
O => \y[4]_INST_0_i_4_n_0\
);
\y[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"1510FFFF15101510"
)
port map (
I0 => \y[7]_INST_0_i_3_n_0\,
I1 => \x[22]\,
I2 => x(10),
I3 => \x[21]\,
I4 => \y[5]_INST_0_i_2_n_0\,
I5 => \y[7]_INST_0_i_5_n_0\,
O => y(5)
);
\y[5]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFCA"
)
port map (
I0 => \y[6]_INST_0_i_4_n_0\,
I1 => \y[5]_INST_0_i_4_n_0\,
I2 => x(10),
I3 => y2,
O => \y[5]_INST_0_i_2_n_0\
);
\y[5]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF47CCFFFF47FF"
)
port map (
I0 => x(2),
I1 => \y[9]_INST_0_i_10_n_0\,
I2 => x(4),
I3 => \y[9]_INST_0_i_9_n_0\,
I4 => \y[9]_INST_0_i_8_n_0\,
I5 => x(0),
O => \y[5]_INST_0_i_4_n_0\
);
\y[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0047FFFF00470047"
)
port map (
I0 => \x_7__s_net_1\,
I1 => x(10),
I2 => \x[22]\,
I3 => \y[7]_INST_0_i_3_n_0\,
I4 => \y[6]_INST_0_i_2_n_0\,
I5 => \y[7]_INST_0_i_5_n_0\,
O => y(6)
);
\y[6]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFCA"
)
port map (
I0 => \y[7]_INST_0_i_10_n_0\,
I1 => \y[6]_INST_0_i_4_n_0\,
I2 => x(10),
I3 => y2,
O => \y[6]_INST_0_i_2_n_0\
);
\y[6]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF47CCFFFF47FF"
)
port map (
I0 => x(3),
I1 => \y[9]_INST_0_i_10_n_0\,
I2 => x(5),
I3 => \y[9]_INST_0_i_9_n_0\,
I4 => \y[9]_INST_0_i_8_n_0\,
I5 => x(1),
O => \y[6]_INST_0_i_4_n_0\
);
\y[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0047FFFF00470047"
)
port map (
I0 => \x[20]\,
I1 => x(10),
I2 => \x_7__s_net_1\,
I3 => \y[7]_INST_0_i_3_n_0\,
I4 => \y[7]_INST_0_i_4_n_0\,
I5 => \y[7]_INST_0_i_5_n_0\,
O => y(7)
);
\y[7]_INST_0_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF47FFFFFF4700"
)
port map (
I0 => x(4),
I1 => \y[9]_INST_0_i_9_n_0\,
I2 => x(0),
I3 => \y[9]_INST_0_i_10_n_0\,
I4 => \y[9]_INST_0_i_8_n_0\,
I5 => \y[7]_INST_0_i_15_n_0\,
O => \y[7]_INST_0_i_10_n_0\
);
\y[7]_INST_0_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"50115FDD"
)
port map (
I0 => x(6),
I1 => O(1),
I2 => \x[25]_3\,
I3 => y2,
I4 => x(2),
O => \y[7]_INST_0_i_15_n_0\
);
\y[7]_INST_0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \x[23]\,
I1 => y2,
O => \y[7]_INST_0_i_3_n_0\
);
\y[7]_INST_0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFCA"
)
port map (
I0 => \y[8]_INST_0_i_2_n_0\,
I1 => \y[7]_INST_0_i_10_n_0\,
I2 => x(10),
I3 => y2,
O => \y[7]_INST_0_i_4_n_0\
);
\y[7]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"4040404040405F40"
)
port map (
I0 => \x[23]\,
I1 => \x[27]_0\,
I2 => y2,
I3 => \x[24]\,
I4 => \y[9]_INST_0_i_14_n_0\,
I5 => \x[30]\,
O => \y[7]_INST_0_i_5_n_0\
);
\y[8]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"BABFAAAA"
)
port map (
I0 => \y[8]_INST_0_i_1_n_0\,
I1 => \y[8]_INST_0_i_2_n_0\,
I2 => x(10),
I3 => \y[9]_INST_0_i_2_n_0\,
I4 => \y[9]_INST_0_i_4_n_0\,
O => y(8)
);
\y[8]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4501"
)
port map (
I0 => \y[7]_INST_0_i_3_n_0\,
I1 => x(10),
I2 => \x[20]\,
I3 => \x[25]\,
O => \y[8]_INST_0_i_1_n_0\
);
\y[8]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF4700FFFF47FF"
)
port map (
I0 => x(5),
I1 => \y[9]_INST_0_i_9_n_0\,
I2 => x(1),
I3 => \y[9]_INST_0_i_10_n_0\,
I4 => \y[9]_INST_0_i_8_n_0\,
I5 => \y[8]_INST_0_i_3_n_0\,
O => \y[8]_INST_0_i_2_n_0\
);
\y[8]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFEEA022"
)
port map (
I0 => x(7),
I1 => O(1),
I2 => \x[25]_3\,
I3 => y2,
I4 => x(3),
O => \y[8]_INST_0_i_3_n_0\
);
\y[9]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"BABFAAAA"
)
port map (
I0 => \y[9]_INST_0_i_1_n_0\,
I1 => \y[9]_INST_0_i_2_n_0\,
I2 => x(10),
I3 => \y[9]_INST_0_i_3_n_0\,
I4 => \y[9]_INST_0_i_4_n_0\,
O => y(9)
);
\y[9]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000E2EEE222"
)
port map (
I0 => \x[25]\,
I1 => x(10),
I2 => \x[25]_1\,
I3 => x(11),
I4 => \x[25]_2\,
I5 => \y[7]_INST_0_i_3_n_0\,
O => \y[9]_INST_0_i_1_n_0\
);
\y[9]_INST_0_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"9F90"
)
port map (
I0 => x(11),
I1 => x(10),
I2 => y2,
I3 => O(0),
O => \y[9]_INST_0_i_10_n_0\
);
\y[9]_INST_0_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"5533FF0F"
)
port map (
I0 => x(0),
I1 => x(8),
I2 => x(4),
I3 => \y[9]_INST_0_i_8_n_0\,
I4 => \y[9]_INST_0_i_9_n_0\,
O => \y[9]_INST_0_i_11_n_0\
);
\y[9]_INST_0_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"5353F0FF"
)
port map (
I0 => x(1),
I1 => x(9),
I2 => \y[9]_INST_0_i_8_n_0\,
I3 => x(5),
I4 => \y[9]_INST_0_i_9_n_0\,
O => \y[9]_INST_0_i_12_n_0\
);
\y[9]_INST_0_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => y2,
I1 => \x[24]_0\(1),
I2 => \x[24]_0\(0),
I3 => \x[24]_0\(2),
I4 => \x[24]_1\,
O => \y[9]_INST_0_i_14_n_0\
);
\y[9]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABFBFFFFABFB0000"
)
port map (
I0 => \y[9]_INST_0_i_8_n_0\,
I1 => x(2),
I2 => \y[9]_INST_0_i_9_n_0\,
I3 => x(6),
I4 => \y[9]_INST_0_i_10_n_0\,
I5 => \y[9]_INST_0_i_11_n_0\,
O => \y[9]_INST_0_i_2_n_0\
);
\y[9]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABFBFFFFABFB0000"
)
port map (
I0 => \y[9]_INST_0_i_8_n_0\,
I1 => x(3),
I2 => \y[9]_INST_0_i_9_n_0\,
I3 => x(7),
I4 => \y[9]_INST_0_i_10_n_0\,
I5 => \y[9]_INST_0_i_12_n_0\,
O => \y[9]_INST_0_i_3_n_0\
);
\y[9]_INST_0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \x[24]\,
I1 => \y[9]_INST_0_i_14_n_0\,
I2 => \x[30]\,
O => \y[9]_INST_0_i_4_n_0\
);
\y[9]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAFFFF6AAA0000"
)
port map (
I0 => x(13),
I1 => x(10),
I2 => x(11),
I3 => x(12),
I4 => y2,
I5 => O(2),
O => \y[9]_INST_0_i_8_n_0\
);
\y[9]_INST_0_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"3FC05555"
)
port map (
I0 => O(1),
I1 => x(11),
I2 => x(10),
I3 => x(12),
I4 => y2,
O => \y[9]_INST_0_i_9_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity affine_block_ieee754_fp_to_uint_0_1 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of affine_block_ieee754_fp_to_uint_0_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of affine_block_ieee754_fp_to_uint_0_1 : entity is "affine_block_ieee754_fp_to_uint_0_1,ieee754_fp_to_uint,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of affine_block_ieee754_fp_to_uint_0_1 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of affine_block_ieee754_fp_to_uint_0_1 : entity is "ieee754_fp_to_uint,Vivado 2016.4";
end affine_block_ieee754_fp_to_uint_0_1;
architecture STRUCTURE of affine_block_ieee754_fp_to_uint_0_1 is
signal U0_n_10 : STD_LOGIC;
signal y4 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \y[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[0]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[0]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[0]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[0]_INST_0_i_5_n_1\ : STD_LOGIC;
signal \y[0]_INST_0_i_5_n_2\ : STD_LOGIC;
signal \y[0]_INST_0_i_5_n_3\ : STD_LOGIC;
signal \y[0]_INST_0_i_5_n_4\ : STD_LOGIC;
signal \y[0]_INST_0_i_5_n_5\ : STD_LOGIC;
signal \y[0]_INST_0_i_5_n_6\ : STD_LOGIC;
signal \y[0]_INST_0_i_5_n_7\ : STD_LOGIC;
signal \y[0]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \y[0]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \y[0]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \y[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[1]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[1]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[2]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[2]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[3]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[3]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[4]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[4]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[5]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[5]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[6]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[6]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[6]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_12_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_13_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_14_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_13_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_15_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_16_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_17_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_18_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_19_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_20_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_20_n_1\ : STD_LOGIC;
signal \y[9]_INST_0_i_20_n_2\ : STD_LOGIC;
signal \y[9]_INST_0_i_20_n_3\ : STD_LOGIC;
signal \y[9]_INST_0_i_20_n_4\ : STD_LOGIC;
signal \y[9]_INST_0_i_20_n_5\ : STD_LOGIC;
signal \y[9]_INST_0_i_20_n_6\ : STD_LOGIC;
signal \y[9]_INST_0_i_20_n_7\ : STD_LOGIC;
signal \y[9]_INST_0_i_21_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_21_n_1\ : STD_LOGIC;
signal \y[9]_INST_0_i_21_n_2\ : STD_LOGIC;
signal \y[9]_INST_0_i_21_n_3\ : STD_LOGIC;
signal \y[9]_INST_0_i_21_n_4\ : STD_LOGIC;
signal \y[9]_INST_0_i_21_n_5\ : STD_LOGIC;
signal \y[9]_INST_0_i_21_n_6\ : STD_LOGIC;
signal \y[9]_INST_0_i_21_n_7\ : STD_LOGIC;
signal \y[9]_INST_0_i_22_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_22_n_1\ : STD_LOGIC;
signal \y[9]_INST_0_i_22_n_2\ : STD_LOGIC;
signal \y[9]_INST_0_i_22_n_3\ : STD_LOGIC;
signal \y[9]_INST_0_i_22_n_4\ : STD_LOGIC;
signal \y[9]_INST_0_i_22_n_5\ : STD_LOGIC;
signal \y[9]_INST_0_i_22_n_6\ : STD_LOGIC;
signal \y[9]_INST_0_i_22_n_7\ : STD_LOGIC;
signal \y[9]_INST_0_i_23_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_24_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_25_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_25_n_1\ : STD_LOGIC;
signal \y[9]_INST_0_i_25_n_2\ : STD_LOGIC;
signal \y[9]_INST_0_i_25_n_3\ : STD_LOGIC;
signal \y[9]_INST_0_i_25_n_4\ : STD_LOGIC;
signal \y[9]_INST_0_i_25_n_5\ : STD_LOGIC;
signal \y[9]_INST_0_i_25_n_6\ : STD_LOGIC;
signal \y[9]_INST_0_i_25_n_7\ : STD_LOGIC;
signal \y[9]_INST_0_i_26_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_27_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_27_n_1\ : STD_LOGIC;
signal \y[9]_INST_0_i_27_n_2\ : STD_LOGIC;
signal \y[9]_INST_0_i_27_n_3\ : STD_LOGIC;
signal \y[9]_INST_0_i_27_n_4\ : STD_LOGIC;
signal \y[9]_INST_0_i_27_n_5\ : STD_LOGIC;
signal \y[9]_INST_0_i_27_n_6\ : STD_LOGIC;
signal \y[9]_INST_0_i_27_n_7\ : STD_LOGIC;
signal \y[9]_INST_0_i_28_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_28_n_1\ : STD_LOGIC;
signal \y[9]_INST_0_i_28_n_2\ : STD_LOGIC;
signal \y[9]_INST_0_i_28_n_3\ : STD_LOGIC;
signal \y[9]_INST_0_i_28_n_4\ : STD_LOGIC;
signal \y[9]_INST_0_i_28_n_5\ : STD_LOGIC;
signal \y[9]_INST_0_i_28_n_6\ : STD_LOGIC;
signal \y[9]_INST_0_i_28_n_7\ : STD_LOGIC;
signal \y[9]_INST_0_i_29_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_30_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_31_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_32_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_33_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_34_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_35_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_36_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_37_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_38_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_39_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_40_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_41_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_42_n_3\ : STD_LOGIC;
signal \y[9]_INST_0_i_42_n_6\ : STD_LOGIC;
signal \y[9]_INST_0_i_42_n_7\ : STD_LOGIC;
signal \y[9]_INST_0_i_43_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_44_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_45_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_46_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_47_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_48_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_49_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_50_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_51_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_52_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_53_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_54_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_55_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_56_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \NLW_y[9]_INST_0_i_42_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y[9]_INST_0_i_42_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \y[0]_INST_0_i_4\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \y[1]_INST_0_i_3\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \y[2]_INST_0_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \y[2]_INST_0_i_3\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \y[2]_INST_0_i_5\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \y[3]_INST_0_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \y[4]_INST_0_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \y[5]_INST_0_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \y[6]_INST_0_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \y[7]_INST_0_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \y[7]_INST_0_i_11\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \y[7]_INST_0_i_12\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \y[7]_INST_0_i_13\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \y[7]_INST_0_i_2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \y[9]_INST_0_i_17\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \y[9]_INST_0_i_18\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \y[9]_INST_0_i_19\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \y[9]_INST_0_i_5\ : label is "soft_lutpair9";
begin
U0: entity work.affine_block_ieee754_fp_to_uint_0_1_ieee754_fp_to_uint
port map (
O(2) => \y[0]_INST_0_i_5_n_5\,
O(1) => \y[0]_INST_0_i_5_n_6\,
O(0) => \y[0]_INST_0_i_5_n_7\,
x(17 downto 10) => x(30 downto 23),
x(9 downto 0) => x(9 downto 0),
\x[20]\ => \y[7]_INST_0_i_1_n_0\,
\x[21]\ => \y[5]_INST_0_i_1_n_0\,
\x[21]_0\ => \y[3]_INST_0_i_1_n_0\,
\x[22]\ => \y[6]_INST_0_i_1_n_0\,
\x[22]_0\ => \y[4]_INST_0_i_1_n_0\,
\x[22]_1\ => \y[0]_INST_0_i_1_n_0\,
\x[23]\ => \y[7]_INST_0_i_9_n_0\,
\x[24]\ => \y[9]_INST_0_i_13_n_0\,
\x[24]_0\(2) => \y[9]_INST_0_i_25_n_4\,
\x[24]_0\(1) => \y[9]_INST_0_i_25_n_5\,
\x[24]_0\(0) => \y[9]_INST_0_i_25_n_7\,
\x[24]_1\ => \y[9]_INST_0_i_26_n_0\,
\x[25]\ => \y[9]_INST_0_i_5_n_0\,
\x[25]_0\ => \y[1]_INST_0_i_1_n_0\,
\x[25]_1\ => \y[9]_INST_0_i_6_n_0\,
\x[25]_2\ => \y[9]_INST_0_i_7_n_0\,
\x[25]_3\ => \y[9]_INST_0_i_17_n_0\,
\x[25]_4\ => \y[9]_INST_0_i_18_n_0\,
\x[27]\ => \y[2]_INST_0_i_1_n_0\,
\x[27]_0\ => \y[7]_INST_0_i_11_n_0\,
\x[30]\ => \y[9]_INST_0_i_15_n_0\,
\x_7__s_port_\ => \y[7]_INST_0_i_2_n_0\,
y(9 downto 0) => y(9 downto 0),
\y_8__s_port_\ => U0_n_10
);
\y[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFB8B8FF00B8B800"
)
port map (
I0 => \y[0]_INST_0_i_3_n_0\,
I1 => x(25),
I2 => \y[0]_INST_0_i_4_n_0\,
I3 => x(23),
I4 => x(24),
I5 => \y[2]_INST_0_i_3_n_0\,
O => \y[0]_INST_0_i_1_n_0\
);
\y[0]_INST_0_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => x(23),
I1 => x(24),
O => y4(1)
);
\y[0]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => x(8),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => x(0),
I3 => \y[7]_INST_0_i_11_n_0\,
I4 => x(16),
O => \y[0]_INST_0_i_3_n_0\
);
\y[0]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => x(12),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => x(4),
I3 => \y[7]_INST_0_i_11_n_0\,
I4 => x(20),
O => \y[0]_INST_0_i_4_n_0\
);
\y[0]_INST_0_i_5\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y[0]_INST_0_i_5_n_0\,
CO(2) => \y[0]_INST_0_i_5_n_1\,
CO(1) => \y[0]_INST_0_i_5_n_2\,
CO(0) => \y[0]_INST_0_i_5_n_3\,
CYINIT => y4(0),
DI(3 downto 0) => B"0000",
O(3) => \y[0]_INST_0_i_5_n_4\,
O(2) => \y[0]_INST_0_i_5_n_5\,
O(1) => \y[0]_INST_0_i_5_n_6\,
O(0) => \y[0]_INST_0_i_5_n_7\,
S(3) => \y[0]_INST_0_i_7_n_0\,
S(2) => \y[0]_INST_0_i_8_n_0\,
S(1) => \y[0]_INST_0_i_9_n_0\,
S(0) => y4(1)
);
\y[0]_INST_0_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => x(23),
O => y4(0)
);
\y[0]_INST_0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"1555EAAA"
)
port map (
I0 => x(26),
I1 => x(23),
I2 => x(24),
I3 => x(25),
I4 => x(27),
O => \y[0]_INST_0_i_7_n_0\
);
\y[0]_INST_0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"807F"
)
port map (
I0 => x(25),
I1 => x(24),
I2 => x(23),
I3 => x(26),
O => \y[0]_INST_0_i_8_n_0\
);
\y[0]_INST_0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => x(24),
I1 => x(23),
I2 => x(25),
O => \y[0]_INST_0_i_9_n_0\
);
\y[1]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFB8B8FF00B8B800"
)
port map (
I0 => \y[1]_INST_0_i_3_n_0\,
I1 => x(25),
I2 => \y[1]_INST_0_i_4_n_0\,
I3 => x(23),
I4 => x(24),
I5 => \y[3]_INST_0_i_3_n_0\,
O => \y[1]_INST_0_i_1_n_0\
);
\y[1]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => x(9),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => x(1),
I3 => \y[7]_INST_0_i_11_n_0\,
I4 => x(17),
O => \y[1]_INST_0_i_3_n_0\
);
\y[1]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => x(13),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => x(5),
I3 => \y[7]_INST_0_i_11_n_0\,
I4 => x(21),
O => \y[1]_INST_0_i_4_n_0\
);
\y[2]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EB28"
)
port map (
I0 => \y[2]_INST_0_i_3_n_0\,
I1 => x(23),
I2 => x(24),
I3 => \y[4]_INST_0_i_3_n_0\,
O => \y[2]_INST_0_i_1_n_0\
);
\y[2]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"EABF2A80"
)
port map (
I0 => \y[2]_INST_0_i_5_n_0\,
I1 => x(24),
I2 => x(23),
I3 => x(25),
I4 => \y[6]_INST_0_i_5_n_0\,
O => \y[2]_INST_0_i_3_n_0\
);
\y[2]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => x(10),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => x(2),
I3 => \y[7]_INST_0_i_11_n_0\,
I4 => x(18),
O => \y[2]_INST_0_i_5_n_0\
);
\y[3]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EB28"
)
port map (
I0 => \y[3]_INST_0_i_3_n_0\,
I1 => x(23),
I2 => x(24),
I3 => \y[5]_INST_0_i_3_n_0\,
O => \y[3]_INST_0_i_1_n_0\
);
\y[3]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAACF0FC00F"
)
port map (
I0 => \y[3]_INST_0_i_5_n_0\,
I1 => x(15),
I2 => \y[9]_INST_0_i_18_n_0\,
I3 => \y[7]_INST_0_i_11_n_0\,
I4 => x(7),
I5 => \y[9]_INST_0_i_17_n_0\,
O => \y[3]_INST_0_i_3_n_0\
);
\y[3]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => x(11),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => x(3),
I3 => \y[7]_INST_0_i_11_n_0\,
I4 => x(19),
O => \y[3]_INST_0_i_5_n_0\
);
\y[4]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EB28"
)
port map (
I0 => \y[4]_INST_0_i_3_n_0\,
I1 => x(23),
I2 => x(24),
I3 => \y[6]_INST_0_i_3_n_0\,
O => \y[4]_INST_0_i_1_n_0\
);
\y[4]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8BB8888B8888888"
)
port map (
I0 => \y[0]_INST_0_i_4_n_0\,
I1 => \y[9]_INST_0_i_17_n_0\,
I2 => x(16),
I3 => \y[9]_INST_0_i_18_n_0\,
I4 => \y[7]_INST_0_i_11_n_0\,
I5 => x(8),
O => \y[4]_INST_0_i_3_n_0\
);
\y[5]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7D41"
)
port map (
I0 => \y[7]_INST_0_i_8_n_0\,
I1 => x(23),
I2 => x(24),
I3 => \y[5]_INST_0_i_3_n_0\,
O => \y[5]_INST_0_i_1_n_0\
);
\y[5]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8888888B88888"
)
port map (
I0 => \y[1]_INST_0_i_4_n_0\,
I1 => \y[9]_INST_0_i_17_n_0\,
I2 => x(9),
I3 => \y[9]_INST_0_i_18_n_0\,
I4 => \y[7]_INST_0_i_11_n_0\,
I5 => x(17),
O => \y[5]_INST_0_i_3_n_0\
);
\y[6]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"82BE"
)
port map (
I0 => \y[7]_INST_0_i_6_n_0\,
I1 => x(23),
I2 => x(24),
I3 => \y[6]_INST_0_i_3_n_0\,
O => \y[6]_INST_0_i_1_n_0\
);
\y[6]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8888888B88888"
)
port map (
I0 => \y[6]_INST_0_i_5_n_0\,
I1 => \y[9]_INST_0_i_17_n_0\,
I2 => x(10),
I3 => \y[9]_INST_0_i_18_n_0\,
I4 => \y[7]_INST_0_i_11_n_0\,
I5 => x(18),
O => \y[6]_INST_0_i_3_n_0\
);
\y[6]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => x(14),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => x(6),
I3 => \y[7]_INST_0_i_11_n_0\,
I4 => x(22),
O => \y[6]_INST_0_i_5_n_0\
);
\y[7]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5CC5"
)
port map (
I0 => \y[9]_INST_0_i_7_n_0\,
I1 => \y[7]_INST_0_i_6_n_0\,
I2 => x(23),
I3 => x(24),
O => \y[7]_INST_0_i_1_n_0\
);
\y[7]_INST_0_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"1555EAAA"
)
port map (
I0 => x(26),
I1 => x(23),
I2 => x(24),
I3 => x(25),
I4 => x(27),
O => \y[7]_INST_0_i_11_n_0\
);
\y[7]_INST_0_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"E020"
)
port map (
I0 => x(12),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => \y[7]_INST_0_i_11_n_0\,
I3 => x(20),
O => \y[7]_INST_0_i_12_n_0\
);
\y[7]_INST_0_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"E020"
)
port map (
I0 => x(9),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => \y[7]_INST_0_i_11_n_0\,
I3 => x(17),
O => \y[7]_INST_0_i_13_n_0\
);
\y[7]_INST_0_i_14\: unisim.vcomponents.LUT4
generic map(
INIT => X"4C7C"
)
port map (
I0 => x(15),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => \y[7]_INST_0_i_11_n_0\,
I3 => x(7),
O => \y[7]_INST_0_i_14_n_0\
);
\y[7]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"5CC5"
)
port map (
I0 => \y[7]_INST_0_i_7_n_0\,
I1 => \y[7]_INST_0_i_8_n_0\,
I2 => x(23),
I3 => x(24),
O => \y[7]_INST_0_i_2_n_0\
);
\y[7]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F7F4F7F0000FFFF"
)
port map (
I0 => x(16),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => \y[7]_INST_0_i_11_n_0\,
I3 => x(8),
I4 => \y[7]_INST_0_i_12_n_0\,
I5 => \y[9]_INST_0_i_17_n_0\,
O => \y[7]_INST_0_i_6_n_0\
);
\y[7]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF0000B080B080"
)
port map (
I0 => x(21),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => \y[7]_INST_0_i_11_n_0\,
I3 => x(13),
I4 => \y[7]_INST_0_i_13_n_0\,
I5 => \y[9]_INST_0_i_17_n_0\,
O => \y[7]_INST_0_i_7_n_0\
);
\y[7]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF00001FDF1FDF"
)
port map (
I0 => x(11),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => \y[7]_INST_0_i_11_n_0\,
I3 => x(19),
I4 => \y[7]_INST_0_i_14_n_0\,
I5 => \y[9]_INST_0_i_17_n_0\,
O => \y[7]_INST_0_i_8_n_0\
);
\y[7]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBFFFFFFFFDDDDD"
)
port map (
I0 => x(30),
I1 => x(28),
I2 => x(26),
I3 => U0_n_10,
I4 => x(27),
I5 => x(29),
O => \y[7]_INST_0_i_9_n_0\
);
\y[9]_INST_0_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \y[9]_INST_0_i_20_n_4\,
I1 => \y[9]_INST_0_i_21_n_6\,
I2 => \y[9]_INST_0_i_20_n_6\,
I3 => \y[9]_INST_0_i_22_n_6\,
I4 => \y[9]_INST_0_i_23_n_0\,
I5 => \y[9]_INST_0_i_24_n_0\,
O => \y[9]_INST_0_i_13_n_0\
);
\y[9]_INST_0_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \y[9]_INST_0_i_27_n_7\,
I1 => \y[9]_INST_0_i_27_n_6\,
I2 => \y[9]_INST_0_i_28_n_6\,
I3 => \y[9]_INST_0_i_21_n_5\,
I4 => \y[9]_INST_0_i_29_n_0\,
O => \y[9]_INST_0_i_15_n_0\
);
\y[9]_INST_0_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"CACA0000FFF00000"
)
port map (
I0 => x(11),
I1 => x(19),
I2 => \y[9]_INST_0_i_18_n_0\,
I3 => x(15),
I4 => \y[7]_INST_0_i_11_n_0\,
I5 => \y[9]_INST_0_i_17_n_0\,
O => \y[9]_INST_0_i_16_n_0\
);
\y[9]_INST_0_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => x(24),
I1 => x(23),
I2 => x(25),
O => \y[9]_INST_0_i_17_n_0\
);
\y[9]_INST_0_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => x(26),
I1 => x(23),
I2 => x(24),
I3 => x(25),
O => \y[9]_INST_0_i_18_n_0\
);
\y[9]_INST_0_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"E020"
)
port map (
I0 => x(10),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => \y[7]_INST_0_i_11_n_0\,
I3 => x(18),
O => \y[9]_INST_0_i_19_n_0\
);
\y[9]_INST_0_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \y[9]_INST_0_i_27_n_0\,
CO(3) => \y[9]_INST_0_i_20_n_0\,
CO(2) => \y[9]_INST_0_i_20_n_1\,
CO(1) => \y[9]_INST_0_i_20_n_2\,
CO(0) => \y[9]_INST_0_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y[9]_INST_0_i_20_n_4\,
O(2) => \y[9]_INST_0_i_20_n_5\,
O(1) => \y[9]_INST_0_i_20_n_6\,
O(0) => \y[9]_INST_0_i_20_n_7\,
S(3) => \y[9]_INST_0_i_30_n_0\,
S(2) => \y[9]_INST_0_i_31_n_0\,
S(1) => \y[9]_INST_0_i_32_n_0\,
S(0) => \y[9]_INST_0_i_33_n_0\
);
\y[9]_INST_0_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \y[9]_INST_0_i_28_n_0\,
CO(3) => \y[9]_INST_0_i_21_n_0\,
CO(2) => \y[9]_INST_0_i_21_n_1\,
CO(1) => \y[9]_INST_0_i_21_n_2\,
CO(0) => \y[9]_INST_0_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y[9]_INST_0_i_21_n_4\,
O(2) => \y[9]_INST_0_i_21_n_5\,
O(1) => \y[9]_INST_0_i_21_n_6\,
O(0) => \y[9]_INST_0_i_21_n_7\,
S(3) => \y[9]_INST_0_i_34_n_0\,
S(2) => \y[9]_INST_0_i_35_n_0\,
S(1) => \y[9]_INST_0_i_36_n_0\,
S(0) => \y[9]_INST_0_i_37_n_0\
);
\y[9]_INST_0_i_22\: unisim.vcomponents.CARRY4
port map (
CI => \y[9]_INST_0_i_20_n_0\,
CO(3) => \y[9]_INST_0_i_22_n_0\,
CO(2) => \y[9]_INST_0_i_22_n_1\,
CO(1) => \y[9]_INST_0_i_22_n_2\,
CO(0) => \y[9]_INST_0_i_22_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y[9]_INST_0_i_22_n_4\,
O(2) => \y[9]_INST_0_i_22_n_5\,
O(1) => \y[9]_INST_0_i_22_n_6\,
O(0) => \y[9]_INST_0_i_22_n_7\,
S(3) => \y[9]_INST_0_i_38_n_0\,
S(2) => \y[9]_INST_0_i_39_n_0\,
S(1) => \y[9]_INST_0_i_40_n_0\,
S(0) => \y[9]_INST_0_i_41_n_0\
);
\y[9]_INST_0_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \y[9]_INST_0_i_42_n_6\,
I1 => \y[9]_INST_0_i_22_n_4\,
I2 => \y[9]_INST_0_i_42_n_7\,
I3 => \y[9]_INST_0_i_25_n_6\,
O => \y[9]_INST_0_i_23_n_0\
);
\y[9]_INST_0_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \y[9]_INST_0_i_27_n_5\,
I1 => \y[0]_INST_0_i_5_n_4\,
I2 => \y[9]_INST_0_i_28_n_4\,
I3 => \y[9]_INST_0_i_22_n_5\,
O => \y[9]_INST_0_i_24_n_0\
);
\y[9]_INST_0_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \y[9]_INST_0_i_21_n_0\,
CO(3) => \y[9]_INST_0_i_25_n_0\,
CO(2) => \y[9]_INST_0_i_25_n_1\,
CO(1) => \y[9]_INST_0_i_25_n_2\,
CO(0) => \y[9]_INST_0_i_25_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y[9]_INST_0_i_25_n_4\,
O(2) => \y[9]_INST_0_i_25_n_5\,
O(1) => \y[9]_INST_0_i_25_n_6\,
O(0) => \y[9]_INST_0_i_25_n_7\,
S(3) => \y[9]_INST_0_i_43_n_0\,
S(2) => \y[9]_INST_0_i_44_n_0\,
S(1) => \y[9]_INST_0_i_45_n_0\,
S(0) => \y[9]_INST_0_i_46_n_0\
);
\y[9]_INST_0_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \y[9]_INST_0_i_20_n_7\,
I1 => \y[9]_INST_0_i_27_n_4\,
I2 => \y[9]_INST_0_i_28_n_5\,
I3 => \y[9]_INST_0_i_22_n_7\,
O => \y[9]_INST_0_i_26_n_0\
);
\y[9]_INST_0_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \y[0]_INST_0_i_5_n_0\,
CO(3) => \y[9]_INST_0_i_27_n_0\,
CO(2) => \y[9]_INST_0_i_27_n_1\,
CO(1) => \y[9]_INST_0_i_27_n_2\,
CO(0) => \y[9]_INST_0_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y[9]_INST_0_i_27_n_4\,
O(2) => \y[9]_INST_0_i_27_n_5\,
O(1) => \y[9]_INST_0_i_27_n_6\,
O(0) => \y[9]_INST_0_i_27_n_7\,
S(3) => \y[9]_INST_0_i_47_n_0\,
S(2) => \y[9]_INST_0_i_48_n_0\,
S(1) => \y[9]_INST_0_i_49_n_0\,
S(0) => \y[9]_INST_0_i_50_n_0\
);
\y[9]_INST_0_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \y[9]_INST_0_i_22_n_0\,
CO(3) => \y[9]_INST_0_i_28_n_0\,
CO(2) => \y[9]_INST_0_i_28_n_1\,
CO(1) => \y[9]_INST_0_i_28_n_2\,
CO(0) => \y[9]_INST_0_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y[9]_INST_0_i_28_n_4\,
O(2) => \y[9]_INST_0_i_28_n_5\,
O(1) => \y[9]_INST_0_i_28_n_6\,
O(0) => \y[9]_INST_0_i_28_n_7\,
S(3) => \y[9]_INST_0_i_51_n_0\,
S(2) => \y[9]_INST_0_i_52_n_0\,
S(1) => \y[9]_INST_0_i_53_n_0\,
S(0) => \y[9]_INST_0_i_54_n_0\
);
\y[9]_INST_0_i_29\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \y[9]_INST_0_i_28_n_7\,
I1 => \y[9]_INST_0_i_20_n_5\,
I2 => \y[9]_INST_0_i_21_n_4\,
I3 => \y[9]_INST_0_i_21_n_7\,
O => \y[9]_INST_0_i_29_n_0\
);
\y[9]_INST_0_i_30\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_30_n_0\
);
\y[9]_INST_0_i_31\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_31_n_0\
);
\y[9]_INST_0_i_32\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_32_n_0\
);
\y[9]_INST_0_i_33\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_33_n_0\
);
\y[9]_INST_0_i_34\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_34_n_0\
);
\y[9]_INST_0_i_35\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_35_n_0\
);
\y[9]_INST_0_i_36\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_36_n_0\
);
\y[9]_INST_0_i_37\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_37_n_0\
);
\y[9]_INST_0_i_38\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_38_n_0\
);
\y[9]_INST_0_i_39\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_39_n_0\
);
\y[9]_INST_0_i_40\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_40_n_0\
);
\y[9]_INST_0_i_41\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_41_n_0\
);
\y[9]_INST_0_i_42\: unisim.vcomponents.CARRY4
port map (
CI => \y[9]_INST_0_i_25_n_0\,
CO(3 downto 1) => \NLW_y[9]_INST_0_i_42_CO_UNCONNECTED\(3 downto 1),
CO(0) => \y[9]_INST_0_i_42_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y[9]_INST_0_i_42_O_UNCONNECTED\(3 downto 2),
O(1) => \y[9]_INST_0_i_42_n_6\,
O(0) => \y[9]_INST_0_i_42_n_7\,
S(3 downto 2) => B"00",
S(1) => \y[9]_INST_0_i_55_n_0\,
S(0) => \y[9]_INST_0_i_56_n_0\
);
\y[9]_INST_0_i_43\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_43_n_0\
);
\y[9]_INST_0_i_44\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_44_n_0\
);
\y[9]_INST_0_i_45\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_45_n_0\
);
\y[9]_INST_0_i_46\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_46_n_0\
);
\y[9]_INST_0_i_47\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_47_n_0\
);
\y[9]_INST_0_i_48\: unisim.vcomponents.LUT6
generic map(
INIT => X"00001115FFFFEEEA"
)
port map (
I0 => x(29),
I1 => x(27),
I2 => U0_n_10,
I3 => x(26),
I4 => x(28),
I5 => x(30),
O => \y[9]_INST_0_i_48_n_0\
);
\y[9]_INST_0_i_49\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAA9995"
)
port map (
I0 => x(29),
I1 => x(27),
I2 => U0_n_10,
I3 => x(26),
I4 => x(28),
O => \y[9]_INST_0_i_49_n_0\
);
\y[9]_INST_0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"EB28"
)
port map (
I0 => \y[7]_INST_0_i_7_n_0\,
I1 => x(23),
I2 => x(24),
I3 => \y[9]_INST_0_i_16_n_0\,
O => \y[9]_INST_0_i_5_n_0\
);
\y[9]_INST_0_i_50\: unisim.vcomponents.LUT6
generic map(
INIT => X"A999999955555555"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => x(23),
I3 => x(24),
I4 => x(25),
I5 => x(27),
O => \y[9]_INST_0_i_50_n_0\
);
\y[9]_INST_0_i_51\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_51_n_0\
);
\y[9]_INST_0_i_52\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_52_n_0\
);
\y[9]_INST_0_i_53\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_53_n_0\
);
\y[9]_INST_0_i_54\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_54_n_0\
);
\y[9]_INST_0_i_55\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_55_n_0\
);
\y[9]_INST_0_i_56\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_56_n_0\
);
\y[9]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"C0C00000AFA00000"
)
port map (
I0 => x(12),
I1 => x(20),
I2 => \y[9]_INST_0_i_17_n_0\,
I3 => x(16),
I4 => \y[7]_INST_0_i_11_n_0\,
I5 => \y[9]_INST_0_i_18_n_0\,
O => \y[9]_INST_0_i_6_n_0\
);
\y[9]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF0000B080B080"
)
port map (
I0 => x(22),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => \y[7]_INST_0_i_11_n_0\,
I3 => x(14),
I4 => \y[9]_INST_0_i_19_n_0\,
I5 => \y[9]_INST_0_i_17_n_0\,
O => \y[9]_INST_0_i_7_n_0\
);
end STRUCTURE;
| mit | 261215750cf56d34c7eef713471e3aea | 0.459003 | 2.191274 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/dma_example/dma_example.srcs/sources_1/bd/system/hdl/system_wrapper.vhd | 1 | 3,442 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Wed May 31 20:09:36 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system_wrapper.bd
--Design : system_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC
);
end system_wrapper;
architecture STRUCTURE of system_wrapper is
component system is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC
);
end component system;
begin
system_i: component system
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb
);
end STRUCTURE;
| mit | 5233d4f5f64bf98bd8903aa145ec8cef | 0.589483 | 3.103697 | false | false | false | false |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/niosii_system_timer_0_s1_translator.vhd | 1 | 14,484 | -- niosii_system_timer_0_s1_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:31
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_timer_0_s1_translator is
generic (
AV_ADDRESS_W : integer := 3;
AV_DATA_W : integer := 16;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 1;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 25;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 0;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(24 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(2 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(15 downto 0); -- .writedata
av_chipselect : out std_logic; -- .chipselect
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_byteenable : out std_logic_vector(0 downto 0);
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_read : out std_logic;
av_readdatavalid : in std_logic := '0';
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_waitrequest : in std_logic := '0';
av_writebyteenable : out std_logic_vector(0 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity niosii_system_timer_0_s1_translator;
architecture rtl of niosii_system_timer_0_s1_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(2 downto 0); -- address
av_write : out std_logic; -- write
av_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(15 downto 0); -- writedata
av_chipselect : out std_logic; -- chipselect
av_read : out std_logic; -- read
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
timer_0_s1_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_chipselect => av_chipselect, -- .chipselect
av_read => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of niosii_system_timer_0_s1_translator
| apache-2.0 | 668accf6cd52ef2bba6754ddcf56b4d7 | 0.430268 | 4.322292 | false | false | false | false |
sbourdeauducq/dspunit | sim/bench_dspunit8.vhd | 2 | 11,808 | -- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspunit_pac.all;
-------------------------------------------------------------------------------
entity bench_dspunit8 is
end bench_dspunit8;
--=----------------------------------------------------------------------------
architecture archi_bench_dspunit of bench_dspunit8 is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
component dspunit
port (
clk : in std_logic;
clk_cpu : in std_logic;
reset : in std_logic;
data_in_m0 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m0 : out std_logic_vector((sig_width - 1) downto 0);
addr_r_m0 : out std_logic_vector((cmdreg_width - 1) downto 0);
addr_w_m0 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m0 : out std_logic;
c_en_m0 : out std_logic;
data_in_m1 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m1 : out std_logic_vector((sig_width - 1) downto 0);
addr_m1 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m1 : out std_logic;
c_en_m1 : out std_logic;
data_in_m2 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m2 : out std_logic_vector((sig_width - 1) downto 0);
addr_m2 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m2 : out std_logic;
c_en_m2 : out std_logic;
addr_cmdreg : in std_logic_vector((cmdreg_addr_width - 1) downto 0);
data_in_cmdreg : in std_logic_vector((cmdreg_data_width - 1) downto 0);
wr_en_cmdreg : in std_logic;
data_out_cmdreg : out std_logic_vector((cmdreg_data_width - 1) downto 0);
irq : out std_logic;
op_done : out std_logic
);
end component;
component gen_memory
generic (
addr_width : natural;
data_width : natural
);
port (
address_a : in std_logic_vector((addr_width - 1) downto 0);
address_b : in std_logic_vector((addr_width - 1) downto 0);
clock_a : in std_logic;
clock_b : in std_logic;
data_a : in std_logic_vector((data_width - 1) downto 0);
data_b : in std_logic_vector((data_width - 1) downto 0);
wren_a : in std_logic;
wren_b : in std_logic;
q_a : out std_logic_vector((data_width - 1) downto 0);
q_b : out std_logic_vector((data_width - 1) downto 0)
);
end component;
component clock_gen
generic (
tpw : time;
tps : time
);
port (
clk : out std_logic;
reset : out std_logic
);
end component;
component regBtoW
generic (
addr_width : integer
);
port (
reset : in std_logic;
clk : in std_logic;
data_in : in std_logic_vector(7 downto 0);
addr_in : in std_logic_vector(addr_width downto 0);
wr_in : in std_logic;
regbank_sel : in std_logic;
data_out : out std_logic_vector(15 downto 0);
addr_out : out std_logic_vector((addr_width - 1) downto 0);
wr_out : out std_logic
);
end component;
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_clk : std_logic;
signal s_reset : std_logic;
signal s_data_in_m0 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_out_m0 : std_logic_vector((sig_width - 1) downto 0);
signal s_addr_r_m0 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_addr_w_m0 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_wr_en_m0 : std_logic;
signal s_c_en_m0 : std_logic;
signal s_data_in_m1 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_out_m1 : std_logic_vector((sig_width - 1) downto 0);
signal s_addr_m1 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_wr_en_m1 : std_logic;
signal s_c_en_m1 : std_logic;
signal s_data_in_m2 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_out_m2 : std_logic_vector((sig_width - 1) downto 0);
signal s_addr_m2 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_wr_en_m2 : std_logic;
signal s_c_en_m2 : std_logic;
signal s_addr_cmdreg : std_logic_vector((cmdreg_addr_width - 1) downto 0);
signal s_data_in_cmdreg : std_logic_vector((cmdreg_data_width - 1) downto 0);
signal s_wr_en_cmdreg : std_logic;
signal s_data_out_cmdreg : std_logic_vector((cmdreg_data_width - 1) downto 0);
signal s_op_done : std_logic;
signal s_data_in_cmdreg8 : std_logic_vector(7 downto 0);
signal s_addr_cmdreg8 : std_logic_vector(cmdreg_addr_width downto 0);
signal s_wr_en_cmdreg8 : std_logic;
signal s_regbank_sel : std_logic;
signal s_irq : std_logic;
begin -- archs_bench_dspunit
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
dspunit_1 : dspunit
port map (
clk => s_clk,
clk_cpu => s_clk,
reset => s_reset,
data_in_m0 => s_data_in_m0,
data_out_m0 => s_data_out_m0,
addr_r_m0 => s_addr_r_m0,
addr_w_m0 => s_addr_w_m0,
wr_en_m0 => s_wr_en_m0,
c_en_m0 => s_c_en_m0,
data_in_m1 => s_data_in_m1,
data_out_m1 => s_data_out_m1,
addr_m1 => s_addr_m1,
wr_en_m1 => s_wr_en_m1,
c_en_m1 => s_c_en_m1,
data_in_m2 => s_data_in_m2,
data_out_m2 => s_data_out_m2,
addr_m2 => s_addr_m2,
wr_en_m2 => s_wr_en_m2,
c_en_m2 => s_c_en_m2,
addr_cmdreg => s_addr_cmdreg,
data_in_cmdreg => s_data_in_cmdreg,
wr_en_cmdreg => s_wr_en_cmdreg,
data_out_cmdreg => s_data_out_cmdreg,
irq => s_irq,
op_done => s_op_done);
gen_memory_1 : gen_memory
generic map (
addr_width => 16,
data_width => 16)
port map (
address_a => s_addr_r_m0,
address_b => s_addr_w_m0,
clock_a => s_clk,
clock_b => s_clk,
data_a => (others => '0'),
data_b => s_data_out_m0,
wren_a => '0',
wren_b => s_wr_en_m0,
q_a => s_data_in_m0,
q_b => open);
gen_memory_2 : gen_memory
generic map (
addr_width => 16,
data_width => 16)
port map (
address_a => s_addr_m1,
address_b => (others => '0'),
clock_a => s_clk,
clock_b => s_clk,
data_a => s_data_out_m1,
data_b => (others => '0'),
wren_a => s_wr_en_m1,
wren_b => '0',
q_a => s_data_in_m1,
q_b => open);
gen_memory_3 : gen_memory
generic map (
addr_width => 16,
data_width => 16)
port map (
address_a => s_addr_m2,
address_b => (others => '0'),
clock_a => s_clk,
clock_b => s_clk,
data_a => s_data_out_m2,
data_b => (others => '0'),
wren_a => s_wr_en_m2,
wren_b => '0',
q_a => s_data_in_m2,
q_b => open);
clock_gen_1 : clock_gen
generic map (
tpw => 2.5 ns,
tps => 0 ns)
port map (
clk => s_clk,
reset => s_reset);
regBtoW_1 : regBtoW
generic map (
addr_width => cmdreg_addr_width)
port map (
reset => s_reset,
clk => s_clk,
data_in => s_data_in_cmdreg8,
addr_in => s_addr_cmdreg8,
wr_in => s_wr_en_cmdreg8,
regbank_sel => s_regbank_sel,
data_out => s_data_in_cmdreg,
addr_out => s_addr_cmdreg,
wr_out => s_wr_en_cmdreg);
--=---------------------------------------------------------------------------
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
-- s_addr_cmdreg <= "000000", "000010" after 151 ns, "000111" after 161 ns, "000000" after 171 ns,
-- "000010" after 851 ns, "000111" after 861 ns, "000000" after 871 ns,
-- "000010" after 3651 ns, "000111" after 3661 ns, "000000" after 3671 ns;
-- s_data_in_cmdreg <= x"0000", x"000F" after 151 ns, x"0002" after 161 ns, x"0000" after 171 ns,
-- x"000F" after 851 ns, x"0003" after 861 ns, x"0000" after 871 ns,
-- x"000F" after 3651 ns, x"0002" after 3661 ns, x"0000" after 3671 ns;
-- s_wr_en_cmdreg <= '0', '1' after 151 ns, '0' after 171 ns, '1' after 851 ns, '0' after 871 ns,
-- '1' after 3651 ns, '0' after 3671 ns;
s_addr_cmdreg8 <= "0000000", "0000111" after 141 ns, "0000110" after 146 ns, "0000101" after 151 ns, "0000100" after 156 ns, "0001111" after 161 ns, "0001110" after 166 ns, "0000001" after 171 ns, "0000000" after 176 ns;
-- "0000101" after 851 ns, "0000100" after 856 ns, "0001111" after 861 ns, "0001110" after 861 ns, "000000" after 871 ns,
-- "000010" after 3651 ns, "000111" after 3661 ns, "000000" after 3671 ns;
s_data_in_cmdreg8 <= x"00", x"01" after 141 ns, x"32" after 146 ns, x"01" after 151 ns, x"FF" after 156 ns, x"00" after 161 ns, x"02" after 166 ns, x"00" after 171 ns, x"00" after 176 ns;
-- x"000F" after 851 ns, x"0003" after 861 ns, x"0000" after 871 ns,
-- x"000F" after 3651 ns, x"0002" after 3661 ns, x"0000" after 3671 ns;
s_wr_en_cmdreg8 <= '0', '1' after 141 ns, '0' after 171 ns; -- '1' after 851 ns, '0' after 871 ns,
-- '1' after 3651 ns, '0' after 3671 ns;
s_regbank_sel <= '1';
end archi_bench_dspunit;
-------------------------------------------------------------------------------
-- Simulation parameters
-->SIMSTOPTIME=10000ns
-->SIMSAVFILE=
-------------------------------------------------------------------------------
| gpl-3.0 | db7aad75a4304c740afc862f297398dd | 0.480098 | 3.371788 | false | false | false | false |
pgavin/carpe | hdl/tech/inferred/encoder_inferred-rtl.vhdl | 1 | 11,834 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture rtl of encoder_inferred is
begin
input_bits_1 : if input_bits = 1 generate
mux : block
signal sel : std_ulogic_vector(0 downto 0);
begin
sel <= datain(0 downto 0);
with sel select
dataout <= "1" when "1",
(others => 'X') when others;
end block;
end generate;
input_bits_2 : if input_bits = 2 generate
mux : block
signal sel : std_ulogic_vector(1 downto 0);
begin
sel <= datain(1 downto 0);
with sel select
dataout <= "0" when "01",
"1" when "10",
(others => 'X') when others;
end block;
end generate;
input_bits_3 : if input_bits = 3 generate
mux : block
signal sel : std_ulogic_vector(2 downto 0);
begin
sel <= datain(2 downto 0);
with sel select
dataout <= "00" when "001",
"01" when "010",
"10" when "100",
(others => 'X') when others;
end block;
end generate;
input_bits_4 : if input_bits = 4 generate
mux : block
signal sel : std_ulogic_vector(3 downto 0);
begin
sel <= datain(3 downto 0);
with sel select
dataout <= "00" when "0001",
"01" when "0010",
"10" when "0100",
"11" when "1000",
(others => 'X') when others;
end block;
end generate;
input_bits_5 : if input_bits = 5 generate
mux : block
signal sel : std_ulogic_vector(4 downto 0);
begin
sel <= datain(4 downto 0);
with sel select
dataout <= "000" when "00001",
"001" when "00010",
"010" when "00100",
"011" when "01000",
"100" when "10000",
(others => 'X') when others;
end block;
end generate;
input_bits_6 : if input_bits = 6 generate
mux : block
signal sel : std_ulogic_vector(5 downto 0);
begin
sel <= datain(5 downto 0);
with sel select
dataout <= "000" when "000001",
"001" when "000010",
"010" when "000100",
"011" when "001000",
"100" when "010000",
"101" when "100000",
(others => 'X') when others;
end block;
end generate;
input_bits_7 : if input_bits = 7 generate
mux : block
signal sel : std_ulogic_vector(6 downto 0);
begin
sel <= datain(6 downto 0);
with sel select
dataout <= "000" when "0000001",
"001" when "0000010",
"010" when "0000100",
"011" when "0001000",
"100" when "0010000",
"101" when "0100000",
"110" when "1000000",
(others => 'X') when others;
end block;
end generate;
input_bits_8 : if input_bits = 8 generate
mux : block
signal sel : std_ulogic_vector(7 downto 0);
begin
sel <= datain(7 downto 0);
with sel select
dataout <= "000" when "00000001",
"001" when "00000010",
"010" when "00000100",
"011" when "00001000",
"100" when "00010000",
"101" when "00100000",
"110" when "01000000",
"111" when "10000000",
(others => 'X') when others;
end block;
end generate;
input_bits_9 : if input_bits = 9 generate
mux : block
signal sel : std_ulogic_vector(8 downto 0);
begin
sel <= datain(8 downto 0);
with sel select
dataout <= "0000" when "000000001",
"0001" when "000000010",
"0010" when "000000100",
"0011" when "000001000",
"0100" when "000010000",
"0101" when "000100000",
"0110" when "001000000",
"0111" when "010000000",
"1000" when "100000000",
(others => 'X') when others;
end block;
end generate;
input_bits_10 : if input_bits = 10 generate
mux : block
signal sel : std_ulogic_vector(9 downto 0);
begin
sel <= datain(9 downto 0);
with sel select
dataout <= "0000" when "0000000001",
"0001" when "0000000010",
"0010" when "0000000100",
"0011" when "0000001000",
"0100" when "0000010000",
"0101" when "0000100000",
"0110" when "0001000000",
"0111" when "0010000000",
"1000" when "0100000000",
"1001" when "1000000000",
(others => 'X') when others;
end block;
end generate;
input_bits_11 : if input_bits = 11 generate
mux : block
signal sel : std_ulogic_vector(10 downto 0);
begin
sel <= datain(10 downto 0);
with sel select
dataout <= "0000" when "00000000001",
"0001" when "00000000010",
"0010" when "00000000100",
"0011" when "00000001000",
"0100" when "00000010000",
"0101" when "00000100000",
"0110" when "00001000000",
"0111" when "00010000000",
"1000" when "00100000000",
"1001" when "01000000000",
"1010" when "10000000000",
(others => 'X') when others;
end block;
end generate;
input_bits_12 : if input_bits = 12 generate
mux : block
signal sel : std_ulogic_vector(11 downto 0);
begin
sel <= datain(11 downto 0);
with sel select
dataout <= "0000" when "000000000001",
"0001" when "000000000010",
"0010" when "000000000100",
"0011" when "000000001000",
"0100" when "000000010000",
"0101" when "000000100000",
"0110" when "000001000000",
"0111" when "000010000000",
"1000" when "000100000000",
"1001" when "001000000000",
"1010" when "010000000000",
"1011" when "100000000000",
(others => 'X') when others;
end block;
end generate;
input_bits_13 : if input_bits = 13 generate
mux : block
signal sel : std_ulogic_vector(12 downto 0);
begin
sel <= datain(12 downto 0);
with sel select
dataout <= "0000" when "0000000000001",
"0001" when "0000000000010",
"0010" when "0000000000100",
"0011" when "0000000001000",
"0100" when "0000000010000",
"0101" when "0000000100000",
"0110" when "0000001000000",
"0111" when "0000010000000",
"1000" when "0000100000000",
"1001" when "0001000000000",
"1010" when "0010000000000",
"1011" when "0100000000000",
"1100" when "1000000000000",
(others => 'X') when others;
end block;
end generate;
input_bits_14 : if input_bits = 14 generate
mux : block
signal sel : std_ulogic_vector(13 downto 0);
begin
sel <= datain(13 downto 0);
with sel select
dataout <= "0000" when "00000000000001",
"0001" when "00000000000010",
"0010" when "00000000000100",
"0011" when "00000000001000",
"0100" when "00000000010000",
"0101" when "00000000100000",
"0110" when "00000001000000",
"0111" when "00000010000000",
"1000" when "00000100000000",
"1001" when "00001000000000",
"1010" when "00010000000000",
"1011" when "00100000000000",
"1100" when "01000000000000",
"1101" when "10000000000000",
(others => 'X') when others;
end block;
end generate;
input_bits_15 : if input_bits = 15 generate
mux : block
signal sel : std_ulogic_vector(14 downto 0);
begin
sel <= datain(14 downto 0);
with sel select
dataout <= "0000" when "000000000000001",
"0001" when "000000000000010",
"0010" when "000000000000100",
"0011" when "000000000001000",
"0100" when "000000000010000",
"0101" when "000000000100000",
"0110" when "000000001000000",
"0111" when "000000010000000",
"1000" when "000000100000000",
"1001" when "000001000000000",
"1010" when "000010000000000",
"1011" when "000100000000000",
"1100" when "001000000000000",
"1101" when "010000000000000",
"1110" when "100000000000000",
(others => 'X') when others;
end block;
end generate;
input_bits_16 : if input_bits = 16 generate
mux : block
signal sel : std_ulogic_vector(15 downto 0);
begin
sel <= datain(15 downto 0);
with sel select
dataout <= "0000" when "0000000000000001",
"0001" when "0000000000000010",
"0010" when "0000000000000100",
"0011" when "0000000000001000",
"0100" when "0000000000010000",
"0101" when "0000000000100000",
"0110" when "0000000001000000",
"0111" when "0000000010000000",
"1000" when "0000000100000000",
"1001" when "0000001000000000",
"1010" when "0000010000000000",
"1011" when "0000100000000000",
"1100" when "0001000000000000",
"1101" when "0010000000000000",
"1110" when "0100000000000000",
"1111" when "1000000000000000",
(others => 'X') when others;
end block;
end generate;
input_bits_out_of_range : if input_bits > 16 generate
input_bits_out_of_rance_proc : process is
begin
assert input_bits > 16 report "input_bits is out of range" severity failure;
wait;
end process;
end generate;
end;
| apache-2.0 | c9d2908b11ce70dadb5e2fd2c4d0c043 | 0.484283 | 4.80471 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0/synth/system_ov7670_controller_0_0.vhd | 5 | 4,423 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ov7670_controller:1.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_ov7670_controller_0_0 IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END system_ov7670_controller_0_0;
ARCHITECTURE system_ov7670_controller_0_0_arch OF system_ov7670_controller_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ov7670_controller_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT ov7670_controller IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END COMPONENT ov7670_controller;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_ov7670_controller_0_0_arch: ARCHITECTURE IS "ov7670_controller,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_ov7670_controller_0_0_arch : ARCHITECTURE IS "system_ov7670_controller_0_0,ov7670_controller,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_ov7670_controller_0_0_arch: ARCHITECTURE IS "system_ov7670_controller_0_0,ov7670_controller,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=ov7670_controller,x_ipVersion=1.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
BEGIN
U0 : ov7670_controller
PORT MAP (
clk => clk,
resend => resend,
config_finished => config_finished,
sioc => sioc,
siod => siod,
reset => reset,
pwdn => pwdn,
xclk => xclk
);
END system_ov7670_controller_0_0_arch;
| mit | 18bfa893b792fd606987641de0c86c74 | 0.732534 | 3.914159 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_clk_wiz_1_0/system_clk_wiz_1_0_sim_netlist.vhdl | 2 | 5,424 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun May 28 20:04:14 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_clk_wiz_1_0 -prefix
-- system_clk_wiz_1_0_ system_clk_wiz_1_0_sim_netlist.vhdl
-- Design : system_clk_wiz_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clk_wiz_1_0_system_clk_wiz_1_0_clk_wiz is
port (
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
end system_clk_wiz_1_0_system_clk_wiz_1_0_clk_wiz;
architecture STRUCTURE of system_clk_wiz_1_0_system_clk_wiz_1_0_clk_wiz is
signal clk_in1_system_clk_wiz_1_0 : STD_LOGIC;
signal clk_out1_system_clk_wiz_1_0 : STD_LOGIC;
signal clkfbout_buf_system_clk_wiz_1_0 : STD_LOGIC;
signal clkfbout_system_clk_wiz_1_0 : STD_LOGIC;
signal NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of plle2_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_system_clk_wiz_1_0,
O => clkfbout_buf_system_clk_wiz_1_0
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_system_clk_wiz_1_0
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_out1_system_clk_wiz_1_0,
O => clk_out1
);
plle2_adv_inst: unisim.vcomponents.PLLE2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT => 10,
CLKFBOUT_PHASE => 0.000000,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE => 5,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
IS_CLKINSEL_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
STARTUP_WAIT => "FALSE"
)
port map (
CLKFBIN => clkfbout_buf_system_clk_wiz_1_0,
CLKFBOUT => clkfbout_system_clk_wiz_1_0,
CLKIN1 => clk_in1_system_clk_wiz_1_0,
CLKIN2 => '0',
CLKINSEL => '1',
CLKOUT0 => clk_out1_system_clk_wiz_1_0,
CLKOUT1 => NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT2 => NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT3 => NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT4 => NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_plle2_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_plle2_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => locked,
PWRDWN => '0',
RST => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clk_wiz_1_0 is
port (
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_clk_wiz_1_0 : entity is true;
end system_clk_wiz_1_0;
architecture STRUCTURE of system_clk_wiz_1_0 is
begin
inst: entity work.system_clk_wiz_1_0_system_clk_wiz_1_0_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1,
locked => locked
);
end STRUCTURE;
| mit | 6d06c3e4cd08857eb8037d07bd58e582 | 0.628503 | 3.275362 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_zed_vga_0_0_1/synth/system_zed_vga_0_0.vhd | 2 | 3,842 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:zed_vga:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_zed_vga_0_0 IS
PORT (
rgb565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vga_r : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_g : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END system_zed_vga_0_0;
ARCHITECTURE system_zed_vga_0_0_arch OF system_zed_vga_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_zed_vga_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT zed_vga IS
PORT (
rgb565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vga_r : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_g : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT zed_vga;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_zed_vga_0_0_arch: ARCHITECTURE IS "zed_vga,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_zed_vga_0_0_arch : ARCHITECTURE IS "system_zed_vga_0_0,zed_vga,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_zed_vga_0_0_arch: ARCHITECTURE IS "system_zed_vga_0_0,zed_vga,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=zed_vga,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : zed_vga
PORT MAP (
rgb565 => rgb565,
vga_r => vga_r,
vga_g => vga_g,
vga_b => vga_b
);
END system_zed_vga_0_0_arch;
| mit | c7627f8ccd5dd2e625e76d4583d7329b | 0.73113 | 3.748293 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_0_1/system_ov7670_vga_0_0_sim_netlist.vhdl | 1 | 5,327 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 07:02:41 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_0_1/system_ov7670_vga_0_0_sim_netlist.vhdl
-- Design : system_ov7670_vga_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_vga_0_0_ov7670_vga is
port (
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 );
pclk : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_vga_0_0_ov7670_vga : entity is "ov7670_vga";
end system_ov7670_vga_0_0_ov7670_vga;
architecture STRUCTURE of system_ov7670_vga_0_0_ov7670_vga is
signal cycle : STD_LOGIC;
signal p_0_in0 : STD_LOGIC;
begin
cycle_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => pclk,
CE => '1',
D => p_0_in0,
Q => cycle,
R => '0'
);
\rgb[15]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => cycle,
O => p_0_in0
);
\rgb_reg[0]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(0),
Q => rgb(0),
R => '0'
);
\rgb_reg[10]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(2),
Q => rgb(10),
R => '0'
);
\rgb_reg[11]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(3),
Q => rgb(11),
R => '0'
);
\rgb_reg[12]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(4),
Q => rgb(12),
R => '0'
);
\rgb_reg[13]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(5),
Q => rgb(13),
R => '0'
);
\rgb_reg[14]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(6),
Q => rgb(14),
R => '0'
);
\rgb_reg[15]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(7),
Q => rgb(15),
R => '0'
);
\rgb_reg[1]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(1),
Q => rgb(1),
R => '0'
);
\rgb_reg[2]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(2),
Q => rgb(2),
R => '0'
);
\rgb_reg[3]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(3),
Q => rgb(3),
R => '0'
);
\rgb_reg[4]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(4),
Q => rgb(4),
R => '0'
);
\rgb_reg[5]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(5),
Q => rgb(5),
R => '0'
);
\rgb_reg[6]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(6),
Q => rgb(6),
R => '0'
);
\rgb_reg[7]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(7),
Q => rgb(7),
R => '0'
);
\rgb_reg[8]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(0),
Q => rgb(8),
R => '0'
);
\rgb_reg[9]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(1),
Q => rgb(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_vga_0_0 is
port (
pclk : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_ov7670_vga_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_ov7670_vga_0_0 : entity is "system_ov7670_vga_0_0,ov7670_vga,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_ov7670_vga_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_ov7670_vga_0_0 : entity is "ov7670_vga,Vivado 2016.4";
end system_ov7670_vga_0_0;
architecture STRUCTURE of system_ov7670_vga_0_0 is
begin
U0: entity work.system_ov7670_vga_0_0_ov7670_vga
port map (
data(7 downto 0) => data(7 downto 0),
pclk => pclk,
rgb(15 downto 0) => rgb(15 downto 0)
);
end STRUCTURE;
| mit | 72f3447b52ab8f43e34c4d2bade3c064 | 0.524122 | 3.178401 | false | false | false | false |
loa-org/loa-hdl | modules/signalprocessing/tb/goertzel_tb.vhd | 2 | 4,199 | -------------------------------------------------------------------------------
-- Title : Testbench for design "goertzel"
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.signalprocessing_pkg.all;
-------------------------------------------------------------------------------
entity goertzel_tb is
end goertzel_tb;
-------------------------------------------------------------------------------
architecture tb of goertzel_tb is
-- component generics
constant SAMPLES : natural := 250;
constant INPUT_WIDTH : natural := 14;
constant CALC_WIDTH : natural := 18;
constant Q : natural := 13;
-- component ports
signal start_p : std_logic;
signal adc_value_p : signed(INPUT_WIDTH-1 downto 0) := (others => '0');
signal result_p : goertzel_result_type;
signal done_s : std_logic;
-- clock
signal clk : std_logic := '1';
-- signal generation
signal PHASE : real := 0.0;
constant SCALE : real := 2.0**7 - 10.0;
constant OFFSET : real := 2.0**13;
constant FSAMPLE : real := 75000.0; -- Sample Frequency in Hertz
constant FSIGNAL : real := 16750.0; -- Signal Frequency in Hertz
signal PHASE_INCREMENT : real := 2.0 * 3.1415 * FSIGNAL / FSAMPLE;
-- calculate Goertzel Coefficient
-- TODO
constant COEF : unsigned := to_unsigned(2732, CALC_WIDTH);
-- debugging signal for goertzel
signal goertzel_value_s : real := 0.0;
begin -- tb
-- component instantiation
DUT : goertzel
generic map (
Q => Q,
SAMPLES => SAMPLES
)
port map (
clk => clk,
coef_p => COEF,
start_p => start_p,
adc_value_p => adc_value_p,
result_p => result_p,
done_p => done_s
);
-- clock generation
clk <= not clk after 20 ns;
-- every 5 clock cycles a start_p signal from ADC
start_gen_proc : process
begin -- process start_gen_proc
start_p <= '0';
wait until clk = '1';
start_p <= '1';
wait until clk = '1';
start_p <= '0';
wait until clk = '1';
wait until clk = '1';
wait until clk = '1';
wait until clk = '1';
end process start_gen_proc;
-- Test signal waveform generation
WaveGen_Proc : process
begin
for n in 0 to 10000 loop
wait until start_p = '1';
-- raw ADC values
-- adc_value_p <= std_logic_vector(to_unsigned(integer(offset + scale*sin(phase)), 14));
-- signed values
adc_value_p <= to_signed(integer(SCALE * sin(PHASE)), INPUT_WIDTH);
-- test
-- adc_value_p <= "00000000001000";
PHASE <= PHASE + PHASE_INCREMENT;
end loop;
-- end, do not repeat pattern
wait for 10 ms;
end process WaveGen_Proc;
-- Calculate Goertzel Value in this test bench. This will not be implemented
-- in VHDL. It is done in the processor in floating point.
GoertzelCheck_proc : process
variable d1 : real := 0.0;
variable d2 : real := 0.0;
variable c : real := 0.0;
begin -- process GoertzelCheck_proc
wait until done_s = '1';
-- new values are available in the result registers
-- convert results from Q-format to real
-- only the upper 16 bits of result_p are stored, so do not shift by 18
-- bits.
d1 := real(to_integer(result_p(0))) / 2.0**(Q-2);
d2 := real(to_integer(result_p(1))) / 2.0**(Q-2);
c := real(to_integer(coef)) / 2.0**Q;
-- calculate goertzel value
goertzel_value_s <= d1**2 + d2**2 - (d2 * d1 * c);
end process GoertzelCheck_proc;
end tb;
| bsd-3-clause | bd0ea2fd1f97e39b84375ca994c24e18 | 0.493927 | 4.04918 | false | false | false | false |
pgavin/carpe | hdl/tech/inferred/div_inferred-rtl.vhdl | 1 | 2,758 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library util;
use util.logic_pkg.all;
architecture rtl of div_inferred is
type comb_type is record
src1_tmp : std_ulogic_vector(src1_bits downto 0);
src2_tmp : std_ulogic_vector(src2_bits downto 0);
dbz : std_ulogic;
overflow : std_ulogic;
error : std_ulogic;
result_tmp : std_ulogic_vector(src1_bits downto 0);
end record;
signal c : comb_type;
pure function div(src1, src2 : std_ulogic_vector(src1_bits downto 0)) return std_ulogic_vector is
variable ret : std_ulogic_vector(src1_bits downto 0);
begin
-- pragma translate_off
if is_x(src1) or is_x(src2) or src2 = (src1_bits downto 0 => '0') then
ret := (others => 'X');
else
-- pragma translate_on
ret := std_ulogic_vector(signed(src1) / signed(src2));
-- pragma translate_off
end if;
-- pragma translate_on
return ret;
end function;
begin
c.src1_tmp <= (src1(src1_bits-1) and not unsgnd) & src1;
c.src2_tmp <= (src2(src2_bits-1) and not unsgnd) & src2;
c.dbz <= all_zeros(src2);
c.overflow <= (not unsgnd and
-- e.g. (signed) 0x80000000 / 0xffffffff = 0x80000000
-- so result is not representable
src1(src1_bits-1) and all_zeros(src1(src1_bits-2 downto 0)) and
all_ones(src2)
);
c.result_tmp <= div(c.src1_tmp, c.src2_tmp);
dbz <= c.dbz;
overflow <= c.overflow;
result <= c.result_tmp(src1_bits-1 downto 0);
end;
| apache-2.0 | ec48e28ab1e04d3d3c66371182885306 | 0.550036 | 3.917614 | false | false | false | false |
SoCdesign/audiomixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/adau1761_audio_v1_00_a/hdl/vhdl/adau1761_izedboard.vhd | 3 | 4,948 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:47:06 01/18/2014
-- Design Name:
-- Module Name: adau1761_izedboard - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library unisim;
use unisim.vcomponents.all;
entity adau1761_izedboard is
Port ( clk_48 : in STD_LOGIC;
AC_ADR0 : out STD_LOGIC;
AC_ADR1 : out STD_LOGIC;
AC_GPIO0 : out STD_LOGIC; -- I2S MISO
AC_GPIO1 : in STD_LOGIC; -- I2S MOSI
AC_GPIO2 : in STD_LOGIC; -- I2S_bclk
AC_GPIO3 : in STD_LOGIC; -- I2S_LR
AC_MCLK : out STD_LOGIC;
AC_SCK : out STD_LOGIC;
AC_SDA_I : IN std_logic;
AC_SDA_O : OUT std_logic;
AC_SDA_T : OUT std_logic;
--AC_SDA : inout STD_LOGIC;
hphone_l : in std_logic_vector(23 downto 0);
hphone_r : in std_logic_vector(23 downto 0);
line_in_l : out std_logic_vector(23 downto 0);
line_in_r : out std_logic_vector(23 downto 0);
new_sample: out std_logic;
sw : in std_logic_vector(1 downto 0);
active : out std_logic_vector(1 downto 0)
);
end adau1761_izedboard;
architecture Behavioral of adau1761_izedboard is
COMPONENT i2c
PORT(
clk : IN std_logic;
i2c_sda_i : IN std_logic;
i2c_sda_o : OUT std_logic;
i2c_sda_t : OUT std_logic;
i2c_scl : OUT std_logic;
sw : in std_logic_vector(1 downto 0);
active : out std_logic_vector(1 downto 0));
END COMPONENT;
COMPONENT ADAU1761_interface
PORT(
clk_48 : IN std_logic;
codec_master_clk : OUT std_logic
);
END COMPONENT;
COMPONENT i2s_bit_clock
PORT(
clk_48 : IN std_logic;
pulse_per_bit : OUT std_logic;
i2s_clk : OUT std_logic
);
END COMPONENT;
component clocking
port(
CLK_100 : in std_logic;
CLK_48 : out std_logic;
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
COMPONENT audio_signal
PORT(
clk : IN std_logic;
sample_taken : IN std_logic;
audio_l : OUT std_logic_vector(15 downto 0);
audio_r : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT i2s_data_interface
PORT(
clk : IN std_logic;
audio_l_in : IN std_logic_vector(23 downto 0);
audio_r_in : IN std_logic_vector(23 downto 0);
i2s_bclk : IN std_logic;
i2s_lr : IN std_logic;
audio_l_out : OUT std_logic_vector(23 downto 0);
audio_r_out : OUT std_logic_vector(23 downto 0);
new_sample : OUT std_logic;
i2s_d_out : OUT std_logic;
i2s_d_in : IN std_logic
);
END COMPONENT;
signal audio_l : std_logic_vector(15 downto 0);
signal audio_r : std_logic_vector(15 downto 0);
signal codec_master_clk : std_logic;
signal i2c_scl : std_logic;
signal i2c_sda_i : std_logic;
signal i2c_sda_o : std_logic;
signal i2c_sda_t : std_logic;
signal i2s_mosi : std_logic;
signal i2s_miso : std_logic;
signal i2s_bclk : std_logic;
signal i2s_lr : std_logic;
begin
AC_ADR0 <= '1';
AC_ADR1 <= '1';
AC_GPIO0 <= i2s_MISO;
i2s_MOSI <= AC_GPIO1;
i2s_bclk <= AC_GPIO2;
i2s_lr <= AC_GPIO3;
AC_MCLK <= codec_master_clk;
AC_SCK <= i2c_scl;
--i_i2s_sda_obuf : IOBUF
-- port map (
-- IO => AC_SDA, -- Buffer inout port (connect directly to top-level port)
-- O => i2c_sda_i, -- Buffer output (to fabric)
-- I => i2c_sda_o, -- Buffer input (from fabric)
-- T => i2c_sda_t -- 3-state enable input, high=input, low=output
-- );
--
Inst_i2c: i2c PORT MAP(
clk => CLK_48,
i2c_sda_i => AC_SDA_I,
i2c_sda_o => AC_SDA_O,
i2c_sda_t => AC_SDA_T,
i2c_scl => i2c_scl,
sw => sw,
active => active
);
i_ADAU1761_interface: ADAU1761_interface PORT MAP(
clk_48 => clk_48 ,
codec_master_clk => codec_master_clk
);
Inst_i2s_data_interface: i2s_data_interface PORT MAP(
clk => clk_48,
audio_l_out => line_in_l,
audio_r_out => line_in_r,
audio_l_in => hphone_l,
audio_r_in => hphone_r,
new_sample => new_sample,
i2s_bclk => i2s_bclk,
i2s_d_out => i2s_MISO,
i2s_d_in => i2s_MOSI,
i2s_lr => i2s_lr
);
end Behavioral; | mit | 7564557681ca97a75690e4f12ba085ad | 0.517583 | 2.927811 | false | false | false | false |
pgavin/carpe | hdl/cpu/l1mem/data/cache/replace/none/cpu_l1mem_data_cache_replace_none-rtl.vhdl | 1 | 1,483 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library util;
use util.types_pkg.all;
architecture rtl of cpu_l1mem_data_cache_replace_none is
begin
cpu_l1mem_data_cache_replace_none_ctrl_out <= (
rway => (0 => '1')
);
cpu_l1mem_data_cache_replace_none_dp_out <= (
rstate => ""
);
end;
| apache-2.0 | 0e5fcadea9559eaad81d30eef3567875 | 0.492245 | 4.910596 | false | false | false | false |
loa-org/loa-hdl | modules/signalprocessing/hdl/goertzel.vhd | 2 | 5,818 | -------------------------------------------------------------------------------
-- Title : Fixed point implementation of Goertzel's Algorithm
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Fixed point implementation of Goertzel's Algorithm to detect a
-- fixed frequency in an analog signal. This does not implement the calculation
-- of the magnitude of the signal at the end of one block.
-- Mind overflows!
-- This implementation only calulates one channel and one frequency. For each
-- channel and each frequency this needs another multiplier. So this is not
-- used any more.
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.signalprocessing_pkg.all;
-------------------------------------------------------------------------------
entity goertzel is
generic (
-- Width of ADC input
-- Due to overflow prevention: Not as wide as the internal width of
-- calculations.
INPUT_WIDTH : natural := 14;
-- Width of internal calculations
-- Remember that internal multiplier are 18 bits wide (in Xilinx Spartan)
CALC_WIDTH : natural := 18;
-- Fixed point data format
Q : natural := 13;
-- Number of samples used to detect a frequency.
-- After SAMPLES samples new goertzel values are available.
SAMPLES : natural := 250
);
port (
coef_p : in unsigned(CALC_WIDTH-1 downto 0);
start_p : in std_logic; -- clock enable, is high when new value
-- from ADC is available.
adc_value_p : in signed(INPUT_WIDTH-1 downto 0);
result_p : out goertzel_result_type;
done_p : out std_logic; -- clock enable outut, is high when new
-- result was generated
clk : in std_logic
);
end goertzel;
architecture behavioural of goertzel is
----------------------------------------------------------------------------
-- Types
----------------------------------------------------------------------------
type goertzel_state_type is (
IDLE,
CALC1
);
type goertzel_type is record
state : goertzel_state_type;
done : std_logic;
delay0 : signed(CALC_WIDTH-1 downto 0);
delay1 : signed(CALC_WIDTH-1 downto 0);
delay2 : signed(CALC_WIDTH-1 downto 0);
result : goertzel_result_type;
sample_count : natural;
end record;
----------------------------------------------------------------------------
-- Internal signals
----------------------------------------------------------------------------
signal r, rin : goertzel_type := (
state => IDLE,
sample_count => 1,
done => '0',
delay0 => (others => '0'),
delay1 => (others => '0'),
delay2 => (others => '0'),
result => (others => (others => '0'))
);
begin -- behavioural
----------------------------------------------------------------------------
-- Mapping of signals
----------------------------------------------------------------------------
done_p <= r.done;
result_p <= r.result;
----------------------------------------------------------------------------
-- Sequential part of FSM
----------------------------------------------------------------------------
seq_proc : process (clk)
begin -- process seq_proc
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
----------------------------------------------------------------------------
-- Transitions and actions of FSM
----------------------------------------------------------------------------
comb_proc : process (adc_value_p, coef_p, r, rin, start_p)
variable v : goertzel_type;
variable prod1 : signed(2*CALC_WIDTH-1 downto 0) := (others => '0');
variable prod1_sc : signed(CALC_WIDTH-1 downto 0) := (others => '0');
variable coef : signed(CALC_WIDTH-1 downto 0);
begin -- process comb_proc
v := r;
coef := signed(coef_p);
case r.state is
when IDLE =>
v.done := '0';
if start_p = '1' then
v.state := CALC1;
-- prod1 := (self.history[1] * coef);
prod1 := r.delay1 * coef;
prod1_sc := prod1((Q + CALC_WIDTH - 1) downto Q);
-- self.history[0] = float(self.input.get())/(2**self.Q) + prod1 - self.history[2]
v.delay0 := adc_value_p + prod1_sc - r.delay2;
-- remember old values
v.delay1 := v.delay0;
v.delay2 := r.delay1;
if r.sample_count = SAMPLES then
v.sample_count := 0;
-- store results of current packet, only the upper 16 bits
-- for STM.
v.result(0) := v.delay1;
v.result(1) := v.delay2;
v.done := '1';
-- reset delay registers
v.delay1 := (others => '0');
v.delay2 := (others => '0');
else
v.sample_count := r.sample_count + 1;
end if;
end if;
when CALC1 =>
v.state := IDLE;
end case;
rin <= v;
end process comb_proc;
end behavioural;
| bsd-3-clause | 20c14761b799445ce75eae44c9746dcd | 0.41595 | 4.864548 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/vga_sync_ref/vga_sync_ref.sim/sim_1/impl/func/vga_sync_func_impl.vhd | 2 | 116,924 | -- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
-- Date : Wed Mar 09 00:15:18 2016
-- Host : GilaMonster running 64-bit major release (build 9200)
-- Command : write_vhdl -mode funcsim -nolib -force -file
-- D:/Users/Rob/Documents/Class/ECEC662/video_processing_ip/vga_sync/vga_sync.sim/sim_1/impl/func/vga_sync_func_impl.vhd
-- Design : vga_sync
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vga_sync is
port (
clk_25 : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of vga_sync : entity is true;
attribute ECO_CHECKSUM : string;
attribute ECO_CHECKSUM of vga_sync : entity is "1cca350c";
attribute H_BACK_DELAY : integer;
attribute H_BACK_DELAY of vga_sync : entity is 48;
attribute H_FRONT_DELAY : integer;
attribute H_FRONT_DELAY of vga_sync : entity is 16;
attribute H_RETRACE_DELAY : integer;
attribute H_RETRACE_DELAY of vga_sync : entity is 96;
attribute H_SIZE : integer;
attribute H_SIZE of vga_sync : entity is 640;
attribute V_BACK_DELAY : integer;
attribute V_BACK_DELAY of vga_sync : entity is 33;
attribute V_FRONT_DELAY : integer;
attribute V_FRONT_DELAY of vga_sync : entity is 10;
attribute V_RETRACE_DELAY : integer;
attribute V_RETRACE_DELAY of vga_sync : entity is 2;
attribute V_SIZE : integer;
attribute V_SIZE of vga_sync : entity is 480;
end vga_sync;
architecture STRUCTURE of vga_sync is
signal active_OBUF : STD_LOGIC;
signal active_i_1_n_0 : STD_LOGIC;
signal active_i_2_n_0 : STD_LOGIC;
signal clk_25_IBUF : STD_LOGIC;
signal clk_25_IBUF_BUFG : STD_LOGIC;
signal hcount1 : STD_LOGIC;
signal hcount18_in : STD_LOGIC;
signal \hcount[0]_i_104_n_0\ : STD_LOGIC;
signal \hcount[0]_i_105_n_0\ : STD_LOGIC;
signal \hcount[0]_i_106_n_0\ : STD_LOGIC;
signal \hcount[0]_i_107_n_0\ : STD_LOGIC;
signal \hcount[0]_i_109_n_0\ : STD_LOGIC;
signal \hcount[0]_i_110_n_0\ : STD_LOGIC;
signal \hcount[0]_i_111_n_0\ : STD_LOGIC;
signal \hcount[0]_i_112_n_0\ : STD_LOGIC;
signal \hcount[0]_i_118_n_0\ : STD_LOGIC;
signal \hcount[0]_i_119_n_0\ : STD_LOGIC;
signal \hcount[0]_i_11_n_0\ : STD_LOGIC;
signal \hcount[0]_i_120_n_0\ : STD_LOGIC;
signal \hcount[0]_i_121_n_0\ : STD_LOGIC;
signal \hcount[0]_i_122_n_0\ : STD_LOGIC;
signal \hcount[0]_i_123_n_0\ : STD_LOGIC;
signal \hcount[0]_i_124_n_0\ : STD_LOGIC;
signal \hcount[0]_i_131_n_0\ : STD_LOGIC;
signal \hcount[0]_i_132_n_0\ : STD_LOGIC;
signal \hcount[0]_i_133_n_0\ : STD_LOGIC;
signal \hcount[0]_i_134_n_0\ : STD_LOGIC;
signal \hcount[0]_i_136_n_0\ : STD_LOGIC;
signal \hcount[0]_i_137_n_0\ : STD_LOGIC;
signal \hcount[0]_i_139_n_0\ : STD_LOGIC;
signal \hcount[0]_i_13_n_0\ : STD_LOGIC;
signal \hcount[0]_i_140_n_0\ : STD_LOGIC;
signal \hcount[0]_i_141_n_0\ : STD_LOGIC;
signal \hcount[0]_i_142_n_0\ : STD_LOGIC;
signal \hcount[0]_i_14_n_0\ : STD_LOGIC;
signal \hcount[0]_i_153_n_0\ : STD_LOGIC;
signal \hcount[0]_i_154_n_0\ : STD_LOGIC;
signal \hcount[0]_i_155_n_0\ : STD_LOGIC;
signal \hcount[0]_i_156_n_0\ : STD_LOGIC;
signal \hcount[0]_i_157_n_0\ : STD_LOGIC;
signal \hcount[0]_i_158_n_0\ : STD_LOGIC;
signal \hcount[0]_i_159_n_0\ : STD_LOGIC;
signal \hcount[0]_i_15_n_0\ : STD_LOGIC;
signal \hcount[0]_i_160_n_0\ : STD_LOGIC;
signal \hcount[0]_i_161_n_0\ : STD_LOGIC;
signal \hcount[0]_i_162_n_0\ : STD_LOGIC;
signal \hcount[0]_i_163_n_0\ : STD_LOGIC;
signal \hcount[0]_i_164_n_0\ : STD_LOGIC;
signal \hcount[0]_i_165_n_0\ : STD_LOGIC;
signal \hcount[0]_i_166_n_0\ : STD_LOGIC;
signal \hcount[0]_i_167_n_0\ : STD_LOGIC;
signal \hcount[0]_i_168_n_0\ : STD_LOGIC;
signal \hcount[0]_i_169_n_0\ : STD_LOGIC;
signal \hcount[0]_i_16_n_0\ : STD_LOGIC;
signal \hcount[0]_i_170_n_0\ : STD_LOGIC;
signal \hcount[0]_i_171_n_0\ : STD_LOGIC;
signal \hcount[0]_i_172_n_0\ : STD_LOGIC;
signal \hcount[0]_i_173_n_0\ : STD_LOGIC;
signal \hcount[0]_i_17_n_0\ : STD_LOGIC;
signal \hcount[0]_i_18_n_0\ : STD_LOGIC;
signal \hcount[0]_i_19_n_0\ : STD_LOGIC;
signal \hcount[0]_i_1_n_0\ : STD_LOGIC;
signal \hcount[0]_i_20_n_0\ : STD_LOGIC;
signal \hcount[0]_i_23_n_0\ : STD_LOGIC;
signal \hcount[0]_i_24_n_0\ : STD_LOGIC;
signal \hcount[0]_i_27_n_0\ : STD_LOGIC;
signal \hcount[0]_i_29_n_0\ : STD_LOGIC;
signal \hcount[0]_i_30_n_0\ : STD_LOGIC;
signal \hcount[0]_i_31_n_0\ : STD_LOGIC;
signal \hcount[0]_i_32_n_0\ : STD_LOGIC;
signal \hcount[0]_i_33_n_0\ : STD_LOGIC;
signal \hcount[0]_i_34_n_0\ : STD_LOGIC;
signal \hcount[0]_i_35_n_0\ : STD_LOGIC;
signal \hcount[0]_i_36_n_0\ : STD_LOGIC;
signal \hcount[0]_i_38_n_0\ : STD_LOGIC;
signal \hcount[0]_i_39_n_0\ : STD_LOGIC;
signal \hcount[0]_i_40_n_0\ : STD_LOGIC;
signal \hcount[0]_i_42_n_0\ : STD_LOGIC;
signal \hcount[0]_i_43_n_0\ : STD_LOGIC;
signal \hcount[0]_i_44_n_0\ : STD_LOGIC;
signal \hcount[0]_i_45_n_0\ : STD_LOGIC;
signal \hcount[0]_i_46_n_0\ : STD_LOGIC;
signal \hcount[0]_i_47_n_0\ : STD_LOGIC;
signal \hcount[0]_i_48_n_0\ : STD_LOGIC;
signal \hcount[0]_i_49_n_0\ : STD_LOGIC;
signal \hcount[0]_i_53_n_0\ : STD_LOGIC;
signal \hcount[0]_i_54_n_0\ : STD_LOGIC;
signal \hcount[0]_i_55_n_0\ : STD_LOGIC;
signal \hcount[0]_i_56_n_0\ : STD_LOGIC;
signal \hcount[0]_i_61_n_0\ : STD_LOGIC;
signal \hcount[0]_i_62_n_0\ : STD_LOGIC;
signal \hcount[0]_i_63_n_0\ : STD_LOGIC;
signal \hcount[0]_i_64_n_0\ : STD_LOGIC;
signal \hcount[0]_i_70_n_0\ : STD_LOGIC;
signal \hcount[0]_i_71_n_0\ : STD_LOGIC;
signal \hcount[0]_i_72_n_0\ : STD_LOGIC;
signal \hcount[0]_i_73_n_0\ : STD_LOGIC;
signal \hcount[0]_i_74_n_0\ : STD_LOGIC;
signal \hcount[0]_i_75_n_0\ : STD_LOGIC;
signal \hcount[0]_i_76_n_0\ : STD_LOGIC;
signal \hcount[0]_i_77_n_0\ : STD_LOGIC;
signal \hcount[0]_i_80_n_0\ : STD_LOGIC;
signal \hcount[0]_i_81_n_0\ : STD_LOGIC;
signal \hcount[0]_i_82_n_0\ : STD_LOGIC;
signal \hcount[0]_i_83_n_0\ : STD_LOGIC;
signal \hcount[0]_i_85_n_0\ : STD_LOGIC;
signal \hcount[0]_i_86_n_0\ : STD_LOGIC;
signal \hcount[0]_i_87_n_0\ : STD_LOGIC;
signal \hcount[0]_i_88_n_0\ : STD_LOGIC;
signal \hcount[0]_i_89_n_0\ : STD_LOGIC;
signal \hcount[0]_i_90_n_0\ : STD_LOGIC;
signal \hcount[0]_i_91_n_0\ : STD_LOGIC;
signal \hcount[0]_i_92_n_0\ : STD_LOGIC;
signal hcount_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \hcount_reg[0]_i_103_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_108_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_117_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_125_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_125_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_125_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_125_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_125_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_126_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_126_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_126_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_126_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_126_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_12_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_135_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_135_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_135_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_135_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_135_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_138_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_138_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_138_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_138_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_138_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_143_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_143_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_143_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_143_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_143_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_144_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_144_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_144_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_144_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_144_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_174_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_174_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_174_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_174_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_174_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_183_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_183_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_183_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_183_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_183_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_21_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_22_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_22_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_22_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_25_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_26_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_26_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_26_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_28_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_2_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_2_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_2_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_2_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_2_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_37_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_3_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_41_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_4_n_2\ : STD_LOGIC;
signal \hcount_reg[0]_i_50_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_50_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_50_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_50_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_50_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_51_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_51_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_51_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_51_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_51_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_52_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_60_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_65_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_65_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_65_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_65_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_65_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_69_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_78_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_78_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_78_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_78_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_78_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_79_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_7_n_1\ : STD_LOGIC;
signal \hcount_reg[0]_i_84_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_93_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_93_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_93_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_93_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_93_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_94_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_94_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_94_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_94_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_94_n_7\ : STD_LOGIC;
signal \hcount_reg[12]_i_1_n_0\ : STD_LOGIC;
signal \hcount_reg[12]_i_1_n_4\ : STD_LOGIC;
signal \hcount_reg[12]_i_1_n_5\ : STD_LOGIC;
signal \hcount_reg[12]_i_1_n_6\ : STD_LOGIC;
signal \hcount_reg[12]_i_1_n_7\ : STD_LOGIC;
signal \hcount_reg[16]_i_1_n_0\ : STD_LOGIC;
signal \hcount_reg[16]_i_1_n_4\ : STD_LOGIC;
signal \hcount_reg[16]_i_1_n_5\ : STD_LOGIC;
signal \hcount_reg[16]_i_1_n_6\ : STD_LOGIC;
signal \hcount_reg[16]_i_1_n_7\ : STD_LOGIC;
signal \hcount_reg[20]_i_1_n_0\ : STD_LOGIC;
signal \hcount_reg[20]_i_1_n_4\ : STD_LOGIC;
signal \hcount_reg[20]_i_1_n_5\ : STD_LOGIC;
signal \hcount_reg[20]_i_1_n_6\ : STD_LOGIC;
signal \hcount_reg[20]_i_1_n_7\ : STD_LOGIC;
signal \hcount_reg[24]_i_1_n_0\ : STD_LOGIC;
signal \hcount_reg[24]_i_1_n_4\ : STD_LOGIC;
signal \hcount_reg[24]_i_1_n_5\ : STD_LOGIC;
signal \hcount_reg[24]_i_1_n_6\ : STD_LOGIC;
signal \hcount_reg[24]_i_1_n_7\ : STD_LOGIC;
signal \hcount_reg[28]_i_1_n_4\ : STD_LOGIC;
signal \hcount_reg[28]_i_1_n_5\ : STD_LOGIC;
signal \hcount_reg[28]_i_1_n_6\ : STD_LOGIC;
signal \hcount_reg[28]_i_1_n_7\ : STD_LOGIC;
signal \hcount_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \hcount_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \hcount_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \hcount_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \hcount_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \hcount_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \hcount_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \hcount_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \hcount_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \hcount_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \hcount_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 10 );
signal hsync_OBUF : STD_LOGIC;
signal hsync_i_1_n_0 : STD_LOGIC;
signal hsync_i_2_n_0 : STD_LOGIC;
signal hsync_i_3_n_0 : STD_LOGIC;
signal hsync_i_4_n_0 : STD_LOGIC;
signal hsync_i_5_n_0 : STD_LOGIC;
signal hsync_i_6_n_0 : STD_LOGIC;
signal hsync_i_7_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal rst_IBUF : STD_LOGIC;
signal \vcount[0]_i_1_n_0\ : STD_LOGIC;
signal \vcount[0]_i_2_n_0\ : STD_LOGIC;
signal \vcount[0]_i_7_n_0\ : STD_LOGIC;
signal vcount_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \vcount_reg[0]_i_3_n_0\ : STD_LOGIC;
signal \vcount_reg[0]_i_3_n_4\ : STD_LOGIC;
signal \vcount_reg[0]_i_3_n_5\ : STD_LOGIC;
signal \vcount_reg[0]_i_3_n_6\ : STD_LOGIC;
signal \vcount_reg[0]_i_3_n_7\ : STD_LOGIC;
signal \vcount_reg[12]_i_1_n_0\ : STD_LOGIC;
signal \vcount_reg[12]_i_1_n_4\ : STD_LOGIC;
signal \vcount_reg[12]_i_1_n_5\ : STD_LOGIC;
signal \vcount_reg[12]_i_1_n_6\ : STD_LOGIC;
signal \vcount_reg[12]_i_1_n_7\ : STD_LOGIC;
signal \vcount_reg[16]_i_1_n_0\ : STD_LOGIC;
signal \vcount_reg[16]_i_1_n_4\ : STD_LOGIC;
signal \vcount_reg[16]_i_1_n_5\ : STD_LOGIC;
signal \vcount_reg[16]_i_1_n_6\ : STD_LOGIC;
signal \vcount_reg[16]_i_1_n_7\ : STD_LOGIC;
signal \vcount_reg[20]_i_1_n_0\ : STD_LOGIC;
signal \vcount_reg[20]_i_1_n_4\ : STD_LOGIC;
signal \vcount_reg[20]_i_1_n_5\ : STD_LOGIC;
signal \vcount_reg[20]_i_1_n_6\ : STD_LOGIC;
signal \vcount_reg[20]_i_1_n_7\ : STD_LOGIC;
signal \vcount_reg[24]_i_1_n_0\ : STD_LOGIC;
signal \vcount_reg[24]_i_1_n_4\ : STD_LOGIC;
signal \vcount_reg[24]_i_1_n_5\ : STD_LOGIC;
signal \vcount_reg[24]_i_1_n_6\ : STD_LOGIC;
signal \vcount_reg[24]_i_1_n_7\ : STD_LOGIC;
signal \vcount_reg[28]_i_1_n_4\ : STD_LOGIC;
signal \vcount_reg[28]_i_1_n_5\ : STD_LOGIC;
signal \vcount_reg[28]_i_1_n_6\ : STD_LOGIC;
signal \vcount_reg[28]_i_1_n_7\ : STD_LOGIC;
signal \vcount_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \vcount_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \vcount_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \vcount_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \vcount_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \vcount_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \vcount_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \vcount_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \vcount_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \vcount_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \vcount_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 10 );
signal vsync_OBUF : STD_LOGIC;
signal vsync_i_1_n_0 : STD_LOGIC;
signal vsync_i_2_n_0 : STD_LOGIC;
signal vsync_i_3_n_0 : STD_LOGIC;
signal vsync_i_4_n_0 : STD_LOGIC;
signal vsync_i_5_n_0 : STD_LOGIC;
signal vsync_i_6_n_0 : STD_LOGIC;
signal vsync_i_7_n_0 : STD_LOGIC;
signal \xaddr[9]_i_10_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_12_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_13_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_14_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_15_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_16_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_17_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_18_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_19_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_1_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_20_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_21_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_5_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_7_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_8_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_9_n_0\ : STD_LOGIC;
signal xaddr_OBUF : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \xaddr_reg[9]_i_11_n_0\ : STD_LOGIC;
signal \xaddr_reg[9]_i_3_n_3\ : STD_LOGIC;
signal \xaddr_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \xaddr_reg[9]_i_6_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_10_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_12_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_13_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_14_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_15_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_16_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_17_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_18_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_19_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_1_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_20_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_21_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_22_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_4_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_5_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_7_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_8_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_9_n_0\ : STD_LOGIC;
signal yaddr_OBUF : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \yaddr_reg[9]_i_11_n_0\ : STD_LOGIC;
signal \yaddr_reg[9]_i_2_n_2\ : STD_LOGIC;
signal \yaddr_reg[9]_i_3_n_0\ : STD_LOGIC;
signal \yaddr_reg[9]_i_6_n_0\ : STD_LOGIC;
signal \NLW_hcount_reg[0]_i_103_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_103_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_108_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_108_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_117_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_117_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_12_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_125_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_126_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_135_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_138_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_143_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_144_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_174_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_183_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_21_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_22_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_22_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_hcount_reg[0]_i_25_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_25_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_26_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_26_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_hcount_reg[0]_i_28_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_28_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_37_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_37_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_41_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_41_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_5_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_hcount_reg[0]_i_5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_50_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_51_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_52_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_52_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_60_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_60_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_65_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_69_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_69_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_7_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_7_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_78_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_79_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_79_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_84_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_84_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_93_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_94_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[20]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[24]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[4]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_vcount_reg[0]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_vcount_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_vcount_reg[16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_vcount_reg[20]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_vcount_reg[24]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_vcount_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_vcount_reg[4]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_vcount_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_xaddr_reg[9]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_xaddr_reg[9]_i_11_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_xaddr_reg[9]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_xaddr_reg[9]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_xaddr_reg[9]_i_4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_xaddr_reg[9]_i_4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_xaddr_reg[9]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_xaddr_reg[9]_i_6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_yaddr_reg[9]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_yaddr_reg[9]_i_11_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_yaddr_reg[9]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_yaddr_reg[9]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_yaddr_reg[9]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_yaddr_reg[9]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_yaddr_reg[9]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_yaddr_reg[9]_i_6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
active_OBUF_inst: unisim.vcomponents.OBUF
port map (
I => active_OBUF,
O => active
);
active_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAFFFFAAAA00EA"
)
port map (
I0 => active_OBUF,
I1 => hcount1,
I2 => active_i_2_n_0,
I3 => \hcount_reg[0]_i_7_n_1\,
I4 => rst_IBUF,
I5 => hcount18_in,
O => active_i_1_n_0
);
active_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_3_n_0\,
I1 => \hcount_reg[0]_i_4_n_2\,
O => active_i_2_n_0
);
active_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => active_i_1_n_0,
Q => active_OBUF,
R => '0'
);
clk_25_IBUF_BUFG_inst: unisim.vcomponents.BUFG
port map (
I => clk_25_IBUF,
O => clk_25_IBUF_BUFG
);
clk_25_IBUF_inst: unisim.vcomponents.IBUF
port map (
I => clk_25,
O => clk_25_IBUF
);
\hcount[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00000E00"
)
port map (
I0 => \hcount_reg[0]_i_3_n_0\,
I1 => \hcount_reg[0]_i_4_n_2\,
I2 => hcount18_in,
I3 => hcount1,
I4 => \hcount_reg[0]_i_7_n_1\,
I5 => rst_IBUF,
O => \hcount[0]_i_1_n_0\
);
\hcount[0]_i_104\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_93_n_6\,
I1 => \hcount_reg[0]_i_93_n_5\,
O => \hcount[0]_i_104_n_0\
);
\hcount[0]_i_105\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_94_n_4\,
I1 => \hcount_reg[0]_i_93_n_7\,
O => \hcount[0]_i_105_n_0\
);
\hcount[0]_i_106\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_94_n_6\,
I1 => \hcount_reg[0]_i_94_n_5\,
O => \hcount[0]_i_106_n_0\
);
\hcount[0]_i_107\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_143_n_4\,
I1 => \hcount_reg[0]_i_94_n_7\,
O => \hcount[0]_i_107_n_0\
);
\hcount[0]_i_109\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_125_n_4\,
I1 => \hcount_reg[0]_i_78_n_7\,
O => \hcount[0]_i_109_n_0\
);
\hcount[0]_i_11\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => hcount_reg(0),
O => \hcount[0]_i_11_n_0\
);
\hcount[0]_i_110\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_125_n_5\,
I1 => \hcount_reg[0]_i_125_n_6\,
O => \hcount[0]_i_110_n_0\
);
\hcount[0]_i_111\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_125_n_7\,
I1 => \hcount_reg[0]_i_126_n_4\,
O => \hcount[0]_i_111_n_0\
);
\hcount[0]_i_112\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_126_n_6\,
I1 => \hcount_reg[0]_i_126_n_5\,
O => \hcount[0]_i_112_n_0\
);
\hcount[0]_i_118\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_126_n_6\,
I1 => \hcount_reg[0]_i_126_n_5\,
O => \hcount[0]_i_118_n_0\
);
\hcount[0]_i_119\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_135_n_4\,
I1 => \hcount_reg[0]_i_126_n_7\,
O => \hcount[0]_i_119_n_0\
);
\hcount[0]_i_120\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_135_n_6\,
I1 => \hcount_reg[0]_i_135_n_5\,
O => \hcount[0]_i_120_n_0\
);
\hcount[0]_i_121\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_126_n_6\,
I1 => \hcount_reg[0]_i_126_n_5\,
O => \hcount[0]_i_121_n_0\
);
\hcount[0]_i_122\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_126_n_7\,
I1 => \hcount_reg[0]_i_135_n_4\,
O => \hcount[0]_i_122_n_0\
);
\hcount[0]_i_123\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_135_n_5\,
I1 => \hcount_reg[0]_i_135_n_6\,
O => \hcount[0]_i_123_n_0\
);
\hcount[0]_i_124\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \hcount_reg[0]_i_174_n_4\,
I1 => \hcount_reg[0]_i_135_n_7\,
O => \hcount[0]_i_124_n_0\
);
\hcount[0]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \hcount_reg[0]_i_22_n_6\,
I1 => \hcount_reg[0]_i_22_n_5\,
O => \hcount[0]_i_13_n_0\
);
\hcount[0]_i_131\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \hcount_reg[0]_i_135_n_7\,
I1 => \hcount_reg[0]_i_135_n_5\,
I2 => \hcount_reg[0]_i_135_n_6\,
O => \hcount[0]_i_131_n_0\
);
\hcount[0]_i_132\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \hcount_reg[0]_i_174_n_4\,
I1 => \hcount_reg[0]_i_174_n_5\,
I2 => \hcount_reg[0]_i_174_n_6\,
O => \hcount[0]_i_132_n_0\
);
\hcount[0]_i_133\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \hcount_reg[0]_i_174_n_7\,
I1 => \hcount_reg[0]_i_183_n_4\,
I2 => \hcount_reg[0]_i_183_n_5\,
O => \hcount[0]_i_133_n_0\
);
\hcount[0]_i_134\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => hcount_reg(0),
I1 => \hcount_reg[0]_i_183_n_7\,
I2 => \hcount_reg[0]_i_183_n_6\,
O => \hcount[0]_i_134_n_0\
);
\hcount[0]_i_136\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_144_n_6\,
I1 => \hcount_reg[0]_i_144_n_5\,
O => \hcount[0]_i_136_n_0\
);
\hcount[0]_i_137\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_138_n_4\,
I1 => \hcount_reg[0]_i_144_n_7\,
O => \hcount[0]_i_137_n_0\
);
\hcount[0]_i_139\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_144_n_6\,
I1 => \hcount_reg[0]_i_144_n_5\,
O => \hcount[0]_i_139_n_0\
);
\hcount[0]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_50_n_4\,
I1 => \hcount_reg[0]_i_22_n_7\,
O => \hcount[0]_i_14_n_0\
);
\hcount[0]_i_140\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_138_n_4\,
I1 => \hcount_reg[0]_i_144_n_7\,
O => \hcount[0]_i_140_n_0\
);
\hcount[0]_i_141\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \hcount_reg[0]_i_138_n_6\,
I1 => \hcount_reg[0]_i_138_n_5\,
O => \hcount[0]_i_141_n_0\
);
\hcount[0]_i_142\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => vcount_reg(0),
I1 => \hcount_reg[0]_i_138_n_7\,
O => \hcount[0]_i_142_n_0\
);
\hcount[0]_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_50_n_6\,
I1 => \hcount_reg[0]_i_50_n_5\,
O => \hcount[0]_i_15_n_0\
);
\hcount[0]_i_153\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_144_n_4\,
I1 => \hcount_reg[0]_i_143_n_7\,
O => \hcount[0]_i_153_n_0\
);
\hcount[0]_i_154\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \hcount_reg[0]_i_144_n_6\,
I1 => \hcount_reg[0]_i_144_n_5\,
O => \hcount[0]_i_154_n_0\
);
\hcount[0]_i_155\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_144_n_7\,
O => \hcount[0]_i_155_n_0\
);
\hcount[0]_i_156\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_143_n_6\,
I1 => \hcount_reg[0]_i_143_n_5\,
O => \hcount[0]_i_156_n_0\
);
\hcount[0]_i_157\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \hcount_reg[0]_i_144_n_4\,
I1 => \hcount_reg[0]_i_143_n_7\,
O => \hcount[0]_i_157_n_0\
);
\hcount[0]_i_158\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \hcount_reg[0]_i_144_n_6\,
I1 => \hcount_reg[0]_i_144_n_5\,
O => \hcount[0]_i_158_n_0\
);
\hcount[0]_i_159\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \hcount_reg[0]_i_144_n_7\,
I1 => \hcount_reg[0]_i_138_n_4\,
O => \hcount[0]_i_159_n_0\
);
\hcount[0]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_51_n_4\,
I1 => \hcount_reg[0]_i_50_n_7\,
O => \hcount[0]_i_16_n_0\
);
\hcount[0]_i_160\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_135_n_7\,
O => \hcount[0]_i_160_n_0\
);
\hcount[0]_i_161\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_174_n_5\,
O => \hcount[0]_i_161_n_0\
);
\hcount[0]_i_162\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_126_n_7\,
I1 => \hcount_reg[0]_i_135_n_4\,
O => \hcount[0]_i_162_n_0\
);
\hcount[0]_i_163\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_135_n_5\,
I1 => \hcount_reg[0]_i_135_n_6\,
O => \hcount[0]_i_163_n_0\
);
\hcount[0]_i_164\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \hcount_reg[0]_i_135_n_7\,
I1 => \hcount_reg[0]_i_174_n_4\,
O => \hcount[0]_i_164_n_0\
);
\hcount[0]_i_165\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \hcount_reg[0]_i_174_n_5\,
I1 => \hcount_reg[0]_i_174_n_6\,
O => \hcount[0]_i_165_n_0\
);
\hcount[0]_i_166\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_174_n_6\,
I1 => \hcount_reg[0]_i_174_n_5\,
O => \hcount[0]_i_166_n_0\
);
\hcount[0]_i_167\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \hcount_reg[0]_i_183_n_4\,
I1 => \hcount_reg[0]_i_174_n_7\,
O => \hcount[0]_i_167_n_0\
);
\hcount[0]_i_168\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_183_n_6\,
I1 => \hcount_reg[0]_i_183_n_5\,
O => \hcount[0]_i_168_n_0\
);
\hcount[0]_i_169\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \hcount_reg[0]_i_183_n_7\,
I1 => hcount_reg(0),
O => \hcount[0]_i_169_n_0\
);
\hcount[0]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_22_n_6\,
I1 => \hcount_reg[0]_i_22_n_5\,
O => \hcount[0]_i_17_n_0\
);
\hcount[0]_i_170\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_174_n_6\,
I1 => \hcount_reg[0]_i_174_n_5\,
O => \hcount[0]_i_170_n_0\
);
\hcount[0]_i_171\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \hcount_reg[0]_i_174_n_7\,
I1 => \hcount_reg[0]_i_183_n_4\,
O => \hcount[0]_i_171_n_0\
);
\hcount[0]_i_172\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_183_n_6\,
I1 => \hcount_reg[0]_i_183_n_5\,
O => \hcount[0]_i_172_n_0\
);
\hcount[0]_i_173\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => hcount_reg(0),
I1 => \hcount_reg[0]_i_183_n_7\,
O => \hcount[0]_i_173_n_0\
);
\hcount[0]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_50_n_4\,
I1 => \hcount_reg[0]_i_22_n_7\,
O => \hcount[0]_i_18_n_0\
);
\hcount[0]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_50_n_6\,
I1 => \hcount_reg[0]_i_50_n_5\,
O => \hcount[0]_i_19_n_0\
);
\hcount[0]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_51_n_4\,
I1 => \hcount_reg[0]_i_50_n_7\,
O => \hcount[0]_i_20_n_0\
);
\hcount[0]_i_23\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_22_n_6\,
I1 => \hcount_reg[0]_i_22_n_5\,
O => \hcount[0]_i_23_n_0\
);
\hcount[0]_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_50_n_4\,
I1 => \hcount_reg[0]_i_22_n_7\,
O => \hcount[0]_i_24_n_0\
);
\hcount[0]_i_27\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_26_n_6\,
I1 => \hcount_reg[0]_i_26_n_5\,
O => \hcount[0]_i_27_n_0\
);
\hcount[0]_i_29\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \hcount_reg[0]_i_26_n_6\,
I1 => \hcount_reg[0]_i_26_n_5\,
O => \hcount[0]_i_29_n_0\
);
\hcount[0]_i_30\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_65_n_4\,
I1 => \hcount_reg[0]_i_26_n_7\,
O => \hcount[0]_i_30_n_0\
);
\hcount[0]_i_31\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_65_n_6\,
I1 => \hcount_reg[0]_i_65_n_5\,
O => \hcount[0]_i_31_n_0\
);
\hcount[0]_i_32\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_78_n_4\,
I1 => \hcount_reg[0]_i_65_n_7\,
O => \hcount[0]_i_32_n_0\
);
\hcount[0]_i_33\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_26_n_6\,
I1 => \hcount_reg[0]_i_26_n_5\,
O => \hcount[0]_i_33_n_0\
);
\hcount[0]_i_34\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_26_n_7\,
I1 => \hcount_reg[0]_i_65_n_4\,
O => \hcount[0]_i_34_n_0\
);
\hcount[0]_i_35\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_65_n_6\,
I1 => \hcount_reg[0]_i_65_n_5\,
O => \hcount[0]_i_35_n_0\
);
\hcount[0]_i_36\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_65_n_7\,
I1 => \hcount_reg[0]_i_78_n_4\,
O => \hcount[0]_i_36_n_0\
);
\hcount[0]_i_38\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_26_n_6\,
I1 => \hcount_reg[0]_i_26_n_5\,
O => \hcount[0]_i_38_n_0\
);
\hcount[0]_i_39\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \hcount_reg[0]_i_26_n_7\,
I1 => \hcount_reg[0]_i_65_n_4\,
I2 => \hcount_reg[0]_i_65_n_5\,
O => \hcount[0]_i_39_n_0\
);
\hcount[0]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \hcount_reg[0]_i_65_n_7\,
I1 => \hcount_reg[0]_i_78_n_4\,
I2 => \hcount_reg[0]_i_65_n_6\,
O => \hcount[0]_i_40_n_0\
);
\hcount[0]_i_42\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_51_n_6\,
I1 => \hcount_reg[0]_i_51_n_5\,
O => \hcount[0]_i_42_n_0\
);
\hcount[0]_i_43\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_93_n_4\,
I1 => \hcount_reg[0]_i_51_n_7\,
O => \hcount[0]_i_43_n_0\
);
\hcount[0]_i_44\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_93_n_6\,
I1 => \hcount_reg[0]_i_93_n_5\,
O => \hcount[0]_i_44_n_0\
);
\hcount[0]_i_45\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_94_n_4\,
I1 => \hcount_reg[0]_i_93_n_7\,
O => \hcount[0]_i_45_n_0\
);
\hcount[0]_i_46\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_51_n_6\,
I1 => \hcount_reg[0]_i_51_n_5\,
O => \hcount[0]_i_46_n_0\
);
\hcount[0]_i_47\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_93_n_4\,
I1 => \hcount_reg[0]_i_51_n_7\,
O => \hcount[0]_i_47_n_0\
);
\hcount[0]_i_48\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_93_n_6\,
I1 => \hcount_reg[0]_i_93_n_5\,
O => \hcount[0]_i_48_n_0\
);
\hcount[0]_i_49\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_94_n_4\,
I1 => \hcount_reg[0]_i_93_n_7\,
O => \hcount[0]_i_49_n_0\
);
\hcount[0]_i_53\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_50_n_6\,
I1 => \hcount_reg[0]_i_50_n_5\,
O => \hcount[0]_i_53_n_0\
);
\hcount[0]_i_54\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_51_n_4\,
I1 => \hcount_reg[0]_i_50_n_7\,
O => \hcount[0]_i_54_n_0\
);
\hcount[0]_i_55\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_51_n_6\,
I1 => \hcount_reg[0]_i_51_n_5\,
O => \hcount[0]_i_55_n_0\
);
\hcount[0]_i_56\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_93_n_4\,
I1 => \hcount_reg[0]_i_51_n_7\,
O => \hcount[0]_i_56_n_0\
);
\hcount[0]_i_61\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_26_n_7\,
I1 => \hcount_reg[0]_i_65_n_4\,
O => \hcount[0]_i_61_n_0\
);
\hcount[0]_i_62\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_65_n_6\,
I1 => \hcount_reg[0]_i_65_n_5\,
O => \hcount[0]_i_62_n_0\
);
\hcount[0]_i_63\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_65_n_7\,
I1 => \hcount_reg[0]_i_78_n_4\,
O => \hcount[0]_i_63_n_0\
);
\hcount[0]_i_64\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_78_n_5\,
I1 => \hcount_reg[0]_i_78_n_6\,
O => \hcount[0]_i_64_n_0\
);
\hcount[0]_i_70\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_78_n_6\,
I1 => \hcount_reg[0]_i_78_n_5\,
O => \hcount[0]_i_70_n_0\
);
\hcount[0]_i_71\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_125_n_4\,
I1 => \hcount_reg[0]_i_78_n_7\,
O => \hcount[0]_i_71_n_0\
);
\hcount[0]_i_72\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_125_n_6\,
I1 => \hcount_reg[0]_i_125_n_5\,
O => \hcount[0]_i_72_n_0\
);
\hcount[0]_i_73\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_126_n_4\,
I1 => \hcount_reg[0]_i_125_n_7\,
O => \hcount[0]_i_73_n_0\
);
\hcount[0]_i_74\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_78_n_5\,
I1 => \hcount_reg[0]_i_78_n_6\,
O => \hcount[0]_i_74_n_0\
);
\hcount[0]_i_75\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_125_n_4\,
I1 => \hcount_reg[0]_i_78_n_7\,
O => \hcount[0]_i_75_n_0\
);
\hcount[0]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_125_n_5\,
I1 => \hcount_reg[0]_i_125_n_6\,
O => \hcount[0]_i_76_n_0\
);
\hcount[0]_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_125_n_7\,
I1 => \hcount_reg[0]_i_126_n_4\,
O => \hcount[0]_i_77_n_0\
);
\hcount[0]_i_80\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \hcount_reg[0]_i_78_n_5\,
I1 => \hcount_reg[0]_i_78_n_6\,
I2 => \hcount_reg[0]_i_78_n_7\,
O => \hcount[0]_i_80_n_0\
);
\hcount[0]_i_81\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \hcount_reg[0]_i_125_n_5\,
I1 => \hcount_reg[0]_i_125_n_6\,
I2 => \hcount_reg[0]_i_125_n_4\,
O => \hcount[0]_i_81_n_0\
);
\hcount[0]_i_82\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \hcount_reg[0]_i_125_n_7\,
I1 => \hcount_reg[0]_i_126_n_4\,
I2 => \hcount_reg[0]_i_126_n_5\,
O => \hcount[0]_i_82_n_0\
);
\hcount[0]_i_83\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \hcount_reg[0]_i_126_n_7\,
I1 => \hcount_reg[0]_i_135_n_4\,
I2 => \hcount_reg[0]_i_126_n_6\,
O => \hcount[0]_i_83_n_0\
);
\hcount[0]_i_85\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_94_n_6\,
I1 => \hcount_reg[0]_i_94_n_5\,
O => \hcount[0]_i_85_n_0\
);
\hcount[0]_i_86\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_143_n_4\,
I1 => \hcount_reg[0]_i_94_n_7\,
O => \hcount[0]_i_86_n_0\
);
\hcount[0]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_143_n_6\,
I1 => \hcount_reg[0]_i_143_n_5\,
O => \hcount[0]_i_87_n_0\
);
\hcount[0]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \hcount_reg[0]_i_144_n_4\,
I1 => \hcount_reg[0]_i_143_n_7\,
O => \hcount[0]_i_88_n_0\
);
\hcount[0]_i_89\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_94_n_6\,
I1 => \hcount_reg[0]_i_94_n_5\,
O => \hcount[0]_i_89_n_0\
);
\hcount[0]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_143_n_4\,
I1 => \hcount_reg[0]_i_94_n_7\,
O => \hcount[0]_i_90_n_0\
);
\hcount[0]_i_91\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_143_n_6\,
I1 => \hcount_reg[0]_i_143_n_5\,
O => \hcount[0]_i_91_n_0\
);
\hcount[0]_i_92\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \hcount_reg[0]_i_143_n_7\,
I1 => \hcount_reg[0]_i_144_n_4\,
O => \hcount[0]_i_92_n_0\
);
\hcount_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[0]_i_2_n_7\,
Q => hcount_reg(0),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[0]_i_103\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \hcount_reg[0]_i_103_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_103_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3) => '0',
DI(2) => \hcount[0]_i_153_n_0\,
DI(1) => \hcount[0]_i_154_n_0\,
DI(0) => \hcount[0]_i_155_n_0\,
O(3 downto 0) => \NLW_hcount_reg[0]_i_103_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_156_n_0\,
S(2) => \hcount[0]_i_157_n_0\,
S(1) => \hcount[0]_i_158_n_0\,
S(0) => \hcount[0]_i_159_n_0\
);
\hcount_reg[0]_i_108\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \hcount_reg[0]_i_108_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_108_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \hcount[0]_i_160_n_0\,
DI(0) => \hcount[0]_i_161_n_0\,
O(3 downto 0) => \NLW_hcount_reg[0]_i_108_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_162_n_0\,
S(2) => \hcount[0]_i_163_n_0\,
S(1) => \hcount[0]_i_164_n_0\,
S(0) => \hcount[0]_i_165_n_0\
);
\hcount_reg[0]_i_117\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \hcount_reg[0]_i_117_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_117_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3) => \hcount[0]_i_166_n_0\,
DI(2) => \hcount[0]_i_167_n_0\,
DI(1) => \hcount[0]_i_168_n_0\,
DI(0) => \hcount[0]_i_169_n_0\,
O(3 downto 0) => \NLW_hcount_reg[0]_i_117_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_170_n_0\,
S(2) => \hcount[0]_i_171_n_0\,
S(1) => \hcount[0]_i_172_n_0\,
S(0) => \hcount[0]_i_173_n_0\
);
\hcount_reg[0]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_41_n_0\,
CO(3) => \hcount_reg[0]_i_12_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_12_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3) => \hcount[0]_i_42_n_0\,
DI(2) => \hcount[0]_i_43_n_0\,
DI(1) => \hcount[0]_i_44_n_0\,
DI(0) => \hcount[0]_i_45_n_0\,
O(3 downto 0) => \NLW_hcount_reg[0]_i_12_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_46_n_0\,
S(2) => \hcount[0]_i_47_n_0\,
S(1) => \hcount[0]_i_48_n_0\,
S(0) => \hcount[0]_i_49_n_0\
);
\hcount_reg[0]_i_125\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_126_n_0\,
CO(3) => \hcount_reg[0]_i_125_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_125_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_125_n_4\,
O(2) => \hcount_reg[0]_i_125_n_5\,
O(1) => \hcount_reg[0]_i_125_n_6\,
O(0) => \hcount_reg[0]_i_125_n_7\,
S(3 downto 0) => \hcount_reg__0\(20 downto 17)
);
\hcount_reg[0]_i_126\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_135_n_0\,
CO(3) => \hcount_reg[0]_i_126_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_126_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_126_n_4\,
O(2) => \hcount_reg[0]_i_126_n_5\,
O(1) => \hcount_reg[0]_i_126_n_6\,
O(0) => \hcount_reg[0]_i_126_n_7\,
S(3 downto 0) => \hcount_reg__0\(16 downto 13)
);
\hcount_reg[0]_i_135\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_174_n_0\,
CO(3) => \hcount_reg[0]_i_135_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_135_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_135_n_4\,
O(2) => \hcount_reg[0]_i_135_n_5\,
O(1) => \hcount_reg[0]_i_135_n_6\,
O(0) => \hcount_reg[0]_i_135_n_7\,
S(3 downto 1) => \hcount_reg__0\(12 downto 10),
S(0) => hcount_reg(9)
);
\hcount_reg[0]_i_138\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \hcount_reg[0]_i_138_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_138_CO_UNCONNECTED\(2 downto 0),
CYINIT => vcount_reg(0),
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_138_n_4\,
O(2) => \hcount_reg[0]_i_138_n_5\,
O(1) => \hcount_reg[0]_i_138_n_6\,
O(0) => \hcount_reg[0]_i_138_n_7\,
S(3 downto 0) => vcount_reg(4 downto 1)
);
\hcount_reg[0]_i_143\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_144_n_0\,
CO(3) => \hcount_reg[0]_i_143_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_143_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_143_n_4\,
O(2) => \hcount_reg[0]_i_143_n_5\,
O(1) => \hcount_reg[0]_i_143_n_6\,
O(0) => \hcount_reg[0]_i_143_n_7\,
S(3 downto 1) => \vcount_reg__0\(12 downto 10),
S(0) => vcount_reg(9)
);
\hcount_reg[0]_i_144\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_138_n_0\,
CO(3) => \hcount_reg[0]_i_144_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_144_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_144_n_4\,
O(2) => \hcount_reg[0]_i_144_n_5\,
O(1) => \hcount_reg[0]_i_144_n_6\,
O(0) => \hcount_reg[0]_i_144_n_7\,
S(3 downto 0) => vcount_reg(8 downto 5)
);
\hcount_reg[0]_i_174\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_183_n_0\,
CO(3) => \hcount_reg[0]_i_174_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_174_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_174_n_4\,
O(2) => \hcount_reg[0]_i_174_n_5\,
O(1) => \hcount_reg[0]_i_174_n_6\,
O(0) => \hcount_reg[0]_i_174_n_7\,
S(3 downto 0) => hcount_reg(8 downto 5)
);
\hcount_reg[0]_i_183\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \hcount_reg[0]_i_183_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_183_CO_UNCONNECTED\(2 downto 0),
CYINIT => hcount_reg(0),
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_183_n_4\,
O(2) => \hcount_reg[0]_i_183_n_5\,
O(1) => \hcount_reg[0]_i_183_n_6\,
O(0) => \hcount_reg[0]_i_183_n_7\,
S(3 downto 0) => hcount_reg(4 downto 1)
);
\hcount_reg[0]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \hcount_reg[0]_i_2_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_2_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \hcount_reg[0]_i_2_n_4\,
O(2) => \hcount_reg[0]_i_2_n_5\,
O(1) => \hcount_reg[0]_i_2_n_6\,
O(0) => \hcount_reg[0]_i_2_n_7\,
S(3 downto 1) => hcount_reg(3 downto 1),
S(0) => \hcount[0]_i_11_n_0\
);
\hcount_reg[0]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_52_n_0\,
CO(3) => \hcount_reg[0]_i_21_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_21_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_hcount_reg[0]_i_21_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_53_n_0\,
S(2) => \hcount[0]_i_54_n_0\,
S(1) => \hcount[0]_i_55_n_0\,
S(0) => \hcount[0]_i_56_n_0\
);
\hcount_reg[0]_i_22\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_50_n_0\,
CO(3 downto 0) => \NLW_hcount_reg[0]_i_22_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_hcount_reg[0]_i_22_O_UNCONNECTED\(3),
O(2) => \hcount_reg[0]_i_22_n_5\,
O(1) => \hcount_reg[0]_i_22_n_6\,
O(0) => \hcount_reg[0]_i_22_n_7\,
S(3) => '0',
S(2 downto 0) => \vcount_reg__0\(31 downto 29)
);
\hcount_reg[0]_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_60_n_0\,
CO(3) => \hcount_reg[0]_i_25_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_25_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_hcount_reg[0]_i_25_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_61_n_0\,
S(2) => \hcount[0]_i_62_n_0\,
S(1) => \hcount[0]_i_63_n_0\,
S(0) => \hcount[0]_i_64_n_0\
);
\hcount_reg[0]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_65_n_0\,
CO(3 downto 0) => \NLW_hcount_reg[0]_i_26_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_hcount_reg[0]_i_26_O_UNCONNECTED\(3),
O(2) => \hcount_reg[0]_i_26_n_5\,
O(1) => \hcount_reg[0]_i_26_n_6\,
O(0) => \hcount_reg[0]_i_26_n_7\,
S(3) => '0',
S(2 downto 0) => \hcount_reg__0\(31 downto 29)
);
\hcount_reg[0]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_69_n_0\,
CO(3) => \hcount_reg[0]_i_28_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_28_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3) => \hcount[0]_i_70_n_0\,
DI(2) => \hcount[0]_i_71_n_0\,
DI(1) => \hcount[0]_i_72_n_0\,
DI(0) => \hcount[0]_i_73_n_0\,
O(3 downto 0) => \NLW_hcount_reg[0]_i_28_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_74_n_0\,
S(2) => \hcount[0]_i_75_n_0\,
S(1) => \hcount[0]_i_76_n_0\,
S(0) => \hcount[0]_i_77_n_0\
);
\hcount_reg[0]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_12_n_0\,
CO(3) => \hcount_reg[0]_i_3_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_3_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3) => \hcount[0]_i_13_n_0\,
DI(2) => \hcount[0]_i_14_n_0\,
DI(1) => \hcount[0]_i_15_n_0\,
DI(0) => \hcount[0]_i_16_n_0\,
O(3 downto 0) => \NLW_hcount_reg[0]_i_3_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_17_n_0\,
S(2) => \hcount[0]_i_18_n_0\,
S(1) => \hcount[0]_i_19_n_0\,
S(0) => \hcount[0]_i_20_n_0\
);
\hcount_reg[0]_i_37\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_79_n_0\,
CO(3) => \hcount_reg[0]_i_37_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_37_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_hcount_reg[0]_i_37_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_80_n_0\,
S(2) => \hcount[0]_i_81_n_0\,
S(1) => \hcount[0]_i_82_n_0\,
S(0) => \hcount[0]_i_83_n_0\
);
\hcount_reg[0]_i_4\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_21_n_0\,
CO(3 downto 2) => \NLW_hcount_reg[0]_i_4_CO_UNCONNECTED\(3 downto 2),
CO(1) => \hcount_reg[0]_i_4_n_2\,
CO(0) => \NLW_hcount_reg[0]_i_4_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \hcount_reg[0]_i_22_n_5\,
DI(0) => '0',
O(3 downto 0) => \NLW_hcount_reg[0]_i_4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => B"00",
S(1) => \hcount[0]_i_23_n_0\,
S(0) => \hcount[0]_i_24_n_0\
);
\hcount_reg[0]_i_41\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_84_n_0\,
CO(3) => \hcount_reg[0]_i_41_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_41_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3) => \hcount[0]_i_85_n_0\,
DI(2) => \hcount[0]_i_86_n_0\,
DI(1) => \hcount[0]_i_87_n_0\,
DI(0) => \hcount[0]_i_88_n_0\,
O(3 downto 0) => \NLW_hcount_reg[0]_i_41_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_89_n_0\,
S(2) => \hcount[0]_i_90_n_0\,
S(1) => \hcount[0]_i_91_n_0\,
S(0) => \hcount[0]_i_92_n_0\
);
\hcount_reg[0]_i_5\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_25_n_0\,
CO(3 downto 1) => \NLW_hcount_reg[0]_i_5_CO_UNCONNECTED\(3 downto 1),
CO(0) => hcount18_in,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \hcount_reg[0]_i_26_n_5\,
O(3 downto 0) => \NLW_hcount_reg[0]_i_5_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => B"000",
S(0) => \hcount[0]_i_27_n_0\
);
\hcount_reg[0]_i_50\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_51_n_0\,
CO(3) => \hcount_reg[0]_i_50_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_50_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_50_n_4\,
O(2) => \hcount_reg[0]_i_50_n_5\,
O(1) => \hcount_reg[0]_i_50_n_6\,
O(0) => \hcount_reg[0]_i_50_n_7\,
S(3 downto 0) => \vcount_reg__0\(28 downto 25)
);
\hcount_reg[0]_i_51\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_93_n_0\,
CO(3) => \hcount_reg[0]_i_51_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_51_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_51_n_4\,
O(2) => \hcount_reg[0]_i_51_n_5\,
O(1) => \hcount_reg[0]_i_51_n_6\,
O(0) => \hcount_reg[0]_i_51_n_7\,
S(3 downto 0) => \vcount_reg__0\(24 downto 21)
);
\hcount_reg[0]_i_52\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_103_n_0\,
CO(3) => \hcount_reg[0]_i_52_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_52_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_hcount_reg[0]_i_52_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_104_n_0\,
S(2) => \hcount[0]_i_105_n_0\,
S(1) => \hcount[0]_i_106_n_0\,
S(0) => \hcount[0]_i_107_n_0\
);
\hcount_reg[0]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_28_n_0\,
CO(3) => hcount1,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_6_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3) => \hcount[0]_i_29_n_0\,
DI(2) => \hcount[0]_i_30_n_0\,
DI(1) => \hcount[0]_i_31_n_0\,
DI(0) => \hcount[0]_i_32_n_0\,
O(3 downto 0) => \NLW_hcount_reg[0]_i_6_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_33_n_0\,
S(2) => \hcount[0]_i_34_n_0\,
S(1) => \hcount[0]_i_35_n_0\,
S(0) => \hcount[0]_i_36_n_0\
);
\hcount_reg[0]_i_60\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_108_n_0\,
CO(3) => \hcount_reg[0]_i_60_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_60_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_hcount_reg[0]_i_60_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_109_n_0\,
S(2) => \hcount[0]_i_110_n_0\,
S(1) => \hcount[0]_i_111_n_0\,
S(0) => \hcount[0]_i_112_n_0\
);
\hcount_reg[0]_i_65\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_78_n_0\,
CO(3) => \hcount_reg[0]_i_65_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_65_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_65_n_4\,
O(2) => \hcount_reg[0]_i_65_n_5\,
O(1) => \hcount_reg[0]_i_65_n_6\,
O(0) => \hcount_reg[0]_i_65_n_7\,
S(3 downto 0) => \hcount_reg__0\(28 downto 25)
);
\hcount_reg[0]_i_69\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_117_n_0\,
CO(3) => \hcount_reg[0]_i_69_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_69_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3) => \hcount[0]_i_118_n_0\,
DI(2) => \hcount[0]_i_119_n_0\,
DI(1) => \hcount[0]_i_120_n_0\,
DI(0) => '0',
O(3 downto 0) => \NLW_hcount_reg[0]_i_69_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_121_n_0\,
S(2) => \hcount[0]_i_122_n_0\,
S(1) => \hcount[0]_i_123_n_0\,
S(0) => \hcount[0]_i_124_n_0\
);
\hcount_reg[0]_i_7\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_37_n_0\,
CO(3) => \NLW_hcount_reg[0]_i_7_CO_UNCONNECTED\(3),
CO(2) => \hcount_reg[0]_i_7_n_1\,
CO(1 downto 0) => \NLW_hcount_reg[0]_i_7_CO_UNCONNECTED\(1 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_hcount_reg[0]_i_7_O_UNCONNECTED\(3 downto 0),
S(3) => '0',
S(2) => \hcount[0]_i_38_n_0\,
S(1) => \hcount[0]_i_39_n_0\,
S(0) => \hcount[0]_i_40_n_0\
);
\hcount_reg[0]_i_78\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_125_n_0\,
CO(3) => \hcount_reg[0]_i_78_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_78_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_78_n_4\,
O(2) => \hcount_reg[0]_i_78_n_5\,
O(1) => \hcount_reg[0]_i_78_n_6\,
O(0) => \hcount_reg[0]_i_78_n_7\,
S(3 downto 0) => \hcount_reg__0\(24 downto 21)
);
\hcount_reg[0]_i_79\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \hcount_reg[0]_i_79_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_79_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_hcount_reg[0]_i_79_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_131_n_0\,
S(2) => \hcount[0]_i_132_n_0\,
S(1) => \hcount[0]_i_133_n_0\,
S(0) => \hcount[0]_i_134_n_0\
);
\hcount_reg[0]_i_84\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \hcount_reg[0]_i_84_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_84_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3) => \hcount[0]_i_136_n_0\,
DI(2) => \hcount[0]_i_137_n_0\,
DI(1) => '0',
DI(0) => \hcount_reg[0]_i_138_n_7\,
O(3 downto 0) => \NLW_hcount_reg[0]_i_84_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_139_n_0\,
S(2) => \hcount[0]_i_140_n_0\,
S(1) => \hcount[0]_i_141_n_0\,
S(0) => \hcount[0]_i_142_n_0\
);
\hcount_reg[0]_i_93\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_94_n_0\,
CO(3) => \hcount_reg[0]_i_93_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_93_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_93_n_4\,
O(2) => \hcount_reg[0]_i_93_n_5\,
O(1) => \hcount_reg[0]_i_93_n_6\,
O(0) => \hcount_reg[0]_i_93_n_7\,
S(3 downto 0) => \vcount_reg__0\(20 downto 17)
);
\hcount_reg[0]_i_94\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_143_n_0\,
CO(3) => \hcount_reg[0]_i_94_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_94_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_94_n_4\,
O(2) => \hcount_reg[0]_i_94_n_5\,
O(1) => \hcount_reg[0]_i_94_n_6\,
O(0) => \hcount_reg[0]_i_94_n_7\,
S(3 downto 0) => \vcount_reg__0\(16 downto 13)
);
\hcount_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[8]_i_1_n_5\,
Q => \hcount_reg__0\(10),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[8]_i_1_n_4\,
Q => \hcount_reg__0\(11),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[12]_i_1_n_7\,
Q => \hcount_reg__0\(12),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[8]_i_1_n_0\,
CO(3) => \hcount_reg[12]_i_1_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[12]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[12]_i_1_n_4\,
O(2) => \hcount_reg[12]_i_1_n_5\,
O(1) => \hcount_reg[12]_i_1_n_6\,
O(0) => \hcount_reg[12]_i_1_n_7\,
S(3 downto 0) => \hcount_reg__0\(15 downto 12)
);
\hcount_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[12]_i_1_n_6\,
Q => \hcount_reg__0\(13),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[12]_i_1_n_5\,
Q => \hcount_reg__0\(14),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[12]_i_1_n_4\,
Q => \hcount_reg__0\(15),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[16]_i_1_n_7\,
Q => \hcount_reg__0\(16),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[16]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[12]_i_1_n_0\,
CO(3) => \hcount_reg[16]_i_1_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[16]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[16]_i_1_n_4\,
O(2) => \hcount_reg[16]_i_1_n_5\,
O(1) => \hcount_reg[16]_i_1_n_6\,
O(0) => \hcount_reg[16]_i_1_n_7\,
S(3 downto 0) => \hcount_reg__0\(19 downto 16)
);
\hcount_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[16]_i_1_n_6\,
Q => \hcount_reg__0\(17),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[16]_i_1_n_5\,
Q => \hcount_reg__0\(18),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[16]_i_1_n_4\,
Q => \hcount_reg__0\(19),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[0]_i_2_n_6\,
Q => hcount_reg(1),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[20]_i_1_n_7\,
Q => \hcount_reg__0\(20),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[20]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[16]_i_1_n_0\,
CO(3) => \hcount_reg[20]_i_1_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[20]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[20]_i_1_n_4\,
O(2) => \hcount_reg[20]_i_1_n_5\,
O(1) => \hcount_reg[20]_i_1_n_6\,
O(0) => \hcount_reg[20]_i_1_n_7\,
S(3 downto 0) => \hcount_reg__0\(23 downto 20)
);
\hcount_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[20]_i_1_n_6\,
Q => \hcount_reg__0\(21),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[20]_i_1_n_5\,
Q => \hcount_reg__0\(22),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[20]_i_1_n_4\,
Q => \hcount_reg__0\(23),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[24]_i_1_n_7\,
Q => \hcount_reg__0\(24),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[24]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[20]_i_1_n_0\,
CO(3) => \hcount_reg[24]_i_1_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[24]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[24]_i_1_n_4\,
O(2) => \hcount_reg[24]_i_1_n_5\,
O(1) => \hcount_reg[24]_i_1_n_6\,
O(0) => \hcount_reg[24]_i_1_n_7\,
S(3 downto 0) => \hcount_reg__0\(27 downto 24)
);
\hcount_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[24]_i_1_n_6\,
Q => \hcount_reg__0\(25),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[24]_i_1_n_5\,
Q => \hcount_reg__0\(26),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[24]_i_1_n_4\,
Q => \hcount_reg__0\(27),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[28]_i_1_n_7\,
Q => \hcount_reg__0\(28),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[28]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[24]_i_1_n_0\,
CO(3 downto 0) => \NLW_hcount_reg[28]_i_1_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[28]_i_1_n_4\,
O(2) => \hcount_reg[28]_i_1_n_5\,
O(1) => \hcount_reg[28]_i_1_n_6\,
O(0) => \hcount_reg[28]_i_1_n_7\,
S(3 downto 0) => \hcount_reg__0\(31 downto 28)
);
\hcount_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[28]_i_1_n_6\,
Q => \hcount_reg__0\(29),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[0]_i_2_n_5\,
Q => hcount_reg(2),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[28]_i_1_n_5\,
Q => \hcount_reg__0\(30),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[28]_i_1_n_4\,
Q => \hcount_reg__0\(31),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[0]_i_2_n_4\,
Q => hcount_reg(3),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[4]_i_1_n_7\,
Q => hcount_reg(4),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_2_n_0\,
CO(3) => \hcount_reg[4]_i_1_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[4]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[4]_i_1_n_4\,
O(2) => \hcount_reg[4]_i_1_n_5\,
O(1) => \hcount_reg[4]_i_1_n_6\,
O(0) => \hcount_reg[4]_i_1_n_7\,
S(3 downto 0) => hcount_reg(7 downto 4)
);
\hcount_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[4]_i_1_n_6\,
Q => hcount_reg(5),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[4]_i_1_n_5\,
Q => hcount_reg(6),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[4]_i_1_n_4\,
Q => hcount_reg(7),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[8]_i_1_n_7\,
Q => hcount_reg(8),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[4]_i_1_n_0\,
CO(3) => \hcount_reg[8]_i_1_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[8]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[8]_i_1_n_4\,
O(2) => \hcount_reg[8]_i_1_n_5\,
O(1) => \hcount_reg[8]_i_1_n_6\,
O(0) => \hcount_reg[8]_i_1_n_7\,
S(3 downto 2) => \hcount_reg__0\(11 downto 10),
S(1 downto 0) => hcount_reg(9 downto 8)
);
\hcount_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[8]_i_1_n_6\,
Q => hcount_reg(9),
R => \hcount[0]_i_1_n_0\
);
hsync_OBUF_inst: unisim.vcomponents.OBUF
port map (
I => hsync_OBUF,
O => hsync
);
hsync_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"F8888888"
)
port map (
I0 => hsync_OBUF,
I1 => rst_IBUF,
I2 => hsync_i_2_n_0,
I3 => hsync_i_3_n_0,
I4 => hsync_i_4_n_0,
O => hsync_i_1_n_0
);
hsync_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000080"
)
port map (
I0 => hsync_i_5_n_0,
I1 => hsync_i_6_n_0,
I2 => hsync_i_7_n_0,
I3 => hcount_reg(2),
I4 => hcount_reg(1),
I5 => hcount_reg(0),
O => hsync_i_2_n_0
);
hsync_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \hcount_reg__0\(29),
I1 => \hcount_reg__0\(30),
I2 => \hcount_reg__0\(27),
I3 => \hcount_reg__0\(28),
I4 => rst_IBUF,
I5 => \hcount_reg__0\(31),
O => hsync_i_3_n_0
);
hsync_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \hcount_reg__0\(23),
I1 => \hcount_reg__0\(24),
I2 => \hcount_reg__0\(21),
I3 => \hcount_reg__0\(22),
I4 => \hcount_reg__0\(26),
I5 => \hcount_reg__0\(25),
O => hsync_i_4_n_0
);
hsync_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \hcount_reg__0\(11),
I1 => \hcount_reg__0\(12),
I2 => hcount_reg(9),
I3 => \hcount_reg__0\(10),
I4 => \hcount_reg__0\(14),
I5 => \hcount_reg__0\(13),
O => hsync_i_5_n_0
);
hsync_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \hcount_reg__0\(17),
I1 => \hcount_reg__0\(18),
I2 => \hcount_reg__0\(15),
I3 => \hcount_reg__0\(16),
I4 => \hcount_reg__0\(20),
I5 => \hcount_reg__0\(19),
O => hsync_i_6_n_0
);
hsync_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => hcount_reg(5),
I1 => hcount_reg(6),
I2 => hcount_reg(3),
I3 => hcount_reg(4),
I4 => hcount_reg(8),
I5 => hcount_reg(7),
O => hsync_i_7_n_0
);
hsync_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => hsync_i_1_n_0,
Q => hsync_OBUF,
R => '0'
);
rst_IBUF_inst: unisim.vcomponents.IBUF
port map (
I => rst,
O => rst_IBUF
);
\vcount[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00001000"
)
port map (
I0 => \hcount_reg[0]_i_4_n_2\,
I1 => hcount18_in,
I2 => \hcount_reg[0]_i_3_n_0\,
I3 => hcount1,
I4 => \hcount_reg[0]_i_7_n_1\,
I5 => rst_IBUF,
O => \vcount[0]_i_1_n_0\
);
\vcount[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => hcount18_in,
I1 => hcount1,
I2 => \hcount_reg[0]_i_7_n_1\,
O => \vcount[0]_i_2_n_0\
);
\vcount[0]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => vcount_reg(0),
O => \vcount[0]_i_7_n_0\
);
\vcount_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[0]_i_3_n_7\,
Q => vcount_reg(0),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[0]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \vcount_reg[0]_i_3_n_0\,
CO(2 downto 0) => \NLW_vcount_reg[0]_i_3_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \vcount_reg[0]_i_3_n_4\,
O(2) => \vcount_reg[0]_i_3_n_5\,
O(1) => \vcount_reg[0]_i_3_n_6\,
O(0) => \vcount_reg[0]_i_3_n_7\,
S(3 downto 1) => vcount_reg(3 downto 1),
S(0) => \vcount[0]_i_7_n_0\
);
\vcount_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[8]_i_1_n_5\,
Q => \vcount_reg__0\(10),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[8]_i_1_n_4\,
Q => \vcount_reg__0\(11),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[12]_i_1_n_7\,
Q => \vcount_reg__0\(12),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \vcount_reg[8]_i_1_n_0\,
CO(3) => \vcount_reg[12]_i_1_n_0\,
CO(2 downto 0) => \NLW_vcount_reg[12]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \vcount_reg[12]_i_1_n_4\,
O(2) => \vcount_reg[12]_i_1_n_5\,
O(1) => \vcount_reg[12]_i_1_n_6\,
O(0) => \vcount_reg[12]_i_1_n_7\,
S(3 downto 0) => \vcount_reg__0\(15 downto 12)
);
\vcount_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[12]_i_1_n_6\,
Q => \vcount_reg__0\(13),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[12]_i_1_n_5\,
Q => \vcount_reg__0\(14),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[12]_i_1_n_4\,
Q => \vcount_reg__0\(15),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[16]_i_1_n_7\,
Q => \vcount_reg__0\(16),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[16]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \vcount_reg[12]_i_1_n_0\,
CO(3) => \vcount_reg[16]_i_1_n_0\,
CO(2 downto 0) => \NLW_vcount_reg[16]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \vcount_reg[16]_i_1_n_4\,
O(2) => \vcount_reg[16]_i_1_n_5\,
O(1) => \vcount_reg[16]_i_1_n_6\,
O(0) => \vcount_reg[16]_i_1_n_7\,
S(3 downto 0) => \vcount_reg__0\(19 downto 16)
);
\vcount_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[16]_i_1_n_6\,
Q => \vcount_reg__0\(17),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[16]_i_1_n_5\,
Q => \vcount_reg__0\(18),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[16]_i_1_n_4\,
Q => \vcount_reg__0\(19),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[0]_i_3_n_6\,
Q => vcount_reg(1),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[20]_i_1_n_7\,
Q => \vcount_reg__0\(20),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[20]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \vcount_reg[16]_i_1_n_0\,
CO(3) => \vcount_reg[20]_i_1_n_0\,
CO(2 downto 0) => \NLW_vcount_reg[20]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \vcount_reg[20]_i_1_n_4\,
O(2) => \vcount_reg[20]_i_1_n_5\,
O(1) => \vcount_reg[20]_i_1_n_6\,
O(0) => \vcount_reg[20]_i_1_n_7\,
S(3 downto 0) => \vcount_reg__0\(23 downto 20)
);
\vcount_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[20]_i_1_n_6\,
Q => \vcount_reg__0\(21),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[20]_i_1_n_5\,
Q => \vcount_reg__0\(22),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[20]_i_1_n_4\,
Q => \vcount_reg__0\(23),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[24]_i_1_n_7\,
Q => \vcount_reg__0\(24),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[24]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \vcount_reg[20]_i_1_n_0\,
CO(3) => \vcount_reg[24]_i_1_n_0\,
CO(2 downto 0) => \NLW_vcount_reg[24]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \vcount_reg[24]_i_1_n_4\,
O(2) => \vcount_reg[24]_i_1_n_5\,
O(1) => \vcount_reg[24]_i_1_n_6\,
O(0) => \vcount_reg[24]_i_1_n_7\,
S(3 downto 0) => \vcount_reg__0\(27 downto 24)
);
\vcount_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[24]_i_1_n_6\,
Q => \vcount_reg__0\(25),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[24]_i_1_n_5\,
Q => \vcount_reg__0\(26),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[24]_i_1_n_4\,
Q => \vcount_reg__0\(27),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[28]_i_1_n_7\,
Q => \vcount_reg__0\(28),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[28]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \vcount_reg[24]_i_1_n_0\,
CO(3 downto 0) => \NLW_vcount_reg[28]_i_1_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \vcount_reg[28]_i_1_n_4\,
O(2) => \vcount_reg[28]_i_1_n_5\,
O(1) => \vcount_reg[28]_i_1_n_6\,
O(0) => \vcount_reg[28]_i_1_n_7\,
S(3 downto 0) => \vcount_reg__0\(31 downto 28)
);
\vcount_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[28]_i_1_n_6\,
Q => \vcount_reg__0\(29),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[0]_i_3_n_5\,
Q => vcount_reg(2),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[28]_i_1_n_5\,
Q => \vcount_reg__0\(30),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[28]_i_1_n_4\,
Q => \vcount_reg__0\(31),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[0]_i_3_n_4\,
Q => vcount_reg(3),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[4]_i_1_n_7\,
Q => vcount_reg(4),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \vcount_reg[0]_i_3_n_0\,
CO(3) => \vcount_reg[4]_i_1_n_0\,
CO(2 downto 0) => \NLW_vcount_reg[4]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \vcount_reg[4]_i_1_n_4\,
O(2) => \vcount_reg[4]_i_1_n_5\,
O(1) => \vcount_reg[4]_i_1_n_6\,
O(0) => \vcount_reg[4]_i_1_n_7\,
S(3 downto 0) => vcount_reg(7 downto 4)
);
\vcount_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[4]_i_1_n_6\,
Q => vcount_reg(5),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[4]_i_1_n_5\,
Q => vcount_reg(6),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[4]_i_1_n_4\,
Q => vcount_reg(7),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[8]_i_1_n_7\,
Q => vcount_reg(8),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \vcount_reg[4]_i_1_n_0\,
CO(3) => \vcount_reg[8]_i_1_n_0\,
CO(2 downto 0) => \NLW_vcount_reg[8]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \vcount_reg[8]_i_1_n_4\,
O(2) => \vcount_reg[8]_i_1_n_5\,
O(1) => \vcount_reg[8]_i_1_n_6\,
O(0) => \vcount_reg[8]_i_1_n_7\,
S(3 downto 2) => \vcount_reg__0\(11 downto 10),
S(1 downto 0) => vcount_reg(9 downto 8)
);
\vcount_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[8]_i_1_n_6\,
Q => vcount_reg(9),
R => \vcount[0]_i_1_n_0\
);
vsync_OBUF_inst: unisim.vcomponents.OBUF
port map (
I => vsync_OBUF,
O => vsync
);
vsync_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"F8888888"
)
port map (
I0 => vsync_OBUF,
I1 => rst_IBUF,
I2 => vsync_i_2_n_0,
I3 => vsync_i_3_n_0,
I4 => vsync_i_4_n_0,
O => vsync_i_1_n_0
);
vsync_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000080"
)
port map (
I0 => vsync_i_5_n_0,
I1 => vsync_i_6_n_0,
I2 => vsync_i_7_n_0,
I3 => vcount_reg(2),
I4 => vcount_reg(1),
I5 => vcount_reg(0),
O => vsync_i_2_n_0
);
vsync_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \vcount_reg__0\(29),
I1 => \vcount_reg__0\(30),
I2 => \vcount_reg__0\(27),
I3 => \vcount_reg__0\(28),
I4 => rst_IBUF,
I5 => \vcount_reg__0\(31),
O => vsync_i_3_n_0
);
vsync_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \vcount_reg__0\(23),
I1 => \vcount_reg__0\(24),
I2 => \vcount_reg__0\(21),
I3 => \vcount_reg__0\(22),
I4 => \vcount_reg__0\(26),
I5 => \vcount_reg__0\(25),
O => vsync_i_4_n_0
);
vsync_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \vcount_reg__0\(11),
I1 => \vcount_reg__0\(12),
I2 => vcount_reg(9),
I3 => \vcount_reg__0\(10),
I4 => \vcount_reg__0\(14),
I5 => \vcount_reg__0\(13),
O => vsync_i_5_n_0
);
vsync_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \vcount_reg__0\(17),
I1 => \vcount_reg__0\(18),
I2 => \vcount_reg__0\(15),
I3 => \vcount_reg__0\(16),
I4 => \vcount_reg__0\(20),
I5 => \vcount_reg__0\(19),
O => vsync_i_6_n_0
);
vsync_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => vcount_reg(5),
I1 => vcount_reg(6),
I2 => vcount_reg(3),
I3 => vcount_reg(4),
I4 => vcount_reg(8),
I5 => vcount_reg(7),
O => vsync_i_7_n_0
);
vsync_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => vsync_i_1_n_0,
Q => vsync_OBUF,
R => '0'
);
\xaddr[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rst_IBUF,
I1 => \xaddr_reg[9]_i_3_n_3\,
O => \xaddr[9]_i_1_n_0\
);
\xaddr[9]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg__0\(22),
I1 => \hcount_reg__0\(23),
O => \xaddr[9]_i_10_n_0\
);
\xaddr[9]_i_12\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg__0\(20),
I1 => \hcount_reg__0\(21),
O => \xaddr[9]_i_12_n_0\
);
\xaddr[9]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg__0\(18),
I1 => \hcount_reg__0\(19),
O => \xaddr[9]_i_13_n_0\
);
\xaddr[9]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg__0\(16),
I1 => \hcount_reg__0\(17),
O => \xaddr[9]_i_14_n_0\
);
\xaddr[9]_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg__0\(14),
I1 => \hcount_reg__0\(15),
O => \xaddr[9]_i_15_n_0\
);
\xaddr[9]_i_16\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => hcount_reg(9),
O => \xaddr[9]_i_16_n_0\
);
\xaddr[9]_i_17\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => hcount_reg(7),
O => \xaddr[9]_i_17_n_0\
);
\xaddr[9]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg__0\(12),
I1 => \hcount_reg__0\(13),
O => \xaddr[9]_i_18_n_0\
);
\xaddr[9]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg__0\(10),
I1 => \hcount_reg__0\(11),
O => \xaddr[9]_i_19_n_0\
);
\xaddr[9]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rst_IBUF,
O => p_0_in
);
\xaddr[9]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => hcount_reg(9),
I1 => hcount_reg(8),
O => \xaddr[9]_i_20_n_0\
);
\xaddr[9]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => hcount_reg(7),
I1 => hcount_reg(6),
O => \xaddr[9]_i_21_n_0\
);
\xaddr[9]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg__0\(30),
I1 => \hcount_reg__0\(31),
O => \xaddr[9]_i_5_n_0\
);
\xaddr[9]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg__0\(28),
I1 => \hcount_reg__0\(29),
O => \xaddr[9]_i_7_n_0\
);
\xaddr[9]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg__0\(26),
I1 => \hcount_reg__0\(27),
O => \xaddr[9]_i_8_n_0\
);
\xaddr[9]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg__0\(24),
I1 => \hcount_reg__0\(25),
O => \xaddr[9]_i_9_n_0\
);
\xaddr_OBUF[0]_inst\: unisim.vcomponents.OBUF
port map (
I => xaddr_OBUF(0),
O => xaddr(0)
);
\xaddr_OBUF[1]_inst\: unisim.vcomponents.OBUF
port map (
I => xaddr_OBUF(1),
O => xaddr(1)
);
\xaddr_OBUF[2]_inst\: unisim.vcomponents.OBUF
port map (
I => xaddr_OBUF(2),
O => xaddr(2)
);
\xaddr_OBUF[3]_inst\: unisim.vcomponents.OBUF
port map (
I => xaddr_OBUF(3),
O => xaddr(3)
);
\xaddr_OBUF[4]_inst\: unisim.vcomponents.OBUF
port map (
I => xaddr_OBUF(4),
O => xaddr(4)
);
\xaddr_OBUF[5]_inst\: unisim.vcomponents.OBUF
port map (
I => xaddr_OBUF(5),
O => xaddr(5)
);
\xaddr_OBUF[6]_inst\: unisim.vcomponents.OBUF
port map (
I => xaddr_OBUF(6),
O => xaddr(6)
);
\xaddr_OBUF[7]_inst\: unisim.vcomponents.OBUF
port map (
I => xaddr_OBUF(7),
O => xaddr(7)
);
\xaddr_OBUF[8]_inst\: unisim.vcomponents.OBUF
port map (
I => xaddr_OBUF(8),
O => xaddr(8)
);
\xaddr_OBUF[9]_inst\: unisim.vcomponents.OBUF
port map (
I => xaddr_OBUF(9),
O => xaddr(9)
);
\xaddr_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => hcount_reg(0),
Q => xaddr_OBUF(0),
S => \xaddr[9]_i_1_n_0\
);
\xaddr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => hcount_reg(1),
Q => xaddr_OBUF(1),
S => \xaddr[9]_i_1_n_0\
);
\xaddr_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => hcount_reg(2),
Q => xaddr_OBUF(2),
S => \xaddr[9]_i_1_n_0\
);
\xaddr_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => hcount_reg(3),
Q => xaddr_OBUF(3),
S => \xaddr[9]_i_1_n_0\
);
\xaddr_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => hcount_reg(4),
Q => xaddr_OBUF(4),
S => \xaddr[9]_i_1_n_0\
);
\xaddr_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => hcount_reg(5),
Q => xaddr_OBUF(5),
S => \xaddr[9]_i_1_n_0\
);
\xaddr_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => hcount_reg(6),
Q => xaddr_OBUF(6),
S => \xaddr[9]_i_1_n_0\
);
\xaddr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => hcount_reg(7),
Q => xaddr_OBUF(7),
R => \xaddr[9]_i_1_n_0\
);
\xaddr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => hcount_reg(8),
Q => xaddr_OBUF(8),
R => \xaddr[9]_i_1_n_0\
);
\xaddr_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => hcount_reg(9),
Q => xaddr_OBUF(9),
S => \xaddr[9]_i_1_n_0\
);
\xaddr_reg[9]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \xaddr_reg[9]_i_11_n_0\,
CO(2 downto 0) => \NLW_xaddr_reg[9]_i_11_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \xaddr[9]_i_16_n_0\,
DI(0) => \xaddr[9]_i_17_n_0\,
O(3 downto 0) => \NLW_xaddr_reg[9]_i_11_O_UNCONNECTED\(3 downto 0),
S(3) => \xaddr[9]_i_18_n_0\,
S(2) => \xaddr[9]_i_19_n_0\,
S(1) => \xaddr[9]_i_20_n_0\,
S(0) => \xaddr[9]_i_21_n_0\
);
\xaddr_reg[9]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \xaddr_reg[9]_i_4_n_0\,
CO(3 downto 1) => \NLW_xaddr_reg[9]_i_3_CO_UNCONNECTED\(3 downto 1),
CO(0) => \xaddr_reg[9]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \hcount_reg__0\(31),
O(3 downto 0) => \NLW_xaddr_reg[9]_i_3_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => B"000",
S(0) => \xaddr[9]_i_5_n_0\
);
\xaddr_reg[9]_i_4\: unisim.vcomponents.CARRY4
port map (
CI => \xaddr_reg[9]_i_6_n_0\,
CO(3) => \xaddr_reg[9]_i_4_n_0\,
CO(2 downto 0) => \NLW_xaddr_reg[9]_i_4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_xaddr_reg[9]_i_4_O_UNCONNECTED\(3 downto 0),
S(3) => \xaddr[9]_i_7_n_0\,
S(2) => \xaddr[9]_i_8_n_0\,
S(1) => \xaddr[9]_i_9_n_0\,
S(0) => \xaddr[9]_i_10_n_0\
);
\xaddr_reg[9]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \xaddr_reg[9]_i_11_n_0\,
CO(3) => \xaddr_reg[9]_i_6_n_0\,
CO(2 downto 0) => \NLW_xaddr_reg[9]_i_6_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_xaddr_reg[9]_i_6_O_UNCONNECTED\(3 downto 0),
S(3) => \xaddr[9]_i_12_n_0\,
S(2) => \xaddr[9]_i_13_n_0\,
S(1) => \xaddr[9]_i_14_n_0\,
S(0) => \xaddr[9]_i_15_n_0\
);
\yaddr[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rst_IBUF,
I1 => \yaddr_reg[9]_i_2_n_2\,
O => \yaddr[9]_i_1_n_0\
);
\yaddr[9]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \vcount_reg__0\(20),
I1 => \vcount_reg__0\(21),
O => \yaddr[9]_i_10_n_0\
);
\yaddr[9]_i_12\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \vcount_reg__0\(18),
I1 => \vcount_reg__0\(19),
O => \yaddr[9]_i_12_n_0\
);
\yaddr[9]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \vcount_reg__0\(16),
I1 => \vcount_reg__0\(17),
O => \yaddr[9]_i_13_n_0\
);
\yaddr[9]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \vcount_reg__0\(14),
I1 => \vcount_reg__0\(15),
O => \yaddr[9]_i_14_n_0\
);
\yaddr[9]_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \vcount_reg__0\(12),
I1 => \vcount_reg__0\(13),
O => \yaddr[9]_i_15_n_0\
);
\yaddr[9]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => vcount_reg(8),
I1 => vcount_reg(9),
O => \yaddr[9]_i_16_n_0\
);
\yaddr[9]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => vcount_reg(6),
I1 => vcount_reg(7),
O => \yaddr[9]_i_17_n_0\
);
\yaddr[9]_i_18\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => vcount_reg(5),
O => \yaddr[9]_i_18_n_0\
);
\yaddr[9]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \vcount_reg__0\(10),
I1 => \vcount_reg__0\(11),
O => \yaddr[9]_i_19_n_0\
);
\yaddr[9]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => vcount_reg(8),
I1 => vcount_reg(9),
O => \yaddr[9]_i_20_n_0\
);
\yaddr[9]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => vcount_reg(6),
I1 => vcount_reg(7),
O => \yaddr[9]_i_21_n_0\
);
\yaddr[9]_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => vcount_reg(5),
I1 => vcount_reg(4),
O => \yaddr[9]_i_22_n_0\
);
\yaddr[9]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \vcount_reg__0\(30),
I1 => \vcount_reg__0\(31),
O => \yaddr[9]_i_4_n_0\
);
\yaddr[9]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \vcount_reg__0\(28),
I1 => \vcount_reg__0\(29),
O => \yaddr[9]_i_5_n_0\
);
\yaddr[9]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \vcount_reg__0\(26),
I1 => \vcount_reg__0\(27),
O => \yaddr[9]_i_7_n_0\
);
\yaddr[9]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \vcount_reg__0\(24),
I1 => \vcount_reg__0\(25),
O => \yaddr[9]_i_8_n_0\
);
\yaddr[9]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \vcount_reg__0\(22),
I1 => \vcount_reg__0\(23),
O => \yaddr[9]_i_9_n_0\
);
\yaddr_OBUF[0]_inst\: unisim.vcomponents.OBUF
port map (
I => yaddr_OBUF(0),
O => yaddr(0)
);
\yaddr_OBUF[1]_inst\: unisim.vcomponents.OBUF
port map (
I => yaddr_OBUF(1),
O => yaddr(1)
);
\yaddr_OBUF[2]_inst\: unisim.vcomponents.OBUF
port map (
I => yaddr_OBUF(2),
O => yaddr(2)
);
\yaddr_OBUF[3]_inst\: unisim.vcomponents.OBUF
port map (
I => yaddr_OBUF(3),
O => yaddr(3)
);
\yaddr_OBUF[4]_inst\: unisim.vcomponents.OBUF
port map (
I => yaddr_OBUF(4),
O => yaddr(4)
);
\yaddr_OBUF[5]_inst\: unisim.vcomponents.OBUF
port map (
I => yaddr_OBUF(5),
O => yaddr(5)
);
\yaddr_OBUF[6]_inst\: unisim.vcomponents.OBUF
port map (
I => yaddr_OBUF(6),
O => yaddr(6)
);
\yaddr_OBUF[7]_inst\: unisim.vcomponents.OBUF
port map (
I => yaddr_OBUF(7),
O => yaddr(7)
);
\yaddr_OBUF[8]_inst\: unisim.vcomponents.OBUF
port map (
I => yaddr_OBUF(8),
O => yaddr(8)
);
\yaddr_OBUF[9]_inst\: unisim.vcomponents.OBUF
port map (
I => yaddr_OBUF(9),
O => yaddr(9)
);
\yaddr_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => vcount_reg(0),
Q => yaddr_OBUF(0),
S => \yaddr[9]_i_1_n_0\
);
\yaddr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => vcount_reg(1),
Q => yaddr_OBUF(1),
S => \yaddr[9]_i_1_n_0\
);
\yaddr_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => vcount_reg(2),
Q => yaddr_OBUF(2),
S => \yaddr[9]_i_1_n_0\
);
\yaddr_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => vcount_reg(3),
Q => yaddr_OBUF(3),
S => \yaddr[9]_i_1_n_0\
);
\yaddr_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => vcount_reg(4),
Q => yaddr_OBUF(4),
S => \yaddr[9]_i_1_n_0\
);
\yaddr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => vcount_reg(5),
Q => yaddr_OBUF(5),
R => \yaddr[9]_i_1_n_0\
);
\yaddr_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => vcount_reg(6),
Q => yaddr_OBUF(6),
S => \yaddr[9]_i_1_n_0\
);
\yaddr_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => vcount_reg(7),
Q => yaddr_OBUF(7),
S => \yaddr[9]_i_1_n_0\
);
\yaddr_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => vcount_reg(8),
Q => yaddr_OBUF(8),
S => \yaddr[9]_i_1_n_0\
);
\yaddr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => vcount_reg(9),
Q => yaddr_OBUF(9),
R => \yaddr[9]_i_1_n_0\
);
\yaddr_reg[9]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \yaddr_reg[9]_i_11_n_0\,
CO(2 downto 0) => \NLW_yaddr_reg[9]_i_11_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3) => '0',
DI(2) => \yaddr[9]_i_16_n_0\,
DI(1) => \yaddr[9]_i_17_n_0\,
DI(0) => \yaddr[9]_i_18_n_0\,
O(3 downto 0) => \NLW_yaddr_reg[9]_i_11_O_UNCONNECTED\(3 downto 0),
S(3) => \yaddr[9]_i_19_n_0\,
S(2) => \yaddr[9]_i_20_n_0\,
S(1) => \yaddr[9]_i_21_n_0\,
S(0) => \yaddr[9]_i_22_n_0\
);
\yaddr_reg[9]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \yaddr_reg[9]_i_3_n_0\,
CO(3 downto 2) => \NLW_yaddr_reg[9]_i_2_CO_UNCONNECTED\(3 downto 2),
CO(1) => \yaddr_reg[9]_i_2_n_2\,
CO(0) => \NLW_yaddr_reg[9]_i_2_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \vcount_reg__0\(31),
DI(0) => '0',
O(3 downto 0) => \NLW_yaddr_reg[9]_i_2_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => B"00",
S(1) => \yaddr[9]_i_4_n_0\,
S(0) => \yaddr[9]_i_5_n_0\
);
\yaddr_reg[9]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \yaddr_reg[9]_i_6_n_0\,
CO(3) => \yaddr_reg[9]_i_3_n_0\,
CO(2 downto 0) => \NLW_yaddr_reg[9]_i_3_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_yaddr_reg[9]_i_3_O_UNCONNECTED\(3 downto 0),
S(3) => \yaddr[9]_i_7_n_0\,
S(2) => \yaddr[9]_i_8_n_0\,
S(1) => \yaddr[9]_i_9_n_0\,
S(0) => \yaddr[9]_i_10_n_0\
);
\yaddr_reg[9]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \yaddr_reg[9]_i_11_n_0\,
CO(3) => \yaddr_reg[9]_i_6_n_0\,
CO(2 downto 0) => \NLW_yaddr_reg[9]_i_6_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_yaddr_reg[9]_i_6_O_UNCONNECTED\(3 downto 0),
S(3) => \yaddr[9]_i_12_n_0\,
S(2) => \yaddr[9]_i_13_n_0\,
S(1) => \yaddr[9]_i_14_n_0\,
S(0) => \yaddr[9]_i_15_n_0\
);
end STRUCTURE;
| mit | c75fa798ea60935aa25e2421eccc0d63 | 0.505893 | 2.479515 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_multiplier_1_0/affine_block_ieee754_fp_multiplier_1_0_sim_netlist.vhdl | 1 | 200,696 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 20 13:53:00 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_multiplier_1_0/affine_block_ieee754_fp_multiplier_1_0_sim_netlist.vhdl
-- Design : affine_block_ieee754_fp_multiplier_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity affine_block_ieee754_fp_multiplier_1_0_ieee754_fp_multiplier is
port (
z : out STD_LOGIC_VECTOR ( 7 downto 0 );
z_mantissa : out STD_LOGIC_VECTOR ( 22 downto 0 );
x : in STD_LOGIC_VECTOR ( 30 downto 0 );
y : in STD_LOGIC_VECTOR ( 30 downto 0 );
\y_11__s_port_\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of affine_block_ieee754_fp_multiplier_1_0_ieee754_fp_multiplier : entity is "ieee754_fp_multiplier";
end affine_block_ieee754_fp_multiplier_1_0_ieee754_fp_multiplier;
architecture STRUCTURE of affine_block_ieee754_fp_multiplier_1_0_ieee754_fp_multiplier is
signal L1 : STD_LOGIC;
signal \L1_carry__0_i_1_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_2_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_3_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_4_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_5_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_6_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_7_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_8_n_0\ : STD_LOGIC;
signal \L1_carry__0_n_0\ : STD_LOGIC;
signal \L1_carry__0_n_1\ : STD_LOGIC;
signal \L1_carry__0_n_2\ : STD_LOGIC;
signal \L1_carry__0_n_3\ : STD_LOGIC;
signal \L1_carry__1_i_1_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_2_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_3_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_4_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_5_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_6_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_7_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_8_n_0\ : STD_LOGIC;
signal \L1_carry__1_n_0\ : STD_LOGIC;
signal \L1_carry__1_n_1\ : STD_LOGIC;
signal \L1_carry__1_n_2\ : STD_LOGIC;
signal \L1_carry__1_n_3\ : STD_LOGIC;
signal \L1_carry__2_i_1_n_0\ : STD_LOGIC;
signal \L1_carry__2_i_2_n_0\ : STD_LOGIC;
signal \L1_carry__2_i_3_n_0\ : STD_LOGIC;
signal \L1_carry__2_i_4_n_0\ : STD_LOGIC;
signal \L1_carry__2_i_5_n_0\ : STD_LOGIC;
signal \L1_carry__2_i_6_n_0\ : STD_LOGIC;
signal \L1_carry__2_i_7_n_0\ : STD_LOGIC;
signal \L1_carry__2_n_1\ : STD_LOGIC;
signal \L1_carry__2_n_2\ : STD_LOGIC;
signal \L1_carry__2_n_3\ : STD_LOGIC;
signal L1_carry_i_10_n_0 : STD_LOGIC;
signal L1_carry_i_11_n_0 : STD_LOGIC;
signal L1_carry_i_12_n_0 : STD_LOGIC;
signal L1_carry_i_13_n_0 : STD_LOGIC;
signal L1_carry_i_14_n_0 : STD_LOGIC;
signal L1_carry_i_15_n_0 : STD_LOGIC;
signal L1_carry_i_16_n_0 : STD_LOGIC;
signal L1_carry_i_17_n_0 : STD_LOGIC;
signal L1_carry_i_18_n_0 : STD_LOGIC;
signal L1_carry_i_19_n_0 : STD_LOGIC;
signal L1_carry_i_1_n_0 : STD_LOGIC;
signal L1_carry_i_20_n_0 : STD_LOGIC;
signal L1_carry_i_21_n_0 : STD_LOGIC;
signal L1_carry_i_22_n_0 : STD_LOGIC;
signal L1_carry_i_23_n_0 : STD_LOGIC;
signal L1_carry_i_24_n_0 : STD_LOGIC;
signal L1_carry_i_25_n_0 : STD_LOGIC;
signal L1_carry_i_26_n_0 : STD_LOGIC;
signal L1_carry_i_27_n_0 : STD_LOGIC;
signal L1_carry_i_28_n_0 : STD_LOGIC;
signal L1_carry_i_29_n_0 : STD_LOGIC;
signal L1_carry_i_2_n_0 : STD_LOGIC;
signal L1_carry_i_30_n_0 : STD_LOGIC;
signal L1_carry_i_31_n_0 : STD_LOGIC;
signal L1_carry_i_32_n_0 : STD_LOGIC;
signal L1_carry_i_33_n_0 : STD_LOGIC;
signal L1_carry_i_34_n_0 : STD_LOGIC;
signal L1_carry_i_35_n_0 : STD_LOGIC;
signal L1_carry_i_36_n_0 : STD_LOGIC;
signal L1_carry_i_37_n_0 : STD_LOGIC;
signal L1_carry_i_38_n_0 : STD_LOGIC;
signal L1_carry_i_39_n_0 : STD_LOGIC;
signal L1_carry_i_3_n_0 : STD_LOGIC;
signal L1_carry_i_40_n_0 : STD_LOGIC;
signal L1_carry_i_41_n_0 : STD_LOGIC;
signal L1_carry_i_42_n_0 : STD_LOGIC;
signal L1_carry_i_43_n_0 : STD_LOGIC;
signal L1_carry_i_44_n_0 : STD_LOGIC;
signal L1_carry_i_45_n_0 : STD_LOGIC;
signal L1_carry_i_46_n_0 : STD_LOGIC;
signal L1_carry_i_47_n_0 : STD_LOGIC;
signal L1_carry_i_48_n_0 : STD_LOGIC;
signal L1_carry_i_49_n_0 : STD_LOGIC;
signal L1_carry_i_4_n_0 : STD_LOGIC;
signal L1_carry_i_50_n_0 : STD_LOGIC;
signal L1_carry_i_51_n_0 : STD_LOGIC;
signal L1_carry_i_52_n_0 : STD_LOGIC;
signal L1_carry_i_53_n_0 : STD_LOGIC;
signal L1_carry_i_54_n_0 : STD_LOGIC;
signal L1_carry_i_5_n_0 : STD_LOGIC;
signal L1_carry_i_6_n_0 : STD_LOGIC;
signal L1_carry_i_7_n_0 : STD_LOGIC;
signal L1_carry_i_8_n_0 : STD_LOGIC;
signal L1_carry_i_9_n_0 : STD_LOGIC;
signal L1_carry_n_0 : STD_LOGIC;
signal L1_carry_n_1 : STD_LOGIC;
signal L1_carry_n_2 : STD_LOGIC;
signal L1_carry_n_3 : STD_LOGIC;
signal \_carry__0_i_1_n_0\ : STD_LOGIC;
signal \_carry__0_i_2_n_0\ : STD_LOGIC;
signal \_carry__0_i_3_n_0\ : STD_LOGIC;
signal \_carry__0_i_4_n_0\ : STD_LOGIC;
signal \_carry__0_n_0\ : STD_LOGIC;
signal \_carry__0_n_1\ : STD_LOGIC;
signal \_carry__0_n_2\ : STD_LOGIC;
signal \_carry__0_n_3\ : STD_LOGIC;
signal \_carry__0_n_4\ : STD_LOGIC;
signal \_carry__0_n_5\ : STD_LOGIC;
signal \_carry__0_n_6\ : STD_LOGIC;
signal \_carry__0_n_7\ : STD_LOGIC;
signal \_carry__1_i_1_n_0\ : STD_LOGIC;
signal \_carry__1_i_2_n_0\ : STD_LOGIC;
signal \_carry__1_i_3_n_0\ : STD_LOGIC;
signal \_carry__1_i_4_n_0\ : STD_LOGIC;
signal \_carry__1_n_0\ : STD_LOGIC;
signal \_carry__1_n_1\ : STD_LOGIC;
signal \_carry__1_n_2\ : STD_LOGIC;
signal \_carry__1_n_3\ : STD_LOGIC;
signal \_carry__1_n_4\ : STD_LOGIC;
signal \_carry__1_n_5\ : STD_LOGIC;
signal \_carry__1_n_6\ : STD_LOGIC;
signal \_carry__1_n_7\ : STD_LOGIC;
signal \_carry__2_i_1_n_0\ : STD_LOGIC;
signal \_carry__2_i_2_n_0\ : STD_LOGIC;
signal \_carry__2_i_3_n_0\ : STD_LOGIC;
signal \_carry__2_i_4_n_0\ : STD_LOGIC;
signal \_carry__2_n_0\ : STD_LOGIC;
signal \_carry__2_n_1\ : STD_LOGIC;
signal \_carry__2_n_2\ : STD_LOGIC;
signal \_carry__2_n_3\ : STD_LOGIC;
signal \_carry__2_n_4\ : STD_LOGIC;
signal \_carry__2_n_5\ : STD_LOGIC;
signal \_carry__2_n_6\ : STD_LOGIC;
signal \_carry__2_n_7\ : STD_LOGIC;
signal \_carry__3_i_1_n_0\ : STD_LOGIC;
signal \_carry__3_i_2_n_0\ : STD_LOGIC;
signal \_carry__3_i_3_n_0\ : STD_LOGIC;
signal \_carry__3_i_4_n_0\ : STD_LOGIC;
signal \_carry__3_n_0\ : STD_LOGIC;
signal \_carry__3_n_1\ : STD_LOGIC;
signal \_carry__3_n_2\ : STD_LOGIC;
signal \_carry__3_n_3\ : STD_LOGIC;
signal \_carry__3_n_4\ : STD_LOGIC;
signal \_carry__3_n_5\ : STD_LOGIC;
signal \_carry__3_n_6\ : STD_LOGIC;
signal \_carry__3_n_7\ : STD_LOGIC;
signal \_carry__4_i_1_n_0\ : STD_LOGIC;
signal \_carry__4_i_2_n_0\ : STD_LOGIC;
signal \_carry__4_i_3_n_0\ : STD_LOGIC;
signal \_carry__4_i_4_n_0\ : STD_LOGIC;
signal \_carry__4_n_0\ : STD_LOGIC;
signal \_carry__4_n_1\ : STD_LOGIC;
signal \_carry__4_n_2\ : STD_LOGIC;
signal \_carry__4_n_3\ : STD_LOGIC;
signal \_carry__4_n_4\ : STD_LOGIC;
signal \_carry__4_n_5\ : STD_LOGIC;
signal \_carry__4_n_6\ : STD_LOGIC;
signal \_carry__4_n_7\ : STD_LOGIC;
signal \_carry__5_i_1_n_0\ : STD_LOGIC;
signal \_carry__5_i_2_n_0\ : STD_LOGIC;
signal \_carry__5_i_3_n_0\ : STD_LOGIC;
signal \_carry__5_i_4_n_0\ : STD_LOGIC;
signal \_carry__5_n_0\ : STD_LOGIC;
signal \_carry__5_n_1\ : STD_LOGIC;
signal \_carry__5_n_2\ : STD_LOGIC;
signal \_carry__5_n_3\ : STD_LOGIC;
signal \_carry__5_n_4\ : STD_LOGIC;
signal \_carry__5_n_5\ : STD_LOGIC;
signal \_carry__5_n_6\ : STD_LOGIC;
signal \_carry__5_n_7\ : STD_LOGIC;
signal \_carry__6_i_1_n_0\ : STD_LOGIC;
signal \_carry__6_i_2_n_0\ : STD_LOGIC;
signal \_carry__6_n_3\ : STD_LOGIC;
signal \_carry__6_n_6\ : STD_LOGIC;
signal \_carry__6_n_7\ : STD_LOGIC;
signal \_carry_i_10_n_0\ : STD_LOGIC;
signal \_carry_i_11_n_0\ : STD_LOGIC;
signal \_carry_i_12_n_0\ : STD_LOGIC;
signal \_carry_i_13_n_0\ : STD_LOGIC;
signal \_carry_i_14_n_0\ : STD_LOGIC;
signal \_carry_i_15_n_0\ : STD_LOGIC;
signal \_carry_i_16_n_0\ : STD_LOGIC;
signal \_carry_i_17_n_0\ : STD_LOGIC;
signal \_carry_i_18_n_0\ : STD_LOGIC;
signal \_carry_i_19_n_0\ : STD_LOGIC;
signal \_carry_i_1_n_0\ : STD_LOGIC;
signal \_carry_i_20_n_0\ : STD_LOGIC;
signal \_carry_i_21_n_0\ : STD_LOGIC;
signal \_carry_i_22_n_0\ : STD_LOGIC;
signal \_carry_i_23_n_0\ : STD_LOGIC;
signal \_carry_i_24_n_0\ : STD_LOGIC;
signal \_carry_i_2_n_0\ : STD_LOGIC;
signal \_carry_i_3_n_0\ : STD_LOGIC;
signal \_carry_i_4_n_0\ : STD_LOGIC;
signal \_carry_i_6_n_0\ : STD_LOGIC;
signal \_carry_i_7_n_0\ : STD_LOGIC;
signal \_carry_i_8_n_0\ : STD_LOGIC;
signal \_carry_i_9_n_0\ : STD_LOGIC;
signal \_carry_n_0\ : STD_LOGIC;
signal \_carry_n_1\ : STD_LOGIC;
signal \_carry_n_2\ : STD_LOGIC;
signal \_carry_n_3\ : STD_LOGIC;
signal \_carry_n_4\ : STD_LOGIC;
signal \_carry_n_5\ : STD_LOGIC;
signal \_carry_n_6\ : STD_LOGIC;
signal \_carry_n_7\ : STD_LOGIC;
signal data0 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal data1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \msb1__1\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal msb1_n_106 : STD_LOGIC;
signal msb1_n_107 : STD_LOGIC;
signal msb1_n_108 : STD_LOGIC;
signal msb1_n_109 : STD_LOGIC;
signal msb1_n_110 : STD_LOGIC;
signal msb1_n_111 : STD_LOGIC;
signal msb1_n_112 : STD_LOGIC;
signal msb1_n_113 : STD_LOGIC;
signal msb1_n_114 : STD_LOGIC;
signal msb1_n_115 : STD_LOGIC;
signal msb1_n_116 : STD_LOGIC;
signal msb1_n_117 : STD_LOGIC;
signal msb1_n_118 : STD_LOGIC;
signal msb1_n_119 : STD_LOGIC;
signal msb1_n_120 : STD_LOGIC;
signal msb1_n_121 : STD_LOGIC;
signal msb1_n_122 : STD_LOGIC;
signal msb1_n_123 : STD_LOGIC;
signal msb1_n_124 : STD_LOGIC;
signal msb1_n_125 : STD_LOGIC;
signal msb1_n_126 : STD_LOGIC;
signal msb1_n_127 : STD_LOGIC;
signal msb1_n_128 : STD_LOGIC;
signal msb1_n_129 : STD_LOGIC;
signal msb1_n_130 : STD_LOGIC;
signal msb1_n_131 : STD_LOGIC;
signal msb1_n_132 : STD_LOGIC;
signal msb1_n_133 : STD_LOGIC;
signal msb1_n_134 : STD_LOGIC;
signal msb1_n_135 : STD_LOGIC;
signal msb1_n_136 : STD_LOGIC;
signal msb1_n_137 : STD_LOGIC;
signal msb1_n_138 : STD_LOGIC;
signal msb1_n_139 : STD_LOGIC;
signal msb1_n_140 : STD_LOGIC;
signal msb1_n_141 : STD_LOGIC;
signal msb1_n_142 : STD_LOGIC;
signal msb1_n_143 : STD_LOGIC;
signal msb1_n_144 : STD_LOGIC;
signal msb1_n_145 : STD_LOGIC;
signal msb1_n_146 : STD_LOGIC;
signal msb1_n_147 : STD_LOGIC;
signal msb1_n_148 : STD_LOGIC;
signal msb1_n_149 : STD_LOGIC;
signal msb1_n_150 : STD_LOGIC;
signal msb1_n_151 : STD_LOGIC;
signal msb1_n_152 : STD_LOGIC;
signal msb1_n_153 : STD_LOGIC;
signal msb1_n_58 : STD_LOGIC;
signal msb1_n_59 : STD_LOGIC;
signal msb1_n_60 : STD_LOGIC;
signal msb1_n_61 : STD_LOGIC;
signal msb1_n_62 : STD_LOGIC;
signal msb1_n_63 : STD_LOGIC;
signal msb1_n_64 : STD_LOGIC;
signal msb1_n_65 : STD_LOGIC;
signal msb1_n_66 : STD_LOGIC;
signal msb1_n_67 : STD_LOGIC;
signal msb1_n_68 : STD_LOGIC;
signal msb1_n_69 : STD_LOGIC;
signal msb1_n_70 : STD_LOGIC;
signal msb1_n_71 : STD_LOGIC;
signal msb1_n_72 : STD_LOGIC;
signal msb1_n_73 : STD_LOGIC;
signal msb1_n_74 : STD_LOGIC;
signal msb1_n_75 : STD_LOGIC;
signal msb1_n_76 : STD_LOGIC;
signal msb1_n_77 : STD_LOGIC;
signal msb1_n_78 : STD_LOGIC;
signal msb1_n_79 : STD_LOGIC;
signal msb1_n_80 : STD_LOGIC;
signal msb1_n_81 : STD_LOGIC;
signal msb1_n_82 : STD_LOGIC;
signal msb1_n_83 : STD_LOGIC;
signal msb1_n_84 : STD_LOGIC;
signal msb1_n_85 : STD_LOGIC;
signal msb1_n_86 : STD_LOGIC;
signal msb1_n_87 : STD_LOGIC;
signal msb1_n_88 : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 1 to 1 );
signal sel0 : STD_LOGIC_VECTOR ( 22 downto 0 );
signal \y_11__s_net_1\ : STD_LOGIC;
signal \z[11]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_1_n_1\ : STD_LOGIC;
signal \z[11]_INST_0_i_1_n_2\ : STD_LOGIC;
signal \z[11]_INST_0_i_1_n_3\ : STD_LOGIC;
signal \z[11]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \z[15]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[15]_INST_0_i_1_n_1\ : STD_LOGIC;
signal \z[15]_INST_0_i_1_n_2\ : STD_LOGIC;
signal \z[15]_INST_0_i_1_n_3\ : STD_LOGIC;
signal \z[15]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[15]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \z[15]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \z[19]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[19]_INST_0_i_1_n_1\ : STD_LOGIC;
signal \z[19]_INST_0_i_1_n_2\ : STD_LOGIC;
signal \z[19]_INST_0_i_1_n_3\ : STD_LOGIC;
signal \z[22]_INST_0_i_1_n_2\ : STD_LOGIC;
signal \z[22]_INST_0_i_1_n_3\ : STD_LOGIC;
signal \z[22]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_100_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_101_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_102_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_103_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_104_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_105_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_106_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_107_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_108_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_109_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_110_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_111_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_112_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_113_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_114_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_115_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_116_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_117_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_118_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_119_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_120_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_121_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_122_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_123_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_124_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_125_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_126_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_127_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_128_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_129_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_130_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_131_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_132_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_133_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_134_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_135_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_136_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_137_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_138_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_139_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_13_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_140_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_141_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_142_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_143_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_144_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_145_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_146_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_147_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_148_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_149_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_14_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_150_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_151_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_152_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_153_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_154_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_155_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_156_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_157_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_158_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_159_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_15_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_160_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_161_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_162_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_163_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_164_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_165_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_166_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_167_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_168_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_169_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_16_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_170_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_171_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_172_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_173_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_174_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_175_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_176_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_177_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_178_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_179_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_17_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_180_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_181_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_182_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_183_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_184_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_185_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_186_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_187_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_188_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_189_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_18_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_190_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_191_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_192_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_193_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_194_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_195_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_196_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_197_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_198_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_199_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_19_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_200_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_201_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_202_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_203_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_204_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_205_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_206_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_207_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_208_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_209_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_20_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_210_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_211_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_212_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_213_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_214_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_215_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_216_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_217_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_218_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_219_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_21_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_220_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_221_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_222_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_223_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_224_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_225_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_226_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_227_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_228_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_229_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_22_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_230_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_231_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_232_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_233_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_234_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_235_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_236_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_237_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_238_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_239_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_240_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_241_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_242_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_243_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_244_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_245_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_246_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_29_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_30_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_31_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_32_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_33_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_34_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_35_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_36_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_37_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_38_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_39_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_40_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_41_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_42_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_43_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_44_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_45_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_46_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_47_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_48_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_49_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_50_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_51_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_52_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_53_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_54_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_55_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_56_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_57_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_58_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_59_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_60_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_61_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_62_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_63_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_64_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_65_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_66_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_67_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_68_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_69_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_70_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_71_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_72_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_73_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_74_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_75_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_76_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_77_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_78_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_79_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_80_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_81_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_82_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_83_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_94_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_95_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_96_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_97_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_98_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_99_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_1_n_1\ : STD_LOGIC;
signal \z[3]_INST_0_i_1_n_2\ : STD_LOGIC;
signal \z[3]_INST_0_i_1_n_3\ : STD_LOGIC;
signal \z[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_12_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_1_n_1\ : STD_LOGIC;
signal \z[7]_INST_0_i_1_n_2\ : STD_LOGIC;
signal \z[7]_INST_0_i_1_n_3\ : STD_LOGIC;
signal \z[7]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_5_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_6_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_7_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_8_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_n_1\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_n_2\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_n_3\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_1_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_2_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_3_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_4_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_5_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_6_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_7_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_n_1\ : STD_LOGIC;
signal \z_exponent0__0_carry_n_2\ : STD_LOGIC;
signal \z_exponent0__0_carry_n_3\ : STD_LOGIC;
signal \z_exponent1_carry__0_n_1\ : STD_LOGIC;
signal \z_exponent1_carry__0_n_2\ : STD_LOGIC;
signal \z_exponent1_carry__0_n_3\ : STD_LOGIC;
signal \z_exponent1_carry_i_1__0_n_0\ : STD_LOGIC;
signal z_exponent1_carry_i_1_n_0 : STD_LOGIC;
signal \z_exponent1_carry_i_2__0_n_0\ : STD_LOGIC;
signal z_exponent1_carry_i_2_n_0 : STD_LOGIC;
signal \z_exponent1_carry_i_3__0_n_0\ : STD_LOGIC;
signal z_exponent1_carry_i_3_n_0 : STD_LOGIC;
signal \z_exponent1_carry_i_4__0_n_0\ : STD_LOGIC;
signal z_exponent1_carry_i_4_n_0 : STD_LOGIC;
signal z_exponent1_carry_i_5_n_0 : STD_LOGIC;
signal z_exponent1_carry_n_0 : STD_LOGIC;
signal z_exponent1_carry_n_1 : STD_LOGIC;
signal z_exponent1_carry_n_2 : STD_LOGIC;
signal z_exponent1_carry_n_3 : STD_LOGIC;
signal NLW_L1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_L1_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_L1_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_L1_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW__carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW__carry__6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_msb1_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_msb1_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_msb1_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_msb1_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_msb1_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_msb1_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_msb1_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_msb1_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_msb1_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_msb1__0_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_msb1__0_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_msb1__0_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_msb1__0_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_msb1__0_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_msb1__0_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_msb1__0_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_msb1__0_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_msb1__0_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_msb1__0_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 31 );
signal \NLW_msb1__0_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_z[22]_INST_0_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_z[22]_INST_0_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_z_exponent0__0_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_z_exponent1_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of L1_carry_i_18 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of L1_carry_i_19 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of L1_carry_i_22 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of L1_carry_i_23 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of L1_carry_i_27 : label is "soft_lutpair44";
attribute SOFT_HLUTNM of L1_carry_i_30 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of L1_carry_i_31 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of L1_carry_i_33 : label is "soft_lutpair30";
attribute SOFT_HLUTNM of L1_carry_i_34 : label is "soft_lutpair27";
attribute SOFT_HLUTNM of L1_carry_i_36 : label is "soft_lutpair31";
attribute SOFT_HLUTNM of L1_carry_i_39 : label is "soft_lutpair29";
attribute SOFT_HLUTNM of L1_carry_i_46 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of L1_carry_i_47 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of L1_carry_i_49 : label is "soft_lutpair24";
attribute SOFT_HLUTNM of L1_carry_i_52 : label is "soft_lutpair29";
attribute SOFT_HLUTNM of L1_carry_i_53 : label is "soft_lutpair31";
attribute SOFT_HLUTNM of L1_carry_i_54 : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \_carry_i_11\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \_carry_i_18\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \_carry_i_19\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \_carry_i_20\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \_carry_i_22\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \_carry_i_24\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \_carry_i_6\ : label is "soft_lutpair27";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of msb1 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \msb1__0\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute SOFT_HLUTNM of \z[11]_INST_0_i_8\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \z[11]_INST_0_i_9\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \z[15]_INST_0_i_8\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_102\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_111\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_112\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_113\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_114\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_173\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_174\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_175\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_176\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_177\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_178\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_179\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_180\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_181\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_182\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_183\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_184\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_185\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_186\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_187\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_188\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_191\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_192\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_197\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_198\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_202\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_203\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_204\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_205\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_212\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_213\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_214\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_215\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_216\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_217\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_220\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_231\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_246\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_31\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_37\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_38\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_39\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_43\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_44\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_47\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_48\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_49\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_50\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_51\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_52\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_57\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_59\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_62\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_63\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_65\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_68\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_70\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_72\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_77\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_79\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_95\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_97\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \z[7]_INST_0_i_10\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \z[7]_INST_0_i_12\ : label is "soft_lutpair32";
attribute HLUTNM : string;
attribute HLUTNM of \z_exponent0__0_carry__0_i_2\ : label is "lutpair3";
attribute SOFT_HLUTNM of \z_exponent0__0_carry__0_i_8\ : label is "soft_lutpair2";
attribute HLUTNM of \z_exponent0__0_carry_i_1\ : label is "lutpair2";
attribute HLUTNM of \z_exponent0__0_carry_i_2\ : label is "lutpair1";
attribute HLUTNM of \z_exponent0__0_carry_i_3\ : label is "lutpair0";
attribute HLUTNM of \z_exponent0__0_carry_i_7\ : label is "lutpair0";
attribute HLUTNM of \z_exponent1_carry_i_1__0\ : label is "lutpair4";
attribute HLUTNM of \z_exponent1_carry_i_3__0\ : label is "lutpair2";
attribute HLUTNM of z_exponent1_carry_i_4 : label is "lutpair1";
attribute HLUTNM of \z_exponent1_carry_i_4__0\ : label is "lutpair3";
attribute HLUTNM of z_exponent1_carry_i_5 : label is "lutpair4";
begin
\y_11__s_net_1\ <= \y_11__s_port_\;
L1_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => L1_carry_n_0,
CO(2) => L1_carry_n_1,
CO(1) => L1_carry_n_2,
CO(0) => L1_carry_n_3,
CYINIT => '1',
DI(3) => L1_carry_i_1_n_0,
DI(2) => L1_carry_i_2_n_0,
DI(1) => L1_carry_i_3_n_0,
DI(0) => L1_carry_i_4_n_0,
O(3 downto 0) => NLW_L1_carry_O_UNCONNECTED(3 downto 0),
S(3) => L1_carry_i_5_n_0,
S(2) => L1_carry_i_6_n_0,
S(1) => L1_carry_i_7_n_0,
S(0) => L1_carry_i_8_n_0
);
\L1_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => L1_carry_n_0,
CO(3) => \L1_carry__0_n_0\,
CO(2) => \L1_carry__0_n_1\,
CO(1) => \L1_carry__0_n_2\,
CO(0) => \L1_carry__0_n_3\,
CYINIT => '0',
DI(3) => \L1_carry__0_i_1_n_0\,
DI(2) => \L1_carry__0_i_2_n_0\,
DI(1) => \L1_carry__0_i_3_n_0\,
DI(0) => \L1_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_L1_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \L1_carry__0_i_5_n_0\,
S(2) => \L1_carry__0_i_6_n_0\,
S(1) => \L1_carry__0_i_7_n_0\,
S(0) => \L1_carry__0_i_8_n_0\
);
\L1_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_1_n_0\
);
\L1_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_2_n_0\
);
\L1_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_3_n_0\
);
\L1_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_4_n_0\
);
\L1_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_5_n_0\
);
\L1_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_6_n_0\
);
\L1_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_7_n_0\
);
\L1_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_8_n_0\
);
\L1_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \L1_carry__0_n_0\,
CO(3) => \L1_carry__1_n_0\,
CO(2) => \L1_carry__1_n_1\,
CO(1) => \L1_carry__1_n_2\,
CO(0) => \L1_carry__1_n_3\,
CYINIT => '0',
DI(3) => \L1_carry__1_i_1_n_0\,
DI(2) => \L1_carry__1_i_2_n_0\,
DI(1) => \L1_carry__1_i_3_n_0\,
DI(0) => \L1_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_L1_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \L1_carry__1_i_5_n_0\,
S(2) => \L1_carry__1_i_6_n_0\,
S(1) => \L1_carry__1_i_7_n_0\,
S(0) => \L1_carry__1_i_8_n_0\
);
\L1_carry__1_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_1_n_0\
);
\L1_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_2_n_0\
);
\L1_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_3_n_0\
);
\L1_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_4_n_0\
);
\L1_carry__1_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_5_n_0\
);
\L1_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_6_n_0\
);
\L1_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_7_n_0\
);
\L1_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_8_n_0\
);
\L1_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \L1_carry__1_n_0\,
CO(3) => L1,
CO(2) => \L1_carry__2_n_1\,
CO(1) => \L1_carry__2_n_2\,
CO(0) => \L1_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \L1_carry__2_i_1_n_0\,
DI(1) => \L1_carry__2_i_2_n_0\,
DI(0) => \L1_carry__2_i_3_n_0\,
O(3 downto 0) => \NLW_L1_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \L1_carry__2_i_4_n_0\,
S(2) => \L1_carry__2_i_5_n_0\,
S(1) => \L1_carry__2_i_6_n_0\,
S(0) => \L1_carry__2_i_7_n_0\
);
\L1_carry__2_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_1_n_0\
);
\L1_carry__2_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_2_n_0\
);
\L1_carry__2_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_3_n_0\
);
\L1_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_4_n_0\
);
\L1_carry__2_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_5_n_0\
);
\L1_carry__2_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_6_n_0\
);
\L1_carry__2_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_7_n_0\
);
L1_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => L1_carry_i_1_n_0
);
L1_carry_i_10: unisim.vcomponents.LUT6
generic map(
INIT => X"4555FFFF45554555"
)
port map (
I0 => L1_carry_i_24_n_0,
I1 => L1_carry_i_25_n_0,
I2 => L1_carry_i_26_n_0,
I3 => L1_carry_i_27_n_0,
I4 => L1_carry_i_28_n_0,
I5 => L1_carry_i_29_n_0,
O => L1_carry_i_10_n_0
);
L1_carry_i_11: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFF7550000"
)
port map (
I0 => L1_carry_i_30_n_0,
I1 => L1_carry_i_31_n_0,
I2 => L1_carry_i_32_n_0,
I3 => L1_carry_i_33_n_0,
I4 => L1_carry_i_34_n_0,
I5 => L1_carry_i_35_n_0,
O => L1_carry_i_11_n_0
);
L1_carry_i_12: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => L1_carry_i_22_n_0,
I2 => L1_carry_i_19_n_0,
O => L1_carry_i_12_n_0
);
L1_carry_i_13: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \msb1__1\(40),
I1 => \msb1__1\(41),
I2 => \msb1__1\(43),
I3 => \msb1__1\(42),
I4 => L1_carry_i_34_n_0,
I5 => L1_carry_i_23_n_0,
O => L1_carry_i_13_n_0
);
L1_carry_i_14: unisim.vcomponents.LUT5
generic map(
INIT => X"A9AA5555"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_10_n_0,
I3 => \_carry_i_1_n_0\,
I4 => L1_carry_i_9_n_0,
O => L1_carry_i_14_n_0
);
L1_carry_i_15: unisim.vcomponents.LUT6
generic map(
INIT => X"0200AAAAFDFF5555"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_10_n_0,
I3 => \_carry_i_1_n_0\,
I4 => L1_carry_i_9_n_0,
I5 => L1_carry_i_13_n_0,
O => L1_carry_i_15_n_0
);
L1_carry_i_16: unisim.vcomponents.LUT3
generic map(
INIT => X"65"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_10_n_0,
I2 => \_carry_i_1_n_0\,
O => L1_carry_i_16_n_0
);
L1_carry_i_17: unisim.vcomponents.LUT4
generic map(
INIT => X"10EF"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_10_n_0,
I2 => \_carry_i_1_n_0\,
I3 => L1_carry_i_9_n_0,
O => L1_carry_i_17_n_0
);
L1_carry_i_18: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => L1_carry_i_34_n_0,
I1 => \msb1__1\(42),
I2 => \msb1__1\(43),
I3 => \msb1__1\(41),
I4 => \msb1__1\(40),
O => L1_carry_i_18_n_0
);
L1_carry_i_19: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => L1_carry_i_36_n_0,
I1 => \msb1__1\(26),
I2 => \msb1__1\(27),
I3 => \msb1__1\(25),
I4 => \msb1__1\(24),
O => L1_carry_i_19_n_0
);
L1_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => L1_carry_i_14_n_0,
I1 => L1_carry_i_15_n_0,
O => L1_carry_i_2_n_0
);
L1_carry_i_20: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(10),
I1 => \msb1__1\(11),
I2 => \msb1__1\(9),
I3 => \msb1__1\(8),
O => L1_carry_i_20_n_0
);
L1_carry_i_21: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \msb1__1\(14),
I1 => \msb1__1\(15),
I2 => \msb1__1\(13),
I3 => \msb1__1\(12),
O => L1_carry_i_21_n_0
);
L1_carry_i_22: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => L1_carry_i_37_n_0,
I1 => \msb1__1\(16),
I2 => \msb1__1\(17),
I3 => \msb1__1\(19),
I4 => \msb1__1\(18),
O => L1_carry_i_22_n_0
);
L1_carry_i_23: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => L1_carry_i_33_n_0,
I1 => \msb1__1\(32),
I2 => \msb1__1\(33),
I3 => \msb1__1\(35),
I4 => \msb1__1\(34),
O => L1_carry_i_23_n_0
);
L1_carry_i_24: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF000EFFFF"
)
port map (
I0 => \msb1__1\(39),
I1 => \msb1__1\(38),
I2 => \msb1__1\(41),
I3 => \msb1__1\(40),
I4 => L1_carry_i_29_n_0,
I5 => L1_carry_i_38_n_0,
O => L1_carry_i_24_n_0
);
L1_carry_i_25: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000F100"
)
port map (
I0 => L1_carry_i_39_n_0,
I1 => L1_carry_i_40_n_0,
I2 => L1_carry_i_41_n_0,
I3 => L1_carry_i_42_n_0,
I4 => \msb1__1\(35),
I5 => \msb1__1\(34),
O => L1_carry_i_25_n_0
);
L1_carry_i_26: unisim.vcomponents.LUT6
generic map(
INIT => X"1111110011111101"
)
port map (
I0 => \msb1__1\(37),
I1 => \msb1__1\(36),
I2 => \msb1__1\(33),
I3 => \msb1__1\(34),
I4 => \msb1__1\(35),
I5 => \msb1__1\(32),
O => L1_carry_i_26_n_0
);
L1_carry_i_27: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(41),
I1 => \msb1__1\(40),
O => L1_carry_i_27_n_0
);
L1_carry_i_28: unisim.vcomponents.LUT6
generic map(
INIT => X"1111111011111111"
)
port map (
I0 => \msb1__1\(45),
I1 => \msb1__1\(44),
I2 => L1_carry_i_43_n_0,
I3 => L1_carry_i_44_n_0,
I4 => L1_carry_i_39_n_0,
I5 => L1_carry_i_45_n_0,
O => L1_carry_i_28_n_0
);
L1_carry_i_29: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(46),
I1 => \msb1__1\(47),
O => L1_carry_i_29_n_0
);
L1_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => L1_carry_i_16_n_0,
I1 => L1_carry_i_17_n_0,
O => L1_carry_i_3_n_0
);
L1_carry_i_30: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(40),
I1 => \msb1__1\(41),
I2 => \msb1__1\(43),
I3 => \msb1__1\(42),
O => L1_carry_i_30_n_0
);
L1_carry_i_31: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(34),
I1 => \msb1__1\(35),
I2 => \msb1__1\(33),
I3 => \msb1__1\(32),
O => L1_carry_i_31_n_0
);
L1_carry_i_32: unisim.vcomponents.LUT6
generic map(
INIT => X"8A888A888A88AA88"
)
port map (
I0 => L1_carry_i_36_n_0,
I1 => L1_carry_i_46_n_0,
I2 => L1_carry_i_47_n_0,
I3 => L1_carry_i_37_n_0,
I4 => L1_carry_i_20_n_0,
I5 => L1_carry_i_21_n_0,
O => L1_carry_i_32_n_0
);
L1_carry_i_33: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(37),
I1 => \msb1__1\(36),
I2 => \msb1__1\(38),
I3 => \msb1__1\(39),
O => L1_carry_i_33_n_0
);
L1_carry_i_34: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(47),
I1 => \msb1__1\(46),
I2 => \msb1__1\(45),
I3 => \msb1__1\(44),
O => L1_carry_i_34_n_0
);
L1_carry_i_35: unisim.vcomponents.LUT6
generic map(
INIT => X"0000400000000000"
)
port map (
I0 => L1_carry_i_48_n_0,
I1 => L1_carry_i_49_n_0,
I2 => L1_carry_i_34_n_0,
I3 => L1_carry_i_36_n_0,
I4 => L1_carry_i_21_n_0,
I5 => L1_carry_i_37_n_0,
O => L1_carry_i_35_n_0
);
L1_carry_i_36: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(28),
I1 => \msb1__1\(29),
I2 => \msb1__1\(30),
I3 => \msb1__1\(31),
O => L1_carry_i_36_n_0
);
L1_carry_i_37: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(23),
I1 => \msb1__1\(22),
I2 => \msb1__1\(20),
I3 => \msb1__1\(21),
O => L1_carry_i_37_n_0
);
L1_carry_i_38: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(42),
I1 => \msb1__1\(43),
O => L1_carry_i_38_n_0
);
L1_carry_i_39: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \msb1__1\(23),
I1 => \msb1__1\(22),
I2 => \msb1__1\(18),
I3 => \msb1__1\(19),
O => L1_carry_i_39_n_0
);
L1_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"D"
)
port map (
I0 => \_carry_i_1_n_0\,
I1 => L1_carry_i_10_n_0,
O => L1_carry_i_4_n_0
);
L1_carry_i_40: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000FFF2"
)
port map (
I0 => L1_carry_i_50_n_0,
I1 => L1_carry_i_51_n_0,
I2 => \msb1__1\(15),
I3 => \msb1__1\(14),
I4 => \msb1__1\(17),
I5 => \msb1__1\(16),
O => L1_carry_i_40_n_0
);
L1_carry_i_41: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFE0FF"
)
port map (
I0 => \msb1__1\(21),
I1 => \msb1__1\(20),
I2 => L1_carry_i_52_n_0,
I3 => L1_carry_i_53_n_0,
I4 => \msb1__1\(25),
I5 => \msb1__1\(24),
O => L1_carry_i_41_n_0
);
L1_carry_i_42: unisim.vcomponents.LUT6
generic map(
INIT => X"1111111111110001"
)
port map (
I0 => \msb1__1\(30),
I1 => \msb1__1\(31),
I2 => \msb1__1\(26),
I3 => \msb1__1\(27),
I4 => \msb1__1\(29),
I5 => \msb1__1\(28),
O => L1_carry_i_42_n_0
);
L1_carry_i_43: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFEFFFF"
)
port map (
I0 => \msb1__1\(2),
I1 => \msb1__1\(3),
I2 => \msb1__1\(26),
I3 => \msb1__1\(27),
I4 => L1_carry_i_54_n_0,
I5 => L1_carry_i_38_n_0,
O => L1_carry_i_43_n_0
);
L1_carry_i_44: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \msb1__1\(7),
I1 => \msb1__1\(6),
I2 => \msb1__1\(10),
I3 => \msb1__1\(11),
O => L1_carry_i_44_n_0
);
L1_carry_i_45: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \msb1__1\(34),
I1 => \msb1__1\(35),
I2 => \msb1__1\(15),
I3 => \msb1__1\(14),
I4 => \msb1__1\(31),
I5 => \msb1__1\(30),
O => L1_carry_i_45_n_0
);
L1_carry_i_46: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \msb1__1\(24),
I1 => \msb1__1\(25),
I2 => \msb1__1\(27),
I3 => \msb1__1\(26),
O => L1_carry_i_46_n_0
);
L1_carry_i_47: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(18),
I1 => \msb1__1\(19),
I2 => \msb1__1\(17),
I3 => \msb1__1\(16),
O => L1_carry_i_47_n_0
);
L1_carry_i_48: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \msb1__1\(7),
I1 => \msb1__1\(6),
I2 => \msb1__1\(39),
I3 => \msb1__1\(38),
I4 => \msb1__1\(36),
I5 => \msb1__1\(37),
O => L1_carry_i_48_n_0
);
L1_carry_i_49: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(5),
I1 => \msb1__1\(4),
O => L1_carry_i_49_n_0
);
L1_carry_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => L1_carry_i_5_n_0
);
L1_carry_i_50: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF1"
)
port map (
I0 => \msb1__1\(4),
I1 => \msb1__1\(5),
I2 => \msb1__1\(11),
I3 => \msb1__1\(10),
I4 => \msb1__1\(6),
I5 => \msb1__1\(7),
O => L1_carry_i_50_n_0
);
L1_carry_i_51: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEEEEEEFFFE"
)
port map (
I0 => \msb1__1\(13),
I1 => \msb1__1\(12),
I2 => \msb1__1\(8),
I3 => \msb1__1\(9),
I4 => \msb1__1\(11),
I5 => \msb1__1\(10),
O => L1_carry_i_51_n_0
);
L1_carry_i_52: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(22),
I1 => \msb1__1\(23),
O => L1_carry_i_52_n_0
);
L1_carry_i_53: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(29),
I1 => \msb1__1\(28),
O => L1_carry_i_53_n_0
);
L1_carry_i_54: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(39),
I1 => \msb1__1\(38),
O => L1_carry_i_54_n_0
);
L1_carry_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => L1_carry_i_15_n_0,
I1 => L1_carry_i_14_n_0,
O => L1_carry_i_6_n_0
);
L1_carry_i_7: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => L1_carry_i_17_n_0,
I1 => L1_carry_i_16_n_0,
O => L1_carry_i_7_n_0
);
L1_carry_i_8: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \_carry_i_1_n_0\,
I1 => L1_carry_i_10_n_0,
O => L1_carry_i_8_n_0
);
L1_carry_i_9: unisim.vcomponents.LUT6
generic map(
INIT => X"00808888AAAAAAAA"
)
port map (
I0 => L1_carry_i_18_n_0,
I1 => L1_carry_i_19_n_0,
I2 => L1_carry_i_20_n_0,
I3 => L1_carry_i_21_n_0,
I4 => L1_carry_i_22_n_0,
I5 => L1_carry_i_23_n_0,
O => L1_carry_i_9_n_0
);
\_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \_carry_n_0\,
CO(2) => \_carry_n_1\,
CO(1) => \_carry_n_2\,
CO(0) => \_carry_n_3\,
CYINIT => \_carry_i_1_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \_carry_n_4\,
O(2) => \_carry_n_5\,
O(1) => \_carry_n_6\,
O(0) => \_carry_n_7\,
S(3) => \_carry_i_2_n_0\,
S(2) => \_carry_i_3_n_0\,
S(1) => \_carry_i_4_n_0\,
S(0) => p_0_in(1)
);
\_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \_carry_n_0\,
CO(3) => \_carry__0_n_0\,
CO(2) => \_carry__0_n_1\,
CO(1) => \_carry__0_n_2\,
CO(0) => \_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \_carry__0_n_4\,
O(2) => \_carry__0_n_5\,
O(1) => \_carry__0_n_6\,
O(0) => \_carry__0_n_7\,
S(3) => \_carry__0_i_1_n_0\,
S(2) => \_carry__0_i_2_n_0\,
S(1) => \_carry__0_i_3_n_0\,
S(0) => \_carry__0_i_4_n_0\
);
\_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__0_i_1_n_0\
);
\_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__0_i_2_n_0\
);
\_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__0_i_3_n_0\
);
\_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0200AAAAFDFF5555"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_10_n_0,
I3 => \_carry_i_1_n_0\,
I4 => L1_carry_i_9_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__0_i_4_n_0\
);
\_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__0_n_0\,
CO(3) => \_carry__1_n_0\,
CO(2) => \_carry__1_n_1\,
CO(1) => \_carry__1_n_2\,
CO(0) => \_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \_carry__1_n_4\,
O(2) => \_carry__1_n_5\,
O(1) => \_carry__1_n_6\,
O(0) => \_carry__1_n_7\,
S(3) => \_carry__1_i_1_n_0\,
S(2) => \_carry__1_i_2_n_0\,
S(1) => \_carry__1_i_3_n_0\,
S(0) => \_carry__1_i_4_n_0\
);
\_carry__1_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__1_i_1_n_0\
);
\_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__1_i_2_n_0\
);
\_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__1_i_3_n_0\
);
\_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__1_i_4_n_0\
);
\_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__1_n_0\,
CO(3) => \_carry__2_n_0\,
CO(2) => \_carry__2_n_1\,
CO(1) => \_carry__2_n_2\,
CO(0) => \_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \_carry__2_n_4\,
O(2) => \_carry__2_n_5\,
O(1) => \_carry__2_n_6\,
O(0) => \_carry__2_n_7\,
S(3) => \_carry__2_i_1_n_0\,
S(2) => \_carry__2_i_2_n_0\,
S(1) => \_carry__2_i_3_n_0\,
S(0) => \_carry__2_i_4_n_0\
);
\_carry__2_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__2_i_1_n_0\
);
\_carry__2_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__2_i_2_n_0\
);
\_carry__2_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__2_i_3_n_0\
);
\_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__2_i_4_n_0\
);
\_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__2_n_0\,
CO(3) => \_carry__3_n_0\,
CO(2) => \_carry__3_n_1\,
CO(1) => \_carry__3_n_2\,
CO(0) => \_carry__3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \_carry__3_n_4\,
O(2) => \_carry__3_n_5\,
O(1) => \_carry__3_n_6\,
O(0) => \_carry__3_n_7\,
S(3) => \_carry__3_i_1_n_0\,
S(2) => \_carry__3_i_2_n_0\,
S(1) => \_carry__3_i_3_n_0\,
S(0) => \_carry__3_i_4_n_0\
);
\_carry__3_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__3_i_1_n_0\
);
\_carry__3_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__3_i_2_n_0\
);
\_carry__3_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__3_i_3_n_0\
);
\_carry__3_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__3_i_4_n_0\
);
\_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__3_n_0\,
CO(3) => \_carry__4_n_0\,
CO(2) => \_carry__4_n_1\,
CO(1) => \_carry__4_n_2\,
CO(0) => \_carry__4_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \_carry__4_n_4\,
O(2) => \_carry__4_n_5\,
O(1) => \_carry__4_n_6\,
O(0) => \_carry__4_n_7\,
S(3) => \_carry__4_i_1_n_0\,
S(2) => \_carry__4_i_2_n_0\,
S(1) => \_carry__4_i_3_n_0\,
S(0) => \_carry__4_i_4_n_0\
);
\_carry__4_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__4_i_1_n_0\
);
\_carry__4_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__4_i_2_n_0\
);
\_carry__4_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__4_i_3_n_0\
);
\_carry__4_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__4_i_4_n_0\
);
\_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__4_n_0\,
CO(3) => \_carry__5_n_0\,
CO(2) => \_carry__5_n_1\,
CO(1) => \_carry__5_n_2\,
CO(0) => \_carry__5_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \_carry__5_n_4\,
O(2) => \_carry__5_n_5\,
O(1) => \_carry__5_n_6\,
O(0) => \_carry__5_n_7\,
S(3) => \_carry__5_i_1_n_0\,
S(2) => \_carry__5_i_2_n_0\,
S(1) => \_carry__5_i_3_n_0\,
S(0) => \_carry__5_i_4_n_0\
);
\_carry__5_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__5_i_1_n_0\
);
\_carry__5_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__5_i_2_n_0\
);
\_carry__5_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__5_i_3_n_0\
);
\_carry__5_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__5_i_4_n_0\
);
\_carry__6\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__5_n_0\,
CO(3 downto 1) => \NLW__carry__6_CO_UNCONNECTED\(3 downto 1),
CO(0) => \_carry__6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW__carry__6_O_UNCONNECTED\(3 downto 2),
O(1) => \_carry__6_n_6\,
O(0) => \_carry__6_n_7\,
S(3 downto 2) => B"00",
S(1) => \_carry__6_i_1_n_0\,
S(0) => \_carry__6_i_2_n_0\
);
\_carry__6_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__6_i_1_n_0\
);
\_carry__6_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__6_i_2_n_0\
);
\_carry_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BBBBABAA"
)
port map (
I0 => \msb1__1\(47),
I1 => \_carry_i_6_n_0\,
I2 => \_carry_i_7_n_0\,
I3 => \_carry_i_8_n_0\,
I4 => \_carry_i_9_n_0\,
O => \_carry_i_1_n_0\
);
\_carry_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \_carry_i_1_n_0\,
I1 => L1_carry_i_10_n_0,
O => \_carry_i_10_n_0\
);
\_carry_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(42),
I1 => \msb1__1\(40),
O => \_carry_i_11_n_0\
);
\_carry_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0FFF0FFFFFFF4"
)
port map (
I0 => \msb1__1\(25),
I1 => \msb1__1\(24),
I2 => \msb1__1\(28),
I3 => \_carry_i_18_n_0\,
I4 => \msb1__1\(26),
I5 => \msb1__1\(27),
O => \_carry_i_12_n_0\
);
\_carry_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0FFF0FFFFFFF4"
)
port map (
I0 => \msb1__1\(15),
I1 => \msb1__1\(14),
I2 => \msb1__1\(18),
I3 => \_carry_i_19_n_0\,
I4 => \msb1__1\(16),
I5 => \msb1__1\(17),
O => \_carry_i_13_n_0\
);
\_carry_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000EFEE"
)
port map (
I0 => \_carry_i_20_n_0\,
I1 => \msb1__1\(7),
I2 => \msb1__1\(6),
I3 => \msb1__1\(5),
I4 => \_carry_i_21_n_0\,
O => \_carry_i_14_n_0\
);
\_carry_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF00BA"
)
port map (
I0 => \msb1__1\(11),
I1 => \msb1__1\(10),
I2 => \msb1__1\(9),
I3 => \msb1__1\(12),
I4 => \_carry_i_22_n_0\,
I5 => \msb1__1\(13),
O => \_carry_i_15_n_0\
);
\_carry_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0FFF0FFFFFFF4"
)
port map (
I0 => \msb1__1\(20),
I1 => \msb1__1\(19),
I2 => \msb1__1\(23),
I3 => \_carry_i_23_n_0\,
I4 => \msb1__1\(21),
I5 => \msb1__1\(22),
O => \_carry_i_16_n_0\
);
\_carry_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0FFF0FFFFFFF4"
)
port map (
I0 => \msb1__1\(30),
I1 => \msb1__1\(29),
I2 => \msb1__1\(33),
I3 => \_carry_i_24_n_0\,
I4 => \msb1__1\(31),
I5 => \msb1__1\(32),
O => \_carry_i_17_n_0\
);
\_carry_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(32),
I1 => \msb1__1\(30),
O => \_carry_i_18_n_0\
);
\_carry_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(22),
I1 => \msb1__1\(20),
O => \_carry_i_19_n_0\
);
\_carry_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"555DAAA2"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
O => \_carry_i_2_n_0\
);
\_carry_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"5504"
)
port map (
I0 => \msb1__1\(4),
I1 => \msb1__1\(1),
I2 => \msb1__1\(2),
I3 => \msb1__1\(3),
O => \_carry_i_20_n_0\
);
\_carry_i_21\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFF4"
)
port map (
I0 => \msb1__1\(7),
I1 => \msb1__1\(6),
I2 => \msb1__1\(12),
I3 => \msb1__1\(10),
I4 => \msb1__1\(8),
O => \_carry_i_21_n_0\
);
\_carry_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(17),
I1 => \msb1__1\(15),
O => \_carry_i_22_n_0\
);
\_carry_i_23\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(27),
I1 => \msb1__1\(25),
O => \_carry_i_23_n_0\
);
\_carry_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(37),
I1 => \msb1__1\(35),
O => \_carry_i_24_n_0\
);
\_carry_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"10EF"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_10_n_0,
I2 => \_carry_i_1_n_0\,
I3 => L1_carry_i_9_n_0,
O => \_carry_i_3_n_0\
);
\_carry_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => L1_carry_i_16_n_0,
O => \_carry_i_4_n_0\
);
\_carry_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \_carry_i_10_n_0\,
O => p_0_in(1)
);
\_carry_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \msb1__1\(46),
I1 => \msb1__1\(45),
I2 => \msb1__1\(44),
O => \_carry_i_6_n_0\
);
\_carry_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0FFF0FFFFFFF4"
)
port map (
I0 => \msb1__1\(35),
I1 => \msb1__1\(34),
I2 => \msb1__1\(38),
I3 => \_carry_i_11_n_0\,
I4 => \msb1__1\(36),
I5 => \msb1__1\(37),
O => \_carry_i_7_n_0\
);
\_carry_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF55551110"
)
port map (
I0 => \_carry_i_12_n_0\,
I1 => \_carry_i_13_n_0\,
I2 => \_carry_i_14_n_0\,
I3 => \_carry_i_15_n_0\,
I4 => \_carry_i_16_n_0\,
I5 => \_carry_i_17_n_0\,
O => \_carry_i_8_n_0\
);
\_carry_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF00F4"
)
port map (
I0 => \msb1__1\(40),
I1 => \msb1__1\(39),
I2 => \msb1__1\(41),
I3 => \msb1__1\(42),
I4 => \msb1__1\(45),
I5 => \msb1__1\(43),
O => \_carry_i_9_n_0\
);
msb1: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29 downto 23) => B"0000001",
A(22 downto 0) => y(22 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_msb1_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => '0',
B(16 downto 0) => x(16 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_msb1_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_msb1_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_msb1_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_msb1_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_msb1_OVERFLOW_UNCONNECTED,
P(47) => msb1_n_58,
P(46) => msb1_n_59,
P(45) => msb1_n_60,
P(44) => msb1_n_61,
P(43) => msb1_n_62,
P(42) => msb1_n_63,
P(41) => msb1_n_64,
P(40) => msb1_n_65,
P(39) => msb1_n_66,
P(38) => msb1_n_67,
P(37) => msb1_n_68,
P(36) => msb1_n_69,
P(35) => msb1_n_70,
P(34) => msb1_n_71,
P(33) => msb1_n_72,
P(32) => msb1_n_73,
P(31) => msb1_n_74,
P(30) => msb1_n_75,
P(29) => msb1_n_76,
P(28) => msb1_n_77,
P(27) => msb1_n_78,
P(26) => msb1_n_79,
P(25) => msb1_n_80,
P(24) => msb1_n_81,
P(23) => msb1_n_82,
P(22) => msb1_n_83,
P(21) => msb1_n_84,
P(20) => msb1_n_85,
P(19) => msb1_n_86,
P(18) => msb1_n_87,
P(17) => msb1_n_88,
P(16 downto 0) => \msb1__1\(16 downto 0),
PATTERNBDETECT => NLW_msb1_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_msb1_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47) => msb1_n_106,
PCOUT(46) => msb1_n_107,
PCOUT(45) => msb1_n_108,
PCOUT(44) => msb1_n_109,
PCOUT(43) => msb1_n_110,
PCOUT(42) => msb1_n_111,
PCOUT(41) => msb1_n_112,
PCOUT(40) => msb1_n_113,
PCOUT(39) => msb1_n_114,
PCOUT(38) => msb1_n_115,
PCOUT(37) => msb1_n_116,
PCOUT(36) => msb1_n_117,
PCOUT(35) => msb1_n_118,
PCOUT(34) => msb1_n_119,
PCOUT(33) => msb1_n_120,
PCOUT(32) => msb1_n_121,
PCOUT(31) => msb1_n_122,
PCOUT(30) => msb1_n_123,
PCOUT(29) => msb1_n_124,
PCOUT(28) => msb1_n_125,
PCOUT(27) => msb1_n_126,
PCOUT(26) => msb1_n_127,
PCOUT(25) => msb1_n_128,
PCOUT(24) => msb1_n_129,
PCOUT(23) => msb1_n_130,
PCOUT(22) => msb1_n_131,
PCOUT(21) => msb1_n_132,
PCOUT(20) => msb1_n_133,
PCOUT(19) => msb1_n_134,
PCOUT(18) => msb1_n_135,
PCOUT(17) => msb1_n_136,
PCOUT(16) => msb1_n_137,
PCOUT(15) => msb1_n_138,
PCOUT(14) => msb1_n_139,
PCOUT(13) => msb1_n_140,
PCOUT(12) => msb1_n_141,
PCOUT(11) => msb1_n_142,
PCOUT(10) => msb1_n_143,
PCOUT(9) => msb1_n_144,
PCOUT(8) => msb1_n_145,
PCOUT(7) => msb1_n_146,
PCOUT(6) => msb1_n_147,
PCOUT(5) => msb1_n_148,
PCOUT(4) => msb1_n_149,
PCOUT(3) => msb1_n_150,
PCOUT(2) => msb1_n_151,
PCOUT(1) => msb1_n_152,
PCOUT(0) => msb1_n_153,
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_msb1_UNDERFLOW_UNCONNECTED
);
\msb1__0\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29 downto 23) => B"0000001",
A(22 downto 0) => y(22 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_msb1__0_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17 downto 6) => B"000000000001",
B(5 downto 0) => x(22 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_msb1__0_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_msb1__0_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_msb1__0_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_msb1__0_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"1010101",
OVERFLOW => \NLW_msb1__0_OVERFLOW_UNCONNECTED\,
P(47 downto 31) => \NLW_msb1__0_P_UNCONNECTED\(47 downto 31),
P(30 downto 0) => \msb1__1\(47 downto 17),
PATTERNBDETECT => \NLW_msb1__0_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_msb1__0_PATTERNDETECT_UNCONNECTED\,
PCIN(47) => msb1_n_106,
PCIN(46) => msb1_n_107,
PCIN(45) => msb1_n_108,
PCIN(44) => msb1_n_109,
PCIN(43) => msb1_n_110,
PCIN(42) => msb1_n_111,
PCIN(41) => msb1_n_112,
PCIN(40) => msb1_n_113,
PCIN(39) => msb1_n_114,
PCIN(38) => msb1_n_115,
PCIN(37) => msb1_n_116,
PCIN(36) => msb1_n_117,
PCIN(35) => msb1_n_118,
PCIN(34) => msb1_n_119,
PCIN(33) => msb1_n_120,
PCIN(32) => msb1_n_121,
PCIN(31) => msb1_n_122,
PCIN(30) => msb1_n_123,
PCIN(29) => msb1_n_124,
PCIN(28) => msb1_n_125,
PCIN(27) => msb1_n_126,
PCIN(26) => msb1_n_127,
PCIN(25) => msb1_n_128,
PCIN(24) => msb1_n_129,
PCIN(23) => msb1_n_130,
PCIN(22) => msb1_n_131,
PCIN(21) => msb1_n_132,
PCIN(20) => msb1_n_133,
PCIN(19) => msb1_n_134,
PCIN(18) => msb1_n_135,
PCIN(17) => msb1_n_136,
PCIN(16) => msb1_n_137,
PCIN(15) => msb1_n_138,
PCIN(14) => msb1_n_139,
PCIN(13) => msb1_n_140,
PCIN(12) => msb1_n_141,
PCIN(11) => msb1_n_142,
PCIN(10) => msb1_n_143,
PCIN(9) => msb1_n_144,
PCIN(8) => msb1_n_145,
PCIN(7) => msb1_n_146,
PCIN(6) => msb1_n_147,
PCIN(5) => msb1_n_148,
PCIN(4) => msb1_n_149,
PCIN(3) => msb1_n_150,
PCIN(2) => msb1_n_151,
PCIN(1) => msb1_n_152,
PCIN(0) => msb1_n_153,
PCOUT(47 downto 0) => \NLW_msb1__0_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_msb1__0_UNDERFLOW_UNCONNECTED\
);
\z[11]_INST_0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \z[7]_INST_0_i_1_n_0\,
CO(3) => \z[11]_INST_0_i_1_n_0\,
CO(2) => \z[11]_INST_0_i_1_n_1\,
CO(1) => \z[11]_INST_0_i_1_n_2\,
CO(0) => \z[11]_INST_0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => z_mantissa(11 downto 8),
S(3) => sel0(11),
S(2) => \z[11]_INST_0_i_3_n_0\,
S(1 downto 0) => sel0(9 downto 8)
);
\z[11]_INST_0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_11_n_0\,
O => sel0(11)
);
\z[11]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_50_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_47_n_0\,
I4 => \z[30]_INST_0_i_51_n_0\,
O => \z[11]_INST_0_i_3_n_0\
);
\z[11]_INST_0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[11]_INST_0_i_6_n_0\,
O => sel0(9)
);
\z[11]_INST_0_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[11]_INST_0_i_7_n_0\,
O => sel0(8)
);
\z[11]_INST_0_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[11]_INST_0_i_8_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[30]_INST_0_i_50_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_52_n_0\,
O => \z[11]_INST_0_i_6_n_0\
);
\z[11]_INST_0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[11]_INST_0_i_9_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[11]_INST_0_i_8_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_54_n_0\,
O => \z[11]_INST_0_i_7_n_0\
);
\z[11]_INST_0_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_121_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_98_n_0\,
O => \z[11]_INST_0_i_8_n_0\
);
\z[11]_INST_0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_100_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_101_n_0\,
O => \z[11]_INST_0_i_9_n_0\
);
\z[15]_INST_0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \z[11]_INST_0_i_1_n_0\,
CO(3) => \z[15]_INST_0_i_1_n_0\,
CO(2) => \z[15]_INST_0_i_1_n_1\,
CO(1) => \z[15]_INST_0_i_1_n_2\,
CO(0) => \z[15]_INST_0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => z_mantissa(15 downto 12),
S(3 downto 0) => sel0(15 downto 12)
);
\z[15]_INST_0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_14_n_0\,
O => sel0(15)
);
\z[15]_INST_0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_15_n_0\,
O => sel0(14)
);
\z[15]_INST_0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[15]_INST_0_i_6_n_0\,
O => sel0(13)
);
\z[15]_INST_0_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[15]_INST_0_i_7_n_0\,
O => sel0(12)
);
\z[15]_INST_0_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[15]_INST_0_i_8_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[30]_INST_0_i_60_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_63_n_0\,
O => \z[15]_INST_0_i_6_n_0\
);
\z[15]_INST_0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[30]_INST_0_i_48_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[15]_INST_0_i_8_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_65_n_0\,
O => \z[15]_INST_0_i_7_n_0\
);
\z[15]_INST_0_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_142_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_120_n_0\,
O => \z[15]_INST_0_i_8_n_0\
);
\z[19]_INST_0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \z[15]_INST_0_i_1_n_0\,
CO(3) => \z[19]_INST_0_i_1_n_0\,
CO(2) => \z[19]_INST_0_i_1_n_1\,
CO(1) => \z[19]_INST_0_i_1_n_2\,
CO(0) => \z[19]_INST_0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => z_mantissa(19 downto 16),
S(3 downto 0) => sel0(19 downto 16)
);
\z[19]_INST_0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_17_n_0\,
O => sel0(19)
);
\z[19]_INST_0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_18_n_0\,
O => sel0(18)
);
\z[19]_INST_0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_19_n_0\,
O => sel0(17)
);
\z[19]_INST_0_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_20_n_0\,
O => sel0(16)
);
\z[22]_INST_0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \z[19]_INST_0_i_1_n_0\,
CO(3 downto 2) => \NLW_z[22]_INST_0_i_1_CO_UNCONNECTED\(3 downto 2),
CO(1) => \z[22]_INST_0_i_1_n_2\,
CO(0) => \z[22]_INST_0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_z[22]_INST_0_i_1_O_UNCONNECTED\(3),
O(2 downto 0) => z_mantissa(22 downto 20),
S(3) => '0',
S(2 downto 0) => sel0(22 downto 20)
);
\z[22]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F2F2FFF2"
)
port map (
I0 => \z[30]_INST_0_i_57_n_0\,
I1 => \z[30]_INST_0_i_81_n_0\,
I2 => \z[30]_INST_0_i_76_n_0\,
I3 => L1,
I4 => \z[22]_INST_0_i_5_n_0\,
O => sel0(22)
);
\z[22]_INST_0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_22_n_0\,
O => sel0(21)
);
\z[22]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"22F222F2FFFF22F2"
)
port map (
I0 => \z[30]_INST_0_i_43_n_0\,
I1 => \z[30]_INST_0_i_82_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_67_n_0\,
I4 => L1,
I5 => \z[22]_INST_0_i_6_n_0\,
O => sel0(20)
);
\z[22]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_168_n_0\,
I1 => \z[30]_INST_0_i_154_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_159_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_158_n_0\,
O => \z[22]_INST_0_i_5_n_0\
);
\z[22]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_154_n_0\,
I1 => \z[30]_INST_0_i_155_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_158_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_152_n_0\,
O => \z[22]_INST_0_i_6_n_0\
);
\z[23]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(0),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(0),
I5 => \y_11__s_net_1\,
O => z(0)
);
\z[24]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(1),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(1),
I5 => \y_11__s_net_1\,
O => z(1)
);
\z[25]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(2),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(2),
I5 => \y_11__s_net_1\,
O => z(2)
);
\z[26]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(3),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(3),
I5 => \y_11__s_net_1\,
O => z(3)
);
\z[27]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(4),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(4),
I5 => \y_11__s_net_1\,
O => z(4)
);
\z[28]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(5),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(5),
I5 => \y_11__s_net_1\,
O => z(5)
);
\z[29]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(6),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(6),
I5 => \y_11__s_net_1\,
O => z(6)
);
\z[30]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(7),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(7),
I5 => \y_11__s_net_1\,
O => z(7)
);
\z[30]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEFFFFFFFFFFF"
)
port map (
I0 => \z[30]_INST_0_i_5_n_0\,
I1 => \z[30]_INST_0_i_6_n_0\,
I2 => sel0(3),
I3 => sel0(0),
I4 => \z[30]_INST_0_i_9_n_0\,
I5 => sel0(2),
O => \z[30]_INST_0_i_1_n_0\
);
\z[30]_INST_0_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_44_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_37_n_0\,
I4 => \z[30]_INST_0_i_46_n_0\,
O => sel0(2)
);
\z[30]_INST_0_i_100\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_181_n_0\,
I1 => \z[30]_INST_0_i_182_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_183_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_184_n_0\,
O => \z[30]_INST_0_i_100_n_0\
);
\z[30]_INST_0_i_101\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_185_n_0\,
I1 => \z[30]_INST_0_i_186_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_187_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_188_n_0\,
O => \z[30]_INST_0_i_101_n_0\
);
\z[30]_INST_0_i_102\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_189_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_171_n_0\,
O => \z[30]_INST_0_i_102_n_0\
);
\z[30]_INST_0_i_103\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFF4FFF7"
)
port map (
I0 => \msb1__1\(1),
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_118_n_0\,
I3 => \z[30]_INST_0_i_170_n_0\,
I4 => \msb1__1\(3),
I5 => \z[30]_INST_0_i_169_n_0\,
O => \z[30]_INST_0_i_103_n_0\
);
\z[30]_INST_0_i_104\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_183_n_0\,
I1 => \z[30]_INST_0_i_184_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_190_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_181_n_0\,
O => \z[30]_INST_0_i_104_n_0\
);
\z[30]_INST_0_i_105\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_187_n_0\,
I1 => \z[30]_INST_0_i_188_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_191_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_185_n_0\,
O => \z[30]_INST_0_i_105_n_0\
);
\z[30]_INST_0_i_106\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_175_n_0\,
I1 => \z[30]_INST_0_i_176_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_192_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_173_n_0\,
O => \z[30]_INST_0_i_106_n_0\
);
\z[30]_INST_0_i_107\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFEAEFFFF"
)
port map (
I0 => \z[30]_INST_0_i_118_n_0\,
I1 => \_carry_n_4\,
I2 => L1,
I3 => L1_carry_i_14_n_0,
I4 => \msb1__1\(3),
I5 => \z[30]_INST_0_i_169_n_0\,
O => \z[30]_INST_0_i_107_n_0\
);
\z[30]_INST_0_i_108\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_179_n_0\,
I1 => \z[30]_INST_0_i_180_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_193_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_177_n_0\,
O => \z[30]_INST_0_i_108_n_0\
);
\z[30]_INST_0_i_109\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFF4F7FFFF"
)
port map (
I0 => \msb1__1\(0),
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_118_n_0\,
I3 => \msb1__1\(2),
I4 => \z[30]_INST_0_i_194_n_0\,
I5 => \z[30]_INST_0_i_169_n_0\,
O => \z[30]_INST_0_i_109_n_0\
);
\z[30]_INST_0_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[30]_INST_0_i_47_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[30]_INST_0_i_48_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_49_n_0\,
O => \z[30]_INST_0_i_11_n_0\
);
\z[30]_INST_0_i_110\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_190_n_0\,
I1 => \z[30]_INST_0_i_181_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_195_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_183_n_0\,
O => \z[30]_INST_0_i_110_n_0\
);
\z[30]_INST_0_i_111\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_191_n_0\,
I1 => L1_carry_i_17_n_0,
I2 => \z[30]_INST_0_i_185_n_0\,
O => \z[30]_INST_0_i_111_n_0\
);
\z[30]_INST_0_i_112\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_196_n_0\,
I1 => L1_carry_i_17_n_0,
I2 => \z[30]_INST_0_i_187_n_0\,
O => \z[30]_INST_0_i_112_n_0\
);
\z[30]_INST_0_i_113\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_192_n_0\,
I1 => L1_carry_i_17_n_0,
I2 => \z[30]_INST_0_i_173_n_0\,
O => \z[30]_INST_0_i_113_n_0\
);
\z[30]_INST_0_i_114\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_197_n_0\,
I1 => L1_carry_i_17_n_0,
I2 => \z[30]_INST_0_i_175_n_0\,
O => \z[30]_INST_0_i_114_n_0\
);
\z[30]_INST_0_i_115\: unisim.vcomponents.LUT6
generic map(
INIT => X"3FFF3FAAFFFFFFFF"
)
port map (
I0 => \_carry_n_5\,
I1 => L1_carry_i_17_n_0,
I2 => \z[30]_INST_0_i_198_n_0\,
I3 => L1,
I4 => \_carry_n_4\,
I5 => \msb1__1\(0),
O => \z[30]_INST_0_i_115_n_0\
);
\z[30]_INST_0_i_116\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \z[30]_INST_0_i_199_n_0\,
I1 => \_carry__0_n_6\,
I2 => \_carry__5_n_6\,
I3 => \_carry__0_n_5\,
I4 => \z[30]_INST_0_i_200_n_0\,
I5 => \z[30]_INST_0_i_201_n_0\,
O => \z[30]_INST_0_i_116_n_0\
);
\z[30]_INST_0_i_117\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF3FFFFFFF3FAFAF"
)
port map (
I0 => \_carry_n_5\,
I1 => L1_carry_i_17_n_0,
I2 => \msb1__1\(1),
I3 => L1_carry_i_14_n_0,
I4 => L1,
I5 => \_carry_n_4\,
O => \z[30]_INST_0_i_117_n_0\
);
\z[30]_INST_0_i_118\: unisim.vcomponents.LUT5
generic map(
INIT => X"3C33AAAA"
)
port map (
I0 => \_carry_n_6\,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_10_n_0,
I3 => \_carry_i_1_n_0\,
I4 => L1,
O => \z[30]_INST_0_i_118_n_0\
);
\z[30]_INST_0_i_119\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFEAEFFFF"
)
port map (
I0 => \z[30]_INST_0_i_118_n_0\,
I1 => \_carry_n_4\,
I2 => L1,
I3 => L1_carry_i_14_n_0,
I4 => \msb1__1\(1),
I5 => \z[30]_INST_0_i_169_n_0\,
O => \z[30]_INST_0_i_119_n_0\
);
\z[30]_INST_0_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_50_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_47_n_0\,
I4 => \z[30]_INST_0_i_51_n_0\,
O => sel0(10)
);
\z[30]_INST_0_i_120\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_176_n_0\,
I1 => \z[30]_INST_0_i_202_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_173_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_174_n_0\,
O => \z[30]_INST_0_i_120_n_0\
);
\z[30]_INST_0_i_121\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_180_n_0\,
I1 => \z[30]_INST_0_i_203_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_177_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_178_n_0\,
O => \z[30]_INST_0_i_121_n_0\
);
\z[30]_INST_0_i_122\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_184_n_0\,
I1 => \z[30]_INST_0_i_204_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_181_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_182_n_0\,
O => \z[30]_INST_0_i_122_n_0\
);
\z[30]_INST_0_i_123\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_188_n_0\,
I1 => \z[30]_INST_0_i_205_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_185_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_186_n_0\,
O => \z[30]_INST_0_i_123_n_0\
);
\z[30]_INST_0_i_124\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \z[30]_INST_0_i_206_n_0\,
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \z[30]_INST_0_i_207_n_0\,
I3 => \z[30]_INST_0_i_95_n_0\,
I4 => \z[30]_INST_0_i_208_n_0\,
O => \z[30]_INST_0_i_124_n_0\
);
\z[30]_INST_0_i_125\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \z[30]_INST_0_i_209_n_0\,
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \z[30]_INST_0_i_132_n_0\,
I3 => \z[30]_INST_0_i_95_n_0\,
I4 => \z[30]_INST_0_i_210_n_0\,
O => \z[30]_INST_0_i_125_n_0\
);
\z[30]_INST_0_i_126\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[30]_INST_0_i_96_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_206_n_0\,
I3 => \z[30]_INST_0_i_118_n_0\,
I4 => \z[30]_INST_0_i_207_n_0\,
O => \z[30]_INST_0_i_126_n_0\
);
\z[30]_INST_0_i_127\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[30]_INST_0_i_172_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_209_n_0\,
I3 => \z[30]_INST_0_i_118_n_0\,
I4 => \z[30]_INST_0_i_132_n_0\,
O => \z[30]_INST_0_i_127_n_0\
);
\z[30]_INST_0_i_128\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA03030AFA03F3F"
)
port map (
I0 => \z[30]_INST_0_i_211_n_0\,
I1 => \z[30]_INST_0_i_212_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_213_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_202_n_0\,
O => \z[30]_INST_0_i_128_n_0\
);
\z[30]_INST_0_i_129\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => \z[30]_INST_0_i_178_n_0\,
I1 => \z[30]_INST_0_i_214_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_180_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_203_n_0\,
O => \z[30]_INST_0_i_129_n_0\
);
\z[30]_INST_0_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"115F1F5F"
)
port map (
I0 => \z[30]_INST_0_i_52_n_0\,
I1 => \z[30]_INST_0_i_53_n_0\,
I2 => \z[30]_INST_0_i_54_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_55_n_0\,
O => \z[30]_INST_0_i_13_n_0\
);
\z[30]_INST_0_i_130\: unisim.vcomponents.LUT6
generic map(
INIT => X"505FC0C0505FCFCF"
)
port map (
I0 => \z[30]_INST_0_i_182_n_0\,
I1 => \z[30]_INST_0_i_215_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_184_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_204_n_0\,
O => \z[30]_INST_0_i_130_n_0\
);
\z[30]_INST_0_i_131\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0AF3030A0AF3F3F"
)
port map (
I0 => \z[30]_INST_0_i_216_n_0\,
I1 => \z[30]_INST_0_i_217_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_188_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_205_n_0\,
O => \z[30]_INST_0_i_131_n_0\
);
\z[30]_INST_0_i_132\: unisim.vcomponents.LUT6
generic map(
INIT => X"1510D5DFFFFFFFFF"
)
port map (
I0 => \msb1__1\(0),
I1 => L1_carry_i_17_n_0,
I2 => L1,
I3 => \_carry_n_5\,
I4 => \msb1__1\(8),
I5 => \z[30]_INST_0_i_194_n_0\,
O => \z[30]_INST_0_i_132_n_0\
);
\z[30]_INST_0_i_133\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF444F4FFF777F7"
)
port map (
I0 => \msb1__1\(4),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \_carry_n_4\,
I3 => L1,
I4 => L1_carry_i_14_n_0,
I5 => \msb1__1\(12),
O => \z[30]_INST_0_i_133_n_0\
);
\z[30]_INST_0_i_134\: unisim.vcomponents.LUT6
generic map(
INIT => X"1510D5DFFFFFFFFF"
)
port map (
I0 => \msb1__1\(2),
I1 => L1_carry_i_17_n_0,
I2 => L1,
I3 => \_carry_n_5\,
I4 => \msb1__1\(10),
I5 => \z[30]_INST_0_i_194_n_0\,
O => \z[30]_INST_0_i_134_n_0\
);
\z[30]_INST_0_i_135\: unisim.vcomponents.LUT6
generic map(
INIT => X"1510D5DFFFFFFFFF"
)
port map (
I0 => \msb1__1\(6),
I1 => L1_carry_i_17_n_0,
I2 => L1,
I3 => \_carry_n_5\,
I4 => \msb1__1\(14),
I5 => \z[30]_INST_0_i_194_n_0\,
O => \z[30]_INST_0_i_135_n_0\
);
\z[30]_INST_0_i_136\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFBBA088"
)
port map (
I0 => \z[30]_INST_0_i_207_n_0\,
I1 => \_carry_n_6\,
I2 => L1_carry_i_16_n_0,
I3 => L1,
I4 => \z[30]_INST_0_i_146_n_0\,
O => \z[30]_INST_0_i_136_n_0\
);
\z[30]_INST_0_i_137\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFBBA088"
)
port map (
I0 => \z[30]_INST_0_i_218_n_0\,
I1 => \_carry_n_6\,
I2 => L1_carry_i_16_n_0,
I3 => L1,
I4 => \z[30]_INST_0_i_148_n_0\,
O => \z[30]_INST_0_i_137_n_0\
);
\z[30]_INST_0_i_138\: unisim.vcomponents.LUT6
generic map(
INIT => X"B080FFFFB0800000"
)
port map (
I0 => \msb1__1\(36),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(20),
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_217_n_0\,
O => \z[30]_INST_0_i_138_n_0\
);
\z[30]_INST_0_i_139\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8BB8888B8B88888"
)
port map (
I0 => \z[30]_INST_0_i_188_n_0\,
I1 => L1_carry_i_17_n_0,
I2 => \msb1__1\(40),
I3 => L1_carry_i_14_n_0,
I4 => L1_carry_i_15_n_0,
I5 => \msb1__1\(24),
O => \z[30]_INST_0_i_139_n_0\
);
\z[30]_INST_0_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0DDD0D0000DD0D"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_56_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_58_n_0\,
I4 => \z[30]_INST_0_i_43_n_0\,
I5 => \z[30]_INST_0_i_59_n_0\,
O => \z[30]_INST_0_i_14_n_0\
);
\z[30]_INST_0_i_140\: unisim.vcomponents.LUT6
generic map(
INIT => X"B080FFFFB0800000"
)
port map (
I0 => \msb1__1\(37),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(21),
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_212_n_0\,
O => \z[30]_INST_0_i_140_n_0\
);
\z[30]_INST_0_i_141\: unisim.vcomponents.LUT6
generic map(
INIT => X"B080FFFFB0800000"
)
port map (
I0 => \msb1__1\(33),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(17),
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_202_n_0\,
O => \z[30]_INST_0_i_141_n_0\
);
\z[30]_INST_0_i_142\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_178_n_0\,
I1 => \z[30]_INST_0_i_214_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_180_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_203_n_0\,
O => \z[30]_INST_0_i_142_n_0\
);
\z[30]_INST_0_i_143\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[30]_INST_0_i_208_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_207_n_0\,
I3 => \z[30]_INST_0_i_118_n_0\,
I4 => \z[30]_INST_0_i_146_n_0\,
O => \z[30]_INST_0_i_143_n_0\
);
\z[30]_INST_0_i_144\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[30]_INST_0_i_210_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_132_n_0\,
I3 => \z[30]_INST_0_i_118_n_0\,
I4 => \z[30]_INST_0_i_133_n_0\,
O => \z[30]_INST_0_i_144_n_0\
);
\z[30]_INST_0_i_145\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_186_n_0\,
I1 => \z[30]_INST_0_i_217_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_188_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_205_n_0\,
O => \z[30]_INST_0_i_145_n_0\
);
\z[30]_INST_0_i_146\: unisim.vcomponents.LUT6
generic map(
INIT => X"4747FF47FFFFFF47"
)
port map (
I0 => \msb1__1\(5),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \msb1__1\(13),
I3 => \_carry_n_4\,
I4 => L1,
I5 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_146_n_0\
);
\z[30]_INST_0_i_147\: unisim.vcomponents.LUT6
generic map(
INIT => X"77CF44CC77CF77CF"
)
port map (
I0 => \msb1__1\(9),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \msb1__1\(1),
I3 => \z[30]_INST_0_i_194_n_0\,
I4 => \z[30]_INST_0_i_170_n_0\,
I5 => \msb1__1\(17),
O => \z[30]_INST_0_i_147_n_0\
);
\z[30]_INST_0_i_148\: unisim.vcomponents.LUT6
generic map(
INIT => X"7757555777F7FFF7"
)
port map (
I0 => \z[30]_INST_0_i_194_n_0\,
I1 => \msb1__1\(15),
I2 => \_carry_n_5\,
I3 => L1,
I4 => L1_carry_i_17_n_0,
I5 => \msb1__1\(7),
O => \z[30]_INST_0_i_148_n_0\
);
\z[30]_INST_0_i_149\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00FFFF47474747"
)
port map (
I0 => \msb1__1\(19),
I1 => \z[30]_INST_0_i_194_n_0\,
I2 => \msb1__1\(3),
I3 => \z[30]_INST_0_i_170_n_0\,
I4 => \msb1__1\(11),
I5 => \z[30]_INST_0_i_169_n_0\,
O => \z[30]_INST_0_i_149_n_0\
);
\z[30]_INST_0_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[30]_INST_0_i_60_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[30]_INST_0_i_61_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_62_n_0\,
O => \z[30]_INST_0_i_15_n_0\
);
\z[30]_INST_0_i_150\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFBBA088"
)
port map (
I0 => \z[30]_INST_0_i_133_n_0\,
I1 => \_carry_n_6\,
I2 => L1_carry_i_16_n_0,
I3 => L1,
I4 => \z[30]_INST_0_i_166_n_0\,
O => \z[30]_INST_0_i_150_n_0\
);
\z[30]_INST_0_i_151\: unisim.vcomponents.LUT5
generic map(
INIT => X"F5DD0511"
)
port map (
I0 => \z[30]_INST_0_i_163_n_0\,
I1 => \_carry_n_6\,
I2 => L1_carry_i_16_n_0,
I3 => L1,
I4 => \z[30]_INST_0_i_135_n_0\,
O => \z[30]_INST_0_i_151_n_0\
);
\z[30]_INST_0_i_152\: unisim.vcomponents.LUT5
generic map(
INIT => X"B888B8BB"
)
port map (
I0 => \z[30]_INST_0_i_219_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_211_n_0\,
I3 => L1_carry_i_17_n_0,
I4 => \z[30]_INST_0_i_212_n_0\,
O => \z[30]_INST_0_i_152_n_0\
);
\z[30]_INST_0_i_153\: unisim.vcomponents.LUT6
generic map(
INIT => X"505FC0C0505FCFCF"
)
port map (
I0 => \z[30]_INST_0_i_203_n_0\,
I1 => \z[30]_INST_0_i_220_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_178_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_214_n_0\,
O => \z[30]_INST_0_i_153_n_0\
);
\z[30]_INST_0_i_154\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \z[30]_INST_0_i_221_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_182_n_0\,
I3 => L1_carry_i_17_n_0,
I4 => \z[30]_INST_0_i_215_n_0\,
O => \z[30]_INST_0_i_154_n_0\
);
\z[30]_INST_0_i_155\: unisim.vcomponents.LUT5
generic map(
INIT => X"B888B8BB"
)
port map (
I0 => \z[30]_INST_0_i_222_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_216_n_0\,
I3 => L1_carry_i_17_n_0,
I4 => \z[30]_INST_0_i_217_n_0\,
O => \z[30]_INST_0_i_155_n_0\
);
\z[30]_INST_0_i_156\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFBBA088"
)
port map (
I0 => \z[30]_INST_0_i_146_n_0\,
I1 => \_carry_n_6\,
I2 => L1_carry_i_16_n_0,
I3 => L1,
I4 => \z[30]_INST_0_i_147_n_0\,
O => \z[30]_INST_0_i_156_n_0\
);
\z[30]_INST_0_i_157\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFBBA088"
)
port map (
I0 => \z[30]_INST_0_i_134_n_0\,
I1 => \_carry_n_6\,
I2 => L1_carry_i_16_n_0,
I3 => L1,
I4 => \z[30]_INST_0_i_135_n_0\,
O => \z[30]_INST_0_i_157_n_0\
);
\z[30]_INST_0_i_158\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \z[30]_INST_0_i_223_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_203_n_0\,
I3 => L1_carry_i_17_n_0,
I4 => \z[30]_INST_0_i_220_n_0\,
O => \z[30]_INST_0_i_158_n_0\
);
\z[30]_INST_0_i_159\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_224_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_219_n_0\,
O => \z[30]_INST_0_i_159_n_0\
);
\z[30]_INST_0_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"115F1F5F"
)
port map (
I0 => \z[30]_INST_0_i_63_n_0\,
I1 => \z[30]_INST_0_i_64_n_0\,
I2 => \z[30]_INST_0_i_65_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_66_n_0\,
O => \z[30]_INST_0_i_16_n_0\
);
\z[30]_INST_0_i_160\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_225_n_0\,
I1 => \z[30]_INST_0_i_222_n_0\,
I2 => \_carry_i_10_n_0\,
I3 => \z[30]_INST_0_i_221_n_0\,
I4 => L1_carry_i_16_n_0,
I5 => \z[30]_INST_0_i_226_n_0\,
O => \z[30]_INST_0_i_160_n_0\
);
\z[30]_INST_0_i_161\: unisim.vcomponents.LUT5
generic map(
INIT => X"B888B8BB"
)
port map (
I0 => \z[30]_INST_0_i_166_n_0\,
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \z[30]_INST_0_i_227_n_0\,
I3 => \z[30]_INST_0_i_169_n_0\,
I4 => \z[30]_INST_0_i_228_n_0\,
O => \z[30]_INST_0_i_161_n_0\
);
\z[30]_INST_0_i_162\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \msb1__1\(14),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \msb1__1\(6),
I3 => \z[30]_INST_0_i_170_n_0\,
I4 => \msb1__1\(22),
O => \z[30]_INST_0_i_162_n_0\
);
\z[30]_INST_0_i_163\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \msb1__1\(10),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \msb1__1\(2),
I3 => \z[30]_INST_0_i_170_n_0\,
I4 => \msb1__1\(18),
O => \z[30]_INST_0_i_163_n_0\
);
\z[30]_INST_0_i_164\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_223_n_0\,
I1 => \z[30]_INST_0_i_229_n_0\,
I2 => \_carry_i_10_n_0\,
I3 => \z[30]_INST_0_i_219_n_0\,
I4 => L1_carry_i_16_n_0,
I5 => \z[30]_INST_0_i_230_n_0\,
O => \z[30]_INST_0_i_164_n_0\
);
\z[30]_INST_0_i_165\: unisim.vcomponents.LUT5
generic map(
INIT => X"47CC47FF"
)
port map (
I0 => \msb1__1\(13),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \msb1__1\(21),
I3 => \z[30]_INST_0_i_194_n_0\,
I4 => \msb1__1\(5),
O => \z[30]_INST_0_i_165_n_0\
);
\z[30]_INST_0_i_166\: unisim.vcomponents.LUT6
generic map(
INIT => X"4447CCCF4447FFFF"
)
port map (
I0 => \msb1__1\(8),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \z[30]_INST_0_i_170_n_0\,
I3 => \msb1__1\(16),
I4 => \z[30]_INST_0_i_194_n_0\,
I5 => \msb1__1\(0),
O => \z[30]_INST_0_i_166_n_0\
);
\z[30]_INST_0_i_167\: unisim.vcomponents.LUT6
generic map(
INIT => X"B0BFB0B0B0BFBFBF"
)
port map (
I0 => \z[30]_INST_0_i_170_n_0\,
I1 => \msb1__1\(12),
I2 => \z[30]_INST_0_i_169_n_0\,
I3 => \msb1__1\(20),
I4 => \z[30]_INST_0_i_194_n_0\,
I5 => \msb1__1\(4),
O => \z[30]_INST_0_i_167_n_0\
);
\z[30]_INST_0_i_168\: unisim.vcomponents.LUT6
generic map(
INIT => X"7477FFFF74770000"
)
port map (
I0 => \z[30]_INST_0_i_217_n_0\,
I1 => L1_carry_i_17_n_0,
I2 => L1_carry_i_14_n_0,
I3 => \z[30]_INST_0_i_231_n_0\,
I4 => L1_carry_i_16_n_0,
I5 => \z[30]_INST_0_i_222_n_0\,
O => \z[30]_INST_0_i_168_n_0\
);
\z[30]_INST_0_i_169\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA6FFFFAAA60000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1,
I5 => \_carry_n_5\,
O => \z[30]_INST_0_i_169_n_0\
);
\z[30]_INST_0_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0DDD0D0000DD0D"
)
port map (
I0 => \z[30]_INST_0_i_43_n_0\,
I1 => \z[30]_INST_0_i_67_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_68_n_0\,
I4 => L1,
I5 => \z[30]_INST_0_i_69_n_0\,
O => \z[30]_INST_0_i_17_n_0\
);
\z[30]_INST_0_i_170\: unisim.vcomponents.LUT6
generic map(
INIT => X"9A55FFFF9A550000"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => \z[30]_INST_0_i_232_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => L1_carry_i_9_n_0,
I4 => L1,
I5 => \_carry_n_4\,
O => \z[30]_INST_0_i_170_n_0\
);
\z[30]_INST_0_i_171\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF7FFF7FFF70FF7F"
)
port map (
I0 => \z[30]_INST_0_i_194_n_0\,
I1 => \msb1__1\(0),
I2 => \z[30]_INST_0_i_118_n_0\,
I3 => \z[30]_INST_0_i_169_n_0\,
I4 => \msb1__1\(4),
I5 => \z[30]_INST_0_i_170_n_0\,
O => \z[30]_INST_0_i_171_n_0\
);
\z[30]_INST_0_i_172\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4FFF7FF"
)
port map (
I0 => \msb1__1\(2),
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \z[30]_INST_0_i_169_n_0\,
I3 => \z[30]_INST_0_i_194_n_0\,
I4 => \msb1__1\(6),
O => \z[30]_INST_0_i_172_n_0\
);
\z[30]_INST_0_i_173\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(29),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(13),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(45),
O => \z[30]_INST_0_i_173_n_0\
);
\z[30]_INST_0_i_174\: unisim.vcomponents.LUT4
generic map(
INIT => X"B080"
)
port map (
I0 => \msb1__1\(37),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(21),
O => \z[30]_INST_0_i_174_n_0\
);
\z[30]_INST_0_i_175\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(25),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(9),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(41),
O => \z[30]_INST_0_i_175_n_0\
);
\z[30]_INST_0_i_176\: unisim.vcomponents.LUT4
generic map(
INIT => X"B080"
)
port map (
I0 => \msb1__1\(33),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(17),
O => \z[30]_INST_0_i_176_n_0\
);
\z[30]_INST_0_i_177\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(27),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(11),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(43),
O => \z[30]_INST_0_i_177_n_0\
);
\z[30]_INST_0_i_178\: unisim.vcomponents.LUT4
generic map(
INIT => X"88C0"
)
port map (
I0 => \msb1__1\(19),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(35),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_178_n_0\
);
\z[30]_INST_0_i_179\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(23),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(7),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(39),
O => \z[30]_INST_0_i_179_n_0\
);
\z[30]_INST_0_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0DDD0D0000DD0D"
)
port map (
I0 => \z[30]_INST_0_i_43_n_0\,
I1 => \z[30]_INST_0_i_68_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_70_n_0\,
I4 => L1,
I5 => \z[30]_INST_0_i_71_n_0\,
O => \z[30]_INST_0_i_18_n_0\
);
\z[30]_INST_0_i_180\: unisim.vcomponents.LUT5
generic map(
INIT => X"ACACF000"
)
port map (
I0 => \msb1__1\(15),
I1 => \msb1__1\(47),
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(31),
I4 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_180_n_0\
);
\z[30]_INST_0_i_181\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(30),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(14),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(46),
O => \z[30]_INST_0_i_181_n_0\
);
\z[30]_INST_0_i_182\: unisim.vcomponents.LUT4
generic map(
INIT => X"88C0"
)
port map (
I0 => \msb1__1\(22),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(38),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_182_n_0\
);
\z[30]_INST_0_i_183\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(26),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(10),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(42),
O => \z[30]_INST_0_i_183_n_0\
);
\z[30]_INST_0_i_184\: unisim.vcomponents.LUT4
generic map(
INIT => X"88C0"
)
port map (
I0 => \msb1__1\(18),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(34),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_184_n_0\
);
\z[30]_INST_0_i_185\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(28),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(12),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(44),
O => \z[30]_INST_0_i_185_n_0\
);
\z[30]_INST_0_i_186\: unisim.vcomponents.LUT4
generic map(
INIT => X"B080"
)
port map (
I0 => \msb1__1\(36),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(20),
O => \z[30]_INST_0_i_186_n_0\
);
\z[30]_INST_0_i_187\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(24),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(8),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(40),
O => \z[30]_INST_0_i_187_n_0\
);
\z[30]_INST_0_i_188\: unisim.vcomponents.LUT4
generic map(
INIT => X"88C0"
)
port map (
I0 => \msb1__1\(16),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(32),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_188_n_0\
);
\z[30]_INST_0_i_189\: unisim.vcomponents.LUT6
generic map(
INIT => X"BFFFFFFFBFFFBFBF"
)
port map (
I0 => \z[30]_INST_0_i_118_n_0\,
I1 => \msb1__1\(2),
I2 => \z[30]_INST_0_i_194_n_0\,
I3 => L1_carry_i_17_n_0,
I4 => L1,
I5 => \_carry_n_5\,
O => \z[30]_INST_0_i_189_n_0\
);
\z[30]_INST_0_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0DDD0D0000DD0D"
)
port map (
I0 => \z[30]_INST_0_i_57_n_0\,
I1 => \z[30]_INST_0_i_72_n_0\,
I2 => \z[30]_INST_0_i_43_n_0\,
I3 => \z[30]_INST_0_i_70_n_0\,
I4 => L1,
I5 => \z[30]_INST_0_i_73_n_0\,
O => \z[30]_INST_0_i_19_n_0\
);
\z[30]_INST_0_i_190\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(22),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(6),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(38),
O => \z[30]_INST_0_i_190_n_0\
);
\z[30]_INST_0_i_191\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(20),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(4),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(36),
O => \z[30]_INST_0_i_191_n_0\
);
\z[30]_INST_0_i_192\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(21),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(5),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(37),
O => \z[30]_INST_0_i_192_n_0\
);
\z[30]_INST_0_i_193\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(19),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(3),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(35),
O => \z[30]_INST_0_i_193_n_0\
);
\z[30]_INST_0_i_194\: unisim.vcomponents.LUT6
generic map(
INIT => X"5DA200005DA2FFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => \z[30]_INST_0_i_232_n_0\,
I3 => L1_carry_i_12_n_0,
I4 => L1,
I5 => \_carry_n_4\,
O => \z[30]_INST_0_i_194_n_0\
);
\z[30]_INST_0_i_195\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(18),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(2),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(34),
O => \z[30]_INST_0_i_195_n_0\
);
\z[30]_INST_0_i_196\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(16),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(0),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(32),
O => \z[30]_INST_0_i_196_n_0\
);
\z[30]_INST_0_i_197\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(17),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(1),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(33),
O => \z[30]_INST_0_i_197_n_0\
);
\z[30]_INST_0_i_198\: unisim.vcomponents.LUT5
generic map(
INIT => X"555DAAA2"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
O => \z[30]_INST_0_i_198_n_0\
);
\z[30]_INST_0_i_199\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \_carry__2_n_4\,
I1 => \_carry__3_n_4\,
I2 => \_carry__4_n_4\,
I3 => \_carry__5_n_5\,
I4 => \z[30]_INST_0_i_233_n_0\,
O => \z[30]_INST_0_i_199_n_0\
);
\z[30]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFB"
)
port map (
I0 => \z[30]_INST_0_i_11_n_0\,
I1 => sel0(10),
I2 => \z[30]_INST_0_i_13_n_0\,
I3 => \z[30]_INST_0_i_14_n_0\,
I4 => \z[30]_INST_0_i_15_n_0\,
I5 => \z[30]_INST_0_i_16_n_0\,
O => \z[30]_INST_0_i_2_n_0\
);
\z[30]_INST_0_i_20\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0DDD0D0000DD0D"
)
port map (
I0 => \z[30]_INST_0_i_43_n_0\,
I1 => \z[30]_INST_0_i_72_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_59_n_0\,
I4 => L1,
I5 => \z[30]_INST_0_i_74_n_0\,
O => \z[30]_INST_0_i_20_n_0\
);
\z[30]_INST_0_i_200\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \_carry__1_n_4\,
I1 => \_carry__6_n_6\,
I2 => \_carry__0_n_7\,
I3 => \_carry__4_n_5\,
I4 => \z[30]_INST_0_i_234_n_0\,
O => \z[30]_INST_0_i_200_n_0\
);
\z[30]_INST_0_i_201\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \_carry__2_n_5\,
I1 => \_carry__6_n_7\,
I2 => \_carry__0_n_4\,
I3 => \_carry__5_n_7\,
I4 => \z[30]_INST_0_i_235_n_0\,
O => \z[30]_INST_0_i_201_n_0\
);
\z[30]_INST_0_i_202\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(41),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(25),
O => \z[30]_INST_0_i_202_n_0\
);
\z[30]_INST_0_i_203\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(39),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(23),
O => \z[30]_INST_0_i_203_n_0\
);
\z[30]_INST_0_i_204\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(42),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(26),
O => \z[30]_INST_0_i_204_n_0\
);
\z[30]_INST_0_i_205\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(40),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(24),
O => \z[30]_INST_0_i_205_n_0\
);
\z[30]_INST_0_i_206\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF3FFFFFFF3FAFAF"
)
port map (
I0 => \_carry_n_5\,
I1 => L1_carry_i_17_n_0,
I2 => \msb1__1\(5),
I3 => L1_carry_i_14_n_0,
I4 => L1,
I5 => \_carry_n_4\,
O => \z[30]_INST_0_i_206_n_0\
);
\z[30]_INST_0_i_207\: unisim.vcomponents.LUT6
generic map(
INIT => X"4747FF47FFFFFF47"
)
port map (
I0 => \msb1__1\(1),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \msb1__1\(9),
I3 => \_carry_n_4\,
I4 => L1,
I5 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_207_n_0\
);
\z[30]_INST_0_i_208\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFCF44FFFFCF77"
)
port map (
I0 => \msb1__1\(7),
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \msb1__1\(3),
I3 => \z[30]_INST_0_i_169_n_0\,
I4 => \z[30]_INST_0_i_170_n_0\,
I5 => \msb1__1\(11),
O => \z[30]_INST_0_i_208_n_0\
);
\z[30]_INST_0_i_209\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF3FFFFFFF3FAFAF"
)
port map (
I0 => \_carry_n_5\,
I1 => L1_carry_i_17_n_0,
I2 => \msb1__1\(4),
I3 => L1_carry_i_14_n_0,
I4 => L1,
I5 => \_carry_n_4\,
O => \z[30]_INST_0_i_209_n_0\
);
\z[30]_INST_0_i_21\: unisim.vcomponents.LUT6
generic map(
INIT => X"101010FF10101010"
)
port map (
I0 => \z[30]_INST_0_i_75_n_0\,
I1 => \z[30]_INST_0_i_76_n_0\,
I2 => \z[30]_INST_0_i_77_n_0\,
I3 => \z[30]_INST_0_i_78_n_0\,
I4 => \z[30]_INST_0_i_79_n_0\,
I5 => \z[30]_INST_0_i_80_n_0\,
O => \z[30]_INST_0_i_21_n_0\
);
\z[30]_INST_0_i_210\: unisim.vcomponents.LUT6
generic map(
INIT => X"CF44CF77FFFFFFFF"
)
port map (
I0 => \msb1__1\(6),
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \msb1__1\(2),
I3 => \z[30]_INST_0_i_169_n_0\,
I4 => \msb1__1\(10),
I5 => \z[30]_INST_0_i_194_n_0\,
O => \z[30]_INST_0_i_210_n_0\
);
\z[30]_INST_0_i_211\: unisim.vcomponents.LUT4
generic map(
INIT => X"773F"
)
port map (
I0 => \msb1__1\(21),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(37),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_211_n_0\
);
\z[30]_INST_0_i_212\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(45),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(29),
O => \z[30]_INST_0_i_212_n_0\
);
\z[30]_INST_0_i_213\: unisim.vcomponents.LUT4
generic map(
INIT => X"773F"
)
port map (
I0 => \msb1__1\(17),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(33),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_213_n_0\
);
\z[30]_INST_0_i_214\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(43),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(27),
O => \z[30]_INST_0_i_214_n_0\
);
\z[30]_INST_0_i_215\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F5F"
)
port map (
I0 => \msb1__1\(46),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(30),
O => \z[30]_INST_0_i_215_n_0\
);
\z[30]_INST_0_i_216\: unisim.vcomponents.LUT4
generic map(
INIT => X"773F"
)
port map (
I0 => \msb1__1\(20),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(36),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_216_n_0\
);
\z[30]_INST_0_i_217\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(44),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(28),
O => \z[30]_INST_0_i_217_n_0\
);
\z[30]_INST_0_i_218\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF444F4FFF777F7"
)
port map (
I0 => \msb1__1\(3),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \_carry_n_4\,
I3 => L1,
I4 => L1_carry_i_14_n_0,
I5 => \msb1__1\(11),
O => \z[30]_INST_0_i_218_n_0\
);
\z[30]_INST_0_i_219\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F103F1FFFFFFFFF"
)
port map (
I0 => \msb1__1\(25),
I1 => \msb1__1\(41),
I2 => L1_carry_i_17_n_0,
I3 => L1_carry_i_14_n_0,
I4 => \msb1__1\(33),
I5 => L1_carry_i_15_n_0,
O => \z[30]_INST_0_i_219_n_0\
);
\z[30]_INST_0_i_22\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0DDD0D0000DD0D"
)
port map (
I0 => \z[30]_INST_0_i_43_n_0\,
I1 => \z[30]_INST_0_i_81_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_82_n_0\,
I4 => L1,
I5 => \z[30]_INST_0_i_83_n_0\,
O => \z[30]_INST_0_i_22_n_0\
);
\z[30]_INST_0_i_220\: unisim.vcomponents.LUT4
generic map(
INIT => X"3777"
)
port map (
I0 => \msb1__1\(47),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(31),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_220_n_0\
);
\z[30]_INST_0_i_221\: unisim.vcomponents.LUT6
generic map(
INIT => X"103F1F3FFFFFFFFF"
)
port map (
I0 => \msb1__1\(26),
I1 => \msb1__1\(42),
I2 => L1_carry_i_17_n_0,
I3 => \z[30]_INST_0_i_198_n_0\,
I4 => \msb1__1\(34),
I5 => L1_carry_i_15_n_0,
O => \z[30]_INST_0_i_221_n_0\
);
\z[30]_INST_0_i_222\: unisim.vcomponents.LUT6
generic map(
INIT => X"103F1F3FFFFFFFFF"
)
port map (
I0 => \msb1__1\(24),
I1 => \msb1__1\(40),
I2 => L1_carry_i_17_n_0,
I3 => \z[30]_INST_0_i_198_n_0\,
I4 => \msb1__1\(32),
I5 => L1_carry_i_15_n_0,
O => \z[30]_INST_0_i_222_n_0\
);
\z[30]_INST_0_i_223\: unisim.vcomponents.LUT6
generic map(
INIT => X"103F1F3FFFFFFFFF"
)
port map (
I0 => \msb1__1\(27),
I1 => \msb1__1\(43),
I2 => L1_carry_i_17_n_0,
I3 => \z[30]_INST_0_i_198_n_0\,
I4 => \msb1__1\(35),
I5 => L1_carry_i_15_n_0,
O => \z[30]_INST_0_i_223_n_0\
);
\z[30]_INST_0_i_224\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F103F1FFFFFFFFF"
)
port map (
I0 => \msb1__1\(29),
I1 => \msb1__1\(45),
I2 => L1_carry_i_17_n_0,
I3 => L1_carry_i_14_n_0,
I4 => \msb1__1\(37),
I5 => L1_carry_i_15_n_0,
O => \z[30]_INST_0_i_224_n_0\
);
\z[30]_INST_0_i_225\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F103F1FFFFFFFFF"
)
port map (
I0 => \msb1__1\(28),
I1 => \msb1__1\(44),
I2 => L1_carry_i_17_n_0,
I3 => L1_carry_i_14_n_0,
I4 => \msb1__1\(36),
I5 => L1_carry_i_15_n_0,
O => \z[30]_INST_0_i_225_n_0\
);
\z[30]_INST_0_i_226\: unisim.vcomponents.LUT6
generic map(
INIT => X"E0E0E0E0E0EFEFEF"
)
port map (
I0 => \z[30]_INST_0_i_236_n_0\,
I1 => \z[30]_INST_0_i_237_n_0\,
I2 => L1_carry_i_17_n_0,
I3 => \msb1__1\(46),
I4 => L1_carry_i_15_n_0,
I5 => \z[30]_INST_0_i_238_n_0\,
O => \z[30]_INST_0_i_226_n_0\
);
\z[30]_INST_0_i_227\: unisim.vcomponents.LUT4
generic map(
INIT => X"E2FF"
)
port map (
I0 => \_carry_n_4\,
I1 => L1,
I2 => L1_carry_i_14_n_0,
I3 => \msb1__1\(12),
O => \z[30]_INST_0_i_227_n_0\
);
\z[30]_INST_0_i_228\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFBA808A"
)
port map (
I0 => \msb1__1\(20),
I1 => \z[30]_INST_0_i_198_n_0\,
I2 => L1,
I3 => \_carry_n_4\,
I4 => \msb1__1\(4),
O => \z[30]_INST_0_i_228_n_0\
);
\z[30]_INST_0_i_229\: unisim.vcomponents.LUT6
generic map(
INIT => X"10105050101F5F5F"
)
port map (
I0 => \z[30]_INST_0_i_239_n_0\,
I1 => \msb1__1\(39),
I2 => L1_carry_i_17_n_0,
I3 => \msb1__1\(47),
I4 => L1_carry_i_15_n_0,
I5 => \z[30]_INST_0_i_240_n_0\,
O => \z[30]_INST_0_i_229_n_0\
);
\z[30]_INST_0_i_230\: unisim.vcomponents.LUT6
generic map(
INIT => X"50503030505F3F3F"
)
port map (
I0 => \z[30]_INST_0_i_241_n_0\,
I1 => \z[30]_INST_0_i_242_n_0\,
I2 => L1_carry_i_17_n_0,
I3 => \z[30]_INST_0_i_243_n_0\,
I4 => \z[30]_INST_0_i_198_n_0\,
I5 => \z[30]_INST_0_i_244_n_0\,
O => \z[30]_INST_0_i_230_n_0\
);
\z[30]_INST_0_i_231\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => L1_carry_i_15_n_0,
I1 => \msb1__1\(36),
O => \z[30]_INST_0_i_231_n_0\
);
\z[30]_INST_0_i_232\: unisim.vcomponents.LUT6
generic map(
INIT => X"AEAEAEAEFFFFFFAE"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_29_n_0,
I2 => L1_carry_i_28_n_0,
I3 => \z[30]_INST_0_i_245_n_0\,
I4 => L1_carry_i_25_n_0,
I5 => L1_carry_i_24_n_0,
O => \z[30]_INST_0_i_232_n_0\
);
\z[30]_INST_0_i_233\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \_carry__2_n_6\,
I1 => \_carry__1_n_6\,
I2 => \_carry__3_n_6\,
I3 => \_carry__1_n_7\,
O => \z[30]_INST_0_i_233_n_0\
);
\z[30]_INST_0_i_234\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \_carry__2_n_7\,
I1 => L1,
I2 => \_carry__3_n_5\,
I3 => \_carry__1_n_5\,
O => \z[30]_INST_0_i_234_n_0\
);
\z[30]_INST_0_i_235\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \_carry__5_n_4\,
I1 => \_carry__3_n_7\,
I2 => \_carry__4_n_6\,
I3 => \_carry__4_n_7\,
O => \z[30]_INST_0_i_235_n_0\
);
\z[30]_INST_0_i_236\: unisim.vcomponents.LUT6
generic map(
INIT => X"C3CC333341441111"
)
port map (
I0 => \msb1__1\(38),
I1 => L1_carry_i_12_n_0,
I2 => \z[30]_INST_0_i_232_n_0\,
I3 => \_carry_i_1_n_0\,
I4 => L1_carry_i_9_n_0,
I5 => L1_carry_i_13_n_0,
O => \z[30]_INST_0_i_236_n_0\
);
\z[30]_INST_0_i_237\: unisim.vcomponents.LUT6
generic map(
INIT => X"343344441C11CCCC"
)
port map (
I0 => \msb1__1\(22),
I1 => L1_carry_i_12_n_0,
I2 => \z[30]_INST_0_i_232_n_0\,
I3 => \_carry_i_1_n_0\,
I4 => L1_carry_i_9_n_0,
I5 => L1_carry_i_13_n_0,
O => \z[30]_INST_0_i_237_n_0\
);
\z[30]_INST_0_i_238\: unisim.vcomponents.LUT6
generic map(
INIT => X"0808880820200020"
)
port map (
I0 => \msb1__1\(30),
I1 => L1_carry_i_13_n_0,
I2 => L1_carry_i_9_n_0,
I3 => \_carry_i_1_n_0\,
I4 => \z[30]_INST_0_i_232_n_0\,
I5 => L1_carry_i_12_n_0,
O => \z[30]_INST_0_i_238_n_0\
);
\z[30]_INST_0_i_239\: unisim.vcomponents.LUT6
generic map(
INIT => X"0808880820200020"
)
port map (
I0 => \msb1__1\(23),
I1 => L1_carry_i_13_n_0,
I2 => L1_carry_i_9_n_0,
I3 => \_carry_i_1_n_0\,
I4 => \z[30]_INST_0_i_232_n_0\,
I5 => L1_carry_i_12_n_0,
O => \z[30]_INST_0_i_239_n_0\
);
\z[30]_INST_0_i_240\: unisim.vcomponents.LUT6
generic map(
INIT => X"0800888820220000"
)
port map (
I0 => \msb1__1\(31),
I1 => L1_carry_i_12_n_0,
I2 => \z[30]_INST_0_i_232_n_0\,
I3 => \_carry_i_1_n_0\,
I4 => L1_carry_i_9_n_0,
I5 => L1_carry_i_13_n_0,
O => \z[30]_INST_0_i_240_n_0\
);
\z[30]_INST_0_i_241\: unisim.vcomponents.LUT6
generic map(
INIT => X"66A6555500000000"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => L1_carry_i_9_n_0,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_232_n_0\,
I4 => L1_carry_i_12_n_0,
I5 => \msb1__1\(21),
O => \z[30]_INST_0_i_241_n_0\
);
\z[30]_INST_0_i_242\: unisim.vcomponents.LUT6
generic map(
INIT => X"66A6555500000000"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => L1_carry_i_9_n_0,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_232_n_0\,
I4 => L1_carry_i_12_n_0,
I5 => \msb1__1\(37),
O => \z[30]_INST_0_i_242_n_0\
);
\z[30]_INST_0_i_243\: unisim.vcomponents.LUT6
generic map(
INIT => X"66A6555500000000"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => L1_carry_i_9_n_0,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_232_n_0\,
I4 => L1_carry_i_12_n_0,
I5 => \msb1__1\(29),
O => \z[30]_INST_0_i_243_n_0\
);
\z[30]_INST_0_i_244\: unisim.vcomponents.LUT6
generic map(
INIT => X"66A6555500000000"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => L1_carry_i_9_n_0,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_232_n_0\,
I4 => L1_carry_i_12_n_0,
I5 => \msb1__1\(45),
O => \z[30]_INST_0_i_244_n_0\
);
\z[30]_INST_0_i_245\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFF5D5"
)
port map (
I0 => L1_carry_i_27_n_0,
I1 => \msb1__1\(32),
I2 => \z[30]_INST_0_i_246_n_0\,
I3 => \msb1__1\(33),
I4 => \msb1__1\(36),
I5 => \msb1__1\(37),
O => \z[30]_INST_0_i_245_n_0\
);
\z[30]_INST_0_i_246\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(35),
I1 => \msb1__1\(34),
O => \z[30]_INST_0_i_246_n_0\
);
\z[30]_INST_0_i_29\: unisim.vcomponents.LUT6
generic map(
INIT => X"4700FFFF47004700"
)
port map (
I0 => \z[30]_INST_0_i_94_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_96_n_0\,
I3 => \z[30]_INST_0_i_43_n_0\,
I4 => \z[30]_INST_0_i_97_n_0\,
I5 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_29_n_0\
);
\z[30]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \z[30]_INST_0_i_17_n_0\,
I1 => \z[30]_INST_0_i_18_n_0\,
I2 => \z[30]_INST_0_i_19_n_0\,
I3 => \z[30]_INST_0_i_20_n_0\,
I4 => \z[30]_INST_0_i_21_n_0\,
I5 => \z[30]_INST_0_i_22_n_0\,
O => \z[30]_INST_0_i_3_n_0\
);
\z[30]_INST_0_i_30\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_98_n_0\,
I1 => \z[30]_INST_0_i_99_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_100_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_101_n_0\,
O => \z[30]_INST_0_i_30_n_0\
);
\z[30]_INST_0_i_31\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_102_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_103_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_31_n_0\
);
\z[30]_INST_0_i_32\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_104_n_0\,
I1 => \z[30]_INST_0_i_105_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_99_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_106_n_0\,
O => \z[30]_INST_0_i_32_n_0\
);
\z[30]_INST_0_i_33\: unisim.vcomponents.LUT6
generic map(
INIT => X"47FF474700FF0000"
)
port map (
I0 => \z[30]_INST_0_i_107_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_94_n_0\,
I3 => \z[30]_INST_0_i_97_n_0\,
I4 => \z[30]_INST_0_i_43_n_0\,
I5 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_33_n_0\
);
\z[30]_INST_0_i_34\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_101_n_0\,
I1 => \z[30]_INST_0_i_104_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_98_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_99_n_0\,
O => \z[30]_INST_0_i_34_n_0\
);
\z[30]_INST_0_i_35\: unisim.vcomponents.LUT6
generic map(
INIT => X"4700FFFF47004700"
)
port map (
I0 => \z[30]_INST_0_i_107_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_94_n_0\,
I3 => \z[30]_INST_0_i_43_n_0\,
I4 => \z[30]_INST_0_i_102_n_0\,
I5 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_35_n_0\
);
\z[30]_INST_0_i_36\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_99_n_0\,
I1 => \z[30]_INST_0_i_106_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_101_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_104_n_0\,
O => \z[30]_INST_0_i_36_n_0\
);
\z[30]_INST_0_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_106_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_108_n_0\,
O => \z[30]_INST_0_i_37_n_0\
);
\z[30]_INST_0_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_104_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_105_n_0\,
O => \z[30]_INST_0_i_38_n_0\
);
\z[30]_INST_0_i_39\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_103_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_109_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_39_n_0\
);
\z[30]_INST_0_i_40\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[30]_INST_0_i_110_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_111_n_0\,
I3 => L1_carry_i_16_n_0,
I4 => \z[30]_INST_0_i_112_n_0\,
O => \z[30]_INST_0_i_40_n_0\
);
\z[30]_INST_0_i_41\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[30]_INST_0_i_108_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_113_n_0\,
I3 => L1_carry_i_16_n_0,
I4 => \z[30]_INST_0_i_114_n_0\,
O => \z[30]_INST_0_i_41_n_0\
);
\z[30]_INST_0_i_42\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFD8"
)
port map (
I0 => L1,
I1 => L1_carry_i_16_n_0,
I2 => \_carry_n_6\,
I3 => \z[30]_INST_0_i_115_n_0\,
I4 => \z[30]_INST_0_i_95_n_0\,
O => \z[30]_INST_0_i_42_n_0\
);
\z[30]_INST_0_i_43\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \_carry_i_1_n_0\,
I1 => \z[30]_INST_0_i_116_n_0\,
O => \z[30]_INST_0_i_43_n_0\
);
\z[30]_INST_0_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_105_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_110_n_0\,
O => \z[30]_INST_0_i_44_n_0\
);
\z[30]_INST_0_i_45\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000040F00000404"
)
port map (
I0 => \z[30]_INST_0_i_117_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_95_n_0\,
I3 => \z[30]_INST_0_i_115_n_0\,
I4 => \z[30]_INST_0_i_118_n_0\,
I5 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_45_n_0\
);
\z[30]_INST_0_i_46\: unisim.vcomponents.LUT5
generic map(
INIT => X"10FF1010"
)
port map (
I0 => \z[30]_INST_0_i_95_n_0\,
I1 => \z[30]_INST_0_i_119_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_109_n_0\,
I4 => \z[30]_INST_0_i_43_n_0\,
O => \z[30]_INST_0_i_46_n_0\
);
\z[30]_INST_0_i_47\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_120_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_121_n_0\,
O => \z[30]_INST_0_i_47_n_0\
);
\z[30]_INST_0_i_48\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_122_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_123_n_0\,
O => \z[30]_INST_0_i_48_n_0\
);
\z[30]_INST_0_i_49\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_124_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_125_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_49_n_0\
);
\z[30]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"115F1F5F"
)
port map (
I0 => \z[30]_INST_0_i_29_n_0\,
I1 => \z[30]_INST_0_i_30_n_0\,
I2 => \z[30]_INST_0_i_31_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_32_n_0\,
O => \z[30]_INST_0_i_5_n_0\
);
\z[30]_INST_0_i_50\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_123_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_100_n_0\,
O => \z[30]_INST_0_i_50_n_0\
);
\z[30]_INST_0_i_51\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_125_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_126_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_51_n_0\
);
\z[30]_INST_0_i_52\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_126_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_127_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_52_n_0\
);
\z[30]_INST_0_i_53\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_121_n_0\,
I1 => \z[30]_INST_0_i_98_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_123_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_100_n_0\,
O => \z[30]_INST_0_i_53_n_0\
);
\z[30]_INST_0_i_54\: unisim.vcomponents.LUT6
generic map(
INIT => X"47FF474700FF0000"
)
port map (
I0 => \z[30]_INST_0_i_94_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_96_n_0\,
I3 => \z[30]_INST_0_i_127_n_0\,
I4 => \z[30]_INST_0_i_43_n_0\,
I5 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_54_n_0\
);
\z[30]_INST_0_i_55\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_100_n_0\,
I1 => \z[30]_INST_0_i_101_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_121_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_98_n_0\,
O => \z[30]_INST_0_i_55_n_0\
);
\z[30]_INST_0_i_56\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_128_n_0\,
I1 => \z[30]_INST_0_i_129_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_130_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_131_n_0\,
O => \z[30]_INST_0_i_56_n_0\
);
\z[30]_INST_0_i_57\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \_carry_i_1_n_0\,
I1 => \z[30]_INST_0_i_116_n_0\,
O => \z[30]_INST_0_i_57_n_0\
);
\z[30]_INST_0_i_58\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_132_n_0\,
I1 => \z[30]_INST_0_i_133_n_0\,
I2 => \z[30]_INST_0_i_95_n_0\,
I3 => \z[30]_INST_0_i_134_n_0\,
I4 => \z[30]_INST_0_i_118_n_0\,
I5 => \z[30]_INST_0_i_135_n_0\,
O => \z[30]_INST_0_i_58_n_0\
);
\z[30]_INST_0_i_59\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_136_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_137_n_0\,
O => \z[30]_INST_0_i_59_n_0\
);
\z[30]_INST_0_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"115F1F5F"
)
port map (
I0 => \z[30]_INST_0_i_33_n_0\,
I1 => \z[30]_INST_0_i_34_n_0\,
I2 => \z[30]_INST_0_i_35_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_36_n_0\,
O => \z[30]_INST_0_i_6_n_0\
);
\z[30]_INST_0_i_60\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \z[30]_INST_0_i_138_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_139_n_0\,
I3 => \_carry_i_10_n_0\,
I4 => \z[30]_INST_0_i_122_n_0\,
O => \z[30]_INST_0_i_60_n_0\
);
\z[30]_INST_0_i_61\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \z[30]_INST_0_i_140_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_141_n_0\,
I3 => \_carry_i_10_n_0\,
I4 => \z[30]_INST_0_i_142_n_0\,
O => \z[30]_INST_0_i_61_n_0\
);
\z[30]_INST_0_i_62\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_58_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_143_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_62_n_0\
);
\z[30]_INST_0_i_63\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_143_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_144_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_63_n_0\
);
\z[30]_INST_0_i_64\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_142_n_0\,
I1 => \z[30]_INST_0_i_120_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_145_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_122_n_0\,
O => \z[30]_INST_0_i_64_n_0\
);
\z[30]_INST_0_i_65\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_144_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_124_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_65_n_0\
);
\z[30]_INST_0_i_66\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_122_n_0\,
I1 => \z[30]_INST_0_i_123_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_142_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_120_n_0\,
O => \z[30]_INST_0_i_66_n_0\
);
\z[30]_INST_0_i_67\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_146_n_0\,
I1 => \z[30]_INST_0_i_147_n_0\,
I2 => \z[30]_INST_0_i_95_n_0\,
I3 => \z[30]_INST_0_i_148_n_0\,
I4 => \z[30]_INST_0_i_118_n_0\,
I5 => \z[30]_INST_0_i_149_n_0\,
O => \z[30]_INST_0_i_67_n_0\
);
\z[30]_INST_0_i_68\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_150_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_151_n_0\,
O => \z[30]_INST_0_i_68_n_0\
);
\z[30]_INST_0_i_69\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_152_n_0\,
I1 => \z[30]_INST_0_i_153_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_154_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_155_n_0\,
O => \z[30]_INST_0_i_69_n_0\
);
\z[30]_INST_0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_37_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_38_n_0\,
I4 => \z[30]_INST_0_i_39_n_0\,
O => sel0(3)
);
\z[30]_INST_0_i_70\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_137_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_156_n_0\,
O => \z[30]_INST_0_i_70_n_0\
);
\z[30]_INST_0_i_71\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_155_n_0\,
I1 => \z[30]_INST_0_i_130_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_152_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_153_n_0\,
O => \z[30]_INST_0_i_71_n_0\
);
\z[30]_INST_0_i_72\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_157_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_150_n_0\,
O => \z[30]_INST_0_i_72_n_0\
);
\z[30]_INST_0_i_73\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_153_n_0\,
I1 => \z[30]_INST_0_i_128_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_155_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_130_n_0\,
O => \z[30]_INST_0_i_73_n_0\
);
\z[30]_INST_0_i_74\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_130_n_0\,
I1 => \z[30]_INST_0_i_131_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_153_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_128_n_0\,
O => \z[30]_INST_0_i_74_n_0\
);
\z[30]_INST_0_i_75\: unisim.vcomponents.LUT6
generic map(
INIT => X"000002A2AAAA02A2"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_158_n_0\,
I2 => \_carry_i_10_n_0\,
I3 => \z[30]_INST_0_i_159_n_0\,
I4 => \_carry_i_1_n_0\,
I5 => \z[30]_INST_0_i_160_n_0\,
O => \z[30]_INST_0_i_75_n_0\
);
\z[30]_INST_0_i_76\: unisim.vcomponents.LUT6
generic map(
INIT => X"4C4C4C4040404C40"
)
port map (
I0 => \z[30]_INST_0_i_161_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_95_n_0\,
I3 => \z[30]_INST_0_i_162_n_0\,
I4 => \z[30]_INST_0_i_118_n_0\,
I5 => \z[30]_INST_0_i_163_n_0\,
O => \z[30]_INST_0_i_76_n_0\
);
\z[30]_INST_0_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \z[30]_INST_0_i_81_n_0\,
I1 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_77_n_0\
);
\z[30]_INST_0_i_78\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_164_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_155_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_154_n_0\,
O => \z[30]_INST_0_i_78_n_0\
);
\z[30]_INST_0_i_79\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \z[30]_INST_0_i_57_n_0\,
I1 => \z[30]_INST_0_i_67_n_0\,
O => \z[30]_INST_0_i_79_n_0\
);
\z[30]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"8A80FFFF8A808A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_40_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_41_n_0\,
I4 => \z[30]_INST_0_i_42_n_0\,
I5 => \z[30]_INST_0_i_43_n_0\,
O => sel0(0)
);
\z[30]_INST_0_i_80\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \z[30]_INST_0_i_82_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
O => \z[30]_INST_0_i_80_n_0\
);
\z[30]_INST_0_i_81\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_148_n_0\,
I1 => \z[30]_INST_0_i_149_n_0\,
I2 => \z[30]_INST_0_i_95_n_0\,
I3 => \z[30]_INST_0_i_147_n_0\,
I4 => \z[30]_INST_0_i_118_n_0\,
I5 => \z[30]_INST_0_i_165_n_0\,
O => \z[30]_INST_0_i_81_n_0\
);
\z[30]_INST_0_i_82\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFC05F5FCFC05050"
)
port map (
I0 => \z[30]_INST_0_i_163_n_0\,
I1 => \z[30]_INST_0_i_135_n_0\,
I2 => \z[30]_INST_0_i_95_n_0\,
I3 => \z[30]_INST_0_i_166_n_0\,
I4 => \z[30]_INST_0_i_118_n_0\,
I5 => \z[30]_INST_0_i_167_n_0\,
O => \z[30]_INST_0_i_82_n_0\
);
\z[30]_INST_0_i_83\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_158_n_0\,
I1 => \z[30]_INST_0_i_152_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_168_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_154_n_0\,
O => \z[30]_INST_0_i_83_n_0\
);
\z[30]_INST_0_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[30]_INST_0_i_41_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[30]_INST_0_i_44_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_45_n_0\,
O => \z[30]_INST_0_i_9_n_0\
);
\z[30]_INST_0_i_94\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF4F7"
)
port map (
I0 => \msb1__1\(1),
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \z[30]_INST_0_i_169_n_0\,
I3 => \msb1__1\(5),
I4 => \z[30]_INST_0_i_170_n_0\,
O => \z[30]_INST_0_i_94_n_0\
);
\z[30]_INST_0_i_95\: unisim.vcomponents.LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => \_carry_n_7\,
I1 => \_carry_i_10_n_0\,
I2 => L1,
O => \z[30]_INST_0_i_95_n_0\
);
\z[30]_INST_0_i_96\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF4F7"
)
port map (
I0 => \msb1__1\(3),
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \z[30]_INST_0_i_170_n_0\,
I3 => \msb1__1\(7),
I4 => \z[30]_INST_0_i_169_n_0\,
O => \z[30]_INST_0_i_96_n_0\
);
\z[30]_INST_0_i_97\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_171_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_172_n_0\,
O => \z[30]_INST_0_i_97_n_0\
);
\z[30]_INST_0_i_98\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_173_n_0\,
I1 => \z[30]_INST_0_i_174_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_175_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_176_n_0\,
O => \z[30]_INST_0_i_98_n_0\
);
\z[30]_INST_0_i_99\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_177_n_0\,
I1 => \z[30]_INST_0_i_178_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_179_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_180_n_0\,
O => \z[30]_INST_0_i_99_n_0\
);
\z[3]_INST_0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \z[3]_INST_0_i_1_n_0\,
CO(2) => \z[3]_INST_0_i_1_n_1\,
CO(1) => \z[3]_INST_0_i_1_n_2\,
CO(0) => \z[3]_INST_0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => sel0(0),
O(3 downto 0) => z_mantissa(3 downto 0),
S(3) => \z[3]_INST_0_i_2_n_0\,
S(2) => \z[3]_INST_0_i_3_n_0\,
S(1) => sel0(1),
S(0) => \z[3]_INST_0_i_5_n_0\
);
\z[3]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_37_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_38_n_0\,
I4 => \z[30]_INST_0_i_39_n_0\,
O => \z[3]_INST_0_i_2_n_0\
);
\z[3]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_44_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_37_n_0\,
I4 => \z[30]_INST_0_i_46_n_0\,
O => \z[3]_INST_0_i_3_n_0\
);
\z[3]_INST_0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_9_n_0\,
O => sel0(1)
);
\z[3]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAA9AA"
)
port map (
I0 => sel0(0),
I1 => \z[30]_INST_0_i_3_n_0\,
I2 => \z[3]_INST_0_i_6_n_0\,
I3 => \z[3]_INST_0_i_7_n_0\,
I4 => \z[3]_INST_0_i_8_n_0\,
I5 => \z[3]_INST_0_i_9_n_0\,
O => \z[3]_INST_0_i_5_n_0\
);
\z[3]_INST_0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => sel0(0),
I1 => sel0(2),
I2 => \z[7]_INST_0_i_8_n_0\,
I3 => \z[7]_INST_0_i_6_n_0\,
O => \z[3]_INST_0_i_6_n_0\
);
\z[3]_INST_0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => \z[7]_INST_0_i_9_n_0\,
I1 => sel0(10),
I2 => \z[30]_INST_0_i_11_n_0\,
I3 => \z[30]_INST_0_i_15_n_0\,
O => \z[3]_INST_0_i_7_n_0\
);
\z[3]_INST_0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => \z[15]_INST_0_i_7_n_0\,
I1 => \z[15]_INST_0_i_6_n_0\,
I2 => sel0(3),
I3 => \z[7]_INST_0_i_7_n_0\,
O => \z[3]_INST_0_i_8_n_0\
);
\z[3]_INST_0_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \z[30]_INST_0_i_9_n_0\,
I1 => \z[11]_INST_0_i_6_n_0\,
I2 => \z[11]_INST_0_i_7_n_0\,
I3 => \z[30]_INST_0_i_14_n_0\,
O => \z[3]_INST_0_i_9_n_0\
);
\z[7]_INST_0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \z[3]_INST_0_i_1_n_0\,
CO(3) => \z[7]_INST_0_i_1_n_0\,
CO(2) => \z[7]_INST_0_i_1_n_1\,
CO(1) => \z[7]_INST_0_i_1_n_2\,
CO(0) => \z[7]_INST_0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => z_mantissa(7 downto 4),
S(3 downto 0) => sel0(7 downto 4)
);
\z[7]_INST_0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_98_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_99_n_0\,
O => \z[7]_INST_0_i_10_n_0\
);
\z[7]_INST_0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_101_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_104_n_0\,
O => \z[7]_INST_0_i_11_n_0\
);
\z[7]_INST_0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_99_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_106_n_0\,
O => \z[7]_INST_0_i_12_n_0\
);
\z[7]_INST_0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[7]_INST_0_i_6_n_0\,
O => sel0(7)
);
\z[7]_INST_0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[7]_INST_0_i_7_n_0\,
O => sel0(6)
);
\z[7]_INST_0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[7]_INST_0_i_8_n_0\,
O => sel0(5)
);
\z[7]_INST_0_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[7]_INST_0_i_9_n_0\,
O => sel0(4)
);
\z[7]_INST_0_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[7]_INST_0_i_10_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[11]_INST_0_i_9_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_29_n_0\,
O => \z[7]_INST_0_i_6_n_0\
);
\z[7]_INST_0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[7]_INST_0_i_11_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[7]_INST_0_i_10_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_33_n_0\,
O => \z[7]_INST_0_i_7_n_0\
);
\z[7]_INST_0_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[7]_INST_0_i_12_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[7]_INST_0_i_11_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_35_n_0\,
O => \z[7]_INST_0_i_8_n_0\
);
\z[7]_INST_0_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[30]_INST_0_i_38_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[7]_INST_0_i_12_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_31_n_0\,
O => \z[7]_INST_0_i_9_n_0\
);
\z_exponent0__0_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \z_exponent0__0_carry_n_0\,
CO(2) => \z_exponent0__0_carry_n_1\,
CO(1) => \z_exponent0__0_carry_n_2\,
CO(0) => \z_exponent0__0_carry_n_3\,
CYINIT => '1',
DI(3) => \z_exponent0__0_carry_i_1_n_0\,
DI(2) => \z_exponent0__0_carry_i_2_n_0\,
DI(1) => \z_exponent0__0_carry_i_3_n_0\,
DI(0) => '1',
O(3 downto 0) => data0(3 downto 0),
S(3) => \z_exponent0__0_carry_i_4_n_0\,
S(2) => \z_exponent0__0_carry_i_5_n_0\,
S(1) => \z_exponent0__0_carry_i_6_n_0\,
S(0) => \z_exponent0__0_carry_i_7_n_0\
);
\z_exponent0__0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \z_exponent0__0_carry_n_0\,
CO(3) => \NLW_z_exponent0__0_carry__0_CO_UNCONNECTED\(3),
CO(2) => \z_exponent0__0_carry__0_n_1\,
CO(1) => \z_exponent0__0_carry__0_n_2\,
CO(0) => \z_exponent0__0_carry__0_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \z_exponent0__0_carry__0_i_1_n_0\,
DI(1) => \z_exponent0__0_carry__0_i_2_n_0\,
DI(0) => \z_exponent0__0_carry__0_i_3_n_0\,
O(3 downto 0) => data0(7 downto 4),
S(3) => \z_exponent0__0_carry__0_i_4_n_0\,
S(2) => \z_exponent0__0_carry__0_i_5_n_0\,
S(1) => \z_exponent0__0_carry__0_i_6_n_0\,
S(0) => \z_exponent0__0_carry__0_i_7_n_0\
);
\z_exponent0__0_carry__0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFA9A900"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => \z_exponent0__0_carry__0_i_8_n_0\,
I2 => L1_carry_i_12_n_0,
I3 => y(28),
I4 => x(28),
O => \z_exponent0__0_carry__0_i_1_n_0\
);
\z_exponent0__0_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F990"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => \z_exponent0__0_carry__0_i_8_n_0\,
I2 => y(27),
I3 => x(27),
O => \z_exponent0__0_carry__0_i_2_n_0\
);
\z_exponent0__0_carry__0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF1E1E00"
)
port map (
I0 => L1_carry_i_10_n_0,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_9_n_0,
I3 => y(26),
I4 => x(26),
O => \z_exponent0__0_carry__0_i_3_n_0\
);
\z_exponent0__0_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6999699969999996"
)
port map (
I0 => x(30),
I1 => y(30),
I2 => x(29),
I3 => y(29),
I4 => \msb1__1\(47),
I5 => \msb1__1\(46),
O => \z_exponent0__0_carry__0_i_4_n_0\
);
\z_exponent0__0_carry__0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"96969669"
)
port map (
I0 => \z_exponent0__0_carry__0_i_1_n_0\,
I1 => y(29),
I2 => x(29),
I3 => \msb1__1\(46),
I4 => \msb1__1\(47),
O => \z_exponent0__0_carry__0_i_5_n_0\
);
\z_exponent0__0_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"56A9A956A95656A9"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => \z_exponent0__0_carry__0_i_8_n_0\,
I2 => L1_carry_i_12_n_0,
I3 => \z_exponent0__0_carry__0_i_2_n_0\,
I4 => y(28),
I5 => x(28),
O => \z_exponent0__0_carry__0_i_6_n_0\
);
\z_exponent0__0_carry__0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => \z_exponent0__0_carry__0_i_8_n_0\,
I2 => \z_exponent0__0_carry__0_i_3_n_0\,
I3 => x(27),
I4 => y(27),
O => \z_exponent0__0_carry__0_i_7_n_0\
);
\z_exponent0__0_carry__0_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => L1_carry_i_10_n_0,
I2 => L1_carry_i_11_n_0,
O => \z_exponent0__0_carry__0_i_8_n_0\
);
\z_exponent0__0_carry_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F660"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_10_n_0,
I2 => y(25),
I3 => x(25),
O => \z_exponent0__0_carry_i_1_n_0\
);
\z_exponent0__0_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y(24),
I1 => x(24),
I2 => L1_carry_i_10_n_0,
O => \z_exponent0__0_carry_i_2_n_0\
);
\z_exponent0__0_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => x(23),
I1 => y(23),
I2 => \_carry_i_1_n_0\,
O => \z_exponent0__0_carry_i_3_n_0\
);
\z_exponent0__0_carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"E11E1EE11EE1E11E"
)
port map (
I0 => L1_carry_i_10_n_0,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_9_n_0,
I3 => \z_exponent0__0_carry_i_1_n_0\,
I4 => y(26),
I5 => x(26),
O => \z_exponent0__0_carry_i_4_n_0\
);
\z_exponent0__0_carry_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_10_n_0,
I2 => \z_exponent0__0_carry_i_2_n_0\,
I3 => y(25),
I4 => x(25),
O => \z_exponent0__0_carry_i_5_n_0\
);
\z_exponent0__0_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y(24),
I1 => L1_carry_i_10_n_0,
I2 => x(24),
I3 => \z_exponent0__0_carry_i_3_n_0\,
O => \z_exponent0__0_carry_i_6_n_0\
);
\z_exponent0__0_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => x(23),
I1 => y(23),
I2 => \_carry_i_1_n_0\,
O => \z_exponent0__0_carry_i_7_n_0\
);
z_exponent1_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => z_exponent1_carry_n_0,
CO(2) => z_exponent1_carry_n_1,
CO(1) => z_exponent1_carry_n_2,
CO(0) => z_exponent1_carry_n_3,
CYINIT => '0',
DI(3) => \z_exponent0__0_carry_i_1_n_0\,
DI(2) => \z_exponent0__0_carry_i_2_n_0\,
DI(1) => \z_exponent1_carry_i_1__0_n_0\,
DI(0) => x(23),
O(3 downto 0) => data1(3 downto 0),
S(3) => \z_exponent1_carry_i_2__0_n_0\,
S(2) => \z_exponent1_carry_i_3__0_n_0\,
S(1) => z_exponent1_carry_i_4_n_0,
S(0) => z_exponent1_carry_i_5_n_0
);
\z_exponent1_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => z_exponent1_carry_n_0,
CO(3) => \NLW_z_exponent1_carry__0_CO_UNCONNECTED\(3),
CO(2) => \z_exponent1_carry__0_n_1\,
CO(1) => \z_exponent1_carry__0_n_2\,
CO(0) => \z_exponent1_carry__0_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \z_exponent0__0_carry__0_i_1_n_0\,
DI(1) => \z_exponent0__0_carry__0_i_2_n_0\,
DI(0) => \z_exponent0__0_carry__0_i_3_n_0\,
O(3 downto 0) => data1(7 downto 4),
S(3) => z_exponent1_carry_i_1_n_0,
S(2) => z_exponent1_carry_i_2_n_0,
S(1) => z_exponent1_carry_i_3_n_0,
S(0) => \z_exponent1_carry_i_4__0_n_0\
);
z_exponent1_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"6999699969999996"
)
port map (
I0 => x(30),
I1 => y(30),
I2 => x(29),
I3 => y(29),
I4 => \msb1__1\(47),
I5 => \msb1__1\(46),
O => z_exponent1_carry_i_1_n_0
);
\z_exponent1_carry_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => y(23),
I1 => \_carry_i_1_n_0\,
O => \z_exponent1_carry_i_1__0_n_0\
);
z_exponent1_carry_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"96969669"
)
port map (
I0 => \z_exponent0__0_carry__0_i_1_n_0\,
I1 => y(29),
I2 => x(29),
I3 => \msb1__1\(46),
I4 => \msb1__1\(47),
O => z_exponent1_carry_i_2_n_0
);
\z_exponent1_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"E11E1EE11EE1E11E"
)
port map (
I0 => L1_carry_i_10_n_0,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_9_n_0,
I3 => \z_exponent0__0_carry_i_1_n_0\,
I4 => y(26),
I5 => x(26),
O => \z_exponent1_carry_i_2__0_n_0\
);
z_exponent1_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"56A9A956A95656A9"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => \z_exponent0__0_carry__0_i_8_n_0\,
I2 => L1_carry_i_12_n_0,
I3 => \z_exponent0__0_carry__0_i_2_n_0\,
I4 => y(28),
I5 => x(28),
O => z_exponent1_carry_i_3_n_0
);
\z_exponent1_carry_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_10_n_0,
I2 => y(25),
I3 => x(25),
I4 => \z_exponent0__0_carry_i_2_n_0\,
O => \z_exponent1_carry_i_3__0_n_0\
);
z_exponent1_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y(24),
I1 => x(24),
I2 => L1_carry_i_10_n_0,
I3 => \z_exponent1_carry_i_1__0_n_0\,
O => z_exponent1_carry_i_4_n_0
);
\z_exponent1_carry_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => \z_exponent0__0_carry__0_i_8_n_0\,
I2 => y(27),
I3 => x(27),
I4 => \z_exponent0__0_carry__0_i_3_n_0\,
O => \z_exponent1_carry_i_4__0_n_0\
);
z_exponent1_carry_i_5: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => y(23),
I1 => \_carry_i_1_n_0\,
I2 => x(23),
O => z_exponent1_carry_i_5_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity affine_block_ieee754_fp_multiplier_1_0 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of affine_block_ieee754_fp_multiplier_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of affine_block_ieee754_fp_multiplier_1_0 : entity is "affine_block_ieee754_fp_multiplier_1_0,ieee754_fp_multiplier,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of affine_block_ieee754_fp_multiplier_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of affine_block_ieee754_fp_multiplier_1_0 : entity is "ieee754_fp_multiplier,Vivado 2016.4";
end affine_block_ieee754_fp_multiplier_1_0;
architecture STRUCTURE of affine_block_ieee754_fp_multiplier_1_0 is
signal \z[30]_INST_0_i_23_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_24_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_25_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_26_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_27_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_28_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_84_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_85_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_86_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_87_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_88_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_89_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_90_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_91_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_92_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_93_n_0\ : STD_LOGIC;
signal z_mantissa : STD_LOGIC_VECTOR ( 22 downto 0 );
begin
U0: entity work.affine_block_ieee754_fp_multiplier_1_0_ieee754_fp_multiplier
port map (
x(30 downto 0) => x(30 downto 0),
y(30 downto 0) => y(30 downto 0),
\y_11__s_port_\ => \z[30]_INST_0_i_4_n_0\,
z(7 downto 0) => z(30 downto 23),
z_mantissa(22 downto 0) => z_mantissa(22 downto 0)
);
\z[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(0),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(0)
);
\z[10]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(10),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(10)
);
\z[11]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(11),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(11)
);
\z[12]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(12),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(12)
);
\z[13]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(13),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(13)
);
\z[14]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(14),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(14)
);
\z[15]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(15),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(15)
);
\z[16]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(16),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(16)
);
\z[17]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(17),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(17)
);
\z[18]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(18),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(18)
);
\z[19]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(19),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(19)
);
\z[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(1),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(1)
);
\z[20]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(20),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(20)
);
\z[21]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(21),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(21)
);
\z[22]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(22),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(22)
);
\z[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(2),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(2)
);
\z[30]_INST_0_i_23\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => x(29),
I1 => x(4),
I2 => x(11),
I3 => x(13),
I4 => \z[30]_INST_0_i_84_n_0\,
O => \z[30]_INST_0_i_23_n_0\
);
\z[30]_INST_0_i_24\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => x(25),
I1 => x(20),
I2 => x(15),
I3 => x(22),
I4 => \z[30]_INST_0_i_85_n_0\,
O => \z[30]_INST_0_i_24_n_0\
);
\z[30]_INST_0_i_25\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \z[30]_INST_0_i_86_n_0\,
I1 => \z[30]_INST_0_i_87_n_0\,
I2 => \z[30]_INST_0_i_88_n_0\,
I3 => x(24),
I4 => x(10),
I5 => x(2),
O => \z[30]_INST_0_i_25_n_0\
);
\z[30]_INST_0_i_26\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => y(30),
I1 => y(5),
I2 => y(0),
I3 => y(1),
I4 => \z[30]_INST_0_i_89_n_0\,
O => \z[30]_INST_0_i_26_n_0\
);
\z[30]_INST_0_i_27\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => y(29),
I1 => y(18),
I2 => y(2),
I3 => y(10),
I4 => \z[30]_INST_0_i_90_n_0\,
O => \z[30]_INST_0_i_27_n_0\
);
\z[30]_INST_0_i_28\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \z[30]_INST_0_i_91_n_0\,
I1 => \z[30]_INST_0_i_92_n_0\,
I2 => \z[30]_INST_0_i_93_n_0\,
I3 => y(12),
I4 => y(20),
I5 => y(4),
O => \z[30]_INST_0_i_28_n_0\
);
\z[30]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"101010FF10101010"
)
port map (
I0 => \z[30]_INST_0_i_23_n_0\,
I1 => \z[30]_INST_0_i_24_n_0\,
I2 => \z[30]_INST_0_i_25_n_0\,
I3 => \z[30]_INST_0_i_26_n_0\,
I4 => \z[30]_INST_0_i_27_n_0\,
I5 => \z[30]_INST_0_i_28_n_0\,
O => \z[30]_INST_0_i_4_n_0\
);
\z[30]_INST_0_i_84\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => x(9),
I1 => x(3),
I2 => x(17),
I3 => x(7),
O => \z[30]_INST_0_i_84_n_0\
);
\z[30]_INST_0_i_85\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => x(18),
I1 => x(30),
I2 => x(21),
I3 => x(6),
O => \z[30]_INST_0_i_85_n_0\
);
\z[30]_INST_0_i_86\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => x(14),
I1 => x(12),
I2 => x(8),
I3 => x(27),
O => \z[30]_INST_0_i_86_n_0\
);
\z[30]_INST_0_i_87\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => x(28),
I1 => x(23),
I2 => x(19),
I3 => x(1),
O => \z[30]_INST_0_i_87_n_0\
);
\z[30]_INST_0_i_88\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => x(0),
I1 => x(26),
I2 => x(16),
I3 => x(5),
O => \z[30]_INST_0_i_88_n_0\
);
\z[30]_INST_0_i_89\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => y(14),
I1 => y(8),
I2 => y(24),
I3 => y(27),
O => \z[30]_INST_0_i_89_n_0\
);
\z[30]_INST_0_i_90\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => y(7),
I1 => y(26),
I2 => y(17),
I3 => y(6),
O => \z[30]_INST_0_i_90_n_0\
);
\z[30]_INST_0_i_91\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => y(21),
I1 => y(15),
I2 => y(22),
I3 => y(23),
O => \z[30]_INST_0_i_91_n_0\
);
\z[30]_INST_0_i_92\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => y(19),
I1 => y(28),
I2 => y(9),
I3 => y(3),
O => \z[30]_INST_0_i_92_n_0\
);
\z[30]_INST_0_i_93\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => y(16),
I1 => y(25),
I2 => y(13),
I3 => y(11),
O => \z[30]_INST_0_i_93_n_0\
);
\z[31]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y(31),
I1 => x(31),
O => z(31)
);
\z[3]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(3),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(3)
);
\z[4]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(4),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(4)
);
\z[5]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(5),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(5)
);
\z[6]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(6),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(6)
);
\z[7]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(7),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(7)
);
\z[8]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(8),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(8)
);
\z[9]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(9),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(9)
);
end STRUCTURE;
| mit | ffa4f630cfb3d7e8d5ce787e77b40de8 | 0.487259 | 2.258717 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/vga_split_controller/vga_split_controller.srcs/sources_1/new/vga_split_controller.vhd | 1 | 1,218 | ----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: vga_split_controller - Structural
-- Description: Create a split screen effect from two inputs
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity vga_split_controller is
generic(
HALF_ROW: integer := 320
);
port(
rgb_0: in std_logic_vector(15 downto 0);
rgb_1: in std_logic_vector(15 downto 0);
clock: in std_logic;
hsync: in std_logic;
rgb: out std_logic_vector(15 downto 0)
);
end vga_split_controller;
architecture Structural of vga_split_controller is
begin
process(clock)
variable counter : integer := 0;
begin
if rising_edge(clock) then
if hsync = '0' then
if counter < HALF_ROW then
rgb <= rgb_0;
else
rgb <= rgb_1;
end if;
counter := counter + 1;
else
counter := 0;
end if;
end if;
end process;
end Structural;
| mit | c5655fc7284747d9568a31eac440c5ed | 0.473727 | 4.631179 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_sync_ref_1_0/sim/system_vga_sync_ref_1_0.vhd | 2 | 3,959 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_sync_ref:1.0
-- IP Revision: 65
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_sync_ref_1_0 IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
start : OUT STD_LOGIC;
active : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_vga_sync_ref_1_0;
ARCHITECTURE system_vga_sync_ref_1_0_arch OF system_vga_sync_ref_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_sync_ref_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_sync_ref IS
GENERIC (
H_SIZE : INTEGER;
H_SYNC_SIZE : INTEGER;
V_SIZE : INTEGER;
DELAY : INTEGER
);
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
start : OUT STD_LOGIC;
active : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT vga_sync_ref;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_sync_ref
GENERIC MAP (
H_SIZE => 640,
H_SYNC_SIZE => 144,
V_SIZE => 480,
DELAY => 2
)
PORT MAP (
clk => clk,
rst => rst,
hsync => hsync,
vsync => vsync,
start => start,
active => active,
xaddr => xaddr,
yaddr => yaddr
);
END system_vga_sync_ref_1_0_arch;
| mit | 135b148153446c792184c1c5b1b45475 | 0.698409 | 3.892822 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_hdmi_test/zed_hdmi_test.srcs/sources_1/bd/system/ip/system_vga_sync_0_0/sim/system_vga_sync_0_0.vhd | 1 | 4,100 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_sync:1.0
-- IP Revision: 13
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_sync_0_0 IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_vga_sync_0_0;
ARCHITECTURE system_vga_sync_0_0_arch OF system_vga_sync_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_sync_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_sync IS
GENERIC (
H_SIZE : INTEGER;
H_FRONT_DELAY : INTEGER;
H_BACK_DELAY : INTEGER;
H_RETRACE_DELAY : INTEGER;
V_SIZE : INTEGER;
V_FRONT_DELAY : INTEGER;
V_BACK_DELAY : INTEGER;
V_RETRACE_DELAY : INTEGER
);
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT vga_sync;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_sync
GENERIC MAP (
H_SIZE => 640,
H_FRONT_DELAY => 16,
H_BACK_DELAY => 48,
H_RETRACE_DELAY => 96,
V_SIZE => 480,
V_FRONT_DELAY => 10,
V_BACK_DELAY => 33,
V_RETRACE_DELAY => 2
)
PORT MAP (
clk => clk,
rst => rst,
active => active,
hsync => hsync,
vsync => vsync,
xaddr => xaddr,
yaddr => yaddr
);
END system_vga_sync_0_0_arch;
| mit | 610114f64fee44bbeecd5760c025d4d2 | 0.692683 | 3.867925 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_zed_hdmi_0_0/synth/system_zed_hdmi_0_0.vhd | 6 | 4,878 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:zed_hdmi:1.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_zed_hdmi_0_0 IS
PORT (
clk : IN STD_LOGIC;
clk_x2 : IN STD_LOGIC;
clk_100 : IN STD_LOGIC;
active : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
rgb888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
hdmi_clk : OUT STD_LOGIC;
hdmi_hsync : OUT STD_LOGIC;
hdmi_vsync : OUT STD_LOGIC;
hdmi_d : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
hdmi_de : OUT STD_LOGIC;
hdmi_scl : OUT STD_LOGIC;
hdmi_sda : INOUT STD_LOGIC
);
END system_zed_hdmi_0_0;
ARCHITECTURE system_zed_hdmi_0_0_arch OF system_zed_hdmi_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_zed_hdmi_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT zed_hdmi IS
PORT (
clk : IN STD_LOGIC;
clk_x2 : IN STD_LOGIC;
clk_100 : IN STD_LOGIC;
active : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
rgb888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
hdmi_clk : OUT STD_LOGIC;
hdmi_hsync : OUT STD_LOGIC;
hdmi_vsync : OUT STD_LOGIC;
hdmi_d : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
hdmi_de : OUT STD_LOGIC;
hdmi_scl : OUT STD_LOGIC;
hdmi_sda : INOUT STD_LOGIC
);
END COMPONENT zed_hdmi;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_zed_hdmi_0_0_arch: ARCHITECTURE IS "zed_hdmi,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_zed_hdmi_0_0_arch : ARCHITECTURE IS "system_zed_hdmi_0_0,zed_hdmi,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_zed_hdmi_0_0_arch: ARCHITECTURE IS "system_zed_hdmi_0_0,zed_hdmi,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=zed_hdmi,x_ipVersion=1.0,x_ipCoreRevision=11,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF hdmi_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 hdmi_clk CLK";
BEGIN
U0 : zed_hdmi
PORT MAP (
clk => clk,
clk_x2 => clk_x2,
clk_100 => clk_100,
active => active,
hsync => hsync,
vsync => vsync,
rgb888 => rgb888,
hdmi_clk => hdmi_clk,
hdmi_hsync => hdmi_hsync,
hdmi_vsync => hdmi_vsync,
hdmi_d => hdmi_d,
hdmi_de => hdmi_de,
hdmi_scl => hdmi_scl,
hdmi_sda => hdmi_sda
);
END system_zed_hdmi_0_0_arch;
| mit | b4e3ed0cb279ec6a72be98716cd23e41 | 0.702132 | 3.670429 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_sync_reset_0_0/system_vga_sync_reset_0_0_sim_netlist.vhdl | 1 | 19,037 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue Jun 06 02:48:32 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_sync_reset_0_0/system_vga_sync_reset_0_0_sim_netlist.vhdl
-- Design : system_vga_sync_reset_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_reset_0_0_vga_sync_reset is
port (
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_sync_reset_0_0_vga_sync_reset : entity is "vga_sync_reset";
end system_vga_sync_reset_0_0_vga_sync_reset;
architecture STRUCTURE of system_vga_sync_reset_0_0_vga_sync_reset is
signal active_i_1_n_0 : STD_LOGIC;
signal active_i_2_n_0 : STD_LOGIC;
signal \h_count_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_3_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal hsync_i_1_n_0 : STD_LOGIC;
signal hsync_i_2_n_0 : STD_LOGIC;
signal hsync_i_3_n_0 : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 9 downto 1 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \v_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_2_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_5_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_6_n_0\ : STD_LOGIC;
signal vsync_i_1_n_0 : STD_LOGIC;
signal vsync_i_2_n_0 : STD_LOGIC;
signal \^xaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^yaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of active_i_2 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[1]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \h_count_reg[2]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \h_count_reg[3]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[4]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \h_count_reg[7]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \h_count_reg[8]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_4\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of hsync_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of hsync_i_3 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \v_count_reg[0]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \v_count_reg[1]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \v_count_reg[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[3]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[4]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \v_count_reg[7]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \v_count_reg[8]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_6\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of vsync_i_2 : label is "soft_lutpair3";
begin
xaddr(9 downto 0) <= \^xaddr\(9 downto 0);
yaddr(9 downto 0) <= \^yaddr\(9 downto 0);
active_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000222A00000000"
)
port map (
I0 => active_i_2_n_0,
I1 => \^xaddr\(9),
I2 => \^xaddr\(7),
I3 => \^xaddr\(8),
I4 => \^yaddr\(9),
I5 => rst,
O => active_i_1_n_0
);
active_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^yaddr\(7),
I1 => \^yaddr\(5),
I2 => \^yaddr\(6),
I3 => \^yaddr\(8),
O => active_i_2_n_0
);
active_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => active_i_1_n_0,
Q => active,
R => '0'
);
\h_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^xaddr\(0),
O => \h_count_reg[0]_i_1_n_0\
);
\h_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^xaddr\(0),
I1 => \^xaddr\(1),
O => plusOp(1)
);
\h_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^xaddr\(1),
I1 => \^xaddr\(0),
I2 => \^xaddr\(2),
O => plusOp(2)
);
\h_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^xaddr\(2),
I1 => \^xaddr\(0),
I2 => \^xaddr\(1),
I3 => \^xaddr\(3),
O => plusOp(3)
);
\h_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^xaddr\(3),
I1 => \^xaddr\(1),
I2 => \^xaddr\(0),
I3 => \^xaddr\(2),
I4 => \^xaddr\(4),
O => plusOp(4)
);
\h_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^xaddr\(4),
I1 => \^xaddr\(2),
I2 => \^xaddr\(0),
I3 => \^xaddr\(1),
I4 => \^xaddr\(3),
I5 => \^xaddr\(5),
O => plusOp(5)
);
\h_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \^xaddr\(5),
I1 => \h_count_reg[9]_i_3_n_0\,
I2 => \^xaddr\(6),
O => plusOp(6)
);
\h_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BF40"
)
port map (
I0 => \h_count_reg[9]_i_3_n_0\,
I1 => \^xaddr\(5),
I2 => \^xaddr\(6),
I3 => \^xaddr\(7),
O => plusOp(7)
);
\h_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF7F0080"
)
port map (
I0 => \^xaddr\(7),
I1 => \^xaddr\(6),
I2 => \^xaddr\(5),
I3 => \h_count_reg[9]_i_3_n_0\,
I4 => \^xaddr\(8),
O => plusOp(8)
);
\h_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"10000000FFFFFFFF"
)
port map (
I0 => \h_count_reg[9]_i_3_n_0\,
I1 => \^xaddr\(7),
I2 => \^xaddr\(8),
I3 => \^xaddr\(9),
I4 => \h_count_reg[9]_i_4_n_0\,
I5 => rst,
O => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"DFFFFFFF20000000"
)
port map (
I0 => \^xaddr\(8),
I1 => \h_count_reg[9]_i_3_n_0\,
I2 => \^xaddr\(5),
I3 => \^xaddr\(6),
I4 => \^xaddr\(7),
I5 => \^xaddr\(9),
O => plusOp(9)
);
\h_count_reg[9]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \^xaddr\(3),
I1 => \^xaddr\(1),
I2 => \^xaddr\(0),
I3 => \^xaddr\(2),
I4 => \^xaddr\(4),
O => \h_count_reg[9]_i_3_n_0\
);
\h_count_reg[9]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^xaddr\(5),
I1 => \^xaddr\(6),
O => \h_count_reg[9]_i_4_n_0\
);
\h_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg[0]_i_1_n_0\,
Q => \^xaddr\(0),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(1),
Q => \^xaddr\(1),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(2),
Q => \^xaddr\(2),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(3),
Q => \^xaddr\(3),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(4),
Q => \^xaddr\(4),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(5),
Q => \^xaddr\(5),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(6),
Q => \^xaddr\(6),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(7),
Q => \^xaddr\(7),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(8),
Q => \^xaddr\(8),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(9),
Q => \^xaddr\(9),
R => \h_count_reg[9]_i_1_n_0\
);
hsync_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"ABEAFFFF"
)
port map (
I0 => hsync_i_2_n_0,
I1 => \^xaddr\(5),
I2 => \^xaddr\(6),
I3 => hsync_i_3_n_0,
I4 => rst,
O => hsync_i_1_n_0
);
hsync_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => \^xaddr\(9),
I1 => \^xaddr\(8),
I2 => \^xaddr\(7),
O => hsync_i_2_n_0
);
hsync_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => \^xaddr\(2),
I1 => \^xaddr\(3),
I2 => \^xaddr\(0),
I3 => \^xaddr\(1),
I4 => \^xaddr\(4),
O => hsync_i_3_n_0
);
hsync_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => hsync_i_1_n_0,
Q => hsync,
R => '0'
);
\v_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^yaddr\(0),
O => \plusOp__0\(0)
);
\v_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^yaddr\(0),
I1 => \^yaddr\(1),
O => \plusOp__0\(1)
);
\v_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^yaddr\(1),
I1 => \^yaddr\(0),
I2 => \^yaddr\(2),
O => \plusOp__0\(2)
);
\v_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^yaddr\(2),
I1 => \^yaddr\(0),
I2 => \^yaddr\(1),
I3 => \^yaddr\(3),
O => \plusOp__0\(3)
);
\v_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^yaddr\(3),
I1 => \^yaddr\(1),
I2 => \^yaddr\(0),
I3 => \^yaddr\(2),
I4 => \^yaddr\(4),
O => \plusOp__0\(4)
);
\v_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^yaddr\(4),
I1 => \^yaddr\(2),
I2 => \^yaddr\(0),
I3 => \^yaddr\(1),
I4 => \^yaddr\(3),
I5 => \^yaddr\(5),
O => \plusOp__0\(5)
);
\v_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \^yaddr\(5),
I1 => \v_count_reg[9]_i_6_n_0\,
I2 => \^yaddr\(6),
O => \plusOp__0\(6)
);
\v_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F708"
)
port map (
I0 => \^yaddr\(5),
I1 => \^yaddr\(6),
I2 => \v_count_reg[9]_i_6_n_0\,
I3 => \^yaddr\(7),
O => \plusOp__0\(7)
);
\v_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFF4000"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => \^yaddr\(6),
I2 => \^yaddr\(5),
I3 => \^yaddr\(7),
I4 => \^yaddr\(8),
O => \plusOp__0\(8)
);
\v_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00400000FFFFFFFF"
)
port map (
I0 => \h_count_reg[9]_i_3_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \h_count_reg[9]_i_4_n_0\,
I3 => \^yaddr\(0),
I4 => \v_count_reg[9]_i_5_n_0\,
I5 => rst,
O => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000001000"
)
port map (
I0 => \^xaddr\(5),
I1 => \^xaddr\(6),
I2 => \^xaddr\(9),
I3 => \^xaddr\(8),
I4 => \^xaddr\(7),
I5 => \h_count_reg[9]_i_3_n_0\,
O => \v_count_reg[9]_i_2_n_0\
);
\v_count_reg[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"BFFFFFFF40000000"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => \^yaddr\(7),
I2 => \^yaddr\(5),
I3 => \^yaddr\(6),
I4 => \^yaddr\(8),
I5 => \^yaddr\(9),
O => \plusOp__0\(9)
);
\v_count_reg[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000000000000"
)
port map (
I0 => \^yaddr\(9),
I1 => \^xaddr\(7),
I2 => \^yaddr\(7),
I3 => \^yaddr\(8),
I4 => \^xaddr\(9),
I5 => \^xaddr\(8),
O => \v_count_reg[9]_i_4_n_0\
);
\v_count_reg[9]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000020"
)
port map (
I0 => \^yaddr\(3),
I1 => \^yaddr\(4),
I2 => \^yaddr\(2),
I3 => \^yaddr\(1),
I4 => \^yaddr\(6),
I5 => \^yaddr\(5),
O => \v_count_reg[9]_i_5_n_0\
);
\v_count_reg[9]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \^yaddr\(3),
I1 => \^yaddr\(1),
I2 => \^yaddr\(0),
I3 => \^yaddr\(2),
I4 => \^yaddr\(4),
O => \v_count_reg[9]_i_6_n_0\
);
\v_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(0),
Q => \^yaddr\(0),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(1),
Q => \^yaddr\(1),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(2),
Q => \^yaddr\(2),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(3),
Q => \^yaddr\(3),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(4),
Q => \^yaddr\(4),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(5),
Q => \^yaddr\(5),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(6),
Q => \^yaddr\(6),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(7),
Q => \^yaddr\(7),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(8),
Q => \^yaddr\(8),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(9),
Q => \^yaddr\(9),
R => \v_count_reg[9]_i_1_n_0\
);
vsync_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFBFFFFFFFF"
)
port map (
I0 => vsync_i_2_n_0,
I1 => \^yaddr\(1),
I2 => \^yaddr\(2),
I3 => \^yaddr\(9),
I4 => \^yaddr\(4),
I5 => rst,
O => vsync_i_1_n_0
);
vsync_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \^yaddr\(8),
I1 => \^yaddr\(6),
I2 => \^yaddr\(5),
I3 => \^yaddr\(7),
I4 => \^yaddr\(3),
O => vsync_i_2_n_0
);
vsync_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => vsync_i_1_n_0,
Q => vsync,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_reset_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_sync_reset_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_sync_reset_0_0 : entity is "system_vga_sync_reset_0_0,vga_sync_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_sync_reset_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_sync_reset_0_0 : entity is "vga_sync_reset,Vivado 2016.4";
end system_vga_sync_reset_0_0;
architecture STRUCTURE of system_vga_sync_reset_0_0 is
begin
U0: entity work.system_vga_sync_reset_0_0_vga_sync_reset
port map (
active => active,
clk => clk,
hsync => hsync,
rst => rst,
vsync => vsync,
xaddr(9 downto 0) => xaddr(9 downto 0),
yaddr(9 downto 0) => yaddr(9 downto 0)
);
end STRUCTURE;
| mit | df2af2afe0d0392bea824d03ac49c55f | 0.491359 | 2.73363 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_zybo_hdmi_0_0/system_zybo_hdmi_0_0_sim_netlist.vhdl | 1 | 129,348 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Feb 08 00:47:17 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Zybo-Open-Source-Video-IP-Toolbox/video_processing_examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_zybo_hdmi_0_0/system_zybo_hdmi_0_0_sim_netlist.vhdl
-- Design : system_zybo_hdmi_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zybo_hdmi_0_0_TMDS_encoder is
port (
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
rgb : in STD_LOGIC_VECTOR ( 7 downto 0 );
active : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
shift_blue : in STD_LOGIC_VECTOR ( 7 downto 0 );
\shift_clock_reg[5]\ : in STD_LOGIC;
clk_25 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_zybo_hdmi_0_0_TMDS_encoder : entity is "TMDS_encoder";
end system_zybo_hdmi_0_0_TMDS_encoder;
architecture STRUCTURE of system_zybo_hdmi_0_0_TMDS_encoder is
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \dc_bias[0]_i_1__1_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_2__1_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_3__1_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_4__1_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_5__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_1__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_2__1_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_3__1_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_4__1_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_5__1_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_6__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_7__1_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_8_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_9__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_10_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_11__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_12__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_13__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_14__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_15__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_1__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_2__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_3__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_4__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_5__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_6__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_7__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_8__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_9__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_10__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_11__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_12__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_13__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_14__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_15__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_16__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_17__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_18__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_19__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_1__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_20__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_21_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_22__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_23__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_24__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_25__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_26__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_27__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_28__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_29__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_2__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_30__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_31__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_32__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_33__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_3__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_4__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_5_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_6__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_7__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_8__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_9__1_n_0\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[0]\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[1]\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[2]\ : STD_LOGIC;
signal \encoded[0]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[1]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[1]_i_2_n_0\ : STD_LOGIC;
signal \encoded[2]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[2]_i_2_n_0\ : STD_LOGIC;
signal \encoded[3]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[3]_i_2_n_0\ : STD_LOGIC;
signal \encoded[4]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[4]_i_2_n_0\ : STD_LOGIC;
signal \encoded[5]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[5]_i_2_n_0\ : STD_LOGIC;
signal \encoded[6]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[6]_i_2__1_n_0\ : STD_LOGIC;
signal \encoded[7]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[7]_i_2__1_n_0\ : STD_LOGIC;
signal \encoded[8]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[9]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded_reg_n_0_[0]\ : STD_LOGIC;
signal \encoded_reg_n_0_[1]\ : STD_LOGIC;
signal \encoded_reg_n_0_[2]\ : STD_LOGIC;
signal \encoded_reg_n_0_[3]\ : STD_LOGIC;
signal \encoded_reg_n_0_[4]\ : STD_LOGIC;
signal \encoded_reg_n_0_[5]\ : STD_LOGIC;
signal \encoded_reg_n_0_[6]\ : STD_LOGIC;
signal \encoded_reg_n_0_[7]\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \dc_bias[0]_i_3__1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \dc_bias[0]_i_4__1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \dc_bias[1]_i_3__1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \dc_bias[1]_i_4__1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \dc_bias[1]_i_6__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \dc_bias[1]_i_7__1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \dc_bias[1]_i_9__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \dc_bias[2]_i_11__1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \dc_bias[2]_i_14__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \dc_bias[2]_i_15__0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \dc_bias[2]_i_7__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \dc_bias[2]_i_9__0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \dc_bias[3]_i_11__1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \dc_bias[3]_i_16__0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \dc_bias[3]_i_19__1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \dc_bias[3]_i_26__1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \dc_bias[3]_i_29__0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \encoded[1]_i_2\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \encoded[2]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \encoded[3]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \encoded[4]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \encoded[6]_i_2__1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \encoded[7]_i_2__1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \encoded[8]_i_1__1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \shift_blue[0]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \shift_blue[1]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \shift_blue[2]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \shift_blue[3]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \shift_blue[4]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \shift_blue[5]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \shift_blue[6]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \shift_blue[7]_i_1\ : label is "soft_lutpair11";
begin
SR(0) <= \^sr\(0);
\dc_bias[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9F90909F909F9F90"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_2__1_n_0\,
I2 => \dc_bias[3]_i_5_n_0\,
I3 => \dc_bias[2]_i_2__0_n_0\,
I4 => \dc_bias[0]_i_3__1_n_0\,
I5 => \dc_bias[0]_i_4__1_n_0\,
O => \dc_bias[0]_i_1__1_n_0\
);
\dc_bias[0]_i_2__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => \encoded[7]_i_2__1_n_0\,
I2 => \dc_bias[0]_i_5__0_n_0\,
I3 => rgb(1),
I4 => rgb(3),
O => \dc_bias[0]_i_2__1_n_0\
);
\dc_bias[0]_i_3__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => \encoded[3]_i_2_n_0\,
I1 => rgb(5),
I2 => rgb(0),
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(7),
O => \dc_bias[0]_i_3__1_n_0\
);
\dc_bias[0]_i_4__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb(2),
I1 => \dc_bias[3]_i_3__1_n_0\,
O => \dc_bias[0]_i_4__1_n_0\
);
\dc_bias[0]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6696969999696966"
)
port map (
I0 => rgb(6),
I1 => rgb(4),
I2 => \dc_bias[2]_i_13__0_n_0\,
I3 => \dc_bias[3]_i_13__0_n_0\,
I4 => \dc_bias[2]_i_12__0_n_0\,
I5 => \encoded[3]_i_2_n_0\,
O => \dc_bias[0]_i_5__0_n_0\
);
\dc_bias[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"C5C0CFCACFCAC5C0"
)
port map (
I0 => \dc_bias[2]_i_2__0_n_0\,
I1 => \dc_bias[1]_i_2__1_n_0\,
I2 => \dc_bias[3]_i_5_n_0\,
I3 => \dc_bias[1]_i_3__1_n_0\,
I4 => \dc_bias[1]_i_4__1_n_0\,
I5 => \dc_bias[1]_i_5__1_n_0\,
O => \dc_bias[1]_i_1__0_n_0\
);
\dc_bias[1]_i_2__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6F60606F606F6F60"
)
port map (
I0 => \dc_bias[1]_i_6__0_n_0\,
I1 => \dc_bias[1]_i_7__1_n_0\,
I2 => \dc_bias[3]_i_3__1_n_0\,
I3 => \dc_bias[1]_i_8_n_0\,
I4 => \dc_bias[1]_i_9__0_n_0\,
I5 => \dc_bias[3]_i_17__0_n_0\,
O => \dc_bias[1]_i_2__1_n_0\
);
\dc_bias[1]_i_3__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5695"
)
port map (
I0 => \dc_bias[1]_i_7__1_n_0\,
I1 => \dc_bias[0]_i_2__1_n_0\,
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias[3]_i_3__1_n_0\,
O => \dc_bias[1]_i_3__1_n_0\
);
\dc_bias[1]_i_4__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"D7BE2841"
)
port map (
I0 => rgb(2),
I1 => rgb(1),
I2 => rgb(0),
I3 => \dc_bias[3]_i_3__1_n_0\,
I4 => \dc_bias[2]_i_10_n_0\,
O => \dc_bias[1]_i_4__1_n_0\
);
\dc_bias[1]_i_5__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EB7D7DEB7D14147D"
)
port map (
I0 => rgb(7),
I1 => \dc_bias_reg_n_0_[0]\,
I2 => rgb(0),
I3 => rgb(5),
I4 => \encoded[3]_i_2_n_0\,
I5 => \dc_bias[0]_i_4__1_n_0\,
O => \dc_bias[1]_i_5__1_n_0\
);
\dc_bias[1]_i_6__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_2__1_n_0\,
O => \dc_bias[1]_i_6__0_n_0\
);
\dc_bias[1]_i_7__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => \dc_bias[3]_i_25__1_n_0\,
O => \dc_bias[1]_i_7__1_n_0\
);
\dc_bias[1]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"14D782BE82BE14D7"
)
port map (
I0 => rgb(0),
I1 => \dc_bias_reg_n_0_[0]\,
I2 => \dc_bias[3]_i_31__0_n_0\,
I3 => \dc_bias[0]_i_5__0_n_0\,
I4 => rgb(3),
I5 => rgb(1),
O => \dc_bias[1]_i_8_n_0\
);
\dc_bias[1]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"6A56566A"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => rgb(0),
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias[3]_i_3__1_n_0\,
I4 => \encoded[7]_i_2__1_n_0\,
O => \dc_bias[1]_i_9__0_n_0\
);
\dc_bias[2]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"9A5965A665A69A59"
)
port map (
I0 => \dc_bias[2]_i_8__1_n_0\,
I1 => \dc_bias[3]_i_3__1_n_0\,
I2 => rgb(7),
I3 => \encoded[6]_i_2__1_n_0\,
I4 => \dc_bias_reg_n_0_[1]\,
I5 => \dc_bias[2]_i_14__0_n_0\,
O => \dc_bias[2]_i_10_n_0\
);
\dc_bias[2]_i_11__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"82EBEB82"
)
port map (
I0 => rgb(7),
I1 => \dc_bias_reg_n_0_[0]\,
I2 => rgb(0),
I3 => rgb(5),
I4 => \encoded[3]_i_2_n_0\,
O => \dc_bias[2]_i_11__1_n_0\
);
\dc_bias[2]_i_12__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"022BBFFF"
)
port map (
I0 => \dc_bias[2]_i_15__0_n_0\,
I1 => rgb(0),
I2 => rgb(7),
I3 => \dc_bias[3]_i_29__0_n_0\,
I4 => \dc_bias[3]_i_12__1_n_0\,
O => \dc_bias[2]_i_12__0_n_0\
);
\dc_bias[2]_i_13__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"79E9EF7FFFFFFFFF"
)
port map (
I0 => rgb(7),
I1 => \dc_bias[3]_i_29__0_n_0\,
I2 => \encoded[3]_i_2_n_0\,
I3 => \dc_bias[2]_i_15__0_n_0\,
I4 => \dc_bias[3]_i_12__1_n_0\,
I5 => rgb(0),
O => \dc_bias[2]_i_13__0_n_0\
);
\dc_bias[2]_i_14__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => rgb(0),
I1 => \dc_bias_reg_n_0_[0]\,
O => \dc_bias[2]_i_14__0_n_0\
);
\dc_bias[2]_i_15__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb(3),
I1 => rgb(2),
I2 => rgb(1),
O => \dc_bias[2]_i_15__0_n_0\
);
\dc_bias[2]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C5C0CFCACFCAC5C0"
)
port map (
I0 => \dc_bias[2]_i_2__0_n_0\,
I1 => \dc_bias[2]_i_3__1_n_0\,
I2 => \dc_bias[3]_i_5_n_0\,
I3 => \dc_bias[2]_i_4__1_n_0\,
I4 => \dc_bias[2]_i_5__1_n_0\,
I5 => \dc_bias[2]_i_6__1_n_0\,
O => \dc_bias[2]_i_1__1_n_0\
);
\dc_bias[2]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"999999A999A9AAAA"
)
port map (
I0 => p_1_in,
I1 => \dc_bias[3]_i_21_n_0\,
I2 => \dc_bias[3]_i_20__0_n_0\,
I3 => \dc_bias[3]_i_19__1_n_0\,
I4 => \dc_bias[3]_i_18__0_n_0\,
I5 => \dc_bias[3]_i_17__0_n_0\,
O => \dc_bias[2]_i_2__0_n_0\
);
\dc_bias[2]_i_3__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6699A5A566995A5A"
)
port map (
I0 => \dc_bias_reg_n_0_[2]\,
I1 => \dc_bias[3]_i_14__0_n_0\,
I2 => \dc_bias[3]_i_9__1_n_0\,
I3 => \dc_bias[3]_i_15__1_n_0\,
I4 => \dc_bias[3]_i_3__1_n_0\,
I5 => \dc_bias[3]_i_8__1_n_0\,
O => \dc_bias[2]_i_3__1_n_0\
);
\dc_bias[2]_i_4__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"4BB4B44B"
)
port map (
I0 => \dc_bias[3]_i_25__1_n_0\,
I1 => \dc_bias_reg_n_0_[1]\,
I2 => \dc_bias_reg_n_0_[2]\,
I3 => \dc_bias[3]_i_14__0_n_0\,
I4 => \dc_bias[3]_i_26__1_n_0\,
O => \dc_bias[2]_i_4__1_n_0\
);
\dc_bias[2]_i_5__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"75F710518A08EFAE"
)
port map (
I0 => \dc_bias[2]_i_7__0_n_0\,
I1 => \dc_bias[3]_i_3__1_n_0\,
I2 => rgb(7),
I3 => \encoded[6]_i_2__1_n_0\,
I4 => \dc_bias[2]_i_8__1_n_0\,
I5 => \dc_bias[2]_i_9__0_n_0\,
O => \dc_bias[2]_i_5__1_n_0\
);
\dc_bias[2]_i_6__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"177E777777777E17"
)
port map (
I0 => \dc_bias[2]_i_10_n_0\,
I1 => \dc_bias[2]_i_11__1_n_0\,
I2 => \dc_bias[0]_i_3__1_n_0\,
I3 => \encoded[1]_i_2_n_0\,
I4 => \dc_bias[3]_i_3__1_n_0\,
I5 => rgb(2),
O => \dc_bias[2]_i_6__1_n_0\
);
\dc_bias[2]_i_7__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => \dc_bias_reg_n_0_[0]\,
I2 => rgb(0),
O => \dc_bias[2]_i_7__0_n_0\
);
\dc_bias[2]_i_8__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2DB4B4B42D2D2DB4"
)
port map (
I0 => rgb(4),
I1 => rgb(5),
I2 => \encoded[3]_i_2_n_0\,
I3 => \dc_bias[2]_i_12__0_n_0\,
I4 => \dc_bias[3]_i_13__0_n_0\,
I5 => \dc_bias[2]_i_13__0_n_0\,
O => \dc_bias[2]_i_8__1_n_0\
);
\dc_bias[2]_i_9__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA95"
)
port map (
I0 => \dc_bias_reg_n_0_[2]\,
I1 => rgb(0),
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[2]_i_9__0_n_0\
);
\dc_bias[3]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active,
O => \^sr\(0)
);
\dc_bias[3]_i_10__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"69FFFF69FF6969FF"
)
port map (
I0 => rgb(1),
I1 => rgb(2),
I2 => rgb(3),
I3 => rgb(0),
I4 => rgb(7),
I5 => \dc_bias[3]_i_29__0_n_0\,
O => \dc_bias[3]_i_10__1_n_0\
);
\dc_bias[3]_i_11__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"17717117"
)
port map (
I0 => rgb(0),
I1 => rgb(7),
I2 => rgb(6),
I3 => rgb(5),
I4 => rgb(4),
O => \dc_bias[3]_i_11__1_n_0\
);
\dc_bias[3]_i_12__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"171717E817E8E8E8"
)
port map (
I0 => rgb(3),
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(5),
I4 => rgb(4),
I5 => rgb(6),
O => \dc_bias[3]_i_12__1_n_0\
);
\dc_bias[3]_i_13__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"171717FF17FFFFFF"
)
port map (
I0 => rgb(3),
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(5),
I4 => rgb(4),
I5 => rgb(6),
O => \dc_bias[3]_i_13__0_n_0\
);
\dc_bias[3]_i_14__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4DDD444D444D2444"
)
port map (
I0 => \dc_bias[3]_i_28__0_n_0\,
I1 => \dc_bias[3]_i_30__0_n_0\,
I2 => \dc_bias[0]_i_5__0_n_0\,
I3 => rgb(0),
I4 => \dc_bias[3]_i_31__0_n_0\,
I5 => \dc_bias[3]_i_19__1_n_0\,
O => \dc_bias[3]_i_14__0_n_0\
);
\dc_bias[3]_i_15__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"ECFE8FC88FC8ECFE"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias_reg_n_0_[1]\,
I2 => \dc_bias[3]_i_19__1_n_0\,
I3 => \dc_bias[3]_i_20__0_n_0\,
I4 => \dc_bias[3]_i_18__0_n_0\,
I5 => \dc_bias[3]_i_17__0_n_0\,
O => \dc_bias[3]_i_15__1_n_0\
);
\dc_bias[3]_i_16__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => \dc_bias_reg_n_0_[2]\,
I2 => \dc_bias_reg_n_0_[0]\,
I3 => p_1_in,
O => \dc_bias[3]_i_16__0_n_0\
);
\dc_bias[3]_i_17__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"D22D4BB42DD2B44B"
)
port map (
I0 => rgb(3),
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(0),
I4 => \dc_bias[3]_i_3__1_n_0\,
I5 => \dc_bias[3]_i_28__0_n_0\,
O => \dc_bias[3]_i_17__0_n_0\
);
\dc_bias[3]_i_18__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"1D8B8B1D8B1D1D8B"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => \encoded[7]_i_2__1_n_0\,
I2 => rgb(0),
I3 => rgb(6),
I4 => rgb(4),
I5 => \encoded[3]_i_2_n_0\,
O => \dc_bias[3]_i_18__0_n_0\
);
\dc_bias[3]_i_19__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb(3),
I1 => rgb(1),
I2 => rgb(0),
O => \dc_bias[3]_i_19__1_n_0\
);
\dc_bias[3]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1DFF1D001DFF1DFF"
)
port map (
I0 => \dc_bias[3]_i_2__1_n_0\,
I1 => \dc_bias[3]_i_3__1_n_0\,
I2 => \dc_bias[3]_i_4__1_n_0\,
I3 => \dc_bias[3]_i_5_n_0\,
I4 => \dc_bias[3]_i_6__1_n_0\,
I5 => \dc_bias[3]_i_7__1_n_0\,
O => \dc_bias[3]_i_1__1_n_0\
);
\dc_bias[3]_i_20__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => \encoded[3]_i_2_n_0\,
I1 => rgb(4),
I2 => rgb(6),
I3 => \encoded[7]_i_2__1_n_0\,
I4 => rgb(0),
O => \dc_bias[3]_i_20__0_n_0\
);
\dc_bias[3]_i_21\: unisim.vcomponents.LUT6
generic map(
INIT => X"A20808A2208A8A20"
)
port map (
I0 => \dc_bias[3]_i_28__0_n_0\,
I1 => rgb(3),
I2 => rgb(2),
I3 => rgb(1),
I4 => rgb(0),
I5 => \dc_bias[3]_i_3__1_n_0\,
O => \dc_bias[3]_i_21_n_0\
);
\dc_bias[3]_i_22__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBABA22BA22BA22"
)
port map (
I0 => \dc_bias_reg_n_0_[2]\,
I1 => \dc_bias[3]_i_32__0_n_0\,
I2 => \dc_bias[3]_i_33__0_n_0\,
I3 => \dc_bias_reg_n_0_[1]\,
I4 => \dc_bias_reg_n_0_[0]\,
I5 => rgb(0),
O => \dc_bias[3]_i_22__1_n_0\
);
\dc_bias[3]_i_23__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFEFFFFEF"
)
port map (
I0 => \dc_bias[2]_i_10_n_0\,
I1 => \dc_bias[0]_i_3__1_n_0\,
I2 => \encoded[1]_i_2_n_0\,
I3 => \dc_bias[3]_i_3__1_n_0\,
I4 => rgb(2),
I5 => \dc_bias[2]_i_11__1_n_0\,
O => \dc_bias[3]_i_23__0_n_0\
);
\dc_bias[3]_i_24__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE7810081000000"
)
port map (
I0 => rgb(2),
I1 => \dc_bias[3]_i_3__1_n_0\,
I2 => \encoded[1]_i_2_n_0\,
I3 => \dc_bias[0]_i_3__1_n_0\,
I4 => \dc_bias[2]_i_11__1_n_0\,
I5 => \dc_bias[2]_i_10_n_0\,
O => \dc_bias[3]_i_24__1_n_0\
);
\dc_bias[3]_i_25__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"188EE771E771188E"
)
port map (
I0 => \dc_bias[3]_i_19__1_n_0\,
I1 => \dc_bias[3]_i_31__0_n_0\,
I2 => rgb(0),
I3 => \dc_bias[0]_i_5__0_n_0\,
I4 => \dc_bias[3]_i_30__0_n_0\,
I5 => \dc_bias[3]_i_28__0_n_0\,
O => \dc_bias[3]_i_25__1_n_0\
);
\dc_bias[3]_i_26__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"9990F999"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => \dc_bias[3]_i_25__1_n_0\,
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias[0]_i_2__1_n_0\,
I4 => \dc_bias[3]_i_3__1_n_0\,
O => \dc_bias[3]_i_26__1_n_0\
);
\dc_bias[3]_i_27__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA696955559696AA"
)
port map (
I0 => \dc_bias[3]_i_28__0_n_0\,
I1 => \encoded[7]_i_2__1_n_0\,
I2 => \dc_bias[3]_i_3__1_n_0\,
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(0),
I5 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[3]_i_27__1_n_0\
);
\dc_bias[3]_i_28__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"28882228BEEEBBBE"
)
port map (
I0 => \encoded[4]_i_2_n_0\,
I1 => \encoded[5]_i_2_n_0\,
I2 => \dc_bias[2]_i_12__0_n_0\,
I3 => \dc_bias[3]_i_13__0_n_0\,
I4 => \dc_bias[2]_i_13__0_n_0\,
I5 => \encoded[6]_i_2__1_n_0\,
O => \dc_bias[3]_i_28__0_n_0\
);
\dc_bias[3]_i_29__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb(6),
I1 => rgb(5),
I2 => rgb(4),
O => \dc_bias[3]_i_29__0_n_0\
);
\dc_bias[3]_i_2__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"24DB"
)
port map (
I0 => \dc_bias[3]_i_8__1_n_0\,
I1 => \dc_bias[3]_i_9__1_n_0\,
I2 => \dc_bias_reg_n_0_[2]\,
I3 => p_1_in,
O => \dc_bias[3]_i_2__1_n_0\
);
\dc_bias[3]_i_30__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2BD400FFFF002BD4"
)
port map (
I0 => \dc_bias[2]_i_13__0_n_0\,
I1 => \dc_bias[3]_i_13__0_n_0\,
I2 => \dc_bias[2]_i_12__0_n_0\,
I3 => \encoded[1]_i_2_n_0\,
I4 => rgb(2),
I5 => rgb(3),
O => \dc_bias[3]_i_30__0_n_0\
);
\dc_bias[3]_i_31__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"55F5F5FFAE8A8A08"
)
port map (
I0 => \dc_bias[3]_i_13__0_n_0\,
I1 => rgb(0),
I2 => \dc_bias[3]_i_12__1_n_0\,
I3 => \dc_bias[3]_i_11__1_n_0\,
I4 => \dc_bias[3]_i_10__1_n_0\,
I5 => \encoded[7]_i_2__1_n_0\,
O => \dc_bias[3]_i_31__0_n_0\
);
\dc_bias[3]_i_32__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"01B00071B20001B0"
)
port map (
I0 => rgb(6),
I1 => rgb(7),
I2 => \dc_bias[3]_i_3__1_n_0\,
I3 => \encoded[3]_i_2_n_0\,
I4 => rgb(5),
I5 => rgb(4),
O => \dc_bias[3]_i_32__0_n_0\
);
\dc_bias[3]_i_33__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9208000059591049"
)
port map (
I0 => \encoded[3]_i_2_n_0\,
I1 => rgb(4),
I2 => rgb(5),
I3 => rgb(6),
I4 => rgb(7),
I5 => \dc_bias[3]_i_3__1_n_0\,
O => \dc_bias[3]_i_33__0_n_0\
);
\dc_bias[3]_i_3__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2B023F03FFBFFFFF"
)
port map (
I0 => \encoded[7]_i_2__1_n_0\,
I1 => \dc_bias[3]_i_10__1_n_0\,
I2 => \dc_bias[3]_i_11__1_n_0\,
I3 => \dc_bias[3]_i_12__1_n_0\,
I4 => rgb(0),
I5 => \dc_bias[3]_i_13__0_n_0\,
O => \dc_bias[3]_i_3__1_n_0\
);
\dc_bias[3]_i_4__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"65A6"
)
port map (
I0 => \dc_bias[2]_i_2__0_n_0\,
I1 => \dc_bias_reg_n_0_[2]\,
I2 => \dc_bias[3]_i_14__0_n_0\,
I3 => \dc_bias[3]_i_15__1_n_0\,
O => \dc_bias[3]_i_4__1_n_0\
);
\dc_bias[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAEAAAAABEABAA"
)
port map (
I0 => \dc_bias[3]_i_16__0_n_0\,
I1 => \dc_bias[3]_i_17__0_n_0\,
I2 => \dc_bias[3]_i_18__0_n_0\,
I3 => \dc_bias[3]_i_19__1_n_0\,
I4 => \dc_bias[3]_i_20__0_n_0\,
I5 => \dc_bias[3]_i_21_n_0\,
O => \dc_bias[3]_i_5_n_0\
);
\dc_bias[3]_i_6__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8228822828288228"
)
port map (
I0 => \dc_bias[2]_i_2__0_n_0\,
I1 => p_1_in,
I2 => \dc_bias[3]_i_22__1_n_0\,
I3 => \dc_bias[3]_i_23__0_n_0\,
I4 => \dc_bias[2]_i_5__1_n_0\,
I5 => \dc_bias[3]_i_24__1_n_0\,
O => \dc_bias[3]_i_6__1_n_0\
);
\dc_bias[3]_i_7__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF4F4F0FBFFFFF4"
)
port map (
I0 => \dc_bias[3]_i_25__1_n_0\,
I1 => \dc_bias_reg_n_0_[1]\,
I2 => \dc_bias[2]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_26__1_n_0\,
I4 => \dc_bias_reg_n_0_[2]\,
I5 => \dc_bias[3]_i_14__0_n_0\,
O => \dc_bias[3]_i_7__1_n_0\
);
\dc_bias[3]_i_8__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"08A28A20AEFBEFBA"
)
port map (
I0 => \dc_bias[3]_i_27__1_n_0\,
I1 => rgb(3),
I2 => rgb(2),
I3 => \encoded[1]_i_2_n_0\,
I4 => \dc_bias[3]_i_3__1_n_0\,
I5 => \dc_bias[1]_i_8_n_0\,
O => \dc_bias[3]_i_8__1_n_0\
);
\dc_bias[3]_i_9__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000099F099FFFFF"
)
port map (
I0 => \encoded[7]_i_2__1_n_0\,
I1 => \dc_bias[3]_i_3__1_n_0\,
I2 => rgb(0),
I3 => \dc_bias_reg_n_0_[0]\,
I4 => \dc_bias_reg_n_0_[1]\,
I5 => \dc_bias[3]_i_28__0_n_0\,
O => \dc_bias[3]_i_9__1_n_0\
);
\dc_bias_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[0]_i_1__1_n_0\,
Q => \dc_bias_reg_n_0_[0]\,
R => \^sr\(0)
);
\dc_bias_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[1]_i_1__0_n_0\,
Q => \dc_bias_reg_n_0_[1]\,
R => \^sr\(0)
);
\dc_bias_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[2]_i_1__1_n_0\,
Q => \dc_bias_reg_n_0_[2]\,
R => \^sr\(0)
);
\dc_bias_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[3]_i_1__1_n_0\,
Q => p_1_in,
R => \^sr\(0)
);
\encoded[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6F6FAF5F6060A050"
)
port map (
I0 => rgb(0),
I1 => \dc_bias[3]_i_3__1_n_0\,
I2 => active,
I3 => \dc_bias[2]_i_2__0_n_0\,
I4 => \dc_bias[3]_i_5_n_0\,
I5 => hsync,
O => \encoded[0]_i_1__1_n_0\
);
\encoded[1]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF7B33B7CC480084"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => active,
I2 => \dc_bias[2]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_5_n_0\,
I4 => \encoded[1]_i_2_n_0\,
I5 => hsync,
O => \encoded[1]_i_1__1_n_0\
);
\encoded[1]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb(0),
I1 => rgb(1),
O => \encoded[1]_i_2_n_0\
);
\encoded[2]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"880C44C0BB3F77F3"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => active,
I2 => \dc_bias[2]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_5_n_0\,
I4 => \encoded[2]_i_2_n_0\,
I5 => hsync,
O => \encoded[2]_i_1__1_n_0\
);
\encoded[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb(2),
I1 => rgb(1),
I2 => rgb(0),
O => \encoded[2]_i_2_n_0\
);
\encoded[3]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"33B7FF7B0084CC48"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => active,
I2 => \dc_bias[2]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_5_n_0\,
I4 => \encoded[3]_i_2_n_0\,
I5 => hsync,
O => \encoded[3]_i_1__1_n_0\
);
\encoded[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => rgb(3),
I1 => rgb(0),
I2 => rgb(1),
I3 => rgb(2),
O => \encoded[3]_i_2_n_0\
);
\encoded[4]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"44C0880C77F3BB3F"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => active,
I2 => \dc_bias[2]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_5_n_0\,
I4 => \encoded[4]_i_2_n_0\,
I5 => hsync,
O => \encoded[4]_i_1__1_n_0\
);
\encoded[4]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => rgb(4),
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(0),
I4 => rgb(3),
O => \encoded[4]_i_2_n_0\
);
\encoded[5]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"33B7FF7B0084CC48"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => active,
I2 => \dc_bias[2]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_5_n_0\,
I4 => \encoded[5]_i_2_n_0\,
I5 => hsync,
O => \encoded[5]_i_1__1_n_0\
);
\encoded[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669699669969669"
)
port map (
I0 => rgb(2),
I1 => rgb(1),
I2 => rgb(0),
I3 => rgb(3),
I4 => rgb(5),
I5 => rgb(4),
O => \encoded[5]_i_2_n_0\
);
\encoded[6]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"880C44C0BB3F77F3"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => active,
I2 => \dc_bias[2]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_5_n_0\,
I4 => \encoded[6]_i_2__1_n_0\,
I5 => hsync,
O => \encoded[6]_i_1__1_n_0\
);
\encoded[6]_i_2__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \encoded[3]_i_2_n_0\,
I1 => rgb(4),
I2 => rgb(5),
I3 => rgb(6),
O => \encoded[6]_i_2__1_n_0\
);
\encoded[7]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF337BB7CC004884"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => active,
I2 => \dc_bias[2]_i_2__0_n_0\,
I3 => \encoded[7]_i_2__1_n_0\,
I4 => \dc_bias[3]_i_5_n_0\,
I5 => hsync,
O => \encoded[7]_i_1__1_n_0\
);
\encoded[7]_i_2__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => rgb(7),
I1 => rgb(6),
I2 => rgb(5),
I3 => rgb(4),
I4 => \encoded[3]_i_2_n_0\,
O => \encoded[7]_i_2__1_n_0\
);
\encoded[8]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => active,
I2 => hsync,
O => \encoded[8]_i_1__1_n_0\
);
\encoded[9]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C5FFC500C500C5FF"
)
port map (
I0 => \dc_bias[2]_i_2__0_n_0\,
I1 => \dc_bias[3]_i_3__1_n_0\,
I2 => \dc_bias[3]_i_5_n_0\,
I3 => active,
I4 => hsync,
I5 => vsync,
O => \encoded[9]_i_1__1_n_0\
);
\encoded_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[0]_i_1__1_n_0\,
Q => \encoded_reg_n_0_[0]\,
R => '0'
);
\encoded_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[1]_i_1__1_n_0\,
Q => \encoded_reg_n_0_[1]\,
R => '0'
);
\encoded_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[2]_i_1__1_n_0\,
Q => \encoded_reg_n_0_[2]\,
R => '0'
);
\encoded_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[3]_i_1__1_n_0\,
Q => \encoded_reg_n_0_[3]\,
R => '0'
);
\encoded_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[4]_i_1__1_n_0\,
Q => \encoded_reg_n_0_[4]\,
R => '0'
);
\encoded_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[5]_i_1__1_n_0\,
Q => \encoded_reg_n_0_[5]\,
R => '0'
);
\encoded_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[6]_i_1__1_n_0\,
Q => \encoded_reg_n_0_[6]\,
R => '0'
);
\encoded_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[7]_i_1__1_n_0\,
Q => \encoded_reg_n_0_[7]\,
R => '0'
);
\encoded_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[8]_i_1__1_n_0\,
Q => Q(0),
R => '0'
);
\encoded_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[9]_i_1__1_n_0\,
Q => Q(1),
R => '0'
);
\shift_blue[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_blue(0),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[0]\,
O => D(0)
);
\shift_blue[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_blue(1),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[1]\,
O => D(1)
);
\shift_blue[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_blue(2),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[2]\,
O => D(2)
);
\shift_blue[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_blue(3),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[3]\,
O => D(3)
);
\shift_blue[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_blue(4),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[4]\,
O => D(4)
);
\shift_blue[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_blue(5),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[5]\,
O => D(5)
);
\shift_blue[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_blue(6),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[6]\,
O => D(6)
);
\shift_blue[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_blue(7),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[7]\,
O => D(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zybo_hdmi_0_0_TMDS_encoder_0 is
port (
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
rgb : in STD_LOGIC_VECTOR ( 7 downto 0 );
active : in STD_LOGIC;
shift_green : in STD_LOGIC_VECTOR ( 7 downto 0 );
\shift_clock_reg[5]\ : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
clk_25 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_zybo_hdmi_0_0_TMDS_encoder_0 : entity is "TMDS_encoder";
end system_zybo_hdmi_0_0_TMDS_encoder_0;
architecture STRUCTURE of system_zybo_hdmi_0_0_TMDS_encoder_0 is
signal \dc_bias[0]_i_1__0_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_2__0_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_3__0_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_4__0_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_5__1_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_6_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_7_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_1_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_2__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_3__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_4__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_5_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_6__1_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_7__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_8__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_9_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_10__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_11__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_1__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_2__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_3__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_4_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_5__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_6__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_7_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_8__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_9_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_10__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_11__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_12__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_13__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_14__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_15__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_16_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_17_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_18__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_19__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_1__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_20_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_21__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_22__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_23__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_24__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_25__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_26__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_27__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_28_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_29_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_2__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_30_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_31_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_32_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_33_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_34_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_3__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_4__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_5__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_6__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_7__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_8__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_9__0_n_0\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[0]\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[1]\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[2]\ : STD_LOGIC;
signal \encoded[0]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[1]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[2]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[3]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[4]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[5]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[6]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[6]_i_2__0_n_0\ : STD_LOGIC;
signal \encoded[7]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[7]_i_2_n_0\ : STD_LOGIC;
signal \encoded[7]_i_3__0_n_0\ : STD_LOGIC;
signal \encoded[8]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[8]_i_2_n_0\ : STD_LOGIC;
signal \encoded[8]_i_3_n_0\ : STD_LOGIC;
signal \encoded[8]_i_4_n_0\ : STD_LOGIC;
signal \encoded[8]_i_5_n_0\ : STD_LOGIC;
signal \encoded[8]_i_6_n_0\ : STD_LOGIC;
signal \encoded[8]_i_7_n_0\ : STD_LOGIC;
signal \encoded[9]_i_1_n_0\ : STD_LOGIC;
signal \encoded[9]_i_2__0_n_0\ : STD_LOGIC;
signal \encoded_reg_n_0_[0]\ : STD_LOGIC;
signal \encoded_reg_n_0_[1]\ : STD_LOGIC;
signal \encoded_reg_n_0_[2]\ : STD_LOGIC;
signal \encoded_reg_n_0_[3]\ : STD_LOGIC;
signal \encoded_reg_n_0_[4]\ : STD_LOGIC;
signal \encoded_reg_n_0_[5]\ : STD_LOGIC;
signal \encoded_reg_n_0_[6]\ : STD_LOGIC;
signal \encoded_reg_n_0_[7]\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \dc_bias[0]_i_2__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \dc_bias[0]_i_3__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \dc_bias[0]_i_4__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \dc_bias[0]_i_5__1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \dc_bias[0]_i_6\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \dc_bias[0]_i_7\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \dc_bias[1]_i_3__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \dc_bias[1]_i_8__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \dc_bias[2]_i_10__1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \dc_bias[2]_i_11__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \dc_bias[2]_i_8__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \dc_bias[2]_i_9\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \dc_bias[3]_i_11__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \dc_bias[3]_i_12__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \dc_bias[3]_i_13__1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \dc_bias[3]_i_14__1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \dc_bias[3]_i_15__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \dc_bias[3]_i_16\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \dc_bias[3]_i_18__1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \dc_bias[3]_i_22__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \dc_bias[3]_i_23__1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \dc_bias[3]_i_24__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \dc_bias[3]_i_2__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \dc_bias[3]_i_33\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \dc_bias[3]_i_7__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \dc_bias[3]_i_8__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \encoded[0]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \encoded[1]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \encoded[2]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \encoded[4]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \encoded[5]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \encoded[6]_i_2__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \encoded[7]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \encoded[7]_i_2\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \encoded[7]_i_3__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \encoded[8]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \encoded[8]_i_4\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \encoded[8]_i_7\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \shift_green[0]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \shift_green[1]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \shift_green[2]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \shift_green[3]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \shift_green[4]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \shift_green[5]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \shift_green[6]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \shift_green[7]_i_1\ : label is "soft_lutpair34";
begin
\dc_bias[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6F60606F606F6F60"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_2__0_n_0\,
I2 => \dc_bias[3]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_5__1_n_0\,
I4 => \dc_bias[0]_i_3__0_n_0\,
I5 => \dc_bias[0]_i_4__0_n_0\,
O => \dc_bias[0]_i_1__0_n_0\
);
\dc_bias[0]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => \dc_bias[0]_i_5__1_n_0\,
I1 => rgb(0),
I2 => \dc_bias[0]_i_6_n_0\,
I3 => \dc_bias[0]_i_7_n_0\,
I4 => rgb(6),
O => \dc_bias[0]_i_2__0_n_0\
);
\dc_bias[0]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => \encoded[6]_i_2__0_n_0\,
I1 => rgb(5),
I2 => rgb(0),
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(7),
O => \dc_bias[0]_i_3__0_n_0\
);
\dc_bias[0]_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb(2),
I1 => \encoded[8]_i_2_n_0\,
O => \dc_bias[0]_i_4__0_n_0\
);
\dc_bias[0]_i_5__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb(3),
I1 => rgb(1),
I2 => rgb(0),
O => \dc_bias[0]_i_5__1_n_0\
);
\dc_bias[0]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => rgb(7),
I1 => \encoded[6]_i_2__0_n_0\,
I2 => rgb(6),
I3 => rgb(5),
I4 => rgb(4),
O => \dc_bias[0]_i_6_n_0\
);
\dc_bias[0]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => rgb(4),
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(0),
I4 => rgb(3),
O => \dc_bias[0]_i_7_n_0\
);
\dc_bias[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \dc_bias[1]_i_2__0_n_0\,
I1 => \dc_bias[3]_i_2__0_n_0\,
I2 => \dc_bias[1]_i_3__0_n_0\,
I3 => \dc_bias[3]_i_5__1_n_0\,
I4 => \dc_bias[1]_i_4__0_n_0\,
O => \dc_bias[1]_i_1_n_0\
);
\dc_bias[1]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"960096FF96FF9600"
)
port map (
I0 => \dc_bias[1]_i_5_n_0\,
I1 => \dc_bias[1]_i_6__1_n_0\,
I2 => \dc_bias[1]_i_7__0_n_0\,
I3 => \encoded[8]_i_2_n_0\,
I4 => \dc_bias[1]_i_8__0_n_0\,
I5 => \dc_bias[2]_i_10__1_n_0\,
O => \dc_bias[1]_i_2__0_n_0\
);
\dc_bias[1]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"5965"
)
port map (
I0 => \dc_bias[2]_i_10__1_n_0\,
I1 => \encoded[8]_i_2_n_0\,
I2 => \dc_bias[0]_i_2__0_n_0\,
I3 => \dc_bias_reg_n_0_[0]\,
O => \dc_bias[1]_i_3__0_n_0\
);
\dc_bias[1]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"56955965A96AA69A"
)
port map (
I0 => \dc_bias[3]_i_11__0_n_0\,
I1 => \dc_bias[0]_i_3__0_n_0\,
I2 => rgb(2),
I3 => \encoded[8]_i_2_n_0\,
I4 => \dc_bias[2]_i_11__0_n_0\,
I5 => \dc_bias[3]_i_12__0_n_0\,
O => \dc_bias[1]_i_4__0_n_0\
);
\dc_bias[1]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"066090096FF6F99F"
)
port map (
I0 => rgb(6),
I1 => \dc_bias[0]_i_7_n_0\,
I2 => \dc_bias[1]_i_9_n_0\,
I3 => \dc_bias[0]_i_6_n_0\,
I4 => \encoded[8]_i_2_n_0\,
I5 => \dc_bias[0]_i_5__1_n_0\,
O => \dc_bias[1]_i_5_n_0\
);
\dc_bias[1]_i_6__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"556969AAAA969655"
)
port map (
I0 => \dc_bias[3]_i_27__0_n_0\,
I1 => \dc_bias[0]_i_6_n_0\,
I2 => \encoded[8]_i_2_n_0\,
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(0),
I5 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[1]_i_6__1_n_0\
);
\dc_bias[1]_i_7__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9C3939399C9C9C39"
)
port map (
I0 => rgb(2),
I1 => \dc_bias[2]_i_11__0_n_0\,
I2 => rgb(3),
I3 => \dc_bias[3]_i_30_n_0\,
I4 => \encoded[8]_i_6_n_0\,
I5 => \dc_bias[3]_i_31_n_0\,
O => \dc_bias[1]_i_7__0_n_0\
);
\dc_bias[1]_i_8__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_2__0_n_0\,
O => \dc_bias[1]_i_8__0_n_0\
);
\dc_bias[1]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb(0),
I1 => \dc_bias_reg_n_0_[0]\,
O => \dc_bias[1]_i_9_n_0\
);
\dc_bias[2]_i_10__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => \dc_bias[3]_i_10__0_n_0\,
O => \dc_bias[2]_i_10__1_n_0\
);
\dc_bias[2]_i_11__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb(0),
I1 => rgb(1),
O => \dc_bias[2]_i_11__0_n_0\
);
\dc_bias[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"B888B8BBB8BBB888"
)
port map (
I0 => \dc_bias[2]_i_2__1_n_0\,
I1 => \dc_bias[3]_i_2__0_n_0\,
I2 => \dc_bias[2]_i_3__0_n_0\,
I3 => \dc_bias[3]_i_5__1_n_0\,
I4 => \dc_bias[2]_i_4_n_0\,
I5 => \dc_bias[2]_i_5__0_n_0\,
O => \dc_bias[2]_i_1__0_n_0\
);
\dc_bias[2]_i_2__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"96FF9600960096FF"
)
port map (
I0 => \dc_bias_reg_n_0_[2]\,
I1 => \dc_bias[2]_i_6__0_n_0\,
I2 => \dc_bias[2]_i_7_n_0\,
I3 => \encoded[8]_i_2_n_0\,
I4 => \dc_bias[2]_i_8__0_n_0\,
I5 => \dc_bias[2]_i_9_n_0\,
O => \dc_bias[2]_i_2__1_n_0\
);
\dc_bias[2]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"04DFFB20FB2004DF"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_2__0_n_0\,
I2 => \encoded[8]_i_2_n_0\,
I3 => \dc_bias[2]_i_10__1_n_0\,
I4 => \dc_bias[3]_i_23__1_n_0\,
I5 => \dc_bias[2]_i_8__0_n_0\,
O => \dc_bias[2]_i_3__0_n_0\
);
\dc_bias[2]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"711818188EE7E7E7"
)
port map (
I0 => \dc_bias[3]_i_16_n_0\,
I1 => \dc_bias[3]_i_17_n_0\,
I2 => \dc_bias_reg_n_0_[1]\,
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(0),
I5 => \dc_bias_reg_n_0_[2]\,
O => \dc_bias[2]_i_4_n_0\
);
\dc_bias[2]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB2BB2BBBBBDDBBB"
)
port map (
I0 => \dc_bias[3]_i_11__0_n_0\,
I1 => \dc_bias[3]_i_12__0_n_0\,
I2 => \dc_bias[2]_i_11__0_n_0\,
I3 => \encoded[8]_i_2_n_0\,
I4 => rgb(2),
I5 => \dc_bias[0]_i_3__0_n_0\,
O => \dc_bias[2]_i_5__0_n_0\
);
\dc_bias[2]_i_6__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"01151501577F7F57"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => rgb(0),
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias[0]_i_6_n_0\,
I4 => \encoded[8]_i_2_n_0\,
I5 => \dc_bias[3]_i_27__0_n_0\,
O => \dc_bias[2]_i_6__0_n_0\
);
\dc_bias[2]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"802AA802EABFFEAB"
)
port map (
I0 => \dc_bias[1]_i_5_n_0\,
I1 => \encoded[8]_i_2_n_0\,
I2 => rgb(3),
I3 => \dc_bias[2]_i_11__0_n_0\,
I4 => rgb(2),
I5 => \dc_bias[1]_i_6__1_n_0\,
O => \dc_bias[2]_i_7_n_0\
);
\dc_bias[2]_i_8__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \dc_bias_reg_n_0_[2]\,
I1 => \dc_bias[3]_i_9__0_n_0\,
O => \dc_bias[2]_i_8__0_n_0\
);
\dc_bias[2]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"2B22"
)
port map (
I0 => \dc_bias[3]_i_10__0_n_0\,
I1 => \dc_bias_reg_n_0_[1]\,
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias[0]_i_2__0_n_0\,
O => \dc_bias[2]_i_9_n_0\
);
\dc_bias[3]_i_10__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"188EE771E771188E"
)
port map (
I0 => \dc_bias[0]_i_5__1_n_0\,
I1 => \dc_bias[3]_i_29_n_0\,
I2 => rgb(0),
I3 => \dc_bias[3]_i_28_n_0\,
I4 => \dc_bias[3]_i_27__0_n_0\,
I5 => \dc_bias[1]_i_7__0_n_0\,
O => \dc_bias[3]_i_10__0_n_0\
);
\dc_bias[3]_i_11__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696969"
)
port map (
I0 => \dc_bias[3]_i_16_n_0\,
I1 => \dc_bias[3]_i_17_n_0\,
I2 => \dc_bias_reg_n_0_[1]\,
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(0),
O => \dc_bias[3]_i_11__0_n_0\
);
\dc_bias[3]_i_12__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"82EBEB82"
)
port map (
I0 => rgb(7),
I1 => \dc_bias_reg_n_0_[0]\,
I2 => rgb(0),
I3 => rgb(5),
I4 => \encoded[6]_i_2__0_n_0\,
O => \dc_bias[3]_i_12__0_n_0\
);
\dc_bias[3]_i_13__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96669996"
)
port map (
I0 => rgb(1),
I1 => rgb(0),
I2 => \dc_bias[3]_i_30_n_0\,
I3 => \encoded[8]_i_6_n_0\,
I4 => \dc_bias[3]_i_31_n_0\,
O => \dc_bias[3]_i_13__1_n_0\
);
\dc_bias[3]_i_14__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb(2),
I1 => rgb(1),
I2 => rgb(0),
O => \dc_bias[3]_i_14__1_n_0\
);
\dc_bias[3]_i_15__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => rgb(0),
I1 => \dc_bias_reg_n_0_[0]\,
O => \dc_bias[3]_i_15__0_n_0\
);
\dc_bias[3]_i_16\: unisim.vcomponents.LUT4
generic map(
INIT => X"B42D"
)
port map (
I0 => \encoded[8]_i_2_n_0\,
I1 => rgb(4),
I2 => \encoded[6]_i_2__0_n_0\,
I3 => rgb(5),
O => \dc_bias[3]_i_16_n_0\
);
\dc_bias[3]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"1771711771171771"
)
port map (
I0 => \encoded[8]_i_2_n_0\,
I1 => rgb(7),
I2 => \encoded[6]_i_2__0_n_0\,
I3 => rgb(6),
I4 => rgb(5),
I5 => rgb(4),
O => \dc_bias[3]_i_17_n_0\
);
\dc_bias[3]_i_18__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"14414114"
)
port map (
I0 => \dc_bias[0]_i_5__1_n_0\,
I1 => rgb(0),
I2 => \dc_bias[0]_i_6_n_0\,
I3 => \dc_bias[0]_i_7_n_0\,
I4 => rgb(6),
O => \dc_bias[3]_i_18__1_n_0\
);
\dc_bias[3]_i_19__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"82BE14D714D782BE"
)
port map (
I0 => \encoded[8]_i_2_n_0\,
I1 => rgb(7),
I2 => \encoded[7]_i_2_n_0\,
I3 => rgb(0),
I4 => \dc_bias[0]_i_7_n_0\,
I5 => rgb(6),
O => \dc_bias[3]_i_19__0_n_0\
);
\dc_bias[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFAAEB"
)
port map (
I0 => \dc_bias[3]_i_2__0_n_0\,
I1 => \dc_bias[3]_i_3__0_n_0\,
I2 => \dc_bias[3]_i_4__0_n_0\,
I3 => \dc_bias[3]_i_5__1_n_0\,
I4 => \dc_bias[3]_i_6__0_n_0\,
I5 => \dc_bias[3]_i_7__0_n_0\,
O => \dc_bias[3]_i_1__0_n_0\
);
\dc_bias[3]_i_20\: unisim.vcomponents.LUT6
generic map(
INIT => X"42BDBD42BD4242BD"
)
port map (
I0 => rgb(6),
I1 => \encoded[8]_i_2_n_0\,
I2 => rgb(5),
I3 => rgb(4),
I4 => \encoded[6]_i_2__0_n_0\,
I5 => \dc_bias[1]_i_7__0_n_0\,
O => \dc_bias[3]_i_20_n_0\
);
\dc_bias[3]_i_21__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BAAEEFFBEFFBBAAE"
)
port map (
I0 => \dc_bias[1]_i_7__0_n_0\,
I1 => rgb(6),
I2 => \encoded[8]_i_2_n_0\,
I3 => rgb(5),
I4 => rgb(4),
I5 => \encoded[6]_i_2__0_n_0\,
O => \dc_bias[3]_i_21__1_n_0\
);
\dc_bias[3]_i_22__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"99F99099"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => \dc_bias[3]_i_10__0_n_0\,
I2 => \encoded[8]_i_2_n_0\,
I3 => \dc_bias[0]_i_2__0_n_0\,
I4 => \dc_bias_reg_n_0_[0]\,
O => \dc_bias[3]_i_22__0_n_0\
);
\dc_bias[3]_i_23__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \dc_bias[3]_i_10__0_n_0\,
I1 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[3]_i_23__1_n_0\
);
\dc_bias[3]_i_24__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_2__0_n_0\,
I2 => \encoded[8]_i_2_n_0\,
O => \dc_bias[3]_i_24__0_n_0\
);
\dc_bias[3]_i_25__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"002BD400FFD42BFF"
)
port map (
I0 => \dc_bias[1]_i_5_n_0\,
I1 => \dc_bias[1]_i_7__0_n_0\,
I2 => \dc_bias[1]_i_6__1_n_0\,
I3 => \dc_bias[2]_i_6__0_n_0\,
I4 => \dc_bias_reg_n_0_[2]\,
I5 => p_1_in,
O => \dc_bias[3]_i_25__0_n_0\
);
\dc_bias[3]_i_26__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFD4DDD4DD0000"
)
port map (
I0 => \dc_bias[3]_i_10__0_n_0\,
I1 => \dc_bias_reg_n_0_[1]\,
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias[0]_i_2__0_n_0\,
I4 => \dc_bias_reg_n_0_[2]\,
I5 => \dc_bias[3]_i_9__0_n_0\,
O => \dc_bias[3]_i_26__0_n_0\
);
\dc_bias[3]_i_27__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EBBBEEEB82228882"
)
port map (
I0 => \dc_bias[0]_i_7_n_0\,
I1 => \dc_bias[3]_i_32_n_0\,
I2 => \dc_bias[3]_i_30_n_0\,
I3 => \encoded[8]_i_6_n_0\,
I4 => \dc_bias[3]_i_31_n_0\,
I5 => \encoded[7]_i_2_n_0\,
O => \dc_bias[3]_i_27__0_n_0\
);
\dc_bias[3]_i_28\: unisim.vcomponents.LUT6
generic map(
INIT => X"8E71718E718E8E71"
)
port map (
I0 => \dc_bias[3]_i_30_n_0\,
I1 => \encoded[8]_i_6_n_0\,
I2 => \dc_bias[3]_i_31_n_0\,
I3 => rgb(4),
I4 => \encoded[6]_i_2__0_n_0\,
I5 => rgb(6),
O => \dc_bias[3]_i_28_n_0\
);
\dc_bias[3]_i_29\: unisim.vcomponents.LUT6
generic map(
INIT => X"BAFB5D45BAFB4504"
)
port map (
I0 => \encoded[8]_i_6_n_0\,
I1 => \encoded[8]_i_5_n_0\,
I2 => \encoded[8]_i_4_n_0\,
I3 => \encoded[8]_i_3_n_0\,
I4 => \dc_bias[0]_i_6_n_0\,
I5 => rgb(0),
O => \dc_bias[3]_i_29_n_0\
);
\dc_bias[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAAE"
)
port map (
I0 => \dc_bias[3]_i_8__0_n_0\,
I1 => \dc_bias[3]_i_9__0_n_0\,
I2 => \dc_bias[3]_i_10__0_n_0\,
I3 => \dc_bias[0]_i_2__0_n_0\,
O => \dc_bias[3]_i_2__0_n_0\
);
\dc_bias[3]_i_30\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F6606000FFF6"
)
port map (
I0 => \dc_bias[3]_i_33_n_0\,
I1 => rgb(6),
I2 => rgb(7),
I3 => rgb(0),
I4 => \encoded[8]_i_5_n_0\,
I5 => \dc_bias[3]_i_34_n_0\,
O => \dc_bias[3]_i_30_n_0\
);
\dc_bias[3]_i_31\: unisim.vcomponents.LUT6
generic map(
INIT => X"4008000029610000"
)
port map (
I0 => rgb(7),
I1 => \encoded[6]_i_2__0_n_0\,
I2 => \encoded[8]_i_7_n_0\,
I3 => \dc_bias[3]_i_34_n_0\,
I4 => rgb(0),
I5 => \encoded[8]_i_5_n_0\,
O => \dc_bias[3]_i_31_n_0\
);
\dc_bias[3]_i_32\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669699669969669"
)
port map (
I0 => rgb(5),
I1 => rgb(4),
I2 => rgb(2),
I3 => rgb(1),
I4 => rgb(0),
I5 => rgb(3),
O => \dc_bias[3]_i_32_n_0\
);
\dc_bias[3]_i_33\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb(4),
I1 => rgb(5),
O => \dc_bias[3]_i_33_n_0\
);
\dc_bias[3]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb(3),
I1 => rgb(2),
I2 => rgb(1),
O => \dc_bias[3]_i_34_n_0\
);
\dc_bias[3]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8A088A8A8A8AAE8A"
)
port map (
I0 => \dc_bias[2]_i_4_n_0\,
I1 => \dc_bias[3]_i_11__0_n_0\,
I2 => \dc_bias[3]_i_12__0_n_0\,
I3 => \dc_bias[3]_i_13__1_n_0\,
I4 => \dc_bias[3]_i_14__1_n_0\,
I5 => \dc_bias[0]_i_3__0_n_0\,
O => \dc_bias[3]_i_3__0_n_0\
);
\dc_bias[3]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"56555555AA6A6A56"
)
port map (
I0 => p_1_in,
I1 => \dc_bias[3]_i_15__0_n_0\,
I2 => \dc_bias_reg_n_0_[1]\,
I3 => \dc_bias[3]_i_16_n_0\,
I4 => \dc_bias[3]_i_17_n_0\,
I5 => \dc_bias_reg_n_0_[2]\,
O => \dc_bias[3]_i_4__0_n_0\
);
\dc_bias[3]_i_5__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A6655555"
)
port map (
I0 => p_1_in,
I1 => \dc_bias[3]_i_18__1_n_0\,
I2 => \dc_bias[3]_i_19__0_n_0\,
I3 => \dc_bias[3]_i_20_n_0\,
I4 => \dc_bias[3]_i_21__1_n_0\,
O => \dc_bias[3]_i_5__1_n_0\
);
\dc_bias[3]_i_6__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C40404040CCC0"
)
port map (
I0 => \dc_bias[3]_i_22__0_n_0\,
I1 => \dc_bias[3]_i_5__1_n_0\,
I2 => \dc_bias[3]_i_23__1_n_0\,
I3 => \dc_bias[3]_i_24__0_n_0\,
I4 => \dc_bias[3]_i_9__0_n_0\,
I5 => \dc_bias_reg_n_0_[2]\,
O => \dc_bias[3]_i_6__0_n_0\
);
\dc_bias[3]_i_7__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B08080B0"
)
port map (
I0 => \dc_bias[3]_i_25__0_n_0\,
I1 => \encoded[8]_i_2_n_0\,
I2 => \dc_bias[3]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_26__0_n_0\,
I4 => \dc_bias[3]_i_5__1_n_0\,
O => \dc_bias[3]_i_7__0_n_0\
);
\dc_bias[3]_i_8__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias_reg_n_0_[2]\,
I2 => p_1_in,
I3 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[3]_i_8__0_n_0\
);
\dc_bias[3]_i_9__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"D444DDD4DDD4BDDD"
)
port map (
I0 => \dc_bias[1]_i_7__0_n_0\,
I1 => \dc_bias[3]_i_27__0_n_0\,
I2 => \dc_bias[3]_i_28_n_0\,
I3 => rgb(0),
I4 => \dc_bias[3]_i_29_n_0\,
I5 => \dc_bias[0]_i_5__1_n_0\,
O => \dc_bias[3]_i_9__0_n_0\
);
\dc_bias_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[0]_i_1__0_n_0\,
Q => \dc_bias_reg_n_0_[0]\,
R => SR(0)
);
\dc_bias_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[1]_i_1_n_0\,
Q => \dc_bias_reg_n_0_[1]\,
R => SR(0)
);
\dc_bias_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[2]_i_1__0_n_0\,
Q => \dc_bias_reg_n_0_[2]\,
R => SR(0)
);
\dc_bias_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[3]_i_1__0_n_0\,
Q => p_1_in,
R => SR(0)
);
\encoded[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"82"
)
port map (
I0 => active,
I1 => rgb(0),
I2 => \encoded[9]_i_2__0_n_0\,
O => \encoded[0]_i_1__0_n_0\
);
\encoded[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2882"
)
port map (
I0 => active,
I1 => rgb(1),
I2 => rgb(0),
I3 => \encoded[7]_i_3__0_n_0\,
O => \encoded[1]_i_1__0_n_0\
);
\encoded[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"D77D7DD7"
)
port map (
I0 => active,
I1 => rgb(0),
I2 => rgb(1),
I3 => rgb(2),
I4 => \encoded[9]_i_2__0_n_0\,
O => \encoded[2]_i_1__0_n_0\
);
\encoded[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2882822882282882"
)
port map (
I0 => active,
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(0),
I4 => rgb(3),
I5 => \encoded[7]_i_3__0_n_0\,
O => \encoded[3]_i_1__0_n_0\
);
\encoded[4]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"D77D"
)
port map (
I0 => active,
I1 => \encoded[6]_i_2__0_n_0\,
I2 => rgb(4),
I3 => \encoded[9]_i_2__0_n_0\,
O => \encoded[4]_i_1__0_n_0\
);
\encoded[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"28828228"
)
port map (
I0 => active,
I1 => \encoded[6]_i_2__0_n_0\,
I2 => rgb(4),
I3 => rgb(5),
I4 => \encoded[7]_i_3__0_n_0\,
O => \encoded[5]_i_1__0_n_0\
);
\encoded[6]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"D77D7DD77DD7D77D"
)
port map (
I0 => active,
I1 => \encoded[6]_i_2__0_n_0\,
I2 => rgb(6),
I3 => rgb(5),
I4 => rgb(4),
I5 => \encoded[9]_i_2__0_n_0\,
O => \encoded[6]_i_1__0_n_0\
);
\encoded[6]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => rgb(3),
I1 => rgb(0),
I2 => rgb(1),
I3 => rgb(2),
O => \encoded[6]_i_2__0_n_0\
);
\encoded[7]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2882"
)
port map (
I0 => active,
I1 => \encoded[7]_i_2_n_0\,
I2 => rgb(7),
I3 => \encoded[7]_i_3__0_n_0\,
O => \encoded[7]_i_1__0_n_0\
);
\encoded[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => rgb(4),
I1 => rgb(5),
I2 => rgb(6),
I3 => \encoded[6]_i_2__0_n_0\,
O => \encoded[7]_i_2_n_0\
);
\encoded[7]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"BE"
)
port map (
I0 => \dc_bias[3]_i_2__0_n_0\,
I1 => \dc_bias[3]_i_5__1_n_0\,
I2 => \encoded[8]_i_2_n_0\,
O => \encoded[7]_i_3__0_n_0\
);
\encoded[8]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \encoded[8]_i_2_n_0\,
I1 => active,
O => \encoded[8]_i_1__0_n_0\
);
\encoded[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00200000F2FF20F2"
)
port map (
I0 => rgb(0),
I1 => \dc_bias[0]_i_6_n_0\,
I2 => \encoded[8]_i_3_n_0\,
I3 => \encoded[8]_i_4_n_0\,
I4 => \encoded[8]_i_5_n_0\,
I5 => \encoded[8]_i_6_n_0\,
O => \encoded[8]_i_2_n_0\
);
\encoded[8]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF6969FF69FFFF69"
)
port map (
I0 => rgb(1),
I1 => rgb(2),
I2 => rgb(3),
I3 => rgb(0),
I4 => rgb(7),
I5 => \encoded[8]_i_7_n_0\,
O => \encoded[8]_i_3_n_0\
);
\encoded[8]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"E88E8EE8"
)
port map (
I0 => rgb(0),
I1 => rgb(7),
I2 => rgb(6),
I3 => rgb(5),
I4 => rgb(4),
O => \encoded[8]_i_4_n_0\
);
\encoded[8]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"E8E8E817E8171717"
)
port map (
I0 => rgb(2),
I1 => rgb(3),
I2 => rgb(1),
I3 => rgb(6),
I4 => rgb(5),
I5 => rgb(4),
O => \encoded[8]_i_5_n_0\
);
\encoded[8]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"E8E8E800E8000000"
)
port map (
I0 => rgb(6),
I1 => rgb(5),
I2 => rgb(4),
I3 => rgb(2),
I4 => rgb(3),
I5 => rgb(1),
O => \encoded[8]_i_6_n_0\
);
\encoded[8]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb(6),
I1 => rgb(5),
I2 => rgb(4),
O => \encoded[8]_i_7_n_0\
);
\encoded[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => active,
I1 => \encoded[9]_i_2__0_n_0\,
O => \encoded[9]_i_1_n_0\
);
\encoded[9]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \encoded[8]_i_2_n_0\,
I1 => \dc_bias[3]_i_2__0_n_0\,
I2 => \dc_bias[3]_i_5__1_n_0\,
O => \encoded[9]_i_2__0_n_0\
);
\encoded_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[0]_i_1__0_n_0\,
Q => \encoded_reg_n_0_[0]\,
R => '0'
);
\encoded_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[1]_i_1__0_n_0\,
Q => \encoded_reg_n_0_[1]\,
R => '0'
);
\encoded_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[2]_i_1__0_n_0\,
Q => \encoded_reg_n_0_[2]\,
R => '0'
);
\encoded_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[3]_i_1__0_n_0\,
Q => \encoded_reg_n_0_[3]\,
R => '0'
);
\encoded_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[4]_i_1__0_n_0\,
Q => \encoded_reg_n_0_[4]\,
R => '0'
);
\encoded_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[5]_i_1__0_n_0\,
Q => \encoded_reg_n_0_[5]\,
R => '0'
);
\encoded_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[6]_i_1__0_n_0\,
Q => \encoded_reg_n_0_[6]\,
R => '0'
);
\encoded_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[7]_i_1__0_n_0\,
Q => \encoded_reg_n_0_[7]\,
R => '0'
);
\encoded_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[8]_i_1__0_n_0\,
Q => Q(0),
R => '0'
);
\encoded_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[9]_i_1_n_0\,
Q => Q(1),
R => '0'
);
\shift_green[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_green(0),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[0]\,
O => D(0)
);
\shift_green[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_green(1),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[1]\,
O => D(1)
);
\shift_green[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_green(2),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[2]\,
O => D(2)
);
\shift_green[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_green(3),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[3]\,
O => D(3)
);
\shift_green[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_green(4),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[4]\,
O => D(4)
);
\shift_green[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_green(5),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[5]\,
O => D(5)
);
\shift_green[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_green(6),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[6]\,
O => D(6)
);
\shift_green[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_green(7),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[7]\,
O => D(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zybo_hdmi_0_0_TMDS_encoder_1 is
port (
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
rgb : in STD_LOGIC_VECTOR ( 7 downto 0 );
active : in STD_LOGIC;
data1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
\shift_clock_reg[5]\ : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
clk_25 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_zybo_hdmi_0_0_TMDS_encoder_1 : entity is "TMDS_encoder";
end system_zybo_hdmi_0_0_TMDS_encoder_1;
architecture STRUCTURE of system_zybo_hdmi_0_0_TMDS_encoder_1 is
signal \dc_bias[0]_i_1_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_2_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_3_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_4_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_5_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_6__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_2_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_3_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_4_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_5__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_6_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_7_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_10__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_11_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_12_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_13_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_14_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_15_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_16_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_17_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_18_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_19_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_20_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_21_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_22_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_2_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_3_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_4__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_5_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_6_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_7__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_8_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_9__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_10_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_11_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_12_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_13_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_14_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_15_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_16__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_17__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_18_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_19_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_20__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_21__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_22_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_23_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_24_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_25_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_26_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_27_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_2_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_3_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_4_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_5__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_6_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_7_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_8_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_9_n_0\ : STD_LOGIC;
signal \dc_bias_reg[1]_i_1_n_0\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[0]\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[1]\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[2]\ : STD_LOGIC;
signal encoded : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \encoded[6]_i_2_n_0\ : STD_LOGIC;
signal \encoded[7]_i_2__0_n_0\ : STD_LOGIC;
signal \encoded[7]_i_3_n_0\ : STD_LOGIC;
signal \encoded[8]_i_1_n_0\ : STD_LOGIC;
signal \encoded[9]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[9]_i_2_n_0\ : STD_LOGIC;
signal \encoded_reg_n_0_[0]\ : STD_LOGIC;
signal \encoded_reg_n_0_[1]\ : STD_LOGIC;
signal \encoded_reg_n_0_[2]\ : STD_LOGIC;
signal \encoded_reg_n_0_[3]\ : STD_LOGIC;
signal \encoded_reg_n_0_[4]\ : STD_LOGIC;
signal \encoded_reg_n_0_[5]\ : STD_LOGIC;
signal \encoded_reg_n_0_[6]\ : STD_LOGIC;
signal \encoded_reg_n_0_[7]\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \dc_bias[0]_i_2\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \dc_bias[0]_i_4\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \dc_bias[0]_i_6__0\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \dc_bias[1]_i_7\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \dc_bias[2]_i_10__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \dc_bias[2]_i_12\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \dc_bias[2]_i_13\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \dc_bias[2]_i_15\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \dc_bias[2]_i_16\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \dc_bias[2]_i_17\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \dc_bias[2]_i_18\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \dc_bias[2]_i_19\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \dc_bias[2]_i_20\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \dc_bias[2]_i_22\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \dc_bias[2]_i_8\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \dc_bias[3]_i_10\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \dc_bias[3]_i_14\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \dc_bias[3]_i_16__1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \dc_bias[3]_i_20__1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \dc_bias[3]_i_25\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \dc_bias[3]_i_3\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \encoded[0]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \encoded[1]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \encoded[2]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \encoded[4]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \encoded[6]_i_2\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \encoded[7]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \encoded[7]_i_2__0\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \encoded[7]_i_3\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \encoded[8]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \encoded[9]_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \encoded[9]_i_2\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \shift_red[0]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \shift_red[1]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \shift_red[2]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \shift_red[3]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \shift_red[4]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \shift_red[5]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \shift_red[6]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \shift_red[7]_i_1\ : label is "soft_lutpair55";
begin
\dc_bias[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6F60606F606F6F60"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_2_n_0\,
I2 => \dc_bias[3]_i_6_n_0\,
I3 => \dc_bias[2]_i_4__0_n_0\,
I4 => \dc_bias[0]_i_3_n_0\,
I5 => \dc_bias[0]_i_4_n_0\,
O => \dc_bias[0]_i_1_n_0\
);
\dc_bias[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb(1),
I1 => rgb(3),
I2 => \dc_bias[0]_i_5_n_0\,
I3 => \dc_bias[0]_i_6__0_n_0\,
O => \dc_bias[0]_i_2_n_0\
);
\dc_bias[0]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => \encoded[6]_i_2_n_0\,
I1 => rgb(5),
I2 => rgb(0),
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(7),
O => \dc_bias[0]_i_3_n_0\
);
\dc_bias[0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb(2),
I1 => \dc_bias[3]_i_4_n_0\,
O => \dc_bias[0]_i_4_n_0\
);
\dc_bias[0]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669699669969669"
)
port map (
I0 => \encoded[6]_i_2_n_0\,
I1 => rgb(4),
I2 => rgb(5),
I3 => rgb(6),
I4 => rgb(7),
I5 => \dc_bias[3]_i_4_n_0\,
O => \dc_bias[0]_i_5_n_0\
);
\dc_bias[0]_i_6__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \dc_bias[3]_i_4_n_0\,
I1 => rgb(4),
I2 => \encoded[6]_i_2_n_0\,
I3 => rgb(6),
O => \dc_bias[0]_i_6__0_n_0\
);
\dc_bias[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CC3CC3CC55555555"
)
port map (
I0 => \dc_bias[1]_i_4_n_0\,
I1 => \dc_bias[1]_i_5__0_n_0\,
I2 => \dc_bias[3]_i_4_n_0\,
I3 => \dc_bias[0]_i_2_n_0\,
I4 => \dc_bias_reg_n_0_[0]\,
I5 => \dc_bias[2]_i_4__0_n_0\,
O => \dc_bias[1]_i_2_n_0\
);
\dc_bias[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"F00F0FF099999999"
)
port map (
I0 => \dc_bias[3]_i_16__1_n_0\,
I1 => \dc_bias[1]_i_5__0_n_0\,
I2 => \dc_bias[1]_i_6_n_0\,
I3 => \dc_bias[1]_i_7_n_0\,
I4 => \dc_bias[2]_i_12_n_0\,
I5 => \dc_bias[3]_i_4_n_0\,
O => \dc_bias[1]_i_3_n_0\
);
\dc_bias[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"95A9A96A569595A9"
)
port map (
I0 => \dc_bias[2]_i_18_n_0\,
I1 => \dc_bias[2]_i_16_n_0\,
I2 => \dc_bias[2]_i_17_n_0\,
I3 => \dc_bias[2]_i_19_n_0\,
I4 => \dc_bias[2]_i_20_n_0\,
I5 => rgb(7),
O => \dc_bias[1]_i_4_n_0\
);
\dc_bias[1]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9996699969996669"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => \dc_bias[3]_i_26_n_0\,
I2 => \dc_bias[0]_i_6__0_n_0\,
I3 => \dc_bias[0]_i_5_n_0\,
I4 => rgb(0),
I5 => \dc_bias[3]_i_25_n_0\,
O => \dc_bias[1]_i_5__0_n_0\
);
\dc_bias[1]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"5CC5355335535CC5"
)
port map (
I0 => \dc_bias[0]_i_6__0_n_0\,
I1 => rgb(0),
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias[0]_i_5_n_0\,
I4 => rgb(3),
I5 => rgb(1),
O => \dc_bias[1]_i_6_n_0\
);
\dc_bias[1]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"A665599A"
)
port map (
I0 => \dc_bias[2]_i_13_n_0\,
I1 => \dc_bias[0]_i_5_n_0\,
I2 => \dc_bias_reg_n_0_[0]\,
I3 => rgb(0),
I4 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[1]_i_7_n_0\
);
\dc_bias[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B888B8BBB8BBB888"
)
port map (
I0 => \dc_bias[2]_i_2_n_0\,
I1 => \dc_bias[3]_i_6_n_0\,
I2 => \dc_bias[2]_i_3_n_0\,
I3 => \dc_bias[2]_i_4__0_n_0\,
I4 => \dc_bias[2]_i_5_n_0\,
I5 => \dc_bias[2]_i_6_n_0\,
O => \dc_bias[2]_i_1_n_0\
);
\dc_bias[2]_i_10__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"90060690"
)
port map (
I0 => \dc_bias[0]_i_5_n_0\,
I1 => \dc_bias[0]_i_6__0_n_0\,
I2 => rgb(0),
I3 => rgb(1),
I4 => rgb(3),
O => \dc_bias[2]_i_10__0_n_0\
);
\dc_bias[2]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"3AA3ACCAACCA3AA3"
)
port map (
I0 => rgb(0),
I1 => \dc_bias[3]_i_4_n_0\,
I2 => rgb(7),
I3 => \encoded[7]_i_2__0_n_0\,
I4 => \dc_bias[2]_i_22_n_0\,
I5 => rgb(6),
O => \dc_bias[2]_i_11_n_0\
);
\dc_bias[2]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"2DD2B44B"
)
port map (
I0 => rgb(2),
I1 => \dc_bias[3]_i_4_n_0\,
I2 => rgb(0),
I3 => rgb(1),
I4 => rgb(3),
O => \dc_bias[2]_i_12_n_0\
);
\dc_bias[2]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"A59669A5"
)
port map (
I0 => rgb(4),
I1 => rgb(5),
I2 => \encoded[6]_i_2_n_0\,
I3 => \dc_bias[3]_i_4_n_0\,
I4 => rgb(6),
O => \dc_bias[2]_i_13_n_0\
);
\dc_bias[2]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"1771711771171771"
)
port map (
I0 => \dc_bias[3]_i_4_n_0\,
I1 => rgb(7),
I2 => rgb(6),
I3 => rgb(5),
I4 => rgb(4),
I5 => \encoded[6]_i_2_n_0\,
O => \dc_bias[2]_i_14_n_0\
);
\dc_bias[2]_i_15\: unisim.vcomponents.LUT4
generic map(
INIT => X"4BD2"
)
port map (
I0 => \dc_bias[3]_i_4_n_0\,
I1 => rgb(4),
I2 => \encoded[6]_i_2_n_0\,
I3 => rgb(5),
O => \dc_bias[2]_i_15_n_0\
);
\dc_bias[2]_i_16\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb(2),
I1 => rgb(1),
I2 => rgb(0),
O => \dc_bias[2]_i_16_n_0\
);
\dc_bias[2]_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb(1),
I1 => rgb(0),
I2 => \dc_bias[3]_i_4_n_0\,
O => \dc_bias[2]_i_17_n_0\
);
\dc_bias[2]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969696"
)
port map (
I0 => \dc_bias[2]_i_15_n_0\,
I1 => \dc_bias[2]_i_14_n_0\,
I2 => \dc_bias_reg_n_0_[1]\,
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(0),
O => \dc_bias[2]_i_18_n_0\
);
\dc_bias[2]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => rgb(5),
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(0),
I4 => rgb(3),
O => \dc_bias[2]_i_19_n_0\
);
\dc_bias[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6F60606F"
)
port map (
I0 => \dc_bias[2]_i_7__1_n_0\,
I1 => \dc_bias[3]_i_9_n_0\,
I2 => \dc_bias[3]_i_4_n_0\,
I3 => \dc_bias[2]_i_8_n_0\,
I4 => \dc_bias[2]_i_9__1_n_0\,
O => \dc_bias[2]_i_2_n_0\
);
\dc_bias[2]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb(0),
I1 => \dc_bias_reg_n_0_[0]\,
O => \dc_bias[2]_i_20_n_0\
);
\dc_bias[2]_i_21\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => rgb(6),
I1 => \dc_bias[2]_i_22_n_0\,
I2 => \encoded[7]_i_2__0_n_0\,
I3 => rgb(7),
I4 => rgb(0),
O => \dc_bias[2]_i_21_n_0\
);
\dc_bias[2]_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => rgb(4),
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(0),
I4 => rgb(3),
O => \dc_bias[2]_i_22_n_0\
);
\dc_bias[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"56569556566A5656"
)
port map (
I0 => \dc_bias[2]_i_8_n_0\,
I1 => \dc_bias_reg_n_0_[1]\,
I2 => \dc_bias[3]_i_17__1_n_0\,
I3 => \dc_bias[3]_i_4_n_0\,
I4 => \dc_bias[0]_i_2_n_0\,
I5 => \dc_bias_reg_n_0_[0]\,
O => \dc_bias[2]_i_3_n_0\
);
\dc_bias[2]_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5556566A"
)
port map (
I0 => p_1_in,
I1 => \dc_bias[2]_i_10__0_n_0\,
I2 => \dc_bias[2]_i_11_n_0\,
I3 => \dc_bias[2]_i_12_n_0\,
I4 => \dc_bias[2]_i_13_n_0\,
O => \dc_bias[2]_i_4__0_n_0\
);
\dc_bias[2]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"D44242422BBDBDBD"
)
port map (
I0 => \dc_bias[2]_i_14_n_0\,
I1 => \dc_bias[2]_i_15_n_0\,
I2 => \dc_bias_reg_n_0_[1]\,
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(0),
I5 => \dc_bias_reg_n_0_[2]\,
O => \dc_bias[2]_i_5_n_0\
);
\dc_bias[2]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7F1F170EFF7F7F1"
)
port map (
I0 => \dc_bias[2]_i_16_n_0\,
I1 => \dc_bias[2]_i_17_n_0\,
I2 => \dc_bias[2]_i_18_n_0\,
I3 => \dc_bias[2]_i_19_n_0\,
I4 => \dc_bias[2]_i_20_n_0\,
I5 => rgb(7),
O => \dc_bias[2]_i_6_n_0\
);
\dc_bias[2]_i_7__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5565656666A6A6AA"
)
port map (
I0 => \dc_bias_reg_n_0_[2]\,
I1 => \dc_bias[2]_i_13_n_0\,
I2 => \dc_bias[0]_i_5_n_0\,
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(0),
I5 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[2]_i_7__1_n_0\
);
\dc_bias[2]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \dc_bias_reg_n_0_[2]\,
I1 => \dc_bias[3]_i_15_n_0\,
O => \dc_bias[2]_i_8_n_0\
);
\dc_bias[2]_i_9__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"41141414417D7D14"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => \dc_bias[3]_i_26_n_0\,
I2 => \dc_bias[2]_i_11_n_0\,
I3 => \dc_bias[2]_i_21_n_0\,
I4 => \dc_bias[3]_i_25_n_0\,
I5 => \dc_bias_reg_n_0_[0]\,
O => \dc_bias[2]_i_9__1_n_0\
);
\dc_bias[3]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"15017F57"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => rgb(0),
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias[0]_i_5_n_0\,
I4 => \dc_bias[2]_i_13_n_0\,
O => \dc_bias[3]_i_10_n_0\
);
\dc_bias[3]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"171717FF17FFFFFF"
)
port map (
I0 => rgb(1),
I1 => rgb(3),
I2 => rgb(2),
I3 => rgb(6),
I4 => rgb(5),
I5 => rgb(4),
O => \dc_bias[3]_i_11_n_0\
);
\dc_bias[3]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb(6),
I1 => rgb(5),
I2 => rgb(4),
O => \dc_bias[3]_i_12_n_0\
);
\dc_bias[3]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"171717E817E8E8E8"
)
port map (
I0 => rgb(1),
I1 => rgb(3),
I2 => rgb(2),
I3 => rgb(6),
I4 => rgb(5),
I5 => rgb(4),
O => \dc_bias[3]_i_13_n_0\
);
\dc_bias[3]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb(3),
I1 => rgb(2),
I2 => rgb(1),
O => \dc_bias[3]_i_14_n_0\
);
\dc_bias[3]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEE78EEE8EEE888E"
)
port map (
I0 => \dc_bias[2]_i_13_n_0\,
I1 => \dc_bias[2]_i_12_n_0\,
I2 => \dc_bias[0]_i_6__0_n_0\,
I3 => \dc_bias[0]_i_5_n_0\,
I4 => rgb(0),
I5 => \dc_bias[3]_i_25_n_0\,
O => \dc_bias[3]_i_15_n_0\
);
\dc_bias[3]_i_16__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EBBEBEEB"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_6__0_n_0\,
I2 => \dc_bias[0]_i_5_n_0\,
I3 => rgb(3),
I4 => rgb(1),
O => \dc_bias[3]_i_16__1_n_0\
);
\dc_bias[3]_i_17__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"90F6F66F6F090990"
)
port map (
I0 => rgb(3),
I1 => rgb(1),
I2 => rgb(0),
I3 => \dc_bias[0]_i_5_n_0\,
I4 => \dc_bias[0]_i_6__0_n_0\,
I5 => \dc_bias[3]_i_26_n_0\,
O => \dc_bias[3]_i_17__1_n_0\
);
\dc_bias[3]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFFF799E799EFFF7"
)
port map (
I0 => \dc_bias[3]_i_25_n_0\,
I1 => rgb(0),
I2 => \dc_bias[0]_i_5_n_0\,
I3 => \dc_bias[0]_i_6__0_n_0\,
I4 => \dc_bias[2]_i_12_n_0\,
I5 => \dc_bias[2]_i_13_n_0\,
O => \dc_bias[3]_i_18_n_0\
);
\dc_bias[3]_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"E00E0EE00EE0E00E"
)
port map (
I0 => \dc_bias[3]_i_16__1_n_0\,
I1 => \dc_bias[3]_i_4_n_0\,
I2 => \dc_bias[2]_i_10__0_n_0\,
I3 => \dc_bias[2]_i_11_n_0\,
I4 => \dc_bias[3]_i_26_n_0\,
I5 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[3]_i_19_n_0\
);
\dc_bias[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8FFB8FFB8FFB800"
)
port map (
I0 => \dc_bias[3]_i_3_n_0\,
I1 => \dc_bias[3]_i_4_n_0\,
I2 => \dc_bias[3]_i_5__0_n_0\,
I3 => \dc_bias[3]_i_6_n_0\,
I4 => \dc_bias[3]_i_7_n_0\,
I5 => \dc_bias[3]_i_8_n_0\,
O => \dc_bias[3]_i_2_n_0\
);
\dc_bias[3]_i_20__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_2_n_0\,
I2 => \dc_bias[3]_i_4_n_0\,
O => \dc_bias[3]_i_20__1_n_0\
);
\dc_bias[3]_i_21__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A96A6A5600000000"
)
port map (
I0 => \dc_bias[3]_i_26_n_0\,
I1 => \dc_bias[0]_i_6__0_n_0\,
I2 => \dc_bias[0]_i_5_n_0\,
I3 => rgb(0),
I4 => \dc_bias[3]_i_25_n_0\,
I5 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[3]_i_21__0_n_0\
);
\dc_bias[3]_i_22\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFAEAE8AAE8AAE8A"
)
port map (
I0 => \dc_bias_reg_n_0_[2]\,
I1 => \dc_bias[2]_i_15_n_0\,
I2 => \dc_bias[2]_i_14_n_0\,
I3 => \dc_bias_reg_n_0_[1]\,
I4 => \dc_bias_reg_n_0_[0]\,
I5 => rgb(0),
O => \dc_bias[3]_i_22_n_0\
);
\dc_bias[3]_i_23\: unisim.vcomponents.LUT6
generic map(
INIT => X"02BF002B002B0002"
)
port map (
I0 => rgb(7),
I1 => \dc_bias[2]_i_20_n_0\,
I2 => \dc_bias[2]_i_19_n_0\,
I3 => \dc_bias[2]_i_18_n_0\,
I4 => \dc_bias[2]_i_17_n_0\,
I5 => \dc_bias[2]_i_16_n_0\,
O => \dc_bias[3]_i_23_n_0\
);
\dc_bias[3]_i_24\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF5775D55D"
)
port map (
I0 => \dc_bias[2]_i_18_n_0\,
I1 => \dc_bias[3]_i_4_n_0\,
I2 => rgb(0),
I3 => rgb(1),
I4 => rgb(2),
I5 => \dc_bias[3]_i_27_n_0\,
O => \dc_bias[3]_i_24_n_0\
);
\dc_bias[3]_i_25\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb(3),
I1 => rgb(1),
I2 => rgb(0),
O => \dc_bias[3]_i_25_n_0\
);
\dc_bias[3]_i_26\: unisim.vcomponents.LUT6
generic map(
INIT => X"963CC39669C33C69"
)
port map (
I0 => rgb(3),
I1 => rgb(1),
I2 => rgb(0),
I3 => \dc_bias[3]_i_4_n_0\,
I4 => rgb(2),
I5 => \dc_bias[2]_i_13_n_0\,
O => \dc_bias[3]_i_26_n_0\
);
\dc_bias[3]_i_27\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFBEBEFF"
)
port map (
I0 => \dc_bias[0]_i_4_n_0\,
I1 => \encoded[6]_i_2_n_0\,
I2 => rgb(5),
I3 => rgb(0),
I4 => \dc_bias_reg_n_0_[0]\,
I5 => rgb(7),
O => \dc_bias[3]_i_27_n_0\
);
\dc_bias[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"E718"
)
port map (
I0 => \dc_bias[3]_i_9_n_0\,
I1 => \dc_bias[3]_i_10_n_0\,
I2 => \dc_bias_reg_n_0_[2]\,
I3 => p_1_in,
O => \dc_bias[3]_i_3_n_0\
);
\dc_bias[3]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0022AAAA32EAAAAA"
)
port map (
I0 => \dc_bias[3]_i_11_n_0\,
I1 => \dc_bias[3]_i_12_n_0\,
I2 => rgb(0),
I3 => rgb(7),
I4 => \dc_bias[3]_i_13_n_0\,
I5 => \dc_bias[3]_i_14_n_0\,
O => \dc_bias[3]_i_4_n_0\
);
\dc_bias[3]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5656566A566A6A6A"
)
port map (
I0 => \dc_bias[2]_i_4__0_n_0\,
I1 => \dc_bias[3]_i_15_n_0\,
I2 => \dc_bias_reg_n_0_[2]\,
I3 => \dc_bias[3]_i_16__1_n_0\,
I4 => \dc_bias[3]_i_17__1_n_0\,
I5 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[3]_i_5__0_n_0\
);
\dc_bias[3]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => p_1_in,
I2 => \dc_bias_reg_n_0_[2]\,
I3 => \dc_bias_reg_n_0_[0]\,
I4 => \dc_bias[3]_i_18_n_0\,
O => \dc_bias[3]_i_6_n_0\
);
\dc_bias[3]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0000400040C0CC"
)
port map (
I0 => \dc_bias[3]_i_19_n_0\,
I1 => \dc_bias[2]_i_4__0_n_0\,
I2 => \dc_bias[3]_i_20__1_n_0\,
I3 => \dc_bias[3]_i_21__0_n_0\,
I4 => \dc_bias_reg_n_0_[2]\,
I5 => \dc_bias[3]_i_15_n_0\,
O => \dc_bias[3]_i_7_n_0\
);
\dc_bias[3]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000096969996"
)
port map (
I0 => p_1_in,
I1 => \dc_bias[3]_i_22_n_0\,
I2 => \dc_bias[3]_i_23_n_0\,
I3 => \dc_bias[3]_i_24_n_0\,
I4 => \dc_bias[2]_i_5_n_0\,
I5 => \dc_bias[2]_i_4__0_n_0\,
O => \dc_bias[3]_i_8_n_0\
);
\dc_bias[3]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"17"
)
port map (
I0 => \dc_bias[1]_i_6_n_0\,
I1 => \dc_bias[2]_i_12_n_0\,
I2 => \dc_bias[1]_i_7_n_0\,
O => \dc_bias[3]_i_9_n_0\
);
\dc_bias_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[0]_i_1_n_0\,
Q => \dc_bias_reg_n_0_[0]\,
R => SR(0)
);
\dc_bias_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias_reg[1]_i_1_n_0\,
Q => \dc_bias_reg_n_0_[1]\,
R => SR(0)
);
\dc_bias_reg[1]_i_1\: unisim.vcomponents.MUXF7
port map (
I0 => \dc_bias[1]_i_2_n_0\,
I1 => \dc_bias[1]_i_3_n_0\,
O => \dc_bias_reg[1]_i_1_n_0\,
S => \dc_bias[3]_i_6_n_0\
);
\dc_bias_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[2]_i_1_n_0\,
Q => \dc_bias_reg_n_0_[2]\,
R => SR(0)
);
\dc_bias_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[3]_i_2_n_0\,
Q => p_1_in,
R => SR(0)
);
\encoded[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"28"
)
port map (
I0 => active,
I1 => rgb(0),
I2 => \encoded[9]_i_2_n_0\,
O => encoded(0)
);
\encoded[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8228"
)
port map (
I0 => active,
I1 => \encoded[7]_i_3_n_0\,
I2 => rgb(1),
I3 => rgb(0),
O => encoded(1)
);
\encoded[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7DD7D77D"
)
port map (
I0 => active,
I1 => rgb(0),
I2 => rgb(1),
I3 => rgb(2),
I4 => \encoded[9]_i_2_n_0\,
O => encoded(2)
);
\encoded[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8228288228828228"
)
port map (
I0 => active,
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(0),
I4 => rgb(3),
I5 => \encoded[7]_i_3_n_0\,
O => encoded(3)
);
\encoded[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7DD7"
)
port map (
I0 => active,
I1 => \encoded[6]_i_2_n_0\,
I2 => rgb(4),
I3 => \encoded[9]_i_2_n_0\,
O => encoded(4)
);
\encoded[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"82282882"
)
port map (
I0 => active,
I1 => rgb(4),
I2 => rgb(5),
I3 => \encoded[6]_i_2_n_0\,
I4 => \encoded[7]_i_3_n_0\,
O => encoded(5)
);
\encoded[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7DD7D77DD77D7DD7"
)
port map (
I0 => active,
I1 => rgb(6),
I2 => rgb(5),
I3 => rgb(4),
I4 => \encoded[6]_i_2_n_0\,
I5 => \encoded[9]_i_2_n_0\,
O => encoded(6)
);
\encoded[6]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => rgb(3),
I1 => rgb(0),
I2 => rgb(1),
I3 => rgb(2),
O => \encoded[6]_i_2_n_0\
);
\encoded[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8228"
)
port map (
I0 => active,
I1 => \encoded[7]_i_2__0_n_0\,
I2 => rgb(7),
I3 => \encoded[7]_i_3_n_0\,
O => encoded(7)
);
\encoded[7]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \encoded[6]_i_2_n_0\,
I1 => rgb(4),
I2 => rgb(5),
I3 => rgb(6),
O => \encoded[7]_i_2__0_n_0\
);
\encoded[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \dc_bias[3]_i_6_n_0\,
I1 => \dc_bias[2]_i_4__0_n_0\,
I2 => \dc_bias[3]_i_4_n_0\,
O => \encoded[7]_i_3_n_0\
);
\encoded[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \dc_bias[3]_i_4_n_0\,
I1 => active,
O => \encoded[8]_i_1_n_0\
);
\encoded[9]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \encoded[9]_i_2_n_0\,
I1 => active,
O => \encoded[9]_i_1__0_n_0\
);
\encoded[9]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"74"
)
port map (
I0 => \dc_bias[3]_i_4_n_0\,
I1 => \dc_bias[3]_i_6_n_0\,
I2 => \dc_bias[2]_i_4__0_n_0\,
O => \encoded[9]_i_2_n_0\
);
\encoded_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => encoded(0),
Q => \encoded_reg_n_0_[0]\,
R => '0'
);
\encoded_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => encoded(1),
Q => \encoded_reg_n_0_[1]\,
R => '0'
);
\encoded_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => encoded(2),
Q => \encoded_reg_n_0_[2]\,
R => '0'
);
\encoded_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => encoded(3),
Q => \encoded_reg_n_0_[3]\,
R => '0'
);
\encoded_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => encoded(4),
Q => \encoded_reg_n_0_[4]\,
R => '0'
);
\encoded_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => encoded(5),
Q => \encoded_reg_n_0_[5]\,
R => '0'
);
\encoded_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => encoded(6),
Q => \encoded_reg_n_0_[6]\,
R => '0'
);
\encoded_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => encoded(7),
Q => \encoded_reg_n_0_[7]\,
R => '0'
);
\encoded_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[8]_i_1_n_0\,
Q => Q(0),
R => '0'
);
\encoded_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[9]_i_1__0_n_0\,
Q => Q(1),
R => '0'
);
\shift_red[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data1(0),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[0]\,
O => D(0)
);
\shift_red[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data1(1),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[1]\,
O => D(1)
);
\shift_red[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data1(2),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[2]\,
O => D(2)
);
\shift_red[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data1(3),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[3]\,
O => D(3)
);
\shift_red[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data1(4),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[4]\,
O => D(4)
);
\shift_red[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data1(5),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[5]\,
O => D(5)
);
\shift_red[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data1(6),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[6]\,
O => D(6)
);
\shift_red[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data1(7),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[7]\,
O => D(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zybo_hdmi_0_0_dvid is
port (
red_s : out STD_LOGIC;
green_s : out STD_LOGIC;
blue_s : out STD_LOGIC;
clock_s : out STD_LOGIC;
clk_125 : in STD_LOGIC;
rgb : in STD_LOGIC_VECTOR ( 23 downto 0 );
active : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
clk_25 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_zybo_hdmi_0_0_dvid : entity is "dvid";
end system_zybo_hdmi_0_0_dvid;
architecture STRUCTURE of system_zybo_hdmi_0_0_dvid is
signal D0 : STD_LOGIC;
signal D1 : STD_LOGIC;
signal TMDS_encoder_BLUE_n_0 : STD_LOGIC;
signal TMDS_encoder_BLUE_n_10 : STD_LOGIC;
signal TMDS_encoder_BLUE_n_9 : STD_LOGIC;
signal TMDS_encoder_GREEN_n_8 : STD_LOGIC;
signal TMDS_encoder_GREEN_n_9 : STD_LOGIC;
signal TMDS_encoder_RED_n_8 : STD_LOGIC;
signal TMDS_encoder_RED_n_9 : STD_LOGIC;
signal clk_dvin : STD_LOGIC;
signal data1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal shift_blue : STD_LOGIC_VECTOR ( 9 downto 2 );
signal shift_blue_0 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \shift_blue_reg_n_0_[0]\ : STD_LOGIC;
signal \shift_blue_reg_n_0_[1]\ : STD_LOGIC;
signal shift_clock : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \shift_clock_reg_n_0_[2]\ : STD_LOGIC;
signal \shift_clock_reg_n_0_[3]\ : STD_LOGIC;
signal \shift_clock_reg_n_0_[4]\ : STD_LOGIC;
signal \shift_clock_reg_n_0_[5]\ : STD_LOGIC;
signal \shift_clock_reg_n_0_[6]\ : STD_LOGIC;
signal \shift_clock_reg_n_0_[7]\ : STD_LOGIC;
signal \shift_clock_reg_n_0_[8]\ : STD_LOGIC;
signal \shift_clock_reg_n_0_[9]\ : STD_LOGIC;
signal shift_green : STD_LOGIC_VECTOR ( 9 downto 2 );
signal shift_green_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \shift_green_reg_n_0_[0]\ : STD_LOGIC;
signal \shift_green_reg_n_0_[1]\ : STD_LOGIC;
signal shift_red : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \shift_red[9]_i_1_n_0\ : STD_LOGIC;
signal \shift_red[9]_i_2_n_0\ : STD_LOGIC;
signal NLW_ODDR2_BLUE_R_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR2_BLUE_S_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR2_CLK_R_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR2_CLK_S_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR2_GREEN_R_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR2_GREEN_S_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR2_RED_R_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR2_RED_S_UNCONNECTED : STD_LOGIC;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of ODDR2_BLUE : label is "ODDR2";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of ODDR2_BLUE : label is "D0:D1 D1:D2 C0:C";
attribute \__SRVAL\ : string;
attribute \__SRVAL\ of ODDR2_BLUE : label is "TRUE";
attribute box_type : string;
attribute box_type of ODDR2_BLUE : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of ODDR2_CLK : label is "ODDR2";
attribute XILINX_TRANSFORM_PINMAP of ODDR2_CLK : label is "D0:D1 D1:D2 C0:C";
attribute \__SRVAL\ of ODDR2_CLK : label is "TRUE";
attribute box_type of ODDR2_CLK : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of ODDR2_GREEN : label is "ODDR2";
attribute XILINX_TRANSFORM_PINMAP of ODDR2_GREEN : label is "D0:D1 D1:D2 C0:C";
attribute \__SRVAL\ of ODDR2_GREEN : label is "TRUE";
attribute box_type of ODDR2_GREEN : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of ODDR2_RED : label is "ODDR2";
attribute XILINX_TRANSFORM_PINMAP of ODDR2_RED : label is "D0:D1 D1:D2 C0:C";
attribute \__SRVAL\ of ODDR2_RED : label is "TRUE";
attribute box_type of ODDR2_RED : label is "PRIMITIVE";
begin
ODDR2_BLUE: unisim.vcomponents.ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "ASYNC"
)
port map (
C => clk_125,
CE => '1',
D1 => \shift_blue_reg_n_0_[0]\,
D2 => \shift_blue_reg_n_0_[1]\,
Q => blue_s,
R => NLW_ODDR2_BLUE_R_UNCONNECTED,
S => NLW_ODDR2_BLUE_S_UNCONNECTED
);
ODDR2_CLK: unisim.vcomponents.ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "ASYNC"
)
port map (
C => clk_125,
CE => '1',
D1 => shift_clock(0),
D2 => shift_clock(1),
Q => clock_s,
R => NLW_ODDR2_CLK_R_UNCONNECTED,
S => NLW_ODDR2_CLK_S_UNCONNECTED
);
ODDR2_GREEN: unisim.vcomponents.ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "ASYNC"
)
port map (
C => clk_125,
CE => '1',
D1 => \shift_green_reg_n_0_[0]\,
D2 => \shift_green_reg_n_0_[1]\,
Q => green_s,
R => NLW_ODDR2_GREEN_R_UNCONNECTED,
S => NLW_ODDR2_GREEN_S_UNCONNECTED
);
ODDR2_RED: unisim.vcomponents.ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "ASYNC"
)
port map (
C => clk_125,
CE => '1',
D1 => D0,
D2 => D1,
Q => red_s,
R => NLW_ODDR2_RED_R_UNCONNECTED,
S => NLW_ODDR2_RED_S_UNCONNECTED
);
ODDR2_RED_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => clk_125,
O => clk_dvin
);
TMDS_encoder_BLUE: entity work.system_zybo_hdmi_0_0_TMDS_encoder
port map (
D(7 downto 0) => shift_blue_0(7 downto 0),
Q(1) => TMDS_encoder_BLUE_n_9,
Q(0) => TMDS_encoder_BLUE_n_10,
SR(0) => TMDS_encoder_BLUE_n_0,
active => active,
clk_25 => clk_25,
hsync => hsync,
rgb(7 downto 0) => rgb(7 downto 0),
shift_blue(7 downto 0) => shift_blue(9 downto 2),
\shift_clock_reg[5]\ => \shift_red[9]_i_1_n_0\,
vsync => vsync
);
TMDS_encoder_GREEN: entity work.system_zybo_hdmi_0_0_TMDS_encoder_0
port map (
D(7 downto 0) => shift_green_1(7 downto 0),
Q(1) => TMDS_encoder_GREEN_n_8,
Q(0) => TMDS_encoder_GREEN_n_9,
SR(0) => TMDS_encoder_BLUE_n_0,
active => active,
clk_25 => clk_25,
rgb(7 downto 0) => rgb(15 downto 8),
\shift_clock_reg[5]\ => \shift_red[9]_i_1_n_0\,
shift_green(7 downto 0) => shift_green(9 downto 2)
);
TMDS_encoder_RED: entity work.system_zybo_hdmi_0_0_TMDS_encoder_1
port map (
D(7 downto 0) => shift_red(7 downto 0),
Q(1) => TMDS_encoder_RED_n_8,
Q(0) => TMDS_encoder_RED_n_9,
SR(0) => TMDS_encoder_BLUE_n_0,
active => active,
clk_25 => clk_25,
data1(7 downto 0) => data1(7 downto 0),
rgb(7 downto 0) => rgb(23 downto 16),
\shift_clock_reg[5]\ => \shift_red[9]_i_1_n_0\
);
\shift_blue_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_blue_0(0),
Q => \shift_blue_reg_n_0_[0]\,
R => '0'
);
\shift_blue_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_blue_0(1),
Q => \shift_blue_reg_n_0_[1]\,
R => '0'
);
\shift_blue_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_blue_0(2),
Q => shift_blue(2),
R => '0'
);
\shift_blue_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_blue_0(3),
Q => shift_blue(3),
R => '0'
);
\shift_blue_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_blue_0(4),
Q => shift_blue(4),
R => '0'
);
\shift_blue_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_blue_0(5),
Q => shift_blue(5),
R => '0'
);
\shift_blue_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_blue_0(6),
Q => shift_blue(6),
R => '0'
);
\shift_blue_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_blue_0(7),
Q => shift_blue(7),
R => '0'
);
\shift_blue_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => TMDS_encoder_BLUE_n_10,
Q => shift_blue(8),
R => \shift_red[9]_i_1_n_0\
);
\shift_blue_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => TMDS_encoder_BLUE_n_9,
Q => shift_blue(9),
R => \shift_red[9]_i_1_n_0\
);
\shift_clock_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_125,
CE => '1',
D => \shift_clock_reg_n_0_[2]\,
Q => shift_clock(0),
R => '0'
);
\shift_clock_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_125,
CE => '1',
D => \shift_clock_reg_n_0_[3]\,
Q => shift_clock(1),
R => '0'
);
\shift_clock_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_125,
CE => '1',
D => \shift_clock_reg_n_0_[4]\,
Q => \shift_clock_reg_n_0_[2]\,
R => '0'
);
\shift_clock_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_125,
CE => '1',
D => \shift_clock_reg_n_0_[5]\,
Q => \shift_clock_reg_n_0_[3]\,
R => '0'
);
\shift_clock_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_125,
CE => '1',
D => \shift_clock_reg_n_0_[6]\,
Q => \shift_clock_reg_n_0_[4]\,
R => '0'
);
\shift_clock_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => \shift_clock_reg_n_0_[7]\,
Q => \shift_clock_reg_n_0_[5]\,
R => '0'
);
\shift_clock_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => \shift_clock_reg_n_0_[8]\,
Q => \shift_clock_reg_n_0_[6]\,
R => '0'
);
\shift_clock_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => \shift_clock_reg_n_0_[9]\,
Q => \shift_clock_reg_n_0_[7]\,
R => '0'
);
\shift_clock_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_clock(0),
Q => \shift_clock_reg_n_0_[8]\,
R => '0'
);
\shift_clock_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_clock(1),
Q => \shift_clock_reg_n_0_[9]\,
R => '0'
);
\shift_green_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_green_1(0),
Q => \shift_green_reg_n_0_[0]\,
R => '0'
);
\shift_green_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_green_1(1),
Q => \shift_green_reg_n_0_[1]\,
R => '0'
);
\shift_green_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_green_1(2),
Q => shift_green(2),
R => '0'
);
\shift_green_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_green_1(3),
Q => shift_green(3),
R => '0'
);
\shift_green_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_green_1(4),
Q => shift_green(4),
R => '0'
);
\shift_green_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_green_1(5),
Q => shift_green(5),
R => '0'
);
\shift_green_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_green_1(6),
Q => shift_green(6),
R => '0'
);
\shift_green_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_green_1(7),
Q => shift_green(7),
R => '0'
);
\shift_green_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => TMDS_encoder_GREEN_n_9,
Q => shift_green(8),
R => \shift_red[9]_i_1_n_0\
);
\shift_green_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => TMDS_encoder_GREEN_n_8,
Q => shift_green(9),
R => \shift_red[9]_i_1_n_0\
);
\shift_red[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EFFFFFFF"
)
port map (
I0 => \shift_red[9]_i_2_n_0\,
I1 => \shift_clock_reg_n_0_[5]\,
I2 => \shift_clock_reg_n_0_[4]\,
I3 => \shift_clock_reg_n_0_[2]\,
I4 => \shift_clock_reg_n_0_[3]\,
O => \shift_red[9]_i_1_n_0\
);
\shift_red[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFFFFFFFFFFF"
)
port map (
I0 => \shift_clock_reg_n_0_[8]\,
I1 => \shift_clock_reg_n_0_[9]\,
I2 => \shift_clock_reg_n_0_[6]\,
I3 => \shift_clock_reg_n_0_[7]\,
I4 => shift_clock(1),
I5 => shift_clock(0),
O => \shift_red[9]_i_2_n_0\
);
\shift_red_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_red(0),
Q => D0,
R => '0'
);
\shift_red_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_red(1),
Q => D1,
R => '0'
);
\shift_red_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_red(2),
Q => data1(0),
R => '0'
);
\shift_red_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_red(3),
Q => data1(1),
R => '0'
);
\shift_red_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_red(4),
Q => data1(2),
R => '0'
);
\shift_red_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_red(5),
Q => data1(3),
R => '0'
);
\shift_red_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_red(6),
Q => data1(4),
R => '0'
);
\shift_red_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_red(7),
Q => data1(5),
R => '0'
);
\shift_red_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => TMDS_encoder_RED_n_9,
Q => data1(6),
R => \shift_red[9]_i_1_n_0\
);
\shift_red_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => TMDS_encoder_RED_n_8,
Q => data1(7),
R => \shift_red[9]_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zybo_hdmi_0_0_zybo_hdmi is
port (
tmds : out STD_LOGIC_VECTOR ( 3 downto 0 );
tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 );
rgb : in STD_LOGIC_VECTOR ( 23 downto 0 );
active : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
clk_125 : in STD_LOGIC;
clk_25 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_zybo_hdmi_0_0_zybo_hdmi : entity is "zybo_hdmi";
end system_zybo_hdmi_0_0_zybo_hdmi;
architecture STRUCTURE of system_zybo_hdmi_0_0_zybo_hdmi is
signal blue_s : STD_LOGIC;
signal clock_s : STD_LOGIC;
signal green_s : STD_LOGIC;
signal red_s : STD_LOGIC;
attribute CAPACITANCE : string;
attribute CAPACITANCE of OBUFDS_blue : label is "DONT_CARE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of OBUFDS_blue : label is "OBUFDS";
attribute box_type : string;
attribute box_type of OBUFDS_blue : label is "PRIMITIVE";
attribute CAPACITANCE of OBUFDS_clock : label is "DONT_CARE";
attribute XILINX_LEGACY_PRIM of OBUFDS_clock : label is "OBUFDS";
attribute box_type of OBUFDS_clock : label is "PRIMITIVE";
attribute CAPACITANCE of OBUFDS_green : label is "DONT_CARE";
attribute XILINX_LEGACY_PRIM of OBUFDS_green : label is "OBUFDS";
attribute box_type of OBUFDS_green : label is "PRIMITIVE";
attribute CAPACITANCE of OBUFDS_red : label is "DONT_CARE";
attribute XILINX_LEGACY_PRIM of OBUFDS_red : label is "OBUFDS";
attribute box_type of OBUFDS_red : label is "PRIMITIVE";
begin
DVID: entity work.system_zybo_hdmi_0_0_dvid
port map (
active => active,
blue_s => blue_s,
clk_125 => clk_125,
clk_25 => clk_25,
clock_s => clock_s,
green_s => green_s,
hsync => hsync,
red_s => red_s,
rgb(23 downto 0) => rgb(23 downto 0),
vsync => vsync
);
OBUFDS_blue: unisim.vcomponents.OBUFDS
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => blue_s,
O => tmds(0),
OB => tmdsb(0)
);
OBUFDS_clock: unisim.vcomponents.OBUFDS
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clock_s,
O => tmds(3),
OB => tmdsb(3)
);
OBUFDS_green: unisim.vcomponents.OBUFDS
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => red_s,
O => tmds(2),
OB => tmdsb(2)
);
OBUFDS_red: unisim.vcomponents.OBUFDS
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => green_s,
O => tmds(1),
OB => tmdsb(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zybo_hdmi_0_0 is
port (
clk_125 : in STD_LOGIC;
clk_25 : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
active : in STD_LOGIC;
rgb : in STD_LOGIC_VECTOR ( 23 downto 0 );
tmds : out STD_LOGIC_VECTOR ( 3 downto 0 );
tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 );
hdmi_cec : in STD_LOGIC;
hdmi_hpd : in STD_LOGIC;
hdmi_out_en : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_zybo_hdmi_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_zybo_hdmi_0_0 : entity is "system_zybo_hdmi_0_0,zybo_hdmi,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_zybo_hdmi_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_zybo_hdmi_0_0 : entity is "zybo_hdmi,Vivado 2016.4";
end system_zybo_hdmi_0_0;
architecture STRUCTURE of system_zybo_hdmi_0_0 is
signal \<const1>\ : STD_LOGIC;
begin
hdmi_out_en <= \<const1>\;
U0: entity work.system_zybo_hdmi_0_0_zybo_hdmi
port map (
active => active,
clk_125 => clk_125,
clk_25 => clk_25,
hsync => hsync,
rgb(23 downto 0) => rgb(23 downto 0),
tmds(3 downto 0) => tmds(3 downto 0),
tmdsb(3 downto 0) => tmdsb(3 downto 0),
vsync => vsync
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
| mit | 61c000d39039cf37825e5c33c2a7c351 | 0.485009 | 2.42479 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_transform_0_1/sim/system_vga_transform_0_1.vhd | 1 | 4,361 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_transform:1.0
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_transform_0_1 IS
PORT (
clk : IN STD_LOGIC;
enable : IN STD_LOGIC;
x_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rot_m00 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m01 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
t_x : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
t_y : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_vga_transform_0_1;
ARCHITECTURE system_vga_transform_0_1_arch OF system_vga_transform_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_transform_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT vga_transform IS
PORT (
clk : IN STD_LOGIC;
enable : IN STD_LOGIC;
x_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rot_m00 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m01 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
t_x : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
t_y : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT vga_transform;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : vga_transform
PORT MAP (
clk => clk,
enable => enable,
x_addr_in => x_addr_in,
y_addr_in => y_addr_in,
rot_m00 => rot_m00,
rot_m01 => rot_m01,
rot_m10 => rot_m10,
rot_m11 => rot_m11,
t_x => t_x,
t_y => t_y,
x_addr_out => x_addr_out,
y_addr_out => y_addr_out
);
END system_vga_transform_0_1_arch;
| mit | 5745863ca2b6d1ad78f261be34a0a874 | 0.698234 | 3.607113 | false | false | false | false |
pgavin/carpe | hdl/cpu/or1knd/i5/cpu_or1knd_i5_pipe_pkg.vhdl | 1 | 35,961 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library isa;
use isa.or1k_pkg.all;
package cpu_or1knd_i5_pipe_pkg is
-- control signals to datapath
type cpu_or1knd_i5_alu_src1_sel_index_type is (
cpu_or1knd_i5_alu_src1_sel_index_ra,
cpu_or1knd_i5_alu_src1_sel_index_pc
);
type cpu_or1knd_i5_alu_src1_sel_type is
array (cpu_or1knd_i5_alu_src1_sel_index_type range
cpu_or1knd_i5_alu_src1_sel_index_type'high downto cpu_or1knd_i5_alu_src1_sel_index_type'low) of std_ulogic;
constant cpu_or1knd_i5_alu_src1_sel_ra : cpu_or1knd_i5_alu_src1_sel_type := "01";
constant cpu_or1knd_i5_alu_src1_sel_pc : cpu_or1knd_i5_alu_src1_sel_type := "10";
type cpu_or1knd_i5_alu_src2_sel_index_type is (
cpu_or1knd_i5_alu_src2_sel_index_rb,
cpu_or1knd_i5_alu_src2_sel_index_imm
);
type cpu_or1knd_i5_alu_src2_sel_type is
array (cpu_or1knd_i5_alu_src2_sel_index_type range
cpu_or1knd_i5_alu_src2_sel_index_type'high downto cpu_or1knd_i5_alu_src2_sel_index_type'low) of std_ulogic;
constant cpu_or1knd_i5_alu_src2_sel_rb : cpu_or1knd_i5_alu_src2_sel_type := "01";
constant cpu_or1knd_i5_alu_src2_sel_imm : cpu_or1knd_i5_alu_src2_sel_type := "10";
type cpu_or1knd_i5_bf_pc_sel_index_type is (
cpu_or1knd_i5_bf_pc_sel_index_f,
cpu_or1knd_i5_bf_pc_sel_index_f_pc_incr,
cpu_or1knd_i5_bf_pc_sel_index_btb,
cpu_or1knd_i5_bf_pc_sel_index_d,
cpu_or1knd_i5_bf_pc_sel_index_e,
cpu_or1knd_i5_bf_pc_sel_index_e_pc_incr,
cpu_or1knd_i5_bf_pc_sel_index_e_toc_target,
cpu_or1knd_i5_bf_pc_sel_index_epcr0,
cpu_or1knd_i5_bf_pc_sel_index_m_exception_pc
);
type cpu_or1knd_i5_bf_pc_sel_type is
array (cpu_or1knd_i5_bf_pc_sel_index_type range
cpu_or1knd_i5_bf_pc_sel_index_type'high downto cpu_or1knd_i5_bf_pc_sel_index_type'low) of std_ulogic;
constant cpu_or1knd_i5_bf_pc_sel_f : cpu_or1knd_i5_bf_pc_sel_type := "000000001";
constant cpu_or1knd_i5_bf_pc_sel_f_pc_incr : cpu_or1knd_i5_bf_pc_sel_type := "000000010";
constant cpu_or1knd_i5_bf_pc_sel_btb : cpu_or1knd_i5_bf_pc_sel_type := "000000100";
constant cpu_or1knd_i5_bf_pc_sel_d : cpu_or1knd_i5_bf_pc_sel_type := "000001000";
constant cpu_or1knd_i5_bf_pc_sel_e : cpu_or1knd_i5_bf_pc_sel_type := "000010000";
constant cpu_or1knd_i5_bf_pc_sel_e_pc_incr : cpu_or1knd_i5_bf_pc_sel_type := "000100000";
constant cpu_or1knd_i5_bf_pc_sel_e_toc_target : cpu_or1knd_i5_bf_pc_sel_type := "001000000";
constant cpu_or1knd_i5_bf_pc_sel_epcr0 : cpu_or1knd_i5_bf_pc_sel_type := "010000000";
constant cpu_or1knd_i5_bf_pc_sel_m_exception_pc : cpu_or1knd_i5_bf_pc_sel_type := "100000000";
type cpu_or1knd_i5_imm_sel_index_type is (
cpu_or1knd_i5_imm_sel_index_contig,
cpu_or1knd_i5_imm_sel_index_split,
cpu_or1knd_i5_imm_sel_index_shift,
cpu_or1knd_i5_imm_sel_index_toc_offset
);
type cpu_or1knd_i5_imm_sel_type is
array (cpu_or1knd_i5_imm_sel_index_type range
cpu_or1knd_i5_imm_sel_index_type'high downto cpu_or1knd_i5_imm_sel_index_type'low) of std_ulogic;
constant cpu_or1knd_i5_imm_sel_contig : cpu_or1knd_i5_imm_sel_type := "0001";
constant cpu_or1knd_i5_imm_sel_split : cpu_or1knd_i5_imm_sel_type := "0010";
constant cpu_or1knd_i5_imm_sel_shift : cpu_or1knd_i5_imm_sel_type := "0100";
constant cpu_or1knd_i5_imm_sel_toc_offset : cpu_or1knd_i5_imm_sel_type := "1000";
type cpu_or1knd_i5_alu_result_sel_index_type is (
cpu_or1knd_i5_alu_result_sel_index_addsub,
cpu_or1knd_i5_alu_result_sel_index_shifter,
cpu_or1knd_i5_alu_result_sel_index_and,
cpu_or1knd_i5_alu_result_sel_index_or,
cpu_or1knd_i5_alu_result_sel_index_xor,
cpu_or1knd_i5_alu_result_sel_index_cmov,
cpu_or1knd_i5_alu_result_sel_index_ff1,
cpu_or1knd_i5_alu_result_sel_index_fl1,
cpu_or1knd_i5_alu_result_sel_index_ext,
cpu_or1knd_i5_alu_result_sel_index_movhi
);
type cpu_or1knd_i5_alu_result_sel_type is
array (cpu_or1knd_i5_alu_result_sel_index_type range
cpu_or1knd_i5_alu_result_sel_index_type'high downto
cpu_or1knd_i5_alu_result_sel_index_type'low) of std_ulogic;
constant cpu_or1knd_i5_alu_result_sel_addsub : cpu_or1knd_i5_alu_result_sel_type := "0000000001";
constant cpu_or1knd_i5_alu_result_sel_shifter : cpu_or1knd_i5_alu_result_sel_type := "0000000010";
constant cpu_or1knd_i5_alu_result_sel_and : cpu_or1knd_i5_alu_result_sel_type := "0000000100";
constant cpu_or1knd_i5_alu_result_sel_or : cpu_or1knd_i5_alu_result_sel_type := "0000001000";
constant cpu_or1knd_i5_alu_result_sel_xor : cpu_or1knd_i5_alu_result_sel_type := "0000010000";
constant cpu_or1knd_i5_alu_result_sel_cmov : cpu_or1knd_i5_alu_result_sel_type := "0000100000";
constant cpu_or1knd_i5_alu_result_sel_ff1 : cpu_or1knd_i5_alu_result_sel_type := "0001000000";
constant cpu_or1knd_i5_alu_result_sel_fl1 : cpu_or1knd_i5_alu_result_sel_type := "0010000000";
constant cpu_or1knd_i5_alu_result_sel_ext : cpu_or1knd_i5_alu_result_sel_type := "0100000000";
constant cpu_or1knd_i5_alu_result_sel_movhi : cpu_or1knd_i5_alu_result_sel_type := "1000000000";
type cpu_or1knd_i5_rd_data_sel_index_type is (
cpu_or1knd_i5_rd_data_sel_index_alu,
cpu_or1knd_i5_rd_data_sel_index_load,
cpu_or1knd_i5_rd_data_sel_index_mfspr,
cpu_or1knd_i5_rd_data_sel_index_div,
cpu_or1knd_i5_rd_data_sel_index_mul,
cpu_or1knd_i5_rd_data_sel_index_pc_incr,
cpu_or1knd_i5_rd_data_sel_index_maclo
);
type cpu_or1knd_i5_rd_data_sel_type is
array (cpu_or1knd_i5_rd_data_sel_index_type range
cpu_or1knd_i5_rd_data_sel_index_type'high downto cpu_or1knd_i5_rd_data_sel_index_type'low) of std_ulogic;
constant cpu_or1knd_i5_rd_data_sel_alu : cpu_or1knd_i5_rd_data_sel_type := "0000001";
constant cpu_or1knd_i5_rd_data_sel_load : cpu_or1knd_i5_rd_data_sel_type := "0000010";
constant cpu_or1knd_i5_rd_data_sel_mfspr : cpu_or1knd_i5_rd_data_sel_type := "0000100";
constant cpu_or1knd_i5_rd_data_sel_div : cpu_or1knd_i5_rd_data_sel_type := "0001000";
constant cpu_or1knd_i5_rd_data_sel_mul : cpu_or1knd_i5_rd_data_sel_type := "0010000";
constant cpu_or1knd_i5_rd_data_sel_pc_incr : cpu_or1knd_i5_rd_data_sel_type := "0100000";
constant cpu_or1knd_i5_rd_data_sel_maclo : cpu_or1knd_i5_rd_data_sel_type := "1000000";
type cpu_or1knd_i5_e_fwd_alu_src_sel_index_type is (
cpu_or1knd_i5_e_fwd_alu_src_sel_index_none,
cpu_or1knd_i5_e_fwd_alu_src_sel_index_w_rd_data,
cpu_or1knd_i5_e_fwd_alu_src_sel_index_m_alu_result
);
type cpu_or1knd_i5_e_fwd_alu_src_sel_type is
array (cpu_or1knd_i5_e_fwd_alu_src_sel_index_type range
cpu_or1knd_i5_e_fwd_alu_src_sel_index_type'high downto
cpu_or1knd_i5_e_fwd_alu_src_sel_index_type'low) of std_ulogic;
constant cpu_or1knd_i5_e_fwd_alu_src_sel_none : cpu_or1knd_i5_e_fwd_alu_src_sel_type := "001";
constant cpu_or1knd_i5_e_fwd_alu_src_sel_w_rd_data : cpu_or1knd_i5_e_fwd_alu_src_sel_type := "010";
constant cpu_or1knd_i5_e_fwd_alu_src_sel_m_alu_result : cpu_or1knd_i5_e_fwd_alu_src_sel_type := "100";
type cpu_or1knd_i5_e_fwd_st_data_sel_index_type is (
cpu_or1knd_i5_e_fwd_st_data_sel_index_none,
cpu_or1knd_i5_e_fwd_st_data_sel_index_w_rd_data,
cpu_or1knd_i5_e_fwd_st_data_sel_index_m_rd_data
);
type cpu_or1knd_i5_e_fwd_st_data_sel_type is
array (cpu_or1knd_i5_e_fwd_st_data_sel_index_type range
cpu_or1knd_i5_e_fwd_st_data_sel_index_type'high downto
cpu_or1knd_i5_e_fwd_st_data_sel_index_type'low) of std_ulogic;
constant cpu_or1knd_i5_e_fwd_st_data_sel_none : cpu_or1knd_i5_e_fwd_st_data_sel_type := "001";
constant cpu_or1knd_i5_e_fwd_st_data_sel_w_rd_data : cpu_or1knd_i5_e_fwd_st_data_sel_type := "010";
constant cpu_or1knd_i5_e_fwd_st_data_sel_m_rd_data : cpu_or1knd_i5_e_fwd_st_data_sel_type := "100";
type cpu_or1knd_i5_e_addr_sel_index_type is (
cpu_or1knd_i5_e_addr_sel_index_ldst,
cpu_or1knd_i5_e_addr_sel_index_spr
);
type cpu_or1knd_i5_e_addr_sel_type is
array (cpu_or1knd_i5_e_addr_sel_index_type range
cpu_or1knd_i5_e_addr_sel_index_spr downto cpu_or1knd_i5_e_addr_sel_index_ldst) of std_ulogic;
constant cpu_or1knd_i5_e_addr_sel_ldst : cpu_or1knd_i5_e_addr_sel_type := "01";
constant cpu_or1knd_i5_e_addr_sel_spr : cpu_or1knd_i5_e_addr_sel_type := "10";
type cpu_or1knd_i5_m_spr_sys_eear0_sel_index_type is (
cpu_or1knd_i5_m_spr_sys_eear0_sel_index_init,
cpu_or1knd_i5_m_spr_sys_eear0_sel_index_mtspr,
cpu_or1knd_i5_m_spr_sys_eear0_sel_index_pc,
cpu_or1knd_i5_m_spr_sys_eear0_sel_index_addr,
cpu_or1knd_i5_m_spr_sys_eear0_sel_index_inst_bus_error_eear,
cpu_or1knd_i5_m_spr_sys_eear0_sel_index_data_bus_error_eear
);
type cpu_or1knd_i5_m_spr_sys_eear0_sel_type is
array (cpu_or1knd_i5_m_spr_sys_eear0_sel_index_type range
cpu_or1knd_i5_m_spr_sys_eear0_sel_index_type'high downto cpu_or1knd_i5_m_spr_sys_eear0_sel_index_type'low) of std_ulogic;
constant cpu_or1knd_i5_m_spr_sys_eear0_sel_init : cpu_or1knd_i5_m_spr_sys_eear0_sel_type := "000001";
constant cpu_or1knd_i5_m_spr_sys_eear0_sel_mtspr : cpu_or1knd_i5_m_spr_sys_eear0_sel_type := "000010";
constant cpu_or1knd_i5_m_spr_sys_eear0_sel_pc : cpu_or1knd_i5_m_spr_sys_eear0_sel_type := "000100";
constant cpu_or1knd_i5_m_spr_sys_eear0_sel_addr : cpu_or1knd_i5_m_spr_sys_eear0_sel_type := "001000";
constant cpu_or1knd_i5_m_spr_sys_eear0_sel_inst_bus_error_eear : cpu_or1knd_i5_m_spr_sys_eear0_sel_type := "010000";
constant cpu_or1knd_i5_m_spr_sys_eear0_sel_data_bus_error_eear : cpu_or1knd_i5_m_spr_sys_eear0_sel_type := "100000";
type cpu_or1knd_i5_m_spr_sys_epcr0_sel_index_type is (
cpu_or1knd_i5_m_spr_sys_epcr0_sel_index_init,
cpu_or1knd_i5_m_spr_sys_epcr0_sel_index_mtspr,
cpu_or1knd_i5_m_spr_sys_epcr0_sel_index_f_pc,
cpu_or1knd_i5_m_spr_sys_epcr0_sel_index_d_pc,
cpu_or1knd_i5_m_spr_sys_epcr0_sel_index_e_pc,
cpu_or1knd_i5_m_spr_sys_epcr0_sel_index_m_pc
);
type cpu_or1knd_i5_m_spr_sys_epcr0_sel_type is
array (cpu_or1knd_i5_m_spr_sys_epcr0_sel_index_type range
cpu_or1knd_i5_m_spr_sys_epcr0_sel_index_type'high downto cpu_or1knd_i5_m_spr_sys_epcr0_sel_index_type'low) of std_ulogic;
constant cpu_or1knd_i5_m_spr_sys_epcr0_sel_init : cpu_or1knd_i5_m_spr_sys_epcr0_sel_type := "000001";
constant cpu_or1knd_i5_m_spr_sys_epcr0_sel_mtspr : cpu_or1knd_i5_m_spr_sys_epcr0_sel_type := "000010";
constant cpu_or1knd_i5_m_spr_sys_epcr0_sel_f_pc : cpu_or1knd_i5_m_spr_sys_epcr0_sel_type := "000100";
constant cpu_or1knd_i5_m_spr_sys_epcr0_sel_d_pc : cpu_or1knd_i5_m_spr_sys_epcr0_sel_type := "001000";
constant cpu_or1knd_i5_m_spr_sys_epcr0_sel_e_pc : cpu_or1knd_i5_m_spr_sys_epcr0_sel_type := "010000";
constant cpu_or1knd_i5_m_spr_sys_epcr0_sel_m_pc : cpu_or1knd_i5_m_spr_sys_epcr0_sel_type := "100000";
type cpu_or1knd_i5_m_spr_mac_machi_sel_index_type is (
cpu_or1knd_i5_m_spr_mac_machi_sel_index_mtspr,
cpu_or1knd_i5_m_spr_mac_machi_sel_index_clear,
cpu_or1knd_i5_m_spr_mac_machi_sel_index_madd
);
type cpu_or1knd_i5_m_spr_mac_machi_sel_type is
array (cpu_or1knd_i5_m_spr_mac_machi_sel_index_type range
cpu_or1knd_i5_m_spr_mac_machi_sel_index_madd downto cpu_or1knd_i5_m_spr_mac_machi_sel_index_mtspr) of std_ulogic;
constant cpu_or1knd_i5_m_spr_mac_machi_sel_mtspr : cpu_or1knd_i5_m_spr_mac_machi_sel_type := "001";
constant cpu_or1knd_i5_m_spr_mac_machi_sel_clear : cpu_or1knd_i5_m_spr_mac_machi_sel_type := "010";
constant cpu_or1knd_i5_m_spr_mac_machi_sel_madd : cpu_or1knd_i5_m_spr_mac_machi_sel_type := "100";
type cpu_or1knd_i5_m_spr_mac_maclo_sel_index_type is (
cpu_or1knd_i5_m_spr_mac_maclo_sel_index_mtspr,
cpu_or1knd_i5_m_spr_mac_maclo_sel_index_clear,
cpu_or1knd_i5_m_spr_mac_maclo_sel_index_madd
);
type cpu_or1knd_i5_m_spr_mac_maclo_sel_type is
array (cpu_or1knd_i5_m_spr_mac_maclo_sel_index_type range
cpu_or1knd_i5_m_spr_mac_maclo_sel_index_madd downto cpu_or1knd_i5_m_spr_mac_maclo_sel_index_mtspr) of std_ulogic;
constant cpu_or1knd_i5_m_spr_mac_maclo_sel_mtspr : cpu_or1knd_i5_m_spr_mac_maclo_sel_type := "001";
constant cpu_or1knd_i5_m_spr_mac_maclo_sel_clear : cpu_or1knd_i5_m_spr_mac_maclo_sel_type := "010";
constant cpu_or1knd_i5_m_spr_mac_maclo_sel_madd : cpu_or1knd_i5_m_spr_mac_maclo_sel_type := "100";
type cpu_or1knd_i5_m_mfspr_data_sel_index_type is (
cpu_or1knd_i5_m_mfspr_data_sel_index_ctrl,
cpu_or1knd_i5_m_mfspr_data_sel_index_sys_vr,
cpu_or1knd_i5_m_mfspr_data_sel_index_sys_upr,
cpu_or1knd_i5_m_mfspr_data_sel_index_sys_cpucfgr,
cpu_or1knd_i5_m_mfspr_data_sel_index_sys_dmmucfgr,
cpu_or1knd_i5_m_mfspr_data_sel_index_sys_immucfgr,
cpu_or1knd_i5_m_mfspr_data_sel_index_sys_dccfgr,
cpu_or1knd_i5_m_mfspr_data_sel_index_sys_iccfgr,
cpu_or1knd_i5_m_mfspr_data_sel_index_sys_eear0,
cpu_or1knd_i5_m_mfspr_data_sel_index_sys_epcr0,
cpu_or1knd_i5_m_mfspr_data_sel_index_sys_gpr,
cpu_or1knd_i5_m_mfspr_data_sel_index_mac_maclo,
cpu_or1knd_i5_m_mfspr_data_sel_index_mac_machi
);
type cpu_or1knd_i5_m_mfspr_data_sel_type is
array (cpu_or1knd_i5_m_mfspr_data_sel_index_type range
cpu_or1knd_i5_m_mfspr_data_sel_index_type'high downto cpu_or1knd_i5_m_mfspr_data_sel_index_type'low) of std_ulogic;
constant cpu_or1knd_i5_m_mfspr_data_sel_ctrl : cpu_or1knd_i5_m_mfspr_data_sel_type := "0000000000001";
constant cpu_or1knd_i5_m_mfspr_data_sel_sys_vr : cpu_or1knd_i5_m_mfspr_data_sel_type := "0000000000010";
constant cpu_or1knd_i5_m_mfspr_data_sel_sys_upr : cpu_or1knd_i5_m_mfspr_data_sel_type := "0000000000100";
constant cpu_or1knd_i5_m_mfspr_data_sel_sys_cpucfgr : cpu_or1knd_i5_m_mfspr_data_sel_type := "0000000001000";
constant cpu_or1knd_i5_m_mfspr_data_sel_sys_dmmucfgr : cpu_or1knd_i5_m_mfspr_data_sel_type := "0000000010000";
constant cpu_or1knd_i5_m_mfspr_data_sel_sys_immucfgr : cpu_or1knd_i5_m_mfspr_data_sel_type := "0000000100000";
constant cpu_or1knd_i5_m_mfspr_data_sel_sys_dccfgr : cpu_or1knd_i5_m_mfspr_data_sel_type := "0000001000000";
constant cpu_or1knd_i5_m_mfspr_data_sel_sys_iccfgr : cpu_or1knd_i5_m_mfspr_data_sel_type := "0000010000000";
constant cpu_or1knd_i5_m_mfspr_data_sel_sys_eear0 : cpu_or1knd_i5_m_mfspr_data_sel_type := "0000100000000";
constant cpu_or1knd_i5_m_mfspr_data_sel_sys_epcr0 : cpu_or1knd_i5_m_mfspr_data_sel_type := "0001000000000";
constant cpu_or1knd_i5_m_mfspr_data_sel_sys_gpr : cpu_or1knd_i5_m_mfspr_data_sel_type := "0010000000000";
constant cpu_or1knd_i5_m_mfspr_data_sel_mac_maclo : cpu_or1knd_i5_m_mfspr_data_sel_type := "0100000000000";
constant cpu_or1knd_i5_m_mfspr_data_sel_mac_machi : cpu_or1knd_i5_m_mfspr_data_sel_type := "1000000000000";
type cpu_or1knd_i5_m_exception_sel_index_type is (
cpu_or1knd_i5_m_exception_sel_index_reset,
cpu_or1knd_i5_m_exception_sel_index_bus,
cpu_or1knd_i5_m_exception_sel_index_dpf,
cpu_or1knd_i5_m_exception_sel_index_ipf,
cpu_or1knd_i5_m_exception_sel_index_tti,
cpu_or1knd_i5_m_exception_sel_index_align,
cpu_or1knd_i5_m_exception_sel_index_ill,
cpu_or1knd_i5_m_exception_sel_index_ext,
cpu_or1knd_i5_m_exception_sel_index_dtlbmiss,
cpu_or1knd_i5_m_exception_sel_index_itlbmiss,
cpu_or1knd_i5_m_exception_sel_index_range,
cpu_or1knd_i5_m_exception_sel_index_syscall,
cpu_or1knd_i5_m_exception_sel_index_fp,
cpu_or1knd_i5_m_exception_sel_index_trap
);
type cpu_or1knd_i5_m_exception_sel_type is
array (cpu_or1knd_i5_m_exception_sel_index_type range
cpu_or1knd_i5_m_exception_sel_index_trap downto cpu_or1knd_i5_m_exception_sel_index_reset) of std_ulogic;
constant cpu_or1knd_i5_m_exception_sel_reset : cpu_or1knd_i5_m_exception_sel_type := "00000000000001";
constant cpu_or1knd_i5_m_exception_sel_bus : cpu_or1knd_i5_m_exception_sel_type := "00000000000010";
constant cpu_or1knd_i5_m_exception_sel_dpf : cpu_or1knd_i5_m_exception_sel_type := "00000000000100";
constant cpu_or1knd_i5_m_exception_sel_ipf : cpu_or1knd_i5_m_exception_sel_type := "00000000001000";
constant cpu_or1knd_i5_m_exception_sel_tti : cpu_or1knd_i5_m_exception_sel_type := "00000000010000";
constant cpu_or1knd_i5_m_exception_sel_align : cpu_or1knd_i5_m_exception_sel_type := "00000000100000";
constant cpu_or1knd_i5_m_exception_sel_ill : cpu_or1knd_i5_m_exception_sel_type := "00000001000000";
constant cpu_or1knd_i5_m_exception_sel_ext : cpu_or1knd_i5_m_exception_sel_type := "00000010000000";
constant cpu_or1knd_i5_m_exception_sel_dtlbmiss : cpu_or1knd_i5_m_exception_sel_type := "00000100000000";
constant cpu_or1knd_i5_m_exception_sel_itlbmiss : cpu_or1knd_i5_m_exception_sel_type := "00001000000000";
constant cpu_or1knd_i5_m_exception_sel_range : cpu_or1knd_i5_m_exception_sel_type := "00010000000000";
constant cpu_or1knd_i5_m_exception_sel_syscall : cpu_or1knd_i5_m_exception_sel_type := "00100000000000";
constant cpu_or1knd_i5_m_exception_sel_fp : cpu_or1knd_i5_m_exception_sel_type := "01000000000000";
constant cpu_or1knd_i5_m_exception_sel_trap : cpu_or1knd_i5_m_exception_sel_type := "10000000000000";
type cpu_or1knd_i5_spr_addr_sel_index_type is (
cpu_or1knd_i5_spr_addr_sel_index_sys_vr,
cpu_or1knd_i5_spr_addr_sel_index_sys_upr,
cpu_or1knd_i5_spr_addr_sel_index_sys_cpucfgr,
cpu_or1knd_i5_spr_addr_sel_index_sys_dmmucfgr,
cpu_or1knd_i5_spr_addr_sel_index_sys_immucfgr,
cpu_or1knd_i5_spr_addr_sel_index_sys_dccfgr,
cpu_or1knd_i5_spr_addr_sel_index_sys_iccfgr,
cpu_or1knd_i5_spr_addr_sel_index_sys_dcfgr,
cpu_or1knd_i5_spr_addr_sel_index_sys_pccfgr,
cpu_or1knd_i5_spr_addr_sel_index_sys_aecr,
cpu_or1knd_i5_spr_addr_sel_index_sys_aesr,
cpu_or1knd_i5_spr_addr_sel_index_sys_npc,
cpu_or1knd_i5_spr_addr_sel_index_sys_sr,
cpu_or1knd_i5_spr_addr_sel_index_sys_ppc,
cpu_or1knd_i5_spr_addr_sel_index_sys_fpcsr,
cpu_or1knd_i5_spr_addr_sel_index_sys_epcr0,
cpu_or1knd_i5_spr_addr_sel_index_sys_eear0,
cpu_or1knd_i5_spr_addr_sel_index_sys_esr0,
cpu_or1knd_i5_spr_addr_sel_index_sys_gpr,
cpu_or1knd_i5_spr_addr_sel_index_dmmu_dmmucr,
cpu_or1knd_i5_spr_addr_sel_index_dmmu_dmmupr,
cpu_or1knd_i5_spr_addr_sel_index_dmmu_dtlbeir,
cpu_or1knd_i5_spr_addr_sel_index_dmmu_datbmr,
cpu_or1knd_i5_spr_addr_sel_index_dmmu_datbtr,
cpu_or1knd_i5_spr_addr_sel_index_dmmu_dtlbwmr,
cpu_or1knd_i5_spr_addr_sel_index_dmmu_dtlbwtr,
cpu_or1knd_i5_spr_addr_sel_index_immu_immucr,
cpu_or1knd_i5_spr_addr_sel_index_immu_immupr,
cpu_or1knd_i5_spr_addr_sel_index_immu_itlbeir,
cpu_or1knd_i5_spr_addr_sel_index_immu_iatbmr,
cpu_or1knd_i5_spr_addr_sel_index_immu_iatbtr,
cpu_or1knd_i5_spr_addr_sel_index_immu_itlbwmr,
cpu_or1knd_i5_spr_addr_sel_index_immu_itlbwtr,
cpu_or1knd_i5_spr_addr_sel_index_dcache_dcbfr,
cpu_or1knd_i5_spr_addr_sel_index_dcache_dcbir,
cpu_or1knd_i5_spr_addr_sel_index_dcache_dcbwr,
cpu_or1knd_i5_spr_addr_sel_index_icache_icbir,
cpu_or1knd_i5_spr_addr_sel_index_mac_maclo,
cpu_or1knd_i5_spr_addr_sel_index_mac_machi
);
type cpu_or1knd_i5_spr_addr_sel_type is
array (cpu_or1knd_i5_spr_addr_sel_index_type range
cpu_or1knd_i5_spr_addr_sel_index_type'high downto cpu_or1knd_i5_spr_addr_sel_index_type'low) of std_ulogic;
constant cpu_or1knd_i5_spr_addr_sel_sys_vr : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_sys_vr => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_sys_upr : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_sys_upr => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_sys_cpucfgr : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_sys_cpucfgr => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_sys_dmmucfgr : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_sys_dmmucfgr => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_sys_immucfgr : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_sys_immucfgr => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_sys_dccfgr : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_sys_dccfgr => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_sys_iccfgr : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_sys_iccfgr => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_sys_dcfgr : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_sys_dcfgr => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_sys_pccfgr : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_sys_pccfgr => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_sys_aecr : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_sys_aecr => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_sys_aesr : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_sys_aesr => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_sys_npc : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_sys_npc => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_sys_sr : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_sys_sr => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_sys_ppc : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_sys_ppc => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_sys_fpcsr : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_sys_fpcsr => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_sys_epcr0 : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_sys_epcr0 => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_sys_eear0 : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_sys_eear0 => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_sys_esr0 : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_sys_esr0 => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_sys_gpr : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_sys_gpr => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_dmmu_dmmucr : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_dmmu_dmmucr => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_dmmu_dmmupr : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_dmmu_dmmupr => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_dmmu_dtlbeir : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_dmmu_dtlbeir => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_dmmu_datbmr : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_dmmu_datbmr => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_dmmu_datbtr : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_dmmu_datbtr => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_dmmu_dtlbwmr : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_dmmu_dtlbwmr => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_dmmu_dtlbwtr : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_dmmu_dtlbwtr => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_immu_immucr : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_immu_immucr => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_immu_immupr : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_immu_immupr => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_immu_itlbeir : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_immu_itlbeir => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_immu_iatbmr : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_immu_iatbmr => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_immu_iatbtr : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_immu_iatbtr => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_immu_itlbwmr : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_immu_itlbwmr => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_immu_itlbwtr : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_immu_itlbwtr => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_dcache_dcbfr : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_dcache_dcbfr => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_dcache_dcbir : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_dcache_dcbir => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_dcache_dcbwr : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_dcache_dcbwr => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_icache_icbir : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_icache_icbir => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_mac_maclo : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_mac_maclo => '1', others => '0');
constant cpu_or1knd_i5_spr_addr_sel_mac_machi : cpu_or1knd_i5_spr_addr_sel_type := (cpu_or1knd_i5_spr_addr_sel_index_mac_machi => '1', others => '0');
type cpu_or1knd_i5_regfile_raddr1_sel_index_type is (
cpu_or1knd_i5_regfile_raddr1_sel_index_f_ra,
cpu_or1knd_i5_regfile_raddr1_sel_index_d_ra,
cpu_or1knd_i5_regfile_raddr1_sel_index_m_mfspr_sys_gpr
);
type cpu_or1knd_i5_regfile_raddr1_sel_type is
array (cpu_or1knd_i5_regfile_raddr1_sel_index_type range
cpu_or1knd_i5_regfile_raddr1_sel_index_m_mfspr_sys_gpr downto cpu_or1knd_i5_regfile_raddr1_sel_index_f_ra) of std_ulogic;
constant cpu_or1knd_i5_regfile_raddr1_sel_f_ra : cpu_or1knd_i5_regfile_raddr1_sel_type := "001";
constant cpu_or1knd_i5_regfile_raddr1_sel_d_ra : cpu_or1knd_i5_regfile_raddr1_sel_type := "010";
constant cpu_or1knd_i5_regfile_raddr1_sel_m_mfspr_sys_gpr : cpu_or1knd_i5_regfile_raddr1_sel_type := "100";
type cpu_or1knd_i5_regfile_raddr2_sel_index_type is (
cpu_or1knd_i5_regfile_raddr2_sel_index_f_rb,
cpu_or1knd_i5_regfile_raddr2_sel_index_d_rb
);
type cpu_or1knd_i5_regfile_raddr2_sel_type is
array (cpu_or1knd_i5_regfile_raddr2_sel_index_type range
cpu_or1knd_i5_regfile_raddr2_sel_index_d_rb downto cpu_or1knd_i5_regfile_raddr2_sel_index_f_rb) of std_ulogic;
constant cpu_or1knd_i5_regfile_raddr2_sel_f_rb : cpu_or1knd_i5_regfile_raddr2_sel_type := "01";
constant cpu_or1knd_i5_regfile_raddr2_sel_d_rb : cpu_or1knd_i5_regfile_raddr2_sel_type := "10";
type cpu_or1knd_i5_regfile_w_sel_index_type is (
cpu_or1knd_i5_regfile_w_sel_index_m_rd,
cpu_or1knd_i5_regfile_w_sel_index_m_mtspr_sys_gpr
);
type cpu_or1knd_i5_regfile_w_sel_type is
array (cpu_or1knd_i5_regfile_w_sel_index_type range
cpu_or1knd_i5_regfile_w_sel_index_type'high downto
cpu_or1knd_i5_regfile_w_sel_index_type'low) of std_ulogic;
constant cpu_or1knd_i5_regfile_w_sel_m_rd : cpu_or1knd_i5_regfile_w_sel_type := "01";
constant cpu_or1knd_i5_regfile_w_sel_m_mtspr_sys_gpr : cpu_or1knd_i5_regfile_w_sel_type := "10";
type cpu_or1knd_i5_data_size_sel_index_type is (
cpu_or1knd_i5_data_size_sel_index_byte,
cpu_or1knd_i5_data_size_sel_index_half,
cpu_or1knd_i5_data_size_sel_index_word
);
type cpu_or1knd_i5_data_size_sel_type is
array (cpu_or1knd_i5_data_size_sel_index_type range
cpu_or1knd_i5_data_size_sel_index_type'high downto
cpu_or1knd_i5_data_size_sel_index_type'low) of std_ulogic;
constant cpu_or1knd_i5_data_size_sel_byte : cpu_or1knd_i5_data_size_sel_type := "001";
constant cpu_or1knd_i5_data_size_sel_half : cpu_or1knd_i5_data_size_sel_type := "010";
constant cpu_or1knd_i5_data_size_sel_word : cpu_or1knd_i5_data_size_sel_type := "100";
type cpu_or1knd_i5_l1mem_inst_vaddr_sel_index_type is (
cpu_or1knd_i5_l1mem_inst_vaddr_sel_index_bf_pc,
cpu_or1knd_i5_l1mem_inst_vaddr_sel_index_m_mtspr_data
);
type cpu_or1knd_i5_l1mem_inst_vaddr_sel_type is
array (cpu_or1knd_i5_l1mem_inst_vaddr_sel_index_type range
cpu_or1knd_i5_l1mem_inst_vaddr_sel_index_type'high downto
cpu_or1knd_i5_l1mem_inst_vaddr_sel_index_type'low) of std_ulogic;
constant cpu_or1knd_i5_l1mem_inst_vaddr_sel_bf_pc : cpu_or1knd_i5_l1mem_inst_vaddr_sel_type := "01";
constant cpu_or1knd_i5_l1mem_inst_vaddr_sel_m_mtspr_data : cpu_or1knd_i5_l1mem_inst_vaddr_sel_type := "10";
type cpu_or1knd_i5_l1mem_data_vaddr_sel_index_type is (
cpu_or1knd_i5_l1mem_data_vaddr_sel_index_e_ldst_addr,
cpu_or1knd_i5_l1mem_data_vaddr_sel_index_m_mtspr_data
);
type cpu_or1knd_i5_l1mem_data_vaddr_sel_type is
array (cpu_or1knd_i5_l1mem_data_vaddr_sel_index_type range
cpu_or1knd_i5_l1mem_data_vaddr_sel_index_type'high downto
cpu_or1knd_i5_l1mem_data_vaddr_sel_index_type'low) of std_ulogic;
constant cpu_or1knd_i5_l1mem_data_vaddr_sel_e_ldst_addr : cpu_or1knd_i5_l1mem_data_vaddr_sel_type := "01";
constant cpu_or1knd_i5_l1mem_data_vaddr_sel_m_mtspr_data : cpu_or1knd_i5_l1mem_data_vaddr_sel_type := "10";
type cpu_or1knd_i5_pipe_dp_in_ctrl_type is record
fd_stall : std_ulogic;
emw_stall : std_ulogic;
bf_pc_sel : cpu_or1knd_i5_bf_pc_sel_type;
f_bpred_buffer_write : std_ulogic;
f_bpred_buffered : std_ulogic;
f_inst_buffer_write : std_ulogic;
f_inst_buffered : std_ulogic;
d_rd_link : std_ulogic;
d_imm_sel : cpu_or1knd_i5_imm_sel_type;
d_imm_sext : std_ulogic;
d_alu_src1_sel : cpu_or1knd_i5_alu_src1_sel_type;
d_alu_src2_sel : cpu_or1knd_i5_alu_src2_sel_type;
e_sext : std_ulogic;
e_data_size_sel : cpu_or1knd_i5_data_size_sel_type;
e_fwd_alu_src1_sel : cpu_or1knd_i5_e_fwd_alu_src_sel_type;
e_fwd_alu_src2_sel : cpu_or1knd_i5_e_fwd_alu_src_sel_type;
e_fwd_st_data_sel : cpu_or1knd_i5_e_fwd_st_data_sel_type;
e_spr_sys_sr_f : std_ulogic;
e_alu_result_sel : cpu_or1knd_i5_alu_result_sel_type;
e_toc_indir : std_ulogic;
e_madd_acc_zero : std_ulogic;
e_addr_sel : cpu_or1knd_i5_e_addr_sel_type;
m_exception_sel : cpu_or1knd_i5_m_exception_sel_type;
m_mfspr_data : or1k_word_type;
m_mfspr_data_sel : cpu_or1knd_i5_m_mfspr_data_sel_type;
m_sext : std_ulogic;
m_rd_data_sel : cpu_or1knd_i5_rd_data_sel_type;
m_data_size_sel : cpu_or1knd_i5_data_size_sel_type;
m_load_buffer_write : std_ulogic;
m_load_data_buffered : std_ulogic;
m_spr_sys_eear0_write : std_ulogic;
m_spr_sys_eear0_sel : cpu_or1knd_i5_m_spr_sys_eear0_sel_type;
m_spr_sys_epcr0_write : std_ulogic;
m_spr_sys_epcr0_sel : cpu_or1knd_i5_m_spr_sys_epcr0_sel_type;
m_spr_mac_machi_write : std_ulogic;
m_spr_mac_machi_sel : cpu_or1knd_i5_m_spr_mac_machi_sel_type;
m_spr_mac_maclo_write : std_ulogic;
m_spr_mac_maclo_sel : cpu_or1knd_i5_m_spr_mac_maclo_sel_type;
p_spr_sys_sr_eph : std_ulogic;
regfile_raddr1_sel : cpu_or1knd_i5_regfile_raddr1_sel_type;
regfile_raddr2_sel : cpu_or1knd_i5_regfile_raddr2_sel_type;
regfile_w_sel : cpu_or1knd_i5_regfile_w_sel_type;
l1mem_inst_vaddr_sel : cpu_or1knd_i5_l1mem_inst_vaddr_sel_type;
l1mem_data_vaddr_sel : cpu_or1knd_i5_l1mem_data_vaddr_sel_type;
end record;
type cpu_or1knd_i5_pipe_dp_out_ctrl_type is record
f_inst : or1k_inst_type;
d_depends_ra_e : std_ulogic;
d_depends_rb_e : std_ulogic;
d_depends_ra_m : std_ulogic;
d_depends_rb_m : std_ulogic;
e_not_equal : std_ulogic;
e_lts : std_ulogic;
e_ltu : std_ulogic;
e_ldst_misaligned : std_ulogic;
e_spr_addr_sel : cpu_or1knd_i5_spr_addr_sel_type;
e_spr_addr_valid : std_ulogic;
e_toc_target_misaligned : std_ulogic;
e_btb_mispred : std_ulogic;
m_mtspr_data : or1k_word_type;
m_madd_result_hi_zeros : std_ulogic;
m_madd_result_hi_ones : std_ulogic;
m_mul_result_msb : std_ulogic;
end record;
type cpu_or1knd_i5_pipe_ctrl_out_misc_type is record
e_addsub_sub : std_ulogic;
e_addsub_carryin : std_ulogic;
e_shifter_right : std_ulogic;
e_shifter_rot : std_ulogic;
e_shifter_unsgnd : std_ulogic;
e_mul_en : std_ulogic;
e_mul_unsgnd : std_ulogic;
e_madd_sub : std_ulogic;
e_div_en : std_ulogic;
e_div_unsgnd : std_ulogic;
regfile_we : std_ulogic;
regfile_re1 : std_ulogic;
regfile_re2 : std_ulogic;
end record;
type cpu_or1knd_i5_pipe_ctrl_in_misc_type is record
e_addsub_carryout : std_ulogic;
e_addsub_overflow : std_ulogic;
m_mul_valid : std_ulogic;
m_mul_overflow : std_ulogic;
m_madd_overflow : std_ulogic;
m_div_valid : std_ulogic;
m_div_dbz : std_ulogic;
m_div_overflow : std_ulogic;
end record;
type cpu_or1knd_i5_pipe_dp_out_misc_type is record
e_alu_src1 : std_ulogic_vector(or1k_word_bits-1 downto 0);
e_alu_src2 : std_ulogic_vector(or1k_word_bits-1 downto 0);
e_madd_acc : std_ulogic_vector(2*or1k_word_bits-1 downto 0);
regfile_waddr : or1k_rfaddr_type;
regfile_wdata : or1k_word_type;
regfile_raddr1 : or1k_rfaddr_type;
regfile_raddr2 : or1k_rfaddr_type;
end record;
type cpu_or1knd_i5_pipe_dp_in_misc_type is record
e_addsub_result : std_ulogic_vector(or1k_word_bits-1 downto 0);
e_shifter_result : std_ulogic_vector(or1k_word_bits-1 downto 0);
m_madd_result_hi : std_ulogic_vector(or1k_word_bits-1 downto 0);
m_mul_result : std_ulogic_vector(or1k_word_bits-1 downto 0);
m_div_result : std_ulogic_vector(or1k_word_bits-1 downto 0);
regfile_rdata1 : or1k_word_type;
regfile_rdata2 : or1k_word_type;
end record;
end package;
| apache-2.0 | d005a26ee5137219e9aa79dd4e83cbbb | 0.671867 | 2.319316 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_xlconstant_0_1/system_xlconstant_0_1_sim_netlist.vhdl | 1 | 2,489 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon May 29 22:11:05 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_xlconstant_0_1/system_xlconstant_0_1_sim_netlist.vhdl
-- Design : system_xlconstant_0_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xlconstant_0_1 is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_xlconstant_0_1 : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_xlconstant_0_1 : entity is "yes";
end system_xlconstant_0_1;
architecture STRUCTURE of system_xlconstant_0_1 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
dout(31) <= \<const0>\;
dout(30) <= \<const0>\;
dout(29) <= \<const0>\;
dout(28) <= \<const0>\;
dout(27) <= \<const0>\;
dout(26) <= \<const0>\;
dout(25) <= \<const0>\;
dout(24) <= \<const0>\;
dout(23) <= \<const0>\;
dout(22) <= \<const0>\;
dout(21) <= \<const0>\;
dout(20) <= \<const0>\;
dout(19) <= \<const0>\;
dout(18) <= \<const0>\;
dout(17) <= \<const0>\;
dout(16) <= \<const0>\;
dout(15) <= \<const0>\;
dout(14) <= \<const0>\;
dout(13) <= \<const1>\;
dout(12) <= \<const0>\;
dout(11) <= \<const0>\;
dout(10) <= \<const1>\;
dout(9) <= \<const1>\;
dout(8) <= \<const1>\;
dout(7) <= \<const0>\;
dout(6) <= \<const0>\;
dout(5) <= \<const0>\;
dout(4) <= \<const1>\;
dout(3) <= \<const0>\;
dout(2) <= \<const0>\;
dout(1) <= \<const0>\;
dout(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
| mit | 4ead08284dec53483ad10edc2b7b37c1 | 0.574528 | 3.409589 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_auto_pc_1/system_auto_pc_1_sim_netlist.vhdl | 1 | 770,799 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed May 31 20:12:37 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_auto_pc_1/system_auto_pc_1_sim_netlist.vhdl
-- Design : system_auto_pc_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_axi_protocol_converter_v2_1_11_b_downsizer is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
wr_cmd_b_ready : out STD_LOGIC;
\S_AXI_BRESP_ACC_reg[0]_0\ : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
dout : in STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
empty : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_axi_protocol_converter_v2_1_11_b_downsizer : entity is "axi_protocol_converter_v2_1_11_b_downsizer";
end system_auto_pc_1_axi_protocol_converter_v2_1_11_b_downsizer;
architecture STRUCTURE of system_auto_pc_1_axi_protocol_converter_v2_1_11_b_downsizer is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal S_AXI_BRESP_ACC : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_bresp_acc_reg[0]_0\ : STD_LOGIC;
signal first_mi_word : STD_LOGIC;
signal last_word : STD_LOGIC;
signal next_repeat_cnt : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \repeat_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \repeat_cnt[2]_i_2_n_0\ : STD_LOGIC;
signal \repeat_cnt[3]_i_2_n_0\ : STD_LOGIC;
signal \repeat_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_bresp\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of fifo_gen_inst_i_3 : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \repeat_cnt[0]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \repeat_cnt[1]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \repeat_cnt[2]_i_2\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \repeat_cnt[3]_i_2\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of s_axi_bvalid_INST_0 : label is "soft_lutpair26";
begin
E(0) <= \^e\(0);
\S_AXI_BRESP_ACC_reg[0]_0\ <= \^s_axi_bresp_acc_reg[0]_0\;
s_axi_bresp(1 downto 0) <= \^s_axi_bresp\(1 downto 0);
\S_AXI_BRESP_ACC_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \^s_axi_bresp\(0),
Q => S_AXI_BRESP_ACC(0),
R => SR(0)
);
\S_AXI_BRESP_ACC_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \^s_axi_bresp\(1),
Q => S_AXI_BRESP_ACC(1),
R => SR(0)
);
fifo_gen_inst_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => \^s_axi_bresp_acc_reg[0]_0\,
I1 => m_axi_bvalid,
I2 => s_axi_bready,
I3 => empty,
O => wr_cmd_b_ready
);
first_mi_word_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000001FFFFFFFF"
)
port map (
I0 => \repeat_cnt_reg__0\(1),
I1 => first_mi_word,
I2 => \repeat_cnt_reg__0\(3),
I3 => \repeat_cnt_reg__0\(0),
I4 => \repeat_cnt_reg__0\(2),
I5 => dout(4),
O => last_word
);
first_mi_word_reg: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => \^e\(0),
D => last_word,
Q => first_mi_word,
S => SR(0)
);
m_axi_bready_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => m_axi_bvalid,
I1 => \^s_axi_bresp_acc_reg[0]_0\,
I2 => s_axi_bready,
O => \^e\(0)
);
\repeat_cnt[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \repeat_cnt_reg__0\(0),
I1 => first_mi_word,
I2 => dout(0),
O => next_repeat_cnt(0)
);
\repeat_cnt[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCA533A5"
)
port map (
I0 => \repeat_cnt_reg__0\(1),
I1 => dout(1),
I2 => \repeat_cnt_reg__0\(0),
I3 => first_mi_word,
I4 => dout(0),
O => \repeat_cnt[1]_i_1_n_0\
);
\repeat_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEFA051111FA05"
)
port map (
I0 => \repeat_cnt[2]_i_2_n_0\,
I1 => dout(1),
I2 => \repeat_cnt_reg__0\(1),
I3 => \repeat_cnt_reg__0\(2),
I4 => first_mi_word,
I5 => dout(2),
O => next_repeat_cnt(2)
);
\repeat_cnt[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => dout(0),
I1 => first_mi_word,
I2 => \repeat_cnt_reg__0\(0),
O => \repeat_cnt[2]_i_2_n_0\
);
\repeat_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFAFCF305050CF30"
)
port map (
I0 => dout(2),
I1 => \repeat_cnt_reg__0\(2),
I2 => \repeat_cnt[3]_i_2_n_0\,
I3 => \repeat_cnt_reg__0\(3),
I4 => first_mi_word,
I5 => dout(3),
O => next_repeat_cnt(3)
);
\repeat_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => \repeat_cnt_reg__0\(1),
I1 => dout(1),
I2 => \repeat_cnt_reg__0\(0),
I3 => first_mi_word,
I4 => dout(0),
O => \repeat_cnt[3]_i_2_n_0\
);
\repeat_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => next_repeat_cnt(0),
Q => \repeat_cnt_reg__0\(0),
R => SR(0)
);
\repeat_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \repeat_cnt[1]_i_1_n_0\,
Q => \repeat_cnt_reg__0\(1),
R => SR(0)
);
\repeat_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => next_repeat_cnt(2),
Q => \repeat_cnt_reg__0\(2),
R => SR(0)
);
\repeat_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => next_repeat_cnt(3),
Q => \repeat_cnt_reg__0\(3),
R => SR(0)
);
\s_axi_bresp[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF00B0FFDF0000"
)
port map (
I0 => S_AXI_BRESP_ACC(1),
I1 => m_axi_bresp(1),
I2 => dout(4),
I3 => first_mi_word,
I4 => m_axi_bresp(0),
I5 => S_AXI_BRESP_ACC(0),
O => \^s_axi_bresp\(0)
);
\s_axi_bresp[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCEC"
)
port map (
I0 => S_AXI_BRESP_ACC(1),
I1 => m_axi_bresp(1),
I2 => dout(4),
I3 => first_mi_word,
O => \^s_axi_bresp\(1)
);
s_axi_bvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => m_axi_bvalid,
I1 => \^s_axi_bresp_acc_reg[0]_0\,
O => s_axi_bvalid
);
s_axi_bvalid_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA8"
)
port map (
I0 => dout(4),
I1 => \repeat_cnt_reg__0\(2),
I2 => \repeat_cnt_reg__0\(0),
I3 => \repeat_cnt_reg__0\(3),
I4 => first_mi_word,
I5 => \repeat_cnt_reg__0\(1),
O => \^s_axi_bresp_acc_reg[0]_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_axi_protocol_converter_v2_1_11_w_axi3_conv is
port (
\length_counter_1_reg[1]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
first_mi_word : out STD_LOGIC;
wr_cmd_ready : out STD_LOGIC;
m_axi_wlast : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
\goreg_dm.dout_i_reg[0]\ : in STD_LOGIC;
empty_fwft_i_reg : in STD_LOGIC;
dout : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
empty : in STD_LOGIC;
m_axi_wready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_axi_protocol_converter_v2_1_11_w_axi3_conv : entity is "axi_protocol_converter_v2_1_11_w_axi3_conv";
end system_auto_pc_1_axi_protocol_converter_v2_1_11_w_axi3_conv;
architecture STRUCTURE of system_auto_pc_1_axi_protocol_converter_v2_1_11_w_axi3_conv is
signal \fifo_gen_inst_i_3__0_n_0\ : STD_LOGIC;
signal \^first_mi_word\ : STD_LOGIC;
signal \first_mi_word_i_1__0_n_0\ : STD_LOGIC;
signal \length_counter_1[1]_i_1_n_0\ : STD_LOGIC;
signal \length_counter_1[2]_i_1_n_0\ : STD_LOGIC;
signal \length_counter_1[3]_i_1_n_0\ : STD_LOGIC;
signal \length_counter_1[3]_i_2_n_0\ : STD_LOGIC;
signal \length_counter_1[4]_i_1_n_0\ : STD_LOGIC;
signal \length_counter_1[4]_i_2_n_0\ : STD_LOGIC;
signal \length_counter_1[5]_i_1_n_0\ : STD_LOGIC;
signal \length_counter_1[6]_i_1_n_0\ : STD_LOGIC;
signal \length_counter_1[7]_i_1_n_0\ : STD_LOGIC;
signal \length_counter_1[7]_i_2_n_0\ : STD_LOGIC;
signal length_counter_1_reg : STD_LOGIC_VECTOR ( 7 downto 1 );
signal \^length_counter_1_reg[1]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_axi_wlast\ : STD_LOGIC;
signal m_axi_wlast_INST_0_i_1_n_0 : STD_LOGIC;
signal m_axi_wlast_INST_0_i_2_n_0 : STD_LOGIC;
signal m_axi_wlast_INST_0_i_3_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \fifo_gen_inst_i_3__0\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \length_counter_1[2]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \length_counter_1[3]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \length_counter_1[3]_i_2\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \length_counter_1[4]_i_2\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of m_axi_wlast_INST_0_i_1 : label is "soft_lutpair64";
begin
first_mi_word <= \^first_mi_word\;
\length_counter_1_reg[1]_0\(0) <= \^length_counter_1_reg[1]_0\(0);
m_axi_wlast <= \^m_axi_wlast\;
\fifo_gen_inst_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => empty_fwft_i_reg,
I1 => m_axi_wlast_INST_0_i_3_n_0,
I2 => \fifo_gen_inst_i_3__0_n_0\,
I3 => m_axi_wlast_INST_0_i_2_n_0,
I4 => m_axi_wlast_INST_0_i_1_n_0,
O => wr_cmd_ready
);
\fifo_gen_inst_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"35"
)
port map (
I0 => length_counter_1_reg(2),
I1 => dout(2),
I2 => \^first_mi_word\,
O => \fifo_gen_inst_i_3__0_n_0\
);
\first_mi_word_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FBFF0800"
)
port map (
I0 => \^m_axi_wlast\,
I1 => m_axi_wready,
I2 => empty,
I3 => s_axi_wvalid,
I4 => \^first_mi_word\,
O => \first_mi_word_i_1__0_n_0\
);
first_mi_word_reg: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \first_mi_word_i_1__0_n_0\,
Q => \^first_mi_word\,
S => SR(0)
);
\length_counter_1[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E2AA2EAAE2662E66"
)
port map (
I0 => length_counter_1_reg(1),
I1 => empty_fwft_i_reg,
I2 => dout(1),
I3 => \^first_mi_word\,
I4 => dout(0),
I5 => \^length_counter_1_reg[1]_0\(0),
O => \length_counter_1[1]_i_1_n_0\
);
\length_counter_1[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"4E66E4CC"
)
port map (
I0 => empty_fwft_i_reg,
I1 => length_counter_1_reg(2),
I2 => dout(2),
I3 => \^first_mi_word\,
I4 => m_axi_wlast_INST_0_i_2_n_0,
O => \length_counter_1[2]_i_1_n_0\
);
\length_counter_1[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"E22EA6A6"
)
port map (
I0 => length_counter_1_reg(3),
I1 => empty_fwft_i_reg,
I2 => \length_counter_1[3]_i_2_n_0\,
I3 => dout(3),
I4 => \^first_mi_word\,
O => \length_counter_1[3]_i_1_n_0\
);
\length_counter_1[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F7D5"
)
port map (
I0 => m_axi_wlast_INST_0_i_2_n_0,
I1 => \^first_mi_word\,
I2 => dout(2),
I3 => length_counter_1_reg(2),
O => \length_counter_1[3]_i_2_n_0\
);
\length_counter_1[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"59555555AAAAAAAA"
)
port map (
I0 => \length_counter_1[4]_i_2_n_0\,
I1 => s_axi_wvalid,
I2 => empty,
I3 => m_axi_wready,
I4 => \^first_mi_word\,
I5 => length_counter_1_reg(4),
O => \length_counter_1[4]_i_1_n_0\
);
\length_counter_1[4]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000202A"
)
port map (
I0 => empty_fwft_i_reg,
I1 => dout(3),
I2 => \^first_mi_word\,
I3 => length_counter_1_reg(3),
I4 => \length_counter_1[3]_i_2_n_0\,
O => \length_counter_1[4]_i_2_n_0\
);
\length_counter_1[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E6E6A6E6E6E6E6E6"
)
port map (
I0 => \length_counter_1[7]_i_2_n_0\,
I1 => length_counter_1_reg(5),
I2 => \^first_mi_word\,
I3 => m_axi_wready,
I4 => empty,
I5 => s_axi_wvalid,
O => \length_counter_1[5]_i_1_n_0\
);
\length_counter_1[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FC70CF70"
)
port map (
I0 => empty_fwft_i_reg,
I1 => \^first_mi_word\,
I2 => length_counter_1_reg(6),
I3 => \length_counter_1[7]_i_2_n_0\,
I4 => length_counter_1_reg(5),
O => \length_counter_1[6]_i_1_n_0\
);
\length_counter_1[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB9888AFFFD888A"
)
port map (
I0 => \length_counter_1[7]_i_2_n_0\,
I1 => \^first_mi_word\,
I2 => length_counter_1_reg(6),
I3 => length_counter_1_reg(5),
I4 => length_counter_1_reg(7),
I5 => empty_fwft_i_reg,
O => \length_counter_1[7]_i_1_n_0\
);
\length_counter_1[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000500000105010"
)
port map (
I0 => \length_counter_1[3]_i_2_n_0\,
I1 => length_counter_1_reg(3),
I2 => empty_fwft_i_reg,
I3 => \^first_mi_word\,
I4 => dout(3),
I5 => length_counter_1_reg(4),
O => \length_counter_1[7]_i_2_n_0\
);
\length_counter_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \goreg_dm.dout_i_reg[0]\,
Q => \^length_counter_1_reg[1]_0\(0),
R => SR(0)
);
\length_counter_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \length_counter_1[1]_i_1_n_0\,
Q => length_counter_1_reg(1),
R => SR(0)
);
\length_counter_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \length_counter_1[2]_i_1_n_0\,
Q => length_counter_1_reg(2),
R => SR(0)
);
\length_counter_1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \length_counter_1[3]_i_1_n_0\,
Q => length_counter_1_reg(3),
R => SR(0)
);
\length_counter_1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \length_counter_1[4]_i_1_n_0\,
Q => length_counter_1_reg(4),
R => SR(0)
);
\length_counter_1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \length_counter_1[5]_i_1_n_0\,
Q => length_counter_1_reg(5),
R => SR(0)
);
\length_counter_1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \length_counter_1[6]_i_1_n_0\,
Q => length_counter_1_reg(6),
R => SR(0)
);
\length_counter_1_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \length_counter_1[7]_i_1_n_0\,
Q => length_counter_1_reg(7),
R => SR(0)
);
m_axi_wlast_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000800888"
)
port map (
I0 => m_axi_wlast_INST_0_i_1_n_0,
I1 => m_axi_wlast_INST_0_i_2_n_0,
I2 => \^first_mi_word\,
I3 => dout(2),
I4 => length_counter_1_reg(2),
I5 => m_axi_wlast_INST_0_i_3_n_0,
O => \^m_axi_wlast\
);
m_axi_wlast_INST_0_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => dout(3),
I1 => \^first_mi_word\,
I2 => length_counter_1_reg(3),
O => m_axi_wlast_INST_0_i_1_n_0
);
m_axi_wlast_INST_0_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => \^length_counter_1_reg[1]_0\(0),
I1 => dout(0),
I2 => length_counter_1_reg(1),
I3 => \^first_mi_word\,
I4 => dout(1),
O => m_axi_wlast_INST_0_i_2_n_0
);
m_axi_wlast_INST_0_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"55555554"
)
port map (
I0 => \^first_mi_word\,
I1 => length_counter_1_reg(5),
I2 => length_counter_1_reg(4),
I3 => length_counter_1_reg(7),
I4 => length_counter_1_reg(6),
O => m_axi_wlast_INST_0_i_3_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_dmem is
port (
dout_i : out STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
EN : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 5 downto 0 );
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
I54 : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_dmem : entity is "dmem";
end system_auto_pc_1_dmem;
architecture STRUCTURE of system_auto_pc_1_dmem is
signal p_0_out : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_RAM_reg_0_31_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_31_0_5 : label is "";
begin
RAM_reg_0_31_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => I54(4 downto 0),
DIA(1 downto 0) => din(1 downto 0),
DIB(1 downto 0) => din(3 downto 2),
DIC(1 downto 0) => din(5 downto 4),
DID(1 downto 0) => B"00",
DOA(1 downto 0) => p_0_out(1 downto 0),
DOB(1 downto 0) => p_0_out(3 downto 2),
DOC(1 downto 0) => p_0_out(5 downto 4),
DOD(1 downto 0) => NLW_RAM_reg_0_31_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => EN
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => p_0_out(0),
Q => dout_i(0),
R => '0'
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => p_0_out(1),
Q => dout_i(1),
R => '0'
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => p_0_out(2),
Q => dout_i(2),
R => '0'
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => p_0_out(3),
Q => dout_i(3),
R => '0'
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => p_0_out(4),
Q => dout_i(4),
R => '0'
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => p_0_out(5),
Q => dout_i(5),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_dmem__parameterized0\ is
port (
dout_i : out STD_LOGIC_VECTOR ( 4 downto 0 );
clk : in STD_LOGIC;
EN : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
I55 : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_dmem__parameterized0\ : entity is "dmem";
end \system_auto_pc_1_dmem__parameterized0\;
architecture STRUCTURE of \system_auto_pc_1_dmem__parameterized0\ is
signal p_0_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_RAM_reg_0_31_0_4_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_RAM_reg_0_31_0_4_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_31_0_4 : label is "";
begin
RAM_reg_0_31_0_4: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => I55(4 downto 0),
DIA(1 downto 0) => din(1 downto 0),
DIB(1 downto 0) => din(3 downto 2),
DIC(1) => '0',
DIC(0) => din(4),
DID(1 downto 0) => B"00",
DOA(1 downto 0) => p_0_out(1 downto 0),
DOB(1 downto 0) => p_0_out(3 downto 2),
DOC(1) => NLW_RAM_reg_0_31_0_4_DOC_UNCONNECTED(1),
DOC(0) => p_0_out(4),
DOD(1 downto 0) => NLW_RAM_reg_0_31_0_4_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => EN
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => p_0_out(0),
Q => dout_i(0),
R => '0'
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => p_0_out(1),
Q => dout_i(1),
R => '0'
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => p_0_out(2),
Q => dout_i(2),
R => '0'
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => p_0_out(3),
Q => dout_i(3),
R => '0'
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => p_0_out(4),
Q => dout_i(4),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_dmem__parameterized1\ is
port (
p_0_out : out STD_LOGIC;
dout_i : out STD_LOGIC;
\goreg_dm.dout_i_reg[0]\ : out STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gpregsm1.curr_fwft_state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
dout : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_dmem__parameterized1\ : entity is "dmem";
end \system_auto_pc_1_dmem__parameterized1\;
architecture STRUCTURE of \system_auto_pc_1_dmem__parameterized1\ is
signal \^dout_i\ : STD_LOGIC;
signal NLW_RAM_reg_0_31_0_0_SPO_UNCONNECTED : STD_LOGIC;
begin
dout_i <= \^dout_i\;
RAM_reg_0_31_0_0: unisim.vcomponents.RAM32X1D
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
A4 => Q(4),
D => din(0),
DPO => p_0_out,
DPRA0 => \gc0.count_d1_reg[4]\(0),
DPRA1 => \gc0.count_d1_reg[4]\(1),
DPRA2 => \gc0.count_d1_reg[4]\(2),
DPRA3 => \gc0.count_d1_reg[4]\(3),
DPRA4 => \gc0.count_d1_reg[4]\(4),
SPO => NLW_RAM_reg_0_31_0_0_SPO_UNCONNECTED,
WCLK => clk,
WE => E(0)
);
\goreg_dm.dout_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFEFFFEF20200020"
)
port map (
I0 => \^dout_i\,
I1 => \out\(0),
I2 => \gpregsm1.curr_fwft_state_reg[1]_0\(1),
I3 => \gpregsm1.curr_fwft_state_reg[1]_0\(0),
I4 => rd_en,
I5 => dout(0),
O => \goreg_dm.dout_i_reg[0]\
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \gpregsm1.curr_fwft_state_reg[1]\,
Q => \^dout_i\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
ram_empty_fb_i_reg_0 : out STD_LOGIC;
\gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
\out\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_rd_bin_cntr : entity is "rd_bin_cntr";
end system_auto_pc_1_rd_bin_cntr;
architecture STRUCTURE of system_auto_pc_1_rd_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^gpr1.dout_i_reg[1]\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ram_empty_fb_i_i_2_n_0 : STD_LOGIC;
signal ram_empty_fb_i_i_6_n_0 : STD_LOGIC;
signal \^ram_empty_fb_i_reg_0\ : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 4 downto 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair33";
begin
Q(2 downto 0) <= \^q\(2 downto 0);
\gpr1.dout_i_reg[1]\(4 downto 0) <= \^gpr1.dout_i_reg[1]\(4 downto 0);
ram_empty_fb_i_reg_0 <= \^ram_empty_fb_i_reg_0\;
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => rd_pntr_plus1(3),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => rd_pntr_plus1(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => rd_pntr_plus1(4),
O => plusOp(4)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(0),
Q => \^gpr1.dout_i_reg[1]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(1),
Q => \^gpr1.dout_i_reg[1]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(2),
Q => \^gpr1.dout_i_reg[1]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => rd_pntr_plus1(3),
Q => \^gpr1.dout_i_reg[1]\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => rd_pntr_plus1(4),
Q => \^gpr1.dout_i_reg[1]\(4)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => plusOp(0),
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(3),
Q => rd_pntr_plus1(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(4),
Q => rd_pntr_plus1(4)
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFA2F3A2"
)
port map (
I0 => ram_empty_fb_i_i_2_n_0,
I1 => wr_en,
I2 => ram_full_fb_i_reg,
I3 => \out\,
I4 => \^ram_empty_fb_i_reg_0\,
O => ram_empty_fb_i_reg
);
ram_empty_fb_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000000000"
)
port map (
I0 => rd_pntr_plus1(3),
I1 => \gcc0.gc0.count_d1_reg[4]\(3),
I2 => rd_pntr_plus1(4),
I3 => \gcc0.gc0.count_d1_reg[4]\(4),
I4 => \gpregsm1.curr_fwft_state_reg[0]\,
I5 => \gcc0.gc0.count_d1_reg[2]\,
O => ram_empty_fb_i_i_2_n_0
);
ram_empty_fb_i_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"BEFFFFBE"
)
port map (
I0 => ram_empty_fb_i_i_6_n_0,
I1 => \^gpr1.dout_i_reg[1]\(2),
I2 => \gcc0.gc0.count_d1_reg[4]\(2),
I3 => \^gpr1.dout_i_reg[1]\(1),
I4 => \gcc0.gc0.count_d1_reg[4]\(1),
O => \^ram_empty_fb_i_reg_0\
);
ram_empty_fb_i_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \^gpr1.dout_i_reg[1]\(4),
I1 => \gcc0.gc0.count_d1_reg[4]\(4),
I2 => \^gpr1.dout_i_reg[1]\(3),
I3 => \gcc0.gc0.count_d1_reg[4]\(3),
I4 => \gcc0.gc0.count_d1_reg[4]\(0),
I5 => \^gpr1.dout_i_reg[1]\(0),
O => ram_empty_fb_i_i_6_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_rd_bin_cntr_18 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
ram_empty_fb_i_reg_0 : out STD_LOGIC;
\gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
\out\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_rd_bin_cntr_18 : entity is "rd_bin_cntr";
end system_auto_pc_1_rd_bin_cntr_18;
architecture STRUCTURE of system_auto_pc_1_rd_bin_cntr_18 is
signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^gpr1.dout_i_reg[1]\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ram_empty_fb_i_i_2_n_0 : STD_LOGIC;
signal ram_empty_fb_i_i_6_n_0 : STD_LOGIC;
signal \^ram_empty_fb_i_reg_0\ : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 4 downto 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair28";
begin
Q(2 downto 0) <= \^q\(2 downto 0);
\gpr1.dout_i_reg[1]\(4 downto 0) <= \^gpr1.dout_i_reg[1]\(4 downto 0);
ram_empty_fb_i_reg_0 <= \^ram_empty_fb_i_reg_0\;
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => rd_pntr_plus1(3),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => rd_pntr_plus1(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => rd_pntr_plus1(4),
O => plusOp(4)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(0),
Q => \^gpr1.dout_i_reg[1]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(1),
Q => \^gpr1.dout_i_reg[1]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(2),
Q => \^gpr1.dout_i_reg[1]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => rd_pntr_plus1(3),
Q => \^gpr1.dout_i_reg[1]\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => rd_pntr_plus1(4),
Q => \^gpr1.dout_i_reg[1]\(4)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => plusOp(0),
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(3),
Q => rd_pntr_plus1(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(4),
Q => rd_pntr_plus1(4)
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFA2F3A2"
)
port map (
I0 => ram_empty_fb_i_i_2_n_0,
I1 => wr_en,
I2 => ram_full_fb_i_reg,
I3 => \out\,
I4 => \^ram_empty_fb_i_reg_0\,
O => ram_empty_fb_i_reg
);
ram_empty_fb_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000000000"
)
port map (
I0 => rd_pntr_plus1(3),
I1 => \gcc0.gc0.count_d1_reg[4]\(3),
I2 => rd_pntr_plus1(4),
I3 => \gcc0.gc0.count_d1_reg[4]\(4),
I4 => \gpregsm1.curr_fwft_state_reg[0]\,
I5 => \gcc0.gc0.count_d1_reg[2]\,
O => ram_empty_fb_i_i_2_n_0
);
ram_empty_fb_i_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"BEFFFFBE"
)
port map (
I0 => ram_empty_fb_i_i_6_n_0,
I1 => \^gpr1.dout_i_reg[1]\(2),
I2 => \gcc0.gc0.count_d1_reg[4]\(2),
I3 => \^gpr1.dout_i_reg[1]\(1),
I4 => \gcc0.gc0.count_d1_reg[4]\(1),
O => \^ram_empty_fb_i_reg_0\
);
ram_empty_fb_i_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \^gpr1.dout_i_reg[1]\(4),
I1 => \gcc0.gc0.count_d1_reg[4]\(4),
I2 => \^gpr1.dout_i_reg[1]\(3),
I3 => \gcc0.gc0.count_d1_reg[4]\(3),
I4 => \gcc0.gc0.count_d1_reg[4]\(0),
I5 => \^gpr1.dout_i_reg[1]\(0),
O => ram_empty_fb_i_i_6_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_rd_bin_cntr_32 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
ram_empty_fb_i_reg_0 : out STD_LOGIC;
\gpr1.dout_i_reg[0]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
\out\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_rd_bin_cntr_32 : entity is "rd_bin_cntr";
end system_auto_pc_1_rd_bin_cntr_32;
architecture STRUCTURE of system_auto_pc_1_rd_bin_cntr_32 is
signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^gpr1.dout_i_reg[0]\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ram_empty_fb_i_i_2_n_0 : STD_LOGIC;
signal ram_empty_fb_i_i_6_n_0 : STD_LOGIC;
signal \^ram_empty_fb_i_reg_0\ : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 4 downto 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair0";
begin
Q(2 downto 0) <= \^q\(2 downto 0);
\gpr1.dout_i_reg[0]\(4 downto 0) <= \^gpr1.dout_i_reg[0]\(4 downto 0);
ram_empty_fb_i_reg_0 <= \^ram_empty_fb_i_reg_0\;
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => rd_pntr_plus1(3),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => rd_pntr_plus1(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => rd_pntr_plus1(4),
O => plusOp(4)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \^gpr1.dout_i_reg[0]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gpr1.dout_i_reg[0]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gpr1.dout_i_reg[0]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => rd_pntr_plus1(3),
Q => \^gpr1.dout_i_reg[0]\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => rd_pntr_plus1(4),
Q => \^gpr1.dout_i_reg[0]\(4)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => plusOp(0),
PRE => AR(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(3),
Q => rd_pntr_plus1(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(4),
Q => rd_pntr_plus1(4)
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFA2F3A2"
)
port map (
I0 => ram_empty_fb_i_i_2_n_0,
I1 => wr_en,
I2 => ram_full_fb_i_reg,
I3 => \out\,
I4 => \^ram_empty_fb_i_reg_0\,
O => ram_empty_fb_i_reg
);
ram_empty_fb_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000000000"
)
port map (
I0 => rd_pntr_plus1(3),
I1 => \gcc0.gc0.count_d1_reg[4]\(3),
I2 => rd_pntr_plus1(4),
I3 => \gcc0.gc0.count_d1_reg[4]\(4),
I4 => \gpregsm1.curr_fwft_state_reg[0]\,
I5 => \gcc0.gc0.count_d1_reg[2]\,
O => ram_empty_fb_i_i_2_n_0
);
ram_empty_fb_i_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"BEFFFFBE"
)
port map (
I0 => ram_empty_fb_i_i_6_n_0,
I1 => \^gpr1.dout_i_reg[0]\(2),
I2 => \gcc0.gc0.count_d1_reg[4]\(2),
I3 => \^gpr1.dout_i_reg[0]\(1),
I4 => \gcc0.gc0.count_d1_reg[4]\(1),
O => \^ram_empty_fb_i_reg_0\
);
ram_empty_fb_i_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \^gpr1.dout_i_reg[0]\(4),
I1 => \gcc0.gc0.count_d1_reg[4]\(4),
I2 => \^gpr1.dout_i_reg[0]\(3),
I3 => \gcc0.gc0.count_d1_reg[4]\(3),
I4 => \gcc0.gc0.count_d1_reg[4]\(0),
I5 => \^gpr1.dout_i_reg[0]\(0),
O => ram_empty_fb_i_i_6_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_rd_fwft is
port (
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
\goreg_dm.dout_i_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_fb_i_reg : out STD_LOGIC;
clk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg_0 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_rd_fwft : entity is "rd_fwft";
end system_auto_pc_1_rd_fwft;
architecture STRUCTURE of system_auto_pc_1_rd_fwft is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
empty <= empty_fwft_i;
aempty_fwft_fb_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FAEF8000"
)
port map (
I0 => ram_empty_fb_i_reg_0,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_i
);
empty_fwft_fb_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => rd_en,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_fb_i
);
empty_fwft_fb_o_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_o_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => rd_en,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => \out\(1),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_i
);
\gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg_0,
O => E(0)
);
\goreg_dm.dout_i[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4404"
)
port map (
I0 => \out\(0),
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => rd_en,
O => \goreg_dm.dout_i_reg[4]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => rd_en,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg_0,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => user_valid
);
ram_empty_fb_i_i_4: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => curr_fwft_state(0),
I1 => rd_en,
I2 => curr_fwft_state(1),
O => ram_empty_fb_i_reg
);
ram_full_fb_i_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FF08"
)
port map (
I0 => curr_fwft_state(0),
I1 => curr_fwft_state(1),
I2 => rd_en,
I3 => ram_empty_fb_i_reg_0,
O => ram_full_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_rd_fwft_16 is
port (
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
\goreg_dm.dout_i_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_fb_i_reg : out STD_LOGIC;
clk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg_0 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_rd_fwft_16 : entity is "rd_fwft";
end system_auto_pc_1_rd_fwft_16;
architecture STRUCTURE of system_auto_pc_1_rd_fwft_16 is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
empty <= empty_fwft_i;
aempty_fwft_fb_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FAEF8000"
)
port map (
I0 => ram_empty_fb_i_reg_0,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_i
);
empty_fwft_fb_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => rd_en,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_fb_i
);
empty_fwft_fb_o_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_o_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => rd_en,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => \out\(1),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_i
);
\gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg_0,
O => E(0)
);
\goreg_dm.dout_i[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4404"
)
port map (
I0 => \out\(0),
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => rd_en,
O => \goreg_dm.dout_i_reg[5]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => rd_en,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg_0,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => user_valid
);
ram_empty_fb_i_i_4: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => curr_fwft_state(0),
I1 => rd_en,
I2 => curr_fwft_state(1),
O => ram_empty_fb_i_reg
);
ram_full_fb_i_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FF08"
)
port map (
I0 => curr_fwft_state(0),
I1 => curr_fwft_state(1),
I2 => rd_en,
I3 => ram_empty_fb_i_reg_0,
O => ram_full_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_rd_fwft_30 is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
empty : out STD_LOGIC;
\gpr1.dout_i_reg[0]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
p_0_out : in STD_LOGIC;
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg_0 : in STD_LOGIC;
dout_i : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_rd_fwft_30 : entity is "rd_fwft";
end system_auto_pc_1_rd_fwft_30;
architecture STRUCTURE of system_auto_pc_1_rd_fwft_30 is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
empty <= empty_fwft_i;
\out\(1 downto 0) <= curr_fwft_state(1 downto 0);
aempty_fwft_fb_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FAEF8000"
)
port map (
I0 => ram_empty_fb_i_reg_0,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => aempty_fwft_i0,
PRE => AR(0),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => aempty_fwft_i0,
PRE => AR(0),
Q => aempty_fwft_i
);
empty_fwft_fb_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => rd_en,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => AR(0),
Q => empty_fwft_fb_i
);
empty_fwft_fb_o_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_o_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => rd_en,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => AR(0),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => AR(0),
Q => empty_fwft_i
);
\gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg_0,
O => E(0)
);
\gpr1.dout_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAEAA0000A2AA"
)
port map (
I0 => p_0_out,
I1 => curr_fwft_state(1),
I2 => rd_en,
I3 => curr_fwft_state(0),
I4 => ram_empty_fb_i_reg_0,
I5 => dout_i,
O => \gpr1.dout_i_reg[0]\
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => rd_en,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg_0,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => AR(0),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => AR(0),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => AR(0),
D => next_fwft_state(0),
Q => user_valid
);
ram_empty_fb_i_i_4: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => curr_fwft_state(0),
I1 => rd_en,
I2 => curr_fwft_state(1),
O => ram_empty_fb_i_reg
);
ram_full_fb_i_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FF08"
)
port map (
I0 => curr_fwft_state(0),
I1 => curr_fwft_state(1),
I2 => rd_en,
I3 => ram_empty_fb_i_reg_0,
O => ram_full_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_rd_status_flags_ss is
port (
\out\ : out STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_rd_status_flags_ss : entity is "rd_status_flags_ss";
end system_auto_pc_1_rd_status_flags_ss;
architecture STRUCTURE of system_auto_pc_1_rd_status_flags_ss is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_fb_i_reg,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_fb_i_reg,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_rd_status_flags_ss_17 is
port (
\out\ : out STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_rd_status_flags_ss_17 : entity is "rd_status_flags_ss";
end system_auto_pc_1_rd_status_flags_ss_17;
architecture STRUCTURE of system_auto_pc_1_rd_status_flags_ss_17 is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_fb_i_reg,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_fb_i_reg,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_rd_status_flags_ss_31 is
port (
\out\ : out STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_rd_status_flags_ss_31 : entity is "rd_status_flags_ss";
end system_auto_pc_1_rd_status_flags_ss_31;
architecture STRUCTURE of system_auto_pc_1_rd_status_flags_ss_31 is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_fb_i_reg,
PRE => AR(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_fb_i_reg,
PRE => AR(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_0 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_0 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_0;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_0 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_1 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_1 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_1;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_1 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_10 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_10 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_10;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_10 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_11 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_11 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_11;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_11 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_12 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_12 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_12;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_12 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_13 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_13 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_13;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_13 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_2 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_2 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_2;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_2 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_22 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_22 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_22;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_22 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_23 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_23 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_23;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_23 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_24 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_24 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_24;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_24 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_25 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_25 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_25;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_25 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_26 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_26 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_26;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_26 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_27 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_27 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_27;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_27 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_3 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_3 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_3;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_3 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_4 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_4 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_4;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_4 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_8 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_8 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_8;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_8 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_9 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_9 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_9;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_9 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_wr_bin_cntr is
port (
ram_full_comb : out STD_LOGIC;
ram_empty_fb_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC;
\out\ : in STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
wr_en : in STD_LOGIC;
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_wr_bin_cntr : entity is "wr_bin_cntr";
end system_auto_pc_1_wr_bin_cntr;
architecture STRUCTURE of system_auto_pc_1_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ram_full_fb_i_i_2_n_0 : STD_LOGIC;
signal ram_full_fb_i_i_4_n_0 : STD_LOGIC;
signal ram_full_fb_i_i_5_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of ram_full_fb_i_i_5 : label is "soft_lutpair36";
begin
Q(4 downto 0) <= \^q\(4 downto 0);
\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_12_out(0),
O => \plusOp__0\(0)
);
\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_12_out(0),
I1 => p_12_out(1),
O => \plusOp__0\(1)
);
\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => p_12_out(1),
I1 => p_12_out(0),
I2 => p_12_out(2),
O => \plusOp__0\(2)
);
\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => p_12_out(2),
I1 => p_12_out(0),
I2 => p_12_out(1),
I3 => p_12_out(3),
O => \plusOp__0\(3)
);
\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => p_12_out(3),
I1 => p_12_out(1),
I2 => p_12_out(0),
I3 => p_12_out(2),
I4 => p_12_out(4),
O => \plusOp__0\(4)
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(0),
Q => \^q\(0)
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(1),
Q => \^q\(1)
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(2),
Q => \^q\(2)
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(3),
Q => \^q\(3)
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(4),
Q => \^q\(4)
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(0),
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
Q => p_12_out(0)
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(1),
Q => p_12_out(1)
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(2),
Q => p_12_out(2)
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(3),
Q => p_12_out(3)
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(4),
Q => p_12_out(4)
);
ram_empty_fb_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_reg[2]\(2),
I2 => \^q\(1),
I3 => \gc0.count_reg[2]\(1),
I4 => \gc0.count_reg[2]\(0),
I5 => \^q\(0),
O => ram_empty_fb_i_reg
);
ram_full_fb_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F8C8"
)
port map (
I0 => ram_full_fb_i_i_2_n_0,
I1 => \gpregsm1.curr_fwft_state_reg[0]\,
I2 => \out\,
I3 => \gc0.count_d1_reg[2]\,
O => ram_full_comb
);
ram_full_fb_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"80000080"
)
port map (
I0 => ram_full_fb_i_i_4_n_0,
I1 => ram_full_fb_i_i_5_n_0,
I2 => wr_en,
I3 => \gc0.count_d1_reg[4]\(4),
I4 => p_12_out(4),
O => ram_full_fb_i_i_2_n_0
);
ram_full_fb_i_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(2),
I1 => \gc0.count_d1_reg[4]\(2),
I2 => p_12_out(3),
I3 => \gc0.count_d1_reg[4]\(3),
O => ram_full_fb_i_i_4_n_0
);
ram_full_fb_i_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(0),
I1 => \gc0.count_d1_reg[4]\(0),
I2 => p_12_out(1),
I3 => \gc0.count_d1_reg[4]\(1),
O => ram_full_fb_i_i_5_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_wr_bin_cntr_15 is
port (
ram_full_comb : out STD_LOGIC;
ram_empty_fb_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC;
\out\ : in STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
wr_en : in STD_LOGIC;
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_wr_bin_cntr_15 : entity is "wr_bin_cntr";
end system_auto_pc_1_wr_bin_cntr_15;
architecture STRUCTURE of system_auto_pc_1_wr_bin_cntr_15 is
signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ram_full_fb_i_i_2_n_0 : STD_LOGIC;
signal ram_full_fb_i_i_4_n_0 : STD_LOGIC;
signal ram_full_fb_i_i_5_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of ram_full_fb_i_i_5 : label is "soft_lutpair31";
begin
Q(4 downto 0) <= \^q\(4 downto 0);
\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_12_out(0),
O => \plusOp__0\(0)
);
\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_12_out(0),
I1 => p_12_out(1),
O => \plusOp__0\(1)
);
\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => p_12_out(1),
I1 => p_12_out(0),
I2 => p_12_out(2),
O => \plusOp__0\(2)
);
\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => p_12_out(2),
I1 => p_12_out(0),
I2 => p_12_out(1),
I3 => p_12_out(3),
O => \plusOp__0\(3)
);
\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => p_12_out(3),
I1 => p_12_out(1),
I2 => p_12_out(0),
I3 => p_12_out(2),
I4 => p_12_out(4),
O => \plusOp__0\(4)
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(0),
Q => \^q\(0)
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(1),
Q => \^q\(1)
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(2),
Q => \^q\(2)
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(3),
Q => \^q\(3)
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(4),
Q => \^q\(4)
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(0),
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
Q => p_12_out(0)
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(1),
Q => p_12_out(1)
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(2),
Q => p_12_out(2)
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(3),
Q => p_12_out(3)
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(4),
Q => p_12_out(4)
);
ram_empty_fb_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_reg[2]\(2),
I2 => \^q\(1),
I3 => \gc0.count_reg[2]\(1),
I4 => \gc0.count_reg[2]\(0),
I5 => \^q\(0),
O => ram_empty_fb_i_reg
);
ram_full_fb_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F8C8"
)
port map (
I0 => ram_full_fb_i_i_2_n_0,
I1 => \gpregsm1.curr_fwft_state_reg[0]\,
I2 => \out\,
I3 => \gc0.count_d1_reg[2]\,
O => ram_full_comb
);
ram_full_fb_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"80000080"
)
port map (
I0 => ram_full_fb_i_i_4_n_0,
I1 => ram_full_fb_i_i_5_n_0,
I2 => wr_en,
I3 => \gc0.count_d1_reg[4]\(4),
I4 => p_12_out(4),
O => ram_full_fb_i_i_2_n_0
);
ram_full_fb_i_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(2),
I1 => \gc0.count_d1_reg[4]\(2),
I2 => p_12_out(3),
I3 => \gc0.count_d1_reg[4]\(3),
O => ram_full_fb_i_i_4_n_0
);
ram_full_fb_i_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(0),
I1 => \gc0.count_d1_reg[4]\(0),
I2 => p_12_out(1),
I3 => \gc0.count_d1_reg[4]\(1),
O => ram_full_fb_i_i_5_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_wr_bin_cntr_29 is
port (
ram_full_comb : out STD_LOGIC;
ram_empty_fb_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC;
\out\ : in STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
wr_en : in STD_LOGIC;
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_wr_bin_cntr_29 : entity is "wr_bin_cntr";
end system_auto_pc_1_wr_bin_cntr_29;
architecture STRUCTURE of system_auto_pc_1_wr_bin_cntr_29 is
signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ram_full_fb_i_i_2_n_0 : STD_LOGIC;
signal ram_full_fb_i_i_4_n_0 : STD_LOGIC;
signal ram_full_fb_i_i_5_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of ram_full_fb_i_i_5 : label is "soft_lutpair3";
begin
Q(4 downto 0) <= \^q\(4 downto 0);
\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_12_out(0),
O => \plusOp__0\(0)
);
\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_12_out(0),
I1 => p_12_out(1),
O => \plusOp__0\(1)
);
\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => p_12_out(1),
I1 => p_12_out(0),
I2 => p_12_out(2),
O => \plusOp__0\(2)
);
\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => p_12_out(2),
I1 => p_12_out(0),
I2 => p_12_out(1),
I3 => p_12_out(3),
O => \plusOp__0\(3)
);
\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => p_12_out(3),
I1 => p_12_out(1),
I2 => p_12_out(0),
I3 => p_12_out(2),
I4 => p_12_out(4),
O => \plusOp__0\(4)
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(0),
Q => \^q\(0)
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(1),
Q => \^q\(1)
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(2),
Q => \^q\(2)
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(3),
Q => \^q\(3)
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(4),
Q => \^q\(4)
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(0),
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
Q => p_12_out(0)
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(1),
Q => p_12_out(1)
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(2),
Q => p_12_out(2)
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(3),
Q => p_12_out(3)
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(4),
Q => p_12_out(4)
);
ram_empty_fb_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_reg[2]\(2),
I2 => \^q\(1),
I3 => \gc0.count_reg[2]\(1),
I4 => \gc0.count_reg[2]\(0),
I5 => \^q\(0),
O => ram_empty_fb_i_reg
);
ram_full_fb_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F8C8"
)
port map (
I0 => ram_full_fb_i_i_2_n_0,
I1 => \gpregsm1.curr_fwft_state_reg[0]\,
I2 => \out\,
I3 => \gc0.count_d1_reg[2]\,
O => ram_full_comb
);
ram_full_fb_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"80000080"
)
port map (
I0 => ram_full_fb_i_i_4_n_0,
I1 => ram_full_fb_i_i_5_n_0,
I2 => wr_en,
I3 => \gc0.count_d1_reg[4]\(4),
I4 => p_12_out(4),
O => ram_full_fb_i_i_2_n_0
);
ram_full_fb_i_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(2),
I1 => \gc0.count_d1_reg[4]\(2),
I2 => p_12_out(3),
I3 => \gc0.count_d1_reg[4]\(3),
O => ram_full_fb_i_i_4_n_0
);
ram_full_fb_i_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(0),
I1 => \gc0.count_d1_reg[4]\(0),
I2 => p_12_out(1),
I3 => \gc0.count_d1_reg[4]\(1),
O => ram_full_fb_i_i_5_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_wr_status_flags_ss is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_comb : in STD_LOGIC;
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_wr_status_flags_ss : entity is "wr_status_flags_ss";
end system_auto_pc_1_wr_status_flags_ss;
architecture STRUCTURE of system_auto_pc_1_wr_status_flags_ss is
signal ram_afull_fb : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_afull_fb : signal is std.standard.true;
signal ram_afull_i : STD_LOGIC;
attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true;
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
full <= ram_full_i;
\out\ <= ram_full_fb_i;
\gcc0.gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => E(0)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => ram_afull_i
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => ram_afull_fb
);
ram_full_fb_i_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => ram_full_comb,
Q => ram_full_fb_i
);
ram_full_i_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => ram_full_comb,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_wr_status_flags_ss_14 is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_comb : in STD_LOGIC;
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_wr_status_flags_ss_14 : entity is "wr_status_flags_ss";
end system_auto_pc_1_wr_status_flags_ss_14;
architecture STRUCTURE of system_auto_pc_1_wr_status_flags_ss_14 is
signal ram_afull_fb : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_afull_fb : signal is std.standard.true;
signal ram_afull_i : STD_LOGIC;
attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true;
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
full <= ram_full_i;
\out\ <= ram_full_fb_i;
\gcc0.gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => E(0)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => ram_afull_i
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => ram_afull_fb
);
ram_full_fb_i_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => ram_full_comb,
Q => ram_full_fb_i
);
ram_full_i_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => ram_full_comb,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_wr_status_flags_ss_28 is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_comb : in STD_LOGIC;
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_wr_status_flags_ss_28 : entity is "wr_status_flags_ss";
end system_auto_pc_1_wr_status_flags_ss_28;
architecture STRUCTURE of system_auto_pc_1_wr_status_flags_ss_28 is
signal ram_afull_fb : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_afull_fb : signal is std.standard.true;
signal ram_afull_i : STD_LOGIC;
attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true;
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
full <= ram_full_i;
\out\ <= ram_full_fb_i;
\gcc0.gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => E(0)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => ram_afull_i
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => ram_afull_fb
);
ram_full_fb_i_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => ram_full_comb,
Q => ram_full_fb_i
);
ram_full_i_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => ram_full_comb,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_memory is
port (
dout : out STD_LOGIC_VECTOR ( 5 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
EN : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 5 downto 0 );
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
I54 : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_memory : entity is "memory";
end system_auto_pc_1_memory;
architecture STRUCTURE of system_auto_pc_1_memory is
signal dout_i : STD_LOGIC_VECTOR ( 5 downto 0 );
begin
\gdm.dm_gen.dm\: entity work.system_auto_pc_1_dmem
port map (
EN => EN,
I54(4 downto 0) => I54(4 downto 0),
clk => clk,
din(5 downto 0) => din(5 downto 0),
dout_i(5 downto 0) => dout_i(5 downto 0),
\gc0.count_d1_reg[4]\(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => \gpregsm1.curr_fwft_state_reg[1]\(0)
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => dout_i(0),
Q => dout(0),
R => '0'
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => dout_i(1),
Q => dout(1),
R => '0'
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => dout_i(2),
Q => dout(2),
R => '0'
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => dout_i(3),
Q => dout(3),
R => '0'
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => dout_i(4),
Q => dout(4),
R => '0'
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => dout_i(5),
Q => dout(5),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_memory__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 4 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
EN : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
I55 : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_memory__parameterized0\ : entity is "memory";
end \system_auto_pc_1_memory__parameterized0\;
architecture STRUCTURE of \system_auto_pc_1_memory__parameterized0\ is
signal dout_i : STD_LOGIC_VECTOR ( 4 downto 0 );
begin
\gdm.dm_gen.dm\: entity work.\system_auto_pc_1_dmem__parameterized0\
port map (
EN => EN,
I55(4 downto 0) => I55(4 downto 0),
clk => clk,
din(4 downto 0) => din(4 downto 0),
dout_i(4 downto 0) => dout_i(4 downto 0),
\gc0.count_d1_reg[4]\(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => \gpregsm1.curr_fwft_state_reg[1]\(0)
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => dout_i(0),
Q => dout(0),
R => '0'
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => dout_i(1),
Q => dout(1),
R => '0'
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => dout_i(2),
Q => dout(2),
R => '0'
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => dout_i(3),
Q => dout(3),
R => '0'
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => dout_i(4),
Q => dout(4),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_memory__parameterized1\ is
port (
p_0_out : out STD_LOGIC;
dout_i : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gpregsm1.curr_fwft_state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_memory__parameterized1\ : entity is "memory";
end \system_auto_pc_1_memory__parameterized1\;
architecture STRUCTURE of \system_auto_pc_1_memory__parameterized1\ is
signal \^dout\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gdm.dm_gen.dm_n_2\ : STD_LOGIC;
begin
dout(0) <= \^dout\(0);
\gdm.dm_gen.dm\: entity work.\system_auto_pc_1_dmem__parameterized1\
port map (
E(0) => E(0),
Q(4 downto 0) => Q(4 downto 0),
clk => clk,
din(0) => din(0),
dout(0) => \^dout\(0),
dout_i => dout_i,
\gc0.count_d1_reg[4]\(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
\goreg_dm.dout_i_reg[0]\ => \gdm.dm_gen.dm_n_2\,
\gpregsm1.curr_fwft_state_reg[1]\ => \gpregsm1.curr_fwft_state_reg[1]\,
\gpregsm1.curr_fwft_state_reg[1]_0\(1 downto 0) => \gpregsm1.curr_fwft_state_reg[1]_0\(1 downto 0),
\out\(0) => \out\(0),
p_0_out => p_0_out,
rd_en => rd_en
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \gdm.dm_gen.dm_n_2\,
Q => \^dout\(0),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_rd_logic is
port (
empty : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
clk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg_0 : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_rd_logic : entity is "rd_logic";
end system_auto_pc_1_rd_logic;
architecture STRUCTURE of system_auto_pc_1_rd_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gr1.gr1_int.rfwft_n_2\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rpntr_n_3 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gr1.gr1_int.rfwft\: entity work.system_auto_pc_1_rd_fwft
port map (
E(0) => \^e\(0),
clk => clk,
empty => empty,
\goreg_dm.dout_i_reg[4]\(0) => \goreg_dm.dout_i_reg[4]\(0),
\out\(1 downto 0) => \out\(1 downto 0),
ram_empty_fb_i_reg => \gr1.gr1_int.rfwft_n_2\,
ram_empty_fb_i_reg_0 => p_2_out,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en
);
\grss.rsts\: entity work.system_auto_pc_1_rd_status_flags_ss
port map (
clk => clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1),
\out\ => p_2_out,
ram_full_fb_i_reg => rpntr_n_3
);
rpntr: entity work.system_auto_pc_1_rd_bin_cntr
port map (
E(0) => \^e\(0),
Q(2 downto 0) => Q(2 downto 0),
clk => clk,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
\gpr1.dout_i_reg[1]\(4 downto 0) => \gpr1.dout_i_reg[1]\(4 downto 0),
\gpregsm1.curr_fwft_state_reg[0]\ => \gr1.gr1_int.rfwft_n_2\,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1),
\out\ => p_2_out,
ram_empty_fb_i_reg => rpntr_n_3,
ram_empty_fb_i_reg_0 => ram_empty_fb_i_reg,
ram_full_fb_i_reg => ram_full_fb_i_reg_0,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_rd_logic_19 is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
empty : out STD_LOGIC;
\gpr1.dout_i_reg[0]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
\gpr1.dout_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
p_0_out : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout_i : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg_0 : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_rd_logic_19 : entity is "rd_logic";
end system_auto_pc_1_rd_logic_19;
architecture STRUCTURE of system_auto_pc_1_rd_logic_19 is
signal \gntv_or_sync_fifo.mem/ram_rd_en_i\ : STD_LOGIC;
signal \gr1.gr1_int.rfwft_n_5\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rpntr_n_3 : STD_LOGIC;
begin
\gr1.gr1_int.rfwft\: entity work.system_auto_pc_1_rd_fwft_30
port map (
AR(0) => AR(0),
E(0) => \gntv_or_sync_fifo.mem/ram_rd_en_i\,
clk => clk,
dout_i => dout_i,
empty => empty,
\gpr1.dout_i_reg[0]\ => \gpr1.dout_i_reg[0]\,
\out\(1 downto 0) => \out\(1 downto 0),
p_0_out => p_0_out,
ram_empty_fb_i_reg => \gr1.gr1_int.rfwft_n_5\,
ram_empty_fb_i_reg_0 => p_2_out,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en
);
\grss.rsts\: entity work.system_auto_pc_1_rd_status_flags_ss_31
port map (
AR(0) => AR(0),
clk => clk,
\out\ => p_2_out,
ram_full_fb_i_reg => rpntr_n_3
);
rpntr: entity work.system_auto_pc_1_rd_bin_cntr_32
port map (
AR(0) => AR(0),
E(0) => \gntv_or_sync_fifo.mem/ram_rd_en_i\,
Q(2 downto 0) => Q(2 downto 0),
clk => clk,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
\gpr1.dout_i_reg[0]\(4 downto 0) => \gpr1.dout_i_reg[0]_0\(4 downto 0),
\gpregsm1.curr_fwft_state_reg[0]\ => \gr1.gr1_int.rfwft_n_5\,
\out\ => p_2_out,
ram_empty_fb_i_reg => rpntr_n_3,
ram_empty_fb_i_reg_0 => ram_empty_fb_i_reg,
ram_full_fb_i_reg => ram_full_fb_i_reg_0,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_rd_logic_5 is
port (
empty : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
clk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg_0 : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_rd_logic_5 : entity is "rd_logic";
end system_auto_pc_1_rd_logic_5;
architecture STRUCTURE of system_auto_pc_1_rd_logic_5 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gr1.gr1_int.rfwft_n_2\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rpntr_n_3 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gr1.gr1_int.rfwft\: entity work.system_auto_pc_1_rd_fwft_16
port map (
E(0) => \^e\(0),
clk => clk,
empty => empty,
\goreg_dm.dout_i_reg[5]\(0) => \goreg_dm.dout_i_reg[5]\(0),
\out\(1 downto 0) => \out\(1 downto 0),
ram_empty_fb_i_reg => \gr1.gr1_int.rfwft_n_2\,
ram_empty_fb_i_reg_0 => p_2_out,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en
);
\grss.rsts\: entity work.system_auto_pc_1_rd_status_flags_ss_17
port map (
clk => clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1),
\out\ => p_2_out,
ram_full_fb_i_reg => rpntr_n_3
);
rpntr: entity work.system_auto_pc_1_rd_bin_cntr_18
port map (
E(0) => \^e\(0),
Q(2 downto 0) => Q(2 downto 0),
clk => clk,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
\gpr1.dout_i_reg[1]\(4 downto 0) => \gpr1.dout_i_reg[1]\(4 downto 0),
\gpregsm1.curr_fwft_state_reg[0]\ => \gr1.gr1_int.rfwft_n_2\,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1),
\out\ => p_2_out,
ram_empty_fb_i_reg => rpntr_n_3,
ram_empty_fb_i_reg_0 => ram_empty_fb_i_reg,
ram_full_fb_i_reg => ram_full_fb_i_reg_0,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_reset_blk_ramfifo is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end system_auto_pc_1_reset_blk_ramfifo;
architecture STRUCTURE of system_auto_pc_1_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(1) <= rd_rst_reg(2);
\gc0.count_reg[1]\(0) <= rd_rst_reg(0);
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.system_auto_pc_1_synchronizer_ff
port map (
clk => clk,
in0(0) => rd_rst_asreg,
\out\ => p_6_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_0
port map (
clk => clk,
in0(0) => wr_rst_asreg,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_1
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_8_out,
clk => clk,
in0(0) => rd_rst_asreg,
\out\ => p_6_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_2
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_9_out,
clk => clk,
in0(0) => wr_rst_asreg,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_3
port map (
\Q_reg_reg[0]_0\ => p_8_out,
clk => clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_4
port map (
\Q_reg_reg[0]_0\ => p_9_out,
clk => clk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_reset_blk_ramfifo_21 is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_reset_blk_ramfifo_21 : entity is "reset_blk_ramfifo";
end system_auto_pc_1_reset_blk_ramfifo_21;
architecture STRUCTURE of system_auto_pc_1_reset_blk_ramfifo_21 is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(1) <= rd_rst_reg(2);
\gc0.count_reg[1]\(0) <= rd_rst_reg(0);
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_22
port map (
clk => clk,
in0(0) => rd_rst_asreg,
\out\ => p_6_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_23
port map (
clk => clk,
in0(0) => wr_rst_asreg,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_24
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_8_out,
clk => clk,
in0(0) => rd_rst_asreg,
\out\ => p_6_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_25
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_9_out,
clk => clk,
in0(0) => wr_rst_asreg,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_26
port map (
\Q_reg_reg[0]_0\ => p_8_out,
clk => clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_27
port map (
\Q_reg_reg[0]_0\ => p_9_out,
clk => clk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_reset_blk_ramfifo_7 is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_reset_blk_ramfifo_7 : entity is "reset_blk_ramfifo";
end system_auto_pc_1_reset_blk_ramfifo_7;
architecture STRUCTURE of system_auto_pc_1_reset_blk_ramfifo_7 is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(1) <= rd_rst_reg(2);
\gc0.count_reg[1]\(0) <= rd_rst_reg(0);
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_8
port map (
clk => clk,
in0(0) => rd_rst_asreg,
\out\ => p_6_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_9
port map (
clk => clk,
in0(0) => wr_rst_asreg,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_10
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_8_out,
clk => clk,
in0(0) => rd_rst_asreg,
\out\ => p_6_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_11
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_9_out,
clk => clk,
in0(0) => wr_rst_asreg,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_12
port map (
\Q_reg_reg[0]_0\ => p_8_out,
clk => clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_13
port map (
\Q_reg_reg[0]_0\ => p_9_out,
clk => clk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_wr_logic is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wr_en : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_wr_logic : entity is "wr_logic";
end system_auto_pc_1_wr_logic;
architecture STRUCTURE of system_auto_pc_1_wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^out\ : STD_LOGIC;
signal ram_full_comb : STD_LOGIC;
begin
E(0) <= \^e\(0);
\out\ <= \^out\;
\gwss.wsts\: entity work.system_auto_pc_1_wr_status_flags_ss
port map (
E(0) => \^e\(0),
clk => clk,
full => full,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
\out\ => \^out\,
ram_full_comb => ram_full_comb,
wr_en => wr_en
);
wpntr: entity work.system_auto_pc_1_wr_bin_cntr
port map (
E(0) => \^e\(0),
Q(4 downto 0) => Q(4 downto 0),
clk => clk,
\gc0.count_d1_reg[2]\ => \gc0.count_d1_reg[2]\,
\gc0.count_d1_reg[4]\(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
\gc0.count_reg[2]\(2 downto 0) => \gc0.count_reg[2]\(2 downto 0),
\gpregsm1.curr_fwft_state_reg[0]\ => \gpregsm1.curr_fwft_state_reg[0]\,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(1),
\out\ => \^out\,
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
ram_full_comb => ram_full_comb,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_wr_logic_20 is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wr_en : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_wr_logic_20 : entity is "wr_logic";
end system_auto_pc_1_wr_logic_20;
architecture STRUCTURE of system_auto_pc_1_wr_logic_20 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^out\ : STD_LOGIC;
signal ram_full_comb : STD_LOGIC;
begin
E(0) <= \^e\(0);
\out\ <= \^out\;
\gwss.wsts\: entity work.system_auto_pc_1_wr_status_flags_ss_28
port map (
E(0) => \^e\(0),
clk => clk,
full => full,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
\out\ => \^out\,
ram_full_comb => ram_full_comb,
wr_en => wr_en
);
wpntr: entity work.system_auto_pc_1_wr_bin_cntr_29
port map (
E(0) => \^e\(0),
Q(4 downto 0) => Q(4 downto 0),
clk => clk,
\gc0.count_d1_reg[2]\ => \gc0.count_d1_reg[2]\,
\gc0.count_d1_reg[4]\(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
\gc0.count_reg[2]\(2 downto 0) => \gc0.count_reg[2]\(2 downto 0),
\gpregsm1.curr_fwft_state_reg[0]\ => \gpregsm1.curr_fwft_state_reg[0]\,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(1),
\out\ => \^out\,
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
ram_full_comb => ram_full_comb,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_wr_logic_6 is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wr_en : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_wr_logic_6 : entity is "wr_logic";
end system_auto_pc_1_wr_logic_6;
architecture STRUCTURE of system_auto_pc_1_wr_logic_6 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^out\ : STD_LOGIC;
signal ram_full_comb : STD_LOGIC;
begin
E(0) <= \^e\(0);
\out\ <= \^out\;
\gwss.wsts\: entity work.system_auto_pc_1_wr_status_flags_ss_14
port map (
E(0) => \^e\(0),
clk => clk,
full => full,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
\out\ => \^out\,
ram_full_comb => ram_full_comb,
wr_en => wr_en
);
wpntr: entity work.system_auto_pc_1_wr_bin_cntr_15
port map (
E(0) => \^e\(0),
Q(4 downto 0) => Q(4 downto 0),
clk => clk,
\gc0.count_d1_reg[2]\ => \gc0.count_d1_reg[2]\,
\gc0.count_d1_reg[4]\(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
\gc0.count_reg[2]\(2 downto 0) => \gc0.count_reg[2]\(2 downto 0),
\gpregsm1.curr_fwft_state_reg[0]\ => \gpregsm1.curr_fwft_state_reg[0]\,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(1),
\out\ => \^out\,
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
ram_full_comb => ram_full_comb,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_fifo_generator_ramfifo is
port (
empty : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 5 downto 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end system_auto_pc_1_fifo_generator_ramfifo;
architecture STRUCTURE of system_auto_pc_1_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gl0.rd_n_12\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal p_0_out_0 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_11_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_17_out : STD_LOGIC;
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 to 1 );
begin
\gntv_or_sync_fifo.gl0.rd\: entity work.system_auto_pc_1_rd_logic_5
port map (
E(0) => ram_rd_en_i,
Q(2 downto 0) => rd_pntr_plus1(2 downto 0),
clk => clk,
empty => empty,
\gcc0.gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.wr_n_3\,
\gcc0.gc0.count_d1_reg[4]\(4 downto 0) => p_11_out(4 downto 0),
\goreg_dm.dout_i_reg[5]\(0) => \gntv_or_sync_fifo.gl0.rd_n_6\,
\gpr1.dout_i_reg[1]\(4 downto 0) => p_0_out_0(4 downto 0),
\out\(1) => rd_rst_i(2),
\out\(0) => rd_rst_i(0),
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.rd_n_4\,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.rd_n_12\,
ram_full_fb_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_0\,
rd_en => rd_en,
wr_en => wr_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.system_auto_pc_1_wr_logic_6
port map (
E(0) => p_17_out,
Q(4 downto 0) => p_11_out(4 downto 0),
clk => clk,
full => full,
\gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.rd_n_4\,
\gc0.count_d1_reg[4]\(4 downto 0) => p_0_out_0(4 downto 0),
\gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gpregsm1.curr_fwft_state_reg[0]\ => \gntv_or_sync_fifo.gl0.rd_n_12\,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(1) => wr_rst_i(1),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => rst_full_ff_i,
\out\ => \gntv_or_sync_fifo.gl0.wr_n_0\,
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\,
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.system_auto_pc_1_memory
port map (
E(0) => \gntv_or_sync_fifo.gl0.rd_n_6\,
EN => p_17_out,
I54(4 downto 0) => p_11_out(4 downto 0),
clk => clk,
din(5 downto 0) => din(5 downto 0),
dout(5 downto 0) => dout(5 downto 0),
\gc0.count_d1_reg[4]\(4 downto 0) => p_0_out_0(4 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => ram_rd_en_i
);
rstblk: entity work.system_auto_pc_1_reset_blk_ramfifo_7
port map (
clk => clk,
\gc0.count_reg[1]\(1) => rd_rst_i(2),
\gc0.count_reg[1]\(0) => rd_rst_i(0),
\out\(1) => wr_rst_i(1),
\out\(0) => rst_full_ff_i,
rst => rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_fifo_generator_ramfifo__parameterized0\ is
port (
empty : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 4 downto 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_fifo_generator_ramfifo__parameterized0\ : entity is "fifo_generator_ramfifo";
end \system_auto_pc_1_fifo_generator_ramfifo__parameterized0\;
architecture STRUCTURE of \system_auto_pc_1_fifo_generator_ramfifo__parameterized0\ is
signal \gntv_or_sync_fifo.gl0.rd_n_12\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal p_0_out_0 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_11_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_17_out : STD_LOGIC;
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 to 1 );
begin
\gntv_or_sync_fifo.gl0.rd\: entity work.system_auto_pc_1_rd_logic
port map (
E(0) => ram_rd_en_i,
Q(2 downto 0) => rd_pntr_plus1(2 downto 0),
clk => clk,
empty => empty,
\gcc0.gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.wr_n_3\,
\gcc0.gc0.count_d1_reg[4]\(4 downto 0) => p_11_out(4 downto 0),
\goreg_dm.dout_i_reg[4]\(0) => \gntv_or_sync_fifo.gl0.rd_n_6\,
\gpr1.dout_i_reg[1]\(4 downto 0) => p_0_out_0(4 downto 0),
\out\(1) => rd_rst_i(2),
\out\(0) => rd_rst_i(0),
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.rd_n_4\,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.rd_n_12\,
ram_full_fb_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_0\,
rd_en => rd_en,
wr_en => wr_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.system_auto_pc_1_wr_logic
port map (
E(0) => p_17_out,
Q(4 downto 0) => p_11_out(4 downto 0),
clk => clk,
full => full,
\gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.rd_n_4\,
\gc0.count_d1_reg[4]\(4 downto 0) => p_0_out_0(4 downto 0),
\gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gpregsm1.curr_fwft_state_reg[0]\ => \gntv_or_sync_fifo.gl0.rd_n_12\,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(1) => wr_rst_i(1),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => rst_full_ff_i,
\out\ => \gntv_or_sync_fifo.gl0.wr_n_0\,
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\,
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.\system_auto_pc_1_memory__parameterized0\
port map (
E(0) => \gntv_or_sync_fifo.gl0.rd_n_6\,
EN => p_17_out,
I55(4 downto 0) => p_11_out(4 downto 0),
clk => clk,
din(4 downto 0) => din(4 downto 0),
dout(4 downto 0) => dout(4 downto 0),
\gc0.count_d1_reg[4]\(4 downto 0) => p_0_out_0(4 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => ram_rd_en_i
);
rstblk: entity work.system_auto_pc_1_reset_blk_ramfifo
port map (
clk => clk,
\gc0.count_reg[1]\(1) => rd_rst_i(2),
\gc0.count_reg[1]\(0) => rd_rst_i(0),
\out\(1) => wr_rst_i(1),
\out\(0) => rst_full_ff_i,
rst => rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_fifo_generator_ramfifo__parameterized1\ is
port (
empty : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_fifo_generator_ramfifo__parameterized1\ : entity is "fifo_generator_ramfifo";
end \system_auto_pc_1_fifo_generator_ramfifo__parameterized1\;
architecture STRUCTURE of \system_auto_pc_1_fifo_generator_ramfifo__parameterized1\ is
signal dout_i : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_13\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_3\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_7\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal \gr1.gr1_int.rfwft/p_0_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_0_out : STD_LOGIC;
signal p_0_out_0 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_11_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_17_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 to 1 );
begin
\gntv_or_sync_fifo.gl0.rd\: entity work.system_auto_pc_1_rd_logic_19
port map (
AR(0) => rd_rst_i(2),
Q(2 downto 0) => rd_pntr_plus1(2 downto 0),
clk => clk,
dout_i => dout_i,
empty => empty,
\gcc0.gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.wr_n_3\,
\gcc0.gc0.count_d1_reg[4]\(4 downto 0) => p_11_out(4 downto 0),
\gpr1.dout_i_reg[0]\ => \gntv_or_sync_fifo.gl0.rd_n_3\,
\gpr1.dout_i_reg[0]_0\(4 downto 0) => p_0_out_0(4 downto 0),
\out\(1) => \gntv_or_sync_fifo.gl0.rd_n_0\,
\out\(0) => \gr1.gr1_int.rfwft/p_0_in\(0),
p_0_out => p_0_out,
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.rd_n_7\,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.rd_n_13\,
ram_full_fb_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_0\,
rd_en => rd_en,
wr_en => wr_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.system_auto_pc_1_wr_logic_20
port map (
E(0) => p_17_out,
Q(4 downto 0) => p_11_out(4 downto 0),
clk => clk,
full => full,
\gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.rd_n_7\,
\gc0.count_d1_reg[4]\(4 downto 0) => p_0_out_0(4 downto 0),
\gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gpregsm1.curr_fwft_state_reg[0]\ => \gntv_or_sync_fifo.gl0.rd_n_13\,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(1) => wr_rst_i(1),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => rst_full_ff_i,
\out\ => \gntv_or_sync_fifo.gl0.wr_n_0\,
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\,
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.\system_auto_pc_1_memory__parameterized1\
port map (
E(0) => p_17_out,
Q(4 downto 0) => p_11_out(4 downto 0),
clk => clk,
din(0) => din(0),
dout(0) => dout(0),
dout_i => dout_i,
\gc0.count_d1_reg[4]\(4 downto 0) => p_0_out_0(4 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\ => \gntv_or_sync_fifo.gl0.rd_n_3\,
\gpregsm1.curr_fwft_state_reg[1]_0\(1) => \gntv_or_sync_fifo.gl0.rd_n_0\,
\gpregsm1.curr_fwft_state_reg[1]_0\(0) => \gr1.gr1_int.rfwft/p_0_in\(0),
\out\(0) => rd_rst_i(0),
p_0_out => p_0_out,
rd_en => rd_en
);
rstblk: entity work.system_auto_pc_1_reset_blk_ramfifo_21
port map (
clk => clk,
\gc0.count_reg[1]\(1) => rd_rst_i(2),
\gc0.count_reg[1]\(0) => rd_rst_i(0),
\out\(1) => wr_rst_i(1),
\out\(0) => rst_full_ff_i,
rst => rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_fifo_generator_top is
port (
empty : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 5 downto 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_fifo_generator_top : entity is "fifo_generator_top";
end system_auto_pc_1_fifo_generator_top;
architecture STRUCTURE of system_auto_pc_1_fifo_generator_top is
begin
\grf.rf\: entity work.system_auto_pc_1_fifo_generator_ramfifo
port map (
clk => clk,
din(5 downto 0) => din(5 downto 0),
dout(5 downto 0) => dout(5 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_fifo_generator_top__parameterized0\ is
port (
empty : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 4 downto 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_fifo_generator_top__parameterized0\ : entity is "fifo_generator_top";
end \system_auto_pc_1_fifo_generator_top__parameterized0\;
architecture STRUCTURE of \system_auto_pc_1_fifo_generator_top__parameterized0\ is
begin
\grf.rf\: entity work.\system_auto_pc_1_fifo_generator_ramfifo__parameterized0\
port map (
clk => clk,
din(4 downto 0) => din(4 downto 0),
dout(4 downto 0) => dout(4 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_fifo_generator_top__parameterized1\ is
port (
empty : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_fifo_generator_top__parameterized1\ : entity is "fifo_generator_top";
end \system_auto_pc_1_fifo_generator_top__parameterized1\;
architecture STRUCTURE of \system_auto_pc_1_fifo_generator_top__parameterized1\ is
begin
\grf.rf\: entity work.\system_auto_pc_1_fifo_generator_ramfifo__parameterized1\
port map (
clk => clk,
din(0) => din(0),
dout(0) => dout(0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_fifo_generator_v13_1_3_synth is
port (
empty : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 5 downto 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_fifo_generator_v13_1_3_synth : entity is "fifo_generator_v13_1_3_synth";
end system_auto_pc_1_fifo_generator_v13_1_3_synth;
architecture STRUCTURE of system_auto_pc_1_fifo_generator_v13_1_3_synth is
begin
\gconvfifo.rf\: entity work.system_auto_pc_1_fifo_generator_top
port map (
clk => clk,
din(5 downto 0) => din(5 downto 0),
dout(5 downto 0) => dout(5 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_fifo_generator_v13_1_3_synth__parameterized0\ is
port (
empty : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 4 downto 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_fifo_generator_v13_1_3_synth__parameterized0\ : entity is "fifo_generator_v13_1_3_synth";
end \system_auto_pc_1_fifo_generator_v13_1_3_synth__parameterized0\;
architecture STRUCTURE of \system_auto_pc_1_fifo_generator_v13_1_3_synth__parameterized0\ is
begin
\gconvfifo.rf\: entity work.\system_auto_pc_1_fifo_generator_top__parameterized0\
port map (
clk => clk,
din(4 downto 0) => din(4 downto 0),
dout(4 downto 0) => dout(4 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_fifo_generator_v13_1_3_synth__parameterized1\ is
port (
empty : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_fifo_generator_v13_1_3_synth__parameterized1\ : entity is "fifo_generator_v13_1_3_synth";
end \system_auto_pc_1_fifo_generator_v13_1_3_synth__parameterized1\;
architecture STRUCTURE of \system_auto_pc_1_fifo_generator_v13_1_3_synth__parameterized1\ is
begin
\gconvfifo.rf\: entity work.\system_auto_pc_1_fifo_generator_top__parameterized1\
port map (
clk => clk,
din(0) => din(0),
dout(0) => dout(0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_fifo_generator_v13_1_3 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 5 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 5 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 64;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 4;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 8;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 4;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 4;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 4;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 2;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 6;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 6;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of system_auto_pc_1_fifo_generator_v13_1_3 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 6;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of system_auto_pc_1_fifo_generator_v13_1_3 : entity is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of system_auto_pc_1_fifo_generator_v13_1_3 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 31;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 30;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 6;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 32;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 5;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 3;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 6;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 32;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 5;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_fifo_generator_v13_1_3 : entity is "fifo_generator_v13_1_3";
end system_auto_pc_1_fifo_generator_v13_1_3;
architecture STRUCTURE of system_auto_pc_1_fifo_generator_v13_1_3 is
signal \<const0>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const0>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const0>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const0>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const0>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const0>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const0>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(3) <= \<const0>\;
m_axi_arid(2) <= \<const0>\;
m_axi_arid(1) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(1) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(3) <= \<const0>\;
m_axi_awid(2) <= \<const0>\;
m_axi_awid(1) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(1) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(63) <= \<const0>\;
m_axis_tdata(62) <= \<const0>\;
m_axis_tdata(61) <= \<const0>\;
m_axis_tdata(60) <= \<const0>\;
m_axis_tdata(59) <= \<const0>\;
m_axis_tdata(58) <= \<const0>\;
m_axis_tdata(57) <= \<const0>\;
m_axis_tdata(56) <= \<const0>\;
m_axis_tdata(55) <= \<const0>\;
m_axis_tdata(54) <= \<const0>\;
m_axis_tdata(53) <= \<const0>\;
m_axis_tdata(52) <= \<const0>\;
m_axis_tdata(51) <= \<const0>\;
m_axis_tdata(50) <= \<const0>\;
m_axis_tdata(49) <= \<const0>\;
m_axis_tdata(48) <= \<const0>\;
m_axis_tdata(47) <= \<const0>\;
m_axis_tdata(46) <= \<const0>\;
m_axis_tdata(45) <= \<const0>\;
m_axis_tdata(44) <= \<const0>\;
m_axis_tdata(43) <= \<const0>\;
m_axis_tdata(42) <= \<const0>\;
m_axis_tdata(41) <= \<const0>\;
m_axis_tdata(40) <= \<const0>\;
m_axis_tdata(39) <= \<const0>\;
m_axis_tdata(38) <= \<const0>\;
m_axis_tdata(37) <= \<const0>\;
m_axis_tdata(36) <= \<const0>\;
m_axis_tdata(35) <= \<const0>\;
m_axis_tdata(34) <= \<const0>\;
m_axis_tdata(33) <= \<const0>\;
m_axis_tdata(32) <= \<const0>\;
m_axis_tdata(31) <= \<const0>\;
m_axis_tdata(30) <= \<const0>\;
m_axis_tdata(29) <= \<const0>\;
m_axis_tdata(28) <= \<const0>\;
m_axis_tdata(27) <= \<const0>\;
m_axis_tdata(26) <= \<const0>\;
m_axis_tdata(25) <= \<const0>\;
m_axis_tdata(24) <= \<const0>\;
m_axis_tdata(23) <= \<const0>\;
m_axis_tdata(22) <= \<const0>\;
m_axis_tdata(21) <= \<const0>\;
m_axis_tdata(20) <= \<const0>\;
m_axis_tdata(19) <= \<const0>\;
m_axis_tdata(18) <= \<const0>\;
m_axis_tdata(17) <= \<const0>\;
m_axis_tdata(16) <= \<const0>\;
m_axis_tdata(15) <= \<const0>\;
m_axis_tdata(14) <= \<const0>\;
m_axis_tdata(13) <= \<const0>\;
m_axis_tdata(12) <= \<const0>\;
m_axis_tdata(11) <= \<const0>\;
m_axis_tdata(10) <= \<const0>\;
m_axis_tdata(9) <= \<const0>\;
m_axis_tdata(8) <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(3) <= \<const0>\;
m_axis_tdest(2) <= \<const0>\;
m_axis_tdest(1) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(7) <= \<const0>\;
m_axis_tid(6) <= \<const0>\;
m_axis_tid(5) <= \<const0>\;
m_axis_tid(4) <= \<const0>\;
m_axis_tid(3) <= \<const0>\;
m_axis_tid(2) <= \<const0>\;
m_axis_tid(1) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(3) <= \<const0>\;
m_axis_tkeep(2) <= \<const0>\;
m_axis_tkeep(1) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(3) <= \<const0>\;
m_axis_tstrb(2) <= \<const0>\;
m_axis_tstrb(1) <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_fifo_gen: entity work.system_auto_pc_1_fifo_generator_v13_1_3_synth
port map (
clk => clk,
din(5 downto 0) => din(5 downto 0),
dout(5 downto 0) => dout(5 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 4 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 64;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 4;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 8;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 4;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 4;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 4;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 2;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 6;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 5;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 5;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 31;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 30;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 6;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 32;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 5;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 3;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 6;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 32;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 5;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is "fifo_generator_v13_1_3";
end \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\;
architecture STRUCTURE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const0>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const0>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const0>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const0>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const0>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const0>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(3) <= \<const0>\;
m_axi_arid(2) <= \<const0>\;
m_axi_arid(1) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(1) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(3) <= \<const0>\;
m_axi_awid(2) <= \<const0>\;
m_axi_awid(1) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(1) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(63) <= \<const0>\;
m_axis_tdata(62) <= \<const0>\;
m_axis_tdata(61) <= \<const0>\;
m_axis_tdata(60) <= \<const0>\;
m_axis_tdata(59) <= \<const0>\;
m_axis_tdata(58) <= \<const0>\;
m_axis_tdata(57) <= \<const0>\;
m_axis_tdata(56) <= \<const0>\;
m_axis_tdata(55) <= \<const0>\;
m_axis_tdata(54) <= \<const0>\;
m_axis_tdata(53) <= \<const0>\;
m_axis_tdata(52) <= \<const0>\;
m_axis_tdata(51) <= \<const0>\;
m_axis_tdata(50) <= \<const0>\;
m_axis_tdata(49) <= \<const0>\;
m_axis_tdata(48) <= \<const0>\;
m_axis_tdata(47) <= \<const0>\;
m_axis_tdata(46) <= \<const0>\;
m_axis_tdata(45) <= \<const0>\;
m_axis_tdata(44) <= \<const0>\;
m_axis_tdata(43) <= \<const0>\;
m_axis_tdata(42) <= \<const0>\;
m_axis_tdata(41) <= \<const0>\;
m_axis_tdata(40) <= \<const0>\;
m_axis_tdata(39) <= \<const0>\;
m_axis_tdata(38) <= \<const0>\;
m_axis_tdata(37) <= \<const0>\;
m_axis_tdata(36) <= \<const0>\;
m_axis_tdata(35) <= \<const0>\;
m_axis_tdata(34) <= \<const0>\;
m_axis_tdata(33) <= \<const0>\;
m_axis_tdata(32) <= \<const0>\;
m_axis_tdata(31) <= \<const0>\;
m_axis_tdata(30) <= \<const0>\;
m_axis_tdata(29) <= \<const0>\;
m_axis_tdata(28) <= \<const0>\;
m_axis_tdata(27) <= \<const0>\;
m_axis_tdata(26) <= \<const0>\;
m_axis_tdata(25) <= \<const0>\;
m_axis_tdata(24) <= \<const0>\;
m_axis_tdata(23) <= \<const0>\;
m_axis_tdata(22) <= \<const0>\;
m_axis_tdata(21) <= \<const0>\;
m_axis_tdata(20) <= \<const0>\;
m_axis_tdata(19) <= \<const0>\;
m_axis_tdata(18) <= \<const0>\;
m_axis_tdata(17) <= \<const0>\;
m_axis_tdata(16) <= \<const0>\;
m_axis_tdata(15) <= \<const0>\;
m_axis_tdata(14) <= \<const0>\;
m_axis_tdata(13) <= \<const0>\;
m_axis_tdata(12) <= \<const0>\;
m_axis_tdata(11) <= \<const0>\;
m_axis_tdata(10) <= \<const0>\;
m_axis_tdata(9) <= \<const0>\;
m_axis_tdata(8) <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(3) <= \<const0>\;
m_axis_tdest(2) <= \<const0>\;
m_axis_tdest(1) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(7) <= \<const0>\;
m_axis_tid(6) <= \<const0>\;
m_axis_tid(5) <= \<const0>\;
m_axis_tid(4) <= \<const0>\;
m_axis_tid(3) <= \<const0>\;
m_axis_tid(2) <= \<const0>\;
m_axis_tid(1) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(3) <= \<const0>\;
m_axis_tkeep(2) <= \<const0>\;
m_axis_tkeep(1) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(3) <= \<const0>\;
m_axis_tstrb(2) <= \<const0>\;
m_axis_tstrb(1) <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_fifo_gen: entity work.\system_auto_pc_1_fifo_generator_v13_1_3_synth__parameterized0\
port map (
clk => clk,
din(4 downto 0) => din(4 downto 0),
dout(4 downto 0) => dout(4 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 0 to 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 64;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 4;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 8;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 4;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 4;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 4;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 2;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 6;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 31;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 30;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 6;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 32;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 5;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 3;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 6;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 32;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 5;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is "fifo_generator_v13_1_3";
end \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\;
architecture STRUCTURE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ is
signal \<const0>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const0>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const0>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const0>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const0>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const0>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const0>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(3) <= \<const0>\;
m_axi_arid(2) <= \<const0>\;
m_axi_arid(1) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(1) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(3) <= \<const0>\;
m_axi_awid(2) <= \<const0>\;
m_axi_awid(1) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(1) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(63) <= \<const0>\;
m_axis_tdata(62) <= \<const0>\;
m_axis_tdata(61) <= \<const0>\;
m_axis_tdata(60) <= \<const0>\;
m_axis_tdata(59) <= \<const0>\;
m_axis_tdata(58) <= \<const0>\;
m_axis_tdata(57) <= \<const0>\;
m_axis_tdata(56) <= \<const0>\;
m_axis_tdata(55) <= \<const0>\;
m_axis_tdata(54) <= \<const0>\;
m_axis_tdata(53) <= \<const0>\;
m_axis_tdata(52) <= \<const0>\;
m_axis_tdata(51) <= \<const0>\;
m_axis_tdata(50) <= \<const0>\;
m_axis_tdata(49) <= \<const0>\;
m_axis_tdata(48) <= \<const0>\;
m_axis_tdata(47) <= \<const0>\;
m_axis_tdata(46) <= \<const0>\;
m_axis_tdata(45) <= \<const0>\;
m_axis_tdata(44) <= \<const0>\;
m_axis_tdata(43) <= \<const0>\;
m_axis_tdata(42) <= \<const0>\;
m_axis_tdata(41) <= \<const0>\;
m_axis_tdata(40) <= \<const0>\;
m_axis_tdata(39) <= \<const0>\;
m_axis_tdata(38) <= \<const0>\;
m_axis_tdata(37) <= \<const0>\;
m_axis_tdata(36) <= \<const0>\;
m_axis_tdata(35) <= \<const0>\;
m_axis_tdata(34) <= \<const0>\;
m_axis_tdata(33) <= \<const0>\;
m_axis_tdata(32) <= \<const0>\;
m_axis_tdata(31) <= \<const0>\;
m_axis_tdata(30) <= \<const0>\;
m_axis_tdata(29) <= \<const0>\;
m_axis_tdata(28) <= \<const0>\;
m_axis_tdata(27) <= \<const0>\;
m_axis_tdata(26) <= \<const0>\;
m_axis_tdata(25) <= \<const0>\;
m_axis_tdata(24) <= \<const0>\;
m_axis_tdata(23) <= \<const0>\;
m_axis_tdata(22) <= \<const0>\;
m_axis_tdata(21) <= \<const0>\;
m_axis_tdata(20) <= \<const0>\;
m_axis_tdata(19) <= \<const0>\;
m_axis_tdata(18) <= \<const0>\;
m_axis_tdata(17) <= \<const0>\;
m_axis_tdata(16) <= \<const0>\;
m_axis_tdata(15) <= \<const0>\;
m_axis_tdata(14) <= \<const0>\;
m_axis_tdata(13) <= \<const0>\;
m_axis_tdata(12) <= \<const0>\;
m_axis_tdata(11) <= \<const0>\;
m_axis_tdata(10) <= \<const0>\;
m_axis_tdata(9) <= \<const0>\;
m_axis_tdata(8) <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(3) <= \<const0>\;
m_axis_tdest(2) <= \<const0>\;
m_axis_tdest(1) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(7) <= \<const0>\;
m_axis_tid(6) <= \<const0>\;
m_axis_tid(5) <= \<const0>\;
m_axis_tid(4) <= \<const0>\;
m_axis_tid(3) <= \<const0>\;
m_axis_tid(2) <= \<const0>\;
m_axis_tid(1) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(3) <= \<const0>\;
m_axis_tkeep(2) <= \<const0>\;
m_axis_tkeep(1) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(3) <= \<const0>\;
m_axis_tstrb(2) <= \<const0>\;
m_axis_tstrb(1) <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_fifo_gen: entity work.\system_auto_pc_1_fifo_generator_v13_1_3_synth__parameterized1\
port map (
clk => clk,
din(0) => din(0),
dout(0) => dout(0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_axi_data_fifo_v2_1_10_fifo_gen is
port (
dout : out STD_LOGIC_VECTOR ( 5 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
din : out STD_LOGIC_VECTOR ( 3 downto 0 );
\USE_B_CHANNEL.cmd_b_empty_reg\ : out STD_LOGIC;
\USE_B_CHANNEL.cmd_b_empty_reg_0\ : out STD_LOGIC;
\length_counter_1_reg_0__s_port_]\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
aclk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
wr_en : in STD_LOGIC;
wr_cmd_ready : in STD_LOGIC;
cmd_empty : in STD_LOGIC;
cmd_b_empty : in STD_LOGIC;
queue_id : in STD_LOGIC_VECTOR ( 1 downto 0 );
cmd_push_block : in STD_LOGIC;
command_ongoing : in STD_LOGIC;
aresetn : in STD_LOGIC;
first_mi_word : in STD_LOGIC;
length_counter_1_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
\S_AXI_ALEN_Q_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\pushed_commands_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
need_to_split_q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_axi_data_fifo_v2_1_10_fifo_gen : entity is "axi_data_fifo_v2_1_10_fifo_gen";
end system_auto_pc_1_axi_data_fifo_v2_1_10_fifo_gen;
architecture STRUCTURE of system_auto_pc_1_axi_data_fifo_v2_1_10_fifo_gen is
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^din\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^dout\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^empty\ : STD_LOGIC;
signal \length_counter_1_reg_0__s_net_1\ : STD_LOGIC;
signal NLW_fifo_gen_inst_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_valid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_fifo_gen_inst_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of fifo_gen_inst : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of fifo_gen_inst : label is 64;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of fifo_gen_inst : label is 4;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of fifo_gen_inst : label is 8;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of fifo_gen_inst : label is 4;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of fifo_gen_inst : label is 4;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of fifo_gen_inst : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of fifo_gen_inst : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of fifo_gen_inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of fifo_gen_inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of fifo_gen_inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of fifo_gen_inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of fifo_gen_inst : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of fifo_gen_inst : label is 4;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of fifo_gen_inst : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of fifo_gen_inst : label is 2;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of fifo_gen_inst : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of fifo_gen_inst : label is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of fifo_gen_inst : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of fifo_gen_inst : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of fifo_gen_inst : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of fifo_gen_inst : label is 6;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of fifo_gen_inst : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of fifo_gen_inst : label is 6;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of fifo_gen_inst : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of fifo_gen_inst : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of fifo_gen_inst : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of fifo_gen_inst : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of fifo_gen_inst : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of fifo_gen_inst : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of fifo_gen_inst : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of fifo_gen_inst : label is 6;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of fifo_gen_inst : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of fifo_gen_inst : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of fifo_gen_inst : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of fifo_gen_inst : label is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of fifo_gen_inst : label is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of fifo_gen_inst : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of fifo_gen_inst : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of fifo_gen_inst : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of fifo_gen_inst : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of fifo_gen_inst : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of fifo_gen_inst : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of fifo_gen_inst : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of fifo_gen_inst : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of fifo_gen_inst : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of fifo_gen_inst : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of fifo_gen_inst : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of fifo_gen_inst : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of fifo_gen_inst : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of fifo_gen_inst : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of fifo_gen_inst : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of fifo_gen_inst : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of fifo_gen_inst : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of fifo_gen_inst : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of fifo_gen_inst : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of fifo_gen_inst : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of fifo_gen_inst : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of fifo_gen_inst : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of fifo_gen_inst : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of fifo_gen_inst : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of fifo_gen_inst : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of fifo_gen_inst : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of fifo_gen_inst : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of fifo_gen_inst : label is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of fifo_gen_inst : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of fifo_gen_inst : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of fifo_gen_inst : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of fifo_gen_inst : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of fifo_gen_inst : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of fifo_gen_inst : label is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of fifo_gen_inst : label is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of fifo_gen_inst : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of fifo_gen_inst : label is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of fifo_gen_inst : label is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of fifo_gen_inst : label is 31;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of fifo_gen_inst : label is 30;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of fifo_gen_inst : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of fifo_gen_inst : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of fifo_gen_inst : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of fifo_gen_inst : label is 6;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of fifo_gen_inst : label is 32;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of fifo_gen_inst : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of fifo_gen_inst : label is 5;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of fifo_gen_inst : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of fifo_gen_inst : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of fifo_gen_inst : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of fifo_gen_inst : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of fifo_gen_inst : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of fifo_gen_inst : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of fifo_gen_inst : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of fifo_gen_inst : label is 3;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of fifo_gen_inst : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of fifo_gen_inst : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of fifo_gen_inst : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of fifo_gen_inst : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of fifo_gen_inst : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of fifo_gen_inst : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of fifo_gen_inst : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of fifo_gen_inst : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of fifo_gen_inst : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of fifo_gen_inst : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of fifo_gen_inst : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of fifo_gen_inst : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of fifo_gen_inst : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of fifo_gen_inst : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of fifo_gen_inst : label is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of fifo_gen_inst : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of fifo_gen_inst : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of fifo_gen_inst : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of fifo_gen_inst : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of fifo_gen_inst : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of fifo_gen_inst : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of fifo_gen_inst : label is 6;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of fifo_gen_inst : label is 32;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of fifo_gen_inst : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of fifo_gen_inst : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of fifo_gen_inst : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of fifo_gen_inst : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of fifo_gen_inst : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of fifo_gen_inst : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of fifo_gen_inst : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of fifo_gen_inst : label is 5;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of fifo_gen_inst : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of fifo_gen_inst : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of fifo_gen_inst : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of fifo_gen_inst : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of fifo_gen_inst : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of fifo_gen_inst : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of fifo_gen_inst : label is 1;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of m_axi_wvalid_INST_0 : label is "soft_lutpair32";
attribute SOFT_HLUTNM of s_axi_wready_INST_0 : label is "soft_lutpair32";
begin
SR(0) <= \^sr\(0);
din(3 downto 0) <= \^din\(3 downto 0);
dout(5 downto 0) <= \^dout\(5 downto 0);
empty <= \^empty\;
\length_counter_1_reg_0__s_port_]\ <= \length_counter_1_reg_0__s_net_1\;
S_AXI_AREADY_I_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn,
O => \^sr\(0)
);
fifo_gen_inst: entity work.system_auto_pc_1_fifo_generator_v13_1_3
port map (
almost_empty => NLW_fifo_gen_inst_almost_empty_UNCONNECTED,
almost_full => NLW_fifo_gen_inst_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_fifo_gen_inst_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_fifo_gen_inst_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_fifo_gen_inst_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => aclk,
data_count(5 downto 0) => NLW_fifo_gen_inst_data_count_UNCONNECTED(5 downto 0),
dbiterr => NLW_fifo_gen_inst_dbiterr_UNCONNECTED,
din(5 downto 4) => Q(1 downto 0),
din(3 downto 0) => \^din\(3 downto 0),
dout(5 downto 0) => \^dout\(5 downto 0),
empty => \^empty\,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(3 downto 0) => NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED(3 downto 0),
m_axi_arlen(7 downto 0) => NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(1 downto 0) => NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED(1 downto 0),
m_axi_arprot(2 downto 0) => NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(3 downto 0) => NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED(3 downto 0),
m_axi_awlen(7 downto 0) => NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(1 downto 0) => NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED(1 downto 0),
m_axi_awprot(2 downto 0) => NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED,
m_axi_bid(3 downto 0) => B"0000",
m_axi_bready => NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(3 downto 0) => B"0000",
m_axi_rlast => '0',
m_axi_rready => NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(3 downto 0) => NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED(3 downto 0),
m_axi_wlast => NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(63 downto 0) => NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED(63 downto 0),
m_axis_tdest(3 downto 0) => NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED(3 downto 0),
m_axis_tid(7 downto 0) => NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED(7 downto 0),
m_axis_tkeep(3 downto 0) => NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED(3 downto 0),
m_axis_tlast => NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(3 downto 0) => NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED(3 downto 0),
m_axis_tuser(3 downto 0) => NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED,
overflow => NLW_fifo_gen_inst_overflow_UNCONNECTED,
prog_empty => NLW_fifo_gen_inst_prog_empty_UNCONNECTED,
prog_empty_thresh(4 downto 0) => B"00000",
prog_empty_thresh_assert(4 downto 0) => B"00000",
prog_empty_thresh_negate(4 downto 0) => B"00000",
prog_full => NLW_fifo_gen_inst_prog_full_UNCONNECTED,
prog_full_thresh(4 downto 0) => B"00000",
prog_full_thresh_assert(4 downto 0) => B"00000",
prog_full_thresh_negate(4 downto 0) => B"00000",
rd_clk => '0',
rd_data_count(5 downto 0) => NLW_fifo_gen_inst_rd_data_count_UNCONNECTED(5 downto 0),
rd_en => wr_cmd_ready,
rd_rst => '0',
rd_rst_busy => NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED,
rst => \^sr\(0),
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(1 downto 0) => B"00",
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(1 downto 0) => B"00",
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(3 downto 0) => NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(3 downto 0) => B"0000",
s_axi_wlast => '0',
s_axi_wready => NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axis_tdest(3 downto 0) => B"0000",
s_axis_tid(7 downto 0) => B"00000000",
s_axis_tkeep(3 downto 0) => B"0000",
s_axis_tlast => '0',
s_axis_tready => NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED,
s_axis_tstrb(3 downto 0) => B"0000",
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_fifo_gen_inst_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_fifo_gen_inst_underflow_UNCONNECTED,
valid => NLW_fifo_gen_inst_valid_UNCONNECTED,
wr_ack => NLW_fifo_gen_inst_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(5 downto 0) => NLW_fifo_gen_inst_wr_data_count_UNCONNECTED(5 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED
);
\length_counter_1[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F047F0F0F0F0F0"
)
port map (
I0 => \^dout\(0),
I1 => first_mi_word,
I2 => length_counter_1_reg(0),
I3 => m_axi_wready,
I4 => \^empty\,
I5 => s_axi_wvalid,
O => \length_counter_1_reg_0__s_net_1\
);
\m_axi_awlen[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFEAAAAAAAA"
)
port map (
I0 => \S_AXI_ALEN_Q_reg[3]\(0),
I1 => \pushed_commands_reg[3]\(1),
I2 => \pushed_commands_reg[3]\(0),
I3 => \pushed_commands_reg[3]\(3),
I4 => \pushed_commands_reg[3]\(2),
I5 => need_to_split_q,
O => \^din\(0)
);
\m_axi_awlen[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFEAAAAAAAA"
)
port map (
I0 => \S_AXI_ALEN_Q_reg[3]\(1),
I1 => \pushed_commands_reg[3]\(1),
I2 => \pushed_commands_reg[3]\(0),
I3 => \pushed_commands_reg[3]\(3),
I4 => \pushed_commands_reg[3]\(2),
I5 => need_to_split_q,
O => \^din\(1)
);
\m_axi_awlen[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFEAAAAAAAA"
)
port map (
I0 => \S_AXI_ALEN_Q_reg[3]\(2),
I1 => \pushed_commands_reg[3]\(1),
I2 => \pushed_commands_reg[3]\(0),
I3 => \pushed_commands_reg[3]\(3),
I4 => \pushed_commands_reg[3]\(2),
I5 => need_to_split_q,
O => \^din\(2)
);
\m_axi_awlen[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFEAAAAAAAA"
)
port map (
I0 => \S_AXI_ALEN_Q_reg[3]\(3),
I1 => \pushed_commands_reg[3]\(1),
I2 => \pushed_commands_reg[3]\(0),
I3 => \pushed_commands_reg[3]\(3),
I4 => \pushed_commands_reg[3]\(2),
I5 => need_to_split_q,
O => \^din\(3)
);
m_axi_awvalid_INST_0_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => cmd_push_block,
I1 => command_ongoing,
O => \USE_B_CHANNEL.cmd_b_empty_reg_0\
);
m_axi_awvalid_INST_0_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0770777777770770"
)
port map (
I0 => cmd_empty,
I1 => cmd_b_empty,
I2 => queue_id(1),
I3 => Q(1),
I4 => queue_id(0),
I5 => Q(0),
O => \USE_B_CHANNEL.cmd_b_empty_reg\
);
m_axi_wvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wvalid,
I1 => \^empty\,
O => m_axi_wvalid
);
s_axi_wready_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => m_axi_wready,
I1 => \^empty\,
I2 => s_axi_wvalid,
O => s_axi_wready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_axi_data_fifo_v2_1_10_fifo_gen__parameterized0\ is
port (
first_mi_word_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.user_valid_reg\ : out STD_LOGIC;
din : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
wr_en : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
multiple_id_non_split_reg : out STD_LOGIC;
split_in_progress_reg : out STD_LOGIC;
cmd_push_block_reg : out STD_LOGIC;
\pushed_commands_reg[0]\ : out STD_LOGIC;
cmd_empty_reg : out STD_LOGIC;
\queue_id_reg[0]\ : out STD_LOGIC;
\queue_id_reg[1]\ : out STD_LOGIC;
cmd_b_push_block_reg : out STD_LOGIC;
\USE_B_CHANNEL.cmd_b_depth_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\USE_B_CHANNEL.cmd_b_empty_reg\ : out STD_LOGIC;
\USE_B_CHANNEL.cmd_b_depth_reg[5]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_awvalid : out STD_LOGIC;
S_AXI_AREADY_I_reg : out STD_LOGIC;
command_ongoing_reg : out STD_LOGIC;
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\num_transactions_q_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
wr_cmd_b_ready : in STD_LOGIC;
almost_empty : in STD_LOGIC;
wr_cmd_ready : in STD_LOGIC;
cmd_empty : in STD_LOGIC;
aresetn : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
need_to_split_q : in STD_LOGIC;
cmd_push_block : in STD_LOGIC;
multiple_id_non_split : in STD_LOGIC;
\S_AXI_AID_Q_reg[0]\ : in STD_LOGIC;
incr_need_to_split_q_reg : in STD_LOGIC;
split_in_progress_reg_0 : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\S_AXI_AID_Q_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
queue_id : in STD_LOGIC_VECTOR ( 1 downto 0 );
cmd_b_push_block : in STD_LOGIC;
S_AXI_AREADY_I_reg_0 : in STD_LOGIC;
almost_b_empty : in STD_LOGIC;
cmd_b_empty : in STD_LOGIC;
\USE_B_CHANNEL.cmd_b_depth_reg[5]_1\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
\goreg_dm.dout_i_reg[4]\ : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
cmd_push_block_reg_0 : in STD_LOGIC;
cmd_empty_reg_0 : in STD_LOGIC;
command_ongoing : in STD_LOGIC;
full : in STD_LOGIC;
access_is_incr_q : in STD_LOGIC;
\pushed_commands_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\areset_d_reg[0]\ : in STD_LOGIC;
areset_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
\areset_d_reg[1]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_axi_data_fifo_v2_1_10_fifo_gen__parameterized0\ : entity is "axi_data_fifo_v2_1_10_fifo_gen";
end \system_auto_pc_1_axi_data_fifo_v2_1_10_fifo_gen__parameterized0\;
architecture STRUCTURE of \system_auto_pc_1_axi_data_fifo_v2_1_10_fifo_gen__parameterized0\ is
signal S_AXI_AREADY_I_i_3_n_0 : STD_LOGIC;
signal S_AXI_AREADY_I_i_4_n_0 : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_depth[5]_i_3_n_0\ : STD_LOGIC;
signal cmd_b_empty0 : STD_LOGIC;
signal cmd_b_push : STD_LOGIC;
signal \cmd_depth[4]_i_2_n_0\ : STD_LOGIC;
signal \cmd_depth[5]_i_3_n_0\ : STD_LOGIC;
signal \cmd_depth[5]_i_4_n_0\ : STD_LOGIC;
signal \^din\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal full_0 : STD_LOGIC;
signal \^gpregsm1.user_valid_reg\ : STD_LOGIC;
signal m_axi_awvalid_INST_0_i_1_n_0 : STD_LOGIC;
signal m_axi_awvalid_INST_0_i_3_n_0 : STD_LOGIC;
signal \multiple_id_non_split_i_4__0_n_0\ : STD_LOGIC;
signal multiple_id_non_split_i_5_n_0 : STD_LOGIC;
signal \^pushed_commands_reg[0]\ : STD_LOGIC;
signal NLW_fifo_gen_inst_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_valid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_fifo_gen_inst_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \USE_B_CHANNEL.cmd_b_depth[2]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \USE_B_CHANNEL.cmd_b_depth[3]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \USE_B_CHANNEL.cmd_b_depth[5]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \USE_B_CHANNEL.cmd_b_empty_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of cmd_b_push_block_i_1 : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \cmd_depth[2]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \cmd_depth[3]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \cmd_depth[4]_i_2\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \cmd_depth[5]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \cmd_depth[5]_i_4\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of cmd_empty_i_1 : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \cmd_push_block_i_1__0\ : label is "soft_lutpair37";
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of fifo_gen_inst : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of fifo_gen_inst : label is 64;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of fifo_gen_inst : label is 4;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of fifo_gen_inst : label is 8;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of fifo_gen_inst : label is 4;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of fifo_gen_inst : label is 4;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of fifo_gen_inst : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of fifo_gen_inst : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of fifo_gen_inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of fifo_gen_inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of fifo_gen_inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of fifo_gen_inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of fifo_gen_inst : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of fifo_gen_inst : label is 4;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of fifo_gen_inst : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of fifo_gen_inst : label is 2;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of fifo_gen_inst : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of fifo_gen_inst : label is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of fifo_gen_inst : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of fifo_gen_inst : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of fifo_gen_inst : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of fifo_gen_inst : label is 6;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of fifo_gen_inst : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of fifo_gen_inst : label is 5;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of fifo_gen_inst : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of fifo_gen_inst : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of fifo_gen_inst : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of fifo_gen_inst : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of fifo_gen_inst : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of fifo_gen_inst : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of fifo_gen_inst : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of fifo_gen_inst : label is 5;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of fifo_gen_inst : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of fifo_gen_inst : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of fifo_gen_inst : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of fifo_gen_inst : label is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of fifo_gen_inst : label is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of fifo_gen_inst : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of fifo_gen_inst : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of fifo_gen_inst : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of fifo_gen_inst : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of fifo_gen_inst : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of fifo_gen_inst : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of fifo_gen_inst : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of fifo_gen_inst : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of fifo_gen_inst : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of fifo_gen_inst : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of fifo_gen_inst : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of fifo_gen_inst : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of fifo_gen_inst : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of fifo_gen_inst : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of fifo_gen_inst : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of fifo_gen_inst : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of fifo_gen_inst : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of fifo_gen_inst : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of fifo_gen_inst : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of fifo_gen_inst : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of fifo_gen_inst : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of fifo_gen_inst : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of fifo_gen_inst : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of fifo_gen_inst : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of fifo_gen_inst : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of fifo_gen_inst : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of fifo_gen_inst : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of fifo_gen_inst : label is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of fifo_gen_inst : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of fifo_gen_inst : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of fifo_gen_inst : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of fifo_gen_inst : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of fifo_gen_inst : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of fifo_gen_inst : label is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of fifo_gen_inst : label is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of fifo_gen_inst : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of fifo_gen_inst : label is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of fifo_gen_inst : label is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of fifo_gen_inst : label is 31;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of fifo_gen_inst : label is 30;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of fifo_gen_inst : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of fifo_gen_inst : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of fifo_gen_inst : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of fifo_gen_inst : label is 6;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of fifo_gen_inst : label is 32;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of fifo_gen_inst : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of fifo_gen_inst : label is 5;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of fifo_gen_inst : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of fifo_gen_inst : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of fifo_gen_inst : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of fifo_gen_inst : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of fifo_gen_inst : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of fifo_gen_inst : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of fifo_gen_inst : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of fifo_gen_inst : label is 3;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of fifo_gen_inst : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of fifo_gen_inst : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of fifo_gen_inst : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of fifo_gen_inst : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of fifo_gen_inst : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of fifo_gen_inst : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of fifo_gen_inst : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of fifo_gen_inst : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of fifo_gen_inst : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of fifo_gen_inst : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of fifo_gen_inst : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of fifo_gen_inst : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of fifo_gen_inst : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of fifo_gen_inst : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of fifo_gen_inst : label is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of fifo_gen_inst : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of fifo_gen_inst : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of fifo_gen_inst : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of fifo_gen_inst : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of fifo_gen_inst : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of fifo_gen_inst : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of fifo_gen_inst : label is 6;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of fifo_gen_inst : label is 32;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of fifo_gen_inst : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of fifo_gen_inst : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of fifo_gen_inst : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of fifo_gen_inst : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of fifo_gen_inst : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of fifo_gen_inst : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of fifo_gen_inst : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of fifo_gen_inst : label is 5;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of fifo_gen_inst : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of fifo_gen_inst : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of fifo_gen_inst : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of fifo_gen_inst : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of fifo_gen_inst : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of fifo_gen_inst : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of fifo_gen_inst : label is 1;
attribute SOFT_HLUTNM of \fifo_gen_inst_i_1__1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of fifo_gen_inst_i_2 : label is "soft_lutpair44";
attribute SOFT_HLUTNM of m_axi_awvalid_INST_0 : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \queue_id[1]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \split_in_progress_i_1__0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of split_ongoing_i_1 : label is "soft_lutpair45";
begin
din(0) <= \^din\(0);
\gpregsm1.user_valid_reg\ <= \^gpregsm1.user_valid_reg\;
\pushed_commands_reg[0]\ <= \^pushed_commands_reg[0]\;
\S_AXI_AREADY_I_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"444444F4FFFF44F4"
)
port map (
I0 => \areset_d_reg[0]\,
I1 => areset_d(0),
I2 => \^pushed_commands_reg[0]\,
I3 => S_AXI_AREADY_I_i_3_n_0,
I4 => S_AXI_AREADY_I_reg_0,
I5 => s_axi_awvalid,
O => S_AXI_AREADY_I_reg
);
S_AXI_AREADY_I_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"8AA8AAAAAAAA8AA8"
)
port map (
I0 => access_is_incr_q,
I1 => S_AXI_AREADY_I_i_4_n_0,
I2 => \num_transactions_q_reg[3]\(1),
I3 => \pushed_commands_reg[3]\(1),
I4 => \num_transactions_q_reg[3]\(3),
I5 => \pushed_commands_reg[3]\(3),
O => S_AXI_AREADY_I_i_3_n_0
);
S_AXI_AREADY_I_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \num_transactions_q_reg[3]\(2),
I1 => \pushed_commands_reg[3]\(2),
I2 => \num_transactions_q_reg[3]\(0),
I3 => \pushed_commands_reg[3]\(0),
O => S_AXI_AREADY_I_i_4_n_0
);
\USE_B_CHANNEL.cmd_b_depth[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => cmd_b_empty0,
I1 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(0),
I2 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(1),
O => \USE_B_CHANNEL.cmd_b_depth_reg[5]_0\(0)
);
\USE_B_CHANNEL.cmd_b_depth[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AA9"
)
port map (
I0 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(2),
I1 => cmd_b_empty0,
I2 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(0),
I3 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(1),
O => \USE_B_CHANNEL.cmd_b_depth_reg[5]_0\(1)
);
\USE_B_CHANNEL.cmd_b_depth[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFE8001"
)
port map (
I0 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(1),
I1 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(0),
I2 => cmd_b_empty0,
I3 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(2),
I4 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(3),
O => \USE_B_CHANNEL.cmd_b_depth_reg[5]_0\(2)
);
\USE_B_CHANNEL.cmd_b_depth[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAA9"
)
port map (
I0 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(4),
I1 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(3),
I2 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(2),
I3 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(1),
I4 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(0),
I5 => cmd_b_empty0,
O => \USE_B_CHANNEL.cmd_b_depth_reg[5]_0\(3)
);
\USE_B_CHANNEL.cmd_b_depth[4]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => m_axi_awvalid_INST_0_i_1_n_0,
I1 => cmd_b_push_block,
I2 => wr_cmd_b_ready,
O => cmd_b_empty0
);
\USE_B_CHANNEL.cmd_b_depth[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => cmd_b_push_block,
I1 => m_axi_awvalid_INST_0_i_1_n_0,
I2 => wr_cmd_b_ready,
O => \USE_B_CHANNEL.cmd_b_depth_reg[5]\(0)
);
\USE_B_CHANNEL.cmd_b_depth[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA6AA9AAAAAAA9AA"
)
port map (
I0 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(5),
I1 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(3),
I2 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(2),
I3 => \USE_B_CHANNEL.cmd_b_depth[5]_i_3_n_0\,
I4 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(4),
I5 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(1),
O => \USE_B_CHANNEL.cmd_b_depth_reg[5]_0\(4)
);
\USE_B_CHANNEL.cmd_b_depth[5]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABABABABABABAB08"
)
port map (
I0 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(2),
I1 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(1),
I2 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(0),
I3 => m_axi_awvalid_INST_0_i_1_n_0,
I4 => cmd_b_push_block,
I5 => wr_cmd_b_ready,
O => \USE_B_CHANNEL.cmd_b_depth[5]_i_3_n_0\
);
\USE_B_CHANNEL.cmd_b_empty_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F1EEE000"
)
port map (
I0 => cmd_b_push_block,
I1 => m_axi_awvalid_INST_0_i_1_n_0,
I2 => almost_b_empty,
I3 => wr_cmd_b_ready,
I4 => cmd_b_empty,
O => \USE_B_CHANNEL.cmd_b_empty_reg\
);
cmd_b_push_block_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"00B0"
)
port map (
I0 => cmd_b_push_block,
I1 => m_axi_awvalid_INST_0_i_1_n_0,
I2 => aresetn,
I3 => S_AXI_AREADY_I_reg_0,
O => cmd_b_push_block_reg
);
\cmd_depth[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cmd_depth[4]_i_2_n_0\,
I1 => Q(0),
I2 => Q(1),
O => D(0)
);
\cmd_depth[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9AA6"
)
port map (
I0 => Q(2),
I1 => \cmd_depth[4]_i_2_n_0\,
I2 => Q(0),
I3 => Q(1),
O => D(1)
);
\cmd_depth[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7EF0810"
)
port map (
I0 => Q(1),
I1 => Q(0),
I2 => \cmd_depth[4]_i_2_n_0\,
I3 => Q(2),
I4 => Q(3),
O => D(2)
);
\cmd_depth[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9AAAAAAAAAAAAAA6"
)
port map (
I0 => Q(4),
I1 => \cmd_depth[4]_i_2_n_0\,
I2 => Q(0),
I3 => Q(1),
I4 => Q(2),
I5 => Q(3),
O => D(3)
);
\cmd_depth[4]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => wr_cmd_ready,
I1 => m_axi_awvalid_INST_0_i_1_n_0,
I2 => cmd_push_block,
O => \cmd_depth[4]_i_2_n_0\
);
\cmd_depth[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => cmd_push_block,
I1 => m_axi_awvalid_INST_0_i_1_n_0,
I2 => wr_cmd_ready,
O => E(0)
);
\cmd_depth[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA65AAAAAA6"
)
port map (
I0 => Q(5),
I1 => \cmd_depth[5]_i_3_n_0\,
I2 => Q(3),
I3 => Q(2),
I4 => Q(4),
I5 => \cmd_depth[5]_i_4_n_0\,
O => D(4)
);
\cmd_depth[5]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFFFFFF000000FE"
)
port map (
I0 => cmd_push_block,
I1 => m_axi_awvalid_INST_0_i_1_n_0,
I2 => wr_cmd_ready,
I3 => Q(0),
I4 => Q(1),
I5 => Q(2),
O => \cmd_depth[5]_i_3_n_0\
);
\cmd_depth[5]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFFFFFF"
)
port map (
I0 => cmd_push_block,
I1 => m_axi_awvalid_INST_0_i_1_n_0,
I2 => wr_cmd_ready,
I3 => Q(0),
I4 => Q(1),
O => \cmd_depth[5]_i_4_n_0\
);
cmd_empty_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"F1EEE000"
)
port map (
I0 => cmd_push_block,
I1 => m_axi_awvalid_INST_0_i_1_n_0,
I2 => almost_empty,
I3 => wr_cmd_ready,
I4 => cmd_empty,
O => cmd_empty_reg
);
\cmd_push_block_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000AB00"
)
port map (
I0 => cmd_push_block,
I1 => m_axi_awvalid_INST_0_i_1_n_0,
I2 => m_axi_awready,
I3 => aresetn,
I4 => \^pushed_commands_reg[0]\,
O => cmd_push_block_reg
);
command_ongoing_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFDDD0000F000"
)
port map (
I0 => \^pushed_commands_reg[0]\,
I1 => S_AXI_AREADY_I_i_3_n_0,
I2 => S_AXI_AREADY_I_reg_0,
I3 => s_axi_awvalid,
I4 => \areset_d_reg[1]\,
I5 => command_ongoing,
O => command_ongoing_reg
);
fifo_gen_inst: entity work.\system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\
port map (
almost_empty => NLW_fifo_gen_inst_almost_empty_UNCONNECTED,
almost_full => NLW_fifo_gen_inst_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_fifo_gen_inst_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_fifo_gen_inst_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_fifo_gen_inst_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => aclk,
data_count(5 downto 0) => NLW_fifo_gen_inst_data_count_UNCONNECTED(5 downto 0),
dbiterr => NLW_fifo_gen_inst_dbiterr_UNCONNECTED,
din(4) => \^din\(0),
din(3 downto 0) => \num_transactions_q_reg[3]\(3 downto 0),
dout(4 downto 0) => first_mi_word_reg(4 downto 0),
empty => \^gpregsm1.user_valid_reg\,
full => full_0,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(3 downto 0) => NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED(3 downto 0),
m_axi_arlen(7 downto 0) => NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(1 downto 0) => NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED(1 downto 0),
m_axi_arprot(2 downto 0) => NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(3 downto 0) => NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED(3 downto 0),
m_axi_awlen(7 downto 0) => NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(1 downto 0) => NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED(1 downto 0),
m_axi_awprot(2 downto 0) => NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED,
m_axi_bid(3 downto 0) => B"0000",
m_axi_bready => NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(3 downto 0) => B"0000",
m_axi_rlast => '0',
m_axi_rready => NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(3 downto 0) => NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED(3 downto 0),
m_axi_wlast => NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(63 downto 0) => NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED(63 downto 0),
m_axis_tdest(3 downto 0) => NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED(3 downto 0),
m_axis_tid(7 downto 0) => NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED(7 downto 0),
m_axis_tkeep(3 downto 0) => NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED(3 downto 0),
m_axis_tlast => NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(3 downto 0) => NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED(3 downto 0),
m_axis_tuser(3 downto 0) => NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED,
overflow => NLW_fifo_gen_inst_overflow_UNCONNECTED,
prog_empty => NLW_fifo_gen_inst_prog_empty_UNCONNECTED,
prog_empty_thresh(4 downto 0) => B"00000",
prog_empty_thresh_assert(4 downto 0) => B"00000",
prog_empty_thresh_negate(4 downto 0) => B"00000",
prog_full => NLW_fifo_gen_inst_prog_full_UNCONNECTED,
prog_full_thresh(4 downto 0) => B"00000",
prog_full_thresh_assert(4 downto 0) => B"00000",
prog_full_thresh_negate(4 downto 0) => B"00000",
rd_clk => '0',
rd_data_count(5 downto 0) => NLW_fifo_gen_inst_rd_data_count_UNCONNECTED(5 downto 0),
rd_en => wr_cmd_b_ready,
rd_rst => '0',
rd_rst_busy => NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED,
rst => SR(0),
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(1 downto 0) => B"00",
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(1 downto 0) => B"00",
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(3 downto 0) => NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(3 downto 0) => B"0000",
s_axi_wlast => '0',
s_axi_wready => NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axis_tdest(3 downto 0) => B"0000",
s_axis_tid(7 downto 0) => B"00000000",
s_axis_tkeep(3 downto 0) => B"0000",
s_axis_tlast => '0',
s_axis_tready => NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED,
s_axis_tstrb(3 downto 0) => B"0000",
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_fifo_gen_inst_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_fifo_gen_inst_underflow_UNCONNECTED,
valid => NLW_fifo_gen_inst_valid_UNCONNECTED,
wr_ack => NLW_fifo_gen_inst_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(5 downto 0) => NLW_fifo_gen_inst_wr_data_count_UNCONNECTED(5 downto 0),
wr_en => cmd_b_push,
wr_rst => '0',
wr_rst_busy => NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED
);
fifo_gen_inst_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => S_AXI_AREADY_I_i_3_n_0,
I1 => need_to_split_q,
O => \^din\(0)
);
\fifo_gen_inst_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => cmd_push_block,
I1 => m_axi_awvalid_INST_0_i_1_n_0,
O => wr_en
);
fifo_gen_inst_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => cmd_b_push_block,
I1 => m_axi_awvalid_INST_0_i_1_n_0,
O => cmd_b_push
);
m_axi_awvalid_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => m_axi_awvalid_INST_0_i_1_n_0,
O => m_axi_awvalid
);
m_axi_awvalid_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"5554554455544444"
)
port map (
I0 => cmd_push_block_reg_0,
I1 => m_axi_awvalid_INST_0_i_3_n_0,
I2 => split_in_progress_reg_0,
I3 => need_to_split_q,
I4 => cmd_empty_reg_0,
I5 => multiple_id_non_split,
O => m_axi_awvalid_INST_0_i_1_n_0
);
m_axi_awvalid_INST_0_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => command_ongoing,
I1 => full_0,
I2 => full,
O => m_axi_awvalid_INST_0_i_3_n_0
);
\multiple_id_non_split_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000F0F1F0F0"
)
port map (
I0 => cmd_push_block,
I1 => m_axi_awvalid_INST_0_i_1_n_0,
I2 => multiple_id_non_split,
I3 => \S_AXI_AID_Q_reg[0]\,
I4 => incr_need_to_split_q_reg,
I5 => \multiple_id_non_split_i_4__0_n_0\,
O => multiple_id_non_split_reg
);
\multiple_id_non_split_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F800FFFF"
)
port map (
I0 => almost_empty,
I1 => wr_cmd_ready,
I2 => cmd_empty,
I3 => multiple_id_non_split_i_5_n_0,
I4 => aresetn,
O => \multiple_id_non_split_i_4__0_n_0\
);
multiple_id_non_split_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAEAAAAAA"
)
port map (
I0 => cmd_b_empty,
I1 => almost_b_empty,
I2 => \goreg_dm.dout_i_reg[4]\,
I3 => m_axi_bvalid,
I4 => s_axi_bready,
I5 => \^gpregsm1.user_valid_reg\,
O => multiple_id_non_split_i_5_n_0
);
\queue_id[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE10"
)
port map (
I0 => cmd_push_block,
I1 => m_axi_awvalid_INST_0_i_1_n_0,
I2 => \S_AXI_AID_Q_reg[1]\(0),
I3 => queue_id(0),
O => \queue_id_reg[0]\
);
\queue_id[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE10"
)
port map (
I0 => cmd_push_block,
I1 => m_axi_awvalid_INST_0_i_1_n_0,
I2 => \S_AXI_AID_Q_reg[1]\(1),
I3 => queue_id(1),
O => \queue_id_reg[1]\
);
\split_in_progress_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000F1F0"
)
port map (
I0 => cmd_push_block,
I1 => m_axi_awvalid_INST_0_i_1_n_0,
I2 => split_in_progress_reg_0,
I3 => need_to_split_q,
I4 => \multiple_id_non_split_i_4__0_n_0\,
O => split_in_progress_reg
);
split_ongoing_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => m_axi_awready,
I1 => m_axi_awvalid_INST_0_i_1_n_0,
O => \^pushed_commands_reg[0]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_axi_data_fifo_v2_1_10_fifo_gen__parameterized1\ is
port (
din : out STD_LOGIC_VECTOR ( 0 to 0 );
wr_en : out STD_LOGIC;
rd_en : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_arvalid : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\pushed_commands_reg[0]\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
S_AXI_AREADY_I_reg : out STD_LOGIC;
cmd_push_block_reg : out STD_LOGIC;
command_ongoing_reg : out STD_LOGIC;
split_in_progress_reg : out STD_LOGIC;
multiple_id_non_split_reg : out STD_LOGIC;
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
need_to_split_q : in STD_LOGIC;
m_axi_rlast : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
command_ongoing : in STD_LOGIC;
cmd_push_block : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
multiple_id_non_split : in STD_LOGIC;
\S_AXI_AID_Q_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\queue_id_reg[0]\ : in STD_LOGIC;
\queue_id_reg[1]\ : in STD_LOGIC;
cmd_empty : in STD_LOGIC;
split_in_progress_reg_0 : in STD_LOGIC;
almost_empty : in STD_LOGIC;
aresetn : in STD_LOGIC;
access_is_incr_q : in STD_LOGIC;
\num_transactions_q_reg[3]\ : in STD_LOGIC;
\pushed_commands_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\num_transactions_q_reg[0]\ : in STD_LOGIC;
\num_transactions_q_reg[1]\ : in STD_LOGIC;
\num_transactions_q_reg[2]\ : in STD_LOGIC;
areset_d : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_AREADY_I_reg_0 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
\areset_d_reg[1]\ : in STD_LOGIC;
split_in_progress_reg_1 : in STD_LOGIC;
\S_AXI_AID_Q_reg[0]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_axi_data_fifo_v2_1_10_fifo_gen__parameterized1\ : entity is "axi_data_fifo_v2_1_10_fifo_gen";
end \system_auto_pc_1_axi_data_fifo_v2_1_10_fifo_gen__parameterized1\;
architecture STRUCTURE of \system_auto_pc_1_axi_data_fifo_v2_1_10_fifo_gen__parameterized1\ is
signal S_AXI_AREADY_I_i_2_n_0 : STD_LOGIC;
signal \S_AXI_AREADY_I_i_3__0_n_0\ : STD_LOGIC;
signal \cmd_depth[4]_i_2__0_n_0\ : STD_LOGIC;
signal \cmd_depth[5]_i_3__0_n_0\ : STD_LOGIC;
signal \cmd_depth[5]_i_4__0_n_0\ : STD_LOGIC;
signal \^din\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal empty : STD_LOGIC;
signal full : STD_LOGIC;
signal m_axi_arvalid_INST_0_i_1_n_0 : STD_LOGIC;
signal m_axi_arvalid_INST_0_i_2_n_0 : STD_LOGIC;
signal m_axi_arvalid_INST_0_i_3_n_0 : STD_LOGIC;
signal \^pushed_commands_reg[0]\ : STD_LOGIC;
signal rd_cmd_split : STD_LOGIC;
signal \^rd_en\ : STD_LOGIC;
signal split_in_progress : STD_LOGIC;
signal \^wr_en\ : STD_LOGIC;
signal NLW_fifo_gen_inst_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_valid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_fifo_gen_inst_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cmd_depth[2]_i_1__0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \cmd_depth[3]_i_1__0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \cmd_depth[4]_i_2__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \cmd_depth[5]_i_1\ : label is "soft_lutpair4";
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of fifo_gen_inst : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of fifo_gen_inst : label is 64;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of fifo_gen_inst : label is 4;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of fifo_gen_inst : label is 8;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of fifo_gen_inst : label is 4;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of fifo_gen_inst : label is 4;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of fifo_gen_inst : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of fifo_gen_inst : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of fifo_gen_inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of fifo_gen_inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of fifo_gen_inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of fifo_gen_inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of fifo_gen_inst : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of fifo_gen_inst : label is 4;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of fifo_gen_inst : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of fifo_gen_inst : label is 2;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of fifo_gen_inst : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of fifo_gen_inst : label is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of fifo_gen_inst : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of fifo_gen_inst : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of fifo_gen_inst : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of fifo_gen_inst : label is 6;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of fifo_gen_inst : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of fifo_gen_inst : label is 1;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of fifo_gen_inst : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of fifo_gen_inst : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of fifo_gen_inst : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of fifo_gen_inst : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of fifo_gen_inst : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of fifo_gen_inst : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of fifo_gen_inst : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of fifo_gen_inst : label is 1;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of fifo_gen_inst : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of fifo_gen_inst : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of fifo_gen_inst : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of fifo_gen_inst : label is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of fifo_gen_inst : label is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of fifo_gen_inst : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of fifo_gen_inst : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of fifo_gen_inst : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of fifo_gen_inst : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of fifo_gen_inst : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of fifo_gen_inst : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of fifo_gen_inst : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of fifo_gen_inst : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of fifo_gen_inst : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of fifo_gen_inst : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of fifo_gen_inst : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of fifo_gen_inst : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of fifo_gen_inst : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of fifo_gen_inst : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of fifo_gen_inst : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of fifo_gen_inst : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of fifo_gen_inst : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of fifo_gen_inst : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of fifo_gen_inst : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of fifo_gen_inst : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of fifo_gen_inst : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of fifo_gen_inst : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of fifo_gen_inst : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of fifo_gen_inst : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of fifo_gen_inst : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of fifo_gen_inst : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of fifo_gen_inst : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of fifo_gen_inst : label is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of fifo_gen_inst : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of fifo_gen_inst : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of fifo_gen_inst : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of fifo_gen_inst : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of fifo_gen_inst : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of fifo_gen_inst : label is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of fifo_gen_inst : label is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of fifo_gen_inst : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of fifo_gen_inst : label is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of fifo_gen_inst : label is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of fifo_gen_inst : label is 31;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of fifo_gen_inst : label is 30;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of fifo_gen_inst : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of fifo_gen_inst : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of fifo_gen_inst : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of fifo_gen_inst : label is 6;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of fifo_gen_inst : label is 32;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of fifo_gen_inst : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of fifo_gen_inst : label is 5;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of fifo_gen_inst : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of fifo_gen_inst : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of fifo_gen_inst : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of fifo_gen_inst : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of fifo_gen_inst : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of fifo_gen_inst : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of fifo_gen_inst : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of fifo_gen_inst : label is 3;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of fifo_gen_inst : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of fifo_gen_inst : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of fifo_gen_inst : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of fifo_gen_inst : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of fifo_gen_inst : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of fifo_gen_inst : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of fifo_gen_inst : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of fifo_gen_inst : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of fifo_gen_inst : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of fifo_gen_inst : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of fifo_gen_inst : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of fifo_gen_inst : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of fifo_gen_inst : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of fifo_gen_inst : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of fifo_gen_inst : label is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of fifo_gen_inst : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of fifo_gen_inst : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of fifo_gen_inst : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of fifo_gen_inst : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of fifo_gen_inst : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of fifo_gen_inst : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of fifo_gen_inst : label is 6;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of fifo_gen_inst : label is 32;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of fifo_gen_inst : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of fifo_gen_inst : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of fifo_gen_inst : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of fifo_gen_inst : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of fifo_gen_inst : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of fifo_gen_inst : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of fifo_gen_inst : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of fifo_gen_inst : label is 5;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of fifo_gen_inst : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of fifo_gen_inst : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of fifo_gen_inst : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of fifo_gen_inst : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of fifo_gen_inst : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of fifo_gen_inst : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of fifo_gen_inst : label is 1;
attribute SOFT_HLUTNM of \fifo_gen_inst_i_3__1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of m_axi_arvalid_INST_0 : label is "soft_lutpair7";
attribute SOFT_HLUTNM of m_axi_rready_INST_0 : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \split_ongoing_i_1__0\ : label is "soft_lutpair7";
begin
din(0) <= \^din\(0);
\pushed_commands_reg[0]\ <= \^pushed_commands_reg[0]\;
rd_en <= \^rd_en\;
wr_en <= \^wr_en\;
\S_AXI_AREADY_I_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"444444F4FFFF44F4"
)
port map (
I0 => areset_d(0),
I1 => areset_d(1),
I2 => \^pushed_commands_reg[0]\,
I3 => S_AXI_AREADY_I_i_2_n_0,
I4 => S_AXI_AREADY_I_reg_0,
I5 => s_axi_arvalid,
O => S_AXI_AREADY_I_reg
);
S_AXI_AREADY_I_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"8AA8AAAAAAAA8AA8"
)
port map (
I0 => access_is_incr_q,
I1 => \S_AXI_AREADY_I_i_3__0_n_0\,
I2 => \num_transactions_q_reg[3]\,
I3 => \pushed_commands_reg[3]\(3),
I4 => \num_transactions_q_reg[0]\,
I5 => \pushed_commands_reg[3]\(0),
O => S_AXI_AREADY_I_i_2_n_0
);
\S_AXI_AREADY_I_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \num_transactions_q_reg[1]\,
I1 => \pushed_commands_reg[3]\(1),
I2 => \num_transactions_q_reg[2]\,
I3 => \pushed_commands_reg[3]\(2),
O => \S_AXI_AREADY_I_i_3__0_n_0\
);
\cmd_depth[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cmd_depth[4]_i_2__0_n_0\,
I1 => Q(0),
I2 => Q(1),
O => D(0)
);
\cmd_depth[2]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9AA6"
)
port map (
I0 => Q(2),
I1 => \cmd_depth[4]_i_2__0_n_0\,
I2 => Q(0),
I3 => Q(1),
O => D(1)
);
\cmd_depth[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7EF0810"
)
port map (
I0 => Q(1),
I1 => Q(0),
I2 => \cmd_depth[4]_i_2__0_n_0\,
I3 => Q(2),
I4 => Q(3),
O => D(2)
);
\cmd_depth[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9AAAAAAAAAAAAAA6"
)
port map (
I0 => Q(4),
I1 => \cmd_depth[4]_i_2__0_n_0\,
I2 => Q(0),
I3 => Q(1),
I4 => Q(2),
I5 => Q(3),
O => D(3)
);
\cmd_depth[4]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0080FFFF"
)
port map (
I0 => m_axi_rlast,
I1 => s_axi_rready,
I2 => m_axi_rvalid,
I3 => empty,
I4 => \^wr_en\,
O => \cmd_depth[4]_i_2__0_n_0\
);
\cmd_depth[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF7F0080"
)
port map (
I0 => m_axi_rlast,
I1 => s_axi_rready,
I2 => m_axi_rvalid,
I3 => empty,
I4 => \^wr_en\,
O => E(0)
);
\cmd_depth[5]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => Q(5),
I1 => \cmd_depth[5]_i_3__0_n_0\,
I2 => Q(4),
I3 => \cmd_depth[5]_i_4__0_n_0\,
O => D(4)
);
\cmd_depth[5]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000010001"
)
port map (
I0 => Q(3),
I1 => Q(2),
I2 => Q(1),
I3 => Q(0),
I4 => \^rd_en\,
I5 => \^wr_en\,
O => \cmd_depth[5]_i_3__0_n_0\
);
\cmd_depth[5]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0800000000000000"
)
port map (
I0 => Q(1),
I1 => Q(0),
I2 => \^rd_en\,
I3 => \^wr_en\,
I4 => Q(2),
I5 => Q(3),
O => \cmd_depth[5]_i_4__0_n_0\
);
cmd_push_block_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0000AE00"
)
port map (
I0 => cmd_push_block,
I1 => \^wr_en\,
I2 => m_axi_arready,
I3 => aresetn,
I4 => \^pushed_commands_reg[0]\,
O => cmd_push_block_reg
);
\command_ongoing_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFDDD0000F000"
)
port map (
I0 => \^pushed_commands_reg[0]\,
I1 => S_AXI_AREADY_I_i_2_n_0,
I2 => S_AXI_AREADY_I_reg_0,
I3 => s_axi_arvalid,
I4 => \areset_d_reg[1]\,
I5 => command_ongoing,
O => command_ongoing_reg
);
fifo_gen_inst: entity work.\system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\
port map (
almost_empty => NLW_fifo_gen_inst_almost_empty_UNCONNECTED,
almost_full => NLW_fifo_gen_inst_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_fifo_gen_inst_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_fifo_gen_inst_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_fifo_gen_inst_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => aclk,
data_count(5 downto 0) => NLW_fifo_gen_inst_data_count_UNCONNECTED(5 downto 0),
dbiterr => NLW_fifo_gen_inst_dbiterr_UNCONNECTED,
din(0) => \^din\(0),
dout(0) => rd_cmd_split,
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(3 downto 0) => NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED(3 downto 0),
m_axi_arlen(7 downto 0) => NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(1 downto 0) => NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED(1 downto 0),
m_axi_arprot(2 downto 0) => NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(3 downto 0) => NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED(3 downto 0),
m_axi_awlen(7 downto 0) => NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(1 downto 0) => NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED(1 downto 0),
m_axi_awprot(2 downto 0) => NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED,
m_axi_bid(3 downto 0) => B"0000",
m_axi_bready => NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(3 downto 0) => B"0000",
m_axi_rlast => '0',
m_axi_rready => NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(3 downto 0) => NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED(3 downto 0),
m_axi_wlast => NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(63 downto 0) => NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED(63 downto 0),
m_axis_tdest(3 downto 0) => NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED(3 downto 0),
m_axis_tid(7 downto 0) => NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED(7 downto 0),
m_axis_tkeep(3 downto 0) => NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED(3 downto 0),
m_axis_tlast => NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(3 downto 0) => NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED(3 downto 0),
m_axis_tuser(3 downto 0) => NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED,
overflow => NLW_fifo_gen_inst_overflow_UNCONNECTED,
prog_empty => NLW_fifo_gen_inst_prog_empty_UNCONNECTED,
prog_empty_thresh(4 downto 0) => B"00000",
prog_empty_thresh_assert(4 downto 0) => B"00000",
prog_empty_thresh_negate(4 downto 0) => B"00000",
prog_full => NLW_fifo_gen_inst_prog_full_UNCONNECTED,
prog_full_thresh(4 downto 0) => B"00000",
prog_full_thresh_assert(4 downto 0) => B"00000",
prog_full_thresh_negate(4 downto 0) => B"00000",
rd_clk => '0',
rd_data_count(5 downto 0) => NLW_fifo_gen_inst_rd_data_count_UNCONNECTED(5 downto 0),
rd_en => \^rd_en\,
rd_rst => '0',
rd_rst_busy => NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED,
rst => SR(0),
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(1 downto 0) => B"00",
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(1 downto 0) => B"00",
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(3 downto 0) => NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(3 downto 0) => B"0000",
s_axi_wlast => '0',
s_axi_wready => NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axis_tdest(3 downto 0) => B"0000",
s_axis_tid(7 downto 0) => B"00000000",
s_axis_tkeep(3 downto 0) => B"0000",
s_axis_tlast => '0',
s_axis_tready => NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED,
s_axis_tstrb(3 downto 0) => B"0000",
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_fifo_gen_inst_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_fifo_gen_inst_underflow_UNCONNECTED,
valid => NLW_fifo_gen_inst_valid_UNCONNECTED,
wr_ack => NLW_fifo_gen_inst_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(5 downto 0) => NLW_fifo_gen_inst_wr_data_count_UNCONNECTED(5 downto 0),
wr_en => \^wr_en\,
wr_rst => '0',
wr_rst_busy => NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED
);
\fifo_gen_inst_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => S_AXI_AREADY_I_i_2_n_0,
I1 => need_to_split_q,
O => \^din\(0)
);
\fifo_gen_inst_i_2__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000001F00"
)
port map (
I0 => need_to_split_q,
I1 => m_axi_arvalid_INST_0_i_3_n_0,
I2 => m_axi_arvalid_INST_0_i_2_n_0,
I3 => command_ongoing,
I4 => full,
I5 => cmd_push_block,
O => \^wr_en\
);
\fifo_gen_inst_i_3__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => empty,
I1 => m_axi_rvalid,
I2 => s_axi_rready,
I3 => m_axi_rlast,
O => \^rd_en\
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => m_axi_arvalid_INST_0_i_1_n_0,
O => m_axi_arvalid
);
m_axi_arvalid_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"5F4F5F4F5F4F4F4F"
)
port map (
I0 => cmd_push_block,
I1 => full,
I2 => command_ongoing,
I3 => m_axi_arvalid_INST_0_i_2_n_0,
I4 => m_axi_arvalid_INST_0_i_3_n_0,
I5 => need_to_split_q,
O => m_axi_arvalid_INST_0_i_1_n_0
);
m_axi_arvalid_INST_0_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAABEFFFFBE"
)
port map (
I0 => multiple_id_non_split,
I1 => \S_AXI_AID_Q_reg[1]\(0),
I2 => \queue_id_reg[0]\,
I3 => \S_AXI_AID_Q_reg[1]\(1),
I4 => \queue_id_reg[1]\,
I5 => cmd_empty,
O => m_axi_arvalid_INST_0_i_2_n_0
);
m_axi_arvalid_INST_0_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0440444444440440"
)
port map (
I0 => cmd_empty,
I1 => split_in_progress_reg_0,
I2 => \queue_id_reg[1]\,
I3 => \S_AXI_AID_Q_reg[1]\(1),
I4 => \queue_id_reg[0]\,
I5 => \S_AXI_AID_Q_reg[1]\(0),
O => m_axi_arvalid_INST_0_i_3_n_0
);
m_axi_rready_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"0D"
)
port map (
I0 => m_axi_rvalid,
I1 => s_axi_rready,
I2 => empty,
O => m_axi_rready
);
multiple_id_non_split_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAAAAAAE"
)
port map (
I0 => multiple_id_non_split,
I1 => \^wr_en\,
I2 => need_to_split_q,
I3 => split_in_progress_reg_1,
I4 => \S_AXI_AID_Q_reg[0]\,
I5 => split_in_progress,
O => multiple_id_non_split_reg
);
multiple_id_non_split_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"FF8F"
)
port map (
I0 => almost_empty,
I1 => \^rd_en\,
I2 => aresetn,
I3 => cmd_empty,
O => split_in_progress
);
s_axi_rlast_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => m_axi_rlast,
I1 => rd_cmd_split,
O => s_axi_rlast
);
s_axi_rvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => m_axi_rvalid,
I1 => empty,
O => s_axi_rvalid
);
split_in_progress_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0000AAEA"
)
port map (
I0 => split_in_progress_reg_0,
I1 => \^wr_en\,
I2 => need_to_split_q,
I3 => m_axi_arvalid_INST_0_i_2_n_0,
I4 => split_in_progress,
O => split_in_progress_reg
);
\split_ongoing_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => m_axi_arready,
I1 => m_axi_arvalid_INST_0_i_1_n_0,
O => \^pushed_commands_reg[0]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_axi_data_fifo_v2_1_10_axic_fifo is
port (
dout : out STD_LOGIC_VECTOR ( 5 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
din : out STD_LOGIC_VECTOR ( 3 downto 0 );
\USE_B_CHANNEL.cmd_b_empty_reg\ : out STD_LOGIC;
\USE_B_CHANNEL.cmd_b_empty_reg_0\ : out STD_LOGIC;
\length_counter_1_reg_0__s_port_]\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
aclk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
wr_en : in STD_LOGIC;
wr_cmd_ready : in STD_LOGIC;
cmd_empty : in STD_LOGIC;
cmd_b_empty : in STD_LOGIC;
queue_id : in STD_LOGIC_VECTOR ( 1 downto 0 );
cmd_push_block : in STD_LOGIC;
command_ongoing : in STD_LOGIC;
aresetn : in STD_LOGIC;
first_mi_word : in STD_LOGIC;
length_counter_1_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
\S_AXI_ALEN_Q_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\pushed_commands_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
need_to_split_q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_axi_data_fifo_v2_1_10_axic_fifo : entity is "axi_data_fifo_v2_1_10_axic_fifo";
end system_auto_pc_1_axi_data_fifo_v2_1_10_axic_fifo;
architecture STRUCTURE of system_auto_pc_1_axi_data_fifo_v2_1_10_axic_fifo is
signal \length_counter_1_reg_0__s_net_1\ : STD_LOGIC;
begin
\length_counter_1_reg_0__s_port_]\ <= \length_counter_1_reg_0__s_net_1\;
inst: entity work.system_auto_pc_1_axi_data_fifo_v2_1_10_fifo_gen
port map (
Q(1 downto 0) => Q(1 downto 0),
SR(0) => SR(0),
\S_AXI_ALEN_Q_reg[3]\(3 downto 0) => \S_AXI_ALEN_Q_reg[3]\(3 downto 0),
\USE_B_CHANNEL.cmd_b_empty_reg\ => \USE_B_CHANNEL.cmd_b_empty_reg\,
\USE_B_CHANNEL.cmd_b_empty_reg_0\ => \USE_B_CHANNEL.cmd_b_empty_reg_0\,
aclk => aclk,
aresetn => aresetn,
cmd_b_empty => cmd_b_empty,
cmd_empty => cmd_empty,
cmd_push_block => cmd_push_block,
command_ongoing => command_ongoing,
din(3 downto 0) => din(3 downto 0),
dout(5 downto 0) => dout(5 downto 0),
empty => empty,
first_mi_word => first_mi_word,
full => full,
length_counter_1_reg(0) => length_counter_1_reg(0),
\length_counter_1_reg_0__s_port_]\ => \length_counter_1_reg_0__s_net_1\,
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
need_to_split_q => need_to_split_q,
\pushed_commands_reg[3]\(3 downto 0) => \pushed_commands_reg[3]\(3 downto 0),
queue_id(1 downto 0) => queue_id(1 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid,
wr_cmd_ready => wr_cmd_ready,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_axi_data_fifo_v2_1_10_axic_fifo__parameterized0\ is
port (
first_mi_word_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.user_valid_reg\ : out STD_LOGIC;
din : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
wr_en : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
multiple_id_non_split_reg : out STD_LOGIC;
split_in_progress_reg : out STD_LOGIC;
cmd_push_block_reg : out STD_LOGIC;
pushed_new_cmd : out STD_LOGIC;
cmd_empty_reg : out STD_LOGIC;
\queue_id_reg[0]\ : out STD_LOGIC;
\queue_id_reg[1]\ : out STD_LOGIC;
cmd_b_push_block_reg : out STD_LOGIC;
\USE_B_CHANNEL.cmd_b_depth_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\USE_B_CHANNEL.cmd_b_empty_reg\ : out STD_LOGIC;
\USE_B_CHANNEL.cmd_b_depth_reg[5]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_awvalid : out STD_LOGIC;
S_AXI_AREADY_I_reg : out STD_LOGIC;
command_ongoing_reg : out STD_LOGIC;
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\num_transactions_q_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
wr_cmd_b_ready : in STD_LOGIC;
almost_empty : in STD_LOGIC;
wr_cmd_ready : in STD_LOGIC;
cmd_empty : in STD_LOGIC;
aresetn : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
need_to_split_q : in STD_LOGIC;
cmd_push_block : in STD_LOGIC;
multiple_id_non_split : in STD_LOGIC;
\S_AXI_AID_Q_reg[0]\ : in STD_LOGIC;
incr_need_to_split_q_reg : in STD_LOGIC;
split_in_progress_reg_0 : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\S_AXI_AID_Q_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
queue_id : in STD_LOGIC_VECTOR ( 1 downto 0 );
cmd_b_push_block : in STD_LOGIC;
S_AXI_AREADY_I_reg_0 : in STD_LOGIC;
almost_b_empty : in STD_LOGIC;
cmd_b_empty : in STD_LOGIC;
\USE_B_CHANNEL.cmd_b_depth_reg[5]_1\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
\goreg_dm.dout_i_reg[4]\ : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
cmd_push_block_reg_0 : in STD_LOGIC;
cmd_empty_reg_0 : in STD_LOGIC;
command_ongoing : in STD_LOGIC;
full : in STD_LOGIC;
access_is_incr_q : in STD_LOGIC;
\pushed_commands_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\areset_d_reg[0]\ : in STD_LOGIC;
areset_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
\areset_d_reg[1]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_axi_data_fifo_v2_1_10_axic_fifo__parameterized0\ : entity is "axi_data_fifo_v2_1_10_axic_fifo";
end \system_auto_pc_1_axi_data_fifo_v2_1_10_axic_fifo__parameterized0\;
architecture STRUCTURE of \system_auto_pc_1_axi_data_fifo_v2_1_10_axic_fifo__parameterized0\ is
begin
inst: entity work.\system_auto_pc_1_axi_data_fifo_v2_1_10_fifo_gen__parameterized0\
port map (
D(4 downto 0) => D(4 downto 0),
E(0) => E(0),
Q(5 downto 0) => Q(5 downto 0),
SR(0) => SR(0),
\S_AXI_AID_Q_reg[0]\ => \S_AXI_AID_Q_reg[0]\,
\S_AXI_AID_Q_reg[1]\(1 downto 0) => \S_AXI_AID_Q_reg[1]\(1 downto 0),
S_AXI_AREADY_I_reg => S_AXI_AREADY_I_reg,
S_AXI_AREADY_I_reg_0 => S_AXI_AREADY_I_reg_0,
\USE_B_CHANNEL.cmd_b_depth_reg[5]\(0) => \USE_B_CHANNEL.cmd_b_depth_reg[5]\(0),
\USE_B_CHANNEL.cmd_b_depth_reg[5]_0\(4 downto 0) => \USE_B_CHANNEL.cmd_b_depth_reg[5]_0\(4 downto 0),
\USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(5 downto 0) => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(5 downto 0),
\USE_B_CHANNEL.cmd_b_empty_reg\ => \USE_B_CHANNEL.cmd_b_empty_reg\,
access_is_incr_q => access_is_incr_q,
aclk => aclk,
almost_b_empty => almost_b_empty,
almost_empty => almost_empty,
areset_d(0) => areset_d(0),
\areset_d_reg[0]\ => \areset_d_reg[0]\,
\areset_d_reg[1]\ => \areset_d_reg[1]\,
aresetn => aresetn,
cmd_b_empty => cmd_b_empty,
cmd_b_push_block => cmd_b_push_block,
cmd_b_push_block_reg => cmd_b_push_block_reg,
cmd_empty => cmd_empty,
cmd_empty_reg => cmd_empty_reg,
cmd_empty_reg_0 => cmd_empty_reg_0,
cmd_push_block => cmd_push_block,
cmd_push_block_reg => cmd_push_block_reg,
cmd_push_block_reg_0 => cmd_push_block_reg_0,
command_ongoing => command_ongoing,
command_ongoing_reg => command_ongoing_reg,
din(0) => din(0),
first_mi_word_reg(4 downto 0) => first_mi_word_reg(4 downto 0),
full => full,
\goreg_dm.dout_i_reg[4]\ => \goreg_dm.dout_i_reg[4]\,
\gpregsm1.user_valid_reg\ => \gpregsm1.user_valid_reg\,
incr_need_to_split_q_reg => incr_need_to_split_q_reg,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_bvalid => m_axi_bvalid,
multiple_id_non_split => multiple_id_non_split,
multiple_id_non_split_reg => multiple_id_non_split_reg,
need_to_split_q => need_to_split_q,
\num_transactions_q_reg[3]\(3 downto 0) => \num_transactions_q_reg[3]\(3 downto 0),
\pushed_commands_reg[0]\ => pushed_new_cmd,
\pushed_commands_reg[3]\(3 downto 0) => \pushed_commands_reg[3]\(3 downto 0),
queue_id(1 downto 0) => queue_id(1 downto 0),
\queue_id_reg[0]\ => \queue_id_reg[0]\,
\queue_id_reg[1]\ => \queue_id_reg[1]\,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
split_in_progress_reg => split_in_progress_reg,
split_in_progress_reg_0 => split_in_progress_reg_0,
wr_cmd_b_ready => wr_cmd_b_ready,
wr_cmd_ready => wr_cmd_ready,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_axi_data_fifo_v2_1_10_axic_fifo__parameterized1\ is
port (
din : out STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push : out STD_LOGIC;
rd_cmd_ready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_arvalid : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
pushed_new_cmd : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
S_AXI_AREADY_I_reg : out STD_LOGIC;
cmd_push_block_reg : out STD_LOGIC;
command_ongoing_reg : out STD_LOGIC;
split_in_progress_reg : out STD_LOGIC;
multiple_id_non_split_reg : out STD_LOGIC;
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
need_to_split_q : in STD_LOGIC;
m_axi_rlast : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
command_ongoing : in STD_LOGIC;
cmd_push_block : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
multiple_id_non_split : in STD_LOGIC;
\S_AXI_AID_Q_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\queue_id_reg[0]\ : in STD_LOGIC;
\queue_id_reg[1]\ : in STD_LOGIC;
cmd_empty : in STD_LOGIC;
split_in_progress_reg_0 : in STD_LOGIC;
almost_empty : in STD_LOGIC;
aresetn : in STD_LOGIC;
access_is_incr_q : in STD_LOGIC;
\num_transactions_q_reg[3]\ : in STD_LOGIC;
\pushed_commands_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\num_transactions_q_reg[0]\ : in STD_LOGIC;
\num_transactions_q_reg[1]\ : in STD_LOGIC;
\num_transactions_q_reg[2]\ : in STD_LOGIC;
areset_d : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_AREADY_I_reg_0 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
\areset_d_reg[1]\ : in STD_LOGIC;
split_in_progress_reg_1 : in STD_LOGIC;
\S_AXI_AID_Q_reg[0]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_axi_data_fifo_v2_1_10_axic_fifo__parameterized1\ : entity is "axi_data_fifo_v2_1_10_axic_fifo";
end \system_auto_pc_1_axi_data_fifo_v2_1_10_axic_fifo__parameterized1\;
architecture STRUCTURE of \system_auto_pc_1_axi_data_fifo_v2_1_10_axic_fifo__parameterized1\ is
begin
inst: entity work.\system_auto_pc_1_axi_data_fifo_v2_1_10_fifo_gen__parameterized1\
port map (
D(4 downto 0) => D(4 downto 0),
E(0) => E(0),
Q(5 downto 0) => Q(5 downto 0),
SR(0) => SR(0),
\S_AXI_AID_Q_reg[0]\ => \S_AXI_AID_Q_reg[0]\,
\S_AXI_AID_Q_reg[1]\(1 downto 0) => \S_AXI_AID_Q_reg[1]\(1 downto 0),
S_AXI_AREADY_I_reg => S_AXI_AREADY_I_reg,
S_AXI_AREADY_I_reg_0 => S_AXI_AREADY_I_reg_0,
access_is_incr_q => access_is_incr_q,
aclk => aclk,
almost_empty => almost_empty,
areset_d(1 downto 0) => areset_d(1 downto 0),
\areset_d_reg[1]\ => \areset_d_reg[1]\,
aresetn => aresetn,
cmd_empty => cmd_empty,
cmd_push_block => cmd_push_block,
cmd_push_block_reg => cmd_push_block_reg,
command_ongoing => command_ongoing,
command_ongoing_reg => command_ongoing_reg,
din(0) => din(0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
multiple_id_non_split => multiple_id_non_split,
multiple_id_non_split_reg => multiple_id_non_split_reg,
need_to_split_q => need_to_split_q,
\num_transactions_q_reg[0]\ => \num_transactions_q_reg[0]\,
\num_transactions_q_reg[1]\ => \num_transactions_q_reg[1]\,
\num_transactions_q_reg[2]\ => \num_transactions_q_reg[2]\,
\num_transactions_q_reg[3]\ => \num_transactions_q_reg[3]\,
\pushed_commands_reg[0]\ => pushed_new_cmd,
\pushed_commands_reg[3]\(3 downto 0) => \pushed_commands_reg[3]\(3 downto 0),
\queue_id_reg[0]\ => \queue_id_reg[0]\,
\queue_id_reg[1]\ => \queue_id_reg[1]\,
rd_en => rd_cmd_ready,
s_axi_arvalid => s_axi_arvalid,
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
split_in_progress_reg => split_in_progress_reg,
split_in_progress_reg_0 => split_in_progress_reg_0,
split_in_progress_reg_1 => split_in_progress_reg_1,
wr_en => cmd_push
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_axi_protocol_converter_v2_1_11_a_axi3_conv is
port (
dout : out STD_LOGIC_VECTOR ( 5 downto 0 );
empty : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
din : out STD_LOGIC_VECTOR ( 5 downto 0 );
first_mi_word_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.user_valid_reg\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
areset_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awvalid : out STD_LOGIC;
\length_counter_1_reg_0__s_port_]\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
command_ongoing_reg_0 : out STD_LOGIC;
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
wr_cmd_ready : in STD_LOGIC;
wr_cmd_b_ready : in STD_LOGIC;
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
aresetn : in STD_LOGIC;
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awready : in STD_LOGIC;
\goreg_dm.dout_i_reg[4]\ : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
first_mi_word : in STD_LOGIC;
length_counter_1_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_axi_protocol_converter_v2_1_11_a_axi3_conv : entity is "axi_protocol_converter_v2_1_11_a_axi3_conv";
end system_auto_pc_1_axi_protocol_converter_v2_1_11_a_axi3_conv;
architecture STRUCTURE of system_auto_pc_1_axi_protocol_converter_v2_1_11_a_axi3_conv is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal S_AXI_AADDR_Q : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXI_ALEN_Q : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \S_AXI_ALOCK_Q_reg_n_0_[0]\ : STD_LOGIC;
signal \USE_BURSTS.cmd_queue_n_13\ : STD_LOGIC;
signal \USE_BURSTS.cmd_queue_n_14\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_depth[0]_i_1_n_0\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_depth_reg__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \USE_B_CHANNEL.cmd_b_queue_n_10\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_11\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_13\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_14\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_15\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_16\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_18\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_19\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_20\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_21\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_22\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_23\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_24\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_25\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_26\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_27\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_28\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_30\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_31\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_6\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_7\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_8\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_9\ : STD_LOGIC;
signal access_is_incr : STD_LOGIC;
signal access_is_incr_q : STD_LOGIC;
signal addr_step : STD_LOGIC_VECTOR ( 11 downto 5 );
signal addr_step_q : STD_LOGIC_VECTOR ( 11 downto 5 );
signal almost_b_empty : STD_LOGIC;
signal almost_empty : STD_LOGIC;
signal \^areset_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal cmd_b_empty : STD_LOGIC;
signal cmd_b_push_block : STD_LOGIC;
signal \cmd_depth[0]_i_1_n_0\ : STD_LOGIC;
signal \cmd_depth_reg__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal cmd_empty : STD_LOGIC;
signal cmd_push : STD_LOGIC;
signal cmd_push_block : STD_LOGIC;
signal command_ongoing : STD_LOGIC;
signal \^command_ongoing_reg_0\ : STD_LOGIC;
signal \^din\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal first_step : STD_LOGIC_VECTOR ( 11 downto 4 );
signal first_step_q : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \first_step_q[0]_i_1_n_0\ : STD_LOGIC;
signal \first_step_q[10]_i_2_n_0\ : STD_LOGIC;
signal \first_step_q[11]_i_2_n_0\ : STD_LOGIC;
signal \first_step_q[1]_i_1_n_0\ : STD_LOGIC;
signal \first_step_q[2]_i_1_n_0\ : STD_LOGIC;
signal \first_step_q[3]_i_1_n_0\ : STD_LOGIC;
signal \first_step_q[6]_i_2_n_0\ : STD_LOGIC;
signal \first_step_q[7]_i_2_n_0\ : STD_LOGIC;
signal \first_step_q[8]_i_2_n_0\ : STD_LOGIC;
signal \first_step_q[9]_i_2_n_0\ : STD_LOGIC;
signal \incr_need_to_split__0\ : STD_LOGIC;
signal \inst/full\ : STD_LOGIC;
signal \length_counter_1_reg_0__s_net_1\ : STD_LOGIC;
signal \^m_axi_awaddr\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal multiple_id_non_split : STD_LOGIC;
signal multiple_id_non_split_i_2_n_0 : STD_LOGIC;
signal \multiple_id_non_split_i_3__0_n_0\ : STD_LOGIC;
signal need_to_split_q : STD_LOGIC;
signal next_mi_addr : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \next_mi_addr[11]_i_2_n_0\ : STD_LOGIC;
signal \next_mi_addr[11]_i_3_n_0\ : STD_LOGIC;
signal \next_mi_addr[11]_i_4_n_0\ : STD_LOGIC;
signal \next_mi_addr[11]_i_5_n_0\ : STD_LOGIC;
signal \next_mi_addr[11]_i_6_n_0\ : STD_LOGIC;
signal \next_mi_addr[15]_i_2_n_0\ : STD_LOGIC;
signal \next_mi_addr[15]_i_3_n_0\ : STD_LOGIC;
signal \next_mi_addr[15]_i_4_n_0\ : STD_LOGIC;
signal \next_mi_addr[15]_i_5_n_0\ : STD_LOGIC;
signal \next_mi_addr[15]_i_6_n_0\ : STD_LOGIC;
signal \next_mi_addr[15]_i_7_n_0\ : STD_LOGIC;
signal \next_mi_addr[15]_i_8_n_0\ : STD_LOGIC;
signal \next_mi_addr[15]_i_9_n_0\ : STD_LOGIC;
signal \next_mi_addr[19]_i_2_n_0\ : STD_LOGIC;
signal \next_mi_addr[19]_i_3_n_0\ : STD_LOGIC;
signal \next_mi_addr[19]_i_4_n_0\ : STD_LOGIC;
signal \next_mi_addr[19]_i_5_n_0\ : STD_LOGIC;
signal \next_mi_addr[23]_i_2_n_0\ : STD_LOGIC;
signal \next_mi_addr[23]_i_3_n_0\ : STD_LOGIC;
signal \next_mi_addr[23]_i_4_n_0\ : STD_LOGIC;
signal \next_mi_addr[23]_i_5_n_0\ : STD_LOGIC;
signal \next_mi_addr[27]_i_2_n_0\ : STD_LOGIC;
signal \next_mi_addr[27]_i_3_n_0\ : STD_LOGIC;
signal \next_mi_addr[27]_i_4_n_0\ : STD_LOGIC;
signal \next_mi_addr[27]_i_5_n_0\ : STD_LOGIC;
signal \next_mi_addr[31]_i_2_n_0\ : STD_LOGIC;
signal \next_mi_addr[31]_i_3_n_0\ : STD_LOGIC;
signal \next_mi_addr[31]_i_4_n_0\ : STD_LOGIC;
signal \next_mi_addr[31]_i_5_n_0\ : STD_LOGIC;
signal \next_mi_addr[3]_i_2_n_0\ : STD_LOGIC;
signal \next_mi_addr[3]_i_3_n_0\ : STD_LOGIC;
signal \next_mi_addr[3]_i_4_n_0\ : STD_LOGIC;
signal \next_mi_addr[3]_i_5_n_0\ : STD_LOGIC;
signal \next_mi_addr[3]_i_6_n_0\ : STD_LOGIC;
signal \next_mi_addr[7]_i_2_n_0\ : STD_LOGIC;
signal \next_mi_addr[7]_i_3_n_0\ : STD_LOGIC;
signal \next_mi_addr[7]_i_4_n_0\ : STD_LOGIC;
signal \next_mi_addr[7]_i_5_n_0\ : STD_LOGIC;
signal \next_mi_addr_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \next_mi_addr_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \next_mi_addr_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \next_mi_addr_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \next_mi_addr_reg[11]_i_1_n_4\ : STD_LOGIC;
signal \next_mi_addr_reg[11]_i_1_n_5\ : STD_LOGIC;
signal \next_mi_addr_reg[11]_i_1_n_6\ : STD_LOGIC;
signal \next_mi_addr_reg[11]_i_1_n_7\ : STD_LOGIC;
signal \next_mi_addr_reg[15]_i_1_n_0\ : STD_LOGIC;
signal \next_mi_addr_reg[15]_i_1_n_1\ : STD_LOGIC;
signal \next_mi_addr_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \next_mi_addr_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \next_mi_addr_reg[15]_i_1_n_4\ : STD_LOGIC;
signal \next_mi_addr_reg[15]_i_1_n_5\ : STD_LOGIC;
signal \next_mi_addr_reg[15]_i_1_n_6\ : STD_LOGIC;
signal \next_mi_addr_reg[15]_i_1_n_7\ : STD_LOGIC;
signal \next_mi_addr_reg[19]_i_1_n_0\ : STD_LOGIC;
signal \next_mi_addr_reg[19]_i_1_n_1\ : STD_LOGIC;
signal \next_mi_addr_reg[19]_i_1_n_2\ : STD_LOGIC;
signal \next_mi_addr_reg[19]_i_1_n_3\ : STD_LOGIC;
signal \next_mi_addr_reg[19]_i_1_n_4\ : STD_LOGIC;
signal \next_mi_addr_reg[19]_i_1_n_5\ : STD_LOGIC;
signal \next_mi_addr_reg[19]_i_1_n_6\ : STD_LOGIC;
signal \next_mi_addr_reg[19]_i_1_n_7\ : STD_LOGIC;
signal \next_mi_addr_reg[23]_i_1_n_0\ : STD_LOGIC;
signal \next_mi_addr_reg[23]_i_1_n_1\ : STD_LOGIC;
signal \next_mi_addr_reg[23]_i_1_n_2\ : STD_LOGIC;
signal \next_mi_addr_reg[23]_i_1_n_3\ : STD_LOGIC;
signal \next_mi_addr_reg[23]_i_1_n_4\ : STD_LOGIC;
signal \next_mi_addr_reg[23]_i_1_n_5\ : STD_LOGIC;
signal \next_mi_addr_reg[23]_i_1_n_6\ : STD_LOGIC;
signal \next_mi_addr_reg[23]_i_1_n_7\ : STD_LOGIC;
signal \next_mi_addr_reg[27]_i_1_n_0\ : STD_LOGIC;
signal \next_mi_addr_reg[27]_i_1_n_1\ : STD_LOGIC;
signal \next_mi_addr_reg[27]_i_1_n_2\ : STD_LOGIC;
signal \next_mi_addr_reg[27]_i_1_n_3\ : STD_LOGIC;
signal \next_mi_addr_reg[27]_i_1_n_4\ : STD_LOGIC;
signal \next_mi_addr_reg[27]_i_1_n_5\ : STD_LOGIC;
signal \next_mi_addr_reg[27]_i_1_n_6\ : STD_LOGIC;
signal \next_mi_addr_reg[27]_i_1_n_7\ : STD_LOGIC;
signal \next_mi_addr_reg[31]_i_1_n_1\ : STD_LOGIC;
signal \next_mi_addr_reg[31]_i_1_n_2\ : STD_LOGIC;
signal \next_mi_addr_reg[31]_i_1_n_3\ : STD_LOGIC;
signal \next_mi_addr_reg[31]_i_1_n_4\ : STD_LOGIC;
signal \next_mi_addr_reg[31]_i_1_n_5\ : STD_LOGIC;
signal \next_mi_addr_reg[31]_i_1_n_6\ : STD_LOGIC;
signal \next_mi_addr_reg[31]_i_1_n_7\ : STD_LOGIC;
signal \next_mi_addr_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \next_mi_addr_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \next_mi_addr_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \next_mi_addr_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \next_mi_addr_reg[3]_i_1_n_4\ : STD_LOGIC;
signal \next_mi_addr_reg[3]_i_1_n_5\ : STD_LOGIC;
signal \next_mi_addr_reg[3]_i_1_n_6\ : STD_LOGIC;
signal \next_mi_addr_reg[3]_i_1_n_7\ : STD_LOGIC;
signal \next_mi_addr_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \next_mi_addr_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \next_mi_addr_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \next_mi_addr_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \next_mi_addr_reg[7]_i_1_n_4\ : STD_LOGIC;
signal \next_mi_addr_reg[7]_i_1_n_5\ : STD_LOGIC;
signal \next_mi_addr_reg[7]_i_1_n_6\ : STD_LOGIC;
signal \next_mi_addr_reg[7]_i_1_n_7\ : STD_LOGIC;
signal num_transactions_q : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_0_in : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \pushed_commands[3]_i_1_n_0\ : STD_LOGIC;
signal \pushed_commands_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal pushed_new_cmd : STD_LOGIC;
signal queue_id : STD_LOGIC_VECTOR ( 1 downto 0 );
signal size_mask : STD_LOGIC_VECTOR ( 6 downto 0 );
signal size_mask_q : STD_LOGIC_VECTOR ( 31 downto 0 );
signal split_in_progress_reg_n_0 : STD_LOGIC;
signal split_ongoing : STD_LOGIC;
signal \NLW_next_mi_addr_reg[31]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \addr_step_q[10]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \addr_step_q[11]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \addr_step_q[5]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \addr_step_q[6]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \addr_step_q[7]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \addr_step_q[8]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \addr_step_q[9]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \first_step_q[0]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \first_step_q[10]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \first_step_q[11]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \first_step_q[1]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \first_step_q[3]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \first_step_q[4]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \first_step_q[6]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \first_step_q[7]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \first_step_q[8]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \first_step_q[9]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_axi_awaddr[28]_INST_0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_axi_awlock[0]_INST_0\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \multiple_id_non_split_i_3__0\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \next_mi_addr[11]_i_6\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \next_mi_addr[3]_i_6\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \pushed_commands[1]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \pushed_commands[2]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \pushed_commands[3]_i_2\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \size_mask_q[0]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \size_mask_q[1]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \size_mask_q[2]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \size_mask_q[3]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \size_mask_q[4]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \size_mask_q[5]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \size_mask_q[6]_i_1\ : label is "soft_lutpair53";
begin
E(0) <= \^e\(0);
SR(0) <= \^sr\(0);
areset_d(1 downto 0) <= \^areset_d\(1 downto 0);
command_ongoing_reg_0 <= \^command_ongoing_reg_0\;
din(5 downto 0) <= \^din\(5 downto 0);
\length_counter_1_reg_0__s_port_]\ <= \length_counter_1_reg_0__s_net_1\;
m_axi_awaddr(31 downto 0) <= \^m_axi_awaddr\(31 downto 0);
\S_AXI_AADDR_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(0),
Q => S_AXI_AADDR_Q(0),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(10),
Q => S_AXI_AADDR_Q(10),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(11),
Q => S_AXI_AADDR_Q(11),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(12),
Q => S_AXI_AADDR_Q(12),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(13),
Q => S_AXI_AADDR_Q(13),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(14),
Q => S_AXI_AADDR_Q(14),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(15),
Q => S_AXI_AADDR_Q(15),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(16),
Q => S_AXI_AADDR_Q(16),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(17),
Q => S_AXI_AADDR_Q(17),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(18),
Q => S_AXI_AADDR_Q(18),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(19),
Q => S_AXI_AADDR_Q(19),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(1),
Q => S_AXI_AADDR_Q(1),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(20),
Q => S_AXI_AADDR_Q(20),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(21),
Q => S_AXI_AADDR_Q(21),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(22),
Q => S_AXI_AADDR_Q(22),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(23),
Q => S_AXI_AADDR_Q(23),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(24),
Q => S_AXI_AADDR_Q(24),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(25),
Q => S_AXI_AADDR_Q(25),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(26),
Q => S_AXI_AADDR_Q(26),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(27),
Q => S_AXI_AADDR_Q(27),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(28),
Q => S_AXI_AADDR_Q(28),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(29),
Q => S_AXI_AADDR_Q(29),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(2),
Q => S_AXI_AADDR_Q(2),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(30),
Q => S_AXI_AADDR_Q(30),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(31),
Q => S_AXI_AADDR_Q(31),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(3),
Q => S_AXI_AADDR_Q(3),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(4),
Q => S_AXI_AADDR_Q(4),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(5),
Q => S_AXI_AADDR_Q(5),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(6),
Q => S_AXI_AADDR_Q(6),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(7),
Q => S_AXI_AADDR_Q(7),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(8),
Q => S_AXI_AADDR_Q(8),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(9),
Q => S_AXI_AADDR_Q(9),
R => \^sr\(0)
);
\S_AXI_ABURST_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awburst(0),
Q => m_axi_awburst(0),
R => \^sr\(0)
);
\S_AXI_ABURST_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awburst(1),
Q => m_axi_awburst(1),
R => \^sr\(0)
);
\S_AXI_ACACHE_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awcache(0),
Q => m_axi_awcache(0),
R => \^sr\(0)
);
\S_AXI_ACACHE_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awcache(1),
Q => m_axi_awcache(1),
R => \^sr\(0)
);
\S_AXI_ACACHE_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awcache(2),
Q => m_axi_awcache(2),
R => \^sr\(0)
);
\S_AXI_ACACHE_Q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awcache(3),
Q => m_axi_awcache(3),
R => \^sr\(0)
);
\S_AXI_AID_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awid(0),
Q => \^din\(4),
R => \^sr\(0)
);
\S_AXI_AID_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awid(1),
Q => \^din\(5),
R => \^sr\(0)
);
\S_AXI_ALEN_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awlen(0),
Q => S_AXI_ALEN_Q(0),
R => \^sr\(0)
);
\S_AXI_ALEN_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awlen(1),
Q => S_AXI_ALEN_Q(1),
R => \^sr\(0)
);
\S_AXI_ALEN_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awlen(2),
Q => S_AXI_ALEN_Q(2),
R => \^sr\(0)
);
\S_AXI_ALEN_Q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awlen(3),
Q => S_AXI_ALEN_Q(3),
R => \^sr\(0)
);
\S_AXI_ALOCK_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awlock(0),
Q => \S_AXI_ALOCK_Q_reg_n_0_[0]\,
R => \^sr\(0)
);
\S_AXI_APROT_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awprot(0),
Q => m_axi_awprot(0),
R => \^sr\(0)
);
\S_AXI_APROT_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awprot(1),
Q => m_axi_awprot(1),
R => \^sr\(0)
);
\S_AXI_APROT_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awprot(2),
Q => m_axi_awprot(2),
R => \^sr\(0)
);
\S_AXI_AQOS_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awqos(0),
Q => m_axi_awqos(0),
R => \^sr\(0)
);
\S_AXI_AQOS_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awqos(1),
Q => m_axi_awqos(1),
R => \^sr\(0)
);
\S_AXI_AQOS_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awqos(2),
Q => m_axi_awqos(2),
R => \^sr\(0)
);
\S_AXI_AQOS_Q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awqos(3),
Q => m_axi_awqos(3),
R => \^sr\(0)
);
S_AXI_AREADY_I_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \USE_B_CHANNEL.cmd_b_queue_n_30\,
Q => \^e\(0),
R => \^sr\(0)
);
\S_AXI_ASIZE_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awsize(0),
Q => m_axi_awsize(0),
R => \^sr\(0)
);
\S_AXI_ASIZE_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awsize(1),
Q => m_axi_awsize(1),
R => \^sr\(0)
);
\S_AXI_ASIZE_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awsize(2),
Q => m_axi_awsize(2),
R => \^sr\(0)
);
\USE_BURSTS.cmd_queue\: entity work.system_auto_pc_1_axi_data_fifo_v2_1_10_axic_fifo
port map (
Q(1 downto 0) => \^din\(5 downto 4),
SR(0) => \^sr\(0),
\S_AXI_ALEN_Q_reg[3]\(3 downto 0) => S_AXI_ALEN_Q(3 downto 0),
\USE_B_CHANNEL.cmd_b_empty_reg\ => \USE_BURSTS.cmd_queue_n_13\,
\USE_B_CHANNEL.cmd_b_empty_reg_0\ => \USE_BURSTS.cmd_queue_n_14\,
aclk => aclk,
aresetn => aresetn,
cmd_b_empty => cmd_b_empty,
cmd_empty => cmd_empty,
cmd_push_block => cmd_push_block,
command_ongoing => command_ongoing,
din(3 downto 0) => \^din\(3 downto 0),
dout(5 downto 0) => dout(5 downto 0),
empty => empty,
first_mi_word => first_mi_word,
full => \inst/full\,
length_counter_1_reg(0) => length_counter_1_reg(0),
\length_counter_1_reg_0__s_port_]\ => \length_counter_1_reg_0__s_net_1\,
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
need_to_split_q => need_to_split_q,
\pushed_commands_reg[3]\(3 downto 0) => \pushed_commands_reg__0\(3 downto 0),
queue_id(1 downto 0) => queue_id(1 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid,
wr_cmd_ready => wr_cmd_ready,
wr_en => cmd_push
);
\USE_B_CHANNEL.cmd_b_depth[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \USE_B_CHANNEL.cmd_b_depth_reg__0\(0),
O => \USE_B_CHANNEL.cmd_b_depth[0]_i_1_n_0\
);
\USE_B_CHANNEL.cmd_b_depth_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_B_CHANNEL.cmd_b_queue_n_22\,
D => \USE_B_CHANNEL.cmd_b_depth[0]_i_1_n_0\,
Q => \USE_B_CHANNEL.cmd_b_depth_reg__0\(0),
R => \^sr\(0)
);
\USE_B_CHANNEL.cmd_b_depth_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_B_CHANNEL.cmd_b_queue_n_22\,
D => \USE_B_CHANNEL.cmd_b_queue_n_28\,
Q => \USE_B_CHANNEL.cmd_b_depth_reg__0\(1),
R => \^sr\(0)
);
\USE_B_CHANNEL.cmd_b_depth_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_B_CHANNEL.cmd_b_queue_n_22\,
D => \USE_B_CHANNEL.cmd_b_queue_n_27\,
Q => \USE_B_CHANNEL.cmd_b_depth_reg__0\(2),
R => \^sr\(0)
);
\USE_B_CHANNEL.cmd_b_depth_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_B_CHANNEL.cmd_b_queue_n_22\,
D => \USE_B_CHANNEL.cmd_b_queue_n_26\,
Q => \USE_B_CHANNEL.cmd_b_depth_reg__0\(3),
R => \^sr\(0)
);
\USE_B_CHANNEL.cmd_b_depth_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_B_CHANNEL.cmd_b_queue_n_22\,
D => \USE_B_CHANNEL.cmd_b_queue_n_25\,
Q => \USE_B_CHANNEL.cmd_b_depth_reg__0\(4),
R => \^sr\(0)
);
\USE_B_CHANNEL.cmd_b_depth_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_B_CHANNEL.cmd_b_queue_n_22\,
D => \USE_B_CHANNEL.cmd_b_queue_n_24\,
Q => \USE_B_CHANNEL.cmd_b_depth_reg__0\(5),
R => \^sr\(0)
);
\USE_B_CHANNEL.cmd_b_empty_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \USE_B_CHANNEL.cmd_b_depth_reg__0\(1),
I1 => \USE_B_CHANNEL.cmd_b_depth_reg__0\(0),
I2 => \USE_B_CHANNEL.cmd_b_depth_reg__0\(5),
I3 => \USE_B_CHANNEL.cmd_b_depth_reg__0\(4),
I4 => \USE_B_CHANNEL.cmd_b_depth_reg__0\(3),
I5 => \USE_B_CHANNEL.cmd_b_depth_reg__0\(2),
O => almost_b_empty
);
\USE_B_CHANNEL.cmd_b_empty_reg\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \USE_B_CHANNEL.cmd_b_queue_n_23\,
Q => cmd_b_empty,
S => \^sr\(0)
);
\USE_B_CHANNEL.cmd_b_queue\: entity work.\system_auto_pc_1_axi_data_fifo_v2_1_10_axic_fifo__parameterized0\
port map (
D(4) => \USE_B_CHANNEL.cmd_b_queue_n_7\,
D(3) => \USE_B_CHANNEL.cmd_b_queue_n_8\,
D(2) => \USE_B_CHANNEL.cmd_b_queue_n_9\,
D(1) => \USE_B_CHANNEL.cmd_b_queue_n_10\,
D(0) => \USE_B_CHANNEL.cmd_b_queue_n_11\,
E(0) => \USE_B_CHANNEL.cmd_b_queue_n_13\,
Q(5 downto 0) => \cmd_depth_reg__0\(5 downto 0),
SR(0) => \^sr\(0),
\S_AXI_AID_Q_reg[0]\ => multiple_id_non_split_i_2_n_0,
\S_AXI_AID_Q_reg[1]\(1 downto 0) => \^din\(5 downto 4),
S_AXI_AREADY_I_reg => \USE_B_CHANNEL.cmd_b_queue_n_30\,
S_AXI_AREADY_I_reg_0 => \^e\(0),
\USE_B_CHANNEL.cmd_b_depth_reg[5]\(0) => \USE_B_CHANNEL.cmd_b_queue_n_22\,
\USE_B_CHANNEL.cmd_b_depth_reg[5]_0\(4) => \USE_B_CHANNEL.cmd_b_queue_n_24\,
\USE_B_CHANNEL.cmd_b_depth_reg[5]_0\(3) => \USE_B_CHANNEL.cmd_b_queue_n_25\,
\USE_B_CHANNEL.cmd_b_depth_reg[5]_0\(2) => \USE_B_CHANNEL.cmd_b_queue_n_26\,
\USE_B_CHANNEL.cmd_b_depth_reg[5]_0\(1) => \USE_B_CHANNEL.cmd_b_queue_n_27\,
\USE_B_CHANNEL.cmd_b_depth_reg[5]_0\(0) => \USE_B_CHANNEL.cmd_b_queue_n_28\,
\USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(5 downto 0) => \USE_B_CHANNEL.cmd_b_depth_reg__0\(5 downto 0),
\USE_B_CHANNEL.cmd_b_empty_reg\ => \USE_B_CHANNEL.cmd_b_queue_n_23\,
access_is_incr_q => access_is_incr_q,
aclk => aclk,
almost_b_empty => almost_b_empty,
almost_empty => almost_empty,
areset_d(0) => \^areset_d\(1),
\areset_d_reg[0]\ => \^areset_d\(0),
\areset_d_reg[1]\ => \^command_ongoing_reg_0\,
aresetn => aresetn,
cmd_b_empty => cmd_b_empty,
cmd_b_push_block => cmd_b_push_block,
cmd_b_push_block_reg => \USE_B_CHANNEL.cmd_b_queue_n_21\,
cmd_empty => cmd_empty,
cmd_empty_reg => \USE_B_CHANNEL.cmd_b_queue_n_18\,
cmd_empty_reg_0 => \USE_BURSTS.cmd_queue_n_13\,
cmd_push_block => cmd_push_block,
cmd_push_block_reg => \USE_B_CHANNEL.cmd_b_queue_n_16\,
cmd_push_block_reg_0 => \USE_BURSTS.cmd_queue_n_14\,
command_ongoing => command_ongoing,
command_ongoing_reg => \USE_B_CHANNEL.cmd_b_queue_n_31\,
din(0) => \USE_B_CHANNEL.cmd_b_queue_n_6\,
first_mi_word_reg(4 downto 0) => first_mi_word_reg(4 downto 0),
full => \inst/full\,
\goreg_dm.dout_i_reg[4]\ => \goreg_dm.dout_i_reg[4]\,
\gpregsm1.user_valid_reg\ => \gpregsm1.user_valid_reg\,
incr_need_to_split_q_reg => \multiple_id_non_split_i_3__0_n_0\,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_bvalid => m_axi_bvalid,
multiple_id_non_split => multiple_id_non_split,
multiple_id_non_split_reg => \USE_B_CHANNEL.cmd_b_queue_n_14\,
need_to_split_q => need_to_split_q,
\num_transactions_q_reg[3]\(3 downto 0) => num_transactions_q(3 downto 0),
\pushed_commands_reg[3]\(3 downto 0) => \pushed_commands_reg__0\(3 downto 0),
pushed_new_cmd => pushed_new_cmd,
queue_id(1 downto 0) => queue_id(1 downto 0),
\queue_id_reg[0]\ => \USE_B_CHANNEL.cmd_b_queue_n_19\,
\queue_id_reg[1]\ => \USE_B_CHANNEL.cmd_b_queue_n_20\,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
split_in_progress_reg => \USE_B_CHANNEL.cmd_b_queue_n_15\,
split_in_progress_reg_0 => split_in_progress_reg_n_0,
wr_cmd_b_ready => wr_cmd_b_ready,
wr_cmd_ready => wr_cmd_ready,
wr_en => cmd_push
);
access_is_incr_q_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_awburst(0),
I1 => s_axi_awburst(1),
O => access_is_incr
);
access_is_incr_q_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => access_is_incr,
Q => access_is_incr_q,
R => \^sr\(0)
);
\addr_step_q[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_awsize(1),
I1 => s_axi_awsize(2),
I2 => s_axi_awsize(0),
O => addr_step(10)
);
\addr_step_q[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => s_axi_awsize(1),
I1 => s_axi_awsize(0),
I2 => s_axi_awsize(2),
O => addr_step(11)
);
\addr_step_q[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => s_axi_awsize(2),
I1 => s_axi_awsize(0),
I2 => s_axi_awsize(1),
O => addr_step(5)
);
\addr_step_q[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => s_axi_awsize(0),
I1 => s_axi_awsize(1),
I2 => s_axi_awsize(2),
O => addr_step(6)
);
\addr_step_q[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_awsize(1),
I1 => s_axi_awsize(0),
I2 => s_axi_awsize(2),
O => addr_step(7)
);
\addr_step_q[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => s_axi_awsize(0),
I1 => s_axi_awsize(2),
I2 => s_axi_awsize(1),
O => addr_step(8)
);
\addr_step_q[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_awsize(2),
I1 => s_axi_awsize(0),
I2 => s_axi_awsize(1),
O => addr_step(9)
);
\addr_step_q_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => addr_step(10),
Q => addr_step_q(10),
R => \^sr\(0)
);
\addr_step_q_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => addr_step(11),
Q => addr_step_q(11),
R => \^sr\(0)
);
\addr_step_q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => addr_step(5),
Q => addr_step_q(5),
R => \^sr\(0)
);
\addr_step_q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => addr_step(6),
Q => addr_step_q(6),
R => \^sr\(0)
);
\addr_step_q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => addr_step(7),
Q => addr_step_q(7),
R => \^sr\(0)
);
\addr_step_q_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => addr_step(8),
Q => addr_step_q(8),
R => \^sr\(0)
);
\addr_step_q_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => addr_step(9),
Q => addr_step_q(9),
R => \^sr\(0)
);
\areset_d_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \^sr\(0),
Q => \^areset_d\(0),
R => '0'
);
\areset_d_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \^areset_d\(0),
Q => \^areset_d\(1),
R => '0'
);
cmd_b_push_block_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \USE_B_CHANNEL.cmd_b_queue_n_21\,
Q => cmd_b_push_block,
R => '0'
);
\cmd_depth[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cmd_depth_reg__0\(0),
O => \cmd_depth[0]_i_1_n_0\
);
\cmd_depth_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_B_CHANNEL.cmd_b_queue_n_13\,
D => \cmd_depth[0]_i_1_n_0\,
Q => \cmd_depth_reg__0\(0),
R => \^sr\(0)
);
\cmd_depth_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_B_CHANNEL.cmd_b_queue_n_13\,
D => \USE_B_CHANNEL.cmd_b_queue_n_11\,
Q => \cmd_depth_reg__0\(1),
R => \^sr\(0)
);
\cmd_depth_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_B_CHANNEL.cmd_b_queue_n_13\,
D => \USE_B_CHANNEL.cmd_b_queue_n_10\,
Q => \cmd_depth_reg__0\(2),
R => \^sr\(0)
);
\cmd_depth_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_B_CHANNEL.cmd_b_queue_n_13\,
D => \USE_B_CHANNEL.cmd_b_queue_n_9\,
Q => \cmd_depth_reg__0\(3),
R => \^sr\(0)
);
\cmd_depth_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_B_CHANNEL.cmd_b_queue_n_13\,
D => \USE_B_CHANNEL.cmd_b_queue_n_8\,
Q => \cmd_depth_reg__0\(4),
R => \^sr\(0)
);
\cmd_depth_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_B_CHANNEL.cmd_b_queue_n_13\,
D => \USE_B_CHANNEL.cmd_b_queue_n_7\,
Q => \cmd_depth_reg__0\(5),
R => \^sr\(0)
);
cmd_empty_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => \cmd_depth_reg__0\(2),
I1 => \cmd_depth_reg__0\(3),
I2 => \cmd_depth_reg__0\(5),
I3 => \cmd_depth_reg__0\(4),
I4 => \cmd_depth_reg__0\(1),
I5 => \cmd_depth_reg__0\(0),
O => almost_empty
);
cmd_empty_reg: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \USE_B_CHANNEL.cmd_b_queue_n_18\,
Q => cmd_empty,
S => \^sr\(0)
);
cmd_push_block_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \USE_B_CHANNEL.cmd_b_queue_n_16\,
Q => cmd_push_block,
R => '0'
);
command_ongoing_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^areset_d\(1),
I1 => \^areset_d\(0),
O => \^command_ongoing_reg_0\
);
command_ongoing_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \USE_B_CHANNEL.cmd_b_queue_n_31\,
Q => command_ongoing,
R => \^sr\(0)
);
\first_step_q[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => s_axi_awsize(1),
I1 => s_axi_awsize(0),
I2 => s_axi_awlen(0),
I3 => s_axi_awsize(2),
O => \first_step_q[0]_i_1_n_0\
);
\first_step_q[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_awsize(2),
I1 => \first_step_q[10]_i_2_n_0\,
O => first_step(10)
);
\first_step_q[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"2AAA800080000000"
)
port map (
I0 => s_axi_awsize(1),
I1 => s_axi_awlen(2),
I2 => s_axi_awlen(0),
I3 => s_axi_awlen(1),
I4 => s_axi_awlen(3),
I5 => s_axi_awsize(0),
O => \first_step_q[10]_i_2_n_0\
);
\first_step_q[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_awsize(2),
I1 => \first_step_q[11]_i_2_n_0\,
O => first_step(11)
);
\first_step_q[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => s_axi_awsize(1),
I1 => s_axi_awlen(3),
I2 => s_axi_awlen(1),
I3 => s_axi_awlen(0),
I4 => s_axi_awlen(2),
I5 => s_axi_awsize(0),
O => \first_step_q[11]_i_2_n_0\
);
\first_step_q[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000514"
)
port map (
I0 => s_axi_awsize(1),
I1 => s_axi_awsize(0),
I2 => s_axi_awlen(0),
I3 => s_axi_awlen(1),
I4 => s_axi_awsize(2),
O => \first_step_q[1]_i_1_n_0\
);
\first_step_q[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000F3C6A"
)
port map (
I0 => s_axi_awlen(2),
I1 => s_axi_awlen(1),
I2 => s_axi_awlen(0),
I3 => s_axi_awsize(0),
I4 => s_axi_awsize(1),
I5 => s_axi_awsize(2),
O => \first_step_q[2]_i_1_n_0\
);
\first_step_q[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \first_step_q[7]_i_2_n_0\,
I1 => s_axi_awsize(2),
O => \first_step_q[3]_i_1_n_0\
);
\first_step_q[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0100"
)
port map (
I0 => s_axi_awlen(0),
I1 => s_axi_awsize(0),
I2 => s_axi_awsize(1),
I3 => s_axi_awsize(2),
I4 => \first_step_q[8]_i_2_n_0\,
O => first_step(4)
);
\first_step_q[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0036FFFF00360000"
)
port map (
I0 => s_axi_awlen(1),
I1 => s_axi_awlen(0),
I2 => s_axi_awsize(0),
I3 => s_axi_awsize(1),
I4 => s_axi_awsize(2),
I5 => \first_step_q[9]_i_2_n_0\,
O => first_step(5)
);
\first_step_q[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \first_step_q[6]_i_2_n_0\,
I1 => s_axi_awsize(2),
I2 => \first_step_q[10]_i_2_n_0\,
O => first_step(6)
);
\first_step_q[6]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"07531642"
)
port map (
I0 => s_axi_awsize(1),
I1 => s_axi_awsize(0),
I2 => s_axi_awlen(0),
I3 => s_axi_awlen(1),
I4 => s_axi_awlen(2),
O => \first_step_q[6]_i_2_n_0\
);
\first_step_q[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \first_step_q[7]_i_2_n_0\,
I1 => s_axi_awsize(2),
I2 => \first_step_q[11]_i_2_n_0\,
O => first_step(7)
);
\first_step_q[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"07FD53B916EC42A8"
)
port map (
I0 => s_axi_awsize(1),
I1 => s_axi_awsize(0),
I2 => s_axi_awlen(1),
I3 => s_axi_awlen(0),
I4 => s_axi_awlen(2),
I5 => s_axi_awlen(3),
O => \first_step_q[7]_i_2_n_0\
);
\first_step_q[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_awsize(2),
I1 => \first_step_q[8]_i_2_n_0\,
O => first_step(8)
);
\first_step_q[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"14EAEA6262C8C840"
)
port map (
I0 => s_axi_awsize(1),
I1 => s_axi_awsize(0),
I2 => s_axi_awlen(3),
I3 => s_axi_awlen(1),
I4 => s_axi_awlen(0),
I5 => s_axi_awlen(2),
O => \first_step_q[8]_i_2_n_0\
);
\first_step_q[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_awsize(2),
I1 => \first_step_q[9]_i_2_n_0\,
O => first_step(9)
);
\first_step_q[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"4AA2A2A228808080"
)
port map (
I0 => s_axi_awsize(1),
I1 => s_axi_awsize(0),
I2 => s_axi_awlen(2),
I3 => s_axi_awlen(0),
I4 => s_axi_awlen(1),
I5 => s_axi_awlen(3),
O => \first_step_q[9]_i_2_n_0\
);
\first_step_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \first_step_q[0]_i_1_n_0\,
Q => first_step_q(0),
R => \^sr\(0)
);
\first_step_q_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => first_step(10),
Q => first_step_q(10),
R => \^sr\(0)
);
\first_step_q_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => first_step(11),
Q => first_step_q(11),
R => \^sr\(0)
);
\first_step_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \first_step_q[1]_i_1_n_0\,
Q => first_step_q(1),
R => \^sr\(0)
);
\first_step_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \first_step_q[2]_i_1_n_0\,
Q => first_step_q(2),
R => \^sr\(0)
);
\first_step_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \first_step_q[3]_i_1_n_0\,
Q => first_step_q(3),
R => \^sr\(0)
);
\first_step_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => first_step(4),
Q => first_step_q(4),
R => \^sr\(0)
);
\first_step_q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => first_step(5),
Q => first_step_q(5),
R => \^sr\(0)
);
\first_step_q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => first_step(6),
Q => first_step_q(6),
R => \^sr\(0)
);
\first_step_q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => first_step(7),
Q => first_step_q(7),
R => \^sr\(0)
);
\first_step_q_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => first_step(8),
Q => first_step_q(8),
R => \^sr\(0)
);
\first_step_q_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => first_step(9),
Q => first_step_q(9),
R => \^sr\(0)
);
incr_need_to_split: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444444444440"
)
port map (
I0 => s_axi_awburst(1),
I1 => s_axi_awburst(0),
I2 => s_axi_awlen(5),
I3 => s_axi_awlen(4),
I4 => s_axi_awlen(6),
I5 => s_axi_awlen(7),
O => \incr_need_to_split__0\
);
incr_need_to_split_q_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \incr_need_to_split__0\,
Q => need_to_split_q,
R => \^sr\(0)
);
\m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FFF8000"
)
port map (
I0 => size_mask_q(0),
I1 => next_mi_addr(0),
I2 => access_is_incr_q,
I3 => split_ongoing,
I4 => S_AXI_AADDR_Q(0),
O => \^m_axi_awaddr\(0)
);
\m_axi_awaddr[10]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(10),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(10),
O => \^m_axi_awaddr\(10)
);
\m_axi_awaddr[11]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(11),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(11),
O => \^m_axi_awaddr\(11)
);
\m_axi_awaddr[12]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(12),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(12),
O => \^m_axi_awaddr\(12)
);
\m_axi_awaddr[13]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(13),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(13),
O => \^m_axi_awaddr\(13)
);
\m_axi_awaddr[14]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(14),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(14),
O => \^m_axi_awaddr\(14)
);
\m_axi_awaddr[15]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(15),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(15),
O => \^m_axi_awaddr\(15)
);
\m_axi_awaddr[16]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(16),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(16),
O => \^m_axi_awaddr\(16)
);
\m_axi_awaddr[17]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(17),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(17),
O => \^m_axi_awaddr\(17)
);
\m_axi_awaddr[18]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(18),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(18),
O => \^m_axi_awaddr\(18)
);
\m_axi_awaddr[19]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(19),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(19),
O => \^m_axi_awaddr\(19)
);
\m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FFF8000"
)
port map (
I0 => size_mask_q(1),
I1 => next_mi_addr(1),
I2 => access_is_incr_q,
I3 => split_ongoing,
I4 => S_AXI_AADDR_Q(1),
O => \^m_axi_awaddr\(1)
);
\m_axi_awaddr[20]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(20),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(20),
O => \^m_axi_awaddr\(20)
);
\m_axi_awaddr[21]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(21),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(21),
O => \^m_axi_awaddr\(21)
);
\m_axi_awaddr[22]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(22),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(22),
O => \^m_axi_awaddr\(22)
);
\m_axi_awaddr[23]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(23),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(23),
O => \^m_axi_awaddr\(23)
);
\m_axi_awaddr[24]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(24),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(24),
O => \^m_axi_awaddr\(24)
);
\m_axi_awaddr[25]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(25),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(25),
O => \^m_axi_awaddr\(25)
);
\m_axi_awaddr[26]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(26),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(26),
O => \^m_axi_awaddr\(26)
);
\m_axi_awaddr[27]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(27),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(27),
O => \^m_axi_awaddr\(27)
);
\m_axi_awaddr[28]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(28),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(28),
O => \^m_axi_awaddr\(28)
);
\m_axi_awaddr[29]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(29),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(29),
O => \^m_axi_awaddr\(29)
);
\m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FFF8000"
)
port map (
I0 => size_mask_q(2),
I1 => next_mi_addr(2),
I2 => access_is_incr_q,
I3 => split_ongoing,
I4 => S_AXI_AADDR_Q(2),
O => \^m_axi_awaddr\(2)
);
\m_axi_awaddr[30]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(30),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(30),
O => \^m_axi_awaddr\(30)
);
\m_axi_awaddr[31]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(31),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(31),
O => \^m_axi_awaddr\(31)
);
\m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FFF8000"
)
port map (
I0 => size_mask_q(3),
I1 => next_mi_addr(3),
I2 => access_is_incr_q,
I3 => split_ongoing,
I4 => S_AXI_AADDR_Q(3),
O => \^m_axi_awaddr\(3)
);
\m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FFF8000"
)
port map (
I0 => size_mask_q(4),
I1 => next_mi_addr(4),
I2 => access_is_incr_q,
I3 => split_ongoing,
I4 => S_AXI_AADDR_Q(4),
O => \^m_axi_awaddr\(4)
);
\m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FFF8000"
)
port map (
I0 => size_mask_q(5),
I1 => next_mi_addr(5),
I2 => access_is_incr_q,
I3 => split_ongoing,
I4 => S_AXI_AADDR_Q(5),
O => \^m_axi_awaddr\(5)
);
\m_axi_awaddr[6]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FFF8000"
)
port map (
I0 => size_mask_q(6),
I1 => next_mi_addr(6),
I2 => access_is_incr_q,
I3 => split_ongoing,
I4 => S_AXI_AADDR_Q(6),
O => \^m_axi_awaddr\(6)
);
\m_axi_awaddr[7]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(7),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(7),
O => \^m_axi_awaddr\(7)
);
\m_axi_awaddr[8]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(8),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(8),
O => \^m_axi_awaddr\(8)
);
\m_axi_awaddr[9]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(9),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(9),
O => \^m_axi_awaddr\(9)
);
\m_axi_awlock[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \S_AXI_ALOCK_Q_reg_n_0_[0]\,
I1 => need_to_split_q,
O => m_axi_awlock(0)
);
multiple_id_non_split_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^din\(4),
I1 => queue_id(0),
I2 => \^din\(5),
I3 => queue_id(1),
O => multiple_id_non_split_i_2_n_0
);
\multiple_id_non_split_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"15"
)
port map (
I0 => need_to_split_q,
I1 => \USE_BURSTS.cmd_queue_n_13\,
I2 => split_in_progress_reg_n_0,
O => \multiple_id_non_split_i_3__0_n_0\
);
multiple_id_non_split_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \USE_B_CHANNEL.cmd_b_queue_n_14\,
Q => multiple_id_non_split,
R => '0'
);
\next_mi_addr[11]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => \^m_axi_awaddr\(11),
I1 => addr_step_q(11),
I2 => \next_mi_addr[11]_i_6_n_0\,
I3 => first_step_q(11),
O => \next_mi_addr[11]_i_2_n_0\
);
\next_mi_addr[11]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => \^m_axi_awaddr\(10),
I1 => addr_step_q(10),
I2 => \next_mi_addr[11]_i_6_n_0\,
I3 => first_step_q(10),
O => \next_mi_addr[11]_i_3_n_0\
);
\next_mi_addr[11]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => \^m_axi_awaddr\(9),
I1 => addr_step_q(9),
I2 => \next_mi_addr[11]_i_6_n_0\,
I3 => first_step_q(9),
O => \next_mi_addr[11]_i_4_n_0\
);
\next_mi_addr[11]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => \^m_axi_awaddr\(8),
I1 => addr_step_q(8),
I2 => \next_mi_addr[11]_i_6_n_0\,
I3 => first_step_q(8),
O => \next_mi_addr[11]_i_5_n_0\
);
\next_mi_addr[11]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \pushed_commands_reg__0\(1),
I1 => \pushed_commands_reg__0\(0),
I2 => \pushed_commands_reg__0\(3),
I3 => \pushed_commands_reg__0\(2),
O => \next_mi_addr[11]_i_6_n_0\
);
\next_mi_addr[15]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(15),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(15),
O => \next_mi_addr[15]_i_2_n_0\
);
\next_mi_addr[15]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(14),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(14),
O => \next_mi_addr[15]_i_3_n_0\
);
\next_mi_addr[15]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(13),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(13),
O => \next_mi_addr[15]_i_4_n_0\
);
\next_mi_addr[15]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(12),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(12),
O => \next_mi_addr[15]_i_5_n_0\
);
\next_mi_addr[15]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(15),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(15),
O => \next_mi_addr[15]_i_6_n_0\
);
\next_mi_addr[15]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(14),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(14),
O => \next_mi_addr[15]_i_7_n_0\
);
\next_mi_addr[15]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(13),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(13),
O => \next_mi_addr[15]_i_8_n_0\
);
\next_mi_addr[15]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(12),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(12),
O => \next_mi_addr[15]_i_9_n_0\
);
\next_mi_addr[19]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(19),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(19),
O => \next_mi_addr[19]_i_2_n_0\
);
\next_mi_addr[19]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(18),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(18),
O => \next_mi_addr[19]_i_3_n_0\
);
\next_mi_addr[19]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(17),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(17),
O => \next_mi_addr[19]_i_4_n_0\
);
\next_mi_addr[19]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(16),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(16),
O => \next_mi_addr[19]_i_5_n_0\
);
\next_mi_addr[23]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(23),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(23),
O => \next_mi_addr[23]_i_2_n_0\
);
\next_mi_addr[23]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(22),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(22),
O => \next_mi_addr[23]_i_3_n_0\
);
\next_mi_addr[23]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(21),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(21),
O => \next_mi_addr[23]_i_4_n_0\
);
\next_mi_addr[23]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(20),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(20),
O => \next_mi_addr[23]_i_5_n_0\
);
\next_mi_addr[27]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(27),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(27),
O => \next_mi_addr[27]_i_2_n_0\
);
\next_mi_addr[27]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(26),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(26),
O => \next_mi_addr[27]_i_3_n_0\
);
\next_mi_addr[27]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(25),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(25),
O => \next_mi_addr[27]_i_4_n_0\
);
\next_mi_addr[27]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(24),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(24),
O => \next_mi_addr[27]_i_5_n_0\
);
\next_mi_addr[31]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(31),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(31),
O => \next_mi_addr[31]_i_2_n_0\
);
\next_mi_addr[31]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(30),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(30),
O => \next_mi_addr[31]_i_3_n_0\
);
\next_mi_addr[31]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(29),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(29),
O => \next_mi_addr[31]_i_4_n_0\
);
\next_mi_addr[31]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(28),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(28),
O => \next_mi_addr[31]_i_5_n_0\
);
\next_mi_addr[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"1DDDE222E222E222"
)
port map (
I0 => S_AXI_AADDR_Q(3),
I1 => \next_mi_addr[3]_i_6_n_0\,
I2 => next_mi_addr(3),
I3 => size_mask_q(3),
I4 => \next_mi_addr[11]_i_6_n_0\,
I5 => first_step_q(3),
O => \next_mi_addr[3]_i_2_n_0\
);
\next_mi_addr[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"1DDDE222E222E222"
)
port map (
I0 => S_AXI_AADDR_Q(2),
I1 => \next_mi_addr[3]_i_6_n_0\,
I2 => next_mi_addr(2),
I3 => size_mask_q(2),
I4 => \next_mi_addr[11]_i_6_n_0\,
I5 => first_step_q(2),
O => \next_mi_addr[3]_i_3_n_0\
);
\next_mi_addr[3]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"1DDDE222E222E222"
)
port map (
I0 => S_AXI_AADDR_Q(1),
I1 => \next_mi_addr[3]_i_6_n_0\,
I2 => next_mi_addr(1),
I3 => size_mask_q(1),
I4 => \next_mi_addr[11]_i_6_n_0\,
I5 => first_step_q(1),
O => \next_mi_addr[3]_i_4_n_0\
);
\next_mi_addr[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"1DDDE222E222E222"
)
port map (
I0 => S_AXI_AADDR_Q(0),
I1 => \next_mi_addr[3]_i_6_n_0\,
I2 => next_mi_addr(0),
I3 => size_mask_q(0),
I4 => \next_mi_addr[11]_i_6_n_0\,
I5 => first_step_q(0),
O => \next_mi_addr[3]_i_5_n_0\
);
\next_mi_addr[3]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => access_is_incr_q,
I1 => split_ongoing,
O => \next_mi_addr[3]_i_6_n_0\
);
\next_mi_addr[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => \^m_axi_awaddr\(7),
I1 => addr_step_q(7),
I2 => \next_mi_addr[11]_i_6_n_0\,
I3 => first_step_q(7),
O => \next_mi_addr[7]_i_2_n_0\
);
\next_mi_addr[7]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => \^m_axi_awaddr\(6),
I1 => addr_step_q(6),
I2 => \next_mi_addr[11]_i_6_n_0\,
I3 => first_step_q(6),
O => \next_mi_addr[7]_i_3_n_0\
);
\next_mi_addr[7]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => \^m_axi_awaddr\(5),
I1 => addr_step_q(5),
I2 => \next_mi_addr[11]_i_6_n_0\,
I3 => first_step_q(5),
O => \next_mi_addr[7]_i_4_n_0\
);
\next_mi_addr[7]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => \^m_axi_awaddr\(4),
I1 => size_mask_q(0),
I2 => \next_mi_addr[11]_i_6_n_0\,
I3 => first_step_q(4),
O => \next_mi_addr[7]_i_5_n_0\
);
\next_mi_addr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[3]_i_1_n_7\,
Q => next_mi_addr(0),
R => \^sr\(0)
);
\next_mi_addr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[11]_i_1_n_5\,
Q => next_mi_addr(10),
R => \^sr\(0)
);
\next_mi_addr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[11]_i_1_n_4\,
Q => next_mi_addr(11),
R => \^sr\(0)
);
\next_mi_addr_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \next_mi_addr_reg[7]_i_1_n_0\,
CO(3) => \next_mi_addr_reg[11]_i_1_n_0\,
CO(2) => \next_mi_addr_reg[11]_i_1_n_1\,
CO(1) => \next_mi_addr_reg[11]_i_1_n_2\,
CO(0) => \next_mi_addr_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^m_axi_awaddr\(11 downto 8),
O(3) => \next_mi_addr_reg[11]_i_1_n_4\,
O(2) => \next_mi_addr_reg[11]_i_1_n_5\,
O(1) => \next_mi_addr_reg[11]_i_1_n_6\,
O(0) => \next_mi_addr_reg[11]_i_1_n_7\,
S(3) => \next_mi_addr[11]_i_2_n_0\,
S(2) => \next_mi_addr[11]_i_3_n_0\,
S(1) => \next_mi_addr[11]_i_4_n_0\,
S(0) => \next_mi_addr[11]_i_5_n_0\
);
\next_mi_addr_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[15]_i_1_n_7\,
Q => next_mi_addr(12),
R => \^sr\(0)
);
\next_mi_addr_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[15]_i_1_n_6\,
Q => next_mi_addr(13),
R => \^sr\(0)
);
\next_mi_addr_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[15]_i_1_n_5\,
Q => next_mi_addr(14),
R => \^sr\(0)
);
\next_mi_addr_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[15]_i_1_n_4\,
Q => next_mi_addr(15),
R => \^sr\(0)
);
\next_mi_addr_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \next_mi_addr_reg[11]_i_1_n_0\,
CO(3) => \next_mi_addr_reg[15]_i_1_n_0\,
CO(2) => \next_mi_addr_reg[15]_i_1_n_1\,
CO(1) => \next_mi_addr_reg[15]_i_1_n_2\,
CO(0) => \next_mi_addr_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => \next_mi_addr[15]_i_2_n_0\,
DI(2) => \next_mi_addr[15]_i_3_n_0\,
DI(1) => \next_mi_addr[15]_i_4_n_0\,
DI(0) => \next_mi_addr[15]_i_5_n_0\,
O(3) => \next_mi_addr_reg[15]_i_1_n_4\,
O(2) => \next_mi_addr_reg[15]_i_1_n_5\,
O(1) => \next_mi_addr_reg[15]_i_1_n_6\,
O(0) => \next_mi_addr_reg[15]_i_1_n_7\,
S(3) => \next_mi_addr[15]_i_6_n_0\,
S(2) => \next_mi_addr[15]_i_7_n_0\,
S(1) => \next_mi_addr[15]_i_8_n_0\,
S(0) => \next_mi_addr[15]_i_9_n_0\
);
\next_mi_addr_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[19]_i_1_n_7\,
Q => next_mi_addr(16),
R => \^sr\(0)
);
\next_mi_addr_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[19]_i_1_n_6\,
Q => next_mi_addr(17),
R => \^sr\(0)
);
\next_mi_addr_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[19]_i_1_n_5\,
Q => next_mi_addr(18),
R => \^sr\(0)
);
\next_mi_addr_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[19]_i_1_n_4\,
Q => next_mi_addr(19),
R => \^sr\(0)
);
\next_mi_addr_reg[19]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \next_mi_addr_reg[15]_i_1_n_0\,
CO(3) => \next_mi_addr_reg[19]_i_1_n_0\,
CO(2) => \next_mi_addr_reg[19]_i_1_n_1\,
CO(1) => \next_mi_addr_reg[19]_i_1_n_2\,
CO(0) => \next_mi_addr_reg[19]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \next_mi_addr_reg[19]_i_1_n_4\,
O(2) => \next_mi_addr_reg[19]_i_1_n_5\,
O(1) => \next_mi_addr_reg[19]_i_1_n_6\,
O(0) => \next_mi_addr_reg[19]_i_1_n_7\,
S(3) => \next_mi_addr[19]_i_2_n_0\,
S(2) => \next_mi_addr[19]_i_3_n_0\,
S(1) => \next_mi_addr[19]_i_4_n_0\,
S(0) => \next_mi_addr[19]_i_5_n_0\
);
\next_mi_addr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[3]_i_1_n_6\,
Q => next_mi_addr(1),
R => \^sr\(0)
);
\next_mi_addr_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[23]_i_1_n_7\,
Q => next_mi_addr(20),
R => \^sr\(0)
);
\next_mi_addr_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[23]_i_1_n_6\,
Q => next_mi_addr(21),
R => \^sr\(0)
);
\next_mi_addr_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[23]_i_1_n_5\,
Q => next_mi_addr(22),
R => \^sr\(0)
);
\next_mi_addr_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[23]_i_1_n_4\,
Q => next_mi_addr(23),
R => \^sr\(0)
);
\next_mi_addr_reg[23]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \next_mi_addr_reg[19]_i_1_n_0\,
CO(3) => \next_mi_addr_reg[23]_i_1_n_0\,
CO(2) => \next_mi_addr_reg[23]_i_1_n_1\,
CO(1) => \next_mi_addr_reg[23]_i_1_n_2\,
CO(0) => \next_mi_addr_reg[23]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \next_mi_addr_reg[23]_i_1_n_4\,
O(2) => \next_mi_addr_reg[23]_i_1_n_5\,
O(1) => \next_mi_addr_reg[23]_i_1_n_6\,
O(0) => \next_mi_addr_reg[23]_i_1_n_7\,
S(3) => \next_mi_addr[23]_i_2_n_0\,
S(2) => \next_mi_addr[23]_i_3_n_0\,
S(1) => \next_mi_addr[23]_i_4_n_0\,
S(0) => \next_mi_addr[23]_i_5_n_0\
);
\next_mi_addr_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[27]_i_1_n_7\,
Q => next_mi_addr(24),
R => \^sr\(0)
);
\next_mi_addr_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[27]_i_1_n_6\,
Q => next_mi_addr(25),
R => \^sr\(0)
);
\next_mi_addr_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[27]_i_1_n_5\,
Q => next_mi_addr(26),
R => \^sr\(0)
);
\next_mi_addr_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[27]_i_1_n_4\,
Q => next_mi_addr(27),
R => \^sr\(0)
);
\next_mi_addr_reg[27]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \next_mi_addr_reg[23]_i_1_n_0\,
CO(3) => \next_mi_addr_reg[27]_i_1_n_0\,
CO(2) => \next_mi_addr_reg[27]_i_1_n_1\,
CO(1) => \next_mi_addr_reg[27]_i_1_n_2\,
CO(0) => \next_mi_addr_reg[27]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \next_mi_addr_reg[27]_i_1_n_4\,
O(2) => \next_mi_addr_reg[27]_i_1_n_5\,
O(1) => \next_mi_addr_reg[27]_i_1_n_6\,
O(0) => \next_mi_addr_reg[27]_i_1_n_7\,
S(3) => \next_mi_addr[27]_i_2_n_0\,
S(2) => \next_mi_addr[27]_i_3_n_0\,
S(1) => \next_mi_addr[27]_i_4_n_0\,
S(0) => \next_mi_addr[27]_i_5_n_0\
);
\next_mi_addr_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[31]_i_1_n_7\,
Q => next_mi_addr(28),
R => \^sr\(0)
);
\next_mi_addr_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[31]_i_1_n_6\,
Q => next_mi_addr(29),
R => \^sr\(0)
);
\next_mi_addr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[3]_i_1_n_5\,
Q => next_mi_addr(2),
R => \^sr\(0)
);
\next_mi_addr_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[31]_i_1_n_5\,
Q => next_mi_addr(30),
R => \^sr\(0)
);
\next_mi_addr_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[31]_i_1_n_4\,
Q => next_mi_addr(31),
R => \^sr\(0)
);
\next_mi_addr_reg[31]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \next_mi_addr_reg[27]_i_1_n_0\,
CO(3) => \NLW_next_mi_addr_reg[31]_i_1_CO_UNCONNECTED\(3),
CO(2) => \next_mi_addr_reg[31]_i_1_n_1\,
CO(1) => \next_mi_addr_reg[31]_i_1_n_2\,
CO(0) => \next_mi_addr_reg[31]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \next_mi_addr_reg[31]_i_1_n_4\,
O(2) => \next_mi_addr_reg[31]_i_1_n_5\,
O(1) => \next_mi_addr_reg[31]_i_1_n_6\,
O(0) => \next_mi_addr_reg[31]_i_1_n_7\,
S(3) => \next_mi_addr[31]_i_2_n_0\,
S(2) => \next_mi_addr[31]_i_3_n_0\,
S(1) => \next_mi_addr[31]_i_4_n_0\,
S(0) => \next_mi_addr[31]_i_5_n_0\
);
\next_mi_addr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[3]_i_1_n_4\,
Q => next_mi_addr(3),
R => \^sr\(0)
);
\next_mi_addr_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \next_mi_addr_reg[3]_i_1_n_0\,
CO(2) => \next_mi_addr_reg[3]_i_1_n_1\,
CO(1) => \next_mi_addr_reg[3]_i_1_n_2\,
CO(0) => \next_mi_addr_reg[3]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^m_axi_awaddr\(3 downto 0),
O(3) => \next_mi_addr_reg[3]_i_1_n_4\,
O(2) => \next_mi_addr_reg[3]_i_1_n_5\,
O(1) => \next_mi_addr_reg[3]_i_1_n_6\,
O(0) => \next_mi_addr_reg[3]_i_1_n_7\,
S(3) => \next_mi_addr[3]_i_2_n_0\,
S(2) => \next_mi_addr[3]_i_3_n_0\,
S(1) => \next_mi_addr[3]_i_4_n_0\,
S(0) => \next_mi_addr[3]_i_5_n_0\
);
\next_mi_addr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[7]_i_1_n_7\,
Q => next_mi_addr(4),
R => \^sr\(0)
);
\next_mi_addr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[7]_i_1_n_6\,
Q => next_mi_addr(5),
R => \^sr\(0)
);
\next_mi_addr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[7]_i_1_n_5\,
Q => next_mi_addr(6),
R => \^sr\(0)
);
\next_mi_addr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[7]_i_1_n_4\,
Q => next_mi_addr(7),
R => \^sr\(0)
);
\next_mi_addr_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \next_mi_addr_reg[3]_i_1_n_0\,
CO(3) => \next_mi_addr_reg[7]_i_1_n_0\,
CO(2) => \next_mi_addr_reg[7]_i_1_n_1\,
CO(1) => \next_mi_addr_reg[7]_i_1_n_2\,
CO(0) => \next_mi_addr_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^m_axi_awaddr\(7 downto 4),
O(3) => \next_mi_addr_reg[7]_i_1_n_4\,
O(2) => \next_mi_addr_reg[7]_i_1_n_5\,
O(1) => \next_mi_addr_reg[7]_i_1_n_6\,
O(0) => \next_mi_addr_reg[7]_i_1_n_7\,
S(3) => \next_mi_addr[7]_i_2_n_0\,
S(2) => \next_mi_addr[7]_i_3_n_0\,
S(1) => \next_mi_addr[7]_i_4_n_0\,
S(0) => \next_mi_addr[7]_i_5_n_0\
);
\next_mi_addr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[11]_i_1_n_7\,
Q => next_mi_addr(8),
R => \^sr\(0)
);
\next_mi_addr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[11]_i_1_n_6\,
Q => next_mi_addr(9),
R => \^sr\(0)
);
\num_transactions_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awlen(4),
Q => num_transactions_q(0),
R => \^sr\(0)
);
\num_transactions_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awlen(5),
Q => num_transactions_q(1),
R => \^sr\(0)
);
\num_transactions_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awlen(6),
Q => num_transactions_q(2),
R => \^sr\(0)
);
\num_transactions_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awlen(7),
Q => num_transactions_q(3),
R => \^sr\(0)
);
\pushed_commands[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \pushed_commands_reg__0\(0),
O => p_0_in(0)
);
\pushed_commands[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \pushed_commands_reg__0\(0),
I1 => \pushed_commands_reg__0\(1),
O => p_0_in(1)
);
\pushed_commands[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \pushed_commands_reg__0\(2),
I1 => \pushed_commands_reg__0\(1),
I2 => \pushed_commands_reg__0\(0),
O => p_0_in(2)
);
\pushed_commands[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^e\(0),
I1 => aresetn,
O => \pushed_commands[3]_i_1_n_0\
);
\pushed_commands[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \pushed_commands_reg__0\(3),
I1 => \pushed_commands_reg__0\(0),
I2 => \pushed_commands_reg__0\(1),
I3 => \pushed_commands_reg__0\(2),
O => p_0_in(3)
);
\pushed_commands_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => p_0_in(0),
Q => \pushed_commands_reg__0\(0),
R => \pushed_commands[3]_i_1_n_0\
);
\pushed_commands_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => p_0_in(1),
Q => \pushed_commands_reg__0\(1),
R => \pushed_commands[3]_i_1_n_0\
);
\pushed_commands_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => p_0_in(2),
Q => \pushed_commands_reg__0\(2),
R => \pushed_commands[3]_i_1_n_0\
);
\pushed_commands_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => p_0_in(3),
Q => \pushed_commands_reg__0\(3),
R => \pushed_commands[3]_i_1_n_0\
);
\queue_id_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \USE_B_CHANNEL.cmd_b_queue_n_19\,
Q => queue_id(0),
R => \^sr\(0)
);
\queue_id_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \USE_B_CHANNEL.cmd_b_queue_n_20\,
Q => queue_id(1),
R => \^sr\(0)
);
\size_mask_q[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => s_axi_awsize(2),
I1 => s_axi_awsize(0),
I2 => s_axi_awsize(1),
O => size_mask(0)
);
\size_mask_q[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_awsize(2),
I1 => s_axi_awsize(1),
O => size_mask(1)
);
\size_mask_q[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"07"
)
port map (
I0 => s_axi_awsize(0),
I1 => s_axi_awsize(1),
I2 => s_axi_awsize(2),
O => size_mask(2)
);
\size_mask_q[3]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_awsize(2),
O => size_mask(3)
);
\size_mask_q[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"57"
)
port map (
I0 => s_axi_awsize(2),
I1 => s_axi_awsize(0),
I2 => s_axi_awsize(1),
O => size_mask(4)
);
\size_mask_q[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => s_axi_awsize(2),
I1 => s_axi_awsize(1),
O => size_mask(5)
);
\size_mask_q[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => s_axi_awsize(2),
I1 => s_axi_awsize(0),
I2 => s_axi_awsize(1),
O => size_mask(6)
);
\size_mask_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => size_mask(0),
Q => size_mask_q(0),
R => \^sr\(0)
);
\size_mask_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => size_mask(1),
Q => size_mask_q(1),
R => \^sr\(0)
);
\size_mask_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => size_mask(2),
Q => size_mask_q(2),
R => \^sr\(0)
);
\size_mask_q_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => '1',
Q => size_mask_q(31),
R => \^sr\(0)
);
\size_mask_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => size_mask(3),
Q => size_mask_q(3),
R => \^sr\(0)
);
\size_mask_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => size_mask(4),
Q => size_mask_q(4),
R => \^sr\(0)
);
\size_mask_q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => size_mask(5),
Q => size_mask_q(5),
R => \^sr\(0)
);
\size_mask_q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => size_mask(6),
Q => size_mask_q(6),
R => \^sr\(0)
);
split_in_progress_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \USE_B_CHANNEL.cmd_b_queue_n_15\,
Q => split_in_progress_reg_n_0,
R => '0'
);
split_ongoing_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \USE_B_CHANNEL.cmd_b_queue_n_6\,
Q => split_ongoing,
R => \^sr\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_axi_protocol_converter_v2_1_11_a_axi3_conv__parameterized0\ is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arvalid : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rlast : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_rlast : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
aresetn : in STD_LOGIC;
areset_d : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
\areset_d_reg[1]\ : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_axi_protocol_converter_v2_1_11_a_axi3_conv__parameterized0\ : entity is "axi_protocol_converter_v2_1_11_a_axi3_conv";
end \system_auto_pc_1_axi_protocol_converter_v2_1_11_a_axi3_conv__parameterized0\;
architecture STRUCTURE of \system_auto_pc_1_axi_protocol_converter_v2_1_11_a_axi3_conv__parameterized0\ is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \S_AXI_AADDR_Q_reg_n_0_[0]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[10]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[11]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[12]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[13]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[14]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[15]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[16]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[17]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[18]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[19]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[1]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[20]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[21]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[22]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[23]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[24]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[25]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[26]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[27]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[28]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[29]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[2]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[30]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[31]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[3]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[4]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[5]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[6]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[7]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[8]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[9]\ : STD_LOGIC;
signal S_AXI_ALEN_Q : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \S_AXI_ALOCK_Q_reg_n_0_[0]\ : STD_LOGIC;
signal \USE_R_CHANNEL.cmd_queue_n_0\ : STD_LOGIC;
signal \USE_R_CHANNEL.cmd_queue_n_14\ : STD_LOGIC;
signal \USE_R_CHANNEL.cmd_queue_n_15\ : STD_LOGIC;
signal \USE_R_CHANNEL.cmd_queue_n_16\ : STD_LOGIC;
signal \USE_R_CHANNEL.cmd_queue_n_17\ : STD_LOGIC;
signal \USE_R_CHANNEL.cmd_queue_n_18\ : STD_LOGIC;
signal \USE_R_CHANNEL.cmd_queue_n_3\ : STD_LOGIC;
signal \USE_R_CHANNEL.cmd_queue_n_4\ : STD_LOGIC;
signal \USE_R_CHANNEL.cmd_queue_n_5\ : STD_LOGIC;
signal \USE_R_CHANNEL.cmd_queue_n_6\ : STD_LOGIC;
signal \USE_R_CHANNEL.cmd_queue_n_7\ : STD_LOGIC;
signal \USE_R_CHANNEL.cmd_queue_n_9\ : STD_LOGIC;
signal access_is_incr : STD_LOGIC;
signal access_is_incr_q : STD_LOGIC;
signal \addr_step_q[10]_i_1__0_n_0\ : STD_LOGIC;
signal \addr_step_q[11]_i_1__0_n_0\ : STD_LOGIC;
signal \addr_step_q[5]_i_1__0_n_0\ : STD_LOGIC;
signal \addr_step_q[6]_i_1__0_n_0\ : STD_LOGIC;
signal \addr_step_q[7]_i_1__0_n_0\ : STD_LOGIC;
signal \addr_step_q[8]_i_1__0_n_0\ : STD_LOGIC;
signal \addr_step_q[9]_i_1__0_n_0\ : STD_LOGIC;
signal \addr_step_q_reg_n_0_[10]\ : STD_LOGIC;
signal \addr_step_q_reg_n_0_[11]\ : STD_LOGIC;
signal \addr_step_q_reg_n_0_[5]\ : STD_LOGIC;
signal \addr_step_q_reg_n_0_[6]\ : STD_LOGIC;
signal \addr_step_q_reg_n_0_[7]\ : STD_LOGIC;
signal \addr_step_q_reg_n_0_[8]\ : STD_LOGIC;
signal \addr_step_q_reg_n_0_[9]\ : STD_LOGIC;
signal almost_empty : STD_LOGIC;
signal \cmd_depth[0]_i_1__0_n_0\ : STD_LOGIC;
signal \cmd_depth_reg__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal cmd_empty : STD_LOGIC;
signal cmd_empty_i_1_n_0 : STD_LOGIC;
signal cmd_push : STD_LOGIC;
signal cmd_push_block : STD_LOGIC;
signal command_ongoing : STD_LOGIC;
signal first_step : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \first_step_q[0]_i_1__0_n_0\ : STD_LOGIC;
signal \first_step_q[10]_i_2__0_n_0\ : STD_LOGIC;
signal \first_step_q[11]_i_2__0_n_0\ : STD_LOGIC;
signal \first_step_q[1]_i_1__0_n_0\ : STD_LOGIC;
signal \first_step_q[2]_i_1__0_n_0\ : STD_LOGIC;
signal \first_step_q[3]_i_1__0_n_0\ : STD_LOGIC;
signal \first_step_q[6]_i_2__0_n_0\ : STD_LOGIC;
signal \first_step_q[7]_i_2__0_n_0\ : STD_LOGIC;
signal \first_step_q[8]_i_2__0_n_0\ : STD_LOGIC;
signal \first_step_q[9]_i_2__0_n_0\ : STD_LOGIC;
signal \first_step_q_reg_n_0_[0]\ : STD_LOGIC;
signal \first_step_q_reg_n_0_[10]\ : STD_LOGIC;
signal \first_step_q_reg_n_0_[11]\ : STD_LOGIC;
signal \first_step_q_reg_n_0_[1]\ : STD_LOGIC;
signal \first_step_q_reg_n_0_[2]\ : STD_LOGIC;
signal \first_step_q_reg_n_0_[3]\ : STD_LOGIC;
signal \first_step_q_reg_n_0_[4]\ : STD_LOGIC;
signal \first_step_q_reg_n_0_[5]\ : STD_LOGIC;
signal \first_step_q_reg_n_0_[6]\ : STD_LOGIC;
signal \first_step_q_reg_n_0_[7]\ : STD_LOGIC;
signal \first_step_q_reg_n_0_[8]\ : STD_LOGIC;
signal \first_step_q_reg_n_0_[9]\ : STD_LOGIC;
signal \incr_need_to_split__0\ : STD_LOGIC;
signal \^m_axi_araddr\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal multiple_id_non_split : STD_LOGIC;
signal \multiple_id_non_split_i_2__0_n_0\ : STD_LOGIC;
signal multiple_id_non_split_i_3_n_0 : STD_LOGIC;
signal need_to_split_q : STD_LOGIC;
signal next_mi_addr : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \next_mi_addr[11]_i_2_n_0\ : STD_LOGIC;
signal \next_mi_addr[11]_i_3_n_0\ : STD_LOGIC;
signal \next_mi_addr[11]_i_4_n_0\ : STD_LOGIC;
signal \next_mi_addr[11]_i_5_n_0\ : STD_LOGIC;
signal \next_mi_addr[11]_i_6__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[15]_i_2__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[15]_i_3__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[15]_i_4__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[15]_i_5__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[15]_i_6__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[15]_i_7__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[15]_i_8__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[15]_i_9__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[19]_i_2__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[19]_i_3__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[19]_i_4__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[19]_i_5__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[23]_i_2__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[23]_i_3__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[23]_i_4__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[23]_i_5__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[27]_i_2__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[27]_i_3__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[27]_i_4__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[27]_i_5__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[31]_i_2__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[31]_i_3__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[31]_i_4__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[31]_i_5__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[3]_i_2_n_0\ : STD_LOGIC;
signal \next_mi_addr[3]_i_3_n_0\ : STD_LOGIC;
signal \next_mi_addr[3]_i_4_n_0\ : STD_LOGIC;
signal \next_mi_addr[3]_i_5_n_0\ : STD_LOGIC;
signal \next_mi_addr[3]_i_6__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[7]_i_2_n_0\ : STD_LOGIC;
signal \next_mi_addr[7]_i_3_n_0\ : STD_LOGIC;
signal \next_mi_addr[7]_i_4_n_0\ : STD_LOGIC;
signal \next_mi_addr[7]_i_5_n_0\ : STD_LOGIC;
signal \next_mi_addr_reg[11]_i_1__0_n_0\ : STD_LOGIC;
signal \next_mi_addr_reg[11]_i_1__0_n_1\ : STD_LOGIC;
signal \next_mi_addr_reg[11]_i_1__0_n_2\ : STD_LOGIC;
signal \next_mi_addr_reg[11]_i_1__0_n_3\ : STD_LOGIC;
signal \next_mi_addr_reg[11]_i_1__0_n_4\ : STD_LOGIC;
signal \next_mi_addr_reg[11]_i_1__0_n_5\ : STD_LOGIC;
signal \next_mi_addr_reg[11]_i_1__0_n_6\ : STD_LOGIC;
signal \next_mi_addr_reg[11]_i_1__0_n_7\ : STD_LOGIC;
signal \next_mi_addr_reg[15]_i_1__0_n_0\ : STD_LOGIC;
signal \next_mi_addr_reg[15]_i_1__0_n_1\ : STD_LOGIC;
signal \next_mi_addr_reg[15]_i_1__0_n_2\ : STD_LOGIC;
signal \next_mi_addr_reg[15]_i_1__0_n_3\ : STD_LOGIC;
signal \next_mi_addr_reg[15]_i_1__0_n_4\ : STD_LOGIC;
signal \next_mi_addr_reg[15]_i_1__0_n_5\ : STD_LOGIC;
signal \next_mi_addr_reg[15]_i_1__0_n_6\ : STD_LOGIC;
signal \next_mi_addr_reg[15]_i_1__0_n_7\ : STD_LOGIC;
signal \next_mi_addr_reg[19]_i_1__0_n_0\ : STD_LOGIC;
signal \next_mi_addr_reg[19]_i_1__0_n_1\ : STD_LOGIC;
signal \next_mi_addr_reg[19]_i_1__0_n_2\ : STD_LOGIC;
signal \next_mi_addr_reg[19]_i_1__0_n_3\ : STD_LOGIC;
signal \next_mi_addr_reg[19]_i_1__0_n_4\ : STD_LOGIC;
signal \next_mi_addr_reg[19]_i_1__0_n_5\ : STD_LOGIC;
signal \next_mi_addr_reg[19]_i_1__0_n_6\ : STD_LOGIC;
signal \next_mi_addr_reg[19]_i_1__0_n_7\ : STD_LOGIC;
signal \next_mi_addr_reg[23]_i_1__0_n_0\ : STD_LOGIC;
signal \next_mi_addr_reg[23]_i_1__0_n_1\ : STD_LOGIC;
signal \next_mi_addr_reg[23]_i_1__0_n_2\ : STD_LOGIC;
signal \next_mi_addr_reg[23]_i_1__0_n_3\ : STD_LOGIC;
signal \next_mi_addr_reg[23]_i_1__0_n_4\ : STD_LOGIC;
signal \next_mi_addr_reg[23]_i_1__0_n_5\ : STD_LOGIC;
signal \next_mi_addr_reg[23]_i_1__0_n_6\ : STD_LOGIC;
signal \next_mi_addr_reg[23]_i_1__0_n_7\ : STD_LOGIC;
signal \next_mi_addr_reg[27]_i_1__0_n_0\ : STD_LOGIC;
signal \next_mi_addr_reg[27]_i_1__0_n_1\ : STD_LOGIC;
signal \next_mi_addr_reg[27]_i_1__0_n_2\ : STD_LOGIC;
signal \next_mi_addr_reg[27]_i_1__0_n_3\ : STD_LOGIC;
signal \next_mi_addr_reg[27]_i_1__0_n_4\ : STD_LOGIC;
signal \next_mi_addr_reg[27]_i_1__0_n_5\ : STD_LOGIC;
signal \next_mi_addr_reg[27]_i_1__0_n_6\ : STD_LOGIC;
signal \next_mi_addr_reg[27]_i_1__0_n_7\ : STD_LOGIC;
signal \next_mi_addr_reg[31]_i_1__0_n_1\ : STD_LOGIC;
signal \next_mi_addr_reg[31]_i_1__0_n_2\ : STD_LOGIC;
signal \next_mi_addr_reg[31]_i_1__0_n_3\ : STD_LOGIC;
signal \next_mi_addr_reg[31]_i_1__0_n_4\ : STD_LOGIC;
signal \next_mi_addr_reg[31]_i_1__0_n_5\ : STD_LOGIC;
signal \next_mi_addr_reg[31]_i_1__0_n_6\ : STD_LOGIC;
signal \next_mi_addr_reg[31]_i_1__0_n_7\ : STD_LOGIC;
signal \next_mi_addr_reg[3]_i_1__0_n_0\ : STD_LOGIC;
signal \next_mi_addr_reg[3]_i_1__0_n_1\ : STD_LOGIC;
signal \next_mi_addr_reg[3]_i_1__0_n_2\ : STD_LOGIC;
signal \next_mi_addr_reg[3]_i_1__0_n_3\ : STD_LOGIC;
signal \next_mi_addr_reg[3]_i_1__0_n_4\ : STD_LOGIC;
signal \next_mi_addr_reg[3]_i_1__0_n_5\ : STD_LOGIC;
signal \next_mi_addr_reg[3]_i_1__0_n_6\ : STD_LOGIC;
signal \next_mi_addr_reg[3]_i_1__0_n_7\ : STD_LOGIC;
signal \next_mi_addr_reg[7]_i_1__0_n_0\ : STD_LOGIC;
signal \next_mi_addr_reg[7]_i_1__0_n_1\ : STD_LOGIC;
signal \next_mi_addr_reg[7]_i_1__0_n_2\ : STD_LOGIC;
signal \next_mi_addr_reg[7]_i_1__0_n_3\ : STD_LOGIC;
signal \next_mi_addr_reg[7]_i_1__0_n_4\ : STD_LOGIC;
signal \next_mi_addr_reg[7]_i_1__0_n_5\ : STD_LOGIC;
signal \next_mi_addr_reg[7]_i_1__0_n_6\ : STD_LOGIC;
signal \next_mi_addr_reg[7]_i_1__0_n_7\ : STD_LOGIC;
signal \num_transactions_q_reg_n_0_[0]\ : STD_LOGIC;
signal \num_transactions_q_reg_n_0_[1]\ : STD_LOGIC;
signal \num_transactions_q_reg_n_0_[2]\ : STD_LOGIC;
signal \num_transactions_q_reg_n_0_[3]\ : STD_LOGIC;
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \pushed_commands[3]_i_1__0_n_0\ : STD_LOGIC;
signal \pushed_commands_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal pushed_new_cmd : STD_LOGIC;
signal \queue_id[0]_i_1_n_0\ : STD_LOGIC;
signal \queue_id[1]_i_1_n_0\ : STD_LOGIC;
signal \queue_id_reg_n_0_[0]\ : STD_LOGIC;
signal \queue_id_reg_n_0_[1]\ : STD_LOGIC;
signal rd_cmd_ready : STD_LOGIC;
signal size_mask_q : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \size_mask_q[0]_i_1__0_n_0\ : STD_LOGIC;
signal \size_mask_q[1]_i_1__0_n_0\ : STD_LOGIC;
signal \size_mask_q[2]_i_1__0_n_0\ : STD_LOGIC;
signal \size_mask_q[3]_i_1__0_n_0\ : STD_LOGIC;
signal \size_mask_q[4]_i_1__0_n_0\ : STD_LOGIC;
signal \size_mask_q[5]_i_1__0_n_0\ : STD_LOGIC;
signal \size_mask_q[6]_i_1__0_n_0\ : STD_LOGIC;
signal split_in_progress_reg_n_0 : STD_LOGIC;
signal split_ongoing : STD_LOGIC;
signal \NLW_next_mi_addr_reg[31]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \addr_step_q[10]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \addr_step_q[11]_i_1__0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \addr_step_q[5]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \addr_step_q[6]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \addr_step_q[7]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \addr_step_q[8]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \addr_step_q[9]_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of cmd_empty_i_1 : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \first_step_q[0]_i_1__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \first_step_q[10]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \first_step_q[11]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \first_step_q[1]_i_1__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \first_step_q[3]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \first_step_q[4]_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \first_step_q[6]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \first_step_q[7]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \first_step_q[8]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \first_step_q[9]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_axi_araddr[26]_INST_0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \multiple_id_non_split_i_2__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of multiple_id_non_split_i_3 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \next_mi_addr[11]_i_6__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \next_mi_addr[3]_i_6__0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \pushed_commands[1]_i_1__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \pushed_commands[2]_i_1__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \pushed_commands[3]_i_2__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \queue_id[0]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \size_mask_q[0]_i_1__0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \size_mask_q[1]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \size_mask_q[2]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \size_mask_q[3]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \size_mask_q[4]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \size_mask_q[5]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \size_mask_q[6]_i_1__0\ : label is "soft_lutpair16";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
m_axi_araddr(31 downto 0) <= \^m_axi_araddr\(31 downto 0);
\S_AXI_AADDR_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(0),
Q => \S_AXI_AADDR_Q_reg_n_0_[0]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(10),
Q => \S_AXI_AADDR_Q_reg_n_0_[10]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(11),
Q => \S_AXI_AADDR_Q_reg_n_0_[11]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(12),
Q => \S_AXI_AADDR_Q_reg_n_0_[12]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(13),
Q => \S_AXI_AADDR_Q_reg_n_0_[13]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(14),
Q => \S_AXI_AADDR_Q_reg_n_0_[14]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(15),
Q => \S_AXI_AADDR_Q_reg_n_0_[15]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(16),
Q => \S_AXI_AADDR_Q_reg_n_0_[16]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(17),
Q => \S_AXI_AADDR_Q_reg_n_0_[17]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(18),
Q => \S_AXI_AADDR_Q_reg_n_0_[18]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(19),
Q => \S_AXI_AADDR_Q_reg_n_0_[19]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(1),
Q => \S_AXI_AADDR_Q_reg_n_0_[1]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(20),
Q => \S_AXI_AADDR_Q_reg_n_0_[20]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(21),
Q => \S_AXI_AADDR_Q_reg_n_0_[21]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(22),
Q => \S_AXI_AADDR_Q_reg_n_0_[22]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(23),
Q => \S_AXI_AADDR_Q_reg_n_0_[23]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(24),
Q => \S_AXI_AADDR_Q_reg_n_0_[24]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(25),
Q => \S_AXI_AADDR_Q_reg_n_0_[25]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(26),
Q => \S_AXI_AADDR_Q_reg_n_0_[26]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(27),
Q => \S_AXI_AADDR_Q_reg_n_0_[27]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(28),
Q => \S_AXI_AADDR_Q_reg_n_0_[28]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(29),
Q => \S_AXI_AADDR_Q_reg_n_0_[29]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(2),
Q => \S_AXI_AADDR_Q_reg_n_0_[2]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(30),
Q => \S_AXI_AADDR_Q_reg_n_0_[30]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(31),
Q => \S_AXI_AADDR_Q_reg_n_0_[31]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(3),
Q => \S_AXI_AADDR_Q_reg_n_0_[3]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(4),
Q => \S_AXI_AADDR_Q_reg_n_0_[4]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(5),
Q => \S_AXI_AADDR_Q_reg_n_0_[5]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(6),
Q => \S_AXI_AADDR_Q_reg_n_0_[6]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(7),
Q => \S_AXI_AADDR_Q_reg_n_0_[7]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(8),
Q => \S_AXI_AADDR_Q_reg_n_0_[8]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(9),
Q => \S_AXI_AADDR_Q_reg_n_0_[9]\,
R => SR(0)
);
\S_AXI_ABURST_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arburst(0),
Q => m_axi_arburst(0),
R => SR(0)
);
\S_AXI_ABURST_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arburst(1),
Q => m_axi_arburst(1),
R => SR(0)
);
\S_AXI_ACACHE_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arcache(0),
Q => m_axi_arcache(0),
R => SR(0)
);
\S_AXI_ACACHE_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arcache(1),
Q => m_axi_arcache(1),
R => SR(0)
);
\S_AXI_ACACHE_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arcache(2),
Q => m_axi_arcache(2),
R => SR(0)
);
\S_AXI_ACACHE_Q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arcache(3),
Q => m_axi_arcache(3),
R => SR(0)
);
\S_AXI_AID_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arid(0),
Q => \^q\(0),
R => SR(0)
);
\S_AXI_AID_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arid(1),
Q => \^q\(1),
R => SR(0)
);
\S_AXI_ALEN_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arlen(0),
Q => S_AXI_ALEN_Q(0),
R => SR(0)
);
\S_AXI_ALEN_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arlen(1),
Q => S_AXI_ALEN_Q(1),
R => SR(0)
);
\S_AXI_ALEN_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arlen(2),
Q => S_AXI_ALEN_Q(2),
R => SR(0)
);
\S_AXI_ALEN_Q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arlen(3),
Q => S_AXI_ALEN_Q(3),
R => SR(0)
);
\S_AXI_ALOCK_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arlock(0),
Q => \S_AXI_ALOCK_Q_reg_n_0_[0]\,
R => SR(0)
);
\S_AXI_APROT_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arprot(0),
Q => m_axi_arprot(0),
R => SR(0)
);
\S_AXI_APROT_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arprot(1),
Q => m_axi_arprot(1),
R => SR(0)
);
\S_AXI_APROT_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arprot(2),
Q => m_axi_arprot(2),
R => SR(0)
);
\S_AXI_AQOS_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arqos(0),
Q => m_axi_arqos(0),
R => SR(0)
);
\S_AXI_AQOS_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arqos(1),
Q => m_axi_arqos(1),
R => SR(0)
);
\S_AXI_AQOS_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arqos(2),
Q => m_axi_arqos(2),
R => SR(0)
);
\S_AXI_AQOS_Q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arqos(3),
Q => m_axi_arqos(3),
R => SR(0)
);
S_AXI_AREADY_I_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \USE_R_CHANNEL.cmd_queue_n_14\,
Q => \^e\(0),
R => SR(0)
);
\S_AXI_ASIZE_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arsize(0),
Q => m_axi_arsize(0),
R => SR(0)
);
\S_AXI_ASIZE_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arsize(1),
Q => m_axi_arsize(1),
R => SR(0)
);
\S_AXI_ASIZE_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arsize(2),
Q => m_axi_arsize(2),
R => SR(0)
);
\USE_R_CHANNEL.cmd_queue\: entity work.\system_auto_pc_1_axi_data_fifo_v2_1_10_axic_fifo__parameterized1\
port map (
D(4) => \USE_R_CHANNEL.cmd_queue_n_3\,
D(3) => \USE_R_CHANNEL.cmd_queue_n_4\,
D(2) => \USE_R_CHANNEL.cmd_queue_n_5\,
D(1) => \USE_R_CHANNEL.cmd_queue_n_6\,
D(0) => \USE_R_CHANNEL.cmd_queue_n_7\,
E(0) => \USE_R_CHANNEL.cmd_queue_n_9\,
Q(5 downto 0) => \cmd_depth_reg__0\(5 downto 0),
SR(0) => SR(0),
\S_AXI_AID_Q_reg[0]\ => multiple_id_non_split_i_3_n_0,
\S_AXI_AID_Q_reg[1]\(1 downto 0) => \^q\(1 downto 0),
S_AXI_AREADY_I_reg => \USE_R_CHANNEL.cmd_queue_n_14\,
S_AXI_AREADY_I_reg_0 => \^e\(0),
access_is_incr_q => access_is_incr_q,
aclk => aclk,
almost_empty => almost_empty,
areset_d(1 downto 0) => areset_d(1 downto 0),
\areset_d_reg[1]\ => \areset_d_reg[1]\,
aresetn => aresetn,
cmd_empty => cmd_empty,
cmd_push => cmd_push,
cmd_push_block => cmd_push_block,
cmd_push_block_reg => \USE_R_CHANNEL.cmd_queue_n_15\,
command_ongoing => command_ongoing,
command_ongoing_reg => \USE_R_CHANNEL.cmd_queue_n_16\,
din(0) => \USE_R_CHANNEL.cmd_queue_n_0\,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
multiple_id_non_split => multiple_id_non_split,
multiple_id_non_split_reg => \USE_R_CHANNEL.cmd_queue_n_18\,
need_to_split_q => need_to_split_q,
\num_transactions_q_reg[0]\ => \num_transactions_q_reg_n_0_[0]\,
\num_transactions_q_reg[1]\ => \num_transactions_q_reg_n_0_[1]\,
\num_transactions_q_reg[2]\ => \num_transactions_q_reg_n_0_[2]\,
\num_transactions_q_reg[3]\ => \num_transactions_q_reg_n_0_[3]\,
\pushed_commands_reg[3]\(3 downto 0) => \pushed_commands_reg__0\(3 downto 0),
pushed_new_cmd => pushed_new_cmd,
\queue_id_reg[0]\ => \queue_id_reg_n_0_[0]\,
\queue_id_reg[1]\ => \queue_id_reg_n_0_[1]\,
rd_cmd_ready => rd_cmd_ready,
s_axi_arvalid => s_axi_arvalid,
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
split_in_progress_reg => \USE_R_CHANNEL.cmd_queue_n_17\,
split_in_progress_reg_0 => split_in_progress_reg_n_0,
split_in_progress_reg_1 => \multiple_id_non_split_i_2__0_n_0\
);
\access_is_incr_q_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_arburst(0),
I1 => s_axi_arburst(1),
O => access_is_incr
);
access_is_incr_q_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => access_is_incr,
Q => access_is_incr_q,
R => SR(0)
);
\addr_step_q[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_arsize(1),
I1 => s_axi_arsize(2),
I2 => s_axi_arsize(0),
O => \addr_step_q[10]_i_1__0_n_0\
);
\addr_step_q[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => s_axi_arsize(1),
I1 => s_axi_arsize(0),
I2 => s_axi_arsize(2),
O => \addr_step_q[11]_i_1__0_n_0\
);
\addr_step_q[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => s_axi_arsize(2),
I1 => s_axi_arsize(0),
I2 => s_axi_arsize(1),
O => \addr_step_q[5]_i_1__0_n_0\
);
\addr_step_q[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => s_axi_arsize(0),
I1 => s_axi_arsize(1),
I2 => s_axi_arsize(2),
O => \addr_step_q[6]_i_1__0_n_0\
);
\addr_step_q[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_arsize(1),
I1 => s_axi_arsize(0),
I2 => s_axi_arsize(2),
O => \addr_step_q[7]_i_1__0_n_0\
);
\addr_step_q[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => s_axi_arsize(0),
I1 => s_axi_arsize(2),
I2 => s_axi_arsize(1),
O => \addr_step_q[8]_i_1__0_n_0\
);
\addr_step_q[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_arsize(2),
I1 => s_axi_arsize(0),
I2 => s_axi_arsize(1),
O => \addr_step_q[9]_i_1__0_n_0\
);
\addr_step_q_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \addr_step_q[10]_i_1__0_n_0\,
Q => \addr_step_q_reg_n_0_[10]\,
R => SR(0)
);
\addr_step_q_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \addr_step_q[11]_i_1__0_n_0\,
Q => \addr_step_q_reg_n_0_[11]\,
R => SR(0)
);
\addr_step_q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \addr_step_q[5]_i_1__0_n_0\,
Q => \addr_step_q_reg_n_0_[5]\,
R => SR(0)
);
\addr_step_q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \addr_step_q[6]_i_1__0_n_0\,
Q => \addr_step_q_reg_n_0_[6]\,
R => SR(0)
);
\addr_step_q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \addr_step_q[7]_i_1__0_n_0\,
Q => \addr_step_q_reg_n_0_[7]\,
R => SR(0)
);
\addr_step_q_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \addr_step_q[8]_i_1__0_n_0\,
Q => \addr_step_q_reg_n_0_[8]\,
R => SR(0)
);
\addr_step_q_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \addr_step_q[9]_i_1__0_n_0\,
Q => \addr_step_q_reg_n_0_[9]\,
R => SR(0)
);
\cmd_depth[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cmd_depth_reg__0\(0),
O => \cmd_depth[0]_i_1__0_n_0\
);
\cmd_depth_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_R_CHANNEL.cmd_queue_n_9\,
D => \cmd_depth[0]_i_1__0_n_0\,
Q => \cmd_depth_reg__0\(0),
R => SR(0)
);
\cmd_depth_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_R_CHANNEL.cmd_queue_n_9\,
D => \USE_R_CHANNEL.cmd_queue_n_7\,
Q => \cmd_depth_reg__0\(1),
R => SR(0)
);
\cmd_depth_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_R_CHANNEL.cmd_queue_n_9\,
D => \USE_R_CHANNEL.cmd_queue_n_6\,
Q => \cmd_depth_reg__0\(2),
R => SR(0)
);
\cmd_depth_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_R_CHANNEL.cmd_queue_n_9\,
D => \USE_R_CHANNEL.cmd_queue_n_5\,
Q => \cmd_depth_reg__0\(3),
R => SR(0)
);
\cmd_depth_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_R_CHANNEL.cmd_queue_n_9\,
D => \USE_R_CHANNEL.cmd_queue_n_4\,
Q => \cmd_depth_reg__0\(4),
R => SR(0)
);
\cmd_depth_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_R_CHANNEL.cmd_queue_n_9\,
D => \USE_R_CHANNEL.cmd_queue_n_3\,
Q => \cmd_depth_reg__0\(5),
R => SR(0)
);
cmd_empty_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"E320"
)
port map (
I0 => almost_empty,
I1 => cmd_push,
I2 => rd_cmd_ready,
I3 => cmd_empty,
O => cmd_empty_i_1_n_0
);
\cmd_empty_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => \cmd_depth_reg__0\(2),
I1 => \cmd_depth_reg__0\(3),
I2 => \cmd_depth_reg__0\(5),
I3 => \cmd_depth_reg__0\(4),
I4 => \cmd_depth_reg__0\(1),
I5 => \cmd_depth_reg__0\(0),
O => almost_empty
);
cmd_empty_reg: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => cmd_empty_i_1_n_0,
Q => cmd_empty,
S => SR(0)
);
cmd_push_block_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \USE_R_CHANNEL.cmd_queue_n_15\,
Q => cmd_push_block,
R => '0'
);
command_ongoing_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \USE_R_CHANNEL.cmd_queue_n_16\,
Q => command_ongoing,
R => SR(0)
);
\first_step_q[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => s_axi_arsize(1),
I1 => s_axi_arsize(0),
I2 => s_axi_arlen(0),
I3 => s_axi_arsize(2),
O => \first_step_q[0]_i_1__0_n_0\
);
\first_step_q[10]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_arsize(2),
I1 => \first_step_q[10]_i_2__0_n_0\,
O => first_step(10)
);
\first_step_q[10]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2AAA800080000000"
)
port map (
I0 => s_axi_arsize(1),
I1 => s_axi_arlen(2),
I2 => s_axi_arlen(0),
I3 => s_axi_arlen(1),
I4 => s_axi_arlen(3),
I5 => s_axi_arsize(0),
O => \first_step_q[10]_i_2__0_n_0\
);
\first_step_q[11]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_arsize(2),
I1 => \first_step_q[11]_i_2__0_n_0\,
O => first_step(11)
);
\first_step_q[11]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => s_axi_arsize(1),
I1 => s_axi_arlen(3),
I2 => s_axi_arlen(1),
I3 => s_axi_arlen(0),
I4 => s_axi_arlen(2),
I5 => s_axi_arsize(0),
O => \first_step_q[11]_i_2__0_n_0\
);
\first_step_q[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000514"
)
port map (
I0 => s_axi_arsize(1),
I1 => s_axi_arsize(0),
I2 => s_axi_arlen(0),
I3 => s_axi_arlen(1),
I4 => s_axi_arsize(2),
O => \first_step_q[1]_i_1__0_n_0\
);
\first_step_q[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000F3C6A"
)
port map (
I0 => s_axi_arlen(2),
I1 => s_axi_arlen(1),
I2 => s_axi_arlen(0),
I3 => s_axi_arsize(0),
I4 => s_axi_arsize(1),
I5 => s_axi_arsize(2),
O => \first_step_q[2]_i_1__0_n_0\
);
\first_step_q[3]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \first_step_q[7]_i_2__0_n_0\,
I1 => s_axi_arsize(2),
O => \first_step_q[3]_i_1__0_n_0\
);
\first_step_q[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0100"
)
port map (
I0 => s_axi_arlen(0),
I1 => s_axi_arsize(0),
I2 => s_axi_arsize(1),
I3 => s_axi_arsize(2),
I4 => \first_step_q[8]_i_2__0_n_0\,
O => first_step(4)
);
\first_step_q[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0036FFFF00360000"
)
port map (
I0 => s_axi_arlen(1),
I1 => s_axi_arlen(0),
I2 => s_axi_arsize(0),
I3 => s_axi_arsize(1),
I4 => s_axi_arsize(2),
I5 => \first_step_q[9]_i_2__0_n_0\,
O => first_step(5)
);
\first_step_q[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \first_step_q[6]_i_2__0_n_0\,
I1 => s_axi_arsize(2),
I2 => \first_step_q[10]_i_2__0_n_0\,
O => first_step(6)
);
\first_step_q[6]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"07531642"
)
port map (
I0 => s_axi_arsize(1),
I1 => s_axi_arsize(0),
I2 => s_axi_arlen(0),
I3 => s_axi_arlen(1),
I4 => s_axi_arlen(2),
O => \first_step_q[6]_i_2__0_n_0\
);
\first_step_q[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \first_step_q[7]_i_2__0_n_0\,
I1 => s_axi_arsize(2),
I2 => \first_step_q[11]_i_2__0_n_0\,
O => first_step(7)
);
\first_step_q[7]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"07FD53B916EC42A8"
)
port map (
I0 => s_axi_arsize(1),
I1 => s_axi_arsize(0),
I2 => s_axi_arlen(1),
I3 => s_axi_arlen(0),
I4 => s_axi_arlen(2),
I5 => s_axi_arlen(3),
O => \first_step_q[7]_i_2__0_n_0\
);
\first_step_q[8]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_arsize(2),
I1 => \first_step_q[8]_i_2__0_n_0\,
O => first_step(8)
);
\first_step_q[8]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"14EAEA6262C8C840"
)
port map (
I0 => s_axi_arsize(1),
I1 => s_axi_arsize(0),
I2 => s_axi_arlen(3),
I3 => s_axi_arlen(1),
I4 => s_axi_arlen(0),
I5 => s_axi_arlen(2),
O => \first_step_q[8]_i_2__0_n_0\
);
\first_step_q[9]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_arsize(2),
I1 => \first_step_q[9]_i_2__0_n_0\,
O => first_step(9)
);
\first_step_q[9]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4AA2A2A228808080"
)
port map (
I0 => s_axi_arsize(1),
I1 => s_axi_arsize(0),
I2 => s_axi_arlen(2),
I3 => s_axi_arlen(0),
I4 => s_axi_arlen(1),
I5 => s_axi_arlen(3),
O => \first_step_q[9]_i_2__0_n_0\
);
\first_step_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \first_step_q[0]_i_1__0_n_0\,
Q => \first_step_q_reg_n_0_[0]\,
R => SR(0)
);
\first_step_q_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => first_step(10),
Q => \first_step_q_reg_n_0_[10]\,
R => SR(0)
);
\first_step_q_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => first_step(11),
Q => \first_step_q_reg_n_0_[11]\,
R => SR(0)
);
\first_step_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \first_step_q[1]_i_1__0_n_0\,
Q => \first_step_q_reg_n_0_[1]\,
R => SR(0)
);
\first_step_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \first_step_q[2]_i_1__0_n_0\,
Q => \first_step_q_reg_n_0_[2]\,
R => SR(0)
);
\first_step_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \first_step_q[3]_i_1__0_n_0\,
Q => \first_step_q_reg_n_0_[3]\,
R => SR(0)
);
\first_step_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => first_step(4),
Q => \first_step_q_reg_n_0_[4]\,
R => SR(0)
);
\first_step_q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => first_step(5),
Q => \first_step_q_reg_n_0_[5]\,
R => SR(0)
);
\first_step_q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => first_step(6),
Q => \first_step_q_reg_n_0_[6]\,
R => SR(0)
);
\first_step_q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => first_step(7),
Q => \first_step_q_reg_n_0_[7]\,
R => SR(0)
);
\first_step_q_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => first_step(8),
Q => \first_step_q_reg_n_0_[8]\,
R => SR(0)
);
\first_step_q_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => first_step(9),
Q => \first_step_q_reg_n_0_[9]\,
R => SR(0)
);
incr_need_to_split: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444444444440"
)
port map (
I0 => s_axi_arburst(1),
I1 => s_axi_arburst(0),
I2 => s_axi_arlen(5),
I3 => s_axi_arlen(4),
I4 => s_axi_arlen(6),
I5 => s_axi_arlen(7),
O => \incr_need_to_split__0\
);
incr_need_to_split_q_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \incr_need_to_split__0\,
Q => need_to_split_q,
R => SR(0)
);
\m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FFF8000"
)
port map (
I0 => size_mask_q(0),
I1 => next_mi_addr(0),
I2 => access_is_incr_q,
I3 => split_ongoing,
I4 => \S_AXI_AADDR_Q_reg_n_0_[0]\,
O => \^m_axi_araddr\(0)
);
\m_axi_araddr[10]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[10]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(10),
O => \^m_axi_araddr\(10)
);
\m_axi_araddr[11]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[11]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(11),
O => \^m_axi_araddr\(11)
);
\m_axi_araddr[12]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[12]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(12),
O => \^m_axi_araddr\(12)
);
\m_axi_araddr[13]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[13]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(13),
O => \^m_axi_araddr\(13)
);
\m_axi_araddr[14]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[14]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(14),
O => \^m_axi_araddr\(14)
);
\m_axi_araddr[15]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[15]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(15),
O => \^m_axi_araddr\(15)
);
\m_axi_araddr[16]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[16]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(16),
O => \^m_axi_araddr\(16)
);
\m_axi_araddr[17]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[17]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(17),
O => \^m_axi_araddr\(17)
);
\m_axi_araddr[18]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[18]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(18),
O => \^m_axi_araddr\(18)
);
\m_axi_araddr[19]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[19]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(19),
O => \^m_axi_araddr\(19)
);
\m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FFF8000"
)
port map (
I0 => size_mask_q(1),
I1 => next_mi_addr(1),
I2 => access_is_incr_q,
I3 => split_ongoing,
I4 => \S_AXI_AADDR_Q_reg_n_0_[1]\,
O => \^m_axi_araddr\(1)
);
\m_axi_araddr[20]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[20]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(20),
O => \^m_axi_araddr\(20)
);
\m_axi_araddr[21]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[21]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(21),
O => \^m_axi_araddr\(21)
);
\m_axi_araddr[22]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[22]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(22),
O => \^m_axi_araddr\(22)
);
\m_axi_araddr[23]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[23]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(23),
O => \^m_axi_araddr\(23)
);
\m_axi_araddr[24]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[24]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(24),
O => \^m_axi_araddr\(24)
);
\m_axi_araddr[25]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[25]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(25),
O => \^m_axi_araddr\(25)
);
\m_axi_araddr[26]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[26]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(26),
O => \^m_axi_araddr\(26)
);
\m_axi_araddr[27]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[27]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(27),
O => \^m_axi_araddr\(27)
);
\m_axi_araddr[28]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[28]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(28),
O => \^m_axi_araddr\(28)
);
\m_axi_araddr[29]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[29]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(29),
O => \^m_axi_araddr\(29)
);
\m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FFF8000"
)
port map (
I0 => size_mask_q(2),
I1 => next_mi_addr(2),
I2 => access_is_incr_q,
I3 => split_ongoing,
I4 => \S_AXI_AADDR_Q_reg_n_0_[2]\,
O => \^m_axi_araddr\(2)
);
\m_axi_araddr[30]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[30]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(30),
O => \^m_axi_araddr\(30)
);
\m_axi_araddr[31]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[31]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(31),
O => \^m_axi_araddr\(31)
);
\m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FFF8000"
)
port map (
I0 => size_mask_q(3),
I1 => next_mi_addr(3),
I2 => access_is_incr_q,
I3 => split_ongoing,
I4 => \S_AXI_AADDR_Q_reg_n_0_[3]\,
O => \^m_axi_araddr\(3)
);
\m_axi_araddr[4]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FFF8000"
)
port map (
I0 => size_mask_q(4),
I1 => next_mi_addr(4),
I2 => access_is_incr_q,
I3 => split_ongoing,
I4 => \S_AXI_AADDR_Q_reg_n_0_[4]\,
O => \^m_axi_araddr\(4)
);
\m_axi_araddr[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FFF8000"
)
port map (
I0 => size_mask_q(5),
I1 => next_mi_addr(5),
I2 => access_is_incr_q,
I3 => split_ongoing,
I4 => \S_AXI_AADDR_Q_reg_n_0_[5]\,
O => \^m_axi_araddr\(5)
);
\m_axi_araddr[6]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FFF8000"
)
port map (
I0 => size_mask_q(6),
I1 => next_mi_addr(6),
I2 => access_is_incr_q,
I3 => split_ongoing,
I4 => \S_AXI_AADDR_Q_reg_n_0_[6]\,
O => \^m_axi_araddr\(6)
);
\m_axi_araddr[7]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[7]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(7),
O => \^m_axi_araddr\(7)
);
\m_axi_araddr[8]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[8]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(8),
O => \^m_axi_araddr\(8)
);
\m_axi_araddr[9]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[9]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(9),
O => \^m_axi_araddr\(9)
);
\m_axi_arlen[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFEAAAAAAAA"
)
port map (
I0 => S_AXI_ALEN_Q(0),
I1 => \pushed_commands_reg__0\(1),
I2 => \pushed_commands_reg__0\(0),
I3 => \pushed_commands_reg__0\(3),
I4 => \pushed_commands_reg__0\(2),
I5 => need_to_split_q,
O => m_axi_arlen(0)
);
\m_axi_arlen[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFEAAAAAAAA"
)
port map (
I0 => S_AXI_ALEN_Q(1),
I1 => \pushed_commands_reg__0\(1),
I2 => \pushed_commands_reg__0\(0),
I3 => \pushed_commands_reg__0\(3),
I4 => \pushed_commands_reg__0\(2),
I5 => need_to_split_q,
O => m_axi_arlen(1)
);
\m_axi_arlen[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFEAAAAAAAA"
)
port map (
I0 => S_AXI_ALEN_Q(2),
I1 => \pushed_commands_reg__0\(1),
I2 => \pushed_commands_reg__0\(0),
I3 => \pushed_commands_reg__0\(3),
I4 => \pushed_commands_reg__0\(2),
I5 => need_to_split_q,
O => m_axi_arlen(2)
);
\m_axi_arlen[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFEAAAAAAAA"
)
port map (
I0 => S_AXI_ALEN_Q(3),
I1 => \pushed_commands_reg__0\(1),
I2 => \pushed_commands_reg__0\(0),
I3 => \pushed_commands_reg__0\(3),
I4 => \pushed_commands_reg__0\(2),
I5 => need_to_split_q,
O => m_axi_arlen(3)
);
\m_axi_arlock[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \S_AXI_ALOCK_Q_reg_n_0_[0]\,
I1 => need_to_split_q,
O => m_axi_arlock(0)
);
\multiple_id_non_split_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => split_in_progress_reg_n_0,
I1 => cmd_empty,
O => \multiple_id_non_split_i_2__0_n_0\
);
multiple_id_non_split_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => \queue_id_reg_n_0_[0]\,
I2 => \^q\(1),
I3 => \queue_id_reg_n_0_[1]\,
O => multiple_id_non_split_i_3_n_0
);
multiple_id_non_split_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \USE_R_CHANNEL.cmd_queue_n_18\,
Q => multiple_id_non_split,
R => '0'
);
\next_mi_addr[11]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => \^m_axi_araddr\(11),
I1 => \addr_step_q_reg_n_0_[11]\,
I2 => \next_mi_addr[11]_i_6__0_n_0\,
I3 => \first_step_q_reg_n_0_[11]\,
O => \next_mi_addr[11]_i_2_n_0\
);
\next_mi_addr[11]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => \^m_axi_araddr\(10),
I1 => \addr_step_q_reg_n_0_[10]\,
I2 => \next_mi_addr[11]_i_6__0_n_0\,
I3 => \first_step_q_reg_n_0_[10]\,
O => \next_mi_addr[11]_i_3_n_0\
);
\next_mi_addr[11]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => \^m_axi_araddr\(9),
I1 => \addr_step_q_reg_n_0_[9]\,
I2 => \next_mi_addr[11]_i_6__0_n_0\,
I3 => \first_step_q_reg_n_0_[9]\,
O => \next_mi_addr[11]_i_4_n_0\
);
\next_mi_addr[11]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => \^m_axi_araddr\(8),
I1 => \addr_step_q_reg_n_0_[8]\,
I2 => \next_mi_addr[11]_i_6__0_n_0\,
I3 => \first_step_q_reg_n_0_[8]\,
O => \next_mi_addr[11]_i_5_n_0\
);
\next_mi_addr[11]_i_6__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \pushed_commands_reg__0\(1),
I1 => \pushed_commands_reg__0\(0),
I2 => \pushed_commands_reg__0\(3),
I3 => \pushed_commands_reg__0\(2),
O => \next_mi_addr[11]_i_6__0_n_0\
);
\next_mi_addr[15]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[15]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(15),
O => \next_mi_addr[15]_i_2__0_n_0\
);
\next_mi_addr[15]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[14]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(14),
O => \next_mi_addr[15]_i_3__0_n_0\
);
\next_mi_addr[15]_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[13]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(13),
O => \next_mi_addr[15]_i_4__0_n_0\
);
\next_mi_addr[15]_i_5__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[12]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(12),
O => \next_mi_addr[15]_i_5__0_n_0\
);
\next_mi_addr[15]_i_6__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[15]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(15),
O => \next_mi_addr[15]_i_6__0_n_0\
);
\next_mi_addr[15]_i_7__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[14]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(14),
O => \next_mi_addr[15]_i_7__0_n_0\
);
\next_mi_addr[15]_i_8__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[13]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(13),
O => \next_mi_addr[15]_i_8__0_n_0\
);
\next_mi_addr[15]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[12]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(12),
O => \next_mi_addr[15]_i_9__0_n_0\
);
\next_mi_addr[19]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[19]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(19),
O => \next_mi_addr[19]_i_2__0_n_0\
);
\next_mi_addr[19]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[18]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(18),
O => \next_mi_addr[19]_i_3__0_n_0\
);
\next_mi_addr[19]_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[17]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(17),
O => \next_mi_addr[19]_i_4__0_n_0\
);
\next_mi_addr[19]_i_5__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[16]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(16),
O => \next_mi_addr[19]_i_5__0_n_0\
);
\next_mi_addr[23]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[23]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(23),
O => \next_mi_addr[23]_i_2__0_n_0\
);
\next_mi_addr[23]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[22]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(22),
O => \next_mi_addr[23]_i_3__0_n_0\
);
\next_mi_addr[23]_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[21]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(21),
O => \next_mi_addr[23]_i_4__0_n_0\
);
\next_mi_addr[23]_i_5__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[20]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(20),
O => \next_mi_addr[23]_i_5__0_n_0\
);
\next_mi_addr[27]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[27]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(27),
O => \next_mi_addr[27]_i_2__0_n_0\
);
\next_mi_addr[27]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[26]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(26),
O => \next_mi_addr[27]_i_3__0_n_0\
);
\next_mi_addr[27]_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[25]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(25),
O => \next_mi_addr[27]_i_4__0_n_0\
);
\next_mi_addr[27]_i_5__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[24]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(24),
O => \next_mi_addr[27]_i_5__0_n_0\
);
\next_mi_addr[31]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[31]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(31),
O => \next_mi_addr[31]_i_2__0_n_0\
);
\next_mi_addr[31]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[30]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(30),
O => \next_mi_addr[31]_i_3__0_n_0\
);
\next_mi_addr[31]_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[29]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(29),
O => \next_mi_addr[31]_i_4__0_n_0\
);
\next_mi_addr[31]_i_5__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[28]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(28),
O => \next_mi_addr[31]_i_5__0_n_0\
);
\next_mi_addr[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"1DDDE222E222E222"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[3]\,
I1 => \next_mi_addr[3]_i_6__0_n_0\,
I2 => next_mi_addr(3),
I3 => size_mask_q(3),
I4 => \next_mi_addr[11]_i_6__0_n_0\,
I5 => \first_step_q_reg_n_0_[3]\,
O => \next_mi_addr[3]_i_2_n_0\
);
\next_mi_addr[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"1DDDE222E222E222"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[2]\,
I1 => \next_mi_addr[3]_i_6__0_n_0\,
I2 => next_mi_addr(2),
I3 => size_mask_q(2),
I4 => \next_mi_addr[11]_i_6__0_n_0\,
I5 => \first_step_q_reg_n_0_[2]\,
O => \next_mi_addr[3]_i_3_n_0\
);
\next_mi_addr[3]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"1DDDE222E222E222"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[1]\,
I1 => \next_mi_addr[3]_i_6__0_n_0\,
I2 => next_mi_addr(1),
I3 => size_mask_q(1),
I4 => \next_mi_addr[11]_i_6__0_n_0\,
I5 => \first_step_q_reg_n_0_[1]\,
O => \next_mi_addr[3]_i_4_n_0\
);
\next_mi_addr[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"1DDDE222E222E222"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[0]\,
I1 => \next_mi_addr[3]_i_6__0_n_0\,
I2 => next_mi_addr(0),
I3 => size_mask_q(0),
I4 => \next_mi_addr[11]_i_6__0_n_0\,
I5 => \first_step_q_reg_n_0_[0]\,
O => \next_mi_addr[3]_i_5_n_0\
);
\next_mi_addr[3]_i_6__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => access_is_incr_q,
I1 => split_ongoing,
O => \next_mi_addr[3]_i_6__0_n_0\
);
\next_mi_addr[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => \^m_axi_araddr\(7),
I1 => \addr_step_q_reg_n_0_[7]\,
I2 => \next_mi_addr[11]_i_6__0_n_0\,
I3 => \first_step_q_reg_n_0_[7]\,
O => \next_mi_addr[7]_i_2_n_0\
);
\next_mi_addr[7]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => \^m_axi_araddr\(6),
I1 => \addr_step_q_reg_n_0_[6]\,
I2 => \next_mi_addr[11]_i_6__0_n_0\,
I3 => \first_step_q_reg_n_0_[6]\,
O => \next_mi_addr[7]_i_3_n_0\
);
\next_mi_addr[7]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => \^m_axi_araddr\(5),
I1 => \addr_step_q_reg_n_0_[5]\,
I2 => \next_mi_addr[11]_i_6__0_n_0\,
I3 => \first_step_q_reg_n_0_[5]\,
O => \next_mi_addr[7]_i_4_n_0\
);
\next_mi_addr[7]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => \^m_axi_araddr\(4),
I1 => size_mask_q(0),
I2 => \next_mi_addr[11]_i_6__0_n_0\,
I3 => \first_step_q_reg_n_0_[4]\,
O => \next_mi_addr[7]_i_5_n_0\
);
\next_mi_addr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[3]_i_1__0_n_7\,
Q => next_mi_addr(0),
R => SR(0)
);
\next_mi_addr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[11]_i_1__0_n_5\,
Q => next_mi_addr(10),
R => SR(0)
);
\next_mi_addr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[11]_i_1__0_n_4\,
Q => next_mi_addr(11),
R => SR(0)
);
\next_mi_addr_reg[11]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => \next_mi_addr_reg[7]_i_1__0_n_0\,
CO(3) => \next_mi_addr_reg[11]_i_1__0_n_0\,
CO(2) => \next_mi_addr_reg[11]_i_1__0_n_1\,
CO(1) => \next_mi_addr_reg[11]_i_1__0_n_2\,
CO(0) => \next_mi_addr_reg[11]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^m_axi_araddr\(11 downto 8),
O(3) => \next_mi_addr_reg[11]_i_1__0_n_4\,
O(2) => \next_mi_addr_reg[11]_i_1__0_n_5\,
O(1) => \next_mi_addr_reg[11]_i_1__0_n_6\,
O(0) => \next_mi_addr_reg[11]_i_1__0_n_7\,
S(3) => \next_mi_addr[11]_i_2_n_0\,
S(2) => \next_mi_addr[11]_i_3_n_0\,
S(1) => \next_mi_addr[11]_i_4_n_0\,
S(0) => \next_mi_addr[11]_i_5_n_0\
);
\next_mi_addr_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[15]_i_1__0_n_7\,
Q => next_mi_addr(12),
R => SR(0)
);
\next_mi_addr_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[15]_i_1__0_n_6\,
Q => next_mi_addr(13),
R => SR(0)
);
\next_mi_addr_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[15]_i_1__0_n_5\,
Q => next_mi_addr(14),
R => SR(0)
);
\next_mi_addr_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[15]_i_1__0_n_4\,
Q => next_mi_addr(15),
R => SR(0)
);
\next_mi_addr_reg[15]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => \next_mi_addr_reg[11]_i_1__0_n_0\,
CO(3) => \next_mi_addr_reg[15]_i_1__0_n_0\,
CO(2) => \next_mi_addr_reg[15]_i_1__0_n_1\,
CO(1) => \next_mi_addr_reg[15]_i_1__0_n_2\,
CO(0) => \next_mi_addr_reg[15]_i_1__0_n_3\,
CYINIT => '0',
DI(3) => \next_mi_addr[15]_i_2__0_n_0\,
DI(2) => \next_mi_addr[15]_i_3__0_n_0\,
DI(1) => \next_mi_addr[15]_i_4__0_n_0\,
DI(0) => \next_mi_addr[15]_i_5__0_n_0\,
O(3) => \next_mi_addr_reg[15]_i_1__0_n_4\,
O(2) => \next_mi_addr_reg[15]_i_1__0_n_5\,
O(1) => \next_mi_addr_reg[15]_i_1__0_n_6\,
O(0) => \next_mi_addr_reg[15]_i_1__0_n_7\,
S(3) => \next_mi_addr[15]_i_6__0_n_0\,
S(2) => \next_mi_addr[15]_i_7__0_n_0\,
S(1) => \next_mi_addr[15]_i_8__0_n_0\,
S(0) => \next_mi_addr[15]_i_9__0_n_0\
);
\next_mi_addr_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[19]_i_1__0_n_7\,
Q => next_mi_addr(16),
R => SR(0)
);
\next_mi_addr_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[19]_i_1__0_n_6\,
Q => next_mi_addr(17),
R => SR(0)
);
\next_mi_addr_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[19]_i_1__0_n_5\,
Q => next_mi_addr(18),
R => SR(0)
);
\next_mi_addr_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[19]_i_1__0_n_4\,
Q => next_mi_addr(19),
R => SR(0)
);
\next_mi_addr_reg[19]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => \next_mi_addr_reg[15]_i_1__0_n_0\,
CO(3) => \next_mi_addr_reg[19]_i_1__0_n_0\,
CO(2) => \next_mi_addr_reg[19]_i_1__0_n_1\,
CO(1) => \next_mi_addr_reg[19]_i_1__0_n_2\,
CO(0) => \next_mi_addr_reg[19]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \next_mi_addr_reg[19]_i_1__0_n_4\,
O(2) => \next_mi_addr_reg[19]_i_1__0_n_5\,
O(1) => \next_mi_addr_reg[19]_i_1__0_n_6\,
O(0) => \next_mi_addr_reg[19]_i_1__0_n_7\,
S(3) => \next_mi_addr[19]_i_2__0_n_0\,
S(2) => \next_mi_addr[19]_i_3__0_n_0\,
S(1) => \next_mi_addr[19]_i_4__0_n_0\,
S(0) => \next_mi_addr[19]_i_5__0_n_0\
);
\next_mi_addr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[3]_i_1__0_n_6\,
Q => next_mi_addr(1),
R => SR(0)
);
\next_mi_addr_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[23]_i_1__0_n_7\,
Q => next_mi_addr(20),
R => SR(0)
);
\next_mi_addr_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[23]_i_1__0_n_6\,
Q => next_mi_addr(21),
R => SR(0)
);
\next_mi_addr_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[23]_i_1__0_n_5\,
Q => next_mi_addr(22),
R => SR(0)
);
\next_mi_addr_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[23]_i_1__0_n_4\,
Q => next_mi_addr(23),
R => SR(0)
);
\next_mi_addr_reg[23]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => \next_mi_addr_reg[19]_i_1__0_n_0\,
CO(3) => \next_mi_addr_reg[23]_i_1__0_n_0\,
CO(2) => \next_mi_addr_reg[23]_i_1__0_n_1\,
CO(1) => \next_mi_addr_reg[23]_i_1__0_n_2\,
CO(0) => \next_mi_addr_reg[23]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \next_mi_addr_reg[23]_i_1__0_n_4\,
O(2) => \next_mi_addr_reg[23]_i_1__0_n_5\,
O(1) => \next_mi_addr_reg[23]_i_1__0_n_6\,
O(0) => \next_mi_addr_reg[23]_i_1__0_n_7\,
S(3) => \next_mi_addr[23]_i_2__0_n_0\,
S(2) => \next_mi_addr[23]_i_3__0_n_0\,
S(1) => \next_mi_addr[23]_i_4__0_n_0\,
S(0) => \next_mi_addr[23]_i_5__0_n_0\
);
\next_mi_addr_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[27]_i_1__0_n_7\,
Q => next_mi_addr(24),
R => SR(0)
);
\next_mi_addr_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[27]_i_1__0_n_6\,
Q => next_mi_addr(25),
R => SR(0)
);
\next_mi_addr_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[27]_i_1__0_n_5\,
Q => next_mi_addr(26),
R => SR(0)
);
\next_mi_addr_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[27]_i_1__0_n_4\,
Q => next_mi_addr(27),
R => SR(0)
);
\next_mi_addr_reg[27]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => \next_mi_addr_reg[23]_i_1__0_n_0\,
CO(3) => \next_mi_addr_reg[27]_i_1__0_n_0\,
CO(2) => \next_mi_addr_reg[27]_i_1__0_n_1\,
CO(1) => \next_mi_addr_reg[27]_i_1__0_n_2\,
CO(0) => \next_mi_addr_reg[27]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \next_mi_addr_reg[27]_i_1__0_n_4\,
O(2) => \next_mi_addr_reg[27]_i_1__0_n_5\,
O(1) => \next_mi_addr_reg[27]_i_1__0_n_6\,
O(0) => \next_mi_addr_reg[27]_i_1__0_n_7\,
S(3) => \next_mi_addr[27]_i_2__0_n_0\,
S(2) => \next_mi_addr[27]_i_3__0_n_0\,
S(1) => \next_mi_addr[27]_i_4__0_n_0\,
S(0) => \next_mi_addr[27]_i_5__0_n_0\
);
\next_mi_addr_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[31]_i_1__0_n_7\,
Q => next_mi_addr(28),
R => SR(0)
);
\next_mi_addr_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[31]_i_1__0_n_6\,
Q => next_mi_addr(29),
R => SR(0)
);
\next_mi_addr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[3]_i_1__0_n_5\,
Q => next_mi_addr(2),
R => SR(0)
);
\next_mi_addr_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[31]_i_1__0_n_5\,
Q => next_mi_addr(30),
R => SR(0)
);
\next_mi_addr_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[31]_i_1__0_n_4\,
Q => next_mi_addr(31),
R => SR(0)
);
\next_mi_addr_reg[31]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => \next_mi_addr_reg[27]_i_1__0_n_0\,
CO(3) => \NLW_next_mi_addr_reg[31]_i_1__0_CO_UNCONNECTED\(3),
CO(2) => \next_mi_addr_reg[31]_i_1__0_n_1\,
CO(1) => \next_mi_addr_reg[31]_i_1__0_n_2\,
CO(0) => \next_mi_addr_reg[31]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \next_mi_addr_reg[31]_i_1__0_n_4\,
O(2) => \next_mi_addr_reg[31]_i_1__0_n_5\,
O(1) => \next_mi_addr_reg[31]_i_1__0_n_6\,
O(0) => \next_mi_addr_reg[31]_i_1__0_n_7\,
S(3) => \next_mi_addr[31]_i_2__0_n_0\,
S(2) => \next_mi_addr[31]_i_3__0_n_0\,
S(1) => \next_mi_addr[31]_i_4__0_n_0\,
S(0) => \next_mi_addr[31]_i_5__0_n_0\
);
\next_mi_addr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[3]_i_1__0_n_4\,
Q => next_mi_addr(3),
R => SR(0)
);
\next_mi_addr_reg[3]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \next_mi_addr_reg[3]_i_1__0_n_0\,
CO(2) => \next_mi_addr_reg[3]_i_1__0_n_1\,
CO(1) => \next_mi_addr_reg[3]_i_1__0_n_2\,
CO(0) => \next_mi_addr_reg[3]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^m_axi_araddr\(3 downto 0),
O(3) => \next_mi_addr_reg[3]_i_1__0_n_4\,
O(2) => \next_mi_addr_reg[3]_i_1__0_n_5\,
O(1) => \next_mi_addr_reg[3]_i_1__0_n_6\,
O(0) => \next_mi_addr_reg[3]_i_1__0_n_7\,
S(3) => \next_mi_addr[3]_i_2_n_0\,
S(2) => \next_mi_addr[3]_i_3_n_0\,
S(1) => \next_mi_addr[3]_i_4_n_0\,
S(0) => \next_mi_addr[3]_i_5_n_0\
);
\next_mi_addr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[7]_i_1__0_n_7\,
Q => next_mi_addr(4),
R => SR(0)
);
\next_mi_addr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[7]_i_1__0_n_6\,
Q => next_mi_addr(5),
R => SR(0)
);
\next_mi_addr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[7]_i_1__0_n_5\,
Q => next_mi_addr(6),
R => SR(0)
);
\next_mi_addr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[7]_i_1__0_n_4\,
Q => next_mi_addr(7),
R => SR(0)
);
\next_mi_addr_reg[7]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => \next_mi_addr_reg[3]_i_1__0_n_0\,
CO(3) => \next_mi_addr_reg[7]_i_1__0_n_0\,
CO(2) => \next_mi_addr_reg[7]_i_1__0_n_1\,
CO(1) => \next_mi_addr_reg[7]_i_1__0_n_2\,
CO(0) => \next_mi_addr_reg[7]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^m_axi_araddr\(7 downto 4),
O(3) => \next_mi_addr_reg[7]_i_1__0_n_4\,
O(2) => \next_mi_addr_reg[7]_i_1__0_n_5\,
O(1) => \next_mi_addr_reg[7]_i_1__0_n_6\,
O(0) => \next_mi_addr_reg[7]_i_1__0_n_7\,
S(3) => \next_mi_addr[7]_i_2_n_0\,
S(2) => \next_mi_addr[7]_i_3_n_0\,
S(1) => \next_mi_addr[7]_i_4_n_0\,
S(0) => \next_mi_addr[7]_i_5_n_0\
);
\next_mi_addr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[11]_i_1__0_n_7\,
Q => next_mi_addr(8),
R => SR(0)
);
\next_mi_addr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[11]_i_1__0_n_6\,
Q => next_mi_addr(9),
R => SR(0)
);
\num_transactions_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arlen(4),
Q => \num_transactions_q_reg_n_0_[0]\,
R => SR(0)
);
\num_transactions_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arlen(5),
Q => \num_transactions_q_reg_n_0_[1]\,
R => SR(0)
);
\num_transactions_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arlen(6),
Q => \num_transactions_q_reg_n_0_[2]\,
R => SR(0)
);
\num_transactions_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arlen(7),
Q => \num_transactions_q_reg_n_0_[3]\,
R => SR(0)
);
\pushed_commands[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \pushed_commands_reg__0\(0),
O => \p_0_in__0\(0)
);
\pushed_commands[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \pushed_commands_reg__0\(0),
I1 => \pushed_commands_reg__0\(1),
O => \p_0_in__0\(1)
);
\pushed_commands[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \pushed_commands_reg__0\(2),
I1 => \pushed_commands_reg__0\(1),
I2 => \pushed_commands_reg__0\(0),
O => \p_0_in__0\(2)
);
\pushed_commands[3]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^e\(0),
I1 => aresetn,
O => \pushed_commands[3]_i_1__0_n_0\
);
\pushed_commands[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \pushed_commands_reg__0\(3),
I1 => \pushed_commands_reg__0\(0),
I2 => \pushed_commands_reg__0\(1),
I3 => \pushed_commands_reg__0\(2),
O => \p_0_in__0\(3)
);
\pushed_commands_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \p_0_in__0\(0),
Q => \pushed_commands_reg__0\(0),
R => \pushed_commands[3]_i_1__0_n_0\
);
\pushed_commands_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \p_0_in__0\(1),
Q => \pushed_commands_reg__0\(1),
R => \pushed_commands[3]_i_1__0_n_0\
);
\pushed_commands_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \p_0_in__0\(2),
Q => \pushed_commands_reg__0\(2),
R => \pushed_commands[3]_i_1__0_n_0\
);
\pushed_commands_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \p_0_in__0\(3),
Q => \pushed_commands_reg__0\(3),
R => \pushed_commands[3]_i_1__0_n_0\
);
\queue_id[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(0),
I1 => cmd_push,
I2 => \queue_id_reg_n_0_[0]\,
O => \queue_id[0]_i_1_n_0\
);
\queue_id[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(1),
I1 => cmd_push,
I2 => \queue_id_reg_n_0_[1]\,
O => \queue_id[1]_i_1_n_0\
);
\queue_id_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \queue_id[0]_i_1_n_0\,
Q => \queue_id_reg_n_0_[0]\,
R => SR(0)
);
\queue_id_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \queue_id[1]_i_1_n_0\,
Q => \queue_id_reg_n_0_[1]\,
R => SR(0)
);
\size_mask_q[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => s_axi_arsize(2),
I1 => s_axi_arsize(0),
I2 => s_axi_arsize(1),
O => \size_mask_q[0]_i_1__0_n_0\
);
\size_mask_q[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_arsize(2),
I1 => s_axi_arsize(1),
O => \size_mask_q[1]_i_1__0_n_0\
);
\size_mask_q[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"07"
)
port map (
I0 => s_axi_arsize(0),
I1 => s_axi_arsize(1),
I2 => s_axi_arsize(2),
O => \size_mask_q[2]_i_1__0_n_0\
);
\size_mask_q[3]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_arsize(2),
O => \size_mask_q[3]_i_1__0_n_0\
);
\size_mask_q[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"57"
)
port map (
I0 => s_axi_arsize(2),
I1 => s_axi_arsize(0),
I2 => s_axi_arsize(1),
O => \size_mask_q[4]_i_1__0_n_0\
);
\size_mask_q[5]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => s_axi_arsize(2),
I1 => s_axi_arsize(1),
O => \size_mask_q[5]_i_1__0_n_0\
);
\size_mask_q[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => s_axi_arsize(2),
I1 => s_axi_arsize(0),
I2 => s_axi_arsize(1),
O => \size_mask_q[6]_i_1__0_n_0\
);
\size_mask_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \size_mask_q[0]_i_1__0_n_0\,
Q => size_mask_q(0),
R => SR(0)
);
\size_mask_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \size_mask_q[1]_i_1__0_n_0\,
Q => size_mask_q(1),
R => SR(0)
);
\size_mask_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \size_mask_q[2]_i_1__0_n_0\,
Q => size_mask_q(2),
R => SR(0)
);
\size_mask_q_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => '1',
Q => size_mask_q(31),
R => SR(0)
);
\size_mask_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \size_mask_q[3]_i_1__0_n_0\,
Q => size_mask_q(3),
R => SR(0)
);
\size_mask_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \size_mask_q[4]_i_1__0_n_0\,
Q => size_mask_q(4),
R => SR(0)
);
\size_mask_q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \size_mask_q[5]_i_1__0_n_0\,
Q => size_mask_q(5),
R => SR(0)
);
\size_mask_q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \size_mask_q[6]_i_1__0_n_0\,
Q => size_mask_q(6),
R => SR(0)
);
split_in_progress_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \USE_R_CHANNEL.cmd_queue_n_17\,
Q => split_in_progress_reg_n_0,
R => '0'
);
split_ongoing_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \USE_R_CHANNEL.cmd_queue_n_0\,
Q => split_ongoing,
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_axi_protocol_converter_v2_1_11_axi3_conv is
port (
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awready : out STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arready : out STD_LOGIC;
\m_axi_arid[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_bvalid : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rlast : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awready : in STD_LOGIC;
aclk : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_rlast : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi3_conv : entity is "axi_protocol_converter_v2_1_11_axi3_conv";
end system_auto_pc_1_axi_protocol_converter_v2_1_11_axi3_conv;
architecture STRUCTURE of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi3_conv is
signal \USE_BURSTS.cmd_queue/inst/empty\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue/inst/empty\ : STD_LOGIC;
signal \USE_WRITE.USE_SPLIT_W.write_resp_inst_n_2\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_56\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_59\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_7\ : STD_LOGIC;
signal areset_d : STD_LOGIC_VECTOR ( 1 downto 0 );
signal first_mi_word : STD_LOGIC;
signal length_counter_1_reg : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_wready\ : STD_LOGIC;
signal wr_cmd_b_ready : STD_LOGIC;
signal wr_cmd_b_repeat : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wr_cmd_b_split : STD_LOGIC;
signal wr_cmd_length : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wr_cmd_ready : STD_LOGIC;
begin
s_axi_wready <= \^s_axi_wready\;
\USE_READ.USE_SPLIT_R.read_addr_inst\: entity work.\system_auto_pc_1_axi_protocol_converter_v2_1_11_a_axi3_conv__parameterized0\
port map (
E(0) => s_axi_arready,
Q(1 downto 0) => \m_axi_arid[1]\(1 downto 0),
SR(0) => \USE_WRITE.write_addr_inst_n_7\,
aclk => aclk,
areset_d(1 downto 0) => areset_d(1 downto 0),
\areset_d_reg[1]\ => \USE_WRITE.write_addr_inst_n_59\,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_arlen(3 downto 0) => m_axi_arlen(3 downto 0),
m_axi_arlock(0) => m_axi_arlock(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_arvalid => m_axi_arvalid,
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(1 downto 0) => s_axi_arid(1 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
\USE_WRITE.USE_SPLIT_W.write_resp_inst\: entity work.system_auto_pc_1_axi_protocol_converter_v2_1_11_b_downsizer
port map (
E(0) => m_axi_bready,
SR(0) => \USE_WRITE.write_addr_inst_n_7\,
\S_AXI_BRESP_ACC_reg[0]_0\ => \USE_WRITE.USE_SPLIT_W.write_resp_inst_n_2\,
aclk => aclk,
dout(4) => wr_cmd_b_split,
dout(3 downto 0) => wr_cmd_b_repeat(3 downto 0),
empty => \USE_B_CHANNEL.cmd_b_queue/inst/empty\,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
wr_cmd_b_ready => wr_cmd_b_ready
);
\USE_WRITE.write_addr_inst\: entity work.system_auto_pc_1_axi_protocol_converter_v2_1_11_a_axi3_conv
port map (
E(0) => s_axi_awready,
SR(0) => \USE_WRITE.write_addr_inst_n_7\,
aclk => aclk,
areset_d(1 downto 0) => areset_d(1 downto 0),
aresetn => aresetn,
command_ongoing_reg_0 => \USE_WRITE.write_addr_inst_n_59\,
din(5 downto 4) => Q(1 downto 0),
din(3 downto 0) => m_axi_awlen(3 downto 0),
dout(5 downto 4) => m_axi_wid(1 downto 0),
dout(3 downto 0) => wr_cmd_length(3 downto 0),
empty => \USE_BURSTS.cmd_queue/inst/empty\,
first_mi_word => first_mi_word,
first_mi_word_reg(4) => wr_cmd_b_split,
first_mi_word_reg(3 downto 0) => wr_cmd_b_repeat(3 downto 0),
\goreg_dm.dout_i_reg[4]\ => \USE_WRITE.USE_SPLIT_W.write_resp_inst_n_2\,
\gpregsm1.user_valid_reg\ => \USE_B_CHANNEL.cmd_b_queue/inst/empty\,
length_counter_1_reg(0) => length_counter_1_reg(0),
\length_counter_1_reg_0__s_port_]\ => \USE_WRITE.write_addr_inst_n_56\,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
m_axi_awlock(0) => m_axi_awlock(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bvalid => m_axi_bvalid,
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(1 downto 0) => s_axi_awid(1 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_wready => \^s_axi_wready\,
s_axi_wvalid => s_axi_wvalid,
wr_cmd_b_ready => wr_cmd_b_ready,
wr_cmd_ready => wr_cmd_ready
);
\USE_WRITE.write_data_inst\: entity work.system_auto_pc_1_axi_protocol_converter_v2_1_11_w_axi3_conv
port map (
SR(0) => \USE_WRITE.write_addr_inst_n_7\,
aclk => aclk,
dout(3 downto 0) => wr_cmd_length(3 downto 0),
empty => \USE_BURSTS.cmd_queue/inst/empty\,
empty_fwft_i_reg => \^s_axi_wready\,
first_mi_word => first_mi_word,
\goreg_dm.dout_i_reg[0]\ => \USE_WRITE.write_addr_inst_n_56\,
\length_counter_1_reg[1]_0\(0) => length_counter_1_reg(0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
s_axi_wvalid => s_axi_wvalid,
wr_cmd_ready => wr_cmd_ready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 2;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 2;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is "axi_protocol_converter_v2_1_11_axi_protocol_converter";
attribute P_AXI3 : integer;
attribute P_AXI3 of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is "3'b011";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 2;
attribute P_DECERR : string;
attribute P_DECERR of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is "2'b11";
attribute P_INCR : string;
attribute P_INCR of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is "2'b10";
end system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter;
architecture STRUCTURE of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter is
signal \<const0>\ : STD_LOGIC;
signal \^m_axi_arlock\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_axi_awlock\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_axi_bid\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_rdata\ : STD_LOGIC_VECTOR ( 63 downto 0 );
signal \^m_axi_rid\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_rresp\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_ruser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 63 downto 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 7 downto 0 );
begin
\^m_axi_bid\(1 downto 0) <= m_axi_bid(1 downto 0);
\^m_axi_rdata\(63 downto 0) <= m_axi_rdata(63 downto 0);
\^m_axi_rid\(1 downto 0) <= m_axi_rid(1 downto 0);
\^m_axi_rresp\(1 downto 0) <= m_axi_rresp(1 downto 0);
\^m_axi_ruser\(0) <= m_axi_ruser(0);
\^s_axi_wdata\(63 downto 0) <= s_axi_wdata(63 downto 0);
\^s_axi_wstrb\(7 downto 0) <= s_axi_wstrb(7 downto 0);
m_axi_arlock(1) <= \<const0>\;
m_axi_arlock(0) <= \^m_axi_arlock\(0);
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awlock(1) <= \<const0>\;
m_axi_awlock(0) <= \^m_axi_awlock\(0);
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(63 downto 0) <= \^s_axi_wdata\(63 downto 0);
m_axi_wstrb(7 downto 0) <= \^s_axi_wstrb\(7 downto 0);
m_axi_wuser(0) <= \<const0>\;
s_axi_bid(1 downto 0) <= \^m_axi_bid\(1 downto 0);
s_axi_buser(0) <= \<const0>\;
s_axi_rdata(63 downto 0) <= \^m_axi_rdata\(63 downto 0);
s_axi_rid(1 downto 0) <= \^m_axi_rid\(1 downto 0);
s_axi_rresp(1 downto 0) <= \^m_axi_rresp\(1 downto 0);
s_axi_ruser(0) <= \^m_axi_ruser\(0);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_axi4_axi3.axi3_conv_inst\: entity work.system_auto_pc_1_axi_protocol_converter_v2_1_11_axi3_conv
port map (
Q(1 downto 0) => m_axi_awid(1 downto 0),
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
\m_axi_arid[1]\(1 downto 0) => m_axi_arid(1 downto 0),
m_axi_arlen(3 downto 0) => m_axi_arlen(3 downto 0),
m_axi_arlock(0) => \^m_axi_arlock\(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
m_axi_awlen(3 downto 0) => m_axi_awlen(3 downto 0),
m_axi_awlock(0) => \^m_axi_awlock\(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
m_axi_wid(1 downto 0) => m_axi_wid(1 downto 0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(1 downto 0) => s_axi_arid(1 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(1 downto 0) => s_axi_awid(1 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_auto_pc_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_auto_pc_1 : entity is "system_auto_pc_1,axi_protocol_converter_v2_1_11_axi_protocol_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_auto_pc_1 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of system_auto_pc_1 : entity is "axi_protocol_converter_v2_1_11_axi_protocol_converter,Vivado 2016.4";
end system_auto_pc_1;
architecture STRUCTURE of system_auto_pc_1 is
signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 2;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of inst : label is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of inst : label is 1;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of inst : label is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of inst : label is 2;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b011";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_DECERR : string;
attribute P_DECERR of inst : label is "2'b11";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of inst : label is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of inst : label is "2'b10";
begin
inst: entity work.system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_arid(1 downto 0) => m_axi_arid(1 downto 0),
m_axi_arlen(3 downto 0) => m_axi_arlen(3 downto 0),
m_axi_arlock(1 downto 0) => m_axi_arlock(1 downto 0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
m_axi_awid(1 downto 0) => m_axi_awid(1 downto 0),
m_axi_awlen(3 downto 0) => m_axi_awlen(3 downto 0),
m_axi_awlock(1 downto 0) => m_axi_awlock(1 downto 0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(1 downto 0) => m_axi_bid(1 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
m_axi_rid(1 downto 0) => m_axi_rid(1 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(63 downto 0) => m_axi_wdata(63 downto 0),
m_axi_wid(1 downto 0) => m_axi_wid(1 downto 0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(7 downto 0) => m_axi_wstrb(7 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(1 downto 0) => s_axi_arid(1 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(1 downto 0) => s_axi_awid(1 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => s_axi_awregion(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(1 downto 0) => s_axi_bid(1 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(63 downto 0) => s_axi_rdata(63 downto 0),
s_axi_rid(1 downto 0) => s_axi_rid(1 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(63 downto 0) => s_axi_wdata(63 downto 0),
s_axi_wid(1 downto 0) => B"00",
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(7 downto 0) => s_axi_wstrb(7 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | d071118b1cc9a62f13f885481a10c694 | 0.601927 | 2.736756 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_vga_test/zed_vga_test.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0_sim_netlist.vhdl | 1 | 194,655 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon May 08 17:41:52 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_processing_system7_0_0 -prefix
-- system_processing_system7_0_0_ system_processing_system7_0_0_sim_netlist.vhdl
-- Design : system_processing_system7_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_processing_system7_0_0_processing_system7_v5_5_processing_system7 is
port (
CAN0_PHY_TX : out STD_LOGIC;
CAN0_PHY_RX : in STD_LOGIC;
CAN1_PHY_TX : out STD_LOGIC;
CAN1_PHY_RX : in STD_LOGIC;
ENET0_GMII_TX_EN : out STD_LOGIC;
ENET0_GMII_TX_ER : out STD_LOGIC;
ENET0_MDIO_MDC : out STD_LOGIC;
ENET0_MDIO_O : out STD_LOGIC;
ENET0_MDIO_T : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_COL : in STD_LOGIC;
ENET0_GMII_CRS : in STD_LOGIC;
ENET0_GMII_RX_CLK : in STD_LOGIC;
ENET0_GMII_RX_DV : in STD_LOGIC;
ENET0_GMII_RX_ER : in STD_LOGIC;
ENET0_GMII_TX_CLK : in STD_LOGIC;
ENET0_MDIO_I : in STD_LOGIC;
ENET0_EXT_INTIN : in STD_LOGIC;
ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_TX_EN : out STD_LOGIC;
ENET1_GMII_TX_ER : out STD_LOGIC;
ENET1_MDIO_MDC : out STD_LOGIC;
ENET1_MDIO_O : out STD_LOGIC;
ENET1_MDIO_T : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET1_SOF_RX : out STD_LOGIC;
ENET1_SOF_TX : out STD_LOGIC;
ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_COL : in STD_LOGIC;
ENET1_GMII_CRS : in STD_LOGIC;
ENET1_GMII_RX_CLK : in STD_LOGIC;
ENET1_GMII_RX_DV : in STD_LOGIC;
ENET1_GMII_RX_ER : in STD_LOGIC;
ENET1_GMII_TX_CLK : in STD_LOGIC;
ENET1_MDIO_I : in STD_LOGIC;
ENET1_EXT_INTIN : in STD_LOGIC;
ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 );
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
PJTAG_TCK : in STD_LOGIC;
PJTAG_TMS : in STD_LOGIC;
PJTAG_TDI : in STD_LOGIC;
PJTAG_TDO : out STD_LOGIC;
SDIO0_CLK : out STD_LOGIC;
SDIO0_CLK_FB : in STD_LOGIC;
SDIO0_CMD_O : out STD_LOGIC;
SDIO0_CMD_I : in STD_LOGIC;
SDIO0_CMD_T : out STD_LOGIC;
SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_LED : out STD_LOGIC;
SDIO0_CDN : in STD_LOGIC;
SDIO0_WP : in STD_LOGIC;
SDIO0_BUSPOW : out STD_LOGIC;
SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SDIO1_CLK : out STD_LOGIC;
SDIO1_CLK_FB : in STD_LOGIC;
SDIO1_CMD_O : out STD_LOGIC;
SDIO1_CMD_I : in STD_LOGIC;
SDIO1_CMD_T : out STD_LOGIC;
SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_LED : out STD_LOGIC;
SDIO1_CDN : in STD_LOGIC;
SDIO1_WP : in STD_LOGIC;
SDIO1_BUSPOW : out STD_LOGIC;
SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
SPI1_SCLK_I : in STD_LOGIC;
SPI1_SCLK_O : out STD_LOGIC;
SPI1_SCLK_T : out STD_LOGIC;
SPI1_MOSI_I : in STD_LOGIC;
SPI1_MOSI_O : out STD_LOGIC;
SPI1_MOSI_T : out STD_LOGIC;
SPI1_MISO_I : in STD_LOGIC;
SPI1_MISO_O : out STD_LOGIC;
SPI1_MISO_T : out STD_LOGIC;
SPI1_SS_I : in STD_LOGIC;
SPI1_SS_O : out STD_LOGIC;
SPI1_SS1_O : out STD_LOGIC;
SPI1_SS2_O : out STD_LOGIC;
SPI1_SS_T : out STD_LOGIC;
UART0_DTRN : out STD_LOGIC;
UART0_RTSN : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_CTSN : in STD_LOGIC;
UART0_DCDN : in STD_LOGIC;
UART0_DSRN : in STD_LOGIC;
UART0_RIN : in STD_LOGIC;
UART0_RX : in STD_LOGIC;
UART1_DTRN : out STD_LOGIC;
UART1_RTSN : out STD_LOGIC;
UART1_TX : out STD_LOGIC;
UART1_CTSN : in STD_LOGIC;
UART1_DCDN : in STD_LOGIC;
UART1_DSRN : in STD_LOGIC;
UART1_RIN : in STD_LOGIC;
UART1_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
TTC0_CLK0_IN : in STD_LOGIC;
TTC0_CLK1_IN : in STD_LOGIC;
TTC0_CLK2_IN : in STD_LOGIC;
TTC1_WAVE0_OUT : out STD_LOGIC;
TTC1_WAVE1_OUT : out STD_LOGIC;
TTC1_WAVE2_OUT : out STD_LOGIC;
TTC1_CLK0_IN : in STD_LOGIC;
TTC1_CLK1_IN : in STD_LOGIC;
TTC1_CLK2_IN : in STD_LOGIC;
WDT_CLK_IN : in STD_LOGIC;
WDT_RST_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 );
TRACE_CLK_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB1_VBUS_PWRSELECT : out STD_LOGIC;
USB1_VBUS_PWRFAULT : in STD_LOGIC;
SRAM_INTIN : in STD_LOGIC;
M_AXI_GP0_ARESETN : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARESETN : out STD_LOGIC;
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARESETN : out STD_LOGIC;
S_AXI_GP0_ARREADY : out STD_LOGIC;
S_AXI_GP0_AWREADY : out STD_LOGIC;
S_AXI_GP0_BVALID : out STD_LOGIC;
S_AXI_GP0_RLAST : out STD_LOGIC;
S_AXI_GP0_RVALID : out STD_LOGIC;
S_AXI_GP0_WREADY : out STD_LOGIC;
S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_ACLK : in STD_LOGIC;
S_AXI_GP0_ARVALID : in STD_LOGIC;
S_AXI_GP0_AWVALID : in STD_LOGIC;
S_AXI_GP0_BREADY : in STD_LOGIC;
S_AXI_GP0_RREADY : in STD_LOGIC;
S_AXI_GP0_WLAST : in STD_LOGIC;
S_AXI_GP0_WVALID : in STD_LOGIC;
S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ARESETN : out STD_LOGIC;
S_AXI_GP1_ARREADY : out STD_LOGIC;
S_AXI_GP1_AWREADY : out STD_LOGIC;
S_AXI_GP1_BVALID : out STD_LOGIC;
S_AXI_GP1_RLAST : out STD_LOGIC;
S_AXI_GP1_RVALID : out STD_LOGIC;
S_AXI_GP1_WREADY : out STD_LOGIC;
S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ACLK : in STD_LOGIC;
S_AXI_GP1_ARVALID : in STD_LOGIC;
S_AXI_GP1_AWVALID : in STD_LOGIC;
S_AXI_GP1_BREADY : in STD_LOGIC;
S_AXI_GP1_RREADY : in STD_LOGIC;
S_AXI_GP1_WLAST : in STD_LOGIC;
S_AXI_GP1_WVALID : in STD_LOGIC;
S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_ACP_ARESETN : out STD_LOGIC;
S_AXI_ACP_ARREADY : out STD_LOGIC;
S_AXI_ACP_AWREADY : out STD_LOGIC;
S_AXI_ACP_BVALID : out STD_LOGIC;
S_AXI_ACP_RLAST : out STD_LOGIC;
S_AXI_ACP_RVALID : out STD_LOGIC;
S_AXI_ACP_WREADY : out STD_LOGIC;
S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_ACLK : in STD_LOGIC;
S_AXI_ACP_ARVALID : in STD_LOGIC;
S_AXI_ACP_AWVALID : in STD_LOGIC;
S_AXI_ACP_BREADY : in STD_LOGIC;
S_AXI_ACP_RREADY : in STD_LOGIC;
S_AXI_ACP_WLAST : in STD_LOGIC;
S_AXI_ACP_WVALID : in STD_LOGIC;
S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_ARESETN : out STD_LOGIC;
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_ARESETN : out STD_LOGIC;
S_AXI_HP1_ARREADY : out STD_LOGIC;
S_AXI_HP1_AWREADY : out STD_LOGIC;
S_AXI_HP1_BVALID : out STD_LOGIC;
S_AXI_HP1_RLAST : out STD_LOGIC;
S_AXI_HP1_RVALID : out STD_LOGIC;
S_AXI_HP1_WREADY : out STD_LOGIC;
S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_ACLK : in STD_LOGIC;
S_AXI_HP1_ARVALID : in STD_LOGIC;
S_AXI_HP1_AWVALID : in STD_LOGIC;
S_AXI_HP1_BREADY : in STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_RREADY : in STD_LOGIC;
S_AXI_HP1_WLAST : in STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_WVALID : in STD_LOGIC;
S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_ARESETN : out STD_LOGIC;
S_AXI_HP2_ARREADY : out STD_LOGIC;
S_AXI_HP2_AWREADY : out STD_LOGIC;
S_AXI_HP2_BVALID : out STD_LOGIC;
S_AXI_HP2_RLAST : out STD_LOGIC;
S_AXI_HP2_RVALID : out STD_LOGIC;
S_AXI_HP2_WREADY : out STD_LOGIC;
S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_ACLK : in STD_LOGIC;
S_AXI_HP2_ARVALID : in STD_LOGIC;
S_AXI_HP2_AWVALID : in STD_LOGIC;
S_AXI_HP2_BREADY : in STD_LOGIC;
S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_RREADY : in STD_LOGIC;
S_AXI_HP2_WLAST : in STD_LOGIC;
S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_WVALID : in STD_LOGIC;
S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_ARESETN : out STD_LOGIC;
S_AXI_HP3_ARREADY : out STD_LOGIC;
S_AXI_HP3_AWREADY : out STD_LOGIC;
S_AXI_HP3_BVALID : out STD_LOGIC;
S_AXI_HP3_RLAST : out STD_LOGIC;
S_AXI_HP3_RVALID : out STD_LOGIC;
S_AXI_HP3_WREADY : out STD_LOGIC;
S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_ACLK : in STD_LOGIC;
S_AXI_HP3_ARVALID : in STD_LOGIC;
S_AXI_HP3_AWVALID : in STD_LOGIC;
S_AXI_HP3_BREADY : in STD_LOGIC;
S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_RREADY : in STD_LOGIC;
S_AXI_HP3_WLAST : in STD_LOGIC;
S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_WVALID : in STD_LOGIC;
S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_P2F_DMAC_ABORT : out STD_LOGIC;
IRQ_P2F_DMAC0 : out STD_LOGIC;
IRQ_P2F_DMAC1 : out STD_LOGIC;
IRQ_P2F_DMAC2 : out STD_LOGIC;
IRQ_P2F_DMAC3 : out STD_LOGIC;
IRQ_P2F_DMAC4 : out STD_LOGIC;
IRQ_P2F_DMAC5 : out STD_LOGIC;
IRQ_P2F_DMAC6 : out STD_LOGIC;
IRQ_P2F_DMAC7 : out STD_LOGIC;
IRQ_P2F_SMC : out STD_LOGIC;
IRQ_P2F_QSPI : out STD_LOGIC;
IRQ_P2F_CTI : out STD_LOGIC;
IRQ_P2F_GPIO : out STD_LOGIC;
IRQ_P2F_USB0 : out STD_LOGIC;
IRQ_P2F_ENET0 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE0 : out STD_LOGIC;
IRQ_P2F_SDIO0 : out STD_LOGIC;
IRQ_P2F_I2C0 : out STD_LOGIC;
IRQ_P2F_SPI0 : out STD_LOGIC;
IRQ_P2F_UART0 : out STD_LOGIC;
IRQ_P2F_CAN0 : out STD_LOGIC;
IRQ_P2F_USB1 : out STD_LOGIC;
IRQ_P2F_ENET1 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE1 : out STD_LOGIC;
IRQ_P2F_SDIO1 : out STD_LOGIC;
IRQ_P2F_I2C1 : out STD_LOGIC;
IRQ_P2F_SPI1 : out STD_LOGIC;
IRQ_P2F_UART1 : out STD_LOGIC;
IRQ_P2F_CAN1 : out STD_LOGIC;
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
Core0_nFIQ : in STD_LOGIC;
Core0_nIRQ : in STD_LOGIC;
Core1_nFIQ : in STD_LOGIC;
Core1_nIRQ : in STD_LOGIC;
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA0_RSTN : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA1_RSTN : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA2_RSTN : out STD_LOGIC;
DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DAVALID : out STD_LOGIC;
DMA3_DRREADY : out STD_LOGIC;
DMA3_RSTN : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA3_ACLK : in STD_LOGIC;
DMA3_DAREADY : in STD_LOGIC;
DMA3_DRLAST : in STD_LOGIC;
DMA3_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK3 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLKTRIG3_N : in STD_LOGIC;
FCLK_CLKTRIG2_N : in STD_LOGIC;
FCLK_CLKTRIG1_N : in STD_LOGIC;
FCLK_CLKTRIG0_N : in STD_LOGIC;
FCLK_RESET3_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMD_TRACEIN_VALID : in STD_LOGIC;
FTMD_TRACEIN_CLK : in STD_LOGIC;
FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 );
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_F2P_TRIG_1 : in STD_LOGIC;
FTMT_F2P_TRIGACK_1 : out STD_LOGIC;
FTMT_F2P_TRIG_2 : in STD_LOGIC;
FTMT_F2P_TRIGACK_2 : out STD_LOGIC;
FTMT_F2P_TRIG_3 : in STD_LOGIC;
FTMT_F2P_TRIGACK_3 : out STD_LOGIC;
FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_1 : in STD_LOGIC;
FTMT_P2F_TRIG_1 : out STD_LOGIC;
FTMT_P2F_TRIGACK_2 : in STD_LOGIC;
FTMT_P2F_TRIG_2 : out STD_LOGIC;
FTMT_P2F_TRIGACK_3 : in STD_LOGIC;
FTMT_P2F_TRIG_3 : out STD_LOGIC;
FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 );
FPGA_IDLE_N : in STD_LOGIC;
EVENT_EVENTO : out STD_LOGIC;
EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_EVENTI : in STD_LOGIC;
DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 );
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "system_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
end system_processing_system7_0_0_processing_system7_v5_5_processing_system7;
architecture STRUCTURE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 is
signal \<const0>\ : STD_LOGIC;
signal ENET0_MDIO_T_n : STD_LOGIC;
signal ENET1_MDIO_T_n : STD_LOGIC;
signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 );
signal I2C0_SCL_T_n : STD_LOGIC;
signal I2C0_SDA_T_n : STD_LOGIC;
signal I2C1_SCL_T_n : STD_LOGIC;
signal I2C1_SDA_T_n : STD_LOGIC;
signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal SDIO0_CMD_T_n : STD_LOGIC;
signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SDIO1_CMD_T_n : STD_LOGIC;
signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SPI0_MISO_T_n : STD_LOGIC;
signal SPI0_MOSI_T_n : STD_LOGIC;
signal SPI0_SCLK_T_n : STD_LOGIC;
signal SPI0_SS_T_n : STD_LOGIC;
signal SPI1_MISO_T_n : STD_LOGIC;
signal SPI1_MOSI_T_n : STD_LOGIC;
signal SPI1_SCLK_T_n : STD_LOGIC;
signal SPI1_SS_T_n : STD_LOGIC;
signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true";
signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true";
signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true";
signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true";
signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true";
signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true";
signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true";
signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true";
signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true";
signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true";
signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true";
signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true";
signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true";
signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true";
signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true";
signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true";
signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 );
signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal buffered_DDR_CAS_n : STD_LOGIC;
signal buffered_DDR_CKE : STD_LOGIC;
signal buffered_DDR_CS_n : STD_LOGIC;
signal buffered_DDR_Clk : STD_LOGIC;
signal buffered_DDR_Clk_n : STD_LOGIC;
signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DRSTB : STD_LOGIC;
signal buffered_DDR_ODT : STD_LOGIC;
signal buffered_DDR_RAS_n : STD_LOGIC;
signal buffered_DDR_VRN : STD_LOGIC;
signal buffered_DDR_VRP : STD_LOGIC;
signal buffered_DDR_WEB : STD_LOGIC;
signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal buffered_PS_CLK : STD_LOGIC;
signal buffered_PS_PORB : STD_LOGIC;
signal buffered_PS_SRSTB : STD_LOGIC;
signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
begin
ENET0_GMII_TXD(7) <= \<const0>\;
ENET0_GMII_TXD(6) <= \<const0>\;
ENET0_GMII_TXD(5) <= \<const0>\;
ENET0_GMII_TXD(4) <= \<const0>\;
ENET0_GMII_TXD(3) <= \<const0>\;
ENET0_GMII_TXD(2) <= \<const0>\;
ENET0_GMII_TXD(1) <= \<const0>\;
ENET0_GMII_TXD(0) <= \<const0>\;
ENET0_GMII_TX_EN <= \<const0>\;
ENET0_GMII_TX_ER <= \<const0>\;
ENET1_GMII_TXD(7) <= \<const0>\;
ENET1_GMII_TXD(6) <= \<const0>\;
ENET1_GMII_TXD(5) <= \<const0>\;
ENET1_GMII_TXD(4) <= \<const0>\;
ENET1_GMII_TXD(3) <= \<const0>\;
ENET1_GMII_TXD(2) <= \<const0>\;
ENET1_GMII_TXD(1) <= \<const0>\;
ENET1_GMII_TXD(0) <= \<const0>\;
ENET1_GMII_TX_EN <= \<const0>\;
ENET1_GMII_TX_ER <= \<const0>\;
M_AXI_GP0_ARSIZE(2) <= \<const0>\;
M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0);
M_AXI_GP0_AWSIZE(2) <= \<const0>\;
M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0);
M_AXI_GP1_ARSIZE(2) <= \<const0>\;
M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0);
M_AXI_GP1_AWSIZE(2) <= \<const0>\;
M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0);
PJTAG_TDO <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \TRACE_CTL_PIPE[0]\;
TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0);
DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CAS_n,
PAD => DDR_CAS_n
);
DDR_CKE_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CKE,
PAD => DDR_CKE
);
DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CS_n,
PAD => DDR_CS_n
);
DDR_Clk_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk,
PAD => DDR_Clk
);
DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk_n,
PAD => DDR_Clk_n
);
DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DRSTB,
PAD => DDR_DRSTB
);
DDR_ODT_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_ODT,
PAD => DDR_ODT
);
DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_RAS_n,
PAD => DDR_RAS_n
);
DDR_VRN_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRN,
PAD => DDR_VRN
);
DDR_VRP_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRP,
PAD => DDR_VRP
);
DDR_WEB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_WEB,
PAD => DDR_WEB
);
ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET0_MDIO_T_n,
O => ENET0_MDIO_T
);
ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET1_MDIO_T_n,
O => ENET1_MDIO_T
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(0),
O => GPIO_T(0)
);
\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(10),
O => GPIO_T(10)
);
\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(11),
O => GPIO_T(11)
);
\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(12),
O => GPIO_T(12)
);
\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(13),
O => GPIO_T(13)
);
\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(14),
O => GPIO_T(14)
);
\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(15),
O => GPIO_T(15)
);
\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(16),
O => GPIO_T(16)
);
\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(17),
O => GPIO_T(17)
);
\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(18),
O => GPIO_T(18)
);
\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(19),
O => GPIO_T(19)
);
\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(1),
O => GPIO_T(1)
);
\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(20),
O => GPIO_T(20)
);
\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(21),
O => GPIO_T(21)
);
\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(22),
O => GPIO_T(22)
);
\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(23),
O => GPIO_T(23)
);
\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(24),
O => GPIO_T(24)
);
\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(25),
O => GPIO_T(25)
);
\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(26),
O => GPIO_T(26)
);
\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(27),
O => GPIO_T(27)
);
\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(28),
O => GPIO_T(28)
);
\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(29),
O => GPIO_T(29)
);
\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(2),
O => GPIO_T(2)
);
\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(30),
O => GPIO_T(30)
);
\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(31),
O => GPIO_T(31)
);
\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(32),
O => GPIO_T(32)
);
\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(33),
O => GPIO_T(33)
);
\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(34),
O => GPIO_T(34)
);
\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(35),
O => GPIO_T(35)
);
\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(36),
O => GPIO_T(36)
);
\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(37),
O => GPIO_T(37)
);
\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(38),
O => GPIO_T(38)
);
\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(39),
O => GPIO_T(39)
);
\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(3),
O => GPIO_T(3)
);
\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(40),
O => GPIO_T(40)
);
\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(41),
O => GPIO_T(41)
);
\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(42),
O => GPIO_T(42)
);
\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(43),
O => GPIO_T(43)
);
\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(44),
O => GPIO_T(44)
);
\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(45),
O => GPIO_T(45)
);
\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(46),
O => GPIO_T(46)
);
\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(47),
O => GPIO_T(47)
);
\GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(48),
O => GPIO_T(48)
);
\GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(49),
O => GPIO_T(49)
);
\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(4),
O => GPIO_T(4)
);
\GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(50),
O => GPIO_T(50)
);
\GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(51),
O => GPIO_T(51)
);
\GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(52),
O => GPIO_T(52)
);
\GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(53),
O => GPIO_T(53)
);
\GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(54),
O => GPIO_T(54)
);
\GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(55),
O => GPIO_T(55)
);
\GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(56),
O => GPIO_T(56)
);
\GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(57),
O => GPIO_T(57)
);
\GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(58),
O => GPIO_T(58)
);
\GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(59),
O => GPIO_T(59)
);
\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(5),
O => GPIO_T(5)
);
\GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(60),
O => GPIO_T(60)
);
\GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(61),
O => GPIO_T(61)
);
\GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(62),
O => GPIO_T(62)
);
\GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(63),
O => GPIO_T(63)
);
\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(6),
O => GPIO_T(6)
);
\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(7),
O => GPIO_T(7)
);
\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(8),
O => GPIO_T(8)
);
\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(9),
O => GPIO_T(9)
);
I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SCL_T_n,
O => I2C0_SCL_T
);
I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SDA_T_n,
O => I2C0_SDA_T
);
I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SCL_T_n,
O => I2C1_SCL_T
);
I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SDA_T_n,
O => I2C1_SDA_T
);
PS7_i: unisim.vcomponents.PS7
port map (
DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0),
DDRARB(3 downto 0) => DDR_ARB(3 downto 0),
DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0),
DDRCASB => buffered_DDR_CAS_n,
DDRCKE => buffered_DDR_CKE,
DDRCKN => buffered_DDR_Clk_n,
DDRCKP => buffered_DDR_Clk,
DDRCSB => buffered_DDR_CS_n,
DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0),
DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0),
DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0),
DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0),
DDRDRSTB => buffered_DDR_DRSTB,
DDRODT => buffered_DDR_ODT,
DDRRASB => buffered_DDR_RAS_n,
DDRVRN => buffered_DDR_VRN,
DDRVRP => buffered_DDR_VRP,
DDRWEB => buffered_DDR_WEB,
DMA0ACLK => DMA0_ACLK,
DMA0DAREADY => DMA0_DAREADY,
DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0),
DMA0DAVALID => DMA0_DAVALID,
DMA0DRLAST => DMA0_DRLAST,
DMA0DRREADY => DMA0_DRREADY,
DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0),
DMA0DRVALID => DMA0_DRVALID,
DMA0RSTN => DMA0_RSTN,
DMA1ACLK => DMA1_ACLK,
DMA1DAREADY => DMA1_DAREADY,
DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0),
DMA1DAVALID => DMA1_DAVALID,
DMA1DRLAST => DMA1_DRLAST,
DMA1DRREADY => DMA1_DRREADY,
DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0),
DMA1DRVALID => DMA1_DRVALID,
DMA1RSTN => DMA1_RSTN,
DMA2ACLK => DMA2_ACLK,
DMA2DAREADY => DMA2_DAREADY,
DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0),
DMA2DAVALID => DMA2_DAVALID,
DMA2DRLAST => DMA2_DRLAST,
DMA2DRREADY => DMA2_DRREADY,
DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0),
DMA2DRVALID => DMA2_DRVALID,
DMA2RSTN => DMA2_RSTN,
DMA3ACLK => DMA3_ACLK,
DMA3DAREADY => DMA3_DAREADY,
DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0),
DMA3DAVALID => DMA3_DAVALID,
DMA3DRLAST => DMA3_DRLAST,
DMA3DRREADY => DMA3_DRREADY,
DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0),
DMA3DRVALID => DMA3_DRVALID,
DMA3RSTN => DMA3_RSTN,
EMIOCAN0PHYRX => CAN0_PHY_RX,
EMIOCAN0PHYTX => CAN0_PHY_TX,
EMIOCAN1PHYRX => CAN1_PHY_RX,
EMIOCAN1PHYTX => CAN1_PHY_TX,
EMIOENET0EXTINTIN => ENET0_EXT_INTIN,
EMIOENET0GMIICOL => '0',
EMIOENET0GMIICRS => '0',
EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK,
EMIOENET0GMIIRXD(7 downto 0) => B"00000000",
EMIOENET0GMIIRXDV => '0',
EMIOENET0GMIIRXER => '0',
EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK,
EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED,
EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED,
EMIOENET0MDIOI => ENET0_MDIO_I,
EMIOENET0MDIOMDC => ENET0_MDIO_MDC,
EMIOENET0MDIOO => ENET0_MDIO_O,
EMIOENET0MDIOTN => ENET0_MDIO_T_n,
EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX,
EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX,
EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX,
EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX,
EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX,
EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX,
EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX,
EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX,
EMIOENET0SOFRX => ENET0_SOF_RX,
EMIOENET0SOFTX => ENET0_SOF_TX,
EMIOENET1EXTINTIN => ENET1_EXT_INTIN,
EMIOENET1GMIICOL => '0',
EMIOENET1GMIICRS => '0',
EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK,
EMIOENET1GMIIRXD(7 downto 0) => B"00000000",
EMIOENET1GMIIRXDV => '0',
EMIOENET1GMIIRXER => '0',
EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK,
EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED,
EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED,
EMIOENET1MDIOI => ENET1_MDIO_I,
EMIOENET1MDIOMDC => ENET1_MDIO_MDC,
EMIOENET1MDIOO => ENET1_MDIO_O,
EMIOENET1MDIOTN => ENET1_MDIO_T_n,
EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX,
EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX,
EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX,
EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX,
EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX,
EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX,
EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX,
EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX,
EMIOENET1SOFRX => ENET1_SOF_RX,
EMIOENET1SOFTX => ENET1_SOF_TX,
EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0),
EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0),
EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0),
EMIOI2C0SCLI => I2C0_SCL_I,
EMIOI2C0SCLO => I2C0_SCL_O,
EMIOI2C0SCLTN => I2C0_SCL_T_n,
EMIOI2C0SDAI => I2C0_SDA_I,
EMIOI2C0SDAO => I2C0_SDA_O,
EMIOI2C0SDATN => I2C0_SDA_T_n,
EMIOI2C1SCLI => I2C1_SCL_I,
EMIOI2C1SCLO => I2C1_SCL_O,
EMIOI2C1SCLTN => I2C1_SCL_T_n,
EMIOI2C1SDAI => I2C1_SDA_I,
EMIOI2C1SDAO => I2C1_SDA_O,
EMIOI2C1SDATN => I2C1_SDA_T_n,
EMIOPJTAGTCK => PJTAG_TCK,
EMIOPJTAGTDI => PJTAG_TDI,
EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED,
EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED,
EMIOPJTAGTMS => PJTAG_TMS,
EMIOSDIO0BUSPOW => SDIO0_BUSPOW,
EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0),
EMIOSDIO0CDN => SDIO0_CDN,
EMIOSDIO0CLK => SDIO0_CLK,
EMIOSDIO0CLKFB => SDIO0_CLK_FB,
EMIOSDIO0CMDI => SDIO0_CMD_I,
EMIOSDIO0CMDO => SDIO0_CMD_O,
EMIOSDIO0CMDTN => SDIO0_CMD_T_n,
EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0),
EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0),
EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0),
EMIOSDIO0LED => SDIO0_LED,
EMIOSDIO0WP => SDIO0_WP,
EMIOSDIO1BUSPOW => SDIO1_BUSPOW,
EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0),
EMIOSDIO1CDN => SDIO1_CDN,
EMIOSDIO1CLK => SDIO1_CLK,
EMIOSDIO1CLKFB => SDIO1_CLK_FB,
EMIOSDIO1CMDI => SDIO1_CMD_I,
EMIOSDIO1CMDO => SDIO1_CMD_O,
EMIOSDIO1CMDTN => SDIO1_CMD_T_n,
EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0),
EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0),
EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0),
EMIOSDIO1LED => SDIO1_LED,
EMIOSDIO1WP => SDIO1_WP,
EMIOSPI0MI => SPI0_MISO_I,
EMIOSPI0MO => SPI0_MOSI_O,
EMIOSPI0MOTN => SPI0_MOSI_T_n,
EMIOSPI0SCLKI => SPI0_SCLK_I,
EMIOSPI0SCLKO => SPI0_SCLK_O,
EMIOSPI0SCLKTN => SPI0_SCLK_T_n,
EMIOSPI0SI => SPI0_MOSI_I,
EMIOSPI0SO => SPI0_MISO_O,
EMIOSPI0SSIN => SPI0_SS_I,
EMIOSPI0SSNTN => SPI0_SS_T_n,
EMIOSPI0SSON(2) => SPI0_SS2_O,
EMIOSPI0SSON(1) => SPI0_SS1_O,
EMIOSPI0SSON(0) => SPI0_SS_O,
EMIOSPI0STN => SPI0_MISO_T_n,
EMIOSPI1MI => SPI1_MISO_I,
EMIOSPI1MO => SPI1_MOSI_O,
EMIOSPI1MOTN => SPI1_MOSI_T_n,
EMIOSPI1SCLKI => SPI1_SCLK_I,
EMIOSPI1SCLKO => SPI1_SCLK_O,
EMIOSPI1SCLKTN => SPI1_SCLK_T_n,
EMIOSPI1SI => SPI1_MOSI_I,
EMIOSPI1SO => SPI1_MISO_O,
EMIOSPI1SSIN => SPI1_SS_I,
EMIOSPI1SSNTN => SPI1_SS_T_n,
EMIOSPI1SSON(2) => SPI1_SS2_O,
EMIOSPI1SSON(1) => SPI1_SS1_O,
EMIOSPI1SSON(0) => SPI1_SS_O,
EMIOSPI1STN => SPI1_MISO_T_n,
EMIOSRAMINTIN => SRAM_INTIN,
EMIOTRACECLK => TRACE_CLK,
EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED,
EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0),
EMIOTTC0CLKI(2) => TTC0_CLK2_IN,
EMIOTTC0CLKI(1) => TTC0_CLK1_IN,
EMIOTTC0CLKI(0) => TTC0_CLK0_IN,
EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT,
EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT,
EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT,
EMIOTTC1CLKI(2) => TTC1_CLK2_IN,
EMIOTTC1CLKI(1) => TTC1_CLK1_IN,
EMIOTTC1CLKI(0) => TTC1_CLK0_IN,
EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT,
EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT,
EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT,
EMIOUART0CTSN => UART0_CTSN,
EMIOUART0DCDN => UART0_DCDN,
EMIOUART0DSRN => UART0_DSRN,
EMIOUART0DTRN => UART0_DTRN,
EMIOUART0RIN => UART0_RIN,
EMIOUART0RTSN => UART0_RTSN,
EMIOUART0RX => UART0_RX,
EMIOUART0TX => UART0_TX,
EMIOUART1CTSN => UART1_CTSN,
EMIOUART1DCDN => UART1_DCDN,
EMIOUART1DSRN => UART1_DSRN,
EMIOUART1DTRN => UART1_DTRN,
EMIOUART1RIN => UART1_RIN,
EMIOUART1RTSN => UART1_RTSN,
EMIOUART1RX => UART1_RX,
EMIOUART1TX => UART1_TX,
EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT,
EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT,
EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT,
EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT,
EMIOWDTCLKI => WDT_CLK_IN,
EMIOWDTRSTO => WDT_RST_OUT,
EVENTEVENTI => EVENT_EVENTI,
EVENTEVENTO => EVENT_EVENTO,
EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0),
EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0),
FCLKCLK(3) => FCLK_CLK3,
FCLKCLK(2) => FCLK_CLK2,
FCLKCLK(1) => FCLK_CLK1,
FCLKCLK(0) => FCLK_CLK_unbuffered(0),
FCLKCLKTRIGN(3 downto 0) => B"0000",
FCLKRESETN(3) => FCLK_RESET3_N,
FCLKRESETN(2) => FCLK_RESET2_N,
FCLKRESETN(1) => FCLK_RESET1_N,
FCLKRESETN(0) => FCLK_RESET0_N,
FPGAIDLEN => FPGA_IDLE_N,
FTMDTRACEINATID(3 downto 0) => B"0000",
FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK,
FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000",
FTMDTRACEINVALID => '0',
FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0),
FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3,
FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2,
FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1,
FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0,
FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3,
FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2,
FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1,
FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0,
FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0),
FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3,
FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2,
FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1,
FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0,
FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3,
FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2,
FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1,
FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0,
IRQF2P(19) => Core1_nFIQ,
IRQF2P(18) => Core0_nFIQ,
IRQF2P(17) => Core1_nIRQ,
IRQF2P(16) => Core0_nIRQ,
IRQF2P(15 downto 1) => B"000000000000000",
IRQF2P(0) => IRQ_F2P(0),
IRQP2F(28) => IRQ_P2F_DMAC_ABORT,
IRQP2F(27) => IRQ_P2F_DMAC7,
IRQP2F(26) => IRQ_P2F_DMAC6,
IRQP2F(25) => IRQ_P2F_DMAC5,
IRQP2F(24) => IRQ_P2F_DMAC4,
IRQP2F(23) => IRQ_P2F_DMAC3,
IRQP2F(22) => IRQ_P2F_DMAC2,
IRQP2F(21) => IRQ_P2F_DMAC1,
IRQP2F(20) => IRQ_P2F_DMAC0,
IRQP2F(19) => IRQ_P2F_SMC,
IRQP2F(18) => IRQ_P2F_QSPI,
IRQP2F(17) => IRQ_P2F_CTI,
IRQP2F(16) => IRQ_P2F_GPIO,
IRQP2F(15) => IRQ_P2F_USB0,
IRQP2F(14) => IRQ_P2F_ENET0,
IRQP2F(13) => IRQ_P2F_ENET_WAKE0,
IRQP2F(12) => IRQ_P2F_SDIO0,
IRQP2F(11) => IRQ_P2F_I2C0,
IRQP2F(10) => IRQ_P2F_SPI0,
IRQP2F(9) => IRQ_P2F_UART0,
IRQP2F(8) => IRQ_P2F_CAN0,
IRQP2F(7) => IRQ_P2F_USB1,
IRQP2F(6) => IRQ_P2F_ENET1,
IRQP2F(5) => IRQ_P2F_ENET_WAKE1,
IRQP2F(4) => IRQ_P2F_SDIO1,
IRQP2F(3) => IRQ_P2F_I2C1,
IRQP2F(2) => IRQ_P2F_SPI1,
IRQP2F(1) => IRQ_P2F_UART1,
IRQP2F(0) => IRQ_P2F_CAN1,
MAXIGP0ACLK => M_AXI_GP0_ACLK,
MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
MAXIGP0ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
MAXIGP0ARESETN => M_AXI_GP0_ARESETN,
MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
MAXIGP0ARREADY => M_AXI_GP0_ARREADY,
MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0),
MAXIGP0ARVALID => M_AXI_GP0_ARVALID,
MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
MAXIGP0AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
MAXIGP0AWREADY => M_AXI_GP0_AWREADY,
MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0),
MAXIGP0AWVALID => M_AXI_GP0_AWVALID,
MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
MAXIGP0BREADY => M_AXI_GP0_BREADY,
MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
MAXIGP0BVALID => M_AXI_GP0_BVALID,
MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
MAXIGP0RLAST => M_AXI_GP0_RLAST,
MAXIGP0RREADY => M_AXI_GP0_RREADY,
MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
MAXIGP0RVALID => M_AXI_GP0_RVALID,
MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
MAXIGP0WLAST => M_AXI_GP0_WLAST,
MAXIGP0WREADY => M_AXI_GP0_WREADY,
MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
MAXIGP0WVALID => M_AXI_GP0_WVALID,
MAXIGP1ACLK => M_AXI_GP1_ACLK,
MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
MAXIGP1ARCACHE(3 downto 0) => M_AXI_GP1_ARCACHE(3 downto 0),
MAXIGP1ARESETN => M_AXI_GP1_ARESETN,
MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
MAXIGP1ARREADY => M_AXI_GP1_ARREADY,
MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0),
MAXIGP1ARVALID => M_AXI_GP1_ARVALID,
MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
MAXIGP1AWCACHE(3 downto 0) => M_AXI_GP1_AWCACHE(3 downto 0),
MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
MAXIGP1AWREADY => M_AXI_GP1_AWREADY,
MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0),
MAXIGP1AWVALID => M_AXI_GP1_AWVALID,
MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
MAXIGP1BREADY => M_AXI_GP1_BREADY,
MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
MAXIGP1BVALID => M_AXI_GP1_BVALID,
MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
MAXIGP1RLAST => M_AXI_GP1_RLAST,
MAXIGP1RREADY => M_AXI_GP1_RREADY,
MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
MAXIGP1RVALID => M_AXI_GP1_RVALID,
MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
MAXIGP1WLAST => M_AXI_GP1_WLAST,
MAXIGP1WREADY => M_AXI_GP1_WREADY,
MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
MAXIGP1WVALID => M_AXI_GP1_WVALID,
MIO(53 downto 0) => buffered_MIO(53 downto 0),
PSCLK => buffered_PS_CLK,
PSPORB => buffered_PS_PORB,
PSSRSTB => buffered_PS_SRSTB,
SAXIACPACLK => S_AXI_ACP_ACLK,
SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0),
SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0),
SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0),
SAXIACPARESETN => S_AXI_ACP_ARESETN,
SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0),
SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0),
SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0),
SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0),
SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0),
SAXIACPARREADY => S_AXI_ACP_ARREADY,
SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0),
SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0),
SAXIACPARVALID => S_AXI_ACP_ARVALID,
SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0),
SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0),
SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0),
SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0),
SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0),
SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0),
SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0),
SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0),
SAXIACPAWREADY => S_AXI_ACP_AWREADY,
SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0),
SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0),
SAXIACPAWVALID => S_AXI_ACP_AWVALID,
SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0),
SAXIACPBREADY => S_AXI_ACP_BREADY,
SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0),
SAXIACPBVALID => S_AXI_ACP_BVALID,
SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0),
SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0),
SAXIACPRLAST => S_AXI_ACP_RLAST,
SAXIACPRREADY => S_AXI_ACP_RREADY,
SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0),
SAXIACPRVALID => S_AXI_ACP_RVALID,
SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0),
SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0),
SAXIACPWLAST => S_AXI_ACP_WLAST,
SAXIACPWREADY => S_AXI_ACP_WREADY,
SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0),
SAXIACPWVALID => S_AXI_ACP_WVALID,
SAXIGP0ACLK => S_AXI_GP0_ACLK,
SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0),
SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0),
SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0),
SAXIGP0ARESETN => S_AXI_GP0_ARESETN,
SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0),
SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0),
SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0),
SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0),
SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0),
SAXIGP0ARREADY => S_AXI_GP0_ARREADY,
SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0),
SAXIGP0ARVALID => S_AXI_GP0_ARVALID,
SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0),
SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0),
SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0),
SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0),
SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0),
SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0),
SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0),
SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0),
SAXIGP0AWREADY => S_AXI_GP0_AWREADY,
SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0),
SAXIGP0AWVALID => S_AXI_GP0_AWVALID,
SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0),
SAXIGP0BREADY => S_AXI_GP0_BREADY,
SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0),
SAXIGP0BVALID => S_AXI_GP0_BVALID,
SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0),
SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0),
SAXIGP0RLAST => S_AXI_GP0_RLAST,
SAXIGP0RREADY => S_AXI_GP0_RREADY,
SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0),
SAXIGP0RVALID => S_AXI_GP0_RVALID,
SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0),
SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0),
SAXIGP0WLAST => S_AXI_GP0_WLAST,
SAXIGP0WREADY => S_AXI_GP0_WREADY,
SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0),
SAXIGP0WVALID => S_AXI_GP0_WVALID,
SAXIGP1ACLK => S_AXI_GP1_ACLK,
SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0),
SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0),
SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0),
SAXIGP1ARESETN => S_AXI_GP1_ARESETN,
SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0),
SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0),
SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0),
SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0),
SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0),
SAXIGP1ARREADY => S_AXI_GP1_ARREADY,
SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0),
SAXIGP1ARVALID => S_AXI_GP1_ARVALID,
SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0),
SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0),
SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0),
SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0),
SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0),
SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0),
SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0),
SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0),
SAXIGP1AWREADY => S_AXI_GP1_AWREADY,
SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0),
SAXIGP1AWVALID => S_AXI_GP1_AWVALID,
SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0),
SAXIGP1BREADY => S_AXI_GP1_BREADY,
SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0),
SAXIGP1BVALID => S_AXI_GP1_BVALID,
SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0),
SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0),
SAXIGP1RLAST => S_AXI_GP1_RLAST,
SAXIGP1RREADY => S_AXI_GP1_RREADY,
SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0),
SAXIGP1RVALID => S_AXI_GP1_RVALID,
SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0),
SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0),
SAXIGP1WLAST => S_AXI_GP1_WLAST,
SAXIGP1WREADY => S_AXI_GP1_WREADY,
SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0),
SAXIGP1WVALID => S_AXI_GP1_WVALID,
SAXIHP0ACLK => S_AXI_HP0_ACLK,
SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
SAXIHP0ARESETN => S_AXI_HP0_ARESETN,
SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
SAXIHP0ARREADY => S_AXI_HP0_ARREADY,
SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0),
SAXIHP0ARVALID => S_AXI_HP0_ARVALID,
SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
SAXIHP0AWREADY => S_AXI_HP0_AWREADY,
SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0),
SAXIHP0AWVALID => S_AXI_HP0_AWVALID,
SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
SAXIHP0BREADY => S_AXI_HP0_BREADY,
SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
SAXIHP0BVALID => S_AXI_HP0_BVALID,
SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN,
SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
SAXIHP0RLAST => S_AXI_HP0_RLAST,
SAXIHP0RREADY => S_AXI_HP0_RREADY,
SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
SAXIHP0RVALID => S_AXI_HP0_RVALID,
SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
SAXIHP0WLAST => S_AXI_HP0_WLAST,
SAXIHP0WREADY => S_AXI_HP0_WREADY,
SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN,
SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
SAXIHP0WVALID => S_AXI_HP0_WVALID,
SAXIHP1ACLK => S_AXI_HP1_ACLK,
SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
SAXIHP1ARESETN => S_AXI_HP1_ARESETN,
SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
SAXIHP1ARREADY => S_AXI_HP1_ARREADY,
SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0),
SAXIHP1ARVALID => S_AXI_HP1_ARVALID,
SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
SAXIHP1AWREADY => S_AXI_HP1_AWREADY,
SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0),
SAXIHP1AWVALID => S_AXI_HP1_AWVALID,
SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
SAXIHP1BREADY => S_AXI_HP1_BREADY,
SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
SAXIHP1BVALID => S_AXI_HP1_BVALID,
SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN,
SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
SAXIHP1RLAST => S_AXI_HP1_RLAST,
SAXIHP1RREADY => S_AXI_HP1_RREADY,
SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
SAXIHP1RVALID => S_AXI_HP1_RVALID,
SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
SAXIHP1WLAST => S_AXI_HP1_WLAST,
SAXIHP1WREADY => S_AXI_HP1_WREADY,
SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN,
SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
SAXIHP1WVALID => S_AXI_HP1_WVALID,
SAXIHP2ACLK => S_AXI_HP2_ACLK,
SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0),
SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0),
SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0),
SAXIHP2ARESETN => S_AXI_HP2_ARESETN,
SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0),
SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0),
SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0),
SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0),
SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0),
SAXIHP2ARREADY => S_AXI_HP2_ARREADY,
SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0),
SAXIHP2ARVALID => S_AXI_HP2_ARVALID,
SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0),
SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0),
SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0),
SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0),
SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0),
SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0),
SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0),
SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0),
SAXIHP2AWREADY => S_AXI_HP2_AWREADY,
SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0),
SAXIHP2AWVALID => S_AXI_HP2_AWVALID,
SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0),
SAXIHP2BREADY => S_AXI_HP2_BREADY,
SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0),
SAXIHP2BVALID => S_AXI_HP2_BVALID,
SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0),
SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0),
SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0),
SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN,
SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0),
SAXIHP2RLAST => S_AXI_HP2_RLAST,
SAXIHP2RREADY => S_AXI_HP2_RREADY,
SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0),
SAXIHP2RVALID => S_AXI_HP2_RVALID,
SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0),
SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0),
SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0),
SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0),
SAXIHP2WLAST => S_AXI_HP2_WLAST,
SAXIHP2WREADY => S_AXI_HP2_WREADY,
SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN,
SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0),
SAXIHP2WVALID => S_AXI_HP2_WVALID,
SAXIHP3ACLK => S_AXI_HP3_ACLK,
SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0),
SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0),
SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0),
SAXIHP3ARESETN => S_AXI_HP3_ARESETN,
SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0),
SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0),
SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0),
SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0),
SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0),
SAXIHP3ARREADY => S_AXI_HP3_ARREADY,
SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0),
SAXIHP3ARVALID => S_AXI_HP3_ARVALID,
SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0),
SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0),
SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0),
SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0),
SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0),
SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0),
SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0),
SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0),
SAXIHP3AWREADY => S_AXI_HP3_AWREADY,
SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0),
SAXIHP3AWVALID => S_AXI_HP3_AWVALID,
SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0),
SAXIHP3BREADY => S_AXI_HP3_BREADY,
SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0),
SAXIHP3BVALID => S_AXI_HP3_BVALID,
SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0),
SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0),
SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0),
SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN,
SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0),
SAXIHP3RLAST => S_AXI_HP3_RLAST,
SAXIHP3RREADY => S_AXI_HP3_RREADY,
SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0),
SAXIHP3RVALID => S_AXI_HP3_RVALID,
SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0),
SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0),
SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0),
SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0),
SAXIHP3WLAST => S_AXI_HP3_WLAST,
SAXIHP3WREADY => S_AXI_HP3_WREADY,
SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN,
SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0),
SAXIHP3WVALID => S_AXI_HP3_WVALID
);
PS_CLK_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_CLK,
PAD => PS_CLK
);
PS_PORB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_PORB,
PAD => PS_PORB
);
PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_SRSTB,
PAD => PS_SRSTB
);
SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_CMD_T_n,
O => SDIO0_CMD_T
);
\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(0),
O => SDIO0_DATA_T(0)
);
\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(1),
O => SDIO0_DATA_T(1)
);
\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(2),
O => SDIO0_DATA_T(2)
);
\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(3),
O => SDIO0_DATA_T(3)
);
SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_CMD_T_n,
O => SDIO1_CMD_T
);
\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(0),
O => SDIO1_DATA_T(0)
);
\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(1),
O => SDIO1_DATA_T(1)
);
\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(2),
O => SDIO1_DATA_T(2)
);
\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(3),
O => SDIO1_DATA_T(3)
);
SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MISO_T_n,
O => SPI0_MISO_T
);
SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MOSI_T_n,
O => SPI0_MOSI_T
);
SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SCLK_T_n,
O => SPI0_SCLK_T
);
SPI0_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SS_T_n,
O => SPI0_SS_T
);
SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MISO_T_n,
O => SPI1_MISO_T
);
SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MOSI_T_n,
O => SPI1_MOSI_T
);
SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SCLK_T_n,
O => SPI1_SCLK_T
);
SPI1_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SS_T_n,
O => SPI1_SS_T
);
\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(0),
O => FCLK_CLK0
);
\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(0),
PAD => MIO(0)
);
\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(10),
PAD => MIO(10)
);
\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(11),
PAD => MIO(11)
);
\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(12),
PAD => MIO(12)
);
\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(13),
PAD => MIO(13)
);
\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(14),
PAD => MIO(14)
);
\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(15),
PAD => MIO(15)
);
\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(16),
PAD => MIO(16)
);
\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(17),
PAD => MIO(17)
);
\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(18),
PAD => MIO(18)
);
\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(19),
PAD => MIO(19)
);
\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(1),
PAD => MIO(1)
);
\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(20),
PAD => MIO(20)
);
\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(21),
PAD => MIO(21)
);
\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(22),
PAD => MIO(22)
);
\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(23),
PAD => MIO(23)
);
\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(24),
PAD => MIO(24)
);
\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(25),
PAD => MIO(25)
);
\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(26),
PAD => MIO(26)
);
\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(27),
PAD => MIO(27)
);
\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(28),
PAD => MIO(28)
);
\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(29),
PAD => MIO(29)
);
\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(2),
PAD => MIO(2)
);
\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(30),
PAD => MIO(30)
);
\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(31),
PAD => MIO(31)
);
\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(32),
PAD => MIO(32)
);
\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(33),
PAD => MIO(33)
);
\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(34),
PAD => MIO(34)
);
\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(35),
PAD => MIO(35)
);
\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(36),
PAD => MIO(36)
);
\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(37),
PAD => MIO(37)
);
\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(38),
PAD => MIO(38)
);
\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(39),
PAD => MIO(39)
);
\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(3),
PAD => MIO(3)
);
\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(40),
PAD => MIO(40)
);
\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(41),
PAD => MIO(41)
);
\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(42),
PAD => MIO(42)
);
\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(43),
PAD => MIO(43)
);
\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(44),
PAD => MIO(44)
);
\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(45),
PAD => MIO(45)
);
\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(46),
PAD => MIO(46)
);
\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(47),
PAD => MIO(47)
);
\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(48),
PAD => MIO(48)
);
\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(49),
PAD => MIO(49)
);
\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(4),
PAD => MIO(4)
);
\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(50),
PAD => MIO(50)
);
\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(51),
PAD => MIO(51)
);
\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(52),
PAD => MIO(52)
);
\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(53),
PAD => MIO(53)
);
\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(5),
PAD => MIO(5)
);
\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(6),
PAD => MIO(6)
);
\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(7),
PAD => MIO(7)
);
\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(8),
PAD => MIO(8)
);
\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(9),
PAD => MIO(9)
);
\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(0),
PAD => DDR_BankAddr(0)
);
\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(1),
PAD => DDR_BankAddr(1)
);
\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(2),
PAD => DDR_BankAddr(2)
);
\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(0),
PAD => DDR_Addr(0)
);
\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(10),
PAD => DDR_Addr(10)
);
\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(11),
PAD => DDR_Addr(11)
);
\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(12),
PAD => DDR_Addr(12)
);
\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(13),
PAD => DDR_Addr(13)
);
\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(14),
PAD => DDR_Addr(14)
);
\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(1),
PAD => DDR_Addr(1)
);
\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(2),
PAD => DDR_Addr(2)
);
\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(3),
PAD => DDR_Addr(3)
);
\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(4),
PAD => DDR_Addr(4)
);
\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(5),
PAD => DDR_Addr(5)
);
\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(6),
PAD => DDR_Addr(6)
);
\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(7),
PAD => DDR_Addr(7)
);
\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(8),
PAD => DDR_Addr(8)
);
\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(9),
PAD => DDR_Addr(9)
);
\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(0),
PAD => DDR_DM(0)
);
\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(1),
PAD => DDR_DM(1)
);
\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(2),
PAD => DDR_DM(2)
);
\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(3),
PAD => DDR_DM(3)
);
\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(0),
PAD => DDR_DQ(0)
);
\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(10),
PAD => DDR_DQ(10)
);
\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(11),
PAD => DDR_DQ(11)
);
\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(12),
PAD => DDR_DQ(12)
);
\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(13),
PAD => DDR_DQ(13)
);
\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(14),
PAD => DDR_DQ(14)
);
\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(15),
PAD => DDR_DQ(15)
);
\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(16),
PAD => DDR_DQ(16)
);
\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(17),
PAD => DDR_DQ(17)
);
\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(18),
PAD => DDR_DQ(18)
);
\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(19),
PAD => DDR_DQ(19)
);
\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(1),
PAD => DDR_DQ(1)
);
\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(20),
PAD => DDR_DQ(20)
);
\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(21),
PAD => DDR_DQ(21)
);
\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(22),
PAD => DDR_DQ(22)
);
\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(23),
PAD => DDR_DQ(23)
);
\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(24),
PAD => DDR_DQ(24)
);
\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(25),
PAD => DDR_DQ(25)
);
\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(26),
PAD => DDR_DQ(26)
);
\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(27),
PAD => DDR_DQ(27)
);
\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(28),
PAD => DDR_DQ(28)
);
\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(29),
PAD => DDR_DQ(29)
);
\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(2),
PAD => DDR_DQ(2)
);
\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(30),
PAD => DDR_DQ(30)
);
\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(31),
PAD => DDR_DQ(31)
);
\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(3),
PAD => DDR_DQ(3)
);
\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(4),
PAD => DDR_DQ(4)
);
\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(5),
PAD => DDR_DQ(5)
);
\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(6),
PAD => DDR_DQ(6)
);
\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(7),
PAD => DDR_DQ(7)
);
\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(8),
PAD => DDR_DQ(8)
);
\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(9),
PAD => DDR_DQ(9)
);
\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(0),
PAD => DDR_DQS_n(0)
);
\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(1),
PAD => DDR_DQS_n(1)
);
\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(2),
PAD => DDR_DQS_n(2)
);
\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(3),
PAD => DDR_DQS_n(3)
);
\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(0),
PAD => DDR_DQS(0)
);
\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(1),
PAD => DDR_DQS(1)
);
\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(2),
PAD => DDR_DQS(2)
);
\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(3),
PAD => DDR_DQS(3)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[0]\
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(1)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(1)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(0)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(1)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(0)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(0)
);
i_16: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(1)
);
i_17: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(0)
);
i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(1)
);
i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(0)
);
i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(1)
);
i_21: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(0)
);
i_22: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(1)
);
i_23: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(0)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[7]\
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[6]\
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[5]\
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[4]\
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[3]\
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[2]\
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_processing_system7_0_0 is
port (
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_processing_system7_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_processing_system7_0_0 : entity is "system_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_processing_system7_0_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of system_processing_system7_0_0 : entity is "processing_system7_v5_5_processing_system7,Vivado 2016.4";
end system_processing_system7_0_0;
architecture STRUCTURE of system_processing_system7_0_0 is
signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of inst : label is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of inst : label is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of inst : label is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of inst : label is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of inst : label is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of inst : label is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of inst : label is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of inst : label is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 0;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 0;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of inst : label is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of inst : label is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of inst : label is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of inst : label is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of inst : label is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of inst : label is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of inst : label is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of inst : label is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of inst : label is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of inst : label is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "system_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
begin
inst: entity work.system_processing_system7_0_0_processing_system7_v5_5_processing_system7
port map (
CAN0_PHY_RX => '0',
CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED,
CAN1_PHY_RX => '0',
CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED,
Core0_nFIQ => '0',
Core0_nIRQ => '0',
Core1_nFIQ => '0',
Core1_nIRQ => '0',
DDR_ARB(3 downto 0) => B"0000",
DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0),
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM(3 downto 0) => DDR_DM(3 downto 0),
DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0),
DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0),
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_WEB => DDR_WEB,
DMA0_ACLK => '0',
DMA0_DAREADY => '0',
DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => '0',
DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1 downto 0) => B"00",
DMA0_DRVALID => '0',
DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED,
DMA1_ACLK => '0',
DMA1_DAREADY => '0',
DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0),
DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED,
DMA1_DRLAST => '0',
DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED,
DMA1_DRTYPE(1 downto 0) => B"00",
DMA1_DRVALID => '0',
DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED,
DMA2_ACLK => '0',
DMA2_DAREADY => '0',
DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => '0',
DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1 downto 0) => B"00",
DMA2_DRVALID => '0',
DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED,
DMA3_ACLK => '0',
DMA3_DAREADY => '0',
DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0),
DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED,
DMA3_DRLAST => '0',
DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED,
DMA3_DRTYPE(1 downto 0) => B"00",
DMA3_DRVALID => '0',
DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED,
ENET0_EXT_INTIN => '0',
ENET0_GMII_COL => '0',
ENET0_GMII_CRS => '0',
ENET0_GMII_RXD(7 downto 0) => B"00000000",
ENET0_GMII_RX_CLK => '0',
ENET0_GMII_RX_DV => '0',
ENET0_GMII_RX_ER => '0',
ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0),
ENET0_GMII_TX_CLK => '0',
ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED,
ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED,
ENET0_MDIO_I => '0',
ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED,
ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED,
ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED,
ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED,
ENET1_EXT_INTIN => '0',
ENET1_GMII_COL => '0',
ENET1_GMII_CRS => '0',
ENET1_GMII_RXD(7 downto 0) => B"00000000",
ENET1_GMII_RX_CLK => '0',
ENET1_GMII_RX_DV => '0',
ENET1_GMII_RX_ER => '0',
ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0),
ENET1_GMII_TX_CLK => '0',
ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED,
ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED,
ENET1_MDIO_I => '0',
ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED,
ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED,
ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED,
ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED,
ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED,
EVENT_EVENTI => '0',
EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
FCLK_CLK0 => FCLK_CLK0,
FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED,
FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED,
FCLK_CLKTRIG0_N => '0',
FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N,
FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,
FPGA_IDLE_N => '0',
FTMD_TRACEIN_ATID(3 downto 0) => B"0000",
FTMD_TRACEIN_CLK => '0',
FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000",
FTMD_TRACEIN_VALID => '0',
FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000",
FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED,
FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED,
FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED,
FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED,
FTMT_F2P_TRIG_0 => '0',
FTMT_F2P_TRIG_1 => '0',
FTMT_F2P_TRIG_2 => '0',
FTMT_F2P_TRIG_3 => '0',
FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0),
FTMT_P2F_TRIGACK_0 => '0',
FTMT_P2F_TRIGACK_1 => '0',
FTMT_P2F_TRIGACK_2 => '0',
FTMT_P2F_TRIGACK_3 => '0',
FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED,
FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED,
FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED,
FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED,
GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0),
GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0),
I2C0_SCL_I => '0',
I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED,
I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED,
I2C0_SDA_I => '0',
I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED,
I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED,
I2C1_SCL_I => '0',
I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => '0',
I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(0) => '0',
IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED,
IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED,
IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED,
IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED,
IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED,
IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED,
IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED,
IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED,
IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED,
IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED,
IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED,
IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED,
IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED,
IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED,
IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED,
IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED,
IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED,
IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED,
IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED,
IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED,
IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED,
IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED,
IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED,
IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED,
IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED,
IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED,
MIO(53 downto 0) => MIO(53 downto 0),
M_AXI_GP0_ACLK => M_AXI_GP0_ACLK,
M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED,
M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => M_AXI_GP0_WVALID,
M_AXI_GP1_ACLK => '0',
M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED,
M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARREADY => '0',
M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED,
M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWREADY => '0',
M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED,
M_AXI_GP1_BID(11 downto 0) => B"000000000000",
M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED,
M_AXI_GP1_BRESP(1 downto 0) => B"00",
M_AXI_GP1_BVALID => '0',
M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP1_RID(11 downto 0) => B"000000000000",
M_AXI_GP1_RLAST => '0',
M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED,
M_AXI_GP1_RRESP(1 downto 0) => B"00",
M_AXI_GP1_RVALID => '0',
M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0),
M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED,
M_AXI_GP1_WREADY => '0',
M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED,
PJTAG_TCK => '0',
PJTAG_TDI => '0',
PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED,
PJTAG_TMS => '0',
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED,
SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO0_CDN => '0',
SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED,
SDIO0_CLK_FB => '0',
SDIO0_CMD_I => '0',
SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED,
SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED,
SDIO0_DATA_I(3 downto 0) => B"0000",
SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0),
SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0),
SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED,
SDIO0_WP => '0',
SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED,
SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO1_CDN => '0',
SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED,
SDIO1_CLK_FB => '0',
SDIO1_CMD_I => '0',
SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED,
SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED,
SDIO1_DATA_I(3 downto 0) => B"0000",
SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0),
SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0),
SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED,
SDIO1_WP => '0',
SPI0_MISO_I => '0',
SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED,
SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED,
SPI0_MOSI_I => '0',
SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED,
SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED,
SPI0_SCLK_I => '0',
SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED,
SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED,
SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED,
SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED,
SPI0_SS_I => '0',
SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED,
SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED,
SPI1_MISO_I => '0',
SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED,
SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED,
SPI1_MOSI_I => '0',
SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED,
SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED,
SPI1_SCLK_I => '0',
SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED,
SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED,
SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED,
SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED,
SPI1_SS_I => '0',
SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED,
SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED,
SRAM_INTIN => '0',
S_AXI_ACP_ACLK => '0',
S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_ARBURST(1 downto 0) => B"00",
S_AXI_ACP_ARCACHE(3 downto 0) => B"0000",
S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED,
S_AXI_ACP_ARID(2 downto 0) => B"000",
S_AXI_ACP_ARLEN(3 downto 0) => B"0000",
S_AXI_ACP_ARLOCK(1 downto 0) => B"00",
S_AXI_ACP_ARPROT(2 downto 0) => B"000",
S_AXI_ACP_ARQOS(3 downto 0) => B"0000",
S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED,
S_AXI_ACP_ARSIZE(2 downto 0) => B"000",
S_AXI_ACP_ARUSER(4 downto 0) => B"00000",
S_AXI_ACP_ARVALID => '0',
S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_AWBURST(1 downto 0) => B"00",
S_AXI_ACP_AWCACHE(3 downto 0) => B"0000",
S_AXI_ACP_AWID(2 downto 0) => B"000",
S_AXI_ACP_AWLEN(3 downto 0) => B"0000",
S_AXI_ACP_AWLOCK(1 downto 0) => B"00",
S_AXI_ACP_AWPROT(2 downto 0) => B"000",
S_AXI_ACP_AWQOS(3 downto 0) => B"0000",
S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED,
S_AXI_ACP_AWSIZE(2 downto 0) => B"000",
S_AXI_ACP_AWUSER(4 downto 0) => B"00000",
S_AXI_ACP_AWVALID => '0',
S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0),
S_AXI_ACP_BREADY => '0',
S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED,
S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0),
S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0),
S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED,
S_AXI_ACP_RREADY => '0',
S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED,
S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_ACP_WID(2 downto 0) => B"000",
S_AXI_ACP_WLAST => '0',
S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED,
S_AXI_ACP_WSTRB(7 downto 0) => B"00000000",
S_AXI_ACP_WVALID => '0',
S_AXI_GP0_ACLK => '0',
S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_ARBURST(1 downto 0) => B"00",
S_AXI_GP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED,
S_AXI_GP0_ARID(5 downto 0) => B"000000",
S_AXI_GP0_ARLEN(3 downto 0) => B"0000",
S_AXI_GP0_ARLOCK(1 downto 0) => B"00",
S_AXI_GP0_ARPROT(2 downto 0) => B"000",
S_AXI_GP0_ARQOS(3 downto 0) => B"0000",
S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED,
S_AXI_GP0_ARSIZE(2 downto 0) => B"000",
S_AXI_GP0_ARVALID => '0',
S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_AWBURST(1 downto 0) => B"00",
S_AXI_GP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP0_AWID(5 downto 0) => B"000000",
S_AXI_GP0_AWLEN(3 downto 0) => B"0000",
S_AXI_GP0_AWLOCK(1 downto 0) => B"00",
S_AXI_GP0_AWPROT(2 downto 0) => B"000",
S_AXI_GP0_AWQOS(3 downto 0) => B"0000",
S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED,
S_AXI_GP0_AWSIZE(2 downto 0) => B"000",
S_AXI_GP0_AWVALID => '0',
S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0),
S_AXI_GP0_BREADY => '0',
S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED,
S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0),
S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED,
S_AXI_GP0_RREADY => '0',
S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED,
S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_WID(5 downto 0) => B"000000",
S_AXI_GP0_WLAST => '0',
S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED,
S_AXI_GP0_WSTRB(3 downto 0) => B"0000",
S_AXI_GP0_WVALID => '0',
S_AXI_GP1_ACLK => '0',
S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_ARBURST(1 downto 0) => B"00",
S_AXI_GP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED,
S_AXI_GP1_ARID(5 downto 0) => B"000000",
S_AXI_GP1_ARLEN(3 downto 0) => B"0000",
S_AXI_GP1_ARLOCK(1 downto 0) => B"00",
S_AXI_GP1_ARPROT(2 downto 0) => B"000",
S_AXI_GP1_ARQOS(3 downto 0) => B"0000",
S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED,
S_AXI_GP1_ARSIZE(2 downto 0) => B"000",
S_AXI_GP1_ARVALID => '0',
S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_AWBURST(1 downto 0) => B"00",
S_AXI_GP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP1_AWID(5 downto 0) => B"000000",
S_AXI_GP1_AWLEN(3 downto 0) => B"0000",
S_AXI_GP1_AWLOCK(1 downto 0) => B"00",
S_AXI_GP1_AWPROT(2 downto 0) => B"000",
S_AXI_GP1_AWQOS(3 downto 0) => B"0000",
S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED,
S_AXI_GP1_AWSIZE(2 downto 0) => B"000",
S_AXI_GP1_AWVALID => '0',
S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0),
S_AXI_GP1_BREADY => '0',
S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED,
S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0),
S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED,
S_AXI_GP1_RREADY => '0',
S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED,
S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_WID(5 downto 0) => B"000000",
S_AXI_GP1_WLAST => '0',
S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED,
S_AXI_GP1_WSTRB(3 downto 0) => B"0000",
S_AXI_GP1_WVALID => '0',
S_AXI_HP0_ACLK => '0',
S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_ARBURST(1 downto 0) => B"00",
S_AXI_HP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED,
S_AXI_HP0_ARID(5 downto 0) => B"000000",
S_AXI_HP0_ARLEN(3 downto 0) => B"0000",
S_AXI_HP0_ARLOCK(1 downto 0) => B"00",
S_AXI_HP0_ARPROT(2 downto 0) => B"000",
S_AXI_HP0_ARQOS(3 downto 0) => B"0000",
S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED,
S_AXI_HP0_ARSIZE(2 downto 0) => B"000",
S_AXI_HP0_ARVALID => '0',
S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_AWBURST(1 downto 0) => B"00",
S_AXI_HP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP0_AWID(5 downto 0) => B"000000",
S_AXI_HP0_AWLEN(3 downto 0) => B"0000",
S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
S_AXI_HP0_AWPROT(2 downto 0) => B"000",
S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED,
S_AXI_HP0_AWSIZE(2 downto 0) => B"000",
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED,
S_AXI_HP0_RREADY => '0',
S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP0_WID(5 downto 0) => B"000000",
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP0_WVALID => '0',
S_AXI_HP1_ACLK => '0',
S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_ARBURST(1 downto 0) => B"00",
S_AXI_HP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED,
S_AXI_HP1_ARID(5 downto 0) => B"000000",
S_AXI_HP1_ARLEN(3 downto 0) => B"0000",
S_AXI_HP1_ARLOCK(1 downto 0) => B"00",
S_AXI_HP1_ARPROT(2 downto 0) => B"000",
S_AXI_HP1_ARQOS(3 downto 0) => B"0000",
S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED,
S_AXI_HP1_ARSIZE(2 downto 0) => B"000",
S_AXI_HP1_ARVALID => '0',
S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_AWBURST(1 downto 0) => B"00",
S_AXI_HP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP1_AWID(5 downto 0) => B"000000",
S_AXI_HP1_AWLEN(3 downto 0) => B"0000",
S_AXI_HP1_AWLOCK(1 downto 0) => B"00",
S_AXI_HP1_AWPROT(2 downto 0) => B"000",
S_AXI_HP1_AWQOS(3 downto 0) => B"0000",
S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED,
S_AXI_HP1_AWSIZE(2 downto 0) => B"000",
S_AXI_HP1_AWVALID => '0',
S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0),
S_AXI_HP1_BREADY => '0',
S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED,
S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP1_RDISSUECAP1_EN => '0',
S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0),
S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED,
S_AXI_HP1_RREADY => '0',
S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED,
S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP1_WID(5 downto 0) => B"000000",
S_AXI_HP1_WLAST => '0',
S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED,
S_AXI_HP1_WRISSUECAP1_EN => '0',
S_AXI_HP1_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP1_WVALID => '0',
S_AXI_HP2_ACLK => '0',
S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_ARBURST(1 downto 0) => B"00",
S_AXI_HP2_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED,
S_AXI_HP2_ARID(5 downto 0) => B"000000",
S_AXI_HP2_ARLEN(3 downto 0) => B"0000",
S_AXI_HP2_ARLOCK(1 downto 0) => B"00",
S_AXI_HP2_ARPROT(2 downto 0) => B"000",
S_AXI_HP2_ARQOS(3 downto 0) => B"0000",
S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED,
S_AXI_HP2_ARSIZE(2 downto 0) => B"000",
S_AXI_HP2_ARVALID => '0',
S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_AWBURST(1 downto 0) => B"00",
S_AXI_HP2_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP2_AWID(5 downto 0) => B"000000",
S_AXI_HP2_AWLEN(3 downto 0) => B"0000",
S_AXI_HP2_AWLOCK(1 downto 0) => B"00",
S_AXI_HP2_AWPROT(2 downto 0) => B"000",
S_AXI_HP2_AWQOS(3 downto 0) => B"0000",
S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED,
S_AXI_HP2_AWSIZE(2 downto 0) => B"000",
S_AXI_HP2_AWVALID => '0',
S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0),
S_AXI_HP2_BREADY => '0',
S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED,
S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP2_RDISSUECAP1_EN => '0',
S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0),
S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED,
S_AXI_HP2_RREADY => '0',
S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED,
S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP2_WID(5 downto 0) => B"000000",
S_AXI_HP2_WLAST => '0',
S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED,
S_AXI_HP2_WRISSUECAP1_EN => '0',
S_AXI_HP2_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP2_WVALID => '0',
S_AXI_HP3_ACLK => '0',
S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_ARBURST(1 downto 0) => B"00",
S_AXI_HP3_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED,
S_AXI_HP3_ARID(5 downto 0) => B"000000",
S_AXI_HP3_ARLEN(3 downto 0) => B"0000",
S_AXI_HP3_ARLOCK(1 downto 0) => B"00",
S_AXI_HP3_ARPROT(2 downto 0) => B"000",
S_AXI_HP3_ARQOS(3 downto 0) => B"0000",
S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED,
S_AXI_HP3_ARSIZE(2 downto 0) => B"000",
S_AXI_HP3_ARVALID => '0',
S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_AWBURST(1 downto 0) => B"00",
S_AXI_HP3_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP3_AWID(5 downto 0) => B"000000",
S_AXI_HP3_AWLEN(3 downto 0) => B"0000",
S_AXI_HP3_AWLOCK(1 downto 0) => B"00",
S_AXI_HP3_AWPROT(2 downto 0) => B"000",
S_AXI_HP3_AWQOS(3 downto 0) => B"0000",
S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED,
S_AXI_HP3_AWSIZE(2 downto 0) => B"000",
S_AXI_HP3_AWVALID => '0',
S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0),
S_AXI_HP3_BREADY => '0',
S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED,
S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP3_RDISSUECAP1_EN => '0',
S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0),
S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED,
S_AXI_HP3_RREADY => '0',
S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED,
S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP3_WID(5 downto 0) => B"000000",
S_AXI_HP3_WLAST => '0',
S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED,
S_AXI_HP3_WRISSUECAP1_EN => '0',
S_AXI_HP3_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP3_WVALID => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED,
TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0),
TTC0_CLK0_IN => '0',
TTC0_CLK1_IN => '0',
TTC0_CLK2_IN => '0',
TTC0_WAVE0_OUT => TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT => TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT => TTC0_WAVE2_OUT,
TTC1_CLK0_IN => '0',
TTC1_CLK1_IN => '0',
TTC1_CLK2_IN => '0',
TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED,
TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED,
TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED,
UART0_CTSN => '0',
UART0_DCDN => '0',
UART0_DSRN => '0',
UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED,
UART0_RIN => '0',
UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED,
UART0_RX => '1',
UART0_TX => NLW_inst_UART0_TX_UNCONNECTED,
UART1_CTSN => '0',
UART1_DCDN => '0',
UART1_DSRN => '0',
UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED,
UART1_RIN => '0',
UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED,
UART1_RX => '1',
UART1_TX => NLW_inst_UART1_TX_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT,
USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB1_VBUS_PWRFAULT => '0',
USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED,
WDT_CLK_IN => '0',
WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED
);
end STRUCTURE;
| mit | ce86a3711c8789f49bae1897324be7cb | 0.633922 | 2.760163 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/ov7670_controller/ov7670_controller.srcs/sources_1/imports/new/ov7670_registers.vhd | 6 | 5,235 | -- Company:
-- Engineer: Mike Field <[email protected]>
--
-- Description: Register settings for the OV7670 Camera (partially from OV7670.c
-- in the Linux Kernel
-- Edited by : Christopher Wilson <[email protected]>
------------------------------------------------------------------------------------
--
-- Notes:
-- 1) Regarding the WITH SELECT Statement:
-- WITH sreg(sel) SELECT
-- finished <= '1' when x"FFFF",
-- '0' when others;
-- This means the transfer is finished the first time sreg ends up as "FFFF",
-- I.E. Need Sequential Addresses in the below case statements
--
-- Common Debug Issues:
--
-- Red Appearing as Green / Green Appearing as Pink
-- Solution: Register Corrections Below
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ov7670_registers is
port(
clk: in std_logic;
resend: in std_logic;
advance: in std_logic;
command: out std_logic_vector(15 downto 0);
finished: out std_logic
);
end ov7670_registers;
architecture Structural of ov7670_registers is
signal sreg : std_logic_vector(15 downto 0);
signal address : std_logic_vector(7 downto 0) := (others => '0');
begin
command <= sreg;
with sreg select finished <= '1' when x"FFFF", '0' when others;
process(clk)
begin
if rising_edge(clk) then
if resend = '1' then
address <= (others => '0');
elsif advance = '1' then
address <= std_logic_vector(unsigned(address)+1);
end if;
case address is
when x"00" => sreg <= x"1280"; -- COM7 Reset
when x"01" => sreg <= x"1280"; -- COM7 Reset
when x"02" => sreg <= x"1204"; -- COM7 Size & RGB output
when x"03" => sreg <= x"1100"; -- CLKRC Prescaler - Fin/(1+1)
when x"04" => sreg <= x"0C00"; -- COM3 Lots of stuff, enable scaling, all others off
when x"05" => sreg <= x"3E00"; -- COM14 PCLK scaling off
when x"06" => sreg <= x"8C00"; -- RGB444 Set RGB format
when x"07" => sreg <= x"0400"; -- COM1 no CCIR601
when x"08" => sreg <= x"4010"; -- COM15 Full 0-255 output, RGB 565
when x"09" => sreg <= x"3a04"; -- TSLB Set UV ordering, do not auto-reset window
when x"0A" => sreg <= x"1438"; -- COM9 - AGC Celling
when x"0B" => sreg <= x"4f40"; --x"4fb3"; -- MTX1 - colour conversion matrix
when x"0C" => sreg <= x"5034"; --x"50b3"; -- MTX2 - colour conversion matrix
when x"0D" => sreg <= x"510C"; --x"5100"; -- MTX3 - colour conversion matrix
when x"0E" => sreg <= x"5217"; --x"523d"; -- MTX4 - colour conversion matrix
when x"0F" => sreg <= x"5329"; --x"53a7"; -- MTX5 - colour conversion matrix
when x"10" => sreg <= x"5440"; --x"54e4"; -- MTX6 - colour conversion matrix
when x"11" => sreg <= x"581e"; --x"589e"; -- MTXS - Matrix sign and auto contrast
when x"12" => sreg <= x"3dc0"; -- COM13 - Turn on GAMMA and UV Auto adjust
when x"13" => sreg <= x"1100"; -- CLKRC Enable double clock Prescaler - Fin/(1+1)
when x"14" => sreg <= x"1711"; -- HSTART HREF start (high 8 bits)
when x"15" => sreg <= x"1861"; -- HSTOP HREF stop (high 8 bits)
when x"16" => sreg <= x"32A4"; -- HREF Edge offset and low 3 bits of HSTART and HSTOP
when x"17" => sreg <= x"1903"; -- VSTART VSYNC start (high 8 bits)
when x"18" => sreg <= x"1A7b"; -- VSTOP VSYNC stop (high 8 bits)
when x"19" => sreg <= x"030a"; -- VREF VSYNC low two bits
when x"1A" => sreg <= x"0e61"; -- COM5(0x0E) 0x61
when x"1B" => sreg <= x"0f4b"; -- COM6(0x0F) 0x4B
when x"1C" => sreg <= x"1602"; --
when x"1D" => sreg <= x"1e37"; -- MVFP (0x1E) 0x07 -- FLIP AND MIRROR IMAGE 0x3x
when x"1E" => sreg <= x"2102";
when x"1F" => sreg <= x"2291";
when x"20" => sreg <= x"2907";
when x"21" => sreg <= x"330b";
when x"22" => sreg <= x"350b";
when x"23" => sreg <= x"371d";
when x"24" => sreg <= x"3871";
when x"25" => sreg <= x"392a";
when x"26" => sreg <= x"3c78"; -- COM12 (0x3C) 0x78
when x"27" => sreg <= x"4d40";
when x"28" => sreg <= x"4e20";
when x"29" => sreg <= x"6900"; -- GFIX (0x69) 0x00
when x"2A" => sreg <= x"6b4a";
when x"2B" => sreg <= x"7410";
when x"2C" => sreg <= x"8d4f";
when x"2D" => sreg <= x"8e00";
when x"2E" => sreg <= x"8f00";
when x"2F" => sreg <= x"9000";
when x"30" => sreg <= x"9100";
when x"31" => sreg <= x"9600";
when x"32" => sreg <= x"9a00";
when x"33" => sreg <= x"b084";
when x"34" => sreg <= x"b10c";
when x"35" => sreg <= x"b20e";
when x"36" => sreg <= x"b382";
when x"37" => sreg <= x"b80a";
when others => sreg <= x"ffff";
end case;
end if;
end process;
end Structural; | mit | df15010ba893b34f9f0ed3ad2fda56a0 | 0.503534 | 3.255597 | false | false | false | false |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/niosii_system_nios2_qsys_0_data_master_translator.vhd | 1 | 13,923 | -- niosii_system_nios2_qsys_0_data_master_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:31
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_nios2_qsys_0_data_master_translator is
generic (
AV_ADDRESS_W : integer := 25;
AV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 25;
UAV_BURSTCOUNT_W : integer := 3;
USE_READ : integer := 1;
USE_WRITE : integer := 1;
USE_BEGINBURSTTRANSFER : integer := 0;
USE_BEGINTRANSFER : integer := 0;
USE_CHIPSELECT : integer := 0;
USE_BURSTCOUNT : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 1;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 1;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_LINEWRAPBURSTS : integer := 0;
AV_REGISTERINCOMINGSIGNALS : integer := 1
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : out std_logic_vector(24 downto 0); -- avalon_universal_master_0.address
uav_burstcount : out std_logic_vector(2 downto 0); -- .burstcount
uav_read : out std_logic; -- .read
uav_write : out std_logic; -- .write
uav_waitrequest : in std_logic := '0'; -- .waitrequest
uav_readdatavalid : in std_logic := '0'; -- .readdatavalid
uav_byteenable : out std_logic_vector(3 downto 0); -- .byteenable
uav_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
uav_writedata : out std_logic_vector(31 downto 0); -- .writedata
uav_lock : out std_logic; -- .lock
uav_debugaccess : out std_logic; -- .debugaccess
av_address : in std_logic_vector(24 downto 0) := (others => '0'); -- avalon_anti_master_0.address
av_waitrequest : out std_logic; -- .waitrequest
av_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
av_read : in std_logic := '0'; -- .read
av_readdata : out std_logic_vector(31 downto 0); -- .readdata
av_write : in std_logic := '0'; -- .write
av_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
av_debugaccess : in std_logic := '0'; -- .debugaccess
av_beginbursttransfer : in std_logic := '0';
av_begintransfer : in std_logic := '0';
av_burstcount : in std_logic_vector(0 downto 0) := (others => '0');
av_chipselect : in std_logic := '0';
av_clken : in std_logic := '0';
av_lock : in std_logic := '0';
av_readdatavalid : out std_logic;
av_response : out std_logic_vector(1 downto 0);
av_writeresponserequest : in std_logic := '0';
av_writeresponsevalid : out std_logic;
uav_clken : out std_logic;
uav_response : in std_logic_vector(1 downto 0) := (others => '0');
uav_writeresponserequest : out std_logic;
uav_writeresponsevalid : in std_logic := '0'
);
end entity niosii_system_nios2_qsys_0_data_master_translator;
architecture rtl of niosii_system_nios2_qsys_0_data_master_translator is
component altera_merlin_master_translator is
generic (
AV_ADDRESS_W : integer := 32;
AV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 38;
UAV_BURSTCOUNT_W : integer := 10;
USE_READ : integer := 1;
USE_WRITE : integer := 1;
USE_BEGINBURSTTRANSFER : integer := 0;
USE_BEGINTRANSFER : integer := 0;
USE_CHIPSELECT : integer := 0;
USE_BURSTCOUNT : integer := 1;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_LINEWRAPBURSTS : integer := 0;
AV_REGISTERINCOMINGSIGNALS : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : out std_logic_vector(24 downto 0); -- address
uav_burstcount : out std_logic_vector(2 downto 0); -- burstcount
uav_read : out std_logic; -- read
uav_write : out std_logic; -- write
uav_waitrequest : in std_logic := 'X'; -- waitrequest
uav_readdatavalid : in std_logic := 'X'; -- readdatavalid
uav_byteenable : out std_logic_vector(3 downto 0); -- byteenable
uav_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
uav_writedata : out std_logic_vector(31 downto 0); -- writedata
uav_lock : out std_logic; -- lock
uav_debugaccess : out std_logic; -- debugaccess
av_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
av_waitrequest : out std_logic; -- waitrequest
av_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
av_read : in std_logic := 'X'; -- read
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_write : in std_logic := 'X'; -- write
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_debugaccess : in std_logic := 'X'; -- debugaccess
av_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount
av_beginbursttransfer : in std_logic := 'X'; -- beginbursttransfer
av_begintransfer : in std_logic := 'X'; -- begintransfer
av_chipselect : in std_logic := 'X'; -- chipselect
av_readdatavalid : out std_logic; -- readdatavalid
av_lock : in std_logic := 'X'; -- lock
uav_clken : out std_logic; -- clken
av_clken : in std_logic := 'X'; -- clken
uav_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
av_response : out std_logic_vector(1 downto 0); -- response
uav_writeresponserequest : out std_logic; -- writeresponserequest
uav_writeresponsevalid : in std_logic := 'X'; -- writeresponsevalid
av_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
av_writeresponsevalid : out std_logic -- writeresponsevalid
);
end component altera_merlin_master_translator;
begin
nios2_qsys_0_data_master_translator : component altera_merlin_master_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
USE_READ => USE_READ,
USE_WRITE => USE_WRITE,
USE_BEGINBURSTTRANSFER => USE_BEGINBURSTTRANSFER,
USE_BEGINTRANSFER => USE_BEGINTRANSFER,
USE_CHIPSELECT => USE_CHIPSELECT,
USE_BURSTCOUNT => USE_BURSTCOUNT,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_LINEWRAPBURSTS => AV_LINEWRAPBURSTS,
AV_REGISTERINCOMINGSIGNALS => AV_REGISTERINCOMINGSIGNALS
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_master_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_master_0.address
av_waitrequest => av_waitrequest, -- .waitrequest
av_byteenable => av_byteenable, -- .byteenable
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_write => av_write, -- .write
av_writedata => av_writedata, -- .writedata
av_debugaccess => av_debugaccess, -- .debugaccess
av_burstcount => "1", -- (terminated)
av_beginbursttransfer => '0', -- (terminated)
av_begintransfer => '0', -- (terminated)
av_chipselect => '0', -- (terminated)
av_readdatavalid => open, -- (terminated)
av_lock => '0', -- (terminated)
uav_clken => open, -- (terminated)
av_clken => '1', -- (terminated)
uav_response => "00", -- (terminated)
av_response => open, -- (terminated)
uav_writeresponserequest => open, -- (terminated)
uav_writeresponsevalid => '0', -- (terminated)
av_writeresponserequest => '0', -- (terminated)
av_writeresponsevalid => open -- (terminated)
);
end architecture rtl; -- of niosii_system_nios2_qsys_0_data_master_translator
| apache-2.0 | 7365d10139965c9eb6dbd857545e916a | 0.423903 | 4.376925 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_util_vector_logic_1_0/synth/system_util_vector_logic_1_0.vhd | 1 | 4,124 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:util_vector_logic:2.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY util_vector_logic_v2_0;
USE util_vector_logic_v2_0.util_vector_logic;
ENTITY system_util_vector_logic_1_0 IS
PORT (
Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END system_util_vector_logic_1_0;
ARCHITECTURE system_util_vector_logic_1_0_arch OF system_util_vector_logic_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_util_vector_logic_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT util_vector_logic IS
GENERIC (
C_OPERATION : STRING;
C_SIZE : INTEGER
);
PORT (
Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT util_vector_logic;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_util_vector_logic_1_0_arch: ARCHITECTURE IS "util_vector_logic,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_util_vector_logic_1_0_arch : ARCHITECTURE IS "system_util_vector_logic_1_0,util_vector_logic,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_util_vector_logic_1_0_arch: ARCHITECTURE IS "system_util_vector_logic_1_0,util_vector_logic,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=util_vector_logic,x_ipVersion=2.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_OPERATION=or,C_SIZE=1}";
BEGIN
U0 : util_vector_logic
GENERIC MAP (
C_OPERATION => "or",
C_SIZE => 1
)
PORT MAP (
Op1 => Op1,
Op2 => Op2,
Res => Res
);
END system_util_vector_logic_1_0_arch;
| mit | f7fc375d9e11eb1b1004dbce7bd6a623 | 0.734239 | 3.773102 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_xbar_0/system_xbar_0_sim_netlist.vhdl | 1 | 478,467 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed May 31 20:14:25 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_xbar_0/system_xbar_0_sim_netlist.vhdl
-- Design : system_xbar_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_crossbar_v2_1_12_addr_arbiter is
port (
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
next_enc : out STD_LOGIC_VECTOR ( 0 to 0 );
aa_mi_arvalid : out STD_LOGIC;
\gen_axi.s_axi_rid_i_reg[0]\ : out STD_LOGIC;
\m_axi_arqos[3]\ : out STD_LOGIC_VECTOR ( 57 downto 0 );
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : out STD_LOGIC;
\gen_single_thread.active_target_hot_reg[0]\ : out STD_LOGIC;
\s_axi_arready[0]\ : out STD_LOGIC;
\gen_single_thread.active_target_enc_reg[0]\ : out STD_LOGIC;
\gen_single_thread.active_target_hot_reg[0]_0\ : out STD_LOGIC;
\s_axi_arready[1]\ : out STD_LOGIC;
\gen_single_thread.active_target_enc_reg[0]_0\ : out STD_LOGIC;
sel_4 : out STD_LOGIC;
\gen_arbiter.last_rr_hot_reg[0]_0\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
sel_4_0 : out STD_LOGIC;
\gen_arbiter.qual_reg_reg[1]_0\ : out STD_LOGIC;
\gen_axi.s_axi_rlast_i_reg\ : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
mi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_11_in : in STD_LOGIC;
p_16_in : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].r_issuing_cnt_reg[2]\ : in STD_LOGIC;
st_aa_arvalid_qual : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_valid_i_reg : in STD_LOGIC;
r_issuing_cnt : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
active_target_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
active_target_enc : in STD_LOGIC;
active_target_hot_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
active_target_enc_2 : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]_0\ : in STD_LOGIC;
\valid_qual_i3__1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg_0 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 15 downto 0 );
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_master_slots[0].r_issuing_cnt_reg[2]_0\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_crossbar_v2_1_12_addr_arbiter : entity is "axi_crossbar_v2_1_12_addr_arbiter";
end system_xbar_0_axi_crossbar_v2_1_12_addr_arbiter;
architecture STRUCTURE of system_xbar_0_axi_crossbar_v2_1_12_addr_arbiter is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^aa_mi_arvalid\ : STD_LOGIC;
signal \gen_arbiter.any_grant_i_1__0_n_0\ : STD_LOGIC;
signal \gen_arbiter.any_grant_reg_n_0\ : STD_LOGIC;
signal \gen_arbiter.grant_hot[0]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_arbiter.grant_hot[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_arbiter.grant_hot[1]_i_4_n_0\ : STD_LOGIC;
signal \gen_arbiter.grant_hot_reg_n_0_[0]\ : STD_LOGIC;
signal \gen_arbiter.grant_hot_reg_n_0_[1]\ : STD_LOGIC;
signal \gen_arbiter.last_rr_hot[0]_i_2_n_0\ : STD_LOGIC;
signal \gen_arbiter.last_rr_hot[0]_i_3_n_0\ : STD_LOGIC;
signal \gen_arbiter.last_rr_hot[2]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_arbiter.last_rr_hot[2]_i_3_n_0\ : STD_LOGIC;
signal \^gen_arbiter.last_rr_hot_reg[0]_0\ : STD_LOGIC;
signal \gen_arbiter.last_rr_hot_reg_n_0_[0]\ : STD_LOGIC;
signal \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\ : STD_LOGIC;
signal \gen_arbiter.m_valid_i_i_1__0_n_0\ : STD_LOGIC;
signal \gen_arbiter.s_ready_i[0]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_arbiter.s_ready_i[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_4_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].r_issuing_cnt[3]_i_3_n_0\ : STD_LOGIC;
signal grant_hot : STD_LOGIC;
signal \^m_axi_arqos[3]\ : STD_LOGIC_VECTOR ( 57 downto 0 );
signal m_mesg_mux : STD_LOGIC_VECTOR ( 63 downto 2 );
signal m_target_hot_mux : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^next_enc\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_1_in : STD_LOGIC;
signal p_5_in : STD_LOGIC;
signal qual_reg : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_arready[0]\ : STD_LOGIC;
signal \^s_axi_arready[1]\ : STD_LOGIC;
signal \^sel_4\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_arbiter.last_rr_hot[0]_i_1__0\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gen_arbiter.last_rr_hot[2]_i_2__0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gen_arbiter.m_grant_enc_i[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[10]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[11]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[12]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[13]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[14]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[15]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[16]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[17]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[18]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[19]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[20]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[21]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[22]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[23]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[24]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[25]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[26]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[27]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[28]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[29]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[30]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[31]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[32]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[33]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[34]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[35]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[36]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[37]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[38]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[39]_i_1__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[3]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[40]_i_1__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[41]_i_1__0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[42]_i_1__0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[43]_i_1__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[44]_i_1__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[45]_i_1__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[47]_i_1__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[48]_i_1__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[49]_i_1__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[4]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[54]_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[55]_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[56]_i_1__0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[57]_i_1__0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[58]_i_1__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[59]_i_1__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[5]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[60]_i_1__0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[61]_i_1__0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[62]_i_1__0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[63]_i_1__0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[6]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[7]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[8]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[9]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \gen_arbiter.m_target_hot_i[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gen_arbiter.m_target_hot_i[1]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gen_arbiter.m_target_hot_i[1]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gen_arbiter.qual_reg[1]_i_4\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gen_arbiter.s_ready_i[0]_i_1__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gen_arbiter.s_ready_i[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gen_single_thread.active_target_enc[0]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gen_single_thread.active_target_hot[0]_i_1__2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_axi_arvalid[0]_INST_0\ : label is "soft_lutpair5";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
SR(0) <= \^sr\(0);
aa_mi_arvalid <= \^aa_mi_arvalid\;
\gen_arbiter.last_rr_hot_reg[0]_0\ <= \^gen_arbiter.last_rr_hot_reg[0]_0\;
\m_axi_arqos[3]\(57 downto 0) <= \^m_axi_arqos[3]\(57 downto 0);
next_enc(0) <= \^next_enc\(0);
\s_axi_arready[0]\ <= \^s_axi_arready[0]\;
\s_axi_arready[1]\ <= \^s_axi_arready[1]\;
sel_4 <= \^sel_4\;
\gen_arbiter.any_grant_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FEEEAAAA"
)
port map (
I0 => \gen_arbiter.any_grant_reg_n_0\,
I1 => \gen_master_slots[0].r_issuing_cnt_reg[2]\,
I2 => st_aa_arvalid_qual(0),
I3 => \gen_arbiter.last_rr_hot[2]_i_3_n_0\,
I4 => \gen_arbiter.last_rr_hot[2]_i_2__0_n_0\,
I5 => \gen_arbiter.grant_hot[1]_i_4_n_0\,
O => \gen_arbiter.any_grant_i_1__0_n_0\
);
\gen_arbiter.any_grant_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_arbiter.any_grant_i_1__0_n_0\,
Q => \gen_arbiter.any_grant_reg_n_0\,
R => '0'
);
\gen_arbiter.grant_hot[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FEAA02AA"
)
port map (
I0 => \gen_arbiter.grant_hot_reg_n_0_[0]\,
I1 => \gen_master_slots[0].r_issuing_cnt_reg[2]\,
I2 => \gen_master_slots[0].r_issuing_cnt_reg[2]_0\,
I3 => \gen_arbiter.last_rr_hot[2]_i_2__0_n_0\,
I4 => \^gen_arbiter.last_rr_hot_reg[0]_0\,
I5 => \gen_arbiter.grant_hot[1]_i_4_n_0\,
O => \gen_arbiter.grant_hot[0]_i_1__0_n_0\
);
\gen_arbiter.grant_hot[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FEAA02AA"
)
port map (
I0 => \gen_arbiter.grant_hot_reg_n_0_[1]\,
I1 => \gen_master_slots[0].r_issuing_cnt_reg[2]\,
I2 => \gen_master_slots[0].r_issuing_cnt_reg[2]_0\,
I3 => \gen_arbiter.last_rr_hot[2]_i_2__0_n_0\,
I4 => \^next_enc\(0),
I5 => \gen_arbiter.grant_hot[1]_i_4_n_0\,
O => \gen_arbiter.grant_hot[1]_i_1_n_0\
);
\gen_arbiter.grant_hot[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFD5D5D555555555"
)
port map (
I0 => aresetn_d,
I1 => \^q\(1),
I2 => mi_arready(0),
I3 => m_axi_arready(0),
I4 => \^q\(0),
I5 => \^aa_mi_arvalid\,
O => \gen_arbiter.grant_hot[1]_i_4_n_0\
);
\gen_arbiter.grant_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_arbiter.grant_hot[0]_i_1__0_n_0\,
Q => \gen_arbiter.grant_hot_reg_n_0_[0]\,
R => '0'
);
\gen_arbiter.grant_hot_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_arbiter.grant_hot[1]_i_1_n_0\,
Q => \gen_arbiter.grant_hot_reg_n_0_[1]\,
R => '0'
);
\gen_arbiter.last_rr_hot[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0F0F080"
)
port map (
I0 => \gen_arbiter.last_rr_hot[0]_i_2_n_0\,
I1 => \gen_arbiter.last_rr_hot_reg_n_0_[0]\,
I2 => \gen_arbiter.last_rr_hot[0]_i_3_n_0\,
I3 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I4 => p_5_in,
O => \^gen_arbiter.last_rr_hot_reg[0]_0\
);
\gen_arbiter.last_rr_hot[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"F7"
)
port map (
I0 => s_axi_arvalid(1),
I1 => qual_reg(1),
I2 => \^s_axi_arready[1]\,
O => \gen_arbiter.last_rr_hot[0]_i_2_n_0\
);
\gen_arbiter.last_rr_hot[0]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_arvalid(0),
I1 => qual_reg(0),
I2 => \^s_axi_arready[0]\,
O => \gen_arbiter.last_rr_hot[0]_i_3_n_0\
);
\gen_arbiter.last_rr_hot[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA80808080808080"
)
port map (
I0 => \gen_arbiter.last_rr_hot[2]_i_2__0_n_0\,
I1 => \gen_arbiter.last_rr_hot[2]_i_3_n_0\,
I2 => st_aa_arvalid_qual(0),
I3 => \gen_master_slots[1].r_issuing_cnt_reg[8]_0\,
I4 => \^next_enc\(0),
I5 => st_aa_arvalid_qual(1),
O => grant_hot
);
\gen_arbiter.last_rr_hot[2]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"1110"
)
port map (
I0 => \^aa_mi_arvalid\,
I1 => \gen_arbiter.any_grant_reg_n_0\,
I2 => \^gen_arbiter.last_rr_hot_reg[0]_0\,
I3 => \^next_enc\(0),
O => \gen_arbiter.last_rr_hot[2]_i_2__0_n_0\
);
\gen_arbiter.last_rr_hot[2]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA200A2"
)
port map (
I0 => \^gen_arbiter.last_rr_hot_reg[0]_0\,
I1 => r_issuing_cnt(4),
I2 => m_valid_i_reg,
I3 => \^sel_4\,
I4 => \valid_qual_i3__1\(0),
O => \gen_arbiter.last_rr_hot[2]_i_3_n_0\
);
\gen_arbiter.last_rr_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => grant_hot,
D => \^gen_arbiter.last_rr_hot_reg[0]_0\,
Q => \gen_arbiter.last_rr_hot_reg_n_0_[0]\,
R => \^sr\(0)
);
\gen_arbiter.last_rr_hot_reg[2]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => grant_hot,
D => '0',
Q => p_5_in,
S => \^sr\(0)
);
\gen_arbiter.m_grant_enc_i[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00FF000E"
)
port map (
I0 => p_5_in,
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => \gen_arbiter.last_rr_hot[0]_i_3_n_0\,
I3 => \gen_arbiter.last_rr_hot[0]_i_2_n_0\,
I4 => \gen_arbiter.last_rr_hot_reg_n_0_[0]\,
O => \^next_enc\(0)
);
\gen_arbiter.m_grant_enc_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => grant_hot,
D => \^next_enc\(0),
Q => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^aa_mi_arvalid\,
O => p_1_in
);
\gen_arbiter.m_mesg_i[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(40),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(8),
O => m_mesg_mux(10)
);
\gen_arbiter.m_mesg_i[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(41),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(9),
O => m_mesg_mux(11)
);
\gen_arbiter.m_mesg_i[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(42),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(10),
O => m_mesg_mux(12)
);
\gen_arbiter.m_mesg_i[13]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(43),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(11),
O => m_mesg_mux(13)
);
\gen_arbiter.m_mesg_i[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(44),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(12),
O => m_mesg_mux(14)
);
\gen_arbiter.m_mesg_i[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(45),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(13),
O => m_mesg_mux(15)
);
\gen_arbiter.m_mesg_i[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(46),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(14),
O => m_mesg_mux(16)
);
\gen_arbiter.m_mesg_i[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(47),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(15),
O => m_mesg_mux(17)
);
\gen_arbiter.m_mesg_i[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(48),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(16),
O => m_mesg_mux(18)
);
\gen_arbiter.m_mesg_i[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(49),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(17),
O => m_mesg_mux(19)
);
\gen_arbiter.m_mesg_i[1]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn_d,
O => \^sr\(0)
);
\gen_arbiter.m_mesg_i[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(50),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(18),
O => m_mesg_mux(20)
);
\gen_arbiter.m_mesg_i[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(51),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(19),
O => m_mesg_mux(21)
);
\gen_arbiter.m_mesg_i[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(52),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(20),
O => m_mesg_mux(22)
);
\gen_arbiter.m_mesg_i[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(53),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(21),
O => m_mesg_mux(23)
);
\gen_arbiter.m_mesg_i[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(54),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(22),
O => m_mesg_mux(24)
);
\gen_arbiter.m_mesg_i[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(55),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(23),
O => m_mesg_mux(25)
);
\gen_arbiter.m_mesg_i[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(56),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(24),
O => m_mesg_mux(26)
);
\gen_arbiter.m_mesg_i[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(57),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(25),
O => m_mesg_mux(27)
);
\gen_arbiter.m_mesg_i[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(58),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(26),
O => m_mesg_mux(28)
);
\gen_arbiter.m_mesg_i[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(59),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(27),
O => m_mesg_mux(29)
);
\gen_arbiter.m_mesg_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(32),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(0),
O => m_mesg_mux(2)
);
\gen_arbiter.m_mesg_i[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(60),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(28),
O => m_mesg_mux(30)
);
\gen_arbiter.m_mesg_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(61),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(29),
O => m_mesg_mux(31)
);
\gen_arbiter.m_mesg_i[32]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(62),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(30),
O => m_mesg_mux(32)
);
\gen_arbiter.m_mesg_i[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(63),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(31),
O => m_mesg_mux(33)
);
\gen_arbiter.m_mesg_i[34]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(8),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arlen(0),
O => m_mesg_mux(34)
);
\gen_arbiter.m_mesg_i[35]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(9),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arlen(1),
O => m_mesg_mux(35)
);
\gen_arbiter.m_mesg_i[36]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(10),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arlen(2),
O => m_mesg_mux(36)
);
\gen_arbiter.m_mesg_i[37]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(11),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arlen(3),
O => m_mesg_mux(37)
);
\gen_arbiter.m_mesg_i[38]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(12),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arlen(4),
O => m_mesg_mux(38)
);
\gen_arbiter.m_mesg_i[39]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(13),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arlen(5),
O => m_mesg_mux(39)
);
\gen_arbiter.m_mesg_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(33),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(1),
O => m_mesg_mux(3)
);
\gen_arbiter.m_mesg_i[40]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(14),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arlen(6),
O => m_mesg_mux(40)
);
\gen_arbiter.m_mesg_i[41]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(15),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arlen(7),
O => m_mesg_mux(41)
);
\gen_arbiter.m_mesg_i[42]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(3),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arsize(0),
O => m_mesg_mux(42)
);
\gen_arbiter.m_mesg_i[43]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(4),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arsize(1),
O => m_mesg_mux(43)
);
\gen_arbiter.m_mesg_i[44]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(5),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arsize(2),
O => m_mesg_mux(44)
);
\gen_arbiter.m_mesg_i[45]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlock(1),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arlock(0),
O => m_mesg_mux(45)
);
\gen_arbiter.m_mesg_i[47]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(3),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arprot(0),
O => m_mesg_mux(47)
);
\gen_arbiter.m_mesg_i[48]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(4),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arprot(1),
O => m_mesg_mux(48)
);
\gen_arbiter.m_mesg_i[49]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(5),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arprot(2),
O => m_mesg_mux(49)
);
\gen_arbiter.m_mesg_i[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(34),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(2),
O => m_mesg_mux(4)
);
\gen_arbiter.m_mesg_i[54]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(2),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arburst(0),
O => m_mesg_mux(54)
);
\gen_arbiter.m_mesg_i[55]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(3),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arburst(1),
O => m_mesg_mux(55)
);
\gen_arbiter.m_mesg_i[56]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arcache(4),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arcache(0),
O => m_mesg_mux(56)
);
\gen_arbiter.m_mesg_i[57]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arcache(5),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arcache(1),
O => m_mesg_mux(57)
);
\gen_arbiter.m_mesg_i[58]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arcache(6),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arcache(2),
O => m_mesg_mux(58)
);
\gen_arbiter.m_mesg_i[59]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arcache(7),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arcache(3),
O => m_mesg_mux(59)
);
\gen_arbiter.m_mesg_i[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(35),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(3),
O => m_mesg_mux(5)
);
\gen_arbiter.m_mesg_i[60]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arqos(4),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arqos(0),
O => m_mesg_mux(60)
);
\gen_arbiter.m_mesg_i[61]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arqos(5),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arqos(1),
O => m_mesg_mux(61)
);
\gen_arbiter.m_mesg_i[62]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arqos(6),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arqos(2),
O => m_mesg_mux(62)
);
\gen_arbiter.m_mesg_i[63]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arqos(7),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arqos(3),
O => m_mesg_mux(63)
);
\gen_arbiter.m_mesg_i[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(36),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(4),
O => m_mesg_mux(6)
);
\gen_arbiter.m_mesg_i[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(37),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(5),
O => m_mesg_mux(7)
);
\gen_arbiter.m_mesg_i[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(38),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(6),
O => m_mesg_mux(8)
);
\gen_arbiter.m_mesg_i[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(39),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(7),
O => m_mesg_mux(9)
);
\gen_arbiter.m_mesg_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
Q => \^m_axi_arqos[3]\(0),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(10),
Q => \^m_axi_arqos[3]\(9),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(11),
Q => \^m_axi_arqos[3]\(10),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(12),
Q => \^m_axi_arqos[3]\(11),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(13),
Q => \^m_axi_arqos[3]\(12),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(14),
Q => \^m_axi_arqos[3]\(13),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(15),
Q => \^m_axi_arqos[3]\(14),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(16),
Q => \^m_axi_arqos[3]\(15),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(17),
Q => \^m_axi_arqos[3]\(16),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(18),
Q => \^m_axi_arqos[3]\(17),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(19),
Q => \^m_axi_arqos[3]\(18),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(20),
Q => \^m_axi_arqos[3]\(19),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(21),
Q => \^m_axi_arqos[3]\(20),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(22),
Q => \^m_axi_arqos[3]\(21),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(23),
Q => \^m_axi_arqos[3]\(22),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(24),
Q => \^m_axi_arqos[3]\(23),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(25),
Q => \^m_axi_arqos[3]\(24),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(26),
Q => \^m_axi_arqos[3]\(25),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(27),
Q => \^m_axi_arqos[3]\(26),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(28),
Q => \^m_axi_arqos[3]\(27),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(29),
Q => \^m_axi_arqos[3]\(28),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(2),
Q => \^m_axi_arqos[3]\(1),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(30),
Q => \^m_axi_arqos[3]\(29),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(31),
Q => \^m_axi_arqos[3]\(30),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(32),
Q => \^m_axi_arqos[3]\(31),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(33),
Q => \^m_axi_arqos[3]\(32),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(34),
Q => \^m_axi_arqos[3]\(33),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(35),
Q => \^m_axi_arqos[3]\(34),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(36),
Q => \^m_axi_arqos[3]\(35),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(37),
Q => \^m_axi_arqos[3]\(36),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(38),
Q => \^m_axi_arqos[3]\(37),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(39),
Q => \^m_axi_arqos[3]\(38),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(3),
Q => \^m_axi_arqos[3]\(2),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(40),
Q => \^m_axi_arqos[3]\(39),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(41),
Q => \^m_axi_arqos[3]\(40),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(42),
Q => \^m_axi_arqos[3]\(41),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(43),
Q => \^m_axi_arqos[3]\(42),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(44),
Q => \^m_axi_arqos[3]\(43),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(45),
Q => \^m_axi_arqos[3]\(44),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(47),
Q => \^m_axi_arqos[3]\(45),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(48),
Q => \^m_axi_arqos[3]\(46),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(49),
Q => \^m_axi_arqos[3]\(47),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(4),
Q => \^m_axi_arqos[3]\(3),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(54),
Q => \^m_axi_arqos[3]\(48),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(55),
Q => \^m_axi_arqos[3]\(49),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(56),
Q => \^m_axi_arqos[3]\(50),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(57),
Q => \^m_axi_arqos[3]\(51),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(58),
Q => \^m_axi_arqos[3]\(52),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(59),
Q => \^m_axi_arqos[3]\(53),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(5),
Q => \^m_axi_arqos[3]\(4),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(60),
Q => \^m_axi_arqos[3]\(54),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(61),
Q => \^m_axi_arqos[3]\(55),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(62),
Q => \^m_axi_arqos[3]\(56),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(63),
Q => \^m_axi_arqos[3]\(57),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(6),
Q => \^m_axi_arqos[3]\(5),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(7),
Q => \^m_axi_arqos[3]\(6),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(8),
Q => \^m_axi_arqos[3]\(7),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(9),
Q => \^m_axi_arqos[3]\(8),
R => \^sr\(0)
);
\gen_arbiter.m_target_hot_i[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2222222E"
)
port map (
I0 => \^sel_4\,
I1 => \^next_enc\(0),
I2 => s_axi_araddr(63),
I3 => s_axi_araddr(62),
I4 => s_axi_araddr(61),
O => m_target_hot_mux(0)
);
\gen_arbiter.m_target_hot_i[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FE00FEFF"
)
port map (
I0 => s_axi_araddr(61),
I1 => s_axi_araddr(62),
I2 => s_axi_araddr(63),
I3 => \^next_enc\(0),
I4 => \^sel_4\,
O => m_target_hot_mux(1)
);
\gen_arbiter.m_target_hot_i[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => s_axi_araddr(31),
I1 => s_axi_araddr(30),
I2 => s_axi_araddr(29),
O => \^sel_4\
);
\gen_arbiter.m_target_hot_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => grant_hot,
D => m_target_hot_mux(0),
Q => \^q\(0),
R => \^sr\(0)
);
\gen_arbiter.m_target_hot_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => grant_hot,
D => m_target_hot_mux(1),
Q => \^q\(1),
R => \^sr\(0)
);
\gen_arbiter.m_valid_i_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"003F3F3FAAAAAAAA"
)
port map (
I0 => \gen_arbiter.any_grant_reg_n_0\,
I1 => \^q\(1),
I2 => mi_arready(0),
I3 => m_axi_arready(0),
I4 => \^q\(0),
I5 => \^aa_mi_arvalid\,
O => \gen_arbiter.m_valid_i_i_1__0_n_0\
);
\gen_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_arbiter.m_valid_i_i_1__0_n_0\,
Q => \^aa_mi_arvalid\,
R => \^sr\(0)
);
\gen_arbiter.qual_reg[1]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => s_axi_araddr(63),
I1 => s_axi_araddr(62),
I2 => s_axi_araddr(61),
O => sel_4_0
);
\gen_arbiter.qual_reg[1]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => r_issuing_cnt(0),
I1 => r_issuing_cnt(1),
O => \gen_arbiter.qual_reg_reg[1]_0\
);
\gen_arbiter.qual_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(0),
Q => qual_reg(0),
R => \^sr\(0)
);
\gen_arbiter.qual_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(1),
Q => qual_reg(1),
R => \^sr\(0)
);
\gen_arbiter.s_ready_i[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \gen_arbiter.grant_hot_reg_n_0_[0]\,
I1 => aresetn_d,
I2 => \^aa_mi_arvalid\,
I3 => \gen_arbiter.any_grant_reg_n_0\,
O => \gen_arbiter.s_ready_i[0]_i_1__0_n_0\
);
\gen_arbiter.s_ready_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \gen_arbiter.grant_hot_reg_n_0_[1]\,
I1 => aresetn_d,
I2 => \^aa_mi_arvalid\,
I3 => \gen_arbiter.any_grant_reg_n_0\,
O => \gen_arbiter.s_ready_i[1]_i_1_n_0\
);
\gen_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_arbiter.s_ready_i[0]_i_1__0_n_0\,
Q => \^s_axi_arready[0]\,
R => '0'
);
\gen_arbiter.s_ready_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_arbiter.s_ready_i[1]_i_1_n_0\,
Q => \^s_axi_arready[1]\,
R => '0'
);
\gen_axi.s_axi_rid_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBFFF00008000"
)
port map (
I0 => \^m_axi_arqos[3]\(0),
I1 => mi_arready(0),
I2 => \^q\(1),
I3 => \^aa_mi_arvalid\,
I4 => p_11_in,
I5 => p_16_in(0),
O => \gen_axi.s_axi_rid_i_reg[0]\
);
\gen_axi.s_axi_rlast_i_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \gen_axi.s_axi_rlast_i_i_4_n_0\,
I1 => p_11_in,
I2 => \^m_axi_arqos[3]\(33),
I3 => \^m_axi_arqos[3]\(34),
O => \gen_axi.s_axi_rlast_i_reg\
);
\gen_axi.s_axi_rlast_i_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \^m_axi_arqos[3]\(35),
I1 => \^m_axi_arqos[3]\(36),
I2 => \^m_axi_arqos[3]\(37),
I3 => \^m_axi_arqos[3]\(38),
I4 => \^m_axi_arqos[3]\(40),
I5 => \^m_axi_arqos[3]\(39),
O => \gen_axi.s_axi_rlast_i_i_4_n_0\
);
\gen_master_slots[0].r_issuing_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => r_issuing_cnt(0),
I1 => r_issuing_cnt(1),
I2 => r_issuing_cnt(2),
I3 => r_issuing_cnt(3),
I4 => \gen_master_slots[0].r_issuing_cnt[3]_i_3_n_0\,
I5 => m_valid_i_reg_0,
O => E(0)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^aa_mi_arvalid\,
I1 => \^q\(0),
I2 => m_axi_arready(0),
O => \gen_master_slots[0].r_issuing_cnt[3]_i_3_n_0\
);
\gen_master_slots[1].r_issuing_cnt[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"95554000"
)
port map (
I0 => m_valid_i_reg,
I1 => mi_arready(0),
I2 => \^q\(1),
I3 => \^aa_mi_arvalid\,
I4 => r_issuing_cnt(4),
O => \gen_master_slots[1].r_issuing_cnt_reg[8]\
);
\gen_single_thread.active_target_enc[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFFFE00"
)
port map (
I0 => s_axi_araddr(29),
I1 => s_axi_araddr(30),
I2 => s_axi_araddr(31),
I3 => \^s_axi_arready[0]\,
I4 => active_target_enc,
O => \gen_single_thread.active_target_enc_reg[0]\
);
\gen_single_thread.active_target_enc[0]_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFFFE00"
)
port map (
I0 => s_axi_araddr(61),
I1 => s_axi_araddr(62),
I2 => s_axi_araddr(63),
I3 => \^s_axi_arready[1]\,
I4 => active_target_enc_2,
O => \gen_single_thread.active_target_enc_reg[0]_0\
);
\gen_single_thread.active_target_hot[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0100"
)
port map (
I0 => s_axi_araddr(31),
I1 => s_axi_araddr(30),
I2 => s_axi_araddr(29),
I3 => \^s_axi_arready[0]\,
I4 => active_target_hot(0),
O => \gen_single_thread.active_target_hot_reg[0]\
);
\gen_single_thread.active_target_hot[0]_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0100"
)
port map (
I0 => s_axi_araddr(63),
I1 => s_axi_araddr(62),
I2 => s_axi_araddr(61),
I3 => \^s_axi_arready[1]\,
I4 => active_target_hot_1(0),
O => \gen_single_thread.active_target_hot_reg[0]_0\
);
\m_axi_arvalid[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^q\(0),
I1 => \^aa_mi_arvalid\,
O => m_axi_arvalid(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_crossbar_v2_1_12_addr_arbiter_0 is
port (
aa_wm_awgrant_enc : out STD_LOGIC_VECTOR ( 0 to 0 );
next_enc : out STD_LOGIC_VECTOR ( 0 to 0 );
aa_sa_awvalid : out STD_LOGIC;
\gen_arbiter.last_rr_hot_reg[0]_0\ : out STD_LOGIC;
\storage_data1_reg[0]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_master_slots[1].w_issuing_cnt_reg[8]\ : out STD_LOGIC;
\storage_data1_reg[1]\ : out STD_LOGIC;
push : out STD_LOGIC;
\storage_data1_reg[0]_0\ : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
\gen_axi.s_axi_awready_i_reg\ : out STD_LOGIC;
\m_ready_d_reg[1]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
sel_4 : out STD_LOGIC;
sel_4_0 : out STD_LOGIC;
ss_aa_awready : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
\storage_data1_reg[1]_0\ : out STD_LOGIC;
\gen_rep[0].fifoaddr_reg[0]\ : out STD_LOGIC;
\m_ready_d_reg[1]_0\ : out STD_LOGIC;
\gen_arbiter.qual_reg_reg[2]_0\ : out STD_LOGIC;
\m_axi_awqos[3]\ : out STD_LOGIC_VECTOR ( 57 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
aa_sa_awready : in STD_LOGIC;
\gen_single_thread.accept_cnt_reg[0]\ : in STD_LOGIC;
\gen_master_slots[1].w_issuing_cnt_reg[8]_0\ : in STD_LOGIC;
\gen_arbiter.m_valid_i_reg_0\ : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_ready_d : in STD_LOGIC_VECTOR ( 1 downto 0 );
mi_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_single_thread.active_target_enc_reg[0]\ : in STD_LOGIC;
w_issuing_cnt : in STD_LOGIC_VECTOR ( 4 downto 0 );
out0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
\storage_data1_reg[1]_1\ : in STD_LOGIC;
st_aa_awvalid_qual : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg_0 : in STD_LOGIC;
\gen_single_thread.active_target_hot_reg[0]\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_ready_d_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 15 downto 0 );
\m_ready_d_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_master_slots[1].w_issuing_cnt_reg[8]_1\ : in STD_LOGIC;
aresetn_d : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_crossbar_v2_1_12_addr_arbiter_0 : entity is "axi_crossbar_v2_1_12_addr_arbiter";
end system_xbar_0_axi_crossbar_v2_1_12_addr_arbiter_0;
architecture STRUCTURE of system_xbar_0_axi_crossbar_v2_1_12_addr_arbiter_0 is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^aa_sa_awvalid\ : STD_LOGIC;
signal \^aa_wm_awgrant_enc\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_arbiter.any_grant_i_1_n_0\ : STD_LOGIC;
signal \gen_arbiter.any_grant_reg_n_0\ : STD_LOGIC;
signal \gen_arbiter.grant_hot[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_arbiter.grant_hot[2]_i_1_n_0\ : STD_LOGIC;
signal \gen_arbiter.grant_hot[2]_i_4_n_0\ : STD_LOGIC;
signal \gen_arbiter.grant_hot_reg_n_0_[0]\ : STD_LOGIC;
signal \gen_arbiter.grant_hot_reg_n_0_[2]\ : STD_LOGIC;
signal \gen_arbiter.last_rr_hot[2]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_arbiter.last_rr_hot[2]_i_4_n_0\ : STD_LOGIC;
signal \^gen_arbiter.last_rr_hot_reg[0]_0\ : STD_LOGIC;
signal \gen_arbiter.last_rr_hot_reg_n_0_[0]\ : STD_LOGIC;
signal \gen_arbiter.m_valid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_arbiter.s_ready_i[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_arbiter.s_ready_i[2]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].w_issuing_cnt[3]_i_3_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].w_issuing_cnt[3]_i_4_n_0\ : STD_LOGIC;
signal grant_hot : STD_LOGIC;
signal m_mesg_mux : STD_LOGIC_VECTOR ( 63 downto 2 );
signal m_target_hot_mux : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^next_enc\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_5_in : STD_LOGIC;
signal qual_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^sel_4\ : STD_LOGIC;
signal \^ss_aa_awready\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_arbiter.last_rr_hot[0]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \gen_arbiter.last_rr_hot[2]_i_2\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \gen_arbiter.last_rr_hot[2]_i_3__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[10]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[11]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[12]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[13]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[14]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[15]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[16]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[17]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[18]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[19]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[20]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[21]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[22]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[23]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[24]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[25]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[26]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[27]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[28]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[29]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[2]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[30]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[31]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[32]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[33]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[34]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[35]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[36]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[37]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[38]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[39]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[3]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[40]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[41]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[42]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[43]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[44]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[45]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[47]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[48]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[49]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[4]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[54]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[55]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[56]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[57]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[58]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[59]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[5]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[60]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[61]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[62]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[63]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[6]_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[7]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[8]_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[9]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \gen_arbiter.m_target_hot_i[0]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \gen_arbiter.m_target_hot_i[1]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \gen_arbiter.m_valid_i_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \gen_arbiter.qual_reg[2]_i_4\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \gen_arbiter.qual_reg[2]_i_5\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \gen_arbiter.s_ready_i[0]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \gen_arbiter.s_ready_i[2]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \gen_axi.write_cs[0]_i_2\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[1]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[2]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_2\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_3\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_4\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_axi_awvalid[0]_INST_0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_ready_d[1]_i_2\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_ready_d[1]_i_3\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of m_valid_i_i_1 : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_valid_i_i_1__1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \storage_data1[1]_i_3\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \storage_data1[1]_i_3__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \storage_data1[1]_i_4\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \storage_data1[1]_i_4__0\ : label is "soft_lutpair40";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
aa_sa_awvalid <= \^aa_sa_awvalid\;
aa_wm_awgrant_enc(0) <= \^aa_wm_awgrant_enc\(0);
\gen_arbiter.last_rr_hot_reg[0]_0\ <= \^gen_arbiter.last_rr_hot_reg[0]_0\;
next_enc(0) <= \^next_enc\(0);
sel_4 <= \^sel_4\;
ss_aa_awready(1 downto 0) <= \^ss_aa_awready\(1 downto 0);
\gen_arbiter.any_grant_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FEEEAAAA"
)
port map (
I0 => \gen_arbiter.any_grant_reg_n_0\,
I1 => \gen_single_thread.accept_cnt_reg[0]\,
I2 => \^gen_arbiter.last_rr_hot_reg[0]_0\,
I3 => \gen_master_slots[1].w_issuing_cnt_reg[8]_0\,
I4 => \gen_arbiter.grant_hot[2]_i_4_n_0\,
I5 => \gen_arbiter.m_valid_i_reg_0\,
O => \gen_arbiter.any_grant_i_1_n_0\
);
\gen_arbiter.any_grant_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_arbiter.any_grant_i_1_n_0\,
Q => \gen_arbiter.any_grant_reg_n_0\,
R => '0'
);
\gen_arbiter.grant_hot[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000F2E2AAAA"
)
port map (
I0 => \gen_arbiter.grant_hot_reg_n_0_[0]\,
I1 => \gen_single_thread.accept_cnt_reg[0]\,
I2 => \^gen_arbiter.last_rr_hot_reg[0]_0\,
I3 => \gen_master_slots[1].w_issuing_cnt_reg[8]_0\,
I4 => \gen_arbiter.grant_hot[2]_i_4_n_0\,
I5 => \gen_arbiter.m_valid_i_reg_0\,
O => \gen_arbiter.grant_hot[0]_i_1_n_0\
);
\gen_arbiter.grant_hot[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FEAA02AA"
)
port map (
I0 => \gen_arbiter.grant_hot_reg_n_0_[2]\,
I1 => \gen_single_thread.accept_cnt_reg[0]\,
I2 => \gen_master_slots[1].w_issuing_cnt_reg[8]_1\,
I3 => \gen_arbiter.grant_hot[2]_i_4_n_0\,
I4 => \^next_enc\(0),
I5 => \gen_arbiter.m_valid_i_reg_0\,
O => \gen_arbiter.grant_hot[2]_i_1_n_0\
);
\gen_arbiter.grant_hot[2]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"1111010111000100"
)
port map (
I0 => \^aa_sa_awvalid\,
I1 => \gen_arbiter.any_grant_reg_n_0\,
I2 => \gen_arbiter.last_rr_hot[2]_i_4_n_0\,
I3 => p_5_in,
I4 => p_2_in,
I5 => \gen_arbiter.last_rr_hot_reg_n_0_[0]\,
O => \gen_arbiter.grant_hot[2]_i_4_n_0\
);
\gen_arbiter.grant_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_arbiter.grant_hot[0]_i_1_n_0\,
Q => \gen_arbiter.grant_hot_reg_n_0_[0]\,
R => '0'
);
\gen_arbiter.grant_hot_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_arbiter.grant_hot[2]_i_1_n_0\,
Q => \gen_arbiter.grant_hot_reg_n_0_[2]\,
R => '0'
);
\gen_arbiter.last_rr_hot[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0F02"
)
port map (
I0 => \gen_arbiter.last_rr_hot_reg_n_0_[0]\,
I1 => p_2_in,
I2 => \gen_arbiter.last_rr_hot[2]_i_4_n_0\,
I3 => p_5_in,
O => \^gen_arbiter.last_rr_hot_reg[0]_0\
);
\gen_arbiter.last_rr_hot[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA80808080808080"
)
port map (
I0 => \gen_arbiter.last_rr_hot[2]_i_3__0_n_0\,
I1 => \gen_master_slots[1].w_issuing_cnt_reg[8]_0\,
I2 => \^gen_arbiter.last_rr_hot_reg[0]_0\,
I3 => \^next_enc\(0),
I4 => st_aa_awvalid_qual(0),
I5 => m_valid_i_reg_0,
O => grant_hot
);
\gen_arbiter.last_rr_hot[2]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F080"
)
port map (
I0 => \gen_arbiter.last_rr_hot[2]_i_4_n_0\,
I1 => p_5_in,
I2 => p_2_in,
I3 => \gen_arbiter.last_rr_hot_reg_n_0_[0]\,
O => \^next_enc\(0)
);
\gen_arbiter.last_rr_hot[2]_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \gen_arbiter.any_grant_reg_n_0\,
I1 => \^aa_sa_awvalid\,
O => \gen_arbiter.last_rr_hot[2]_i_3__0_n_0\
);
\gen_arbiter.last_rr_hot[2]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => s_axi_awvalid(0),
I1 => qual_reg(0),
I2 => \^ss_aa_awready\(0),
I3 => m_ready_d_1(0),
O => \gen_arbiter.last_rr_hot[2]_i_4_n_0\
);
\gen_arbiter.last_rr_hot[2]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => s_axi_awvalid(1),
I1 => qual_reg(2),
I2 => \^ss_aa_awready\(1),
I3 => m_ready_d_2(0),
O => p_2_in
);
\gen_arbiter.last_rr_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => grant_hot,
D => \^gen_arbiter.last_rr_hot_reg[0]_0\,
Q => \gen_arbiter.last_rr_hot_reg_n_0_[0]\,
R => SR(0)
);
\gen_arbiter.last_rr_hot_reg[2]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => grant_hot,
D => \^next_enc\(0),
Q => p_5_in,
S => SR(0)
);
\gen_arbiter.m_grant_enc_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => grant_hot,
D => \^next_enc\(0),
Q => \^aa_wm_awgrant_enc\(0),
R => SR(0)
);
\gen_arbiter.m_mesg_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(40),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awaddr(8),
O => m_mesg_mux(10)
);
\gen_arbiter.m_mesg_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(41),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awaddr(9),
O => m_mesg_mux(11)
);
\gen_arbiter.m_mesg_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(42),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awaddr(10),
O => m_mesg_mux(12)
);
\gen_arbiter.m_mesg_i[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(43),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awaddr(11),
O => m_mesg_mux(13)
);
\gen_arbiter.m_mesg_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(44),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awaddr(12),
O => m_mesg_mux(14)
);
\gen_arbiter.m_mesg_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(45),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awaddr(13),
O => m_mesg_mux(15)
);
\gen_arbiter.m_mesg_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(46),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awaddr(14),
O => m_mesg_mux(16)
);
\gen_arbiter.m_mesg_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(47),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awaddr(15),
O => m_mesg_mux(17)
);
\gen_arbiter.m_mesg_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(48),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awaddr(16),
O => m_mesg_mux(18)
);
\gen_arbiter.m_mesg_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(49),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awaddr(17),
O => m_mesg_mux(19)
);
\gen_arbiter.m_mesg_i[1]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^aa_sa_awvalid\,
O => p_1_in
);
\gen_arbiter.m_mesg_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(50),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awaddr(18),
O => m_mesg_mux(20)
);
\gen_arbiter.m_mesg_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(51),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awaddr(19),
O => m_mesg_mux(21)
);
\gen_arbiter.m_mesg_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(52),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awaddr(20),
O => m_mesg_mux(22)
);
\gen_arbiter.m_mesg_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(53),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awaddr(21),
O => m_mesg_mux(23)
);
\gen_arbiter.m_mesg_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(54),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awaddr(22),
O => m_mesg_mux(24)
);
\gen_arbiter.m_mesg_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(55),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awaddr(23),
O => m_mesg_mux(25)
);
\gen_arbiter.m_mesg_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(56),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awaddr(24),
O => m_mesg_mux(26)
);
\gen_arbiter.m_mesg_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(57),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awaddr(25),
O => m_mesg_mux(27)
);
\gen_arbiter.m_mesg_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(58),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awaddr(26),
O => m_mesg_mux(28)
);
\gen_arbiter.m_mesg_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(59),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awaddr(27),
O => m_mesg_mux(29)
);
\gen_arbiter.m_mesg_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(32),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awaddr(0),
O => m_mesg_mux(2)
);
\gen_arbiter.m_mesg_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(60),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awaddr(28),
O => m_mesg_mux(30)
);
\gen_arbiter.m_mesg_i[31]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(61),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awaddr(29),
O => m_mesg_mux(31)
);
\gen_arbiter.m_mesg_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(62),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awaddr(30),
O => m_mesg_mux(32)
);
\gen_arbiter.m_mesg_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(63),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awaddr(31),
O => m_mesg_mux(33)
);
\gen_arbiter.m_mesg_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(8),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awlen(0),
O => m_mesg_mux(34)
);
\gen_arbiter.m_mesg_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(9),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awlen(1),
O => m_mesg_mux(35)
);
\gen_arbiter.m_mesg_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(10),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awlen(2),
O => m_mesg_mux(36)
);
\gen_arbiter.m_mesg_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(11),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awlen(3),
O => m_mesg_mux(37)
);
\gen_arbiter.m_mesg_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(12),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awlen(4),
O => m_mesg_mux(38)
);
\gen_arbiter.m_mesg_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(13),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awlen(5),
O => m_mesg_mux(39)
);
\gen_arbiter.m_mesg_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(33),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awaddr(1),
O => m_mesg_mux(3)
);
\gen_arbiter.m_mesg_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(14),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awlen(6),
O => m_mesg_mux(40)
);
\gen_arbiter.m_mesg_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(15),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awlen(7),
O => m_mesg_mux(41)
);
\gen_arbiter.m_mesg_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(3),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awsize(0),
O => m_mesg_mux(42)
);
\gen_arbiter.m_mesg_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(4),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awsize(1),
O => m_mesg_mux(43)
);
\gen_arbiter.m_mesg_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(5),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awsize(2),
O => m_mesg_mux(44)
);
\gen_arbiter.m_mesg_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlock(1),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awlock(0),
O => m_mesg_mux(45)
);
\gen_arbiter.m_mesg_i[47]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(3),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awprot(0),
O => m_mesg_mux(47)
);
\gen_arbiter.m_mesg_i[48]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(4),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awprot(1),
O => m_mesg_mux(48)
);
\gen_arbiter.m_mesg_i[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(5),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awprot(2),
O => m_mesg_mux(49)
);
\gen_arbiter.m_mesg_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(34),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awaddr(2),
O => m_mesg_mux(4)
);
\gen_arbiter.m_mesg_i[54]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(2),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awburst(0),
O => m_mesg_mux(54)
);
\gen_arbiter.m_mesg_i[55]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(3),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awburst(1),
O => m_mesg_mux(55)
);
\gen_arbiter.m_mesg_i[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awcache(4),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awcache(0),
O => m_mesg_mux(56)
);
\gen_arbiter.m_mesg_i[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awcache(5),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awcache(1),
O => m_mesg_mux(57)
);
\gen_arbiter.m_mesg_i[58]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awcache(6),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awcache(2),
O => m_mesg_mux(58)
);
\gen_arbiter.m_mesg_i[59]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awcache(7),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awcache(3),
O => m_mesg_mux(59)
);
\gen_arbiter.m_mesg_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(35),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awaddr(3),
O => m_mesg_mux(5)
);
\gen_arbiter.m_mesg_i[60]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awqos(4),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awqos(0),
O => m_mesg_mux(60)
);
\gen_arbiter.m_mesg_i[61]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awqos(5),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awqos(1),
O => m_mesg_mux(61)
);
\gen_arbiter.m_mesg_i[62]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awqos(6),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awqos(2),
O => m_mesg_mux(62)
);
\gen_arbiter.m_mesg_i[63]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awqos(7),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awqos(3),
O => m_mesg_mux(63)
);
\gen_arbiter.m_mesg_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(36),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awaddr(4),
O => m_mesg_mux(6)
);
\gen_arbiter.m_mesg_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(37),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awaddr(5),
O => m_mesg_mux(7)
);
\gen_arbiter.m_mesg_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(38),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awaddr(6),
O => m_mesg_mux(8)
);
\gen_arbiter.m_mesg_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(39),
I1 => \^aa_wm_awgrant_enc\(0),
I2 => s_axi_awaddr(7),
O => m_mesg_mux(9)
);
\gen_arbiter.m_mesg_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(10),
Q => \m_axi_awqos[3]\(9),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(11),
Q => \m_axi_awqos[3]\(10),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(12),
Q => \m_axi_awqos[3]\(11),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(13),
Q => \m_axi_awqos[3]\(12),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(14),
Q => \m_axi_awqos[3]\(13),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(15),
Q => \m_axi_awqos[3]\(14),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(16),
Q => \m_axi_awqos[3]\(15),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(17),
Q => \m_axi_awqos[3]\(16),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(18),
Q => \m_axi_awqos[3]\(17),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(19),
Q => \m_axi_awqos[3]\(18),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \^aa_wm_awgrant_enc\(0),
Q => \m_axi_awqos[3]\(0),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(20),
Q => \m_axi_awqos[3]\(19),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(21),
Q => \m_axi_awqos[3]\(20),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(22),
Q => \m_axi_awqos[3]\(21),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(23),
Q => \m_axi_awqos[3]\(22),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(24),
Q => \m_axi_awqos[3]\(23),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(25),
Q => \m_axi_awqos[3]\(24),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(26),
Q => \m_axi_awqos[3]\(25),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(27),
Q => \m_axi_awqos[3]\(26),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(28),
Q => \m_axi_awqos[3]\(27),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(29),
Q => \m_axi_awqos[3]\(28),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(2),
Q => \m_axi_awqos[3]\(1),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(30),
Q => \m_axi_awqos[3]\(29),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(31),
Q => \m_axi_awqos[3]\(30),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(32),
Q => \m_axi_awqos[3]\(31),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(33),
Q => \m_axi_awqos[3]\(32),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(34),
Q => \m_axi_awqos[3]\(33),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(35),
Q => \m_axi_awqos[3]\(34),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(36),
Q => \m_axi_awqos[3]\(35),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(37),
Q => \m_axi_awqos[3]\(36),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(38),
Q => \m_axi_awqos[3]\(37),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(39),
Q => \m_axi_awqos[3]\(38),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(3),
Q => \m_axi_awqos[3]\(2),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(40),
Q => \m_axi_awqos[3]\(39),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(41),
Q => \m_axi_awqos[3]\(40),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(42),
Q => \m_axi_awqos[3]\(41),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(43),
Q => \m_axi_awqos[3]\(42),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(44),
Q => \m_axi_awqos[3]\(43),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(45),
Q => \m_axi_awqos[3]\(44),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(47),
Q => \m_axi_awqos[3]\(45),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(48),
Q => \m_axi_awqos[3]\(46),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(49),
Q => \m_axi_awqos[3]\(47),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(4),
Q => \m_axi_awqos[3]\(3),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(54),
Q => \m_axi_awqos[3]\(48),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(55),
Q => \m_axi_awqos[3]\(49),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(56),
Q => \m_axi_awqos[3]\(50),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(57),
Q => \m_axi_awqos[3]\(51),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(58),
Q => \m_axi_awqos[3]\(52),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(59),
Q => \m_axi_awqos[3]\(53),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(5),
Q => \m_axi_awqos[3]\(4),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(60),
Q => \m_axi_awqos[3]\(54),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(61),
Q => \m_axi_awqos[3]\(55),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(62),
Q => \m_axi_awqos[3]\(56),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(63),
Q => \m_axi_awqos[3]\(57),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(6),
Q => \m_axi_awqos[3]\(5),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(7),
Q => \m_axi_awqos[3]\(6),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(8),
Q => \m_axi_awqos[3]\(7),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(9),
Q => \m_axi_awqos[3]\(8),
R => SR(0)
);
\gen_arbiter.m_target_hot_i[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"2222222E"
)
port map (
I0 => \^sel_4\,
I1 => \^next_enc\(0),
I2 => s_axi_awaddr(63),
I3 => s_axi_awaddr(62),
I4 => s_axi_awaddr(61),
O => m_target_hot_mux(0)
);
\gen_arbiter.m_target_hot_i[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FE00FEFF"
)
port map (
I0 => s_axi_awaddr(61),
I1 => s_axi_awaddr(62),
I2 => s_axi_awaddr(63),
I3 => \^next_enc\(0),
I4 => \^sel_4\,
O => m_target_hot_mux(1)
);
\gen_arbiter.m_target_hot_i[1]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => s_axi_awaddr(31),
I1 => s_axi_awaddr(30),
I2 => s_axi_awaddr(29),
O => \^sel_4\
);
\gen_arbiter.m_target_hot_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => grant_hot,
D => m_target_hot_mux(0),
Q => \^q\(0),
R => SR(0)
);
\gen_arbiter.m_target_hot_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => grant_hot,
D => m_target_hot_mux(1),
Q => \^q\(1),
R => SR(0)
);
\gen_arbiter.m_valid_i_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"5C"
)
port map (
I0 => aa_sa_awready,
I1 => \gen_arbiter.any_grant_reg_n_0\,
I2 => \^aa_sa_awvalid\,
O => \gen_arbiter.m_valid_i_i_1_n_0\
);
\gen_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_arbiter.m_valid_i_i_1_n_0\,
Q => \^aa_sa_awvalid\,
R => SR(0)
);
\gen_arbiter.qual_reg[2]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => s_axi_awaddr(63),
I1 => s_axi_awaddr(62),
I2 => s_axi_awaddr(61),
O => sel_4_0
);
\gen_arbiter.qual_reg[2]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => w_issuing_cnt(3),
I1 => w_issuing_cnt(2),
I2 => w_issuing_cnt(1),
I3 => w_issuing_cnt(0),
O => \gen_arbiter.qual_reg_reg[2]_0\
);
\gen_arbiter.qual_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_ready_d_reg[0]\(0),
Q => qual_reg(0),
R => SR(0)
);
\gen_arbiter.qual_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_ready_d_reg[0]\(1),
Q => qual_reg(2),
R => SR(0)
);
\gen_arbiter.s_ready_i[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \gen_arbiter.grant_hot_reg_n_0_[0]\,
I1 => aresetn_d,
I2 => \^aa_sa_awvalid\,
I3 => \gen_arbiter.any_grant_reg_n_0\,
O => \gen_arbiter.s_ready_i[0]_i_1_n_0\
);
\gen_arbiter.s_ready_i[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \gen_arbiter.grant_hot_reg_n_0_[2]\,
I1 => aresetn_d,
I2 => \^aa_sa_awvalid\,
I3 => \gen_arbiter.any_grant_reg_n_0\,
O => \gen_arbiter.s_ready_i[2]_i_1_n_0\
);
\gen_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_arbiter.s_ready_i[0]_i_1_n_0\,
Q => \^ss_aa_awready\(0),
R => '0'
);
\gen_arbiter.s_ready_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_arbiter.s_ready_i[2]_i_1_n_0\,
Q => \^ss_aa_awready\(1),
R => '0'
);
\gen_axi.write_cs[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"DFFF"
)
port map (
I0 => mi_awready(0),
I1 => m_ready_d(1),
I2 => \^aa_sa_awvalid\,
I3 => \^q\(1),
O => \gen_axi.s_axi_awready_i_reg\
);
\gen_master_slots[0].w_issuing_cnt[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => w_issuing_cnt(1),
I1 => w_issuing_cnt(0),
I2 => \gen_master_slots[0].w_issuing_cnt[3]_i_4_n_0\,
O => D(0)
);
\gen_master_slots[0].w_issuing_cnt[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AA9"
)
port map (
I0 => w_issuing_cnt(2),
I1 => w_issuing_cnt(0),
I2 => w_issuing_cnt(1),
I3 => \gen_master_slots[0].w_issuing_cnt[3]_i_4_n_0\,
O => D(1)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => w_issuing_cnt(0),
I1 => w_issuing_cnt(1),
I2 => w_issuing_cnt(2),
I3 => w_issuing_cnt(3),
I4 => \gen_master_slots[0].w_issuing_cnt[3]_i_3_n_0\,
I5 => \gen_single_thread.active_target_hot_reg[0]\,
O => E(0)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => w_issuing_cnt(3),
I1 => w_issuing_cnt(1),
I2 => w_issuing_cnt(2),
I3 => w_issuing_cnt(0),
I4 => \gen_master_slots[0].w_issuing_cnt[3]_i_4_n_0\,
O => D(2)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"DFFF"
)
port map (
I0 => m_axi_awready(0),
I1 => m_ready_d(1),
I2 => \^aa_sa_awvalid\,
I3 => \^q\(0),
O => \gen_master_slots[0].w_issuing_cnt[3]_i_3_n_0\
);
\gen_master_slots[0].w_issuing_cnt[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => \gen_single_thread.active_target_hot_reg[0]\,
I1 => \^q\(0),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(1),
I4 => m_axi_awready(0),
O => \gen_master_slots[0].w_issuing_cnt[3]_i_4_n_0\
);
\gen_master_slots[1].w_issuing_cnt[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2000DFFF00002000"
)
port map (
I0 => mi_awready(0),
I1 => m_ready_d(1),
I2 => \^aa_sa_awvalid\,
I3 => \^q\(1),
I4 => \gen_single_thread.active_target_enc_reg[0]\,
I5 => w_issuing_cnt(4),
O => \gen_master_slots[1].w_issuing_cnt_reg[8]\
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F00000008000"
)
port map (
I0 => \storage_data1_reg[1]_1\,
I1 => \out\(1),
I2 => \^aa_sa_awvalid\,
I3 => \^q\(1),
I4 => m_ready_d(0),
I5 => \out\(2),
O => push
);
\m_axi_awvalid[0]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^aa_sa_awvalid\,
I1 => \^q\(0),
I2 => m_ready_d(1),
O => m_axi_awvalid(0)
);
\m_ready_d[1]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^q\(0),
I1 => \^aa_sa_awvalid\,
O => \m_ready_d_reg[1]_0\
);
\m_ready_d[1]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^q\(1),
I1 => \^aa_sa_awvalid\,
O => \m_ready_d_reg[1]\
);
m_valid_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^aa_sa_awvalid\,
I1 => \^q\(1),
I2 => m_ready_d(0),
O => m_valid_i_reg
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"F7"
)
port map (
I0 => \^aa_sa_awvalid\,
I1 => \^q\(0),
I2 => m_ready_d(0),
O => \gen_rep[0].fifoaddr_reg[0]\
);
\storage_data1[1]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => \out\(0),
I1 => m_ready_d(0),
I2 => \^q\(1),
I3 => \^aa_sa_awvalid\,
O => \storage_data1_reg[0]\
);
\storage_data1[1]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => out0(1),
I1 => m_ready_d(0),
I2 => \^q\(0),
I3 => \^aa_sa_awvalid\,
O => \storage_data1_reg[1]\
);
\storage_data1[1]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => m_ready_d(0),
I1 => \^q\(1),
I2 => \^aa_sa_awvalid\,
I3 => \out\(1),
O => \storage_data1_reg[0]_0\
);
\storage_data1[1]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => out0(0),
I1 => m_ready_d(0),
I2 => \^q\(0),
I3 => \^aa_sa_awvalid\,
O => \storage_data1_reg[1]_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_crossbar_v2_1_12_decerr_slave is
port (
mi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_10_in : out STD_LOGIC;
p_20_in : out STD_LOGIC_VECTOR ( 0 to 0 );
p_17_in : out STD_LOGIC;
p_11_in : out STD_LOGIC;
p_16_in : out STD_LOGIC_VECTOR ( 0 to 0 );
p_13_in : out STD_LOGIC;
mi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
\gen_arbiter.m_mesg_i_reg[0]\ : in STD_LOGIC;
\gen_axi.s_axi_awready_i_reg_0\ : in STD_LOGIC;
mi_bready_1 : in STD_LOGIC;
\write_cs0__0\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
mi_rready_1 : in STD_LOGIC;
aa_mi_arvalid : in STD_LOGIC;
\gen_arbiter.m_target_hot_i_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axi.read_cs_reg[0]_0\ : in STD_LOGIC;
\gen_arbiter.m_mesg_i_reg[41]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
bready_carry : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_crossbar_v2_1_12_decerr_slave : entity is "axi_crossbar_v2_1_12_decerr_slave";
end system_xbar_0_axi_crossbar_v2_1_12_decerr_slave;
architecture STRUCTURE of system_xbar_0_axi_crossbar_v2_1_12_decerr_slave is
signal \gen_axi.read_cnt[4]_i_2_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[5]_i_2_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[7]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 1 );
signal \gen_axi.read_cnt_reg__0__0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_axi.read_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_arready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_arready_i_i_2_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_awready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_bid_i[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_bvalid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_3_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_5_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_wready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.write_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.write_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \^mi_arready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^mi_awready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^p_10_in\ : STD_LOGIC;
signal \^p_11_in\ : STD_LOGIC;
signal \^p_13_in\ : STD_LOGIC;
signal \^p_17_in\ : STD_LOGIC;
signal \^p_20_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal s_axi_rvalid_i : STD_LOGIC;
signal write_cs : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.read_cnt[0]_i_1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[1]_i_1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[4]_i_2\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[5]_i_2\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[7]_i_2\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \gen_axi.s_axi_arready_i_i_2\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \gen_axi.s_axi_bvalid_i_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \gen_axi.s_axi_wready_i_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \gen_axi.write_cs[0]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \gen_axi.write_cs[1]_i_1\ : label is "soft_lutpair76";
begin
mi_arready(0) <= \^mi_arready\(0);
mi_awready(0) <= \^mi_awready\(0);
p_10_in <= \^p_10_in\;
p_11_in <= \^p_11_in\;
p_13_in <= \^p_13_in\;
p_17_in <= \^p_17_in\;
p_20_in(0) <= \^p_20_in\(0);
\gen_axi.read_cnt[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"74"
)
port map (
I0 => \gen_axi.read_cnt_reg__0__0\(0),
I1 => \^p_11_in\,
I2 => \gen_arbiter.m_mesg_i_reg[41]\(0),
O => p_0_in(0)
);
\gen_axi.read_cnt[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E22E"
)
port map (
I0 => \gen_arbiter.m_mesg_i_reg[41]\(1),
I1 => \^p_11_in\,
I2 => \gen_axi.read_cnt_reg__0__0\(0),
I3 => \gen_axi.read_cnt_reg__0\(1),
O => p_0_in(1)
);
\gen_axi.read_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FC03AAAA"
)
port map (
I0 => \gen_arbiter.m_mesg_i_reg[41]\(2),
I1 => \gen_axi.read_cnt_reg__0__0\(0),
I2 => \gen_axi.read_cnt_reg__0\(1),
I3 => \gen_axi.read_cnt_reg__0\(2),
I4 => \^p_11_in\,
O => p_0_in(2)
);
\gen_axi.read_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFC0003AAAAAAAA"
)
port map (
I0 => \gen_arbiter.m_mesg_i_reg[41]\(3),
I1 => \gen_axi.read_cnt_reg__0\(2),
I2 => \gen_axi.read_cnt_reg__0\(1),
I3 => \gen_axi.read_cnt_reg__0__0\(0),
I4 => \gen_axi.read_cnt_reg__0\(3),
I5 => \^p_11_in\,
O => p_0_in(3)
);
\gen_axi.read_cnt[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"C3AA"
)
port map (
I0 => \gen_arbiter.m_mesg_i_reg[41]\(4),
I1 => \gen_axi.read_cnt[4]_i_2_n_0\,
I2 => \gen_axi.read_cnt_reg__0\(4),
I3 => \^p_11_in\,
O => p_0_in(4)
);
\gen_axi.read_cnt[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(2),
I1 => \gen_axi.read_cnt_reg__0\(1),
I2 => \gen_axi.read_cnt_reg__0__0\(0),
I3 => \gen_axi.read_cnt_reg__0\(3),
O => \gen_axi.read_cnt[4]_i_2_n_0\
);
\gen_axi.read_cnt[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"C3AA"
)
port map (
I0 => \gen_arbiter.m_mesg_i_reg[41]\(5),
I1 => \gen_axi.read_cnt_reg__0\(5),
I2 => \gen_axi.read_cnt[5]_i_2_n_0\,
I3 => \^p_11_in\,
O => p_0_in(5)
);
\gen_axi.read_cnt[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(3),
I1 => \gen_axi.read_cnt_reg__0__0\(0),
I2 => \gen_axi.read_cnt_reg__0\(1),
I3 => \gen_axi.read_cnt_reg__0\(2),
I4 => \gen_axi.read_cnt_reg__0\(4),
O => \gen_axi.read_cnt[5]_i_2_n_0\
);
\gen_axi.read_cnt[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"C3AA"
)
port map (
I0 => \gen_arbiter.m_mesg_i_reg[41]\(6),
I1 => \gen_axi.read_cnt[7]_i_3_n_0\,
I2 => \gen_axi.read_cnt_reg__0\(6),
I3 => \^p_11_in\,
O => p_0_in(6)
);
\gen_axi.read_cnt[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8F80808080808080"
)
port map (
I0 => \gen_axi.s_axi_arready_i_i_2_n_0\,
I1 => mi_rready_1,
I2 => \^p_11_in\,
I3 => aa_mi_arvalid,
I4 => \gen_arbiter.m_target_hot_i_reg[1]\(0),
I5 => \^mi_arready\(0),
O => \gen_axi.read_cnt[7]_i_1_n_0\
);
\gen_axi.read_cnt[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FCAA03AA"
)
port map (
I0 => \gen_arbiter.m_mesg_i_reg[41]\(7),
I1 => \gen_axi.read_cnt[7]_i_3_n_0\,
I2 => \gen_axi.read_cnt_reg__0\(6),
I3 => \^p_11_in\,
I4 => \gen_axi.read_cnt_reg__0\(7),
O => p_0_in(7)
);
\gen_axi.read_cnt[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(5),
I1 => \gen_axi.read_cnt_reg__0\(4),
I2 => \gen_axi.read_cnt_reg__0\(2),
I3 => \gen_axi.read_cnt_reg__0\(1),
I4 => \gen_axi.read_cnt_reg__0__0\(0),
I5 => \gen_axi.read_cnt_reg__0\(3),
O => \gen_axi.read_cnt[7]_i_3_n_0\
);
\gen_axi.read_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(0),
Q => \gen_axi.read_cnt_reg__0__0\(0),
R => SR(0)
);
\gen_axi.read_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(1),
Q => \gen_axi.read_cnt_reg__0\(1),
R => SR(0)
);
\gen_axi.read_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(2),
Q => \gen_axi.read_cnt_reg__0\(2),
R => SR(0)
);
\gen_axi.read_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(3),
Q => \gen_axi.read_cnt_reg__0\(3),
R => SR(0)
);
\gen_axi.read_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(4),
Q => \gen_axi.read_cnt_reg__0\(4),
R => SR(0)
);
\gen_axi.read_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(5),
Q => \gen_axi.read_cnt_reg__0\(5),
R => SR(0)
);
\gen_axi.read_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(6),
Q => \gen_axi.read_cnt_reg__0\(6),
R => SR(0)
);
\gen_axi.read_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(7),
Q => \gen_axi.read_cnt_reg__0\(7),
R => SR(0)
);
\gen_axi.read_cs[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BFB0B0B0B0B0B0B0"
)
port map (
I0 => \gen_axi.s_axi_arready_i_i_2_n_0\,
I1 => mi_rready_1,
I2 => \^p_11_in\,
I3 => aa_mi_arvalid,
I4 => \gen_arbiter.m_target_hot_i_reg[1]\(0),
I5 => \^mi_arready\(0),
O => \gen_axi.read_cs[0]_i_1_n_0\
);
\gen_axi.read_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.read_cs[0]_i_1_n_0\,
Q => \^p_11_in\,
R => SR(0)
);
\gen_axi.s_axi_arready_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BFBB0000"
)
port map (
I0 => \^mi_arready\(0),
I1 => \^p_11_in\,
I2 => \gen_axi.s_axi_arready_i_i_2_n_0\,
I3 => mi_rready_1,
I4 => aresetn_d,
I5 => s_axi_rvalid_i,
O => \gen_axi.s_axi_arready_i_i_1_n_0\
);
\gen_axi.s_axi_arready_i_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \gen_axi.read_cnt[7]_i_3_n_0\,
I1 => \gen_axi.read_cnt_reg__0\(7),
I2 => \gen_axi.read_cnt_reg__0\(6),
O => \gen_axi.s_axi_arready_i_i_2_n_0\
);
\gen_axi.s_axi_arready_i_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \^mi_arready\(0),
I1 => \gen_arbiter.m_target_hot_i_reg[1]\(0),
I2 => aa_mi_arvalid,
I3 => \^p_11_in\,
O => s_axi_rvalid_i
);
\gen_axi.s_axi_arready_i_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_arready_i_i_1_n_0\,
Q => \^mi_arready\(0),
R => '0'
);
\gen_axi.s_axi_awready_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFA00CA"
)
port map (
I0 => \gen_axi.s_axi_awready_i_reg_0\,
I1 => mi_bready_1,
I2 => write_cs(1),
I3 => write_cs(0),
I4 => \^mi_awready\(0),
O => \gen_axi.s_axi_awready_i_i_1_n_0\
);
\gen_axi.s_axi_awready_i_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_awready_i_i_1_n_0\,
Q => \^mi_awready\(0),
R => SR(0)
);
\gen_axi.s_axi_bid_i[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0002"
)
port map (
I0 => Q(0),
I1 => write_cs(1),
I2 => write_cs(0),
I3 => \gen_axi.s_axi_awready_i_reg_0\,
I4 => \^p_20_in\(0),
O => \gen_axi.s_axi_bid_i[1]_i_1_n_0\
);
\gen_axi.s_axi_bid_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_bid_i[1]_i_1_n_0\,
Q => \^p_20_in\(0),
R => SR(0)
);
\gen_axi.s_axi_bvalid_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F5FF00C0"
)
port map (
I0 => mi_bready_1,
I1 => \write_cs0__0\,
I2 => write_cs(0),
I3 => write_cs(1),
I4 => \^p_17_in\,
O => \gen_axi.s_axi_bvalid_i_i_1_n_0\
);
\gen_axi.s_axi_bvalid_i_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_bvalid_i_i_1_n_0\,
Q => \^p_17_in\,
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_arbiter.m_mesg_i_reg[0]\,
Q => p_16_in(0),
R => SR(0)
);
\gen_axi.s_axi_rlast_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F8FFF800"
)
port map (
I0 => \^p_11_in\,
I1 => \gen_axi.s_axi_arready_i_i_2_n_0\,
I2 => \gen_axi.read_cs_reg[0]_0\,
I3 => \gen_axi.s_axi_rlast_i_i_3_n_0\,
I4 => \^p_13_in\,
O => \gen_axi.s_axi_rlast_i_i_1_n_0\
);
\gen_axi.s_axi_rlast_i_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF0100"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(3),
I1 => \gen_axi.read_cnt_reg__0\(2),
I2 => \gen_axi.read_cnt_reg__0\(1),
I3 => \gen_axi.s_axi_rlast_i_i_5_n_0\,
I4 => s_axi_rvalid_i,
O => \gen_axi.s_axi_rlast_i_i_3_n_0\
);
\gen_axi.s_axi_rlast_i_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(4),
I1 => \gen_axi.read_cnt_reg__0\(5),
I2 => \gen_axi.read_cnt_reg__0\(6),
I3 => \gen_axi.read_cnt_reg__0\(7),
I4 => mi_rready_1,
I5 => \^p_11_in\,
O => \gen_axi.s_axi_rlast_i_i_5_n_0\
);
\gen_axi.s_axi_rlast_i_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_rlast_i_i_1_n_0\,
Q => \^p_13_in\,
R => SR(0)
);
\gen_axi.s_axi_wready_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF5F0003"
)
port map (
I0 => \write_cs0__0\,
I1 => \gen_axi.s_axi_awready_i_reg_0\,
I2 => write_cs(0),
I3 => write_cs(1),
I4 => \^p_10_in\,
O => \gen_axi.s_axi_wready_i_i_1_n_0\
);
\gen_axi.s_axi_wready_i_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_wready_i_i_1_n_0\,
Q => \^p_10_in\,
R => SR(0)
);
\gen_axi.write_cs[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"C1F1"
)
port map (
I0 => \gen_axi.s_axi_awready_i_reg_0\,
I1 => write_cs(1),
I2 => write_cs(0),
I3 => \write_cs0__0\,
O => \gen_axi.write_cs[0]_i_1_n_0\
);
\gen_axi.write_cs[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"C8EA"
)
port map (
I0 => write_cs(1),
I1 => write_cs(0),
I2 => \write_cs0__0\,
I3 => mi_bready_1,
O => \gen_axi.write_cs[1]_i_1_n_0\
);
\gen_axi.write_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.write_cs[0]_i_1_n_0\,
Q => write_cs(0),
R => SR(0)
);
\gen_axi.write_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.write_cs[1]_i_1_n_0\,
Q => write_cs(1),
R => SR(0)
);
\m_valid_i_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \^p_17_in\,
I1 => mi_bready_1,
I2 => bready_carry(0),
O => m_valid_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_crossbar_v2_1_12_si_transactor is
port (
active_target_enc : out STD_LOGIC;
active_target_hot : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_arbiter.grant_hot_reg[1]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_arvalid_qual : out STD_LOGIC_VECTOR ( 0 to 0 );
rready_carry : out STD_LOGIC_VECTOR ( 0 to 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_arbiter.s_ready_i_reg[0]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\gen_arbiter.s_ready_i_reg[0]_0\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
\valid_qual_i3__1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
sel_4 : in STD_LOGIC;
\m_payload_i_reg[66]\ : in STD_LOGIC;
\gen_arbiter.last_rr_hot_reg[0]\ : in STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
p_2_in : in STD_LOGIC;
\m_payload_i_reg[66]_0\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 1 downto 0 );
st_mr_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
active_target_enc_0 : in STD_LOGIC;
\gen_arbiter.s_ready_i_reg[0]_1\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_crossbar_v2_1_12_si_transactor : entity is "axi_crossbar_v2_1_12_si_transactor";
end system_xbar_0_axi_crossbar_v2_1_12_si_transactor;
architecture STRUCTURE of system_xbar_0_axi_crossbar_v2_1_12_si_transactor is
signal accept_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^active_target_enc\ : STD_LOGIC;
signal \gen_arbiter.grant_hot[1]_i_15_n_0\ : STD_LOGIC;
signal \gen_arbiter.grant_hot[1]_i_8_n_0\ : STD_LOGIC;
signal \gen_arbiter.grant_hot[1]_i_9_n_0\ : STD_LOGIC;
signal \gen_single_thread.accept_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_single_thread.accept_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \^st_aa_arvalid_qual\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_arbiter.grant_hot[1]_i_15\ : label is "soft_lutpair191";
attribute SOFT_HLUTNM of \gen_single_thread.accept_cnt[0]_i_1\ : label is "soft_lutpair190";
attribute SOFT_HLUTNM of \gen_single_thread.accept_cnt[1]_i_1\ : label is "soft_lutpair190";
attribute SOFT_HLUTNM of \s_axi_rresp[1]_INST_0\ : label is "soft_lutpair191";
begin
active_target_enc <= \^active_target_enc\;
st_aa_arvalid_qual(0) <= \^st_aa_arvalid_qual\(0);
\gen_arbiter.grant_hot[1]_i_15\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_araddr(1),
I2 => s_axi_araddr(2),
I3 => \^active_target_enc\,
O => \gen_arbiter.grant_hot[1]_i_15_n_0\
);
\gen_arbiter.grant_hot[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B800B8000000"
)
port map (
I0 => \valid_qual_i3__1\(0),
I1 => sel_4,
I2 => \m_payload_i_reg[66]\,
I3 => \gen_arbiter.last_rr_hot_reg[0]\,
I4 => \gen_arbiter.grant_hot[1]_i_8_n_0\,
I5 => \gen_arbiter.grant_hot[1]_i_9_n_0\,
O => \gen_arbiter.grant_hot_reg[1]\
);
\gen_arbiter.grant_hot[1]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"4440444044404040"
)
port map (
I0 => sel_4,
I1 => \^active_target_enc\,
I2 => accept_cnt(0),
I3 => \m_payload_i_reg[66]_0\,
I4 => m_valid_i_reg,
I5 => m_valid_i_reg_0,
O => \gen_arbiter.grant_hot[1]_i_8_n_0\
);
\gen_arbiter.grant_hot[1]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00FF00E000FFFF"
)
port map (
I0 => m_valid_i_reg_0,
I1 => m_valid_i_reg,
I2 => \m_payload_i_reg[66]_0\,
I3 => \gen_arbiter.grant_hot[1]_i_15_n_0\,
I4 => accept_cnt(1),
I5 => accept_cnt(0),
O => \gen_arbiter.grant_hot[1]_i_9_n_0\
);
\gen_arbiter.qual_reg[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^st_aa_arvalid_qual\(0),
I1 => \gen_master_slots[1].r_issuing_cnt_reg[8]\,
I2 => s_axi_arvalid(0),
O => D(0)
);
\gen_arbiter.qual_reg[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"05FDFD05"
)
port map (
I0 => accept_cnt(1),
I1 => p_2_in,
I2 => accept_cnt(0),
I3 => \^active_target_enc\,
I4 => sel_4,
O => \^st_aa_arvalid_qual\(0)
);
\gen_master_slots[1].r_issuing_cnt[8]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"F8080808"
)
port map (
I0 => s_axi_rready(0),
I1 => \^active_target_enc\,
I2 => st_mr_rid(0),
I3 => s_axi_rready(1),
I4 => active_target_enc_0,
O => rready_carry(0)
);
\gen_single_thread.accept_cnt[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A54A"
)
port map (
I0 => \gen_arbiter.s_ready_i_reg[0]_1\,
I1 => accept_cnt(1),
I2 => p_2_in,
I3 => accept_cnt(0),
O => \gen_single_thread.accept_cnt[0]_i_1_n_0\
);
\gen_single_thread.accept_cnt[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9CC4"
)
port map (
I0 => p_2_in,
I1 => accept_cnt(1),
I2 => accept_cnt(0),
I3 => \gen_arbiter.s_ready_i_reg[0]_1\,
O => \gen_single_thread.accept_cnt[1]_i_1_n_0\
);
\gen_single_thread.accept_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_single_thread.accept_cnt[0]_i_1_n_0\,
Q => accept_cnt(0),
R => SR(0)
);
\gen_single_thread.accept_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_single_thread.accept_cnt[1]_i_1_n_0\,
Q => accept_cnt(1),
R => SR(0)
);
\gen_single_thread.active_target_enc_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_arbiter.s_ready_i_reg[0]\,
Q => \^active_target_enc\,
R => SR(0)
);
\gen_single_thread.active_target_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_arbiter.s_ready_i_reg[0]_0\,
Q => active_target_hot(0),
R => SR(0)
);
\s_axi_rresp[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^active_target_enc\,
I1 => Q(0),
O => s_axi_rresp(0)
);
\s_axi_rresp[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^active_target_enc\,
I1 => Q(1),
O => s_axi_rresp(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_xbar_0_axi_crossbar_v2_1_12_si_transactor__parameterized0\ is
port (
active_target_enc : out STD_LOGIC;
active_target_hot : out STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_awvalid_qual : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_single_thread.active_target_enc_reg[0]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\gen_single_thread.active_target_hot_reg[0]_0\ : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC;
st_mr_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
st_mr_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[2]\ : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_ready_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_xbar_0_axi_crossbar_v2_1_12_si_transactor__parameterized0\ : entity is "axi_crossbar_v2_1_12_si_transactor";
end \system_xbar_0_axi_crossbar_v2_1_12_si_transactor__parameterized0\;
architecture STRUCTURE of \system_xbar_0_axi_crossbar_v2_1_12_si_transactor__parameterized0\ is
signal accept_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^active_target_enc\ : STD_LOGIC;
signal \^active_target_hot\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_arbiter.qual_reg[0]_i_7_n_0\ : STD_LOGIC;
signal \gen_single_thread.accept_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_single_thread.accept_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_single_thread.accept_cnt[0]_i_1__0\ : label is "soft_lutpair192";
attribute SOFT_HLUTNM of \gen_single_thread.accept_cnt[1]_i_1__0\ : label is "soft_lutpair192";
begin
active_target_enc <= \^active_target_enc\;
active_target_hot(0) <= \^active_target_hot\(0);
s_axi_bvalid(0) <= \^s_axi_bvalid\(0);
\gen_arbiter.qual_reg[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFBFBBB11111111"
)
port map (
I0 => accept_cnt(0),
I1 => accept_cnt(1),
I2 => s_axi_bready(0),
I3 => m_valid_i_reg,
I4 => \m_payload_i_reg[3]\,
I5 => \gen_arbiter.qual_reg[0]_i_7_n_0\,
O => st_aa_awvalid_qual(0)
);
\gen_arbiter.qual_reg[0]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE01"
)
port map (
I0 => s_axi_awaddr(0),
I1 => s_axi_awaddr(1),
I2 => s_axi_awaddr(2),
I3 => \^active_target_enc\,
O => \gen_arbiter.qual_reg[0]_i_7_n_0\
);
\gen_single_thread.accept_cnt[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"A5554AAA"
)
port map (
I0 => s_ready_i_reg,
I1 => accept_cnt(1),
I2 => \^s_axi_bvalid\(0),
I3 => s_axi_bready(0),
I4 => accept_cnt(0),
O => \gen_single_thread.accept_cnt[0]_i_1__0_n_0\
);
\gen_single_thread.accept_cnt[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"87F0F070"
)
port map (
I0 => s_axi_bready(0),
I1 => \^s_axi_bvalid\(0),
I2 => accept_cnt(1),
I3 => accept_cnt(0),
I4 => s_ready_i_reg,
O => \gen_single_thread.accept_cnt[1]_i_1__0_n_0\
);
\gen_single_thread.accept_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_single_thread.accept_cnt[0]_i_1__0_n_0\,
Q => accept_cnt(0),
R => SR(0)
);
\gen_single_thread.accept_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_single_thread.accept_cnt[1]_i_1__0_n_0\,
Q => accept_cnt(1),
R => SR(0)
);
\gen_single_thread.active_target_enc_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_single_thread.active_target_enc_reg[0]_0\,
Q => \^active_target_enc\,
R => SR(0)
);
\gen_single_thread.active_target_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_single_thread.active_target_hot_reg[0]_0\,
Q => \^active_target_hot\(0),
R => SR(0)
);
\s_axi_bvalid[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF08080808080808"
)
port map (
I0 => \^active_target_enc\,
I1 => st_mr_bvalid(1),
I2 => st_mr_bid(0),
I3 => \m_payload_i_reg[2]\,
I4 => \^active_target_hot\(0),
I5 => st_mr_bvalid(0),
O => \^s_axi_bvalid\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_xbar_0_axi_crossbar_v2_1_12_si_transactor__parameterized1\ is
port (
active_target_enc : out STD_LOGIC;
active_target_hot : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_arbiter.grant_hot_reg[1]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_arvalid_qual : out STD_LOGIC_VECTOR ( 0 to 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_arbiter.s_ready_i_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\gen_arbiter.s_ready_i_reg[1]_0\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
\valid_qual_i3__1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
sel_4 : in STD_LOGIC;
\m_payload_i_reg[66]\ : in STD_LOGIC;
next_enc : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
p_2_in : in STD_LOGIC;
\m_payload_i_reg[67]\ : in STD_LOGIC;
\m_payload_i_reg[66]_0\ : in STD_LOGIC;
st_mr_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_arbiter.s_ready_i_reg[1]_1\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_xbar_0_axi_crossbar_v2_1_12_si_transactor__parameterized1\ : entity is "axi_crossbar_v2_1_12_si_transactor";
end \system_xbar_0_axi_crossbar_v2_1_12_si_transactor__parameterized1\;
architecture STRUCTURE of \system_xbar_0_axi_crossbar_v2_1_12_si_transactor__parameterized1\ is
signal accept_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^active_target_enc\ : STD_LOGIC;
signal \^active_target_hot\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_arbiter.grant_hot[1]_i_10_n_0\ : STD_LOGIC;
signal \gen_arbiter.grant_hot[1]_i_12_n_0\ : STD_LOGIC;
signal \gen_arbiter.grant_hot[1]_i_6_n_0\ : STD_LOGIC;
signal \gen_arbiter.grant_hot[1]_i_7_n_0\ : STD_LOGIC;
signal \gen_single_thread.accept_cnt[0]_i_1__1_n_0\ : STD_LOGIC;
signal \gen_single_thread.accept_cnt[1]_i_1__1_n_0\ : STD_LOGIC;
signal \^st_aa_arvalid_qual\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_arbiter.grant_hot[1]_i_12\ : label is "soft_lutpair195";
attribute SOFT_HLUTNM of \gen_single_thread.accept_cnt[0]_i_1__1\ : label is "soft_lutpair196";
attribute SOFT_HLUTNM of \gen_single_thread.accept_cnt[1]_i_1__1\ : label is "soft_lutpair196";
attribute SOFT_HLUTNM of \s_axi_rresp[3]_INST_0\ : label is "soft_lutpair195";
begin
active_target_enc <= \^active_target_enc\;
active_target_hot(0) <= \^active_target_hot\(0);
st_aa_arvalid_qual(0) <= \^st_aa_arvalid_qual\(0);
\gen_arbiter.grant_hot[1]_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^active_target_hot\(0),
I1 => st_mr_rvalid(0),
I2 => s_axi_rready(0),
O => \gen_arbiter.grant_hot[1]_i_10_n_0\
);
\gen_arbiter.grant_hot[1]_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_araddr(1),
I2 => s_axi_araddr(2),
I3 => \^active_target_enc\,
O => \gen_arbiter.grant_hot[1]_i_12_n_0\
);
\gen_arbiter.grant_hot[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B800B8000000"
)
port map (
I0 => \valid_qual_i3__1\(0),
I1 => sel_4,
I2 => \m_payload_i_reg[66]\,
I3 => next_enc(0),
I4 => \gen_arbiter.grant_hot[1]_i_6_n_0\,
I5 => \gen_arbiter.grant_hot[1]_i_7_n_0\,
O => \gen_arbiter.grant_hot_reg[1]\
);
\gen_arbiter.grant_hot[1]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444444404040"
)
port map (
I0 => sel_4,
I1 => \^active_target_enc\,
I2 => accept_cnt(0),
I3 => \gen_arbiter.grant_hot[1]_i_10_n_0\,
I4 => \m_payload_i_reg[66]_0\,
I5 => \m_payload_i_reg[67]\,
O => \gen_arbiter.grant_hot[1]_i_6_n_0\
);
\gen_arbiter.grant_hot[1]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00FF00EA00FFFF"
)
port map (
I0 => \m_payload_i_reg[67]\,
I1 => \m_payload_i_reg[66]_0\,
I2 => \gen_arbiter.grant_hot[1]_i_10_n_0\,
I3 => \gen_arbiter.grant_hot[1]_i_12_n_0\,
I4 => accept_cnt(1),
I5 => accept_cnt(0),
O => \gen_arbiter.grant_hot[1]_i_7_n_0\
);
\gen_arbiter.qual_reg[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^st_aa_arvalid_qual\(0),
I1 => \gen_master_slots[1].r_issuing_cnt_reg[8]\,
I2 => s_axi_arvalid(0),
O => D(0)
);
\gen_arbiter.qual_reg[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"05FDFD05"
)
port map (
I0 => accept_cnt(1),
I1 => p_2_in,
I2 => accept_cnt(0),
I3 => \^active_target_enc\,
I4 => sel_4,
O => \^st_aa_arvalid_qual\(0)
);
\gen_single_thread.accept_cnt[0]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A54A"
)
port map (
I0 => \gen_arbiter.s_ready_i_reg[1]_1\,
I1 => accept_cnt(1),
I2 => p_2_in,
I3 => accept_cnt(0),
O => \gen_single_thread.accept_cnt[0]_i_1__1_n_0\
);
\gen_single_thread.accept_cnt[1]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9CC4"
)
port map (
I0 => p_2_in,
I1 => accept_cnt(1),
I2 => accept_cnt(0),
I3 => \gen_arbiter.s_ready_i_reg[1]_1\,
O => \gen_single_thread.accept_cnt[1]_i_1__1_n_0\
);
\gen_single_thread.accept_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_single_thread.accept_cnt[0]_i_1__1_n_0\,
Q => accept_cnt(0),
R => SR(0)
);
\gen_single_thread.accept_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_single_thread.accept_cnt[1]_i_1__1_n_0\,
Q => accept_cnt(1),
R => SR(0)
);
\gen_single_thread.active_target_enc_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_arbiter.s_ready_i_reg[1]\,
Q => \^active_target_enc\,
R => SR(0)
);
\gen_single_thread.active_target_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_arbiter.s_ready_i_reg[1]_0\,
Q => \^active_target_hot\(0),
R => SR(0)
);
\s_axi_rresp[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^active_target_enc\,
I1 => Q(0),
O => s_axi_rresp(0)
);
\s_axi_rresp[3]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^active_target_enc\,
I1 => Q(1),
O => s_axi_rresp(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_xbar_0_axi_crossbar_v2_1_12_si_transactor__parameterized2\ is
port (
active_target_enc : out STD_LOGIC;
active_target_hot : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_arbiter.grant_hot_reg[2]\ : out STD_LOGIC;
st_aa_awvalid_qual : out STD_LOGIC_VECTOR ( 0 to 0 );
bready_carry : out STD_LOGIC_VECTOR ( 0 to 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_single_thread.active_target_enc_reg[0]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\gen_single_thread.active_target_hot_reg[0]_0\ : in STD_LOGIC;
next_enc : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_single_thread.active_target_enc_reg[0]_1\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC;
sel_4 : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
st_mr_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
active_target_enc_0 : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_xbar_0_axi_crossbar_v2_1_12_si_transactor__parameterized2\ : entity is "axi_crossbar_v2_1_12_si_transactor";
end \system_xbar_0_axi_crossbar_v2_1_12_si_transactor__parameterized2\;
architecture STRUCTURE of \system_xbar_0_axi_crossbar_v2_1_12_si_transactor__parameterized2\ is
signal accept_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^active_target_enc\ : STD_LOGIC;
signal \gen_arbiter.grant_hot[2]_i_7_n_0\ : STD_LOGIC;
signal \gen_single_thread.accept_cnt[0]_i_1__2_n_0\ : STD_LOGIC;
signal \gen_single_thread.accept_cnt[1]_i_1__2_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_single_thread.accept_cnt[0]_i_1__2\ : label is "soft_lutpair197";
attribute SOFT_HLUTNM of \gen_single_thread.accept_cnt[1]_i_1__2\ : label is "soft_lutpair197";
begin
active_target_enc <= \^active_target_enc\;
\gen_arbiter.grant_hot[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAA020200000000"
)
port map (
I0 => next_enc(0),
I1 => accept_cnt(0),
I2 => accept_cnt(1),
I3 => \gen_single_thread.active_target_enc_reg[0]_1\,
I4 => \gen_arbiter.grant_hot[2]_i_7_n_0\,
I5 => m_valid_i_reg,
O => \gen_arbiter.grant_hot_reg[2]\
);
\gen_arbiter.grant_hot[2]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE01"
)
port map (
I0 => s_axi_awaddr(0),
I1 => s_axi_awaddr(1),
I2 => s_axi_awaddr(2),
I3 => \^active_target_enc\,
O => \gen_arbiter.grant_hot[2]_i_7_n_0\
);
\gen_arbiter.qual_reg[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"1111FBBBFBBB1111"
)
port map (
I0 => accept_cnt(0),
I1 => accept_cnt(1),
I2 => s_axi_bready(1),
I3 => \m_payload_i_reg[3]\,
I4 => sel_4,
I5 => \^active_target_enc\,
O => st_aa_awvalid_qual(0)
);
\gen_single_thread.accept_cnt[0]_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"A5554AAA"
)
port map (
I0 => s_ready_i_reg,
I1 => accept_cnt(1),
I2 => \m_payload_i_reg[3]\,
I3 => s_axi_bready(1),
I4 => accept_cnt(0),
O => \gen_single_thread.accept_cnt[0]_i_1__2_n_0\
);
\gen_single_thread.accept_cnt[1]_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"87F0F070"
)
port map (
I0 => s_axi_bready(1),
I1 => \m_payload_i_reg[3]\,
I2 => accept_cnt(1),
I3 => accept_cnt(0),
I4 => s_ready_i_reg,
O => \gen_single_thread.accept_cnt[1]_i_1__2_n_0\
);
\gen_single_thread.accept_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_single_thread.accept_cnt[0]_i_1__2_n_0\,
Q => accept_cnt(0),
R => SR(0)
);
\gen_single_thread.accept_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_single_thread.accept_cnt[1]_i_1__2_n_0\,
Q => accept_cnt(1),
R => SR(0)
);
\gen_single_thread.active_target_enc_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_single_thread.active_target_enc_reg[0]_0\,
Q => \^active_target_enc\,
R => SR(0)
);
\gen_single_thread.active_target_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_single_thread.active_target_hot_reg[0]_0\,
Q => active_target_hot(0),
R => SR(0)
);
\m_valid_i_i_2__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8F808080"
)
port map (
I0 => s_axi_bready(1),
I1 => \^active_target_enc\,
I2 => st_mr_bid(0),
I3 => s_axi_bready(0),
I4 => active_target_enc_0,
O => bready_carry(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_crossbar_v2_1_12_splitter is
port (
\gen_single_thread.active_target_hot_reg[0]\ : out STD_LOGIC;
\s_axi_awready[0]\ : out STD_LOGIC;
\gen_single_thread.active_target_enc_reg[0]\ : out STD_LOGIC;
\gen_arbiter.qual_reg_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_rep[0].fifoaddr_reg[0]\ : out STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
active_target_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
active_target_enc : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].w_issuing_cnt_reg[8]\ : in STD_LOGIC;
ss_wr_awready_0 : in STD_LOGIC;
ss_aa_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_crossbar_v2_1_12_splitter : entity is "axi_crossbar_v2_1_12_splitter";
end system_xbar_0_axi_crossbar_v2_1_12_splitter;
architecture STRUCTURE of system_xbar_0_axi_crossbar_v2_1_12_splitter is
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_awready[0]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_primitive_shifter.gen_srls[0].srl_inst_i_4\ : label is "soft_lutpair193";
attribute SOFT_HLUTNM of \s_axi_awready[0]_INST_0\ : label is "soft_lutpair193";
begin
m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
\s_axi_awready[0]\ <= \^s_axi_awready[0]\;
\gen_arbiter.qual_reg[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => s_axi_awvalid(0),
I1 => \^m_ready_d\(0),
I2 => \gen_master_slots[1].w_issuing_cnt_reg[8]\,
O => \gen_arbiter.qual_reg_reg[0]\(0)
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^m_ready_d\(1),
I1 => s_axi_awvalid(0),
O => \gen_rep[0].fifoaddr_reg[0]\
);
\gen_single_thread.active_target_enc[0]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFFFE00"
)
port map (
I0 => s_axi_awaddr(0),
I1 => s_axi_awaddr(1),
I2 => s_axi_awaddr(2),
I3 => \^s_axi_awready[0]\,
I4 => active_target_enc,
O => \gen_single_thread.active_target_enc_reg[0]\
);
\gen_single_thread.active_target_hot[0]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0100"
)
port map (
I0 => s_axi_awaddr(2),
I1 => s_axi_awaddr(1),
I2 => s_axi_awaddr(0),
I3 => \^s_axi_awready[0]\,
I4 => active_target_hot(0),
O => \gen_single_thread.active_target_hot_reg[0]\
);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C0008000C0000"
)
port map (
I0 => s_axi_awvalid(0),
I1 => aresetn_d,
I2 => ss_wr_awready_0,
I3 => \^m_ready_d\(1),
I4 => \^m_ready_d\(0),
I5 => ss_aa_awready(0),
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000CC80"
)
port map (
I0 => s_axi_awvalid(0),
I1 => aresetn_d,
I2 => ss_wr_awready_0,
I3 => \^m_ready_d\(1),
I4 => \^m_ready_d\(0),
I5 => ss_aa_awready(0),
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
\s_axi_awready[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"EEE0"
)
port map (
I0 => ss_wr_awready_0,
I1 => \^m_ready_d\(1),
I2 => \^m_ready_d\(0),
I3 => ss_aa_awready(0),
O => \^s_axi_awready[0]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_crossbar_v2_1_12_splitter_2 is
port (
\gen_single_thread.active_target_hot_reg[0]\ : out STD_LOGIC;
\s_axi_awready[2]\ : out STD_LOGIC;
\gen_single_thread.active_target_enc_reg[0]\ : out STD_LOGIC;
\gen_arbiter.qual_reg_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_rep[0].fifoaddr_reg[0]\ : out STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
active_target_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
active_target_enc : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_awvalid_qual : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC;
ss_wr_awready_2 : in STD_LOGIC;
ss_aa_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_crossbar_v2_1_12_splitter_2 : entity is "axi_crossbar_v2_1_12_splitter";
end system_xbar_0_axi_crossbar_v2_1_12_splitter_2;
architecture STRUCTURE of system_xbar_0_axi_crossbar_v2_1_12_splitter_2 is
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_awready[2]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_primitive_shifter.gen_srls[0].srl_inst_i_4__0\ : label is "soft_lutpair198";
attribute SOFT_HLUTNM of \s_axi_awready[2]_INST_0\ : label is "soft_lutpair198";
begin
m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
\s_axi_awready[2]\ <= \^s_axi_awready[2]\;
\gen_arbiter.qual_reg[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FDDD"
)
port map (
I0 => s_axi_awvalid(0),
I1 => \^m_ready_d\(0),
I2 => st_aa_awvalid_qual(0),
I3 => m_valid_i_reg,
O => \gen_arbiter.qual_reg_reg[2]\(0)
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^m_ready_d\(1),
I1 => s_axi_awvalid(0),
O => \gen_rep[0].fifoaddr_reg[0]\
);
\gen_single_thread.active_target_enc[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFFFE00"
)
port map (
I0 => s_axi_awaddr(0),
I1 => s_axi_awaddr(1),
I2 => s_axi_awaddr(2),
I3 => \^s_axi_awready[2]\,
I4 => active_target_enc,
O => \gen_single_thread.active_target_enc_reg[0]\
);
\gen_single_thread.active_target_hot[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0100"
)
port map (
I0 => s_axi_awaddr(2),
I1 => s_axi_awaddr(1),
I2 => s_axi_awaddr(0),
I3 => \^s_axi_awready[2]\,
I4 => active_target_hot(0),
O => \gen_single_thread.active_target_hot_reg[0]\
);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C0008000C0000"
)
port map (
I0 => s_axi_awvalid(0),
I1 => aresetn_d,
I2 => ss_wr_awready_2,
I3 => \^m_ready_d\(1),
I4 => \^m_ready_d\(0),
I5 => ss_aa_awready(0),
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000CC80"
)
port map (
I0 => s_axi_awvalid(0),
I1 => aresetn_d,
I2 => ss_wr_awready_2,
I3 => \^m_ready_d\(1),
I4 => \^m_ready_d\(0),
I5 => ss_aa_awready(0),
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
\s_axi_awready[2]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"EEE0"
)
port map (
I0 => ss_wr_awready_2,
I1 => \^m_ready_d\(1),
I2 => \^m_ready_d\(0),
I3 => ss_aa_awready(0),
O => \^s_axi_awready[2]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_crossbar_v2_1_12_splitter_4 is
port (
aa_sa_awready : out STD_LOGIC;
\gen_arbiter.grant_hot_reg[2]\ : out STD_LOGIC;
m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
aresetn_d : in STD_LOGIC;
aa_sa_awvalid : in STD_LOGIC;
mi_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_arbiter.m_target_hot_i_reg[0]\ : in STD_LOGIC;
\gen_arbiter.m_target_hot_i_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_crossbar_v2_1_12_splitter_4 : entity is "axi_crossbar_v2_1_12_splitter";
end system_xbar_0_axi_crossbar_v2_1_12_splitter_4;
architecture STRUCTURE of system_xbar_0_axi_crossbar_v2_1_12_splitter_4 is
signal \^aa_sa_awready\ : STD_LOGIC;
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_4_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_arbiter.grant_hot[2]_i_5\ : label is "soft_lutpair201";
attribute SOFT_HLUTNM of \m_ready_d[1]_i_4\ : label is "soft_lutpair201";
begin
aa_sa_awready <= \^aa_sa_awready\;
m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
\gen_arbiter.grant_hot[2]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^aa_sa_awready\,
I1 => aa_sa_awvalid,
I2 => aresetn_d,
O => \gen_arbiter.grant_hot_reg[2]\
);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FCF80000"
)
port map (
I0 => Q(1),
I1 => aa_sa_awvalid,
I2 => \^m_ready_d\(0),
I3 => Q(0),
I4 => aresetn_d,
I5 => \^aa_sa_awready\,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFCFFCCFFF0AA00"
)
port map (
I0 => \^m_ready_d\(0),
I1 => mi_awready(0),
I2 => m_axi_awready(0),
I3 => \^m_ready_d\(1),
I4 => Q(0),
I5 => Q(1),
O => \^aa_sa_awready\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFF2F22"
)
port map (
I0 => m_axi_awready(0),
I1 => \gen_arbiter.m_target_hot_i_reg[0]\,
I2 => \gen_arbiter.m_target_hot_i_reg[1]\,
I3 => mi_awready(0),
I4 => \^m_ready_d\(1),
I5 => \m_ready_d[1]_i_4_n_0\,
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d[1]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^aa_sa_awready\,
I1 => aresetn_d,
O => \m_ready_d[1]_i_4_n_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl is
port (
push : out STD_LOGIC;
\storage_data1_reg[0]\ : out STD_LOGIC;
fifoaddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
aclk : in STD_LOGIC;
out0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
\FSM_onehot_state_reg[0]\ : in STD_LOGIC;
\m_aready__1\ : in STD_LOGIC;
\FSM_onehot_state_reg[1]\ : in STD_LOGIC;
m_select_enc : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
\storage_data1_reg[1]\ : in STD_LOGIC;
\m_ready_d_reg[1]\ : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl : entity is "axi_data_fifo_v2_1_10_ndeep_srl";
end system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl;
architecture STRUCTURE of system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl is
signal \gen_primitive_shifter.gen_srls[0].srl_inst_i_2_n_0\ : STD_LOGIC;
signal \gen_primitive_shifter.gen_srls[0].srl_inst_i_3__0_n_0\ : STD_LOGIC;
signal \^push\ : STD_LOGIC;
signal \storage_data1[0]_i_2_n_0\ : STD_LOGIC;
signal storage_data2 : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "SRLC32E";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[2].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[2].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_primitive_shifter.gen_srls[0].srl_inst_i_2\ : label is "soft_lutpair199";
attribute SOFT_HLUTNM of \storage_data1[0]_i_2\ : label is "soft_lutpair199";
begin
push <= \^push\;
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => fifoaddr(0),
A1 => fifoaddr(1),
A2 => '0',
A3 => '0',
CE => \^push\,
CLK => aclk,
D => \gen_primitive_shifter.gen_srls[0].srl_inst_i_2_n_0\,
Q => storage_data2
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FF007000700070"
)
port map (
I0 => \gen_primitive_shifter.gen_srls[0].srl_inst_i_3__0_n_0\,
I1 => \storage_data1_reg[1]\,
I2 => out0(1),
I3 => \m_ready_d_reg[1]\,
I4 => out0(0),
I5 => s_ready_i_reg,
O => \^push\
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => s_axi_awaddr(0),
I1 => s_axi_awaddr(1),
I2 => s_axi_awaddr(2),
O => \gen_primitive_shifter.gen_srls[0].srl_inst_i_2_n_0\
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => s_axi_wvalid(0),
I1 => m_valid_i_reg,
I2 => s_axi_wlast(0),
O => \gen_primitive_shifter.gen_srls[0].srl_inst_i_3__0_n_0\
);
\storage_data1[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAFABAFAAA0A8A0"
)
port map (
I0 => \storage_data1[0]_i_2_n_0\,
I1 => out0(0),
I2 => \FSM_onehot_state_reg[0]\,
I3 => \m_aready__1\,
I4 => \FSM_onehot_state_reg[1]\,
I5 => m_select_enc,
O => \storage_data1_reg[0]\
);
\storage_data1[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"BBBBBBB8"
)
port map (
I0 => storage_data2,
I1 => out0(0),
I2 => s_axi_awaddr(0),
I3 => s_axi_awaddr(1),
I4 => s_axi_awaddr(2),
O => \storage_data1[0]_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl_6 is
port (
push : out STD_LOGIC;
\storage_data1_reg[0]\ : out STD_LOGIC;
fifoaddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
aclk : in STD_LOGIC;
out0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
\FSM_onehot_state_reg[0]\ : in STD_LOGIC;
\m_aready__1\ : in STD_LOGIC;
\FSM_onehot_state_reg[1]\ : in STD_LOGIC;
\storage_data1_reg[0]_0\ : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
\storage_data1_reg[1]\ : in STD_LOGIC;
\m_ready_d_reg[1]\ : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl_6 : entity is "axi_data_fifo_v2_1_10_ndeep_srl";
end system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl_6;
architecture STRUCTURE of system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl_6 is
signal \gen_primitive_shifter.gen_srls[0].srl_inst_i_2__0_n_0\ : STD_LOGIC;
signal \gen_primitive_shifter.gen_srls[0].srl_inst_i_3_n_0\ : STD_LOGIC;
signal \^push\ : STD_LOGIC;
signal \storage_data1[0]_i_2__0_n_0\ : STD_LOGIC;
signal storage_data2 : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "SRLC32E";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_primitive_shifter.gen_srls[0].srl_inst_i_2__0\ : label is "soft_lutpair194";
attribute SOFT_HLUTNM of \storage_data1[0]_i_2__0\ : label is "soft_lutpair194";
begin
push <= \^push\;
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => fifoaddr(0),
A1 => fifoaddr(1),
A2 => '0',
A3 => '0',
CE => \^push\,
CLK => aclk,
D => \gen_primitive_shifter.gen_srls[0].srl_inst_i_2__0_n_0\,
Q => storage_data2
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FF007000700070"
)
port map (
I0 => \gen_primitive_shifter.gen_srls[0].srl_inst_i_3_n_0\,
I1 => \storage_data1_reg[1]\,
I2 => out0(1),
I3 => \m_ready_d_reg[1]\,
I4 => out0(0),
I5 => s_ready_i_reg,
O => \^push\
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => s_axi_awaddr(0),
I1 => s_axi_awaddr(1),
I2 => s_axi_awaddr(2),
O => \gen_primitive_shifter.gen_srls[0].srl_inst_i_2__0_n_0\
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_valid_i_reg,
I1 => s_axi_wvalid(0),
I2 => s_axi_wlast(0),
O => \gen_primitive_shifter.gen_srls[0].srl_inst_i_3_n_0\
);
\storage_data1[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAFABAFAAA0A8A0"
)
port map (
I0 => \storage_data1[0]_i_2__0_n_0\,
I1 => out0(0),
I2 => \FSM_onehot_state_reg[0]\,
I3 => \m_aready__1\,
I4 => \FSM_onehot_state_reg[1]\,
I5 => \storage_data1_reg[0]_0\,
O => \storage_data1_reg[0]\
);
\storage_data1[0]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"BBBBBBB8"
)
port map (
I0 => storage_data2,
I1 => out0(0),
I2 => s_axi_awaddr(0),
I3 => s_axi_awaddr(1),
I4 => s_axi_awaddr(2),
O => \storage_data1[0]_i_2__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl_7 is
port (
\storage_data1_reg[0]\ : out STD_LOGIC;
push : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 1 downto 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl_7 : entity is "axi_data_fifo_v2_1_10_ndeep_srl";
end system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl_7;
architecture STRUCTURE of system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl_7 is
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "SRLC32E";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
begin
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => A(0),
A1 => A(1),
A2 => '0',
A3 => '0',
CE => push,
CLK => aclk,
D => '0',
Q => \storage_data1_reg[0]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl_8 is
port (
m_valid_i_reg : out STD_LOGIC;
\storage_data1_reg[1]\ : out STD_LOGIC;
push : in STD_LOGIC;
aa_wm_awgrant_enc : in STD_LOGIC_VECTOR ( 0 to 0 );
A : in STD_LOGIC_VECTOR ( 1 downto 0 );
aclk : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
\storage_data1_reg[1]_0\ : in STD_LOGIC;
m_select_enc_0 : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
p_10_in : in STD_LOGIC;
m_select_enc_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_avalid_0 : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_avalid_1 : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl_8 : entity is "axi_data_fifo_v2_1_10_ndeep_srl";
end system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl_8;
architecture STRUCTURE of system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl_8 is
signal m_valid_i_i_5_n_0 : STD_LOGIC;
signal p_2_out : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "SRLC32E";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
begin
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => A(0),
A1 => A(1),
A2 => '0',
A3 => '0',
CE => push,
CLK => aclk,
D => aa_wm_awgrant_enc(0),
Q => p_2_out
);
\m_valid_i_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"15555555FFFFFFFF"
)
port map (
I0 => m_valid_i_reg_0,
I1 => m_valid_i_i_5_n_0,
I2 => \storage_data1_reg[1]_0\,
I3 => m_select_enc_0,
I4 => s_axi_wlast(0),
I5 => p_10_in,
O => m_valid_i_reg
);
m_valid_i_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => m_select_enc_1(0),
I1 => m_avalid_0,
I2 => s_axi_wvalid(0),
I3 => m_avalid_1,
O => m_valid_i_i_5_n_0
);
\storage_data1[1]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => p_2_out,
I1 => \out\(0),
I2 => aa_wm_awgrant_enc(0),
O => \storage_data1_reg[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl__parameterized8\ is
port (
\storage_data1_reg[0]\ : out STD_LOGIC;
push : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
out0 : in STD_LOGIC_VECTOR ( 0 to 0 );
\FSM_onehot_state_reg[0]\ : in STD_LOGIC;
\m_aready__1\ : in STD_LOGIC;
\FSM_onehot_state_reg[1]\ : in STD_LOGIC;
m_select_enc_0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl__parameterized8\ : entity is "axi_data_fifo_v2_1_10_ndeep_srl";
end \system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl__parameterized8\;
architecture STRUCTURE of \system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl__parameterized8\ is
signal \gen_primitive_shifter.gen_srls[0].srl_inst_n_0\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "SRLC32E";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
begin
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => A(0),
A1 => A(1),
A2 => A(2),
A3 => '0',
CE => push,
CLK => aclk,
D => '0',
Q => \gen_primitive_shifter.gen_srls[0].srl_inst_n_0\
);
\storage_data1[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"888F8B8F88808880"
)
port map (
I0 => \gen_primitive_shifter.gen_srls[0].srl_inst_n_0\,
I1 => out0(0),
I2 => \FSM_onehot_state_reg[0]\,
I3 => \m_aready__1\,
I4 => \FSM_onehot_state_reg[1]\,
I5 => m_select_enc_0(0),
O => \storage_data1_reg[0]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl__parameterized9\ is
port (
push : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
\storage_data1_reg[1]\ : out STD_LOGIC;
aa_wm_awgrant_enc : in STD_LOGIC_VECTOR ( 0 to 0 );
A : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
out0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_arbiter.m_valid_i_reg\ : in STD_LOGIC;
m_select_enc_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_avalid : in STD_LOGIC;
\storage_data1_reg[0]\ : in STD_LOGIC;
m_select_enc : in STD_LOGIC;
\storage_data1_reg[1]_0\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
\FSM_onehot_state_reg[0]\ : in STD_LOGIC;
\m_aready__1\ : in STD_LOGIC;
\FSM_onehot_state_reg[1]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl__parameterized9\ : entity is "axi_data_fifo_v2_1_10_ndeep_srl";
end \system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl__parameterized9\;
architecture STRUCTURE of \system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl__parameterized9\ is
signal \gen_primitive_shifter.gen_srls[0].srl_inst_i_2__1_n_0\ : STD_LOGIC;
signal \^m_axi_wvalid\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_0_in : STD_LOGIC_VECTOR ( 1 to 1 );
signal p_2_out : STD_LOGIC;
signal \^push\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "SRLC32E";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
begin
m_axi_wvalid(0) <= \^m_axi_wvalid\(0);
push <= \^push\;
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => A(0),
A1 => A(1),
A2 => A(2),
A3 => '0',
CE => \^push\,
CLK => aclk,
D => aa_wm_awgrant_enc(0),
Q => p_2_out
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00FF0070"
)
port map (
I0 => \gen_primitive_shifter.gen_srls[0].srl_inst_i_2__1_n_0\,
I1 => \^m_axi_wvalid\(0),
I2 => out0(1),
I3 => \gen_arbiter.m_valid_i_reg\,
I4 => out0(0),
O => \^push\
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_2__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"44400040"
)
port map (
I0 => m_select_enc_0(0),
I1 => m_axi_wready(0),
I2 => s_axi_wlast(0),
I3 => \storage_data1_reg[1]_0\,
I4 => s_axi_wlast(1),
O => \gen_primitive_shifter.gen_srls[0].srl_inst_i_2__1_n_0\
);
\m_axi_wvalid[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4044404040404040"
)
port map (
I0 => m_select_enc_0(0),
I1 => m_avalid,
I2 => \storage_data1_reg[0]\,
I3 => m_select_enc,
I4 => \storage_data1_reg[1]_0\,
I5 => m_valid_i_reg,
O => \^m_axi_wvalid\(0)
);
\storage_data1[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAFABAFAAA0A8A0"
)
port map (
I0 => p_0_in(1),
I1 => out0(0),
I2 => \FSM_onehot_state_reg[0]\,
I3 => \m_aready__1\,
I4 => \FSM_onehot_state_reg[1]\,
I5 => \storage_data1_reg[1]_0\,
O => \storage_data1_reg[1]\
);
\storage_data1[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => p_2_out,
I1 => out0(0),
I2 => aa_wm_awgrant_enc(0),
O => p_0_in(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized1\ is
port (
s_ready_i_reg_0 : out STD_LOGIC;
mi_bready_1 : out STD_LOGIC;
\m_payload_i_reg[3]_0\ : out STD_LOGIC;
s_ready_i_reg_1 : out STD_LOGIC;
\gen_arbiter.grant_hot_reg[2]\ : out STD_LOGIC;
\gen_arbiter.grant_hot_reg[2]_0\ : out STD_LOGIC;
\s_axi_bvalid[2]\ : out STD_LOGIC;
\gen_arbiter.grant_hot_reg[2]_1\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
\gen_axi.s_axi_bvalid_i_reg\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
p_20_in : in STD_LOGIC_VECTOR ( 0 to 0 );
p_17_in : in STD_LOGIC;
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
sel_4 : in STD_LOGIC;
w_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_awvalid_qual : in STD_LOGIC_VECTOR ( 0 to 0 );
\valid_qual_i3__1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_arbiter.last_rr_hot_reg[0]\ : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_single_thread.active_target_hot_reg[0]\ : in STD_LOGIC;
active_target_enc_2 : in STD_LOGIC;
\m_payload_i_reg[2]\ : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
active_target_hot_3 : in STD_LOGIC_VECTOR ( 0 to 0 );
active_target_enc_4 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_11_axic_register_slice";
end \system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized1\;
architecture STRUCTURE of \system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized1\ is
signal \m_payload_i[3]_i_1__1_n_0\ : STD_LOGIC;
signal \^m_payload_i_reg[3]_0\ : STD_LOGIC;
signal \s_ready_i_i_1__3_n_0\ : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal \^s_ready_i_reg_1\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_arbiter.qual_reg[0]_i_6\ : label is "soft_lutpair185";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair185";
begin
\m_payload_i_reg[3]_0\ <= \^m_payload_i_reg[3]_0\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
s_ready_i_reg_1 <= \^s_ready_i_reg_1\;
\gen_arbiter.grant_hot[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF00450000000000"
)
port map (
I0 => sel_4,
I1 => \^s_ready_i_reg_1\,
I2 => w_issuing_cnt(0),
I3 => st_aa_awvalid_qual(0),
I4 => \valid_qual_i3__1\(0),
I5 => \gen_arbiter.last_rr_hot_reg[0]\,
O => \gen_arbiter.grant_hot_reg[2]\
);
\gen_arbiter.grant_hot[2]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"57777777"
)
port map (
I0 => s_axi_bready(1),
I1 => \gen_single_thread.active_target_hot_reg[0]\,
I2 => active_target_enc_2,
I3 => \^s_ready_i_reg_0\,
I4 => \^m_payload_i_reg[3]_0\,
O => \gen_arbiter.grant_hot_reg[2]_0\
);
\gen_arbiter.qual_reg[0]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^m_payload_i_reg[3]_0\,
I1 => \^s_ready_i_reg_0\,
I2 => active_target_enc_4,
O => \gen_arbiter.grant_hot_reg[2]_1\
);
\m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^m_payload_i_reg[3]_0\,
I1 => \^s_ready_i_reg_0\,
I2 => p_20_in(0),
O => \m_payload_i[3]_i_1__1_n_0\
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i[3]_i_1__1_n_0\,
Q => \^m_payload_i_reg[3]_0\,
R => '0'
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_bvalid_i_reg\,
Q => \^s_ready_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_axi_bvalid[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"80FF808080808080"
)
port map (
I0 => \^m_payload_i_reg[3]_0\,
I1 => \^s_ready_i_reg_0\,
I2 => active_target_enc_2,
I3 => \m_payload_i_reg[2]\,
I4 => m_valid_i_reg_0(0),
I5 => active_target_hot_3(0),
O => \s_axi_bvalid[2]\
);
\s_ready_i_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABFF"
)
port map (
I0 => \^s_ready_i_reg_1\,
I1 => p_17_in,
I2 => \^s_ready_i_reg_0\,
I3 => \aresetn_d_reg[1]_0\,
O => \s_ready_i_i_1__3_n_0\
);
s_ready_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F808080800000000"
)
port map (
I0 => active_target_enc_4,
I1 => s_axi_bready(0),
I2 => \^m_payload_i_reg[3]_0\,
I3 => active_target_enc_2,
I4 => s_axi_bready(1),
I5 => \^s_ready_i_reg_0\,
O => \^s_ready_i_reg_1\
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__3_n_0\,
Q => mi_bready_1,
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized1_9\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
s_ready_i_reg_1 : out STD_LOGIC;
\gen_arbiter.qual_reg_reg[0]\ : out STD_LOGIC;
\valid_qual_i3__1_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_arbiter.qual_reg_reg[2]\ : out STD_LOGIC;
s_ready_i_reg_2 : out STD_LOGIC;
\gen_arbiter.grant_hot_reg[2]\ : out STD_LOGIC;
\gen_arbiter.grant_hot_reg[2]_0\ : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_awvalid_qual : in STD_LOGIC_VECTOR ( 0 to 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gen_single_thread.active_target_enc_reg[0]\ : in STD_LOGIC;
sel_4 : in STD_LOGIC;
\gen_master_slots[0].w_issuing_cnt_reg[3]\ : in STD_LOGIC;
sel_4_3 : in STD_LOGIC;
active_target_hot_4 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 1 downto 0 );
active_target_hot_5 : in STD_LOGIC_VECTOR ( 0 to 0 );
active_target_enc_6 : in STD_LOGIC;
active_target_enc_7 : in STD_LOGIC;
\m_axi_bid[1]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized1_9\ : entity is "axi_register_slice_v2_1_11_axic_register_slice";
end \system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized1_9\;
architecture STRUCTURE of \system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized1_9\ is
signal \aresetn_d[1]_i_1_n_0\ : STD_LOGIC;
signal bready_carry : STD_LOGIC_VECTOR ( 4 to 4 );
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \m_payload_i[3]_i_1_n_0\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal m_valid_i_i_2_n_0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^p_1_in\ : STD_LOGIC;
signal \s_ready_i_i_2__0_n_0\ : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal \^s_ready_i_reg_1\ : STD_LOGIC;
signal \^s_ready_i_reg_2\ : STD_LOGIC;
signal st_mr_bid : STD_LOGIC_VECTOR ( 1 downto 0 );
signal st_mr_bmesg : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^valid_qual_i3__1_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_arbiter.grant_hot[2]_i_8\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \gen_arbiter.qual_reg[0]_i_5\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \s_axi_bresp[0]_INST_0\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \s_axi_bresp[1]_INST_0\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \s_axi_bresp[4]_INST_0\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \s_axi_bresp[5]_INST_0\ : label is "soft_lutpair83";
begin
m_axi_bready(0) <= \^m_axi_bready\(0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
p_1_in <= \^p_1_in\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
s_ready_i_reg_1 <= \^s_ready_i_reg_1\;
s_ready_i_reg_2 <= \^s_ready_i_reg_2\;
\valid_qual_i3__1_0\(0) <= \^valid_qual_i3__1_0\(0);
\aresetn_d[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_0_in(1),
I1 => aresetn,
O => \aresetn_d[1]_i_1_n_0\
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => p_0_in(1),
R => '0'
);
\aresetn_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d[1]_i_1_n_0\,
Q => \^s_ready_i_reg_0\,
R => '0'
);
\gen_arbiter.grant_hot[2]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => active_target_hot_4(0),
I1 => \^m_payload_i_reg[0]_0\,
I2 => st_mr_bid(1),
I3 => st_mr_bid(0),
O => \gen_arbiter.grant_hot_reg[2]_0\
);
\gen_arbiter.qual_reg[0]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8888CC0C"
)
port map (
I0 => \^valid_qual_i3__1_0\(0),
I1 => st_aa_awvalid_qual(0),
I2 => w_issuing_cnt(4),
I3 => \gen_single_thread.active_target_enc_reg[0]\,
I4 => sel_4,
O => \gen_arbiter.qual_reg_reg[0]\
);
\gen_arbiter.qual_reg[0]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFEFFFEFFFEFF"
)
port map (
I0 => w_issuing_cnt(0),
I1 => w_issuing_cnt(1),
I2 => w_issuing_cnt(2),
I3 => w_issuing_cnt(3),
I4 => \^m_payload_i_reg[0]_0\,
I5 => bready_carry(4),
O => \^valid_qual_i3__1_0\(0)
);
\gen_arbiter.qual_reg[0]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8808"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => active_target_hot_5(0),
I2 => st_mr_bid(1),
I3 => st_mr_bid(0),
O => \gen_arbiter.grant_hot_reg[2]\
);
\gen_arbiter.qual_reg[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"EAFFEA00EAFFEAFF"
)
port map (
I0 => \gen_master_slots[0].w_issuing_cnt_reg[3]\,
I1 => \^m_payload_i_reg[0]_0\,
I2 => bready_carry(4),
I3 => sel_4_3,
I4 => \gen_single_thread.active_target_enc_reg[0]\,
I5 => w_issuing_cnt(4),
O => \gen_arbiter.qual_reg_reg[2]\
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
O => \m_payload_i[3]_i_1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[3]_i_1_n_0\,
D => \m_axi_bid[1]\(0),
Q => st_mr_bmesg(0),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[3]_i_1_n_0\,
D => \m_axi_bid[1]\(1),
Q => st_mr_bmesg(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[3]_i_1_n_0\,
D => \m_axi_bid[1]\(2),
Q => st_mr_bid(0),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[3]_i_1_n_0\,
D => \m_axi_bid[1]\(3),
Q => st_mr_bid(1),
R => '0'
);
\m_valid_i_i_1__4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^s_ready_i_reg_0\,
O => \^m_valid_i_reg_0\
);
m_valid_i_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => bready_carry(4),
O => m_valid_i_i_2_n_0
);
m_valid_i_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"8F88808880888088"
)
port map (
I0 => s_axi_bready(0),
I1 => active_target_hot_5(0),
I2 => st_mr_bid(0),
I3 => st_mr_bid(1),
I4 => s_axi_bready(1),
I5 => active_target_hot_4(0),
O => bready_carry(4)
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => m_valid_i_i_2_n_0,
Q => \^m_payload_i_reg[0]_0\,
R => \^m_valid_i_reg_0\
);
\s_axi_bresp[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => st_mr_bmesg(0),
I1 => active_target_enc_7,
O => s_axi_bresp(0)
);
\s_axi_bresp[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => st_mr_bmesg(1),
I1 => active_target_enc_7,
O => s_axi_bresp(1)
);
\s_axi_bresp[4]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => st_mr_bmesg(0),
I1 => active_target_enc_6,
O => s_axi_bresp(2)
);
\s_axi_bresp[5]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => st_mr_bmesg(1),
I1 => active_target_enc_6,
O => s_axi_bresp(3)
);
\s_axi_bvalid[2]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => st_mr_bid(0),
I1 => st_mr_bid(1),
O => \^s_ready_i_reg_2\
);
\s_ready_i_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in(1),
O => \^p_1_in\
);
\s_ready_i_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"57FF"
)
port map (
I0 => \^s_ready_i_reg_1\,
I1 => m_axi_bvalid(0),
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^s_ready_i_reg_0\,
O => \s_ready_i_i_2__0_n_0\
);
s_ready_i_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"07F7F7F7FFFFFFFF"
)
port map (
I0 => active_target_hot_4(0),
I1 => s_axi_bready(1),
I2 => \^s_ready_i_reg_2\,
I3 => active_target_hot_5(0),
I4 => s_axi_bready(0),
I5 => \^m_payload_i_reg[0]_0\,
O => \^s_ready_i_reg_1\
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_2__0_n_0\,
Q => \^m_axi_bready\(0),
R => \^p_1_in\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ is
port (
\skid_buffer_reg[66]_0\ : out STD_LOGIC;
p_2_in : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[67]_0\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_arbiter.grant_hot_reg[1]\ : out STD_LOGIC;
\gen_single_thread.accept_cnt_reg[1]\ : out STD_LOGIC;
\m_payload_i_reg[66]_0\ : out STD_LOGIC;
\gen_arbiter.grant_hot_reg[1]_0\ : out STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
p_11_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_valid_i_reg_0 : in STD_LOGIC;
active_target_enc : in STD_LOGIC;
\m_payload_i_reg[68]\ : in STD_LOGIC;
active_target_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
active_target_enc_0 : in STD_LOGIC;
active_target_hot_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
rready_carry : in STD_LOGIC_VECTOR ( 0 to 0 );
r_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
p_16_in : in STD_LOGIC_VECTOR ( 0 to 0 );
p_13_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_11_axic_register_slice";
end \system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\;
architecture STRUCTURE of \system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ is
signal \m_payload_i[66]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[67]_i_1_n_0\ : STD_LOGIC;
signal \^m_payload_i_reg[66]_0\ : STD_LOGIC;
signal \^m_payload_i_reg[67]_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal p_1_in_0 : STD_LOGIC;
signal \^s_axi_rlast\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \s_ready_i_i_1__4_n_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 67 downto 66 );
signal \^skid_buffer_reg[66]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[66]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[67]\ : STD_LOGIC;
signal st_mr_rvalid : STD_LOGIC_VECTOR ( 1 to 1 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_arbiter.grant_hot[1]_i_5\ : label is "soft_lutpair188";
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[8]_i_2\ : label is "soft_lutpair188";
attribute SOFT_HLUTNM of \m_payload_i[66]_i_1\ : label is "soft_lutpair187";
attribute SOFT_HLUTNM of \m_payload_i[67]_i_1\ : label is "soft_lutpair186";
attribute SOFT_HLUTNM of \s_axi_rlast[0]_INST_0\ : label is "soft_lutpair189";
attribute SOFT_HLUTNM of \s_axi_rlast[1]_INST_0\ : label is "soft_lutpair189";
attribute SOFT_HLUTNM of \skid_buffer[66]_i_1\ : label is "soft_lutpair187";
attribute SOFT_HLUTNM of \skid_buffer[67]_i_1\ : label is "soft_lutpair186";
begin
\m_payload_i_reg[66]_0\ <= \^m_payload_i_reg[66]_0\;
\m_payload_i_reg[67]_0\ <= \^m_payload_i_reg[67]_0\;
s_axi_rlast(1 downto 0) <= \^s_axi_rlast\(1 downto 0);
\skid_buffer_reg[66]_0\ <= \^skid_buffer_reg[66]_0\;
\gen_arbiter.grant_hot[1]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => st_mr_rvalid(1),
I1 => active_target_enc,
I2 => \^m_payload_i_reg[67]_0\,
O => \gen_arbiter.grant_hot_reg[1]\
);
\gen_arbiter.grant_hot[1]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"80FF"
)
port map (
I0 => \^m_payload_i_reg[66]_0\,
I1 => st_mr_rvalid(1),
I2 => rready_carry(0),
I3 => r_issuing_cnt(0),
O => \gen_arbiter.grant_hot_reg[1]_0\
);
\gen_master_slots[1].r_issuing_cnt[8]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => rready_carry(0),
I1 => st_mr_rvalid(1),
I2 => \^m_payload_i_reg[66]_0\,
O => \gen_master_slots[1].r_issuing_cnt_reg[8]\
);
\gen_single_thread.accept_cnt[1]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8080808088808080"
)
port map (
I0 => s_axi_rready(0),
I1 => \^s_axi_rlast\(0),
I2 => m_valid_i_reg_0,
I3 => st_mr_rvalid(1),
I4 => active_target_enc,
I5 => \^m_payload_i_reg[67]_0\,
O => p_2_in
);
\gen_single_thread.accept_cnt[1]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => \^m_payload_i_reg[67]_0\,
I1 => s_axi_rready(1),
I2 => active_target_enc_0,
I3 => st_mr_rvalid(1),
I4 => \^m_payload_i_reg[66]_0\,
O => \gen_single_thread.accept_cnt_reg[1]\
);
\m_payload_i[66]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => p_13_in,
I1 => \^skid_buffer_reg[66]_0\,
I2 => \skid_buffer_reg_n_0_[66]\,
I3 => p_1_in_0,
I4 => \^m_payload_i_reg[66]_0\,
O => \m_payload_i[66]_i_1_n_0\
);
\m_payload_i[67]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => p_16_in(0),
I1 => \^skid_buffer_reg[66]_0\,
I2 => \skid_buffer_reg_n_0_[67]\,
I3 => p_1_in_0,
I4 => \^m_payload_i_reg[67]_0\,
O => \m_payload_i[67]_i_1_n_0\
);
\m_payload_i_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i[66]_i_1_n_0\,
Q => \^m_payload_i_reg[66]_0\,
R => '0'
);
\m_payload_i_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i[67]_i_1_n_0\,
Q => \^m_payload_i_reg[67]_0\,
R => '0'
);
\m_valid_i_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => \^skid_buffer_reg[66]_0\,
I1 => p_11_in,
I2 => p_1_in_0,
O => m_valid_i0
);
\m_valid_i_i_2__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8F808080FFFFFFFF"
)
port map (
I0 => active_target_enc_0,
I1 => s_axi_rready(1),
I2 => \^m_payload_i_reg[67]_0\,
I3 => active_target_enc,
I4 => s_axi_rready(0),
I5 => st_mr_rvalid(1),
O => p_1_in_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => st_mr_rvalid(1),
R => \aresetn_d_reg[1]\
);
\s_axi_rlast[0]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^m_payload_i_reg[66]_0\,
I1 => active_target_enc,
I2 => Q(0),
O => \^s_axi_rlast\(0)
);
\s_axi_rlast[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^m_payload_i_reg[66]_0\,
I1 => active_target_enc_0,
I2 => Q(0),
O => \^s_axi_rlast\(1)
);
\s_axi_rvalid[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF40404040404040"
)
port map (
I0 => \^m_payload_i_reg[67]_0\,
I1 => active_target_enc,
I2 => st_mr_rvalid(1),
I3 => \m_payload_i_reg[68]\,
I4 => active_target_hot(0),
I5 => m_valid_i_reg_1(0),
O => s_axi_rvalid(0)
);
\s_axi_rvalid[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"80FF808080808080"
)
port map (
I0 => \^m_payload_i_reg[67]_0\,
I1 => st_mr_rvalid(1),
I2 => active_target_enc_0,
I3 => \m_payload_i_reg[68]\,
I4 => m_valid_i_reg_1(0),
I5 => active_target_hot_1(0),
O => s_axi_rvalid(1)
);
\s_ready_i_i_1__4\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => p_1_in_0,
I1 => \^skid_buffer_reg[66]_0\,
I2 => p_11_in,
O => \s_ready_i_i_1__4_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__4_n_0\,
Q => \^skid_buffer_reg[66]_0\,
R => p_1_in
);
\skid_buffer[66]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => p_13_in,
I1 => \^skid_buffer_reg[66]_0\,
I2 => \skid_buffer_reg_n_0_[66]\,
O => skid_buffer(66)
);
\skid_buffer[67]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => p_16_in(0),
I1 => \^skid_buffer_reg[66]_0\,
I2 => \skid_buffer_reg_n_0_[67]\,
O => skid_buffer(67)
);
\skid_buffer_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => skid_buffer(66),
Q => \skid_buffer_reg_n_0_[66]\,
R => '0'
);
\skid_buffer_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => skid_buffer(67),
Q => \skid_buffer_reg_n_0_[67]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2_10\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
\m_axi_rready[0]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
\gen_arbiter.qual_reg_reg[0]\ : out STD_LOGIC;
\valid_qual_i3__1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
p_2_in : out STD_LOGIC;
\m_payload_i_reg[0]_1\ : out STD_LOGIC;
\gen_arbiter.grant_hot_reg[1]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_arbiter.qual_reg_reg[1]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : out STD_LOGIC;
\gen_single_thread.accept_cnt_reg[1]\ : out STD_LOGIC;
\gen_arbiter.grant_hot_reg[1]_0\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
active_target_enc : in STD_LOGIC;
active_target_enc_1 : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_valid_i_reg_0 : in STD_LOGIC;
r_issuing_cnt : in STD_LOGIC_VECTOR ( 4 downto 0 );
active_target_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[67]_0\ : in STD_LOGIC;
st_mr_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
active_target_hot_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].r_issuing_cnt_reg[0]_0\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_arbiter.m_target_hot_i_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_mi_arvalid : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2_10\ : entity is "axi_register_slice_v2_1_11_axic_register_slice";
end \system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2_10\;
architecture STRUCTURE of \system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2_10\ is
signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\ : STD_LOGIC;
signal \^m_axi_rready[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_1\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal p_1_in_0 : STD_LOGIC;
signal rready_carry : STD_LOGIC_VECTOR ( 4 to 4 );
signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 68 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[65]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[66]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[67]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[68]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal st_mr_rid : STD_LOGIC_VECTOR ( 1 downto 0 );
signal st_mr_rmesg : STD_LOGIC_VECTOR ( 66 downto 3 );
signal \^valid_qual_i3__1\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_arbiter.grant_hot[1]_i_11\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \gen_arbiter.grant_hot[1]_i_13\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[2]_i_1\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_2\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[52]_i_1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[65]_i_1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[66]_i_1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[67]_i_1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[68]_i_2\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair118";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair118";
attribute SOFT_HLUTNM of \s_axi_rdata[0]_INST_0\ : label is "soft_lutpair184";
attribute SOFT_HLUTNM of \s_axi_rdata[100]_INST_0\ : label is "soft_lutpair148";
attribute SOFT_HLUTNM of \s_axi_rdata[101]_INST_0\ : label is "soft_lutpair147";
attribute SOFT_HLUTNM of \s_axi_rdata[102]_INST_0\ : label is "soft_lutpair146";
attribute SOFT_HLUTNM of \s_axi_rdata[103]_INST_0\ : label is "soft_lutpair145";
attribute SOFT_HLUTNM of \s_axi_rdata[104]_INST_0\ : label is "soft_lutpair144";
attribute SOFT_HLUTNM of \s_axi_rdata[105]_INST_0\ : label is "soft_lutpair143";
attribute SOFT_HLUTNM of \s_axi_rdata[106]_INST_0\ : label is "soft_lutpair142";
attribute SOFT_HLUTNM of \s_axi_rdata[107]_INST_0\ : label is "soft_lutpair141";
attribute SOFT_HLUTNM of \s_axi_rdata[108]_INST_0\ : label is "soft_lutpair140";
attribute SOFT_HLUTNM of \s_axi_rdata[109]_INST_0\ : label is "soft_lutpair139";
attribute SOFT_HLUTNM of \s_axi_rdata[10]_INST_0\ : label is "soft_lutpair174";
attribute SOFT_HLUTNM of \s_axi_rdata[110]_INST_0\ : label is "soft_lutpair138";
attribute SOFT_HLUTNM of \s_axi_rdata[111]_INST_0\ : label is "soft_lutpair137";
attribute SOFT_HLUTNM of \s_axi_rdata[112]_INST_0\ : label is "soft_lutpair136";
attribute SOFT_HLUTNM of \s_axi_rdata[113]_INST_0\ : label is "soft_lutpair135";
attribute SOFT_HLUTNM of \s_axi_rdata[114]_INST_0\ : label is "soft_lutpair134";
attribute SOFT_HLUTNM of \s_axi_rdata[115]_INST_0\ : label is "soft_lutpair133";
attribute SOFT_HLUTNM of \s_axi_rdata[116]_INST_0\ : label is "soft_lutpair132";
attribute SOFT_HLUTNM of \s_axi_rdata[117]_INST_0\ : label is "soft_lutpair131";
attribute SOFT_HLUTNM of \s_axi_rdata[118]_INST_0\ : label is "soft_lutpair130";
attribute SOFT_HLUTNM of \s_axi_rdata[119]_INST_0\ : label is "soft_lutpair129";
attribute SOFT_HLUTNM of \s_axi_rdata[11]_INST_0\ : label is "soft_lutpair173";
attribute SOFT_HLUTNM of \s_axi_rdata[120]_INST_0\ : label is "soft_lutpair128";
attribute SOFT_HLUTNM of \s_axi_rdata[121]_INST_0\ : label is "soft_lutpair127";
attribute SOFT_HLUTNM of \s_axi_rdata[122]_INST_0\ : label is "soft_lutpair126";
attribute SOFT_HLUTNM of \s_axi_rdata[123]_INST_0\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \s_axi_rdata[124]_INST_0\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \s_axi_rdata[125]_INST_0\ : label is "soft_lutpair123";
attribute SOFT_HLUTNM of \s_axi_rdata[126]_INST_0\ : label is "soft_lutpair122";
attribute SOFT_HLUTNM of \s_axi_rdata[127]_INST_0\ : label is "soft_lutpair122";
attribute SOFT_HLUTNM of \s_axi_rdata[12]_INST_0\ : label is "soft_lutpair172";
attribute SOFT_HLUTNM of \s_axi_rdata[13]_INST_0\ : label is "soft_lutpair171";
attribute SOFT_HLUTNM of \s_axi_rdata[14]_INST_0\ : label is "soft_lutpair170";
attribute SOFT_HLUTNM of \s_axi_rdata[15]_INST_0\ : label is "soft_lutpair169";
attribute SOFT_HLUTNM of \s_axi_rdata[16]_INST_0\ : label is "soft_lutpair168";
attribute SOFT_HLUTNM of \s_axi_rdata[17]_INST_0\ : label is "soft_lutpair167";
attribute SOFT_HLUTNM of \s_axi_rdata[18]_INST_0\ : label is "soft_lutpair166";
attribute SOFT_HLUTNM of \s_axi_rdata[19]_INST_0\ : label is "soft_lutpair165";
attribute SOFT_HLUTNM of \s_axi_rdata[1]_INST_0\ : label is "soft_lutpair183";
attribute SOFT_HLUTNM of \s_axi_rdata[20]_INST_0\ : label is "soft_lutpair164";
attribute SOFT_HLUTNM of \s_axi_rdata[21]_INST_0\ : label is "soft_lutpair163";
attribute SOFT_HLUTNM of \s_axi_rdata[22]_INST_0\ : label is "soft_lutpair162";
attribute SOFT_HLUTNM of \s_axi_rdata[23]_INST_0\ : label is "soft_lutpair161";
attribute SOFT_HLUTNM of \s_axi_rdata[24]_INST_0\ : label is "soft_lutpair160";
attribute SOFT_HLUTNM of \s_axi_rdata[25]_INST_0\ : label is "soft_lutpair159";
attribute SOFT_HLUTNM of \s_axi_rdata[26]_INST_0\ : label is "soft_lutpair158";
attribute SOFT_HLUTNM of \s_axi_rdata[27]_INST_0\ : label is "soft_lutpair157";
attribute SOFT_HLUTNM of \s_axi_rdata[28]_INST_0\ : label is "soft_lutpair156";
attribute SOFT_HLUTNM of \s_axi_rdata[29]_INST_0\ : label is "soft_lutpair155";
attribute SOFT_HLUTNM of \s_axi_rdata[2]_INST_0\ : label is "soft_lutpair182";
attribute SOFT_HLUTNM of \s_axi_rdata[30]_INST_0\ : label is "soft_lutpair154";
attribute SOFT_HLUTNM of \s_axi_rdata[31]_INST_0\ : label is "soft_lutpair153";
attribute SOFT_HLUTNM of \s_axi_rdata[32]_INST_0\ : label is "soft_lutpair152";
attribute SOFT_HLUTNM of \s_axi_rdata[33]_INST_0\ : label is "soft_lutpair151";
attribute SOFT_HLUTNM of \s_axi_rdata[34]_INST_0\ : label is "soft_lutpair150";
attribute SOFT_HLUTNM of \s_axi_rdata[35]_INST_0\ : label is "soft_lutpair149";
attribute SOFT_HLUTNM of \s_axi_rdata[36]_INST_0\ : label is "soft_lutpair148";
attribute SOFT_HLUTNM of \s_axi_rdata[37]_INST_0\ : label is "soft_lutpair147";
attribute SOFT_HLUTNM of \s_axi_rdata[38]_INST_0\ : label is "soft_lutpair146";
attribute SOFT_HLUTNM of \s_axi_rdata[39]_INST_0\ : label is "soft_lutpair145";
attribute SOFT_HLUTNM of \s_axi_rdata[3]_INST_0\ : label is "soft_lutpair181";
attribute SOFT_HLUTNM of \s_axi_rdata[40]_INST_0\ : label is "soft_lutpair144";
attribute SOFT_HLUTNM of \s_axi_rdata[41]_INST_0\ : label is "soft_lutpair143";
attribute SOFT_HLUTNM of \s_axi_rdata[42]_INST_0\ : label is "soft_lutpair142";
attribute SOFT_HLUTNM of \s_axi_rdata[43]_INST_0\ : label is "soft_lutpair141";
attribute SOFT_HLUTNM of \s_axi_rdata[44]_INST_0\ : label is "soft_lutpair140";
attribute SOFT_HLUTNM of \s_axi_rdata[45]_INST_0\ : label is "soft_lutpair139";
attribute SOFT_HLUTNM of \s_axi_rdata[46]_INST_0\ : label is "soft_lutpair138";
attribute SOFT_HLUTNM of \s_axi_rdata[47]_INST_0\ : label is "soft_lutpair137";
attribute SOFT_HLUTNM of \s_axi_rdata[48]_INST_0\ : label is "soft_lutpair136";
attribute SOFT_HLUTNM of \s_axi_rdata[49]_INST_0\ : label is "soft_lutpair135";
attribute SOFT_HLUTNM of \s_axi_rdata[4]_INST_0\ : label is "soft_lutpair180";
attribute SOFT_HLUTNM of \s_axi_rdata[50]_INST_0\ : label is "soft_lutpair134";
attribute SOFT_HLUTNM of \s_axi_rdata[51]_INST_0\ : label is "soft_lutpair133";
attribute SOFT_HLUTNM of \s_axi_rdata[52]_INST_0\ : label is "soft_lutpair132";
attribute SOFT_HLUTNM of \s_axi_rdata[53]_INST_0\ : label is "soft_lutpair131";
attribute SOFT_HLUTNM of \s_axi_rdata[54]_INST_0\ : label is "soft_lutpair130";
attribute SOFT_HLUTNM of \s_axi_rdata[55]_INST_0\ : label is "soft_lutpair129";
attribute SOFT_HLUTNM of \s_axi_rdata[56]_INST_0\ : label is "soft_lutpair128";
attribute SOFT_HLUTNM of \s_axi_rdata[57]_INST_0\ : label is "soft_lutpair127";
attribute SOFT_HLUTNM of \s_axi_rdata[58]_INST_0\ : label is "soft_lutpair126";
attribute SOFT_HLUTNM of \s_axi_rdata[59]_INST_0\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \s_axi_rdata[5]_INST_0\ : label is "soft_lutpair179";
attribute SOFT_HLUTNM of \s_axi_rdata[60]_INST_0\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \s_axi_rdata[61]_INST_0\ : label is "soft_lutpair123";
attribute SOFT_HLUTNM of \s_axi_rdata[63]_INST_0\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \s_axi_rdata[64]_INST_0\ : label is "soft_lutpair184";
attribute SOFT_HLUTNM of \s_axi_rdata[65]_INST_0\ : label is "soft_lutpair183";
attribute SOFT_HLUTNM of \s_axi_rdata[66]_INST_0\ : label is "soft_lutpair182";
attribute SOFT_HLUTNM of \s_axi_rdata[67]_INST_0\ : label is "soft_lutpair181";
attribute SOFT_HLUTNM of \s_axi_rdata[68]_INST_0\ : label is "soft_lutpair180";
attribute SOFT_HLUTNM of \s_axi_rdata[69]_INST_0\ : label is "soft_lutpair179";
attribute SOFT_HLUTNM of \s_axi_rdata[6]_INST_0\ : label is "soft_lutpair178";
attribute SOFT_HLUTNM of \s_axi_rdata[70]_INST_0\ : label is "soft_lutpair178";
attribute SOFT_HLUTNM of \s_axi_rdata[71]_INST_0\ : label is "soft_lutpair177";
attribute SOFT_HLUTNM of \s_axi_rdata[72]_INST_0\ : label is "soft_lutpair176";
attribute SOFT_HLUTNM of \s_axi_rdata[73]_INST_0\ : label is "soft_lutpair175";
attribute SOFT_HLUTNM of \s_axi_rdata[74]_INST_0\ : label is "soft_lutpair174";
attribute SOFT_HLUTNM of \s_axi_rdata[75]_INST_0\ : label is "soft_lutpair173";
attribute SOFT_HLUTNM of \s_axi_rdata[76]_INST_0\ : label is "soft_lutpair172";
attribute SOFT_HLUTNM of \s_axi_rdata[77]_INST_0\ : label is "soft_lutpair171";
attribute SOFT_HLUTNM of \s_axi_rdata[78]_INST_0\ : label is "soft_lutpair170";
attribute SOFT_HLUTNM of \s_axi_rdata[79]_INST_0\ : label is "soft_lutpair169";
attribute SOFT_HLUTNM of \s_axi_rdata[7]_INST_0\ : label is "soft_lutpair177";
attribute SOFT_HLUTNM of \s_axi_rdata[80]_INST_0\ : label is "soft_lutpair168";
attribute SOFT_HLUTNM of \s_axi_rdata[81]_INST_0\ : label is "soft_lutpair167";
attribute SOFT_HLUTNM of \s_axi_rdata[82]_INST_0\ : label is "soft_lutpair166";
attribute SOFT_HLUTNM of \s_axi_rdata[83]_INST_0\ : label is "soft_lutpair165";
attribute SOFT_HLUTNM of \s_axi_rdata[84]_INST_0\ : label is "soft_lutpair164";
attribute SOFT_HLUTNM of \s_axi_rdata[85]_INST_0\ : label is "soft_lutpair163";
attribute SOFT_HLUTNM of \s_axi_rdata[86]_INST_0\ : label is "soft_lutpair162";
attribute SOFT_HLUTNM of \s_axi_rdata[87]_INST_0\ : label is "soft_lutpair161";
attribute SOFT_HLUTNM of \s_axi_rdata[88]_INST_0\ : label is "soft_lutpair160";
attribute SOFT_HLUTNM of \s_axi_rdata[89]_INST_0\ : label is "soft_lutpair159";
attribute SOFT_HLUTNM of \s_axi_rdata[8]_INST_0\ : label is "soft_lutpair176";
attribute SOFT_HLUTNM of \s_axi_rdata[90]_INST_0\ : label is "soft_lutpair158";
attribute SOFT_HLUTNM of \s_axi_rdata[91]_INST_0\ : label is "soft_lutpair157";
attribute SOFT_HLUTNM of \s_axi_rdata[92]_INST_0\ : label is "soft_lutpair156";
attribute SOFT_HLUTNM of \s_axi_rdata[93]_INST_0\ : label is "soft_lutpair155";
attribute SOFT_HLUTNM of \s_axi_rdata[94]_INST_0\ : label is "soft_lutpair154";
attribute SOFT_HLUTNM of \s_axi_rdata[95]_INST_0\ : label is "soft_lutpair153";
attribute SOFT_HLUTNM of \s_axi_rdata[96]_INST_0\ : label is "soft_lutpair152";
attribute SOFT_HLUTNM of \s_axi_rdata[97]_INST_0\ : label is "soft_lutpair151";
attribute SOFT_HLUTNM of \s_axi_rdata[98]_INST_0\ : label is "soft_lutpair150";
attribute SOFT_HLUTNM of \s_axi_rdata[99]_INST_0\ : label is "soft_lutpair149";
attribute SOFT_HLUTNM of \s_axi_rdata[9]_INST_0\ : label is "soft_lutpair175";
attribute SOFT_HLUTNM of \s_axi_rvalid[1]_INST_0_i_1\ : label is "soft_lutpair86";
begin
Q(2 downto 0) <= \^q\(2 downto 0);
\m_axi_rready[0]\ <= \^m_axi_rready[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
\m_payload_i_reg[0]_1\ <= \^m_payload_i_reg[0]_1\;
\valid_qual_i3__1\(0) <= \^valid_qual_i3__1\(0);
\gen_arbiter.grant_hot[1]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000E200"
)
port map (
I0 => \^q\(2),
I1 => active_target_enc,
I2 => st_mr_rlast(0),
I3 => st_mr_rid(0),
I4 => st_mr_rid(1),
O => \gen_arbiter.grant_hot_reg[1]\
);
\gen_arbiter.grant_hot[1]_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"E200"
)
port map (
I0 => \^q\(2),
I1 => active_target_enc_1,
I2 => st_mr_rlast(0),
I3 => s_axi_rready(0),
O => \gen_arbiter.grant_hot_reg[1]_0\
);
\gen_arbiter.qual_reg[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFE0002FFFEFFFE"
)
port map (
I0 => \^valid_qual_i3__1\(0),
I1 => s_axi_araddr(2),
I2 => s_axi_araddr(1),
I3 => s_axi_araddr(0),
I4 => m_valid_i_reg_0,
I5 => r_issuing_cnt(4),
O => \gen_arbiter.qual_reg_reg[0]\
);
\gen_arbiter.qual_reg[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFE0002FFFEFFFE"
)
port map (
I0 => \^valid_qual_i3__1\(0),
I1 => s_axi_araddr(5),
I2 => s_axi_araddr(4),
I3 => s_axi_araddr(3),
I4 => m_valid_i_reg_0,
I5 => r_issuing_cnt(4),
O => \gen_arbiter.qual_reg_reg[1]\
);
\gen_arbiter.qual_reg[1]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFEFEFEFEFEFEF"
)
port map (
I0 => \gen_master_slots[0].r_issuing_cnt_reg[0]_0\,
I1 => r_issuing_cnt(2),
I2 => r_issuing_cnt(3),
I3 => rready_carry(4),
I4 => \^q\(2),
I5 => \^m_payload_i_reg[0]_0\,
O => \^valid_qual_i3__1\(0)
);
\gen_master_slots[0].r_issuing_cnt[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => r_issuing_cnt(1),
I1 => r_issuing_cnt(0),
I2 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\,
O => D(0)
);
\gen_master_slots[0].r_issuing_cnt[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AA9"
)
port map (
I0 => r_issuing_cnt(2),
I1 => r_issuing_cnt(0),
I2 => r_issuing_cnt(1),
I3 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\,
O => D(1)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => r_issuing_cnt(3),
I1 => r_issuing_cnt(1),
I2 => r_issuing_cnt(2),
I3 => r_issuing_cnt(0),
I4 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\,
O => D(2)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => \^q\(2),
I2 => rready_carry(4),
O => \gen_master_slots[0].r_issuing_cnt_reg[0]\
);
\gen_master_slots[0].r_issuing_cnt[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"7F00000000000000"
)
port map (
I0 => rready_carry(4),
I1 => \^q\(2),
I2 => \^m_payload_i_reg[0]_0\,
I3 => m_axi_arready(0),
I4 => \gen_arbiter.m_target_hot_i_reg[0]\(0),
I5 => aa_mi_arvalid,
O => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\
);
\gen_master_slots[0].r_issuing_cnt[3]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"8F88808880888088"
)
port map (
I0 => s_axi_rready(0),
I1 => active_target_hot_2(0),
I2 => st_mr_rid(1),
I3 => st_mr_rid(0),
I4 => s_axi_rready(1),
I5 => active_target_hot(0),
O => rready_carry(4)
);
\gen_single_thread.accept_cnt[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00008000"
)
port map (
I0 => active_target_hot(0),
I1 => \^m_payload_i_reg[0]_0\,
I2 => s_axi_rready(1),
I3 => s_axi_rlast(0),
I4 => \^m_payload_i_reg[0]_1\,
I5 => \m_payload_i_reg[67]_0\,
O => p_2_in
);
\gen_single_thread.accept_cnt[1]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8808"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => active_target_hot_2(0),
I2 => st_mr_rid(0),
I3 => st_mr_rid(1),
O => \gen_single_thread.accept_cnt_reg[1]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(32),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(33),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(34),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(35),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(36),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(37),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(38),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(39),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(40),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(41),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(42),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(43),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(44),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(45),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(46),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[47]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(47),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => skid_buffer(47)
);
\m_payload_i[48]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(48),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => skid_buffer(48)
);
\m_payload_i[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(49),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => skid_buffer(49)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[50]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(50),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => skid_buffer(50)
);
\m_payload_i[51]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(51),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => skid_buffer(51)
);
\m_payload_i[52]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(52),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[52]\,
O => skid_buffer(52)
);
\m_payload_i[53]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(53),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => skid_buffer(53)
);
\m_payload_i[54]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(54),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => skid_buffer(54)
);
\m_payload_i[55]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(55),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => skid_buffer(55)
);
\m_payload_i[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(56),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => skid_buffer(56)
);
\m_payload_i[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(57),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => skid_buffer(57)
);
\m_payload_i[58]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(58),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => skid_buffer(58)
);
\m_payload_i[59]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(59),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => skid_buffer(59)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[60]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(60),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => skid_buffer(60)
);
\m_payload_i[61]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(61),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => skid_buffer(61)
);
\m_payload_i[62]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(62),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => skid_buffer(62)
);
\m_payload_i[63]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(63),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => skid_buffer(63)
);
\m_payload_i[64]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => skid_buffer(64)
);
\m_payload_i[65]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[65]\,
O => skid_buffer(65)
);
\m_payload_i[66]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[66]\,
O => skid_buffer(66)
);
\m_payload_i[67]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[67]\,
O => skid_buffer(67)
);
\m_payload_i[68]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8080808FFFFFFFF"
)
port map (
I0 => active_target_hot(0),
I1 => s_axi_rready(1),
I2 => \^m_payload_i_reg[0]_1\,
I3 => active_target_hot_2(0),
I4 => s_axi_rready(0),
I5 => \^m_payload_i_reg[0]_0\,
O => p_1_in_0
);
\m_payload_i[68]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[68]\,
O => skid_buffer(68)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(0),
Q => st_mr_rmesg(3),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(10),
Q => st_mr_rmesg(13),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(11),
Q => st_mr_rmesg(14),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(12),
Q => st_mr_rmesg(15),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(13),
Q => st_mr_rmesg(16),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(14),
Q => st_mr_rmesg(17),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(15),
Q => st_mr_rmesg(18),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(16),
Q => st_mr_rmesg(19),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(17),
Q => st_mr_rmesg(20),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(18),
Q => st_mr_rmesg(21),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(19),
Q => st_mr_rmesg(22),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(1),
Q => st_mr_rmesg(4),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(20),
Q => st_mr_rmesg(23),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(21),
Q => st_mr_rmesg(24),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(22),
Q => st_mr_rmesg(25),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(23),
Q => st_mr_rmesg(26),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(24),
Q => st_mr_rmesg(27),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(25),
Q => st_mr_rmesg(28),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(26),
Q => st_mr_rmesg(29),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(27),
Q => st_mr_rmesg(30),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(28),
Q => st_mr_rmesg(31),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(29),
Q => st_mr_rmesg(32),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(2),
Q => st_mr_rmesg(5),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(30),
Q => st_mr_rmesg(33),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(31),
Q => st_mr_rmesg(34),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(32),
Q => st_mr_rmesg(35),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(33),
Q => st_mr_rmesg(36),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(34),
Q => st_mr_rmesg(37),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(35),
Q => st_mr_rmesg(38),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(36),
Q => st_mr_rmesg(39),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(37),
Q => st_mr_rmesg(40),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(38),
Q => st_mr_rmesg(41),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(39),
Q => st_mr_rmesg(42),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(3),
Q => st_mr_rmesg(6),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(40),
Q => st_mr_rmesg(43),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(41),
Q => st_mr_rmesg(44),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(42),
Q => st_mr_rmesg(45),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(43),
Q => st_mr_rmesg(46),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(44),
Q => st_mr_rmesg(47),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(45),
Q => st_mr_rmesg(48),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(46),
Q => st_mr_rmesg(49),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(47),
Q => st_mr_rmesg(50),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(48),
Q => st_mr_rmesg(51),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(49),
Q => st_mr_rmesg(52),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(4),
Q => st_mr_rmesg(7),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(50),
Q => st_mr_rmesg(53),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(51),
Q => st_mr_rmesg(54),
R => '0'
);
\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(52),
Q => st_mr_rmesg(55),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(53),
Q => st_mr_rmesg(56),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(54),
Q => st_mr_rmesg(57),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(55),
Q => st_mr_rmesg(58),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(56),
Q => st_mr_rmesg(59),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(57),
Q => st_mr_rmesg(60),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(58),
Q => st_mr_rmesg(61),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(59),
Q => st_mr_rmesg(62),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(5),
Q => st_mr_rmesg(8),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(60),
Q => st_mr_rmesg(63),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(61),
Q => st_mr_rmesg(64),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(62),
Q => st_mr_rmesg(65),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(63),
Q => st_mr_rmesg(66),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(64),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(65),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(66),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(67),
Q => st_mr_rid(0),
R => '0'
);
\m_payload_i_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(68),
Q => st_mr_rid(1),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(6),
Q => st_mr_rmesg(9),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(7),
Q => st_mr_rmesg(10),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(8),
Q => st_mr_rmesg(11),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(9),
Q => st_mr_rmesg(12),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => \^m_axi_rready[0]\,
I1 => m_axi_rvalid(0),
I2 => p_1_in_0,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]\
);
\s_axi_rdata[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(3),
I1 => active_target_enc_1,
O => s_axi_rdata(0)
);
\s_axi_rdata[100]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(39),
I1 => active_target_enc,
O => s_axi_rdata(100)
);
\s_axi_rdata[101]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(40),
I1 => active_target_enc,
O => s_axi_rdata(101)
);
\s_axi_rdata[102]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(41),
I1 => active_target_enc,
O => s_axi_rdata(102)
);
\s_axi_rdata[103]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(42),
I1 => active_target_enc,
O => s_axi_rdata(103)
);
\s_axi_rdata[104]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(43),
I1 => active_target_enc,
O => s_axi_rdata(104)
);
\s_axi_rdata[105]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(44),
I1 => active_target_enc,
O => s_axi_rdata(105)
);
\s_axi_rdata[106]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(45),
I1 => active_target_enc,
O => s_axi_rdata(106)
);
\s_axi_rdata[107]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(46),
I1 => active_target_enc,
O => s_axi_rdata(107)
);
\s_axi_rdata[108]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(47),
I1 => active_target_enc,
O => s_axi_rdata(108)
);
\s_axi_rdata[109]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(48),
I1 => active_target_enc,
O => s_axi_rdata(109)
);
\s_axi_rdata[10]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(13),
I1 => active_target_enc_1,
O => s_axi_rdata(10)
);
\s_axi_rdata[110]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(49),
I1 => active_target_enc,
O => s_axi_rdata(110)
);
\s_axi_rdata[111]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(50),
I1 => active_target_enc,
O => s_axi_rdata(111)
);
\s_axi_rdata[112]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(51),
I1 => active_target_enc,
O => s_axi_rdata(112)
);
\s_axi_rdata[113]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(52),
I1 => active_target_enc,
O => s_axi_rdata(113)
);
\s_axi_rdata[114]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(53),
I1 => active_target_enc,
O => s_axi_rdata(114)
);
\s_axi_rdata[115]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(54),
I1 => active_target_enc,
O => s_axi_rdata(115)
);
\s_axi_rdata[116]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(55),
I1 => active_target_enc,
O => s_axi_rdata(116)
);
\s_axi_rdata[117]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(56),
I1 => active_target_enc,
O => s_axi_rdata(117)
);
\s_axi_rdata[118]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(57),
I1 => active_target_enc,
O => s_axi_rdata(118)
);
\s_axi_rdata[119]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(58),
I1 => active_target_enc,
O => s_axi_rdata(119)
);
\s_axi_rdata[11]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(14),
I1 => active_target_enc_1,
O => s_axi_rdata(11)
);
\s_axi_rdata[120]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(59),
I1 => active_target_enc,
O => s_axi_rdata(120)
);
\s_axi_rdata[121]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(60),
I1 => active_target_enc,
O => s_axi_rdata(121)
);
\s_axi_rdata[122]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(61),
I1 => active_target_enc,
O => s_axi_rdata(122)
);
\s_axi_rdata[123]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(62),
I1 => active_target_enc,
O => s_axi_rdata(123)
);
\s_axi_rdata[124]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(63),
I1 => active_target_enc,
O => s_axi_rdata(124)
);
\s_axi_rdata[125]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(64),
I1 => active_target_enc,
O => s_axi_rdata(125)
);
\s_axi_rdata[126]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(65),
I1 => active_target_enc,
O => s_axi_rdata(126)
);
\s_axi_rdata[127]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(66),
I1 => active_target_enc,
O => s_axi_rdata(127)
);
\s_axi_rdata[12]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(15),
I1 => active_target_enc_1,
O => s_axi_rdata(12)
);
\s_axi_rdata[13]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(16),
I1 => active_target_enc_1,
O => s_axi_rdata(13)
);
\s_axi_rdata[14]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(17),
I1 => active_target_enc_1,
O => s_axi_rdata(14)
);
\s_axi_rdata[15]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(18),
I1 => active_target_enc_1,
O => s_axi_rdata(15)
);
\s_axi_rdata[16]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(19),
I1 => active_target_enc_1,
O => s_axi_rdata(16)
);
\s_axi_rdata[17]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(20),
I1 => active_target_enc_1,
O => s_axi_rdata(17)
);
\s_axi_rdata[18]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(21),
I1 => active_target_enc_1,
O => s_axi_rdata(18)
);
\s_axi_rdata[19]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(22),
I1 => active_target_enc_1,
O => s_axi_rdata(19)
);
\s_axi_rdata[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(4),
I1 => active_target_enc_1,
O => s_axi_rdata(1)
);
\s_axi_rdata[20]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(23),
I1 => active_target_enc_1,
O => s_axi_rdata(20)
);
\s_axi_rdata[21]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(24),
I1 => active_target_enc_1,
O => s_axi_rdata(21)
);
\s_axi_rdata[22]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(25),
I1 => active_target_enc_1,
O => s_axi_rdata(22)
);
\s_axi_rdata[23]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(26),
I1 => active_target_enc_1,
O => s_axi_rdata(23)
);
\s_axi_rdata[24]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(27),
I1 => active_target_enc_1,
O => s_axi_rdata(24)
);
\s_axi_rdata[25]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(28),
I1 => active_target_enc_1,
O => s_axi_rdata(25)
);
\s_axi_rdata[26]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(29),
I1 => active_target_enc_1,
O => s_axi_rdata(26)
);
\s_axi_rdata[27]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(30),
I1 => active_target_enc_1,
O => s_axi_rdata(27)
);
\s_axi_rdata[28]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(31),
I1 => active_target_enc_1,
O => s_axi_rdata(28)
);
\s_axi_rdata[29]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(32),
I1 => active_target_enc_1,
O => s_axi_rdata(29)
);
\s_axi_rdata[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(5),
I1 => active_target_enc_1,
O => s_axi_rdata(2)
);
\s_axi_rdata[30]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(33),
I1 => active_target_enc_1,
O => s_axi_rdata(30)
);
\s_axi_rdata[31]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(34),
I1 => active_target_enc_1,
O => s_axi_rdata(31)
);
\s_axi_rdata[32]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(35),
I1 => active_target_enc_1,
O => s_axi_rdata(32)
);
\s_axi_rdata[33]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(36),
I1 => active_target_enc_1,
O => s_axi_rdata(33)
);
\s_axi_rdata[34]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(37),
I1 => active_target_enc_1,
O => s_axi_rdata(34)
);
\s_axi_rdata[35]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(38),
I1 => active_target_enc_1,
O => s_axi_rdata(35)
);
\s_axi_rdata[36]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(39),
I1 => active_target_enc_1,
O => s_axi_rdata(36)
);
\s_axi_rdata[37]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(40),
I1 => active_target_enc_1,
O => s_axi_rdata(37)
);
\s_axi_rdata[38]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(41),
I1 => active_target_enc_1,
O => s_axi_rdata(38)
);
\s_axi_rdata[39]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(42),
I1 => active_target_enc_1,
O => s_axi_rdata(39)
);
\s_axi_rdata[3]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(6),
I1 => active_target_enc_1,
O => s_axi_rdata(3)
);
\s_axi_rdata[40]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(43),
I1 => active_target_enc_1,
O => s_axi_rdata(40)
);
\s_axi_rdata[41]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(44),
I1 => active_target_enc_1,
O => s_axi_rdata(41)
);
\s_axi_rdata[42]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(45),
I1 => active_target_enc_1,
O => s_axi_rdata(42)
);
\s_axi_rdata[43]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(46),
I1 => active_target_enc_1,
O => s_axi_rdata(43)
);
\s_axi_rdata[44]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(47),
I1 => active_target_enc_1,
O => s_axi_rdata(44)
);
\s_axi_rdata[45]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(48),
I1 => active_target_enc_1,
O => s_axi_rdata(45)
);
\s_axi_rdata[46]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(49),
I1 => active_target_enc_1,
O => s_axi_rdata(46)
);
\s_axi_rdata[47]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(50),
I1 => active_target_enc_1,
O => s_axi_rdata(47)
);
\s_axi_rdata[48]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(51),
I1 => active_target_enc_1,
O => s_axi_rdata(48)
);
\s_axi_rdata[49]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(52),
I1 => active_target_enc_1,
O => s_axi_rdata(49)
);
\s_axi_rdata[4]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(7),
I1 => active_target_enc_1,
O => s_axi_rdata(4)
);
\s_axi_rdata[50]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(53),
I1 => active_target_enc_1,
O => s_axi_rdata(50)
);
\s_axi_rdata[51]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(54),
I1 => active_target_enc_1,
O => s_axi_rdata(51)
);
\s_axi_rdata[52]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(55),
I1 => active_target_enc_1,
O => s_axi_rdata(52)
);
\s_axi_rdata[53]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(56),
I1 => active_target_enc_1,
O => s_axi_rdata(53)
);
\s_axi_rdata[54]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(57),
I1 => active_target_enc_1,
O => s_axi_rdata(54)
);
\s_axi_rdata[55]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(58),
I1 => active_target_enc_1,
O => s_axi_rdata(55)
);
\s_axi_rdata[56]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(59),
I1 => active_target_enc_1,
O => s_axi_rdata(56)
);
\s_axi_rdata[57]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(60),
I1 => active_target_enc_1,
O => s_axi_rdata(57)
);
\s_axi_rdata[58]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(61),
I1 => active_target_enc_1,
O => s_axi_rdata(58)
);
\s_axi_rdata[59]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(62),
I1 => active_target_enc_1,
O => s_axi_rdata(59)
);
\s_axi_rdata[5]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(8),
I1 => active_target_enc_1,
O => s_axi_rdata(5)
);
\s_axi_rdata[60]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(63),
I1 => active_target_enc_1,
O => s_axi_rdata(60)
);
\s_axi_rdata[61]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(64),
I1 => active_target_enc_1,
O => s_axi_rdata(61)
);
\s_axi_rdata[62]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(65),
I1 => active_target_enc_1,
O => s_axi_rdata(62)
);
\s_axi_rdata[63]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(66),
I1 => active_target_enc_1,
O => s_axi_rdata(63)
);
\s_axi_rdata[64]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(3),
I1 => active_target_enc,
O => s_axi_rdata(64)
);
\s_axi_rdata[65]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(4),
I1 => active_target_enc,
O => s_axi_rdata(65)
);
\s_axi_rdata[66]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(5),
I1 => active_target_enc,
O => s_axi_rdata(66)
);
\s_axi_rdata[67]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(6),
I1 => active_target_enc,
O => s_axi_rdata(67)
);
\s_axi_rdata[68]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(7),
I1 => active_target_enc,
O => s_axi_rdata(68)
);
\s_axi_rdata[69]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(8),
I1 => active_target_enc,
O => s_axi_rdata(69)
);
\s_axi_rdata[6]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(9),
I1 => active_target_enc_1,
O => s_axi_rdata(6)
);
\s_axi_rdata[70]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(9),
I1 => active_target_enc,
O => s_axi_rdata(70)
);
\s_axi_rdata[71]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(10),
I1 => active_target_enc,
O => s_axi_rdata(71)
);
\s_axi_rdata[72]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(11),
I1 => active_target_enc,
O => s_axi_rdata(72)
);
\s_axi_rdata[73]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(12),
I1 => active_target_enc,
O => s_axi_rdata(73)
);
\s_axi_rdata[74]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(13),
I1 => active_target_enc,
O => s_axi_rdata(74)
);
\s_axi_rdata[75]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(14),
I1 => active_target_enc,
O => s_axi_rdata(75)
);
\s_axi_rdata[76]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(15),
I1 => active_target_enc,
O => s_axi_rdata(76)
);
\s_axi_rdata[77]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(16),
I1 => active_target_enc,
O => s_axi_rdata(77)
);
\s_axi_rdata[78]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(17),
I1 => active_target_enc,
O => s_axi_rdata(78)
);
\s_axi_rdata[79]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(18),
I1 => active_target_enc,
O => s_axi_rdata(79)
);
\s_axi_rdata[7]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(10),
I1 => active_target_enc_1,
O => s_axi_rdata(7)
);
\s_axi_rdata[80]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(19),
I1 => active_target_enc,
O => s_axi_rdata(80)
);
\s_axi_rdata[81]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(20),
I1 => active_target_enc,
O => s_axi_rdata(81)
);
\s_axi_rdata[82]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(21),
I1 => active_target_enc,
O => s_axi_rdata(82)
);
\s_axi_rdata[83]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(22),
I1 => active_target_enc,
O => s_axi_rdata(83)
);
\s_axi_rdata[84]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(23),
I1 => active_target_enc,
O => s_axi_rdata(84)
);
\s_axi_rdata[85]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(24),
I1 => active_target_enc,
O => s_axi_rdata(85)
);
\s_axi_rdata[86]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(25),
I1 => active_target_enc,
O => s_axi_rdata(86)
);
\s_axi_rdata[87]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(26),
I1 => active_target_enc,
O => s_axi_rdata(87)
);
\s_axi_rdata[88]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(27),
I1 => active_target_enc,
O => s_axi_rdata(88)
);
\s_axi_rdata[89]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(28),
I1 => active_target_enc,
O => s_axi_rdata(89)
);
\s_axi_rdata[8]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(11),
I1 => active_target_enc_1,
O => s_axi_rdata(8)
);
\s_axi_rdata[90]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(29),
I1 => active_target_enc,
O => s_axi_rdata(90)
);
\s_axi_rdata[91]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(30),
I1 => active_target_enc,
O => s_axi_rdata(91)
);
\s_axi_rdata[92]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(31),
I1 => active_target_enc,
O => s_axi_rdata(92)
);
\s_axi_rdata[93]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(32),
I1 => active_target_enc,
O => s_axi_rdata(93)
);
\s_axi_rdata[94]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(33),
I1 => active_target_enc,
O => s_axi_rdata(94)
);
\s_axi_rdata[95]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(34),
I1 => active_target_enc,
O => s_axi_rdata(95)
);
\s_axi_rdata[96]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(35),
I1 => active_target_enc,
O => s_axi_rdata(96)
);
\s_axi_rdata[97]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(36),
I1 => active_target_enc,
O => s_axi_rdata(97)
);
\s_axi_rdata[98]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(37),
I1 => active_target_enc,
O => s_axi_rdata(98)
);
\s_axi_rdata[99]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(38),
I1 => active_target_enc,
O => s_axi_rdata(99)
);
\s_axi_rdata[9]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(12),
I1 => active_target_enc_1,
O => s_axi_rdata(9)
);
\s_axi_rvalid[1]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => st_mr_rid(1),
I1 => st_mr_rid(0),
O => \^m_payload_i_reg[0]_1\
);
\s_ready_i_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => p_1_in_0,
I1 => \^m_axi_rready[0]\,
I2 => m_axi_rvalid(0),
O => \s_ready_i_i_1__2_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__2_n_0\,
Q => \^m_axi_rready[0]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(32),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(33),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(34),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(35),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(36),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(37),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(38),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(39),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(40),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(41),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(42),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(43),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(44),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(45),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(46),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(47),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(48),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(49),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(50),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(51),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(52),
Q => \skid_buffer_reg_n_0_[52]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(53),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(54),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(55),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(56),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(57),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(58),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(59),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(60),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(61),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(62),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(63),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[65]\,
R => '0'
);
\skid_buffer_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[66]\,
R => '0'
);
\skid_buffer_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[67]\,
R => '0'
);
\skid_buffer_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(1),
Q => \skid_buffer_reg_n_0_[68]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo is
port (
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\storage_data1_reg[0]_0\ : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_select_enc : out STD_LOGIC;
\write_cs0__0\ : out STD_LOGIC;
\gen_axi.s_axi_wready_i_reg\ : out STD_LOGIC;
aclk : in STD_LOGIC;
aresetn_d_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
\storage_data1_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg_0 : in STD_LOGIC;
m_valid_i_reg_1 : in STD_LOGIC;
\storage_data1_reg[1]_0\ : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[1]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo : entity is "axi_data_fifo_v2_1_10_axic_reg_srl_fifo";
end system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo;
architecture STRUCTURE of system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo is
signal \FSM_onehot_state[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[2]_i_2__0_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[3]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[3]_i_3__0_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[3]_i_4__0_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[3]_i_5__0_n_0\ : STD_LOGIC;
signal \FSM_onehot_state_reg_n_0_[2]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[2]\ : signal is "yes";
signal \FSM_onehot_state_reg_n_0_[3]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[3]\ : signal is "yes";
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal fifoaddr : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^gen_axi.s_axi_wready_i_reg\ : STD_LOGIC;
signal \gen_rep[0].fifoaddr[0]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_rep[0].fifoaddr[1]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[0].srl_nx1_n_1\ : STD_LOGIC;
signal \m_aready__1\ : STD_LOGIC;
signal \^m_select_enc\ : STD_LOGIC;
signal m_valid_i : STD_LOGIC;
signal m_valid_i_i_1_n_0 : STD_LOGIC;
signal m_valid_i_i_2_n_0 : STD_LOGIC;
signal p_0_in8_in : STD_LOGIC;
attribute RTL_KEEP of p_0_in8_in : signal is "yes";
signal p_9_in : STD_LOGIC;
attribute RTL_KEEP of p_9_in : signal is "yes";
signal push : STD_LOGIC;
signal \s_ready_i_i_1__0_n_0\ : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal \storage_data1[0]_i_3__0_n_0\ : STD_LOGIC;
signal \^storage_data1_reg[0]_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_onehot_state[3]_i_6__0\ : label is "soft_lutpair200";
attribute KEEP : string;
attribute KEEP of \FSM_onehot_state_reg[0]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[1]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[2]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[3]\ : label is "yes";
attribute syn_keep : string;
attribute syn_keep of \gen_rep[0].fifoaddr_reg[0]\ : label is "1";
attribute syn_keep of \gen_rep[0].fifoaddr_reg[1]\ : label is "1";
attribute SOFT_HLUTNM of \m_axi_wvalid[0]_INST_0_i_2\ : label is "soft_lutpair200";
begin
SR(0) <= \^sr\(0);
\gen_axi.s_axi_wready_i_reg\ <= \^gen_axi.s_axi_wready_i_reg\;
m_select_enc <= \^m_select_enc\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\storage_data1_reg[0]_0\ <= \^storage_data1_reg[0]_0\;
\FSM_onehot_state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"51000000"
)
port map (
I0 => p_9_in,
I1 => s_axi_awvalid(0),
I2 => m_ready_d(0),
I3 => \m_aready__1\,
I4 => p_0_in8_in,
O => \FSM_onehot_state[0]_i_1_n_0\
);
\FSM_onehot_state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444444444744"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => p_9_in,
I2 => push,
I3 => \FSM_onehot_state[3]_i_5__0_n_0\,
I4 => \FSM_onehot_state[2]_i_2__0_n_0\,
I5 => p_0_in8_in,
O => \FSM_onehot_state[1]_i_1_n_0\
);
\FSM_onehot_state[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"88888888BBBBB8BB"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => p_9_in,
I2 => push,
I3 => \FSM_onehot_state[3]_i_5__0_n_0\,
I4 => \FSM_onehot_state[2]_i_2__0_n_0\,
I5 => p_0_in8_in,
O => \FSM_onehot_state[2]_i_1_n_0\
);
\FSM_onehot_state[2]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[3]\,
I1 => \storage_data1_reg[1]_0\,
I2 => s_axi_wvalid(0),
I3 => \^storage_data1_reg[0]_0\,
I4 => s_axi_wlast(0),
O => \FSM_onehot_state[2]_i_2__0_n_0\
);
\FSM_onehot_state[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFEEEEEEEEEEEEEE"
)
port map (
I0 => \FSM_onehot_state[3]_i_3__0_n_0\,
I1 => \FSM_onehot_state[3]_i_4__0_n_0\,
I2 => push,
I3 => \FSM_onehot_state[3]_i_5__0_n_0\,
I4 => \m_aready__1\,
I5 => \FSM_onehot_state_reg_n_0_[3]\,
O => m_valid_i
);
\FSM_onehot_state[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"000008AA"
)
port map (
I0 => p_0_in8_in,
I1 => s_axi_awvalid(0),
I2 => m_ready_d(0),
I3 => \m_aready__1\,
I4 => p_9_in,
O => \FSM_onehot_state[3]_i_2_n_0\
);
\FSM_onehot_state[3]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"800000002AAAAAAA"
)
port map (
I0 => p_0_in8_in,
I1 => s_axi_wlast(0),
I2 => \^storage_data1_reg[0]_0\,
I3 => s_axi_wvalid(0),
I4 => \storage_data1_reg[1]_0\,
I5 => \m_ready_d_reg[1]\,
O => \FSM_onehot_state[3]_i_3__0_n_0\
);
\FSM_onehot_state[3]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => p_9_in,
I1 => s_axi_awvalid(0),
I2 => m_ready_d(0),
O => \FSM_onehot_state[3]_i_4__0_n_0\
);
\FSM_onehot_state[3]_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => fifoaddr(0),
I1 => fifoaddr(1),
O => \FSM_onehot_state[3]_i_5__0_n_0\
);
\FSM_onehot_state[3]_i_6__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => s_axi_wlast(0),
I1 => \^storage_data1_reg[0]_0\,
I2 => s_axi_wvalid(0),
I3 => \storage_data1_reg[1]_0\,
O => \m_aready__1\
);
\FSM_onehot_state_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => m_valid_i,
D => \FSM_onehot_state[0]_i_1_n_0\,
Q => p_9_in,
S => \^sr\(0)
);
\FSM_onehot_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => m_valid_i,
D => \FSM_onehot_state[1]_i_1_n_0\,
Q => p_0_in8_in,
R => \^sr\(0)
);
\FSM_onehot_state_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => m_valid_i,
D => \FSM_onehot_state[2]_i_1_n_0\,
Q => \FSM_onehot_state_reg_n_0_[2]\,
R => \^sr\(0)
);
\FSM_onehot_state_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => m_valid_i,
D => \FSM_onehot_state[3]_i_2_n_0\,
Q => \FSM_onehot_state_reg_n_0_[3]\,
R => \^sr\(0)
);
areset_d1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => aresetn_d_reg(0),
Q => \^sr\(0),
R => '0'
);
\gen_axi.write_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF80000000"
)
port map (
I0 => s_axi_wlast(0),
I1 => \^m_select_enc\,
I2 => \storage_data1_reg[1]\(0),
I3 => m_valid_i_reg_0,
I4 => \^gen_axi.s_axi_wready_i_reg\,
I5 => m_valid_i_reg_1,
O => \write_cs0__0\
);
\gen_rep[0].fifoaddr[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5AFB51FBA504AE04"
)
port map (
I0 => \m_aready__1\,
I1 => p_0_in8_in,
I2 => \m_ready_d_reg[1]\,
I3 => \FSM_onehot_state_reg_n_0_[3]\,
I4 => \^s_ready_i_reg_0\,
I5 => fifoaddr(0),
O => \gen_rep[0].fifoaddr[0]_i_1__0_n_0\
);
\gen_rep[0].fifoaddr[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"D5BF2A40"
)
port map (
I0 => fifoaddr(0),
I1 => \m_aready__1\,
I2 => \FSM_onehot_state_reg_n_0_[3]\,
I3 => push,
I4 => fifoaddr(1),
O => \gen_rep[0].fifoaddr[1]_i_1__0_n_0\
);
\gen_rep[0].fifoaddr_reg[0]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[0]_i_1__0_n_0\,
Q => fifoaddr(0),
S => aresetn_d_reg(0)
);
\gen_rep[0].fifoaddr_reg[1]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[1]_i_1__0_n_0\,
Q => fifoaddr(1),
S => aresetn_d_reg(0)
);
\gen_srls[0].gen_rep[0].srl_nx1\: entity work.system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl
port map (
\FSM_onehot_state_reg[0]\ => \FSM_onehot_state[3]_i_4__0_n_0\,
\FSM_onehot_state_reg[1]\ => \storage_data1[0]_i_3__0_n_0\,
aclk => aclk,
fifoaddr(1 downto 0) => fifoaddr(1 downto 0),
\m_aready__1\ => \m_aready__1\,
\m_ready_d_reg[1]\ => \m_ready_d_reg[1]\,
m_select_enc => \^m_select_enc\,
m_valid_i_reg => \^storage_data1_reg[0]_0\,
out0(1) => p_0_in8_in,
out0(0) => \FSM_onehot_state_reg_n_0_[3]\,
push => push,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
s_ready_i_reg => \^s_ready_i_reg_0\,
\storage_data1_reg[0]\ => \gen_srls[0].gen_rep[0].srl_nx1_n_1\,
\storage_data1_reg[1]\ => \storage_data1_reg[1]_0\
);
\m_axi_wvalid[0]_INST_0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^storage_data1_reg[0]_0\,
I1 => s_axi_wvalid(0),
O => \^gen_axi.s_axi_wready_i_reg\
);
m_valid_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EFEEEEEEEEEEEEEE"
)
port map (
I0 => m_valid_i_i_2_n_0,
I1 => \FSM_onehot_state[3]_i_4__0_n_0\,
I2 => push,
I3 => \FSM_onehot_state[3]_i_5__0_n_0\,
I4 => \m_aready__1\,
I5 => \FSM_onehot_state_reg_n_0_[3]\,
O => m_valid_i_i_1_n_0
);
m_valid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"000000002AAAAAAA"
)
port map (
I0 => p_0_in8_in,
I1 => s_axi_wlast(0),
I2 => \^storage_data1_reg[0]_0\,
I3 => s_axi_wvalid(0),
I4 => \storage_data1_reg[1]_0\,
I5 => \m_ready_d_reg[1]\,
O => m_valid_i_i_2_n_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i,
D => m_valid_i_i_1_n_0,
Q => \^storage_data1_reg[0]_0\,
R => \^sr\(0)
);
\s_ready_i_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDFFFDDDDDDDD"
)
port map (
I0 => \FSM_onehot_state[2]_i_2__0_n_0\,
I1 => \^sr\(0),
I2 => push,
I3 => fifoaddr(1),
I4 => fifoaddr(0),
I5 => \^s_ready_i_reg_0\,
O => \s_ready_i_i_1__0_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__0_n_0\,
Q => \^s_ready_i_reg_0\,
R => aresetn_d_reg(0)
);
\storage_data1[0]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => p_0_in8_in,
I1 => s_axi_awvalid(0),
I2 => m_ready_d(0),
O => \storage_data1[0]_i_3__0_n_0\
);
\storage_data1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_srls[0].gen_rep[0].srl_nx1_n_1\,
Q => \^m_select_enc\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo_5 is
port (
\storage_data1_reg[0]_0\ : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
\storage_data1_reg[0]_1\ : out STD_LOGIC;
\gen_axi.s_axi_wready_i_reg\ : out STD_LOGIC;
\gen_rep[0].fifoaddr_reg[2]\ : out STD_LOGIC;
aclk : in STD_LOGIC;
SS : in STD_LOGIC_VECTOR ( 0 to 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
\storage_data1_reg[1]\ : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[1]\ : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
\storage_data1_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\storage_data1_reg[1]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo_5 : entity is "axi_data_fifo_v2_1_10_axic_reg_srl_fifo";
end system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo_5;
architecture STRUCTURE of system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo_5 is
signal \FSM_onehot_state[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[2]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[3]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[3]_i_3_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[3]_i_4_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[3]_i_5_n_0\ : STD_LOGIC;
signal \FSM_onehot_state_reg_n_0_[2]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[2]\ : signal is "yes";
signal \FSM_onehot_state_reg_n_0_[3]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[3]\ : signal is "yes";
signal fifoaddr : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \gen_rep[0].fifoaddr[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_rep[0].fifoaddr[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[0].srl_nx1_n_1\ : STD_LOGIC;
signal \m_aready__1\ : STD_LOGIC;
signal m_valid_i : STD_LOGIC;
signal m_valid_i_i_1_n_0 : STD_LOGIC;
signal m_valid_i_i_2_n_0 : STD_LOGIC;
signal p_0_in8_in : STD_LOGIC;
attribute RTL_KEEP of p_0_in8_in : signal is "yes";
signal p_9_in : STD_LOGIC;
attribute RTL_KEEP of p_9_in : signal is "yes";
signal push : STD_LOGIC;
signal s_ready_i_i_1_n_0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal \storage_data1[0]_i_3_n_0\ : STD_LOGIC;
signal \^storage_data1_reg[0]_0\ : STD_LOGIC;
signal \^storage_data1_reg[0]_1\ : STD_LOGIC;
attribute KEEP : string;
attribute KEEP of \FSM_onehot_state_reg[0]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[1]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[2]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[3]\ : label is "yes";
attribute syn_keep : string;
attribute syn_keep of \gen_rep[0].fifoaddr_reg[0]\ : label is "1";
attribute syn_keep of \gen_rep[0].fifoaddr_reg[1]\ : label is "1";
begin
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\storage_data1_reg[0]_0\ <= \^storage_data1_reg[0]_0\;
\storage_data1_reg[0]_1\ <= \^storage_data1_reg[0]_1\;
\FSM_onehot_state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"51000000"
)
port map (
I0 => p_9_in,
I1 => s_axi_awvalid(0),
I2 => m_ready_d(0),
I3 => \m_aready__1\,
I4 => p_0_in8_in,
O => \FSM_onehot_state[0]_i_1_n_0\
);
\FSM_onehot_state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444444444744"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => p_9_in,
I2 => push,
I3 => \FSM_onehot_state[3]_i_5_n_0\,
I4 => \FSM_onehot_state[2]_i_2_n_0\,
I5 => p_0_in8_in,
O => \FSM_onehot_state[1]_i_1_n_0\
);
\FSM_onehot_state[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"88888888BBBBB8BB"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => p_9_in,
I2 => push,
I3 => \FSM_onehot_state[3]_i_5_n_0\,
I4 => \FSM_onehot_state[2]_i_2_n_0\,
I5 => p_0_in8_in,
O => \FSM_onehot_state[2]_i_1_n_0\
);
\FSM_onehot_state[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[3]\,
I1 => \storage_data1_reg[1]\,
I2 => \^storage_data1_reg[0]_0\,
I3 => s_axi_wvalid(0),
I4 => s_axi_wlast(0),
O => \FSM_onehot_state[2]_i_2_n_0\
);
\FSM_onehot_state[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFEEEEEEEEEEEEEE"
)
port map (
I0 => \FSM_onehot_state[3]_i_3_n_0\,
I1 => \FSM_onehot_state[3]_i_4_n_0\,
I2 => push,
I3 => \FSM_onehot_state[3]_i_5_n_0\,
I4 => \m_aready__1\,
I5 => \FSM_onehot_state_reg_n_0_[3]\,
O => m_valid_i
);
\FSM_onehot_state[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"000008AA"
)
port map (
I0 => p_0_in8_in,
I1 => s_axi_awvalid(0),
I2 => m_ready_d(0),
I3 => \m_aready__1\,
I4 => p_9_in,
O => \FSM_onehot_state[3]_i_2_n_0\
);
\FSM_onehot_state[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"800000002AAAAAAA"
)
port map (
I0 => p_0_in8_in,
I1 => s_axi_wlast(0),
I2 => s_axi_wvalid(0),
I3 => \^storage_data1_reg[0]_0\,
I4 => \storage_data1_reg[1]\,
I5 => \m_ready_d_reg[1]\,
O => \FSM_onehot_state[3]_i_3_n_0\
);
\FSM_onehot_state[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => p_9_in,
I1 => s_axi_awvalid(0),
I2 => m_ready_d(0),
O => \FSM_onehot_state[3]_i_4_n_0\
);
\FSM_onehot_state[3]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => fifoaddr(0),
I1 => fifoaddr(1),
O => \FSM_onehot_state[3]_i_5_n_0\
);
\FSM_onehot_state[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => s_axi_wlast(0),
I1 => s_axi_wvalid(0),
I2 => \^storage_data1_reg[0]_0\,
I3 => \storage_data1_reg[1]\,
O => \m_aready__1\
);
\FSM_onehot_state_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => m_valid_i,
D => \FSM_onehot_state[0]_i_1_n_0\,
Q => p_9_in,
S => SS(0)
);
\FSM_onehot_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => m_valid_i,
D => \FSM_onehot_state[1]_i_1_n_0\,
Q => p_0_in8_in,
R => SS(0)
);
\FSM_onehot_state_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => m_valid_i,
D => \FSM_onehot_state[2]_i_1_n_0\,
Q => \FSM_onehot_state_reg_n_0_[2]\,
R => SS(0)
);
\FSM_onehot_state_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => m_valid_i,
D => \FSM_onehot_state[3]_i_2_n_0\,
Q => \FSM_onehot_state_reg_n_0_[3]\,
R => SS(0)
);
\gen_rep[0].fifoaddr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5AFB51FBA504AE04"
)
port map (
I0 => \m_aready__1\,
I1 => p_0_in8_in,
I2 => \m_ready_d_reg[1]\,
I3 => \FSM_onehot_state_reg_n_0_[3]\,
I4 => \^s_ready_i_reg_0\,
I5 => fifoaddr(0),
O => \gen_rep[0].fifoaddr[0]_i_1_n_0\
);
\gen_rep[0].fifoaddr[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"D5BF2A40"
)
port map (
I0 => fifoaddr(0),
I1 => \m_aready__1\,
I2 => \FSM_onehot_state_reg_n_0_[3]\,
I3 => push,
I4 => fifoaddr(1),
O => \gen_rep[0].fifoaddr[1]_i_1_n_0\
);
\gen_rep[0].fifoaddr_reg[0]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[0]_i_1_n_0\,
Q => fifoaddr(0),
S => SR(0)
);
\gen_rep[0].fifoaddr_reg[1]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[1]_i_1_n_0\,
Q => fifoaddr(1),
S => SR(0)
);
\gen_srls[0].gen_rep[0].srl_nx1\: entity work.system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl_6
port map (
\FSM_onehot_state_reg[0]\ => \FSM_onehot_state[3]_i_4_n_0\,
\FSM_onehot_state_reg[1]\ => \storage_data1[0]_i_3_n_0\,
aclk => aclk,
fifoaddr(1 downto 0) => fifoaddr(1 downto 0),
\m_aready__1\ => \m_aready__1\,
\m_ready_d_reg[1]\ => \m_ready_d_reg[1]\,
m_valid_i_reg => \^storage_data1_reg[0]_0\,
out0(1) => p_0_in8_in,
out0(0) => \FSM_onehot_state_reg_n_0_[3]\,
push => push,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
s_ready_i_reg => \^s_ready_i_reg_0\,
\storage_data1_reg[0]\ => \gen_srls[0].gen_rep[0].srl_nx1_n_1\,
\storage_data1_reg[0]_0\ => \^storage_data1_reg[0]_1\,
\storage_data1_reg[1]\ => \storage_data1_reg[1]\
);
\m_axi_wvalid[0]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => \^storage_data1_reg[0]_1\,
I1 => \storage_data1_reg[1]_1\(0),
I2 => \^storage_data1_reg[0]_0\,
I3 => s_axi_wvalid(0),
O => \gen_rep[0].fifoaddr_reg[2]\
);
m_valid_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EFEEEEEEEEEEEEEE"
)
port map (
I0 => m_valid_i_i_2_n_0,
I1 => \FSM_onehot_state[3]_i_4_n_0\,
I2 => push,
I3 => \FSM_onehot_state[3]_i_5_n_0\,
I4 => \m_aready__1\,
I5 => \FSM_onehot_state_reg_n_0_[3]\,
O => m_valid_i_i_1_n_0
);
m_valid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"000000002AAAAAAA"
)
port map (
I0 => p_0_in8_in,
I1 => s_axi_wlast(0),
I2 => s_axi_wvalid(0),
I3 => \^storage_data1_reg[0]_0\,
I4 => \storage_data1_reg[1]\,
I5 => \m_ready_d_reg[1]\,
O => m_valid_i_i_2_n_0
);
m_valid_i_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0080000000000000"
)
port map (
I0 => s_axi_wvalid(0),
I1 => \^storage_data1_reg[0]_0\,
I2 => m_valid_i_reg_0,
I3 => \storage_data1_reg[1]_0\(0),
I4 => s_axi_wlast(0),
I5 => \^storage_data1_reg[0]_1\,
O => \gen_axi.s_axi_wready_i_reg\
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i,
D => m_valid_i_i_1_n_0,
Q => \^storage_data1_reg[0]_0\,
R => SS(0)
);
s_ready_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDFFFDDDDDDDD"
)
port map (
I0 => \FSM_onehot_state[2]_i_2_n_0\,
I1 => SS(0),
I2 => push,
I3 => fifoaddr(1),
I4 => fifoaddr(0),
I5 => \^s_ready_i_reg_0\,
O => s_ready_i_i_1_n_0
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => s_ready_i_i_1_n_0,
Q => \^s_ready_i_reg_0\,
R => SR(0)
);
\storage_data1[0]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => p_0_in8_in,
I1 => s_axi_awvalid(0),
I2 => m_ready_d(0),
O => \storage_data1[0]_i_3_n_0\
);
\storage_data1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_srls[0].gen_rep[0].srl_nx1_n_1\,
Q => \^storage_data1_reg[0]_1\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized0\ is
port (
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
\storage_data1_reg[1]_0\ : out STD_LOGIC;
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_ready_i_reg : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
out0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_ready_i_reg_0 : out STD_LOGIC;
s_ready_i_reg_1 : out STD_LOGIC;
m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
aa_wm_awgrant_enc : in STD_LOGIC_VECTOR ( 0 to 0 );
in1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
\gen_arbiter.m_valid_i_reg\ : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
\storage_data1_reg[0]_0\ : in STD_LOGIC;
m_select_enc : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\FSM_onehot_state_reg[0]_0\ : in STD_LOGIC;
\FSM_onehot_state_reg[1]_0\ : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_sa_awvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized0\ : entity is "axi_data_fifo_v2_1_10_axic_reg_srl_fifo";
end \system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized0\;
architecture STRUCTURE of \system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized0\ is
signal \FSM_onehot_state[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[3]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_state_reg_n_0_[2]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[2]\ : signal is "yes";
signal \FSM_onehot_state_reg_n_0_[3]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[3]\ : signal is "yes";
signal fifoaddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_rep[0].fifoaddr[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_rep[0].fifoaddr[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_rep[0].fifoaddr[2]_i_1_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[0].srl_nx1_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[1].srl_nx1_n_2\ : STD_LOGIC;
signal \m_aready__1\ : STD_LOGIC;
signal m_avalid : STD_LOGIC;
signal \^m_axi_wvalid\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal m_select_enc_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal \m_valid_i__0\ : STD_LOGIC;
signal \m_valid_i_i_3__0_n_0\ : STD_LOGIC;
signal m_valid_i_n_0 : STD_LOGIC;
signal \^out0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of out0 : signal is "yes";
signal push : STD_LOGIC;
signal \^storage_data1_reg[1]_0\ : STD_LOGIC;
attribute KEEP : string;
attribute KEEP of \FSM_onehot_state_reg[0]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[1]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[2]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[3]\ : label is "yes";
attribute syn_keep : string;
attribute syn_keep of \gen_rep[0].fifoaddr_reg[0]\ : label is "1";
attribute syn_keep of \gen_rep[0].fifoaddr_reg[1]\ : label is "1";
attribute syn_keep of \gen_rep[0].fifoaddr_reg[2]\ : label is "1";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_axi_wdata[34]_INST_0\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_axi_wdata[35]_INST_0\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \s_axi_wready[0]_INST_0_i_2\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \s_axi_wready[2]_INST_0_i_3\ : label is "soft_lutpair81";
begin
m_axi_wvalid(0) <= \^m_axi_wvalid\(0);
out0(1 downto 0) <= \^out0\(1 downto 0);
\storage_data1_reg[1]_0\ <= \^storage_data1_reg[1]_0\;
\FSM_onehot_state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4555000000000000"
)
port map (
I0 => \^out0\(1),
I1 => m_ready_d(0),
I2 => Q(0),
I3 => aa_sa_awvalid,
I4 => \m_aready__1\,
I5 => \^out0\(0),
O => \FSM_onehot_state[0]_i_1_n_0\
);
\FSM_onehot_state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0A0A0A4A0A0A0A"
)
port map (
I0 => \^out0\(1),
I1 => \m_aready__1\,
I2 => \gen_arbiter.m_valid_i_reg\,
I3 => \FSM_onehot_state_reg_n_0_[3]\,
I4 => \m_valid_i_i_3__0_n_0\,
I5 => \^out0\(0),
O => \FSM_onehot_state[1]_i_1_n_0\
);
\FSM_onehot_state[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A0A0A0B5F5F5F5"
)
port map (
I0 => \^out0\(1),
I1 => \m_aready__1\,
I2 => \gen_arbiter.m_valid_i_reg\,
I3 => \FSM_onehot_state_reg_n_0_[3]\,
I4 => \m_valid_i_i_3__0_n_0\,
I5 => \^out0\(0),
O => \FSM_onehot_state[2]_i_1_n_0\
);
\FSM_onehot_state[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E3E2E322E322E322"
)
port map (
I0 => \^out0\(1),
I1 => \gen_arbiter.m_valid_i_reg\,
I2 => \m_aready__1\,
I3 => \^out0\(0),
I4 => \FSM_onehot_state_reg_n_0_[3]\,
I5 => \m_valid_i_i_3__0_n_0\,
O => \m_valid_i__0\
);
\FSM_onehot_state[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000002000AAAA"
)
port map (
I0 => \^out0\(0),
I1 => m_ready_d(0),
I2 => Q(0),
I3 => aa_sa_awvalid,
I4 => \m_aready__1\,
I5 => \^out0\(1),
O => \FSM_onehot_state[3]_i_2_n_0\
);
\FSM_onehot_state_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => \FSM_onehot_state[0]_i_1_n_0\,
Q => \^out0\(1),
S => in1
);
\FSM_onehot_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => \FSM_onehot_state[1]_i_1_n_0\,
Q => \^out0\(0),
R => in1
);
\FSM_onehot_state_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => \FSM_onehot_state[2]_i_1_n_0\,
Q => \FSM_onehot_state_reg_n_0_[2]\,
R => in1
);
\FSM_onehot_state_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => \FSM_onehot_state[3]_i_2_n_0\,
Q => \FSM_onehot_state_reg_n_0_[3]\,
R => in1
);
\gen_rep[0].fifoaddr[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"5AFBA504"
)
port map (
I0 => \m_aready__1\,
I1 => \^out0\(0),
I2 => \gen_arbiter.m_valid_i_reg\,
I3 => \FSM_onehot_state_reg_n_0_[3]\,
I4 => fifoaddr(0),
O => \gen_rep[0].fifoaddr[0]_i_1_n_0\
);
\gen_rep[0].fifoaddr[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BFBFF5F740400A08"
)
port map (
I0 => fifoaddr(0),
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => \gen_arbiter.m_valid_i_reg\,
I3 => \^out0\(0),
I4 => \m_aready__1\,
I5 => fifoaddr(1),
O => \gen_rep[0].fifoaddr[1]_i_1_n_0\
);
\gen_rep[0].fifoaddr[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F777EFFF08881000"
)
port map (
I0 => fifoaddr(1),
I1 => fifoaddr(0),
I2 => \m_aready__1\,
I3 => \FSM_onehot_state_reg_n_0_[3]\,
I4 => push,
I5 => fifoaddr(2),
O => \gen_rep[0].fifoaddr[2]_i_1_n_0\
);
\gen_rep[0].fifoaddr_reg[0]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[0]_i_1_n_0\,
Q => fifoaddr(0),
S => SR(0)
);
\gen_rep[0].fifoaddr_reg[1]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[1]_i_1_n_0\,
Q => fifoaddr(1),
S => SR(0)
);
\gen_rep[0].fifoaddr_reg[2]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[2]_i_1_n_0\,
Q => fifoaddr(2),
S => SR(0)
);
\gen_srls[0].gen_rep[0].srl_nx1\: entity work.\system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl__parameterized8\
port map (
A(2 downto 0) => fifoaddr(2 downto 0),
\FSM_onehot_state_reg[0]\ => \FSM_onehot_state_reg[0]_0\,
\FSM_onehot_state_reg[1]\ => \FSM_onehot_state_reg[1]_0\,
aclk => aclk,
\m_aready__1\ => \m_aready__1\,
m_select_enc_0(0) => m_select_enc_0(0),
out0(0) => \FSM_onehot_state_reg_n_0_[3]\,
push => push,
\storage_data1_reg[0]\ => \gen_srls[0].gen_rep[0].srl_nx1_n_0\
);
\gen_srls[0].gen_rep[1].srl_nx1\: entity work.\system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl__parameterized9\
port map (
A(2 downto 0) => fifoaddr(2 downto 0),
\FSM_onehot_state_reg[0]\ => \FSM_onehot_state_reg[0]_0\,
\FSM_onehot_state_reg[1]\ => \FSM_onehot_state_reg[1]_0\,
aa_wm_awgrant_enc(0) => aa_wm_awgrant_enc(0),
aclk => aclk,
\gen_arbiter.m_valid_i_reg\ => \gen_arbiter.m_valid_i_reg\,
\m_aready__1\ => \m_aready__1\,
m_avalid => m_avalid,
m_axi_wready(0) => m_axi_wready(0),
m_axi_wvalid(0) => \^m_axi_wvalid\(0),
m_select_enc => m_select_enc,
m_select_enc_0(0) => m_select_enc_0(0),
m_valid_i_reg => m_valid_i_reg_0,
out0(1) => \^out0\(0),
out0(0) => \FSM_onehot_state_reg_n_0_[3]\,
push => push,
s_axi_wlast(1 downto 0) => s_axi_wlast(1 downto 0),
\storage_data1_reg[0]\ => \storage_data1_reg[0]_0\,
\storage_data1_reg[1]\ => \gen_srls[0].gen_rep[1].srl_nx1_n_2\,
\storage_data1_reg[1]_0\ => \^storage_data1_reg[1]_0\
);
\m_axi_wdata[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(64),
I1 => s_axi_wdata(0),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(0)
);
\m_axi_wdata[10]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(74),
I1 => s_axi_wdata(10),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(10)
);
\m_axi_wdata[11]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(75),
I1 => s_axi_wdata(11),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(11)
);
\m_axi_wdata[12]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(76),
I1 => s_axi_wdata(12),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(12)
);
\m_axi_wdata[13]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(77),
I1 => s_axi_wdata(13),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(13)
);
\m_axi_wdata[14]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(78),
I1 => s_axi_wdata(14),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(14)
);
\m_axi_wdata[15]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(79),
I1 => s_axi_wdata(15),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(15)
);
\m_axi_wdata[16]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(80),
I1 => s_axi_wdata(16),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(16)
);
\m_axi_wdata[17]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(81),
I1 => s_axi_wdata(17),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(17)
);
\m_axi_wdata[18]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(82),
I1 => s_axi_wdata(18),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(18)
);
\m_axi_wdata[19]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(83),
I1 => s_axi_wdata(19),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(19)
);
\m_axi_wdata[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(65),
I1 => s_axi_wdata(1),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(1)
);
\m_axi_wdata[20]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(84),
I1 => s_axi_wdata(20),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(20)
);
\m_axi_wdata[21]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(85),
I1 => s_axi_wdata(21),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(21)
);
\m_axi_wdata[22]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(86),
I1 => s_axi_wdata(22),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(22)
);
\m_axi_wdata[23]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(87),
I1 => s_axi_wdata(23),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(23)
);
\m_axi_wdata[24]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(88),
I1 => s_axi_wdata(24),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(24)
);
\m_axi_wdata[25]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(89),
I1 => s_axi_wdata(25),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(25)
);
\m_axi_wdata[26]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(90),
I1 => s_axi_wdata(26),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(26)
);
\m_axi_wdata[27]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(91),
I1 => s_axi_wdata(27),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(27)
);
\m_axi_wdata[28]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(92),
I1 => s_axi_wdata(28),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(28)
);
\m_axi_wdata[29]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(93),
I1 => s_axi_wdata(29),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(29)
);
\m_axi_wdata[2]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(66),
I1 => s_axi_wdata(2),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(2)
);
\m_axi_wdata[30]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(94),
I1 => s_axi_wdata(30),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(30)
);
\m_axi_wdata[31]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(95),
I1 => s_axi_wdata(31),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(31)
);
\m_axi_wdata[32]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(96),
I1 => s_axi_wdata(32),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(32)
);
\m_axi_wdata[33]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(97),
I1 => s_axi_wdata(33),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(33)
);
\m_axi_wdata[34]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(98),
I1 => s_axi_wdata(34),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(34)
);
\m_axi_wdata[35]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(99),
I1 => s_axi_wdata(35),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(35)
);
\m_axi_wdata[36]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(100),
I1 => s_axi_wdata(36),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(36)
);
\m_axi_wdata[37]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(101),
I1 => s_axi_wdata(37),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(37)
);
\m_axi_wdata[38]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(102),
I1 => s_axi_wdata(38),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(38)
);
\m_axi_wdata[39]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(103),
I1 => s_axi_wdata(39),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(39)
);
\m_axi_wdata[3]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(67),
I1 => s_axi_wdata(3),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(3)
);
\m_axi_wdata[40]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(104),
I1 => s_axi_wdata(40),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(40)
);
\m_axi_wdata[41]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(105),
I1 => s_axi_wdata(41),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(41)
);
\m_axi_wdata[42]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(106),
I1 => s_axi_wdata(42),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(42)
);
\m_axi_wdata[43]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(107),
I1 => s_axi_wdata(43),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(43)
);
\m_axi_wdata[44]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(108),
I1 => s_axi_wdata(44),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(44)
);
\m_axi_wdata[45]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(109),
I1 => s_axi_wdata(45),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(45)
);
\m_axi_wdata[46]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(110),
I1 => s_axi_wdata(46),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(46)
);
\m_axi_wdata[47]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(111),
I1 => s_axi_wdata(47),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(47)
);
\m_axi_wdata[48]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(112),
I1 => s_axi_wdata(48),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(48)
);
\m_axi_wdata[49]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(113),
I1 => s_axi_wdata(49),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(49)
);
\m_axi_wdata[4]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(68),
I1 => s_axi_wdata(4),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(4)
);
\m_axi_wdata[50]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(114),
I1 => s_axi_wdata(50),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(50)
);
\m_axi_wdata[51]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(115),
I1 => s_axi_wdata(51),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(51)
);
\m_axi_wdata[52]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(116),
I1 => s_axi_wdata(52),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(52)
);
\m_axi_wdata[53]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(117),
I1 => s_axi_wdata(53),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(53)
);
\m_axi_wdata[54]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(118),
I1 => s_axi_wdata(54),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(54)
);
\m_axi_wdata[55]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(119),
I1 => s_axi_wdata(55),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(55)
);
\m_axi_wdata[56]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(120),
I1 => s_axi_wdata(56),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(56)
);
\m_axi_wdata[57]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(121),
I1 => s_axi_wdata(57),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(57)
);
\m_axi_wdata[58]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(122),
I1 => s_axi_wdata(58),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(58)
);
\m_axi_wdata[59]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(123),
I1 => s_axi_wdata(59),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(59)
);
\m_axi_wdata[5]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(69),
I1 => s_axi_wdata(5),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(5)
);
\m_axi_wdata[60]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(124),
I1 => s_axi_wdata(60),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(60)
);
\m_axi_wdata[61]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(125),
I1 => s_axi_wdata(61),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(61)
);
\m_axi_wdata[62]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(126),
I1 => s_axi_wdata(62),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(62)
);
\m_axi_wdata[63]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(127),
I1 => s_axi_wdata(63),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(63)
);
\m_axi_wdata[6]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(70),
I1 => s_axi_wdata(6),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(6)
);
\m_axi_wdata[7]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(71),
I1 => s_axi_wdata(7),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(7)
);
\m_axi_wdata[8]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(72),
I1 => s_axi_wdata(8),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(8)
);
\m_axi_wdata[9]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wdata(73),
I1 => s_axi_wdata(9),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wdata(9)
);
\m_axi_wlast[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => s_axi_wlast(0),
I1 => \^storage_data1_reg[1]_0\,
I2 => s_axi_wlast(1),
I3 => m_select_enc_0(0),
O => m_axi_wlast(0)
);
\m_axi_wstrb[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wstrb(8),
I1 => s_axi_wstrb(0),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wstrb(0)
);
\m_axi_wstrb[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wstrb(9),
I1 => s_axi_wstrb(1),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wstrb(1)
);
\m_axi_wstrb[2]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wstrb(10),
I1 => s_axi_wstrb(2),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wstrb(2)
);
\m_axi_wstrb[3]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wstrb(11),
I1 => s_axi_wstrb(3),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wstrb(3)
);
\m_axi_wstrb[4]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wstrb(12),
I1 => s_axi_wstrb(4),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wstrb(4)
);
\m_axi_wstrb[5]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wstrb(13),
I1 => s_axi_wstrb(5),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wstrb(5)
);
\m_axi_wstrb[6]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wstrb(14),
I1 => s_axi_wstrb(6),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wstrb(6)
);
\m_axi_wstrb[7]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A0C"
)
port map (
I0 => s_axi_wstrb(15),
I1 => s_axi_wstrb(7),
I2 => m_select_enc_0(0),
I3 => \^storage_data1_reg[1]_0\,
O => m_axi_wstrb(7)
);
m_valid_i: unisim.vcomponents.LUT6
generic map(
INIT => X"E3E2232223222322"
)
port map (
I0 => \^out0\(1),
I1 => \gen_arbiter.m_valid_i_reg\,
I2 => \m_aready__1\,
I3 => \^out0\(0),
I4 => \FSM_onehot_state_reg_n_0_[3]\,
I5 => \m_valid_i_i_3__0_n_0\,
O => m_valid_i_n_0
);
\m_valid_i_i_2__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000B80000000000"
)
port map (
I0 => s_axi_wlast(1),
I1 => \^storage_data1_reg[1]_0\,
I2 => s_axi_wlast(0),
I3 => m_axi_wready(0),
I4 => m_select_enc_0(0),
I5 => \^m_axi_wvalid\(0),
O => \m_aready__1\
);
\m_valid_i_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => fifoaddr(1),
I1 => fifoaddr(0),
I2 => fifoaddr(2),
O => \m_valid_i_i_3__0_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_valid_i__0\,
D => m_valid_i_n_0,
Q => m_avalid,
R => in1
);
\s_axi_wready[0]_INST_0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => m_select_enc_0(0),
I1 => \^storage_data1_reg[1]_0\,
O => s_ready_i_reg
);
\s_axi_wready[2]_INST_0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^storage_data1_reg[1]_0\,
I1 => m_select_enc_0(0),
O => s_ready_i_reg_0
);
\s_axi_wready[2]_INST_0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => m_axi_wready(0),
I1 => m_avalid,
O => s_ready_i_reg_1
);
\storage_data1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_srls[0].gen_rep[0].srl_nx1_n_0\,
Q => m_select_enc_0(0),
R => '0'
);
\storage_data1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_srls[0].gen_rep[1].srl_nx1_n_2\,
Q => \^storage_data1_reg[1]_0\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized1\ is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_1 : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_ready_i_reg : out STD_LOGIC;
\gen_axi.s_axi_wready_i_reg\ : out STD_LOGIC;
\storage_data1_reg[1]_0\ : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
push : in STD_LOGIC;
aclk : in STD_LOGIC;
aa_wm_awgrant_enc : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_arbiter.m_valid_i_reg\ : in STD_LOGIC;
in1 : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_sa_awvalid : in STD_LOGIC;
m_avalid : in STD_LOGIC;
p_10_in : in STD_LOGIC;
\storage_data1_reg[0]_0\ : in STD_LOGIC;
m_valid_i_reg_2 : in STD_LOGIC;
m_select_enc : in STD_LOGIC;
m_valid_i_reg_3 : in STD_LOGIC;
m_select_enc_0 : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_avalid_1 : in STD_LOGIC;
\storage_data1_reg[1]_1\ : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\ : in STD_LOGIC;
\m_ready_d_reg[0]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized1\ : entity is "axi_data_fifo_v2_1_10_axic_reg_srl_fifo";
end \system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized1\;
architecture STRUCTURE of \system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized1\ is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal fifoaddr : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^gen_axi.s_axi_wready_i_reg\ : STD_LOGIC;
signal \gen_rep[0].fifoaddr[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_rep[0].fifoaddr[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[0].srl_nx1_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[1].srl_nx1_n_1\ : STD_LOGIC;
signal m_avalid_0 : STD_LOGIC;
signal m_select_enc_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal m_valid_i_n_0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^m_valid_i_reg_1\ : STD_LOGIC;
signal \^s_ready_i_reg\ : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal \storage_data1[0]_i_1_n_0\ : STD_LOGIC;
signal \storage_data1[1]_i_1_n_0\ : STD_LOGIC;
signal \^storage_data1_reg[1]_0\ : STD_LOGIC;
attribute syn_keep : string;
attribute syn_keep of \gen_rep[0].fifoaddr_reg[0]\ : label is "1";
attribute syn_keep of \gen_rep[0].fifoaddr_reg[1]\ : label is "1";
begin
E(0) <= \^e\(0);
\gen_axi.s_axi_wready_i_reg\ <= \^gen_axi.s_axi_wready_i_reg\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
m_valid_i_reg_1 <= \^m_valid_i_reg_1\;
s_ready_i_reg <= \^s_ready_i_reg\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\storage_data1_reg[1]_0\ <= \^storage_data1_reg[1]_0\;
\FSM_onehot_state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1011111100000000"
)
port map (
I0 => \out\(0),
I1 => \^m_valid_i_reg_0\,
I2 => m_ready_d(0),
I3 => Q(0),
I4 => aa_sa_awvalid,
I5 => \out\(1),
O => D(0)
);
\FSM_onehot_state[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CB8BCB88CB88CB88"
)
port map (
I0 => \out\(0),
I1 => \gen_arbiter.m_valid_i_reg\,
I2 => \^m_valid_i_reg_0\,
I3 => \out\(1),
I4 => \out\(2),
I5 => \^m_valid_i_reg_1\,
O => \^e\(0)
);
\FSM_onehot_state[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008A888888"
)
port map (
I0 => \out\(1),
I1 => \^m_valid_i_reg_0\,
I2 => m_ready_d(0),
I3 => Q(0),
I4 => aa_sa_awvalid,
I5 => \out\(0),
O => D(1)
);
\gen_rep[0].fifoaddr[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"5A7FA580"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => \out\(1),
I2 => \gen_arbiter.m_valid_i_reg\,
I3 => \out\(2),
I4 => fifoaddr(0),
O => \gen_rep[0].fifoaddr[0]_i_1_n_0\
);
\gen_rep[0].fifoaddr[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5F7FFBFBA0800404"
)
port map (
I0 => fifoaddr(0),
I1 => \out\(2),
I2 => \gen_arbiter.m_valid_i_reg\,
I3 => \out\(1),
I4 => \^m_valid_i_reg_0\,
I5 => fifoaddr(1),
O => \gen_rep[0].fifoaddr[1]_i_1_n_0\
);
\gen_rep[0].fifoaddr_reg[0]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[0]_i_1_n_0\,
Q => fifoaddr(0),
S => SR(0)
);
\gen_rep[0].fifoaddr_reg[1]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[1]_i_1_n_0\,
Q => fifoaddr(1),
S => SR(0)
);
\gen_srls[0].gen_rep[0].srl_nx1\: entity work.system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl_7
port map (
A(1 downto 0) => fifoaddr(1 downto 0),
aclk => aclk,
push => push,
\storage_data1_reg[0]\ => \gen_srls[0].gen_rep[0].srl_nx1_n_0\
);
\gen_srls[0].gen_rep[1].srl_nx1\: entity work.system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl_8
port map (
A(1 downto 0) => fifoaddr(1 downto 0),
aa_wm_awgrant_enc(0) => aa_wm_awgrant_enc(0),
aclk => aclk,
m_avalid_0 => m_avalid_0,
m_avalid_1 => m_avalid_1,
m_select_enc_0 => m_select_enc_0,
m_select_enc_1(0) => m_select_enc_1(0),
m_valid_i_reg => \^m_valid_i_reg_0\,
m_valid_i_reg_0 => m_valid_i_reg_3,
\out\(0) => \out\(2),
p_10_in => p_10_in,
push => push,
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
\storage_data1_reg[1]\ => \gen_srls[0].gen_rep[1].srl_nx1_n_1\,
\storage_data1_reg[1]_0\ => \^storage_data1_reg[1]_0\
);
m_valid_i: unisim.vcomponents.LUT6
generic map(
INIT => X"CB8BC888C888C888"
)
port map (
I0 => \out\(0),
I1 => \gen_arbiter.m_valid_i_reg\,
I2 => \^m_valid_i_reg_0\,
I3 => \out\(1),
I4 => \out\(2),
I5 => \^m_valid_i_reg_1\,
O => m_valid_i_n_0
);
\m_valid_i_i_3__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => fifoaddr(0),
I1 => fifoaddr(1),
O => \^m_valid_i_reg_1\
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => m_valid_i_n_0,
Q => m_avalid_0,
R => in1
);
\s_axi_wready[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^s_ready_i_reg\,
I1 => m_avalid,
O => s_axi_wready(0)
);
\s_axi_wready[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"20202020FF000000"
)
port map (
I0 => \^gen_axi.s_axi_wready_i_reg\,
I1 => \^storage_data1_reg[1]_0\,
I2 => p_10_in,
I3 => \storage_data1_reg[0]_0\,
I4 => m_valid_i_reg_2,
I5 => m_select_enc,
O => \^s_ready_i_reg\
);
\s_axi_wready[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^s_ready_i_reg_0\,
I1 => m_avalid_1,
O => s_axi_wready(1)
);
\s_axi_wready[2]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"80808080FF000000"
)
port map (
I0 => \^gen_axi.s_axi_wready_i_reg\,
I1 => \^storage_data1_reg[1]_0\,
I2 => p_10_in,
I3 => \storage_data1_reg[1]_1\,
I4 => m_valid_i_reg_2,
I5 => m_select_enc_0,
O => \^s_ready_i_reg_0\
);
\s_axi_wready[2]_INST_0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => m_avalid_0,
I1 => m_select_enc_1(0),
O => \^gen_axi.s_axi_wready_i_reg\
);
\storage_data1[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8F888F8B80888088"
)
port map (
I0 => \gen_srls[0].gen_rep[0].srl_nx1_n_0\,
I1 => \out\(2),
I2 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\,
I3 => \^m_valid_i_reg_0\,
I4 => \m_ready_d_reg[0]\,
I5 => m_select_enc_1(0),
O => \storage_data1[0]_i_1_n_0\
);
\storage_data1[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFAAAFABA0AAA0A8"
)
port map (
I0 => \gen_srls[0].gen_rep[1].srl_nx1_n_1\,
I1 => \out\(2),
I2 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\,
I3 => \^m_valid_i_reg_0\,
I4 => \m_ready_d_reg[0]\,
I5 => \^storage_data1_reg[1]_0\,
O => \storage_data1[1]_i_1_n_0\
);
\storage_data1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \storage_data1[0]_i_1_n_0\,
Q => m_select_enc_1(0),
R => '0'
);
\storage_data1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \storage_data1[1]_i_1_n_0\,
Q => \^storage_data1_reg[1]_0\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_register_slice_v2_1_11_axi_register_slice is
port (
st_mr_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : out STD_LOGIC;
st_mr_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_axi_rready[0]\ : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_arbiter.qual_reg_reg[0]\ : out STD_LOGIC;
\valid_qual_i3__1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
p_2_in : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\gen_arbiter.grant_hot_reg[1]\ : out STD_LOGIC;
\gen_arbiter.qual_reg_reg[1]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : out STD_LOGIC;
\gen_single_thread.accept_cnt_reg[1]\ : out STD_LOGIC;
\gen_arbiter.qual_reg_reg[0]_0\ : out STD_LOGIC;
\valid_qual_i3__1_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_arbiter.qual_reg_reg[2]\ : out STD_LOGIC;
s_ready_i_reg_1 : out STD_LOGIC;
\gen_arbiter.grant_hot_reg[2]\ : out STD_LOGIC;
\gen_arbiter.grant_hot_reg[2]_0\ : out STD_LOGIC;
\gen_arbiter.grant_hot_reg[1]_0\ : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
active_target_enc : in STD_LOGIC;
active_target_enc_1 : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_valid_i_reg_0 : in STD_LOGIC;
r_issuing_cnt : in STD_LOGIC_VECTOR ( 4 downto 0 );
active_target_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[67]\ : in STD_LOGIC;
st_mr_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
active_target_hot_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].r_issuing_cnt_reg[0]_0\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_arbiter.m_target_hot_i_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_mi_arvalid : in STD_LOGIC;
st_aa_awvalid_qual : in STD_LOGIC_VECTOR ( 0 to 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gen_single_thread.active_target_enc_reg[0]\ : in STD_LOGIC;
sel_4 : in STD_LOGIC;
\gen_master_slots[0].w_issuing_cnt_reg[3]\ : in STD_LOGIC;
sel_4_3 : in STD_LOGIC;
active_target_hot_4 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 1 downto 0 );
active_target_hot_5 : in STD_LOGIC_VECTOR ( 0 to 0 );
active_target_enc_6 : in STD_LOGIC;
active_target_enc_7 : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
\m_axi_bid[1]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_register_slice_v2_1_11_axi_register_slice : entity is "axi_register_slice_v2_1_11_axi_register_slice";
end system_xbar_0_axi_register_slice_v2_1_11_axi_register_slice;
architecture STRUCTURE of system_xbar_0_axi_register_slice_v2_1_11_axi_register_slice is
signal \^m_valid_i_reg\ : STD_LOGIC;
signal \^p_1_in\ : STD_LOGIC;
begin
m_valid_i_reg <= \^m_valid_i_reg\;
p_1_in <= \^p_1_in\;
b_pipe: entity work.\system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized1_9\
port map (
aclk => aclk,
active_target_enc_6 => active_target_enc_6,
active_target_enc_7 => active_target_enc_7,
active_target_hot_4(0) => active_target_hot_4(0),
active_target_hot_5(0) => active_target_hot_5(0),
aresetn => aresetn,
\gen_arbiter.grant_hot_reg[2]\ => \gen_arbiter.grant_hot_reg[2]\,
\gen_arbiter.grant_hot_reg[2]_0\ => \gen_arbiter.grant_hot_reg[2]_0\,
\gen_arbiter.qual_reg_reg[0]\ => \gen_arbiter.qual_reg_reg[0]_0\,
\gen_arbiter.qual_reg_reg[2]\ => \gen_arbiter.qual_reg_reg[2]\,
\gen_master_slots[0].w_issuing_cnt_reg[3]\ => \gen_master_slots[0].w_issuing_cnt_reg[3]\,
\gen_single_thread.active_target_enc_reg[0]\ => \gen_single_thread.active_target_enc_reg[0]\,
\m_axi_bid[1]\(3 downto 0) => \m_axi_bid[1]\(3 downto 0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
\m_payload_i_reg[0]_0\ => st_mr_bvalid(0),
m_valid_i_reg_0 => \^m_valid_i_reg\,
p_1_in => \^p_1_in\,
s_axi_bready(1 downto 0) => s_axi_bready(1 downto 0),
s_axi_bresp(3 downto 0) => s_axi_bresp(3 downto 0),
s_ready_i_reg_0 => s_ready_i_reg,
s_ready_i_reg_1 => s_ready_i_reg_0,
s_ready_i_reg_2 => s_ready_i_reg_1,
sel_4 => sel_4,
sel_4_3 => sel_4_3,
st_aa_awvalid_qual(0) => st_aa_awvalid_qual(0),
\valid_qual_i3__1_0\(0) => \valid_qual_i3__1_0\(0),
w_issuing_cnt(4 downto 0) => w_issuing_cnt(4 downto 0)
);
r_pipe: entity work.\system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2_10\
port map (
D(2 downto 0) => D(2 downto 0),
Q(2 downto 0) => Q(2 downto 0),
aa_mi_arvalid => aa_mi_arvalid,
aclk => aclk,
active_target_enc => active_target_enc,
active_target_enc_1 => active_target_enc_1,
active_target_hot(0) => active_target_hot(0),
active_target_hot_2(0) => active_target_hot_2(0),
\aresetn_d_reg[1]\ => \^m_valid_i_reg\,
\gen_arbiter.grant_hot_reg[1]\ => \gen_arbiter.grant_hot_reg[1]\,
\gen_arbiter.grant_hot_reg[1]_0\ => \gen_arbiter.grant_hot_reg[1]_0\,
\gen_arbiter.m_target_hot_i_reg[0]\(0) => \gen_arbiter.m_target_hot_i_reg[0]\(0),
\gen_arbiter.qual_reg_reg[0]\ => \gen_arbiter.qual_reg_reg[0]\,
\gen_arbiter.qual_reg_reg[1]\ => \gen_arbiter.qual_reg_reg[1]\,
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].r_issuing_cnt_reg[0]\,
\gen_master_slots[0].r_issuing_cnt_reg[0]_0\ => \gen_master_slots[0].r_issuing_cnt_reg[0]_0\,
\gen_single_thread.accept_cnt_reg[1]\ => \gen_single_thread.accept_cnt_reg[1]\,
m_axi_arready(0) => m_axi_arready(0),
m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
m_axi_rid(1 downto 0) => m_axi_rid(1 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[0]\ => \m_axi_rready[0]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
\m_payload_i_reg[0]_0\ => st_mr_rvalid(0),
\m_payload_i_reg[0]_1\ => \m_payload_i_reg[0]\,
\m_payload_i_reg[67]_0\ => \m_payload_i_reg[67]\,
m_valid_i_reg_0 => m_valid_i_reg_0,
p_1_in => \^p_1_in\,
p_2_in => p_2_in,
r_issuing_cnt(4 downto 0) => r_issuing_cnt(4 downto 0),
s_axi_araddr(5 downto 0) => s_axi_araddr(5 downto 0),
s_axi_rdata(127 downto 0) => s_axi_rdata(127 downto 0),
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(1 downto 0) => s_axi_rready(1 downto 0),
st_mr_rlast(0) => st_mr_rlast(0),
\valid_qual_i3__1\(0) => \valid_qual_i3__1\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_register_slice_v2_1_11_axi_register_slice_1 is
port (
st_mr_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
mi_bready_1 : out STD_LOGIC;
mi_rready_1 : out STD_LOGIC;
st_mr_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_ready_i_reg : out STD_LOGIC;
p_2_in : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC_VECTOR ( 1 downto 0 );
st_mr_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_arbiter.grant_hot_reg[1]\ : out STD_LOGIC;
\gen_arbiter.grant_hot_reg[2]\ : out STD_LOGIC;
\gen_arbiter.grant_hot_reg[2]_0\ : out STD_LOGIC;
\s_axi_bvalid[2]\ : out STD_LOGIC;
\gen_arbiter.grant_hot_reg[2]_1\ : out STD_LOGIC;
\gen_single_thread.accept_cnt_reg[1]\ : out STD_LOGIC;
st_mr_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_arbiter.grant_hot_reg[1]_0\ : out STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
\gen_axi.s_axi_bvalid_i_reg\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
p_20_in : in STD_LOGIC_VECTOR ( 0 to 0 );
p_17_in : in STD_LOGIC;
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
p_11_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_valid_i_reg_0 : in STD_LOGIC;
active_target_enc : in STD_LOGIC;
\m_payload_i_reg[68]\ : in STD_LOGIC;
active_target_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
active_target_enc_0 : in STD_LOGIC;
active_target_hot_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
sel_4 : in STD_LOGIC;
w_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_awvalid_qual : in STD_LOGIC_VECTOR ( 0 to 0 );
\valid_qual_i3__1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_arbiter.last_rr_hot_reg[0]\ : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_single_thread.active_target_hot_reg[0]\ : in STD_LOGIC;
active_target_enc_2 : in STD_LOGIC;
\m_payload_i_reg[2]\ : in STD_LOGIC;
m_valid_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
active_target_hot_3 : in STD_LOGIC_VECTOR ( 0 to 0 );
active_target_enc_4 : in STD_LOGIC;
rready_carry : in STD_LOGIC_VECTOR ( 0 to 0 );
r_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
p_16_in : in STD_LOGIC_VECTOR ( 0 to 0 );
p_13_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_register_slice_v2_1_11_axi_register_slice_1 : entity is "axi_register_slice_v2_1_11_axi_register_slice";
end system_xbar_0_axi_register_slice_v2_1_11_axi_register_slice_1;
architecture STRUCTURE of system_xbar_0_axi_register_slice_v2_1_11_axi_register_slice_1 is
begin
b_pipe: entity work.\system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized1\
port map (
aclk => aclk,
active_target_enc_2 => active_target_enc_2,
active_target_enc_4 => active_target_enc_4,
active_target_hot_3(0) => active_target_hot_3(0),
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
\gen_arbiter.grant_hot_reg[2]\ => \gen_arbiter.grant_hot_reg[2]\,
\gen_arbiter.grant_hot_reg[2]_0\ => \gen_arbiter.grant_hot_reg[2]_0\,
\gen_arbiter.grant_hot_reg[2]_1\ => \gen_arbiter.grant_hot_reg[2]_1\,
\gen_arbiter.last_rr_hot_reg[0]\ => \gen_arbiter.last_rr_hot_reg[0]\,
\gen_axi.s_axi_bvalid_i_reg\ => \gen_axi.s_axi_bvalid_i_reg\,
\gen_single_thread.active_target_hot_reg[0]\ => \gen_single_thread.active_target_hot_reg[0]\,
\m_payload_i_reg[2]\ => \m_payload_i_reg[2]\,
\m_payload_i_reg[3]_0\ => st_mr_bid(0),
m_valid_i_reg_0(0) => m_valid_i_reg_1(0),
mi_bready_1 => mi_bready_1,
p_17_in => p_17_in,
p_1_in => p_1_in,
p_20_in(0) => p_20_in(0),
s_axi_bready(1 downto 0) => s_axi_bready(1 downto 0),
\s_axi_bvalid[2]\ => \s_axi_bvalid[2]\,
s_ready_i_reg_0 => st_mr_bvalid(0),
s_ready_i_reg_1 => s_ready_i_reg,
sel_4 => sel_4,
st_aa_awvalid_qual(0) => st_aa_awvalid_qual(0),
\valid_qual_i3__1\(0) => \valid_qual_i3__1\(0),
w_issuing_cnt(0) => w_issuing_cnt(0)
);
r_pipe: entity work.\system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\
port map (
Q(0) => Q(0),
aclk => aclk,
active_target_enc => active_target_enc,
active_target_enc_0 => active_target_enc_0,
active_target_hot(0) => active_target_hot(0),
active_target_hot_1(0) => active_target_hot_1(0),
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\gen_arbiter.grant_hot_reg[1]\ => \gen_arbiter.grant_hot_reg[1]\,
\gen_arbiter.grant_hot_reg[1]_0\ => \gen_arbiter.grant_hot_reg[1]_0\,
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].r_issuing_cnt_reg[8]\,
\gen_single_thread.accept_cnt_reg[1]\ => \gen_single_thread.accept_cnt_reg[1]\,
\m_payload_i_reg[66]_0\ => st_mr_rlast(0),
\m_payload_i_reg[67]_0\ => st_mr_rid(0),
\m_payload_i_reg[68]\ => \m_payload_i_reg[68]\,
m_valid_i_reg_0 => m_valid_i_reg_0,
m_valid_i_reg_1(0) => m_valid_i_reg(0),
p_11_in => p_11_in,
p_13_in => p_13_in,
p_16_in(0) => p_16_in(0),
p_1_in => p_1_in,
p_2_in => p_2_in,
r_issuing_cnt(0) => r_issuing_cnt(0),
rready_carry(0) => rready_carry(0),
s_axi_rlast(1 downto 0) => s_axi_rlast(1 downto 0),
s_axi_rready(1 downto 0) => s_axi_rready(1 downto 0),
s_axi_rvalid(1 downto 0) => s_axi_rvalid(1 downto 0),
\skid_buffer_reg[66]_0\ => mi_rready_1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_crossbar_v2_1_12_wdata_mux is
port (
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
\storage_data1_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_ready_i_reg : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
out0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_ready_i_reg_0 : out STD_LOGIC;
s_ready_i_reg_1 : out STD_LOGIC;
m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
aa_wm_awgrant_enc : in STD_LOGIC_VECTOR ( 0 to 0 );
in1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
\gen_arbiter.m_valid_i_reg\ : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
\storage_data1_reg[0]\ : in STD_LOGIC;
m_select_enc : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\FSM_onehot_state_reg[0]\ : in STD_LOGIC;
\FSM_onehot_state_reg[1]\ : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_sa_awvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_crossbar_v2_1_12_wdata_mux : entity is "axi_crossbar_v2_1_12_wdata_mux";
end system_xbar_0_axi_crossbar_v2_1_12_wdata_mux;
architecture STRUCTURE of system_xbar_0_axi_crossbar_v2_1_12_wdata_mux is
begin
\gen_wmux.wmux_aw_fifo\: entity work.\system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized0\
port map (
\FSM_onehot_state_reg[0]_0\ => \FSM_onehot_state_reg[0]\,
\FSM_onehot_state_reg[1]_0\ => \FSM_onehot_state_reg[1]\,
Q(0) => Q(0),
SR(0) => SR(0),
aa_sa_awvalid => aa_sa_awvalid,
aa_wm_awgrant_enc(0) => aa_wm_awgrant_enc(0),
aclk => aclk,
\gen_arbiter.m_valid_i_reg\ => \gen_arbiter.m_valid_i_reg\,
in1 => in1,
m_axi_wdata(63 downto 0) => m_axi_wdata(63 downto 0),
m_axi_wlast(0) => m_axi_wlast(0),
m_axi_wready(0) => m_axi_wready(0),
m_axi_wstrb(7 downto 0) => m_axi_wstrb(7 downto 0),
m_axi_wvalid(0) => m_axi_wvalid(0),
m_ready_d(0) => m_ready_d(0),
m_select_enc => m_select_enc,
m_valid_i_reg_0 => m_valid_i_reg,
out0(1 downto 0) => out0(1 downto 0),
s_axi_wdata(127 downto 0) => s_axi_wdata(127 downto 0),
s_axi_wlast(1 downto 0) => s_axi_wlast(1 downto 0),
s_axi_wstrb(15 downto 0) => s_axi_wstrb(15 downto 0),
s_ready_i_reg => s_ready_i_reg,
s_ready_i_reg_0 => s_ready_i_reg_0,
s_ready_i_reg_1 => s_ready_i_reg_1,
\storage_data1_reg[0]_0\ => \storage_data1_reg[0]\,
\storage_data1_reg[1]_0\ => \storage_data1_reg[1]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_xbar_0_axi_crossbar_v2_1_12_wdata_mux__parameterized0\ is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_ready_i_reg : out STD_LOGIC;
\gen_axi.s_axi_wready_i_reg\ : out STD_LOGIC;
\storage_data1_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_ready_i_reg_0 : out STD_LOGIC;
push : in STD_LOGIC;
aclk : in STD_LOGIC;
aa_wm_awgrant_enc : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_arbiter.m_valid_i_reg\ : in STD_LOGIC;
in1 : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_sa_awvalid : in STD_LOGIC;
m_avalid : in STD_LOGIC;
p_10_in : in STD_LOGIC;
\storage_data1_reg[0]\ : in STD_LOGIC;
m_valid_i_reg_1 : in STD_LOGIC;
m_select_enc : in STD_LOGIC;
m_valid_i_reg_2 : in STD_LOGIC;
m_select_enc_0 : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_avalid_1 : in STD_LOGIC;
\storage_data1_reg[1]_0\ : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\ : in STD_LOGIC;
\m_ready_d_reg[0]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_xbar_0_axi_crossbar_v2_1_12_wdata_mux__parameterized0\ : entity is "axi_crossbar_v2_1_12_wdata_mux";
end \system_xbar_0_axi_crossbar_v2_1_12_wdata_mux__parameterized0\;
architecture STRUCTURE of \system_xbar_0_axi_crossbar_v2_1_12_wdata_mux__parameterized0\ is
begin
\gen_wmux.wmux_aw_fifo\: entity work.\system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized1\
port map (
D(1 downto 0) => D(1 downto 0),
E(0) => E(0),
Q(0) => Q(0),
SR(0) => SR(0),
aa_sa_awvalid => aa_sa_awvalid,
aa_wm_awgrant_enc(0) => aa_wm_awgrant_enc(0),
aclk => aclk,
\gen_arbiter.m_valid_i_reg\ => \gen_arbiter.m_valid_i_reg\,
\gen_axi.s_axi_wready_i_reg\ => \gen_axi.s_axi_wready_i_reg\,
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\ => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\,
in1 => in1,
m_avalid => m_avalid,
m_avalid_1 => m_avalid_1,
m_ready_d(0) => m_ready_d(0),
\m_ready_d_reg[0]\ => \m_ready_d_reg[0]\,
m_select_enc => m_select_enc,
m_select_enc_0 => m_select_enc_0,
m_valid_i_reg_0 => m_valid_i_reg,
m_valid_i_reg_1 => m_valid_i_reg_0,
m_valid_i_reg_2 => m_valid_i_reg_1,
m_valid_i_reg_3 => m_valid_i_reg_2,
\out\(2 downto 0) => \out\(2 downto 0),
p_10_in => p_10_in,
push => push,
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(1 downto 0) => s_axi_wready(1 downto 0),
s_axi_wvalid(0) => s_axi_wvalid(0),
s_ready_i_reg => s_ready_i_reg,
s_ready_i_reg_0 => s_ready_i_reg_0,
\storage_data1_reg[0]_0\ => \storage_data1_reg[0]\,
\storage_data1_reg[1]_0\ => \storage_data1_reg[1]\(0),
\storage_data1_reg[1]_1\ => \storage_data1_reg[1]_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_crossbar_v2_1_12_wdata_router is
port (
m_avalid : out STD_LOGIC;
ss_wr_awready_0 : out STD_LOGIC;
m_select_enc : out STD_LOGIC;
\gen_axi.s_axi_wready_i_reg\ : out STD_LOGIC;
\gen_rep[0].fifoaddr_reg[2]\ : out STD_LOGIC;
aclk : in STD_LOGIC;
SS : in STD_LOGIC_VECTOR ( 0 to 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
\storage_data1_reg[1]\ : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[1]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
\storage_data1_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\storage_data1_reg[1]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_crossbar_v2_1_12_wdata_router : entity is "axi_crossbar_v2_1_12_wdata_router";
end system_xbar_0_axi_crossbar_v2_1_12_wdata_router;
architecture STRUCTURE of system_xbar_0_axi_crossbar_v2_1_12_wdata_router is
begin
wrouter_aw_fifo: entity work.system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo_5
port map (
SR(0) => SR(0),
SS(0) => SS(0),
aclk => aclk,
\gen_axi.s_axi_wready_i_reg\ => \gen_axi.s_axi_wready_i_reg\,
\gen_rep[0].fifoaddr_reg[2]\ => \gen_rep[0].fifoaddr_reg[2]\,
m_ready_d(0) => m_ready_d(0),
\m_ready_d_reg[1]\ => \m_ready_d_reg[1]\,
m_valid_i_reg_0 => m_valid_i_reg,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
s_ready_i_reg_0 => ss_wr_awready_0,
\storage_data1_reg[0]_0\ => m_avalid,
\storage_data1_reg[0]_1\ => m_select_enc,
\storage_data1_reg[1]\ => \storage_data1_reg[1]\,
\storage_data1_reg[1]_0\(0) => \storage_data1_reg[1]_0\(0),
\storage_data1_reg[1]_1\(0) => \storage_data1_reg[1]_1\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_crossbar_v2_1_12_wdata_router_3 is
port (
SS : out STD_LOGIC_VECTOR ( 0 to 0 );
m_avalid : out STD_LOGIC;
ss_wr_awready_2 : out STD_LOGIC;
m_select_enc : out STD_LOGIC;
\write_cs0__0\ : out STD_LOGIC;
\gen_axi.s_axi_wready_i_reg\ : out STD_LOGIC;
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
\storage_data1_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
\storage_data1_reg[1]_0\ : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[1]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_crossbar_v2_1_12_wdata_router_3 : entity is "axi_crossbar_v2_1_12_wdata_router";
end system_xbar_0_axi_crossbar_v2_1_12_wdata_router_3;
architecture STRUCTURE of system_xbar_0_axi_crossbar_v2_1_12_wdata_router_3 is
begin
wrouter_aw_fifo: entity work.system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo
port map (
SR(0) => SS(0),
aclk => aclk,
aresetn_d_reg(0) => SR(0),
\gen_axi.s_axi_wready_i_reg\ => \gen_axi.s_axi_wready_i_reg\,
m_ready_d(0) => m_ready_d(0),
\m_ready_d_reg[1]\ => \m_ready_d_reg[1]\,
m_select_enc => m_select_enc,
m_valid_i_reg_0 => m_valid_i_reg,
m_valid_i_reg_1 => m_valid_i_reg_0,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
s_ready_i_reg_0 => ss_wr_awready_2,
\storage_data1_reg[0]_0\ => m_avalid,
\storage_data1_reg[1]\(0) => \storage_data1_reg[1]\(0),
\storage_data1_reg[1]_0\ => \storage_data1_reg[1]_0\,
\write_cs0__0\ => \write_cs0__0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_crossbar_v2_1_12_crossbar is
port (
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_axi_rready[0]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
sa_wm_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
areset_d1 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 57 downto 0 );
\m_axi_arqos[3]\ : out STD_LOGIC_VECTOR ( 57 downto 0 );
\s_axi_arready[0]\ : out STD_LOGIC;
\s_axi_awready[2]\ : out STD_LOGIC;
\s_axi_awready[0]\ : out STD_LOGIC;
\s_axi_arready[1]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
aresetn : in STD_LOGIC;
m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_axi_bid[1]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_crossbar_v2_1_12_crossbar : entity is "axi_crossbar_v2_1_12_crossbar";
end system_xbar_0_axi_crossbar_v2_1_12_crossbar;
architecture STRUCTURE of system_xbar_0_axi_crossbar_v2_1_12_crossbar is
signal \^q\ : STD_LOGIC_VECTOR ( 57 downto 0 );
signal aa_mi_artarget_hot : STD_LOGIC_VECTOR ( 1 downto 0 );
signal aa_mi_arvalid : STD_LOGIC;
signal aa_mi_awtarget_hot : STD_LOGIC_VECTOR ( 1 downto 0 );
signal aa_sa_awready : STD_LOGIC;
signal aa_sa_awvalid : STD_LOGIC;
signal aa_wm_awgrant_enc : STD_LOGIC_VECTOR ( 1 to 1 );
signal active_target_enc : STD_LOGIC;
signal active_target_enc_11 : STD_LOGIC;
signal active_target_enc_13 : STD_LOGIC;
signal active_target_enc_8 : STD_LOGIC;
signal active_target_hot : STD_LOGIC_VECTOR ( 0 to 0 );
signal active_target_hot_10 : STD_LOGIC_VECTOR ( 0 to 0 );
signal active_target_hot_12 : STD_LOGIC_VECTOR ( 0 to 0 );
signal active_target_hot_7 : STD_LOGIC_VECTOR ( 0 to 0 );
signal addr_arbiter_ar_n_3 : STD_LOGIC;
signal addr_arbiter_ar_n_64 : STD_LOGIC;
signal addr_arbiter_ar_n_65 : STD_LOGIC;
signal addr_arbiter_ar_n_67 : STD_LOGIC;
signal addr_arbiter_ar_n_68 : STD_LOGIC;
signal addr_arbiter_ar_n_70 : STD_LOGIC;
signal addr_arbiter_ar_n_72 : STD_LOGIC;
signal addr_arbiter_ar_n_73 : STD_LOGIC;
signal addr_arbiter_ar_n_75 : STD_LOGIC;
signal addr_arbiter_ar_n_76 : STD_LOGIC;
signal addr_arbiter_aw_n_10 : STD_LOGIC;
signal addr_arbiter_aw_n_12 : STD_LOGIC;
signal addr_arbiter_aw_n_13 : STD_LOGIC;
signal addr_arbiter_aw_n_14 : STD_LOGIC;
signal addr_arbiter_aw_n_15 : STD_LOGIC;
signal addr_arbiter_aw_n_16 : STD_LOGIC;
signal addr_arbiter_aw_n_17 : STD_LOGIC;
signal addr_arbiter_aw_n_23 : STD_LOGIC;
signal addr_arbiter_aw_n_24 : STD_LOGIC;
signal addr_arbiter_aw_n_25 : STD_LOGIC;
signal addr_arbiter_aw_n_26 : STD_LOGIC;
signal addr_arbiter_aw_n_3 : STD_LOGIC;
signal addr_arbiter_aw_n_4 : STD_LOGIC;
signal addr_arbiter_aw_n_7 : STD_LOGIC;
signal addr_arbiter_aw_n_8 : STD_LOGIC;
signal \^areset_d1\ : STD_LOGIC;
signal aresetn_d : STD_LOGIC;
signal bready_carry : STD_LOGIC_VECTOR ( 5 to 5 );
signal \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4_0\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4_1\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4_2\ : STD_LOGIC;
signal \gen_decerr_slave.decerr_slave_inst_n_8\ : STD_LOGIC;
signal \gen_master_slots[0].gen_mi_write.wdata_mux_w_n_73\ : STD_LOGIC;
signal \gen_master_slots[0].gen_mi_write.wdata_mux_w_n_77\ : STD_LOGIC;
signal \gen_master_slots[0].gen_mi_write.wdata_mux_w_n_78\ : STD_LOGIC;
signal \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_1\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_139\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_142\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_143\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_144\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_145\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_146\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_147\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_148\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_149\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_150\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_152\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_153\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_154\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_155\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_156\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_6\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_7\ : STD_LOGIC;
signal \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].gen_mi_write.wdata_mux_w_n_10\ : STD_LOGIC;
signal \gen_master_slots[1].gen_mi_write.wdata_mux_w_n_7\ : STD_LOGIC;
signal \gen_master_slots[1].gen_mi_write.wdata_mux_w_n_8\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_11\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_12\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_13\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_15\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_16\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_18\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_19\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_4\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_4\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_5\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_0\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_2\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_3\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_6\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.wdata_router_w_n_3\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.wdata_router_w_n_4\ : STD_LOGIC;
signal \gen_slave_slots[1].gen_si_read.si_transactor_ar_n_4\ : STD_LOGIC;
signal \gen_slave_slots[1].gen_si_read.si_transactor_ar_n_5\ : STD_LOGIC;
signal \gen_slave_slots[2].gen_si_write.si_transactor_aw_n_2\ : STD_LOGIC;
signal \gen_slave_slots[2].gen_si_write.splitter_aw_si_n_0\ : STD_LOGIC;
signal \gen_slave_slots[2].gen_si_write.splitter_aw_si_n_2\ : STD_LOGIC;
signal \gen_slave_slots[2].gen_si_write.splitter_aw_si_n_3\ : STD_LOGIC;
signal \gen_slave_slots[2].gen_si_write.splitter_aw_si_n_6\ : STD_LOGIC;
signal \gen_slave_slots[2].gen_si_write.wdata_router_w_n_5\ : STD_LOGIC;
signal \gen_wmux.wmux_aw_fifo/p_0_in6_in\ : STD_LOGIC;
signal \gen_wmux.wmux_aw_fifo/p_7_in\ : STD_LOGIC;
signal \gen_wmux.wmux_aw_fifo/push\ : STD_LOGIC;
signal m_avalid : STD_LOGIC;
signal m_avalid_16 : STD_LOGIC;
signal \^m_axi_arqos[3]\ : STD_LOGIC_VECTOR ( 57 downto 0 );
signal m_ready_d : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m_ready_d_14 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m_ready_d_17 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m_select_enc : STD_LOGIC_VECTOR ( 1 to 1 );
signal m_select_enc_15 : STD_LOGIC;
signal m_select_enc_5 : STD_LOGIC_VECTOR ( 1 to 1 );
signal m_select_enc_9 : STD_LOGIC;
signal \^m_valid_i_reg\ : STD_LOGIC;
signal mi_arready : STD_LOGIC_VECTOR ( 1 to 1 );
signal mi_awready : STD_LOGIC_VECTOR ( 1 to 1 );
signal mi_bready_1 : STD_LOGIC;
signal mi_rready_1 : STD_LOGIC;
signal next_enc : STD_LOGIC_VECTOR ( 0 to 0 );
signal next_enc_3 : STD_LOGIC_VECTOR ( 1 to 1 );
signal p_10_in : STD_LOGIC;
signal p_11_in : STD_LOGIC;
signal p_13_in : STD_LOGIC;
signal p_16_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_17_in : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_20_in : STD_LOGIC_VECTOR ( 1 to 1 );
signal p_2_in : STD_LOGIC;
signal p_2_in_6 : STD_LOGIC;
signal r_issuing_cnt : STD_LOGIC_VECTOR ( 8 downto 0 );
signal reset : STD_LOGIC;
signal rready_carry : STD_LOGIC_VECTOR ( 5 to 5 );
signal \^s_axi_arready[0]\ : STD_LOGIC;
signal \^s_axi_arready[1]\ : STD_LOGIC;
signal \^s_axi_awready[0]\ : STD_LOGIC;
signal \^s_axi_awready[2]\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_rlast\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^sa_wm_awvalid\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal splitter_aw_mi_n_1 : STD_LOGIC;
signal ss_aa_awready : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ss_wr_awready_0 : STD_LOGIC;
signal ss_wr_awready_2 : STD_LOGIC;
signal st_aa_arvalid_qual : STD_LOGIC_VECTOR ( 1 downto 0 );
signal st_aa_awvalid_qual : STD_LOGIC_VECTOR ( 2 downto 0 );
signal st_mr_bid : STD_LOGIC_VECTOR ( 3 to 3 );
signal st_mr_bvalid : STD_LOGIC_VECTOR ( 1 downto 0 );
signal st_mr_rid : STD_LOGIC_VECTOR ( 2 to 2 );
signal st_mr_rlast : STD_LOGIC_VECTOR ( 1 downto 0 );
signal st_mr_rmesg : STD_LOGIC_VECTOR ( 1 downto 0 );
signal st_mr_rvalid : STD_LOGIC_VECTOR ( 0 to 0 );
signal \valid_qual_i3__1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \valid_qual_i3__1_4\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal w_issuing_cnt : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \write_cs0__0\ : STD_LOGIC;
begin
Q(57 downto 0) <= \^q\(57 downto 0);
areset_d1 <= \^areset_d1\;
\m_axi_arqos[3]\(57 downto 0) <= \^m_axi_arqos[3]\(57 downto 0);
m_valid_i_reg <= \^m_valid_i_reg\;
\s_axi_arready[0]\ <= \^s_axi_arready[0]\;
\s_axi_arready[1]\ <= \^s_axi_arready[1]\;
\s_axi_awready[0]\ <= \^s_axi_awready[0]\;
\s_axi_awready[2]\ <= \^s_axi_awready[2]\;
s_axi_bvalid(1 downto 0) <= \^s_axi_bvalid\(1 downto 0);
s_axi_rlast(1 downto 0) <= \^s_axi_rlast\(1 downto 0);
sa_wm_awvalid(0) <= \^sa_wm_awvalid\(0);
addr_arbiter_ar: entity work.system_xbar_0_axi_crossbar_v2_1_12_addr_arbiter
port map (
D(1) => \gen_slave_slots[1].gen_si_read.si_transactor_ar_n_5\,
D(0) => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_5\,
E(0) => addr_arbiter_ar_n_73,
Q(1 downto 0) => aa_mi_artarget_hot(1 downto 0),
SR(0) => reset,
aa_mi_arvalid => aa_mi_arvalid,
aclk => aclk,
active_target_enc => active_target_enc,
active_target_enc_2 => active_target_enc_11,
active_target_hot(0) => active_target_hot(0),
active_target_hot_1(0) => active_target_hot_10(0),
aresetn_d => aresetn_d,
\gen_arbiter.last_rr_hot_reg[0]_0\ => addr_arbiter_ar_n_72,
\gen_arbiter.qual_reg_reg[1]_0\ => addr_arbiter_ar_n_75,
\gen_axi.s_axi_rid_i_reg[0]\ => addr_arbiter_ar_n_3,
\gen_axi.s_axi_rlast_i_reg\ => addr_arbiter_ar_n_76,
\gen_master_slots[0].r_issuing_cnt_reg[2]\ => \gen_slave_slots[1].gen_si_read.si_transactor_ar_n_4\,
\gen_master_slots[0].r_issuing_cnt_reg[2]_0\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_4\,
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => addr_arbiter_ar_n_64,
\gen_master_slots[1].r_issuing_cnt_reg[8]_0\ => \gen_master_slots[0].reg_slice_mi_n_144\,
\gen_single_thread.active_target_enc_reg[0]\ => addr_arbiter_ar_n_67,
\gen_single_thread.active_target_enc_reg[0]_0\ => addr_arbiter_ar_n_70,
\gen_single_thread.active_target_hot_reg[0]\ => addr_arbiter_ar_n_65,
\gen_single_thread.active_target_hot_reg[0]_0\ => addr_arbiter_ar_n_68,
\m_axi_arqos[3]\(57 downto 0) => \^m_axi_arqos[3]\(57 downto 0),
m_axi_arready(0) => m_axi_arready(0),
m_axi_arvalid(0) => m_axi_arvalid(0),
m_valid_i_reg => \gen_master_slots[1].reg_slice_mi_n_19\,
m_valid_i_reg_0 => \gen_master_slots[0].reg_slice_mi_n_148\,
mi_arready(0) => mi_arready(1),
next_enc(0) => next_enc(0),
p_11_in => p_11_in,
p_16_in(0) => p_16_in(0),
r_issuing_cnt(4) => r_issuing_cnt(8),
r_issuing_cnt(3 downto 0) => r_issuing_cnt(3 downto 0),
s_axi_araddr(63 downto 0) => s_axi_araddr(63 downto 0),
s_axi_arburst(3 downto 0) => s_axi_arburst(3 downto 0),
s_axi_arcache(7 downto 0) => s_axi_arcache(7 downto 0),
s_axi_arlen(15 downto 0) => s_axi_arlen(15 downto 0),
s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0),
s_axi_arprot(5 downto 0) => s_axi_arprot(5 downto 0),
s_axi_arqos(7 downto 0) => s_axi_arqos(7 downto 0),
\s_axi_arready[0]\ => \^s_axi_arready[0]\,
\s_axi_arready[1]\ => \^s_axi_arready[1]\,
s_axi_arsize(5 downto 0) => s_axi_arsize(5 downto 0),
s_axi_arvalid(1 downto 0) => s_axi_arvalid(1 downto 0),
sel_4 => \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4_0\,
sel_4_0 => \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
st_aa_arvalid_qual(1 downto 0) => st_aa_arvalid_qual(1 downto 0),
\valid_qual_i3__1\(0) => \valid_qual_i3__1_4\(0)
);
addr_arbiter_aw: entity work.system_xbar_0_axi_crossbar_v2_1_12_addr_arbiter_0
port map (
D(2) => addr_arbiter_aw_n_15,
D(1) => addr_arbiter_aw_n_16,
D(0) => addr_arbiter_aw_n_17,
E(0) => addr_arbiter_aw_n_14,
Q(1 downto 0) => aa_mi_awtarget_hot(1 downto 0),
SR(0) => reset,
aa_sa_awready => aa_sa_awready,
aa_sa_awvalid => aa_sa_awvalid,
aa_wm_awgrant_enc(0) => aa_wm_awgrant_enc(1),
aclk => aclk,
aresetn_d => aresetn_d,
\gen_arbiter.last_rr_hot_reg[0]_0\ => addr_arbiter_aw_n_3,
\gen_arbiter.m_valid_i_reg_0\ => splitter_aw_mi_n_1,
\gen_arbiter.qual_reg_reg[2]_0\ => addr_arbiter_aw_n_26,
\gen_axi.s_axi_awready_i_reg\ => addr_arbiter_aw_n_12,
\gen_master_slots[1].w_issuing_cnt_reg[8]\ => addr_arbiter_aw_n_7,
\gen_master_slots[1].w_issuing_cnt_reg[8]_0\ => \gen_master_slots[0].reg_slice_mi_n_150\,
\gen_master_slots[1].w_issuing_cnt_reg[8]_1\ => \gen_master_slots[1].reg_slice_mi_n_12\,
\gen_rep[0].fifoaddr_reg[0]\ => addr_arbiter_aw_n_24,
\gen_single_thread.accept_cnt_reg[0]\ => \gen_slave_slots[2].gen_si_write.si_transactor_aw_n_2\,
\gen_single_thread.active_target_enc_reg[0]\ => \gen_master_slots[1].reg_slice_mi_n_4\,
\gen_single_thread.active_target_hot_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_7\,
\m_axi_awqos[3]\(57 downto 0) => \^q\(57 downto 0),
m_axi_awready(0) => m_axi_awready(0),
m_axi_awvalid(0) => m_axi_awvalid(0),
m_ready_d(1 downto 0) => m_ready_d_17(1 downto 0),
m_ready_d_1(0) => m_ready_d(0),
m_ready_d_2(0) => m_ready_d_14(0),
\m_ready_d_reg[0]\(1) => \gen_slave_slots[2].gen_si_write.splitter_aw_si_n_3\,
\m_ready_d_reg[0]\(0) => \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_3\,
\m_ready_d_reg[1]\ => addr_arbiter_aw_n_13,
\m_ready_d_reg[1]_0\ => addr_arbiter_aw_n_25,
m_valid_i_reg => \^sa_wm_awvalid\(0),
m_valid_i_reg_0 => \gen_master_slots[0].reg_slice_mi_n_152\,
mi_awready(0) => mi_awready(1),
next_enc(0) => next_enc_3(1),
\out\(2 downto 0) => \out\(2 downto 0),
out0(1) => \gen_wmux.wmux_aw_fifo/p_7_in\,
out0(0) => \gen_wmux.wmux_aw_fifo/p_0_in6_in\,
push => \gen_wmux.wmux_aw_fifo/push\,
s_axi_awaddr(63 downto 0) => s_axi_awaddr(63 downto 0),
s_axi_awburst(3 downto 0) => s_axi_awburst(3 downto 0),
s_axi_awcache(7 downto 0) => s_axi_awcache(7 downto 0),
s_axi_awlen(15 downto 0) => s_axi_awlen(15 downto 0),
s_axi_awlock(1 downto 0) => s_axi_awlock(1 downto 0),
s_axi_awprot(5 downto 0) => s_axi_awprot(5 downto 0),
s_axi_awqos(7 downto 0) => s_axi_awqos(7 downto 0),
s_axi_awsize(5 downto 0) => s_axi_awsize(5 downto 0),
s_axi_awvalid(1 downto 0) => s_axi_awvalid(1 downto 0),
sel_4 => \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4_2\,
sel_4_0 => \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4_1\,
ss_aa_awready(1) => ss_aa_awready(2),
ss_aa_awready(0) => ss_aa_awready(0),
st_aa_awvalid_qual(0) => st_aa_awvalid_qual(2),
\storage_data1_reg[0]\ => addr_arbiter_aw_n_4,
\storage_data1_reg[0]_0\ => addr_arbiter_aw_n_10,
\storage_data1_reg[1]\ => addr_arbiter_aw_n_8,
\storage_data1_reg[1]_0\ => addr_arbiter_aw_n_23,
\storage_data1_reg[1]_1\ => \^m_valid_i_reg\,
w_issuing_cnt(4) => w_issuing_cnt(8),
w_issuing_cnt(3 downto 0) => w_issuing_cnt(3 downto 0)
);
aresetn_d_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => aresetn_d,
R => '0'
);
\gen_decerr_slave.decerr_slave_inst\: entity work.system_xbar_0_axi_crossbar_v2_1_12_decerr_slave
port map (
Q(0) => \^q\(0),
SR(0) => reset,
aa_mi_arvalid => aa_mi_arvalid,
aclk => aclk,
aresetn_d => aresetn_d,
bready_carry(0) => bready_carry(5),
\gen_arbiter.m_mesg_i_reg[0]\ => addr_arbiter_ar_n_3,
\gen_arbiter.m_mesg_i_reg[41]\(7 downto 0) => \^m_axi_arqos[3]\(40 downto 33),
\gen_arbiter.m_target_hot_i_reg[1]\(0) => aa_mi_artarget_hot(1),
\gen_axi.read_cs_reg[0]_0\ => addr_arbiter_ar_n_76,
\gen_axi.s_axi_awready_i_reg_0\ => addr_arbiter_aw_n_12,
m_valid_i_reg => \gen_decerr_slave.decerr_slave_inst_n_8\,
mi_arready(0) => mi_arready(1),
mi_awready(0) => mi_awready(1),
mi_bready_1 => mi_bready_1,
mi_rready_1 => mi_rready_1,
p_10_in => p_10_in,
p_11_in => p_11_in,
p_13_in => p_13_in,
p_16_in(0) => p_16_in(0),
p_17_in => p_17_in,
p_20_in(0) => p_20_in(1),
\write_cs0__0\ => \write_cs0__0\
);
\gen_master_slots[0].gen_mi_write.wdata_mux_w\: entity work.system_xbar_0_axi_crossbar_v2_1_12_wdata_mux
port map (
\FSM_onehot_state_reg[0]\ => addr_arbiter_aw_n_8,
\FSM_onehot_state_reg[1]\ => addr_arbiter_aw_n_23,
Q(0) => aa_mi_awtarget_hot(0),
SR(0) => reset,
aa_sa_awvalid => aa_sa_awvalid,
aa_wm_awgrant_enc(0) => aa_wm_awgrant_enc(1),
aclk => aclk,
\gen_arbiter.m_valid_i_reg\ => addr_arbiter_aw_n_24,
in1 => \^areset_d1\,
m_axi_wdata(63 downto 0) => m_axi_wdata(63 downto 0),
m_axi_wlast(0) => m_axi_wlast(0),
m_axi_wready(0) => m_axi_wready(0),
m_axi_wstrb(7 downto 0) => m_axi_wstrb(7 downto 0),
m_axi_wvalid(0) => m_axi_wvalid(0),
m_ready_d(0) => m_ready_d_17(0),
m_select_enc => m_select_enc_15,
m_valid_i_reg => \gen_slave_slots[2].gen_si_write.wdata_router_w_n_5\,
out0(1) => \gen_wmux.wmux_aw_fifo/p_7_in\,
out0(0) => \gen_wmux.wmux_aw_fifo/p_0_in6_in\,
s_axi_wdata(127 downto 0) => s_axi_wdata(127 downto 0),
s_axi_wlast(1 downto 0) => s_axi_wlast(1 downto 0),
s_axi_wstrb(15 downto 0) => s_axi_wstrb(15 downto 0),
s_ready_i_reg => \gen_master_slots[0].gen_mi_write.wdata_mux_w_n_73\,
s_ready_i_reg_0 => \gen_master_slots[0].gen_mi_write.wdata_mux_w_n_77\,
s_ready_i_reg_1 => \gen_master_slots[0].gen_mi_write.wdata_mux_w_n_78\,
\storage_data1_reg[0]\ => \gen_slave_slots[0].gen_si_write.wdata_router_w_n_4\,
\storage_data1_reg[1]\(0) => m_select_enc(1)
);
\gen_master_slots[0].r_issuing_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(0),
O => \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\
);
\gen_master_slots[0].r_issuing_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_73,
D => \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\,
Q => r_issuing_cnt(0),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_73,
D => \gen_master_slots[0].reg_slice_mi_n_147\,
Q => r_issuing_cnt(1),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_73,
D => \gen_master_slots[0].reg_slice_mi_n_146\,
Q => r_issuing_cnt(2),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_73,
D => \gen_master_slots[0].reg_slice_mi_n_145\,
Q => r_issuing_cnt(3),
R => reset
);
\gen_master_slots[0].reg_slice_mi\: entity work.system_xbar_0_axi_register_slice_v2_1_11_axi_register_slice
port map (
D(2) => \gen_master_slots[0].reg_slice_mi_n_145\,
D(1) => \gen_master_slots[0].reg_slice_mi_n_146\,
D(0) => \gen_master_slots[0].reg_slice_mi_n_147\,
Q(2) => st_mr_rlast(0),
Q(1 downto 0) => st_mr_rmesg(1 downto 0),
aa_mi_arvalid => aa_mi_arvalid,
aclk => aclk,
active_target_enc => active_target_enc_11,
active_target_enc_1 => active_target_enc,
active_target_enc_6 => active_target_enc_13,
active_target_enc_7 => active_target_enc_8,
active_target_hot(0) => active_target_hot_10(0),
active_target_hot_2(0) => active_target_hot(0),
active_target_hot_4(0) => active_target_hot_12(0),
active_target_hot_5(0) => active_target_hot_7(0),
aresetn => aresetn,
\gen_arbiter.grant_hot_reg[1]\ => \gen_master_slots[0].reg_slice_mi_n_143\,
\gen_arbiter.grant_hot_reg[1]_0\ => \gen_master_slots[0].reg_slice_mi_n_156\,
\gen_arbiter.grant_hot_reg[2]\ => \gen_master_slots[0].reg_slice_mi_n_154\,
\gen_arbiter.grant_hot_reg[2]_0\ => \gen_master_slots[0].reg_slice_mi_n_155\,
\gen_arbiter.m_target_hot_i_reg[0]\(0) => aa_mi_artarget_hot(0),
\gen_arbiter.qual_reg_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_139\,
\gen_arbiter.qual_reg_reg[0]_0\ => \gen_master_slots[0].reg_slice_mi_n_150\,
\gen_arbiter.qual_reg_reg[1]\ => \gen_master_slots[0].reg_slice_mi_n_144\,
\gen_arbiter.qual_reg_reg[2]\ => \gen_master_slots[0].reg_slice_mi_n_152\,
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_148\,
\gen_master_slots[0].r_issuing_cnt_reg[0]_0\ => addr_arbiter_ar_n_75,
\gen_master_slots[0].w_issuing_cnt_reg[3]\ => addr_arbiter_aw_n_26,
\gen_single_thread.accept_cnt_reg[1]\ => \gen_master_slots[0].reg_slice_mi_n_149\,
\gen_single_thread.active_target_enc_reg[0]\ => \gen_master_slots[1].reg_slice_mi_n_4\,
m_axi_arready(0) => m_axi_arready(0),
\m_axi_bid[1]\(3 downto 0) => \m_axi_bid[1]\(3 downto 0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
m_axi_rid(1 downto 0) => m_axi_rid(1 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[0]\ => \m_axi_rready[0]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
\m_payload_i_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_142\,
\m_payload_i_reg[67]\ => \gen_master_slots[1].reg_slice_mi_n_16\,
m_valid_i_reg => \gen_master_slots[0].reg_slice_mi_n_1\,
m_valid_i_reg_0 => \gen_master_slots[1].reg_slice_mi_n_19\,
p_1_in => p_1_in,
p_2_in => p_2_in,
r_issuing_cnt(4) => r_issuing_cnt(8),
r_issuing_cnt(3 downto 0) => r_issuing_cnt(3 downto 0),
s_axi_araddr(5 downto 3) => s_axi_araddr(63 downto 61),
s_axi_araddr(2 downto 0) => s_axi_araddr(31 downto 29),
s_axi_bready(1 downto 0) => s_axi_bready(1 downto 0),
s_axi_bresp(3 downto 0) => s_axi_bresp(3 downto 0),
s_axi_rdata(127 downto 0) => s_axi_rdata(127 downto 0),
s_axi_rlast(0) => \^s_axi_rlast\(1),
s_axi_rready(1 downto 0) => s_axi_rready(1 downto 0),
s_ready_i_reg => \gen_master_slots[0].reg_slice_mi_n_6\,
s_ready_i_reg_0 => \gen_master_slots[0].reg_slice_mi_n_7\,
s_ready_i_reg_1 => \gen_master_slots[0].reg_slice_mi_n_153\,
sel_4 => \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4_2\,
sel_4_3 => \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4_1\,
st_aa_awvalid_qual(0) => st_aa_awvalid_qual(0),
st_mr_bvalid(0) => st_mr_bvalid(0),
st_mr_rlast(0) => st_mr_rlast(1),
st_mr_rvalid(0) => st_mr_rvalid(0),
\valid_qual_i3__1\(0) => \valid_qual_i3__1_4\(0),
\valid_qual_i3__1_0\(0) => \valid_qual_i3__1\(0),
w_issuing_cnt(4) => w_issuing_cnt(8),
w_issuing_cnt(3 downto 0) => w_issuing_cnt(3 downto 0)
);
\gen_master_slots[0].w_issuing_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(0),
O => \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\
);
\gen_master_slots[0].w_issuing_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_14,
D => \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\,
Q => w_issuing_cnt(0),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_14,
D => addr_arbiter_aw_n_17,
Q => w_issuing_cnt(1),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_14,
D => addr_arbiter_aw_n_16,
Q => w_issuing_cnt(2),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_14,
D => addr_arbiter_aw_n_15,
Q => w_issuing_cnt(3),
R => reset
);
\gen_master_slots[1].gen_mi_write.wdata_mux_w\: entity work.\system_xbar_0_axi_crossbar_v2_1_12_wdata_mux__parameterized0\
port map (
D(1 downto 0) => D(1 downto 0),
E(0) => E(0),
Q(0) => aa_mi_awtarget_hot(1),
SR(0) => reset,
aa_sa_awvalid => aa_sa_awvalid,
aa_wm_awgrant_enc(0) => aa_wm_awgrant_enc(1),
aclk => aclk,
\gen_arbiter.m_valid_i_reg\ => \^sa_wm_awvalid\(0),
\gen_axi.s_axi_wready_i_reg\ => \gen_master_slots[1].gen_mi_write.wdata_mux_w_n_8\,
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\ => addr_arbiter_aw_n_4,
in1 => \^areset_d1\,
m_avalid => m_avalid,
m_avalid_1 => m_avalid_16,
m_ready_d(0) => m_ready_d_17(0),
\m_ready_d_reg[0]\ => addr_arbiter_aw_n_10,
m_select_enc => m_select_enc_9,
m_select_enc_0 => m_select_enc_15,
m_valid_i_reg => \^m_valid_i_reg\,
m_valid_i_reg_0 => m_valid_i_reg_0,
m_valid_i_reg_1 => \gen_master_slots[0].gen_mi_write.wdata_mux_w_n_78\,
m_valid_i_reg_2 => \gen_slave_slots[0].gen_si_write.wdata_router_w_n_3\,
\out\(2 downto 0) => \out\(2 downto 0),
p_10_in => p_10_in,
push => \gen_wmux.wmux_aw_fifo/push\,
s_axi_wlast(0) => s_axi_wlast(1),
s_axi_wready(1 downto 0) => s_axi_wready(1 downto 0),
s_axi_wvalid(0) => s_axi_wvalid(1),
s_ready_i_reg => \gen_master_slots[1].gen_mi_write.wdata_mux_w_n_7\,
s_ready_i_reg_0 => \gen_master_slots[1].gen_mi_write.wdata_mux_w_n_10\,
\storage_data1_reg[0]\ => \gen_master_slots[0].gen_mi_write.wdata_mux_w_n_73\,
\storage_data1_reg[1]\(0) => m_select_enc_5(1),
\storage_data1_reg[1]_0\ => \gen_master_slots[0].gen_mi_write.wdata_mux_w_n_77\
);
\gen_master_slots[1].r_issuing_cnt_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => addr_arbiter_ar_n_64,
Q => r_issuing_cnt(8),
R => reset
);
\gen_master_slots[1].reg_slice_mi\: entity work.system_xbar_0_axi_register_slice_v2_1_11_axi_register_slice_1
port map (
Q(0) => st_mr_rlast(0),
aclk => aclk,
active_target_enc => active_target_enc,
active_target_enc_0 => active_target_enc_11,
active_target_enc_2 => active_target_enc_13,
active_target_enc_4 => active_target_enc_8,
active_target_hot(0) => active_target_hot(0),
active_target_hot_1(0) => active_target_hot_10(0),
active_target_hot_3(0) => active_target_hot_12(0),
\aresetn_d_reg[1]\ => \gen_master_slots[0].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[0].reg_slice_mi_n_6\,
\gen_arbiter.grant_hot_reg[1]\ => \gen_master_slots[1].reg_slice_mi_n_11\,
\gen_arbiter.grant_hot_reg[1]_0\ => \gen_master_slots[1].reg_slice_mi_n_18\,
\gen_arbiter.grant_hot_reg[2]\ => \gen_master_slots[1].reg_slice_mi_n_12\,
\gen_arbiter.grant_hot_reg[2]_0\ => \gen_master_slots[1].reg_slice_mi_n_13\,
\gen_arbiter.grant_hot_reg[2]_1\ => \gen_master_slots[1].reg_slice_mi_n_15\,
\gen_arbiter.last_rr_hot_reg[0]\ => addr_arbiter_aw_n_3,
\gen_axi.s_axi_bvalid_i_reg\ => \gen_decerr_slave.decerr_slave_inst_n_8\,
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].reg_slice_mi_n_19\,
\gen_single_thread.accept_cnt_reg[1]\ => \gen_master_slots[1].reg_slice_mi_n_16\,
\gen_single_thread.active_target_hot_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_155\,
\m_payload_i_reg[2]\ => \gen_master_slots[0].reg_slice_mi_n_153\,
\m_payload_i_reg[68]\ => \gen_master_slots[0].reg_slice_mi_n_142\,
m_valid_i_reg(0) => st_mr_rvalid(0),
m_valid_i_reg_0 => \gen_master_slots[0].reg_slice_mi_n_149\,
m_valid_i_reg_1(0) => st_mr_bvalid(0),
mi_bready_1 => mi_bready_1,
mi_rready_1 => mi_rready_1,
p_11_in => p_11_in,
p_13_in => p_13_in,
p_16_in(0) => p_16_in(0),
p_17_in => p_17_in,
p_1_in => p_1_in,
p_20_in(0) => p_20_in(1),
p_2_in => p_2_in_6,
r_issuing_cnt(0) => r_issuing_cnt(8),
rready_carry(0) => rready_carry(5),
s_axi_bready(1 downto 0) => s_axi_bready(1 downto 0),
\s_axi_bvalid[2]\ => \^s_axi_bvalid\(1),
s_axi_rlast(1 downto 0) => \^s_axi_rlast\(1 downto 0),
s_axi_rready(1 downto 0) => s_axi_rready(1 downto 0),
s_axi_rvalid(1 downto 0) => s_axi_rvalid(1 downto 0),
s_ready_i_reg => \gen_master_slots[1].reg_slice_mi_n_4\,
sel_4 => \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4_2\,
st_aa_awvalid_qual(0) => st_aa_awvalid_qual(0),
st_mr_bid(0) => st_mr_bid(3),
st_mr_bvalid(0) => st_mr_bvalid(1),
st_mr_rid(0) => st_mr_rid(2),
st_mr_rlast(0) => st_mr_rlast(1),
\valid_qual_i3__1\(0) => \valid_qual_i3__1\(0),
w_issuing_cnt(0) => w_issuing_cnt(8)
);
\gen_master_slots[1].w_issuing_cnt_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => addr_arbiter_aw_n_7,
Q => w_issuing_cnt(8),
R => reset
);
\gen_slave_slots[0].gen_si_read.si_transactor_ar\: entity work.system_xbar_0_axi_crossbar_v2_1_12_si_transactor
port map (
D(0) => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_5\,
Q(1 downto 0) => st_mr_rmesg(1 downto 0),
SR(0) => reset,
aclk => aclk,
active_target_enc => active_target_enc,
active_target_enc_0 => active_target_enc_11,
active_target_hot(0) => active_target_hot(0),
\gen_arbiter.grant_hot_reg[1]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_4\,
\gen_arbiter.last_rr_hot_reg[0]\ => addr_arbiter_ar_n_72,
\gen_arbiter.s_ready_i_reg[0]\ => addr_arbiter_ar_n_67,
\gen_arbiter.s_ready_i_reg[0]_0\ => addr_arbiter_ar_n_65,
\gen_arbiter.s_ready_i_reg[0]_1\ => \^s_axi_arready[0]\,
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[0].reg_slice_mi_n_139\,
\m_payload_i_reg[66]\ => \gen_master_slots[1].reg_slice_mi_n_18\,
\m_payload_i_reg[66]_0\ => \gen_master_slots[0].reg_slice_mi_n_156\,
m_valid_i_reg => \gen_master_slots[0].reg_slice_mi_n_149\,
m_valid_i_reg_0 => \gen_master_slots[1].reg_slice_mi_n_11\,
p_2_in => p_2_in_6,
rready_carry(0) => rready_carry(5),
s_axi_araddr(2 downto 0) => s_axi_araddr(31 downto 29),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_rready(1 downto 0) => s_axi_rready(1 downto 0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
sel_4 => \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4_0\,
st_aa_arvalid_qual(0) => st_aa_arvalid_qual(0),
st_mr_rid(0) => st_mr_rid(2),
\valid_qual_i3__1\(0) => \valid_qual_i3__1_4\(0)
);
\gen_slave_slots[0].gen_si_write.si_transactor_aw\: entity work.\system_xbar_0_axi_crossbar_v2_1_12_si_transactor__parameterized0\
port map (
SR(0) => reset,
aclk => aclk,
active_target_enc => active_target_enc_8,
active_target_hot(0) => active_target_hot_7(0),
\gen_single_thread.active_target_enc_reg[0]_0\ => \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_2\,
\gen_single_thread.active_target_hot_reg[0]_0\ => \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_0\,
\m_payload_i_reg[2]\ => \gen_master_slots[0].reg_slice_mi_n_153\,
\m_payload_i_reg[3]\ => \gen_master_slots[1].reg_slice_mi_n_15\,
m_valid_i_reg => \gen_master_slots[0].reg_slice_mi_n_154\,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(31 downto 29),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bvalid(0) => \^s_axi_bvalid\(0),
s_ready_i_reg => \^s_axi_awready[0]\,
st_aa_awvalid_qual(0) => st_aa_awvalid_qual(0),
st_mr_bid(0) => st_mr_bid(3),
st_mr_bvalid(1 downto 0) => st_mr_bvalid(1 downto 0)
);
\gen_slave_slots[0].gen_si_write.splitter_aw_si\: entity work.system_xbar_0_axi_crossbar_v2_1_12_splitter
port map (
aclk => aclk,
active_target_enc => active_target_enc_8,
active_target_hot(0) => active_target_hot_7(0),
aresetn_d => aresetn_d,
\gen_arbiter.qual_reg_reg[0]\(0) => \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_3\,
\gen_master_slots[1].w_issuing_cnt_reg[8]\ => \gen_master_slots[0].reg_slice_mi_n_150\,
\gen_rep[0].fifoaddr_reg[0]\ => \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_6\,
\gen_single_thread.active_target_enc_reg[0]\ => \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_2\,
\gen_single_thread.active_target_hot_reg[0]\ => \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_0\,
m_ready_d(1 downto 0) => m_ready_d(1 downto 0),
s_axi_awaddr(2 downto 0) => s_axi_awaddr(31 downto 29),
\s_axi_awready[0]\ => \^s_axi_awready[0]\,
s_axi_awvalid(0) => s_axi_awvalid(0),
ss_aa_awready(0) => ss_aa_awready(0),
ss_wr_awready_0 => ss_wr_awready_0
);
\gen_slave_slots[0].gen_si_write.wdata_router_w\: entity work.system_xbar_0_axi_crossbar_v2_1_12_wdata_router
port map (
SR(0) => reset,
SS(0) => \^areset_d1\,
aclk => aclk,
\gen_axi.s_axi_wready_i_reg\ => \gen_slave_slots[0].gen_si_write.wdata_router_w_n_3\,
\gen_rep[0].fifoaddr_reg[2]\ => \gen_slave_slots[0].gen_si_write.wdata_router_w_n_4\,
m_avalid => m_avalid,
m_ready_d(0) => m_ready_d(1),
\m_ready_d_reg[1]\ => \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_6\,
m_select_enc => m_select_enc_9,
m_valid_i_reg => \gen_master_slots[1].gen_mi_write.wdata_mux_w_n_8\,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(31 downto 29),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
ss_wr_awready_0 => ss_wr_awready_0,
\storage_data1_reg[1]\ => \gen_master_slots[1].gen_mi_write.wdata_mux_w_n_7\,
\storage_data1_reg[1]_0\(0) => m_select_enc_5(1),
\storage_data1_reg[1]_1\(0) => m_select_enc(1)
);
\gen_slave_slots[1].gen_si_read.si_transactor_ar\: entity work.\system_xbar_0_axi_crossbar_v2_1_12_si_transactor__parameterized1\
port map (
D(0) => \gen_slave_slots[1].gen_si_read.si_transactor_ar_n_5\,
Q(1 downto 0) => st_mr_rmesg(1 downto 0),
SR(0) => reset,
aclk => aclk,
active_target_enc => active_target_enc_11,
active_target_hot(0) => active_target_hot_10(0),
\gen_arbiter.grant_hot_reg[1]\ => \gen_slave_slots[1].gen_si_read.si_transactor_ar_n_4\,
\gen_arbiter.s_ready_i_reg[1]\ => addr_arbiter_ar_n_70,
\gen_arbiter.s_ready_i_reg[1]_0\ => addr_arbiter_ar_n_68,
\gen_arbiter.s_ready_i_reg[1]_1\ => \^s_axi_arready[1]\,
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[0].reg_slice_mi_n_144\,
\m_payload_i_reg[66]\ => \gen_master_slots[1].reg_slice_mi_n_18\,
\m_payload_i_reg[66]_0\ => \gen_master_slots[0].reg_slice_mi_n_143\,
\m_payload_i_reg[67]\ => \gen_master_slots[1].reg_slice_mi_n_16\,
next_enc(0) => next_enc(0),
p_2_in => p_2_in,
s_axi_araddr(2 downto 0) => s_axi_araddr(63 downto 61),
s_axi_arvalid(0) => s_axi_arvalid(1),
s_axi_rready(0) => s_axi_rready(1),
s_axi_rresp(1 downto 0) => s_axi_rresp(3 downto 2),
sel_4 => \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
st_aa_arvalid_qual(0) => st_aa_arvalid_qual(1),
st_mr_rvalid(0) => st_mr_rvalid(0),
\valid_qual_i3__1\(0) => \valid_qual_i3__1_4\(0)
);
\gen_slave_slots[2].gen_si_write.si_transactor_aw\: entity work.\system_xbar_0_axi_crossbar_v2_1_12_si_transactor__parameterized2\
port map (
SR(0) => reset,
aclk => aclk,
active_target_enc => active_target_enc_13,
active_target_enc_0 => active_target_enc_8,
active_target_hot(0) => active_target_hot_12(0),
bready_carry(0) => bready_carry(5),
\gen_arbiter.grant_hot_reg[2]\ => \gen_slave_slots[2].gen_si_write.si_transactor_aw_n_2\,
\gen_single_thread.active_target_enc_reg[0]_0\ => \gen_slave_slots[2].gen_si_write.splitter_aw_si_n_2\,
\gen_single_thread.active_target_enc_reg[0]_1\ => \gen_master_slots[1].reg_slice_mi_n_13\,
\gen_single_thread.active_target_hot_reg[0]_0\ => \gen_slave_slots[2].gen_si_write.splitter_aw_si_n_0\,
\m_payload_i_reg[3]\ => \^s_axi_bvalid\(1),
m_valid_i_reg => \gen_master_slots[0].reg_slice_mi_n_152\,
next_enc(0) => next_enc_3(1),
s_axi_awaddr(2 downto 0) => s_axi_awaddr(63 downto 61),
s_axi_bready(1 downto 0) => s_axi_bready(1 downto 0),
s_ready_i_reg => \^s_axi_awready[2]\,
sel_4 => \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4_1\,
st_aa_awvalid_qual(0) => st_aa_awvalid_qual(2),
st_mr_bid(0) => st_mr_bid(3)
);
\gen_slave_slots[2].gen_si_write.splitter_aw_si\: entity work.system_xbar_0_axi_crossbar_v2_1_12_splitter_2
port map (
aclk => aclk,
active_target_enc => active_target_enc_13,
active_target_hot(0) => active_target_hot_12(0),
aresetn_d => aresetn_d,
\gen_arbiter.qual_reg_reg[2]\(0) => \gen_slave_slots[2].gen_si_write.splitter_aw_si_n_3\,
\gen_rep[0].fifoaddr_reg[0]\ => \gen_slave_slots[2].gen_si_write.splitter_aw_si_n_6\,
\gen_single_thread.active_target_enc_reg[0]\ => \gen_slave_slots[2].gen_si_write.splitter_aw_si_n_2\,
\gen_single_thread.active_target_hot_reg[0]\ => \gen_slave_slots[2].gen_si_write.splitter_aw_si_n_0\,
m_ready_d(1 downto 0) => m_ready_d_14(1 downto 0),
m_valid_i_reg => \gen_master_slots[0].reg_slice_mi_n_152\,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(63 downto 61),
\s_axi_awready[2]\ => \^s_axi_awready[2]\,
s_axi_awvalid(0) => s_axi_awvalid(1),
ss_aa_awready(0) => ss_aa_awready(2),
ss_wr_awready_2 => ss_wr_awready_2,
st_aa_awvalid_qual(0) => st_aa_awvalid_qual(2)
);
\gen_slave_slots[2].gen_si_write.wdata_router_w\: entity work.system_xbar_0_axi_crossbar_v2_1_12_wdata_router_3
port map (
SR(0) => reset,
SS(0) => \^areset_d1\,
aclk => aclk,
\gen_axi.s_axi_wready_i_reg\ => \gen_slave_slots[2].gen_si_write.wdata_router_w_n_5\,
m_avalid => m_avalid_16,
m_ready_d(0) => m_ready_d_14(1),
\m_ready_d_reg[1]\ => \gen_slave_slots[2].gen_si_write.splitter_aw_si_n_6\,
m_select_enc => m_select_enc_15,
m_valid_i_reg => \gen_master_slots[1].gen_mi_write.wdata_mux_w_n_8\,
m_valid_i_reg_0 => \gen_slave_slots[0].gen_si_write.wdata_router_w_n_3\,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(63 downto 61),
s_axi_awvalid(0) => s_axi_awvalid(1),
s_axi_wlast(0) => s_axi_wlast(1),
s_axi_wvalid(0) => s_axi_wvalid(1),
ss_wr_awready_2 => ss_wr_awready_2,
\storage_data1_reg[1]\(0) => m_select_enc_5(1),
\storage_data1_reg[1]_0\ => \gen_master_slots[1].gen_mi_write.wdata_mux_w_n_10\,
\write_cs0__0\ => \write_cs0__0\
);
splitter_aw_mi: entity work.system_xbar_0_axi_crossbar_v2_1_12_splitter_4
port map (
Q(1 downto 0) => aa_mi_awtarget_hot(1 downto 0),
aa_sa_awready => aa_sa_awready,
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_arbiter.grant_hot_reg[2]\ => splitter_aw_mi_n_1,
\gen_arbiter.m_target_hot_i_reg[0]\ => addr_arbiter_aw_n_25,
\gen_arbiter.m_target_hot_i_reg[1]\ => addr_arbiter_aw_n_13,
m_axi_awready(0) => m_axi_awready(0),
m_ready_d(1 downto 0) => m_ready_d_17(1 downto 0),
mi_awready(0) => mi_awready(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 95 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wid : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 191 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wuser : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 95 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 191 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_ruser : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 2;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute C_DEBUG : integer;
attribute C_DEBUG of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "zynq";
attribute C_M_AXI_ADDR_WIDTH : integer;
attribute C_M_AXI_ADDR_WIDTH of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 29;
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : integer;
attribute C_M_AXI_READ_CONNECTIVITY of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 3;
attribute C_M_AXI_READ_ISSUING : integer;
attribute C_M_AXI_READ_ISSUING of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 8;
attribute C_M_AXI_SECURE : integer;
attribute C_M_AXI_SECURE of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 0;
attribute C_M_AXI_WRITE_CONNECTIVITY : integer;
attribute C_M_AXI_WRITE_CONNECTIVITY of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 5;
attribute C_M_AXI_WRITE_ISSUING : integer;
attribute C_M_AXI_WRITE_ISSUING of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 8;
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 3;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 0;
attribute C_S_AXI_ARB_PRIORITY : string;
attribute C_S_AXI_ARB_PRIORITY of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_S_AXI_BASE_ID : string;
attribute C_S_AXI_BASE_ID of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "96'b000000000000000000000000000000100000000000000000000000000000000100000000000000000000000000000000";
attribute C_S_AXI_READ_ACCEPTANCE : string;
attribute C_S_AXI_READ_ACCEPTANCE of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "96'b000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010";
attribute C_S_AXI_SINGLE_THREAD : string;
attribute C_S_AXI_SINGLE_THREAD of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_S_AXI_THREAD_ID_WIDTH : string;
attribute C_S_AXI_THREAD_ID_WIDTH of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_S_AXI_WRITE_ACCEPTANCE : string;
attribute C_S_AXI_WRITE_ACCEPTANCE of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "96'b000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "axi_crossbar_v2_1_12_axi_crossbar";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "zynq";
attribute P_INCR : string;
attribute P_INCR of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 8;
attribute P_LOCK : integer;
attribute P_LOCK of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "32'b00000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "1'b1";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "1'b1";
attribute P_ONES : string;
attribute P_ONES of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "192'b000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "192'b000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "3'b011";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "3'b101";
end system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar;
architecture STRUCTURE of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar is
signal \<const0>\ : STD_LOGIC;
signal \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state[2]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[2]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[2]\ : signal is "yes";
signal \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[3]\ : STD_LOGIC;
attribute RTL_KEEP of \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[3]\ : signal is "yes";
signal \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i\ : STD_LOGIC;
signal \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_0_in6_in\ : STD_LOGIC;
attribute RTL_KEEP of \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_0_in6_in\ : signal is "yes";
signal \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_7_in\ : STD_LOGIC;
attribute RTL_KEEP of \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_7_in\ : signal is "yes";
signal \gen_samd.crossbar_samd_n_259\ : STD_LOGIC;
signal \gen_samd.crossbar_samd_n_260\ : STD_LOGIC;
signal \gen_samd.crossbar_samd_n_4\ : STD_LOGIC;
signal \gen_samd.crossbar_samd_n_5\ : STD_LOGIC;
signal \gen_slave_slots[2].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1\ : STD_LOGIC;
signal \^m_axi_arid\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_axi_awid\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^s_axi_arready\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_awready\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_bresp\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^s_axi_bvalid\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 127 downto 0 );
signal \^s_axi_rlast\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_rresp\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_rvalid\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_wready\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal sa_wm_awvalid : STD_LOGIC_VECTOR ( 1 to 1 );
attribute KEEP : string;
attribute KEEP of \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\ : label is "yes";
attribute KEEP of \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\ : label is "yes";
attribute KEEP of \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[2]\ : label is "yes";
attribute KEEP of \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\ : label is "yes";
begin
m_axi_arid(1) <= \<const0>\;
m_axi_arid(0) <= \^m_axi_arid\(0);
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awid(1) <= \^m_axi_awid\(1);
m_axi_awid(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
s_axi_arready(2) <= \<const0>\;
s_axi_arready(1 downto 0) <= \^s_axi_arready\(1 downto 0);
s_axi_awready(2) <= \^s_axi_awready\(2);
s_axi_awready(1) <= \<const0>\;
s_axi_awready(0) <= \^s_axi_awready\(0);
s_axi_bid(5) <= \<const0>\;
s_axi_bid(4) <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(5 downto 4) <= \^s_axi_bresp\(5 downto 4);
s_axi_bresp(3) <= \<const0>\;
s_axi_bresp(2) <= \<const0>\;
s_axi_bresp(1 downto 0) <= \^s_axi_bresp\(1 downto 0);
s_axi_buser(2) <= \<const0>\;
s_axi_buser(1) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid(2) <= \^s_axi_bvalid\(2);
s_axi_bvalid(1) <= \<const0>\;
s_axi_bvalid(0) <= \^s_axi_bvalid\(0);
s_axi_rdata(191) <= \<const0>\;
s_axi_rdata(190) <= \<const0>\;
s_axi_rdata(189) <= \<const0>\;
s_axi_rdata(188) <= \<const0>\;
s_axi_rdata(187) <= \<const0>\;
s_axi_rdata(186) <= \<const0>\;
s_axi_rdata(185) <= \<const0>\;
s_axi_rdata(184) <= \<const0>\;
s_axi_rdata(183) <= \<const0>\;
s_axi_rdata(182) <= \<const0>\;
s_axi_rdata(181) <= \<const0>\;
s_axi_rdata(180) <= \<const0>\;
s_axi_rdata(179) <= \<const0>\;
s_axi_rdata(178) <= \<const0>\;
s_axi_rdata(177) <= \<const0>\;
s_axi_rdata(176) <= \<const0>\;
s_axi_rdata(175) <= \<const0>\;
s_axi_rdata(174) <= \<const0>\;
s_axi_rdata(173) <= \<const0>\;
s_axi_rdata(172) <= \<const0>\;
s_axi_rdata(171) <= \<const0>\;
s_axi_rdata(170) <= \<const0>\;
s_axi_rdata(169) <= \<const0>\;
s_axi_rdata(168) <= \<const0>\;
s_axi_rdata(167) <= \<const0>\;
s_axi_rdata(166) <= \<const0>\;
s_axi_rdata(165) <= \<const0>\;
s_axi_rdata(164) <= \<const0>\;
s_axi_rdata(163) <= \<const0>\;
s_axi_rdata(162) <= \<const0>\;
s_axi_rdata(161) <= \<const0>\;
s_axi_rdata(160) <= \<const0>\;
s_axi_rdata(159) <= \<const0>\;
s_axi_rdata(158) <= \<const0>\;
s_axi_rdata(157) <= \<const0>\;
s_axi_rdata(156) <= \<const0>\;
s_axi_rdata(155) <= \<const0>\;
s_axi_rdata(154) <= \<const0>\;
s_axi_rdata(153) <= \<const0>\;
s_axi_rdata(152) <= \<const0>\;
s_axi_rdata(151) <= \<const0>\;
s_axi_rdata(150) <= \<const0>\;
s_axi_rdata(149) <= \<const0>\;
s_axi_rdata(148) <= \<const0>\;
s_axi_rdata(147) <= \<const0>\;
s_axi_rdata(146) <= \<const0>\;
s_axi_rdata(145) <= \<const0>\;
s_axi_rdata(144) <= \<const0>\;
s_axi_rdata(143) <= \<const0>\;
s_axi_rdata(142) <= \<const0>\;
s_axi_rdata(141) <= \<const0>\;
s_axi_rdata(140) <= \<const0>\;
s_axi_rdata(139) <= \<const0>\;
s_axi_rdata(138) <= \<const0>\;
s_axi_rdata(137) <= \<const0>\;
s_axi_rdata(136) <= \<const0>\;
s_axi_rdata(135) <= \<const0>\;
s_axi_rdata(134) <= \<const0>\;
s_axi_rdata(133) <= \<const0>\;
s_axi_rdata(132) <= \<const0>\;
s_axi_rdata(131) <= \<const0>\;
s_axi_rdata(130) <= \<const0>\;
s_axi_rdata(129) <= \<const0>\;
s_axi_rdata(128) <= \<const0>\;
s_axi_rdata(127 downto 0) <= \^s_axi_rdata\(127 downto 0);
s_axi_rid(5) <= \<const0>\;
s_axi_rid(4) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast(2) <= \<const0>\;
s_axi_rlast(1 downto 0) <= \^s_axi_rlast\(1 downto 0);
s_axi_rresp(5) <= \<const0>\;
s_axi_rresp(4) <= \<const0>\;
s_axi_rresp(3 downto 0) <= \^s_axi_rresp\(3 downto 0);
s_axi_ruser(2) <= \<const0>\;
s_axi_ruser(1) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid(2) <= \<const0>\;
s_axi_rvalid(1 downto 0) <= \^s_axi_rvalid\(1 downto 0);
s_axi_wready(2) <= \^s_axi_wready\(2);
s_axi_wready(1) <= \<const0>\;
s_axi_wready(0) <= \^s_axi_wready\(0);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A0A0A0A1A0A0A0"
)
port map (
I0 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_7_in\,
I1 => \gen_samd.crossbar_samd_n_4\,
I2 => sa_wm_awvalid(1),
I3 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[3]\,
I4 => \gen_samd.crossbar_samd_n_5\,
I5 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_0_in6_in\,
O => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state[1]_i_1_n_0\
);
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0A0A0A5E5F5F5F"
)
port map (
I0 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_7_in\,
I1 => \gen_samd.crossbar_samd_n_4\,
I2 => sa_wm_awvalid(1),
I3 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[3]\,
I4 => \gen_samd.crossbar_samd_n_5\,
I5 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_0_in6_in\,
O => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state[2]_i_1_n_0\
);
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i\,
D => \gen_samd.crossbar_samd_n_260\,
Q => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_7_in\,
S => \gen_slave_slots[2].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1\
);
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i\,
D => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state[1]_i_1_n_0\,
Q => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_0_in6_in\,
R => \gen_slave_slots[2].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1\
);
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i\,
D => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state[2]_i_1_n_0\,
Q => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[2]\,
R => \gen_slave_slots[2].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1\
);
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i\,
D => \gen_samd.crossbar_samd_n_259\,
Q => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[3]\,
R => \gen_slave_slots[2].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1\
);
\gen_samd.crossbar_samd\: entity work.system_xbar_0_axi_crossbar_v2_1_12_crossbar
port map (
D(1) => \gen_samd.crossbar_samd_n_259\,
D(0) => \gen_samd.crossbar_samd_n_260\,
E(0) => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i\,
Q(57 downto 54) => m_axi_awqos(3 downto 0),
Q(53 downto 50) => m_axi_awcache(3 downto 0),
Q(49 downto 48) => m_axi_awburst(1 downto 0),
Q(47 downto 45) => m_axi_awprot(2 downto 0),
Q(44) => m_axi_awlock(0),
Q(43 downto 41) => m_axi_awsize(2 downto 0),
Q(40 downto 33) => m_axi_awlen(7 downto 0),
Q(32 downto 1) => m_axi_awaddr(31 downto 0),
Q(0) => \^m_axi_awid\(1),
aclk => aclk,
areset_d1 => \gen_slave_slots[2].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1\,
aresetn => aresetn,
\m_axi_arqos[3]\(57 downto 54) => m_axi_arqos(3 downto 0),
\m_axi_arqos[3]\(53 downto 50) => m_axi_arcache(3 downto 0),
\m_axi_arqos[3]\(49 downto 48) => m_axi_arburst(1 downto 0),
\m_axi_arqos[3]\(47 downto 45) => m_axi_arprot(2 downto 0),
\m_axi_arqos[3]\(44) => m_axi_arlock(0),
\m_axi_arqos[3]\(43 downto 41) => m_axi_arsize(2 downto 0),
\m_axi_arqos[3]\(40 downto 33) => m_axi_arlen(7 downto 0),
\m_axi_arqos[3]\(32 downto 1) => m_axi_araddr(31 downto 0),
\m_axi_arqos[3]\(0) => \^m_axi_arid\(0),
m_axi_arready(0) => m_axi_arready(0),
m_axi_arvalid(0) => m_axi_arvalid(0),
m_axi_awready(0) => m_axi_awready(0),
m_axi_awvalid(0) => m_axi_awvalid(0),
\m_axi_bid[1]\(3 downto 2) => m_axi_bid(1 downto 0),
\m_axi_bid[1]\(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
m_axi_rid(1 downto 0) => m_axi_rid(1 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[0]\ => m_axi_rready(0),
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
m_axi_wdata(63 downto 0) => m_axi_wdata(63 downto 0),
m_axi_wlast(0) => m_axi_wlast(0),
m_axi_wready(0) => m_axi_wready(0),
m_axi_wstrb(7 downto 0) => m_axi_wstrb(7 downto 0),
m_axi_wvalid(0) => m_axi_wvalid(0),
m_valid_i_reg => \gen_samd.crossbar_samd_n_4\,
m_valid_i_reg_0 => \gen_samd.crossbar_samd_n_5\,
\out\(2) => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[3]\,
\out\(1) => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_0_in6_in\,
\out\(0) => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_7_in\,
s_axi_araddr(63 downto 0) => s_axi_araddr(63 downto 0),
s_axi_arburst(3 downto 0) => s_axi_arburst(3 downto 0),
s_axi_arcache(7 downto 0) => s_axi_arcache(7 downto 0),
s_axi_arlen(15 downto 0) => s_axi_arlen(15 downto 0),
s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0),
s_axi_arprot(5 downto 0) => s_axi_arprot(5 downto 0),
s_axi_arqos(7 downto 0) => s_axi_arqos(7 downto 0),
\s_axi_arready[0]\ => \^s_axi_arready\(0),
\s_axi_arready[1]\ => \^s_axi_arready\(1),
s_axi_arsize(5 downto 0) => s_axi_arsize(5 downto 0),
s_axi_arvalid(1 downto 0) => s_axi_arvalid(1 downto 0),
s_axi_awaddr(63 downto 32) => s_axi_awaddr(95 downto 64),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(3 downto 2) => s_axi_awburst(5 downto 4),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(7 downto 4) => s_axi_awcache(11 downto 8),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awlen(15 downto 8) => s_axi_awlen(23 downto 16),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(1) => s_axi_awlock(2),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(5 downto 3) => s_axi_awprot(8 downto 6),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(7 downto 4) => s_axi_awqos(11 downto 8),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
\s_axi_awready[0]\ => \^s_axi_awready\(0),
\s_axi_awready[2]\ => \^s_axi_awready\(2),
s_axi_awsize(5 downto 3) => s_axi_awsize(8 downto 6),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awvalid(1) => s_axi_awvalid(2),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bready(1) => s_axi_bready(2),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(3 downto 2) => \^s_axi_bresp\(5 downto 4),
s_axi_bresp(1 downto 0) => \^s_axi_bresp\(1 downto 0),
s_axi_bvalid(1) => \^s_axi_bvalid\(2),
s_axi_bvalid(0) => \^s_axi_bvalid\(0),
s_axi_rdata(127 downto 0) => \^s_axi_rdata\(127 downto 0),
s_axi_rlast(1 downto 0) => \^s_axi_rlast\(1 downto 0),
s_axi_rready(1 downto 0) => s_axi_rready(1 downto 0),
s_axi_rresp(3 downto 0) => \^s_axi_rresp\(3 downto 0),
s_axi_rvalid(1 downto 0) => \^s_axi_rvalid\(1 downto 0),
s_axi_wdata(127 downto 64) => s_axi_wdata(191 downto 128),
s_axi_wdata(63 downto 0) => s_axi_wdata(63 downto 0),
s_axi_wlast(1) => s_axi_wlast(2),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(1) => \^s_axi_wready\(2),
s_axi_wready(0) => \^s_axi_wready\(0),
s_axi_wstrb(15 downto 8) => s_axi_wstrb(23 downto 16),
s_axi_wstrb(7 downto 0) => s_axi_wstrb(7 downto 0),
s_axi_wvalid(1) => s_axi_wvalid(2),
s_axi_wvalid(0) => s_axi_wvalid(0),
sa_wm_awvalid(0) => sa_wm_awvalid(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 95 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 191 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 95 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 191 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_xbar_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_xbar_0 : entity is "system_xbar_0,axi_crossbar_v2_1_12_axi_crossbar,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_xbar_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of system_xbar_0 : entity is "axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4";
end system_xbar_0;
architecture STRUCTURE of system_xbar_0 is
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 2;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of inst : label is 1;
attribute C_DEBUG : integer;
attribute C_DEBUG of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_M_AXI_ADDR_WIDTH : integer;
attribute C_M_AXI_ADDR_WIDTH of inst : label is 29;
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : integer;
attribute C_M_AXI_READ_CONNECTIVITY of inst : label is 3;
attribute C_M_AXI_READ_ISSUING : integer;
attribute C_M_AXI_READ_ISSUING of inst : label is 8;
attribute C_M_AXI_SECURE : integer;
attribute C_M_AXI_SECURE of inst : label is 0;
attribute C_M_AXI_WRITE_CONNECTIVITY : integer;
attribute C_M_AXI_WRITE_CONNECTIVITY of inst : label is 5;
attribute C_M_AXI_WRITE_ISSUING : integer;
attribute C_M_AXI_WRITE_ISSUING of inst : label is 8;
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of inst : label is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of inst : label is 1;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of inst : label is 3;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of inst : label is 0;
attribute C_S_AXI_ARB_PRIORITY : string;
attribute C_S_AXI_ARB_PRIORITY of inst : label is "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_S_AXI_BASE_ID : string;
attribute C_S_AXI_BASE_ID of inst : label is "96'b000000000000000000000000000000100000000000000000000000000000000100000000000000000000000000000000";
attribute C_S_AXI_READ_ACCEPTANCE : string;
attribute C_S_AXI_READ_ACCEPTANCE of inst : label is "96'b000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010";
attribute C_S_AXI_SINGLE_THREAD : string;
attribute C_S_AXI_SINGLE_THREAD of inst : label is "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_S_AXI_THREAD_ID_WIDTH : string;
attribute C_S_AXI_THREAD_ID_WIDTH of inst : label is "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_S_AXI_WRITE_ACCEPTANCE : string;
attribute C_S_AXI_WRITE_ACCEPTANCE of inst : label is "96'b000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010";
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of inst : label is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of inst : label is "zynq";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of inst : label is 8;
attribute P_LOCK : integer;
attribute P_LOCK of inst : label is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of inst : label is "32'b00000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of inst : label is "1'b1";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of inst : label is "1'b1";
attribute P_ONES : string;
attribute P_ONES of inst : label is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of inst : label is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of inst : label is "192'b000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of inst : label is "192'b000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of inst : label is "3'b011";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of inst : label is "3'b101";
begin
inst: entity work.system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_arid(1 downto 0) => m_axi_arid(1 downto 0),
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arlock(0) => m_axi_arlock(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready(0) => m_axi_arready(0),
m_axi_arregion(3 downto 0) => m_axi_arregion(3 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid(0) => m_axi_arvalid(0),
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
m_axi_awid(1 downto 0) => m_axi_awid(1 downto 0),
m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
m_axi_awlock(0) => m_axi_awlock(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
m_axi_awready(0) => m_axi_awready(0),
m_axi_awregion(3 downto 0) => m_axi_awregion(3 downto 0),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid(0) => m_axi_awvalid(0),
m_axi_bid(1 downto 0) => m_axi_bid(1 downto 0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid(0) => m_axi_bvalid(0),
m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
m_axi_rid(1 downto 0) => m_axi_rid(1 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
m_axi_rready(0) => m_axi_rready(0),
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid(0) => m_axi_rvalid(0),
m_axi_wdata(63 downto 0) => m_axi_wdata(63 downto 0),
m_axi_wid(1 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(1 downto 0),
m_axi_wlast(0) => m_axi_wlast(0),
m_axi_wready(0) => m_axi_wready(0),
m_axi_wstrb(7 downto 0) => m_axi_wstrb(7 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid(0) => m_axi_wvalid(0),
s_axi_araddr(95 downto 0) => s_axi_araddr(95 downto 0),
s_axi_arburst(5 downto 0) => s_axi_arburst(5 downto 0),
s_axi_arcache(11 downto 0) => s_axi_arcache(11 downto 0),
s_axi_arid(5 downto 0) => s_axi_arid(5 downto 0),
s_axi_arlen(23 downto 0) => s_axi_arlen(23 downto 0),
s_axi_arlock(2 downto 0) => s_axi_arlock(2 downto 0),
s_axi_arprot(8 downto 0) => s_axi_arprot(8 downto 0),
s_axi_arqos(11 downto 0) => s_axi_arqos(11 downto 0),
s_axi_arready(2 downto 0) => s_axi_arready(2 downto 0),
s_axi_arsize(8 downto 0) => s_axi_arsize(8 downto 0),
s_axi_aruser(2 downto 0) => B"000",
s_axi_arvalid(2 downto 0) => s_axi_arvalid(2 downto 0),
s_axi_awaddr(95 downto 0) => s_axi_awaddr(95 downto 0),
s_axi_awburst(5 downto 0) => s_axi_awburst(5 downto 0),
s_axi_awcache(11 downto 0) => s_axi_awcache(11 downto 0),
s_axi_awid(5 downto 0) => s_axi_awid(5 downto 0),
s_axi_awlen(23 downto 0) => s_axi_awlen(23 downto 0),
s_axi_awlock(2 downto 0) => s_axi_awlock(2 downto 0),
s_axi_awprot(8 downto 0) => s_axi_awprot(8 downto 0),
s_axi_awqos(11 downto 0) => s_axi_awqos(11 downto 0),
s_axi_awready(2 downto 0) => s_axi_awready(2 downto 0),
s_axi_awsize(8 downto 0) => s_axi_awsize(8 downto 0),
s_axi_awuser(2 downto 0) => B"000",
s_axi_awvalid(2 downto 0) => s_axi_awvalid(2 downto 0),
s_axi_bid(5 downto 0) => s_axi_bid(5 downto 0),
s_axi_bready(2 downto 0) => s_axi_bready(2 downto 0),
s_axi_bresp(5 downto 0) => s_axi_bresp(5 downto 0),
s_axi_buser(2 downto 0) => NLW_inst_s_axi_buser_UNCONNECTED(2 downto 0),
s_axi_bvalid(2 downto 0) => s_axi_bvalid(2 downto 0),
s_axi_rdata(191 downto 0) => s_axi_rdata(191 downto 0),
s_axi_rid(5 downto 0) => s_axi_rid(5 downto 0),
s_axi_rlast(2 downto 0) => s_axi_rlast(2 downto 0),
s_axi_rready(2 downto 0) => s_axi_rready(2 downto 0),
s_axi_rresp(5 downto 0) => s_axi_rresp(5 downto 0),
s_axi_ruser(2 downto 0) => NLW_inst_s_axi_ruser_UNCONNECTED(2 downto 0),
s_axi_rvalid(2 downto 0) => s_axi_rvalid(2 downto 0),
s_axi_wdata(191 downto 0) => s_axi_wdata(191 downto 0),
s_axi_wid(5 downto 0) => B"000000",
s_axi_wlast(2 downto 0) => s_axi_wlast(2 downto 0),
s_axi_wready(2 downto 0) => s_axi_wready(2 downto 0),
s_axi_wstrb(23 downto 0) => s_axi_wstrb(23 downto 0),
s_axi_wuser(2 downto 0) => B"000",
s_axi_wvalid(2 downto 0) => s_axi_wvalid(2 downto 0)
);
end STRUCTURE;
| mit | 7c56dac1fe2b660d3c6e31861b0fa344 | 0.55534 | 2.647867 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/uint_to_ieee754_fp/uint_to_ieee754_fp.srcs/sources_1/new/uint_to_ieee754_fp.vhd | 3 | 1,596 | ----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: uint_to_ieee754_fp - Structural
-- Description: Converts an unsigned integer into IEEE-754 floating point notation
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity uint_to_ieee754_fp is
generic(
WIDTH : integer := 10
);
port(
x : in std_logic_vector(WIDTH - 1 downto 0);
y : out std_logic_vector(31 downto 0)
);
end uint_to_ieee754_fp;
architecture Structural of uint_to_ieee754_fp is
signal exponent : std_logic_vector(7 downto 0);
signal mantissa : std_logic_vector(22 downto 0) := "00000000000000000000000";
begin
y(31) <= '0'; -- sign is always positive
y(30 downto 23) <= exponent;
y(22 downto 0) <= mantissa;
process(x)
variable x_exp : integer := 0;
begin
x_exp := -1;
-- find place of most significant '1'
for i in 0 to WIDTH - 1 loop
if x(i) = '1' then
x_exp := i;
end if;
end loop;
if x_exp >= 0 then
exponent <= std_logic_vector(to_signed(x_exp + 127, 8));
-- bit shift x into mantissa
mantissa(22 downto 22 - WIDTH + 1) <= std_logic_vector(unsigned(x) sll WIDTH - x_exp);
else
exponent <= x"00";
mantissa <= "00000000000000000000000";
end if;
end process;
end Structural;
| mit | 80c6a408992da28004898ed8394af235 | 0.52381 | 4.061069 | false | false | false | false |
sbourdeauducq/dspunit | sim/bench_dspalu.vhd | 2 | 7,246 | -- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspalu_pac.all;
-------------------------------------------------------------------------------
entity bench_dspalu is
end bench_dspalu;
--=----------------------------------------------------------------------------
architecture archi_bench_dspalu of bench_dspalu is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
constant sig_width : integer := 16;
constant acc_width : integer := 40;
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
component clock_gen
generic (
tpw : time;
tps : time
);
port (
clk : out std_logic;
reset : out std_logic
);
end component;
component dspalu_acc
generic (
sig_width : integer ;
acc_width : integer
);
port (
a1 : in std_logic_vector((sig_width - 1) downto 0);
b1 : in std_logic_vector((sig_width - 1) downto 0);
a2 : in std_logic_vector((sig_width - 1) downto 0);
b2 : in std_logic_vector((sig_width - 1) downto 0);
clk : in std_logic;
clr_acc : in std_logic;
acc_mode1 : in std_logic_vector((acc_mode_width - 1) downto 0);
acc_mode2 : in std_logic_vector((acc_mode_width - 1) downto 0);
alu_select : in std_logic_vector((alu_select_width - 1) downto 0);
cmp_mode : in std_logic_vector((cmp_mode_width - 1) downto 0);
cmp_pol : in std_logic;
cmp_store : in std_logic;
chain_acc : in std_logic;
result1 : out std_logic_vector((sig_width - 1) downto 0);
result_acc1 : out std_logic_vector((acc_width - 1) downto 0);
result2 : out std_logic_vector((sig_width - 1) downto 0);
result_acc2 : out std_logic_vector((acc_width - 1) downto 0);
result_sum : out std_logic_vector((2*sig_width - 1) downto 0);
cmp_reg : out std_logic_vector((acc_width - 1) downto 0);
cmp_greater : out std_logic;
cmp_out : out std_logic
);
end component;
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_reset : std_logic;
signal s_a1 : std_logic_vector((sig_width - 1) downto 0);
signal s_b1 : std_logic_vector((sig_width - 1) downto 0);
signal s_a2 : std_logic_vector((sig_width - 1) downto 0);
signal s_b2 : std_logic_vector((sig_width - 1) downto 0);
signal s_clk : std_logic;
signal s_clr_acc : std_logic;
signal s_acc_mode1 : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
signal s_acc_mode2 : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
signal s_alu_select : std_logic_vector((alu_select_width - 1) downto 0); -- t_alu_select;
signal s_result1 : std_logic_vector((sig_width - 1) downto 0);
signal s_result_acc1 : std_logic_vector((acc_width - 1) downto 0);
signal s_result2 : std_logic_vector((sig_width - 1) downto 0);
signal s_result_acc2 : std_logic_vector((acc_width - 1) downto 0);
signal s_cmp_mode : std_logic_vector((cmp_mode_width - 1) downto 0);
signal s_cmp_pol : std_logic;
signal s_cmp_store : std_logic;
signal s_chain_acc : std_logic;
signal s_cmp_reg : std_logic_vector((acc_width - 1) downto 0);
signal s_cmp_greater : std_logic;
signal s_cmp_out : std_logic;
signal s_result_sum : std_logic_vector((2*sig_width - 1) downto 0);
begin -- archs_bench_dspalu
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
clock_gen_1 : clock_gen
generic map (
tpw => 5 ns,
tps => 0 ns)
port map (
clk => s_clk,
reset => s_reset);
dspalu_acc_1 : dspalu_acc
generic map (
sig_width => sig_width,
acc_width => acc_width)
port map (
a1 => s_a1,
b1 => s_b1,
a2 => s_a2,
b2 => s_b2,
clk => s_clk,
clr_acc => s_clr_acc,
acc_mode1 => s_acc_mode1,
acc_mode2 => s_acc_mode2,
alu_select => s_alu_select,
cmp_mode => s_cmp_mode,
cmp_pol => s_cmp_pol,
cmp_store => s_cmp_store,
chain_acc => s_chain_acc,
result1 => s_result1,
result_acc1 => s_result_acc1,
result2 => s_result2,
result_acc2 => s_result_acc2,
result_sum => s_result_sum,
cmp_reg => s_cmp_reg,
cmp_greater => s_cmp_greater,
cmp_out => s_cmp_out);
--=---------------------------------------------------------------------------
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
s_a1 <= "0010000100000000", "0000000000000010" after 501 ns;
s_b1 <= "1111111111111011", "0000000000000011" after 501 ns;
s_a2 <= "0000000000000100";
s_b2 <= "1111111111111110";
s_clr_acc <= not s_reset;
s_acc_mode1 <= acc_add, acc_store after 201 ns, acc_sub after 301 ns, acc_sumstore after 401 ns,
acc_store after 501 ns, acc_sub after 701 ns, acc_add after 901 ns;
s_acc_mode2 <= acc_add, acc_store after 501 ns, acc_sub after 701 ns, acc_add after 901 ns;
s_alu_select <= alu_mul, alu_cmul after 501 ns;
end archi_bench_dspalu;
--------------------------------------------------------------------------------
-- Simulation parameters
-->SIMSTOPTIME=1000ns
-->SIMSAVFILE=dspalu.sav
-------------------------------------------------------------------------------
| gpl-3.0 | 6cabca23909540da250dbf675a068598 | 0.478885 | 3.783812 | false | false | false | false |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo.vhd | 1 | 8,096 | -- niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:30
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 18;
FIFO_DEPTH : integer := 8;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 3;
USE_MEMORY_BLOCKS : integer := 1;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- clk_reset.reset
in_data : in std_logic_vector(17 downto 0) := (others => '0'); -- in.data
in_valid : in std_logic := '0'; -- .valid
in_ready : out std_logic; -- .ready
out_data : out std_logic_vector(17 downto 0); -- out.data
out_valid : out std_logic; -- .valid
out_ready : in std_logic := '0'; -- .ready
almost_empty_data : out std_logic;
almost_full_data : out std_logic;
csr_address : in std_logic_vector(1 downto 0) := (others => '0');
csr_read : in std_logic := '0';
csr_readdata : out std_logic_vector(31 downto 0);
csr_write : in std_logic := '0';
csr_writedata : in std_logic_vector(31 downto 0) := (others => '0');
in_channel : in std_logic := '0';
in_empty : in std_logic := '0';
in_endofpacket : in std_logic := '0';
in_error : in std_logic := '0';
in_startofpacket : in std_logic := '0';
out_channel : out std_logic;
out_empty : out std_logic;
out_endofpacket : out std_logic;
out_error : out std_logic;
out_startofpacket : out std_logic
);
end entity niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo;
architecture rtl of niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo is
component altera_avalon_sc_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 3;
USE_MEMORY_BLOCKS : integer := 1;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(17 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
out_data : out std_logic_vector(17 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
csr_read : in std_logic := 'X'; -- read
csr_write : in std_logic := 'X'; -- write
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
almost_full_data : out std_logic; -- data
almost_empty_data : out std_logic; -- data
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic; -- endofpacket
in_empty : in std_logic := 'X'; -- empty
out_empty : out std_logic; -- empty
in_error : in std_logic := 'X'; -- error
out_error : out std_logic; -- error
in_channel : in std_logic := 'X'; -- channel
out_channel : out std_logic -- channel
);
end component altera_avalon_sc_fifo;
begin
sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo : component altera_avalon_sc_fifo
generic map (
SYMBOLS_PER_BEAT => SYMBOLS_PER_BEAT,
BITS_PER_SYMBOL => BITS_PER_SYMBOL,
FIFO_DEPTH => FIFO_DEPTH,
CHANNEL_WIDTH => CHANNEL_WIDTH,
ERROR_WIDTH => ERROR_WIDTH,
USE_PACKETS => USE_PACKETS,
USE_FILL_LEVEL => USE_FILL_LEVEL,
EMPTY_LATENCY => EMPTY_LATENCY,
USE_MEMORY_BLOCKS => USE_MEMORY_BLOCKS,
USE_STORE_FORWARD => USE_STORE_FORWARD,
USE_ALMOST_FULL_IF => USE_ALMOST_FULL_IF,
USE_ALMOST_EMPTY_IF => USE_ALMOST_EMPTY_IF
)
port map (
clk => clk, -- clk.clk
reset => reset, -- clk_reset.reset
in_data => in_data, -- in.data
in_valid => in_valid, -- .valid
in_ready => in_ready, -- .ready
out_data => out_data, -- out.data
out_valid => out_valid, -- .valid
out_ready => out_ready, -- .ready
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_startofpacket => '0', -- (terminated)
in_endofpacket => '0', -- (terminated)
out_startofpacket => open, -- (terminated)
out_endofpacket => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
end architecture rtl; -- of niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo
| apache-2.0 | af0ae171b37ef7a6cc4c67cd5cc90c0f | 0.428854 | 3.892308 | false | false | false | false |
loa-org/loa-hdl | modules/imotor/hdl/imotor_transceiver.vhd | 2 | 5,864 | -------------------------------------------------------------------------------
-- Title : iMotor Transceiver
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.imotor_module_pkg.all;
-------------------------------------------------------------------------------
entity imotor_transceiver is
generic (
DATA_WORDS_SEND : positive;
DATA_WORDS_READ : positive;
DATA_WIDTH : positive := 16
);
port (
-- parallel data in and out
data_in_p : in imotor_input_type(DATA_WORDS_SEND - 1 downto 0);
data_out_p : out imotor_output_type(DATA_WORDS_READ - 1 downto 0);
-- UART RX/TX
tx_out_p : out std_logic;
rx_in_p : in std_logic;
-- Clocks for UART and sender
timer_in_p : in imotor_timer_type;
clk : in std_logic
);
end imotor_transceiver;
-------------------------------------------------------------------------------
architecture behavioural of imotor_transceiver is
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
constant DATA_BITS : positive := 8;
constant START_BITS : positive := 1;
constant STOP_BITS : positive := 1;
constant PARITY : parity_type := Odd;
signal uart_start_s : std_logic;
signal uart_start_ns : std_logic;
signal uart_busy_s : std_logic;
signal uart_ready_s : std_logic;
signal data_tx_s : std_logic_vector(7 downto 0);
signal data_rx_s : std_logic_vector(7 downto 0); -- Received data from uart
-- to receiver
signal parity_error_s : std_logic; -- Info about parity error from uart to receiver
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-- None here. If any: in package
begin -- architecture behavourial
----------------------------------------------------------------------------
-- Connections between ports and signals
----------------------------------------------------------------------------
uart_start_ns <= not uart_start_s;
----------------------------------------------------------------------------
-- Sequential part of finite state machine (FSM)
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Combinatorial part of FSM
----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
imotor_sender_1 : entity work.imotor_sender
generic map (
DATA_WORDS => DATA_WORDS_SEND,
DATA_WIDTH => DATA_WIDTH)
port map (
data_in_p => data_in_p,
data_out_p => data_tx_s,
start_out_p => uart_start_s,
busy_in_p => uart_busy_s,
start_in_p => timer_in_p.send,
clk => clk);
--imotor_uart_tx_1 : entity work.imotor_uart_tx
-- generic map (
-- START_BITS => START_BITS,
-- DATA_BITS => DATA_BITS,
-- STOP_BITS => STOP_BITS,
-- PARITY => PARITY)
-- port map (
-- data_in_p => data_tx_s,
-- start_in_p => uart_start_s,
-- busy_out_p => uart_busy_s,
-- txd_out_p => tx_out_p,
-- clock_tx_in_p => timer_in_p.tx,
-- clk => clk);
uart_tx_1 : entity work.uart_tx
port map (
txd_p => tx_out_p,
busy_p => uart_busy_s,
data_p => data_tx_s,
empty_p => uart_start_ns,
re_p => open,
clk_tx_en => timer_in_p.tx,
clk => clk);
uart_rx_1 : entity work.uart_rx
port map (
rxd_p => rx_in_p,
disable_p => uart_busy_s,
data_p => data_rx_s,
we_p => uart_ready_s,
error_p => parity_error_s,
full_p => '0', -- always get data
clk_rx_en => timer_in_p.rx,
clk => clk);
--imotor_uart_rx_1 : entity work.imotor_uart_rx
-- generic map (
-- START_BITS => START_BITS,
-- DATA_BITS => DATA_BITS,
-- STOP_BITS => STOP_BITS,
-- PARITY => PARITY)
-- port map (
-- data_out_p => data_rx_s,
-- rxd_in_p => rx_in_p,
-- deaf_in_p => uart_busy_s, -- make the receiver deaf when the
-- -- transmitter is active
-- ready_out_p => uart_ready_s,
-- parity_error_out_p => parity_error_s,
-- clock_rx_in_p => timer_in_p.rx,
-- clk => clk);
imotor_receiver_1 : entity work.imotor_receiver
generic map (
DATA_WORDS => DATA_WORDS_READ,
DATA_WIDTH => DATA_WIDTH)
port map (
data_out_p => data_out_p,
data_in_p => data_rx_s,
parity_error_in_p => parity_error_s,
ready_in_p => uart_ready_s,
clk => clk);
end behavioural;
| bsd-3-clause | 5c38b144e404f44dc90ef61a97b3e961 | 0.38148 | 4.445792 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_ov7670_controller_1_0/system_ov7670_controller_1_0_sim_netlist.vhdl | 1 | 70,017 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue May 30 22:27:55 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_ov7670_controller_1_0 -prefix
-- system_ov7670_controller_1_0_ system_ov7670_controller_1_0_sim_netlist.vhdl
-- Design : system_ov7670_controller_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_1_0_i2c_sender is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
sioc : out STD_LOGIC;
p_0_in : out STD_LOGIC;
\busy_sr_reg[1]_0\ : out STD_LOGIC;
siod : out STD_LOGIC;
\busy_sr_reg[31]_0\ : in STD_LOGIC;
clk : in STD_LOGIC;
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
DOADO : in STD_LOGIC_VECTOR ( 15 downto 0 );
\busy_sr_reg[31]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end system_ov7670_controller_1_0_i2c_sender;
architecture STRUCTURE of system_ov7670_controller_1_0_i2c_sender is
signal busy_sr0 : STD_LOGIC;
signal \busy_sr[0]_i_3_n_0\ : STD_LOGIC;
signal \busy_sr[0]_i_5_n_0\ : STD_LOGIC;
signal \busy_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[11]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[1]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[20]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[21]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[23]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[24]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[25]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[26]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[28]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[29]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[2]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \busy_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \^busy_sr_reg[1]_0\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[0]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \data_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \data_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \data_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[20]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[31]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \divider_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 6 );
signal \divider_reg__1\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^p_0_in\ : STD_LOGIC;
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_1_in_0 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sioc_i_1_n_0 : STD_LOGIC;
signal sioc_i_2_n_0 : STD_LOGIC;
signal sioc_i_3_n_0 : STD_LOGIC;
signal sioc_i_4_n_0 : STD_LOGIC;
signal sioc_i_5_n_0 : STD_LOGIC;
signal siod_INST_0_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \busy_sr[0]_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \busy_sr[0]_i_5\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \busy_sr[10]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[11]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[12]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[13]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[14]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[15]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[16]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[17]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[18]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[19]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \busy_sr[20]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[21]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[22]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[23]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[24]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[25]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[26]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \busy_sr[27]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[28]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[29]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[2]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[30]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \busy_sr[31]_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \busy_sr[3]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[4]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[5]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[6]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[7]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[8]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[9]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \data_sr[10]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[12]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[13]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[14]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_sr[15]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[16]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[17]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[18]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[19]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[31]_i_2\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \data_sr[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[4]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[5]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[6]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[7]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[8]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[9]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \divider[0]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[1]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \divider[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[6]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \divider[7]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of sioc_i_3 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of sioc_i_4 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of sioc_i_5 : label is "soft_lutpair3";
begin
\busy_sr_reg[1]_0\ <= \^busy_sr_reg[1]_0\;
p_0_in <= \^p_0_in\;
\busy_sr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
I2 => \divider_reg__0\(7),
I3 => \^p_0_in\,
I4 => \^busy_sr_reg[1]_0\,
I5 => p_1_in(0),
O => busy_sr0
);
\busy_sr[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \busy_sr[0]_i_3_n_0\
);
\busy_sr[0]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(3),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \busy_sr[0]_i_5_n_0\,
O => \^busy_sr_reg[1]_0\
);
\busy_sr[0]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \divider_reg__1\(5),
I1 => \divider_reg__1\(4),
I2 => \divider_reg__0\(7),
I3 => \divider_reg__0\(6),
O => \busy_sr[0]_i_5_n_0\
);
\busy_sr[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
O => \busy_sr[10]_i_1_n_0\
);
\busy_sr[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[10]\,
I1 => \^p_0_in\,
O => \busy_sr[11]_i_1_n_0\
);
\busy_sr[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
O => \busy_sr[12]_i_1_n_0\
);
\busy_sr[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
O => \busy_sr[13]_i_1_n_0\
);
\busy_sr[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
O => \busy_sr[14]_i_1_n_0\
);
\busy_sr[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
O => \busy_sr[15]_i_1_n_0\
);
\busy_sr[16]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
O => \busy_sr[16]_i_1_n_0\
);
\busy_sr[17]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
O => \busy_sr[17]_i_1_n_0\
);
\busy_sr[18]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
O => \busy_sr[18]_i_1_n_0\
);
\busy_sr[19]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
O => \busy_sr[19]_i_1_n_0\
);
\busy_sr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \^p_0_in\,
O => \busy_sr[1]_i_1_n_0\
);
\busy_sr[20]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(0),
I1 => \^p_0_in\,
O => \busy_sr[20]_i_1_n_0\
);
\busy_sr[21]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(1),
I1 => \^p_0_in\,
O => \busy_sr[21]_i_1_n_0\
);
\busy_sr[22]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[21]\,
I1 => \^p_0_in\,
O => \busy_sr[22]_i_1_n_0\
);
\busy_sr[23]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[22]\,
I1 => \^p_0_in\,
O => \busy_sr[23]_i_1_n_0\
);
\busy_sr[24]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[23]\,
I1 => \^p_0_in\,
O => \busy_sr[24]_i_1_n_0\
);
\busy_sr[25]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[24]\,
I1 => \^p_0_in\,
O => \busy_sr[25]_i_1_n_0\
);
\busy_sr[26]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[25]\,
I1 => \^p_0_in\,
O => \busy_sr[26]_i_1_n_0\
);
\busy_sr[27]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[26]\,
I1 => \^p_0_in\,
O => \busy_sr[27]_i_1_n_0\
);
\busy_sr[28]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[27]\,
I1 => \^p_0_in\,
O => \busy_sr[28]_i_1_n_0\
);
\busy_sr[29]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \^p_0_in\,
O => \busy_sr[29]_i_1_n_0\
);
\busy_sr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[1]\,
I1 => \^p_0_in\,
O => \busy_sr[2]_i_1_n_0\
);
\busy_sr[30]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \^p_0_in\,
O => \busy_sr[30]_i_1_n_0\
);
\busy_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"22222222A2222222"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
I3 => \divider_reg__0\(7),
I4 => \divider_reg__0\(6),
I5 => \busy_sr[0]_i_3_n_0\,
O => \busy_sr[31]_i_1_n_0\
);
\busy_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^p_0_in\,
I1 => \busy_sr_reg_n_0_[30]\,
O => \busy_sr[31]_i_2_n_0\
);
\busy_sr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
O => \busy_sr[3]_i_1_n_0\
);
\busy_sr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
O => \busy_sr[4]_i_1_n_0\
);
\busy_sr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
O => \busy_sr[5]_i_1_n_0\
);
\busy_sr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
O => \busy_sr[6]_i_1_n_0\
);
\busy_sr[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
O => \busy_sr[7]_i_1_n_0\
);
\busy_sr[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
O => \busy_sr[8]_i_1_n_0\
);
\busy_sr[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
O => \busy_sr[9]_i_1_n_0\
);
\busy_sr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => p_1_in(0),
Q => \busy_sr_reg_n_0_[0]\,
R => '0'
);
\busy_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[10]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[10]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[11]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[11]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[11]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[12]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[12]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[12]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[13]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[13]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[13]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[14]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[14]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[14]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[15]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[15]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[15]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[16]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[16]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[16]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[17]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[17]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[17]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[18]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[18]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[18]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[19]_i_1_n_0\,
Q => p_1_in_0(0),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[1]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[1]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[20]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[20]_i_1_n_0\,
Q => p_1_in_0(1),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[21]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[21]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[21]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[22]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[22]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[22]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[23]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[23]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[23]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[24]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[24]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[24]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[25]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[25]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[25]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[26]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[26]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[26]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[27]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[27]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[27]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[28]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[28]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[28]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[29]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[29]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[29]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[2]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[2]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[30]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[30]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[30]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[31]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[31]_i_2_n_0\,
Q => \^p_0_in\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[3]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[3]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[4]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[4]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[5]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[5]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[6]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[6]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[7]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[7]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[8]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[8]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[9]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[9]\,
S => \busy_sr[31]_i_1_n_0\
);
\data_sr[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
I2 => DOADO(7),
O => \data_sr[10]_i_1_n_0\
);
\data_sr[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
I2 => DOADO(8),
O => \data_sr[12]_i_1_n_0\
);
\data_sr[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
I2 => DOADO(9),
O => \data_sr[13]_i_1_n_0\
);
\data_sr[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
I2 => DOADO(10),
O => \data_sr[14]_i_1_n_0\
);
\data_sr[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
I2 => DOADO(11),
O => \data_sr[15]_i_1_n_0\
);
\data_sr[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
I2 => DOADO(12),
O => \data_sr[16]_i_1_n_0\
);
\data_sr[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
I2 => DOADO(13),
O => \data_sr[17]_i_1_n_0\
);
\data_sr[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
I2 => DOADO(14),
O => \data_sr[18]_i_1_n_0\
);
\data_sr[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
I2 => DOADO(15),
O => \data_sr[19]_i_1_n_0\
);
\data_sr[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[22]\,
I1 => \data_sr_reg_n_0_[21]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[22]_i_1_n_0\
);
\data_sr[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[27]\,
I1 => \data_sr_reg_n_0_[26]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[27]_i_1_n_0\
);
\data_sr[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
O => \data_sr[30]_i_1_n_0\
);
\data_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => \data_sr_reg_n_0_[30]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[31]_i_1_n_0\
);
\data_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \data_sr[31]_i_2_n_0\
);
\data_sr[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
I2 => DOADO(0),
O => \data_sr[3]_i_1_n_0\
);
\data_sr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
I2 => DOADO(1),
O => \data_sr[4]_i_1_n_0\
);
\data_sr[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
I2 => DOADO(2),
O => \data_sr[5]_i_1_n_0\
);
\data_sr[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
I2 => DOADO(3),
O => \data_sr[6]_i_1_n_0\
);
\data_sr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
I2 => DOADO(4),
O => \data_sr[7]_i_1_n_0\
);
\data_sr[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
I2 => DOADO(5),
O => \data_sr[8]_i_1_n_0\
);
\data_sr[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
I2 => DOADO(6),
O => \data_sr[9]_i_1_n_0\
);
\data_sr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[10]_i_1_n_0\,
Q => \data_sr_reg_n_0_[10]\,
R => '0'
);
\data_sr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[10]\,
Q => \data_sr_reg_n_0_[11]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[12]_i_1_n_0\,
Q => \data_sr_reg_n_0_[12]\,
R => '0'
);
\data_sr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[13]_i_1_n_0\,
Q => \data_sr_reg_n_0_[13]\,
R => '0'
);
\data_sr_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[14]_i_1_n_0\,
Q => \data_sr_reg_n_0_[14]\,
R => '0'
);
\data_sr_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[15]_i_1_n_0\,
Q => \data_sr_reg_n_0_[15]\,
R => '0'
);
\data_sr_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[16]_i_1_n_0\,
Q => \data_sr_reg_n_0_[16]\,
R => '0'
);
\data_sr_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[17]_i_1_n_0\,
Q => \data_sr_reg_n_0_[17]\,
R => '0'
);
\data_sr_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[18]_i_1_n_0\,
Q => \data_sr_reg_n_0_[18]\,
R => '0'
);
\data_sr_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[19]_i_1_n_0\,
Q => \data_sr_reg_n_0_[19]\,
R => '0'
);
\data_sr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \^p_0_in\,
Q => \data_sr_reg_n_0_[1]\,
R => '0'
);
\data_sr_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[19]\,
Q => \data_sr_reg_n_0_[20]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[20]\,
Q => \data_sr_reg_n_0_[21]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[22]_i_1_n_0\,
Q => \data_sr_reg_n_0_[22]\,
R => '0'
);
\data_sr_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[22]\,
Q => \data_sr_reg_n_0_[23]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[23]\,
Q => \data_sr_reg_n_0_[24]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[24]\,
Q => \data_sr_reg_n_0_[25]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[25]\,
Q => \data_sr_reg_n_0_[26]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[27]_i_1_n_0\,
Q => \data_sr_reg_n_0_[27]\,
R => '0'
);
\data_sr_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[27]\,
Q => \data_sr_reg_n_0_[28]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[28]\,
Q => \data_sr_reg_n_0_[29]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[1]\,
Q => \data_sr_reg_n_0_[2]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[29]\,
Q => \data_sr_reg_n_0_[30]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[31]_i_1_n_0\,
Q => \data_sr_reg_n_0_[31]\,
R => '0'
);
\data_sr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[3]_i_1_n_0\,
Q => \data_sr_reg_n_0_[3]\,
R => '0'
);
\data_sr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[4]_i_1_n_0\,
Q => \data_sr_reg_n_0_[4]\,
R => '0'
);
\data_sr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[5]_i_1_n_0\,
Q => \data_sr_reg_n_0_[5]\,
R => '0'
);
\data_sr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[6]_i_1_n_0\,
Q => \data_sr_reg_n_0_[6]\,
R => '0'
);
\data_sr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[7]_i_1_n_0\,
Q => \data_sr_reg_n_0_[7]\,
R => '0'
);
\data_sr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[8]_i_1_n_0\,
Q => \data_sr_reg_n_0_[8]\,
R => '0'
);
\data_sr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[9]_i_1_n_0\,
Q => \data_sr_reg_n_0_[9]\,
R => '0'
);
\divider[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \divider_reg__1\(0),
O => \p_0_in__0\(0)
);
\divider[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__1\(0),
I1 => \divider_reg__1\(1),
O => \p_0_in__0\(1)
);
\divider[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \divider_reg__1\(1),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(2),
O => \p_0_in__0\(2)
);
\divider[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(1),
I3 => \divider_reg__1\(3),
O => \p_0_in__0\(3)
);
\divider[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \divider_reg__1\(3),
I1 => \divider_reg__1\(1),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(2),
I4 => \divider_reg__1\(4),
O => \p_0_in__0\(4)
);
\divider[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \p_0_in__0\(5)
);
\divider[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \p_0_in__0\(6)
);
\divider[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \busy_sr[0]_i_3_n_0\,
I2 => \divider_reg__0\(7),
O => \p_0_in__0\(7)
);
\divider_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(0),
Q => \divider_reg__1\(0),
R => '0'
);
\divider_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(1),
Q => \divider_reg__1\(1),
R => '0'
);
\divider_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(2),
Q => \divider_reg__1\(2),
R => '0'
);
\divider_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(3),
Q => \divider_reg__1\(3),
R => '0'
);
\divider_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(4),
Q => \divider_reg__1\(4),
R => '0'
);
\divider_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(5),
Q => \divider_reg__1\(5),
R => '0'
);
\divider_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(6),
Q => \divider_reg__0\(6),
R => '0'
);
\divider_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(7),
Q => \divider_reg__0\(7),
R => '0'
);
sioc_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFCFFF8FFFFFFFF"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => sioc_i_2_n_0,
I2 => sioc_i_3_n_0,
I3 => \busy_sr_reg_n_0_[1]\,
I4 => sioc_i_4_n_0,
I5 => \^p_0_in\,
O => sioc_i_1_n_0
);
sioc_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \divider_reg__0\(7),
O => sioc_i_2_n_0
);
sioc_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"A222"
)
port map (
I0 => sioc_i_5_n_0,
I1 => \busy_sr_reg_n_0_[30]\,
I2 => \divider_reg__0\(6),
I3 => \^p_0_in\,
O => sioc_i_3_n_0
);
sioc_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \busy_sr_reg_n_0_[2]\,
I2 => \^p_0_in\,
I3 => \busy_sr_reg_n_0_[30]\,
O => sioc_i_4_n_0
);
sioc_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \busy_sr_reg_n_0_[1]\,
I2 => \busy_sr_reg_n_0_[29]\,
I3 => \busy_sr_reg_n_0_[2]\,
O => sioc_i_5_n_0
);
sioc_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => sioc_i_1_n_0,
Q => sioc,
R => '0'
);
siod_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => siod_INST_0_i_1_n_0,
O => siod
);
siod_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"B0BBB0BB0000B0BB"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \busy_sr_reg_n_0_[29]\,
I2 => p_1_in_0(0),
I3 => p_1_in_0(1),
I4 => \busy_sr_reg_n_0_[11]\,
I5 => \busy_sr_reg_n_0_[10]\,
O => siod_INST_0_i_1_n_0
);
taken_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \busy_sr_reg[31]_0\,
Q => E(0),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_1_0_ov7670_registers is
port (
DOADO : out STD_LOGIC_VECTOR ( 15 downto 0 );
\divider_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
config_finished : out STD_LOGIC;
taken_reg : out STD_LOGIC;
p_1_in : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\divider_reg[2]\ : in STD_LOGIC;
p_0_in : in STD_LOGIC;
resend : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end system_ov7670_controller_1_0_ov7670_registers;
architecture STRUCTURE of system_ov7670_controller_1_0_ov7670_registers is
signal \^doado\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal address : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_rep[0]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[1]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[2]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[3]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[4]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[5]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[6]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_2_n_0\ : STD_LOGIC;
signal config_finished_INST_0_i_1_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_2_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_3_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_4_n_0 : STD_LOGIC;
signal NLW_sreg_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_sreg_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_sreg_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \address_reg[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg[7]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[7]\ : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \address_rep[1]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[2]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[3]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[4]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[6]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \address_rep[7]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \busy_sr[0]_i_2\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of config_finished_INST_0 : label is "soft_lutpair30";
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of sreg_reg : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of sreg_reg : label is "p0_d16";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of sreg_reg : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of sreg_reg : label is 4096;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of sreg_reg : label is "U0/Inst_ov7670_registers/sreg";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of sreg_reg : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of sreg_reg : label is 1023;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of sreg_reg : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of sreg_reg : label is 15;
begin
DOADO(15 downto 0) <= \^doado\(15 downto 0);
\address_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => \address_reg__0\(0),
R => resend
);
\address_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => \address_reg__0\(1),
R => resend
);
\address_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => \address_reg__0\(2),
R => resend
);
\address_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => \address_reg__0\(3),
R => resend
);
\address_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => \address_reg__0\(4),
R => resend
);
\address_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => \address_reg__0\(5),
R => resend
);
\address_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => \address_reg__0\(6),
R => resend
);
\address_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => \address_reg__0\(7),
R => resend
);
\address_reg_rep[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => address(0),
R => resend
);
\address_reg_rep[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => address(1),
R => resend
);
\address_reg_rep[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => address(2),
R => resend
);
\address_reg_rep[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => address(3),
R => resend
);
\address_reg_rep[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => address(4),
R => resend
);
\address_reg_rep[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => address(5),
R => resend
);
\address_reg_rep[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => address(6),
R => resend
);
\address_reg_rep[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => address(7),
R => resend
);
\address_rep[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \address_reg__0\(0),
O => \address_rep[0]_i_1_n_0\
);
\address_rep[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \address_reg__0\(0),
I1 => \address_reg__0\(1),
O => \address_rep[1]_i_1_n_0\
);
\address_rep[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \address_reg__0\(1),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(2),
O => \address_rep[2]_i_1_n_0\
);
\address_rep[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \address_reg__0\(2),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(1),
I3 => \address_reg__0\(3),
O => \address_rep[3]_i_1_n_0\
);
\address_rep[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \address_reg__0\(3),
I1 => \address_reg__0\(1),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(2),
I4 => \address_reg__0\(4),
O => \address_rep[4]_i_1_n_0\
);
\address_rep[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[5]_i_1_n_0\
);
\address_rep[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \address_rep[7]_i_2_n_0\,
I1 => \address_reg__0\(6),
O => \address_rep[6]_i_1_n_0\
);
\address_rep[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \address_reg__0\(6),
I1 => \address_rep[7]_i_2_n_0\,
I2 => \address_reg__0\(7),
O => \address_rep[7]_i_1_n_0\
);
\address_rep[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[7]_i_2_n_0\
);
\busy_sr[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FFFE"
)
port map (
I0 => config_finished_INST_0_i_4_n_0,
I1 => config_finished_INST_0_i_3_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_1_n_0,
I4 => p_0_in,
O => p_1_in(0)
);
config_finished_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
O => config_finished
);
config_finished_INST_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(5),
I1 => \^doado\(4),
I2 => \^doado\(7),
I3 => \^doado\(6),
O => config_finished_INST_0_i_1_n_0
);
config_finished_INST_0_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(1),
I1 => \^doado\(0),
I2 => \^doado\(3),
I3 => \^doado\(2),
O => config_finished_INST_0_i_2_n_0
);
config_finished_INST_0_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(13),
I1 => \^doado\(12),
I2 => \^doado\(15),
I3 => \^doado\(14),
O => config_finished_INST_0_i_3_n_0
);
config_finished_INST_0_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(9),
I1 => \^doado\(8),
I2 => \^doado\(11),
I3 => \^doado\(10),
O => config_finished_INST_0_i_4_n_0
);
\divider[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFE0000"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
I4 => \divider_reg[2]\,
I5 => p_0_in,
O => \divider_reg[7]\(0)
);
sreg_reg: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"53295217510C50344F4014383A04401004008C003E000C001100120412801280",
INIT_01 => X"229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440",
INIT_02 => X"90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(13 downto 12) => B"00",
ADDRARDADDR(11 downto 4) => address(7 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 0) => B"11111111111111",
CLKARDCLK => clk,
CLKBWRCLK => '0',
DIADI(15 downto 0) => B"1111111111111111",
DIBDI(15 downto 0) => B"1111111111111111",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"11",
DOADO(15 downto 0) => \^doado\(15 downto 0),
DOBDO(15 downto 0) => NLW_sreg_reg_DOBDO_UNCONNECTED(15 downto 0),
DOPADOP(1 downto 0) => NLW_sreg_reg_DOPADOP_UNCONNECTED(1 downto 0),
DOPBDOP(1 downto 0) => NLW_sreg_reg_DOPBDOP_UNCONNECTED(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"00",
WEBWE(3 downto 0) => B"0000"
);
taken_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055555554"
)
port map (
I0 => p_0_in,
I1 => config_finished_INST_0_i_1_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_3_n_0,
I4 => config_finished_INST_0_i_4_n_0,
I5 => \divider_reg[2]\,
O => taken_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_1_0_ov7670_controller is
port (
config_finished : out STD_LOGIC;
siod : out STD_LOGIC;
sioc : out STD_LOGIC;
resend : in STD_LOGIC;
clk : in STD_LOGIC
);
end system_ov7670_controller_1_0_ov7670_controller;
architecture STRUCTURE of system_ov7670_controller_1_0_ov7670_controller is
signal Inst_i2c_sender_n_3 : STD_LOGIC;
signal Inst_ov7670_registers_n_16 : STD_LOGIC;
signal Inst_ov7670_registers_n_18 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal sreg_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
signal taken : STD_LOGIC;
begin
Inst_i2c_sender: entity work.system_ov7670_controller_1_0_i2c_sender
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
\busy_sr_reg[1]_0\ => Inst_i2c_sender_n_3,
\busy_sr_reg[31]_0\ => Inst_ov7670_registers_n_18,
\busy_sr_reg[31]_1\(0) => Inst_ov7670_registers_n_16,
clk => clk,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
sioc => sioc,
siod => siod
);
Inst_ov7670_registers: entity work.system_ov7670_controller_1_0_ov7670_registers
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
clk => clk,
config_finished => config_finished,
\divider_reg[2]\ => Inst_i2c_sender_n_3,
\divider_reg[7]\(0) => Inst_ov7670_registers_n_16,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
resend => resend,
taken_reg => Inst_ov7670_registers_n_18
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_1_0 is
port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_ov7670_controller_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_ov7670_controller_1_0 : entity is "system_ov7670_controller_1_0,ov7670_controller,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_ov7670_controller_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_ov7670_controller_1_0 : entity is "ov7670_controller,Vivado 2016.4";
end system_ov7670_controller_1_0;
architecture STRUCTURE of system_ov7670_controller_1_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
pwdn <= \<const0>\;
reset <= \<const1>\;
xclk <= 'Z';
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_ov7670_controller_1_0_ov7670_controller
port map (
clk => clk,
config_finished => config_finished,
resend => resend,
sioc => sioc,
siod => siod
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
| mit | 9c43e2eea7a78e156e297adbb888f7f7 | 0.531728 | 2.810573 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0/sim/system_ov7670_controller_0_0.vhd | 5 | 3,747 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ov7670_controller:1.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_ov7670_controller_0_0 IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END system_ov7670_controller_0_0;
ARCHITECTURE system_ov7670_controller_0_0_arch OF system_ov7670_controller_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ov7670_controller_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT ov7670_controller IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END COMPONENT ov7670_controller;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
BEGIN
U0 : ov7670_controller
PORT MAP (
clk => clk,
resend => resend,
config_finished => config_finished,
sioc => sioc,
siod => siod,
reset => reset,
pwdn => pwdn,
xclk => xclk
);
END system_ov7670_controller_0_0_arch;
| mit | 94e956914f2b260cdb341f45a0815033 | 0.721911 | 4.037716 | false | false | false | false |
ashikpoojari/Hardware-Security | PUF Lab/Students_PUFS/puf_lab_mos283_ad3572/rogenie.vhd | 4 | 2,221 | ----------------------------------------------------------------------------------
-- Company: VNIE ENTITIES
-- Engineer: Vinayaka Jyothi
--
-- Create Date: 18:42:34 04/19/2017
-- Design Name: Variable_Chain_Ring_Oscillator_Generator
-- Module Name: RO_GENIE - Structural
-- Project Name: FPGA Trojan Detection
-- Target Devices: Any FPGA Device
-- Tool versions: ISE, Vivado
-- Description: This file allows to describe a N-stage ring oscillator.
-- User can change the value of RO_ChainLength in Line 30.
-- RO needs odd number of elements. RO_ChainLength should be odd.
-- ENABLE=1 to activate RO--> you get oscillations else RO is deactivated
--
-- Dependencies: None
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity RO_GENIE is
generic (RO_ChainLength: integer := 5
);
port( ENABLE : in std_logic;
RO_OSC_OUT: out std_logic
);
end RO_GENIE;
architecture structure of RO_GENIE is
signal RO_PATH_INV : std_logic_vector(RO_ChainLength-1 downto 0);
-- The following attributes stop delay/inverter logic chain from being optimised
-- Keeps the nodes being absorbed/collapsed and allows creating a combinational loop
ATTRIBUTE KEEP: BOOLEAN;
ATTRIBUTE SYN_KEEP: BOOLEAN;
ATTRIBUTE KEEP of RO_PATH_INV: signal is TRUE;
ATTRIBUTE SYN_KEEP of RO_PATH_INV: signal is TRUE;
begin
--This line raises an error if the user specifies a RO with even number of inverting elements. Will not generate any hardware
assert RO_ChainLength mod 2 = 1 report "The number of inverting elements should be an odd number.. Change RO_ChainLength!" severity failure;
gen_ring_osc:
for i in 2 to RO_ChainLength generate
RO_PATH_INV(i-1) <= not RO_PATH_INV(i-2);
end generate;
-- NAND GATES ACTS AS INVERTER WHEN '1'; So when ENABLE=1, you get oscillations else RO chain is broken and no oscillations are produced
RO_PATH_INV(0) <= RO_PATH_INV(RO_ChainLength-1) nand enable;
RO_OSC_OUT <= RO_PATH_INV(RO_ChainLength-2);
end structure; | mit | 4f150d762d1708b4f31b750565df263d | 0.669968 | 3.677152 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_vga_pll_0_0/system_vga_pll_0_0_sim_netlist.vhdl | 1 | 4,341 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:28:56 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_vga_pll_0_0/system_vga_pll_0_0_sim_netlist.vhdl
-- Design : system_vga_pll_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_pll_0_0_vga_pll is
port (
clk_50 : out STD_LOGIC;
clk_25 : out STD_LOGIC;
clk_12_5 : out STD_LOGIC;
clk_6_25 : out STD_LOGIC;
clk_100 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_pll_0_0_vga_pll : entity is "vga_pll";
end system_vga_pll_0_0_vga_pll;
architecture STRUCTURE of system_vga_pll_0_0_vga_pll is
signal \^clk_12_5\ : STD_LOGIC;
signal clk_12_5_s_i_1_n_0 : STD_LOGIC;
signal \^clk_25\ : STD_LOGIC;
signal clk_25_s_i_1_n_0 : STD_LOGIC;
signal \^clk_50\ : STD_LOGIC;
signal \^clk_6_25\ : STD_LOGIC;
signal clk_6_25_s_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
begin
clk_12_5 <= \^clk_12_5\;
clk_25 <= \^clk_25\;
clk_50 <= \^clk_50\;
clk_6_25 <= \^clk_6_25\;
clk_12_5_s_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^clk_12_5\,
O => clk_12_5_s_i_1_n_0
);
clk_12_5_s_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^clk_25\,
CE => '1',
D => clk_12_5_s_i_1_n_0,
Q => \^clk_12_5\,
R => '0'
);
clk_25_s_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^clk_25\,
O => clk_25_s_i_1_n_0
);
clk_25_s_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^clk_50\,
CE => '1',
D => clk_25_s_i_1_n_0,
Q => \^clk_25\,
R => '0'
);
clk_50_s_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^clk_50\,
O => p_0_in
);
clk_50_s_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => '1',
D => p_0_in,
Q => \^clk_50\,
R => '0'
);
clk_6_25_s_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^clk_6_25\,
O => clk_6_25_s_i_1_n_0
);
clk_6_25_s_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^clk_6_25\,
CE => '1',
D => clk_6_25_s_i_1_n_0,
Q => \^clk_6_25\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_pll_0_0 is
port (
clk_100 : in STD_LOGIC;
clk_50 : out STD_LOGIC;
clk_25 : out STD_LOGIC;
clk_12_5 : out STD_LOGIC;
clk_6_25 : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_pll_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_pll_0_0 : entity is "system_vga_pll_0_0,vga_pll,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_pll_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_pll_0_0 : entity is "vga_pll,Vivado 2016.4";
end system_vga_pll_0_0;
architecture STRUCTURE of system_vga_pll_0_0 is
begin
U0: entity work.system_vga_pll_0_0_vga_pll
port map (
clk_100 => clk_100,
clk_12_5 => clk_12_5,
clk_25 => clk_25,
clk_50 => clk_50,
clk_6_25 => clk_6_25
);
end STRUCTURE;
| mit | d5fa502ecefd3d5ba31d4153709586e4 | 0.554711 | 2.923232 | false | false | false | false |
pgavin/carpe | hdl/tech/inferred/syncram_1r1w-rtl.vhdl | 1 | 1,672 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of syncram_1r1w is
begin
syncram : entity work.syncram_1r1w_inferred(rtl)
generic map (
addr_bits => addr_bits,
data_bits => data_bits,
write_first => write_first
)
port map (
clk => clk,
we => we,
waddr => waddr,
wdata => wdata,
re => re,
raddr => raddr,
rdata => rdata
);
end;
| apache-2.0 | c01849108fe3cfc186f412ee6c99a03e | 0.489833 | 4.961424 | false | false | false | false |
loa-org/loa-hdl | modules/uss_tx/tb/uss_tx_module_tb.vhd | 2 | 3,524 | -------------------------------------------------------------------------------
-- Title : Testbench for Ultrasonic Transmitters
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.motor_control_pkg.all;
-------------------------------------------------------------------------------
entity uss_tx_module_tb is
end uss_tx_module_tb;
-------------------------------------------------------------------------------
architecture tb of uss_tx_module_tb is
use work.uss_tx_pkg.all;
use work.reg_file_pkg.all;
use work.bus_pkg.all;
-- Component generics
constant BASE_ADDRESS : integer := 16#0000#;
-- Signals for component ports
signal uss_tx0_out_s : half_bridge_type;
signal uss_tx1_out_s : half_bridge_type;
signal uss_tx2_out_s : half_bridge_type;
signal clk_uss_enable_p : std_logic;
signal bus_o : busdevice_out_type;
signal bus_i : busdevice_in_type;
signal clk : std_logic := '0';
begin -- tb
---------------------------------------------------------------------------
-- component instatiation
---------------------------------------------------------------------------
uss_tx_module_1 : uss_tx_module
generic map (
BASE_ADDRESS => BASE_ADDRESS)
port map (
uss_tx0_out_p => uss_tx0_out_s,
uss_tx1_out_p => uss_tx1_out_s,
uss_tx2_out_p => uss_tx2_out_s,
clk_uss_enable_p => clk_uss_enable_p,
bus_o => bus_o,
bus_i => bus_i,
clk => clk);
-------------------------------------------------------------------------------
-- Stimuli
-------------------------------------------------------------------------------
-- clock generation, 50 MHz
clk <= not clk after 10 ns;
-- bus stimulus
bus_stimulus_proc : process
begin
bus_i.addr <= (others => '0');
bus_i.data <= (others => '0');
bus_i.re <= '0';
bus_i.we <= '0';
wait until clk = '1';
-- write 0x0000 (MUL) to 0x00
wait until clk = '1';
bus_i.addr <= (others => '0');
bus_i.data <= x"0001";
bus_i.re <= '0';
bus_i.we <= '1';
wait until clk = '1';
bus_i.we <= '0';
wait until clk = '1';
wait until clk = '1';
-- write 0x05f4 (DIV) to 0x01
wait until clk = '1';
bus_i.addr(0) <= '1';
bus_i.data <= x"0400";
bus_i.re <= '0';
bus_i.we <= '1';
wait until clk = '1';
bus_i.data <= (others => '0');
bus_i.we <= '0';
-- write 0x5501 pattern to 0x02
wait until clk = '1';
bus_i.addr(0) <= '0';
bus_i.addr(1) <= '1';
bus_i.data <= x"5501";
bus_i.re <= '0';
bus_i.we <= '1';
wait until clk = '1';
bus_i.data <= (others => '0');
bus_i.we <= '0';
wait for 200 us;
-- decrease frequency by writing 0x0500 to 0x01
wait until clk = '1';
bus_i.addr(0) <= '1';
bus_i.data <= x"0500";
bus_i.re <= '0';
bus_i.we <= '1';
wait until clk = '1';
bus_i.data <= (others => '0');
bus_i.we <= '0';
wait for 10 ms;
end process bus_stimulus_proc;
end tb;
| bsd-3-clause | c0cf9fd9975f6fc006fd7ccefe9ed8eb | 0.404654 | 3.651813 | false | false | false | false |
loa-org/loa-hdl | modules/peripheral_register/hdl/double_buffering.vhd | 2 | 2,247 | -------------------------------------------------------------------------------
-- Title : Double Buffering Control
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.reg_file_pkg.all;
use work.utils_pkg.all;
entity double_buffering is
port (
ready_p : in std_logic;
enable_p : out std_logic;
irq_p : out std_logic;
ack_p : in std_logic;
bank_p : out std_logic;
clk : in std_logic);
end double_buffering;
architecture behavourial of double_buffering is
signal enable_s : std_logic := '0';
signal irq_s : std_logic := '0';
signal bank_s : std_logic := '0';
signal ack_rise_s : std_logic := '0';
begin -- behavourial
-- does synchronisation, can be connected directly to port pin.
edge_detect_1 : entity work.edge_detect
port map (
async_sig => ack_p,
clk => clk,
rise => ack_rise_s,
fall => open);
enable_p <= enable_s;
irq_p <= irq_s;
bank_p <= bank_s;
irq_proc : process (clk) is
begin -- process
if rising_edge(clk) then -- rising clock edge
if (ready_p = '1') then
irq_s <= '1';
elsif (ack_rise_s = '1') then
irq_s <= '0';
else
-- keep
irq_s <= irq_s;
end if;
end if;
end process irq_proc;
--
bank_proc : process (clk) is
begin -- process bank_proc
if rising_edge(clk) then -- rising clock edge
if (ready_p = '1') and (irq_s = '0') then
-- the other bank was read and is empty now (= irq_s low)
bank_s <= not bank_s;
end if;
end if;
end process bank_proc;
-- types
-- signals
end behavourial;
| bsd-3-clause | a7566d9b879b98121a5e0a708acadadf | 0.439252 | 4.070652 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/test_cdma/test_cdma.srcs/sources_1/bd/system/ip/system_axi_datamover_0_0/sim/system_axi_datamover_0_0.vhd | 1 | 24,467 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_datamover:5.1
-- IP Revision: 13
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_datamover_v5_1_13;
USE axi_datamover_v5_1_13.axi_datamover;
ENTITY system_axi_datamover_0_0 IS
PORT (
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_mm2s_aresetn : IN STD_LOGIC;
mm2s_err : OUT STD_LOGIC;
m_axis_mm2s_cmdsts_aclk : IN STD_LOGIC;
m_axis_mm2s_cmdsts_aresetn : IN STD_LOGIC;
s_axis_mm2s_cmd_tvalid : IN STD_LOGIC;
s_axis_mm2s_cmd_tready : OUT STD_LOGIC;
s_axis_mm2s_cmd_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
m_axis_mm2s_sts_tvalid : OUT STD_LOGIC;
m_axis_mm2s_sts_tready : IN STD_LOGIC;
m_axis_mm2s_sts_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_mm2s_sts_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_sts_tlast : OUT STD_LOGIC;
m_axi_mm2s_arid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
m_axi_s2mm_aresetn : IN STD_LOGIC;
s2mm_err : OUT STD_LOGIC;
m_axis_s2mm_cmdsts_awclk : IN STD_LOGIC;
m_axis_s2mm_cmdsts_aresetn : IN STD_LOGIC;
s_axis_s2mm_cmd_tvalid : IN STD_LOGIC;
s_axis_s2mm_cmd_tready : OUT STD_LOGIC;
s_axis_s2mm_cmd_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
m_axis_s2mm_sts_tvalid : OUT STD_LOGIC;
m_axis_s2mm_sts_tready : IN STD_LOGIC;
m_axis_s2mm_sts_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_s2mm_sts_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_s2mm_sts_tlast : OUT STD_LOGIC;
m_axi_s2mm_awid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tlast : IN STD_LOGIC;
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC
);
END system_axi_datamover_0_0;
ARCHITECTURE system_axi_datamover_0_0_arch OF system_axi_datamover_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_datamover_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_datamover IS
GENERIC (
C_INCLUDE_MM2S : INTEGER;
C_M_AXI_MM2S_ARID : INTEGER;
C_M_AXI_MM2S_ID_WIDTH : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_STSFIFO : INTEGER;
C_MM2S_STSCMD_FIFO_DEPTH : INTEGER;
C_MM2S_STSCMD_IS_ASYNC : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_MM2S_BURST_SIZE : INTEGER;
C_MM2S_BTT_USED : INTEGER;
C_MM2S_ADDR_PIPE_DEPTH : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_M_AXI_S2MM_AWID : INTEGER;
C_M_AXI_S2MM_ID_WIDTH : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_STSFIFO : INTEGER;
C_S2MM_STSCMD_FIFO_DEPTH : INTEGER;
C_S2MM_STSCMD_IS_ASYNC : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_S2MM_BURST_SIZE : INTEGER;
C_S2MM_BTT_USED : INTEGER;
C_S2MM_SUPPORT_INDET_BTT : INTEGER;
C_S2MM_ADDR_PIPE_DEPTH : INTEGER;
C_FAMILY : STRING;
C_MM2S_INCLUDE_SF : INTEGER;
C_S2MM_INCLUDE_SF : INTEGER;
C_ENABLE_CACHE_USER : INTEGER;
C_ENABLE_MM2S_TKEEP : INTEGER;
C_ENABLE_S2MM_TKEEP : INTEGER;
C_ENABLE_SKID_BUF : STRING;
C_ENABLE_S2MM_ADV_SIG : INTEGER;
C_ENABLE_MM2S_ADV_SIG : INTEGER;
C_CMD_WIDTH : INTEGER
);
PORT (
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_mm2s_aresetn : IN STD_LOGIC;
mm2s_halt : IN STD_LOGIC;
mm2s_halt_cmplt : OUT STD_LOGIC;
mm2s_err : OUT STD_LOGIC;
m_axis_mm2s_cmdsts_aclk : IN STD_LOGIC;
m_axis_mm2s_cmdsts_aresetn : IN STD_LOGIC;
s_axis_mm2s_cmd_tvalid : IN STD_LOGIC;
s_axis_mm2s_cmd_tready : OUT STD_LOGIC;
s_axis_mm2s_cmd_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
m_axis_mm2s_sts_tvalid : OUT STD_LOGIC;
m_axis_mm2s_sts_tready : IN STD_LOGIC;
m_axis_mm2s_sts_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_mm2s_sts_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_sts_tlast : OUT STD_LOGIC;
mm2s_allow_addr_req : IN STD_LOGIC;
mm2s_addr_req_posted : OUT STD_LOGIC;
mm2s_rd_xfer_cmplt : OUT STD_LOGIC;
m_axi_mm2s_arid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
mm2s_dbg_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
mm2s_dbg_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_aclk : IN STD_LOGIC;
m_axi_s2mm_aresetn : IN STD_LOGIC;
s2mm_halt : IN STD_LOGIC;
s2mm_halt_cmplt : OUT STD_LOGIC;
s2mm_err : OUT STD_LOGIC;
m_axis_s2mm_cmdsts_awclk : IN STD_LOGIC;
m_axis_s2mm_cmdsts_aresetn : IN STD_LOGIC;
s_axis_s2mm_cmd_tvalid : IN STD_LOGIC;
s_axis_s2mm_cmd_tready : OUT STD_LOGIC;
s_axis_s2mm_cmd_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
m_axis_s2mm_sts_tvalid : OUT STD_LOGIC;
m_axis_s2mm_sts_tready : IN STD_LOGIC;
m_axis_s2mm_sts_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_s2mm_sts_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_s2mm_sts_tlast : OUT STD_LOGIC;
s2mm_allow_addr_req : IN STD_LOGIC;
s2mm_addr_req_posted : OUT STD_LOGIC;
s2mm_wr_xfer_cmplt : OUT STD_LOGIC;
s2mm_ld_nxt_len : OUT STD_LOGIC;
s2mm_wr_len : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tlast : IN STD_LOGIC;
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s2mm_dbg_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s2mm_dbg_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_datamover;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXI_MM2S_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_cmdsts_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_MM2S_CMDSTS_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_cmdsts_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXIS_MM2S_CMDSTS_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_mm2s_cmd_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_MM2S_CMD TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_mm2s_cmd_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_MM2S_CMD TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_mm2s_cmd_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_MM2S_CMD TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_sts_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S_STS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_sts_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S_STS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_sts_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S_STS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_sts_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S_STS TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_sts_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S_STS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aruser: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXI_S2MM_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_cmdsts_awclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_S2MM_CMDSTS_AWCLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_cmdsts_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXIS_S2MM_CMDSTS_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_cmd_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM_CMD TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_cmd_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM_CMD TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_cmd_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM_CMD TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_sts_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_STS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_sts_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_STS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_sts_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_STS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_sts_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_STS TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_sts_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_STS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awuser: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
BEGIN
U0 : axi_datamover
GENERIC MAP (
C_INCLUDE_MM2S => 1,
C_M_AXI_MM2S_ARID => 0,
C_M_AXI_MM2S_ID_WIDTH => 4,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 32,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_MM2S_STSFIFO => 1,
C_MM2S_STSCMD_FIFO_DEPTH => 4,
C_MM2S_STSCMD_IS_ASYNC => 1,
C_INCLUDE_MM2S_DRE => 0,
C_MM2S_BURST_SIZE => 16,
C_MM2S_BTT_USED => 16,
C_MM2S_ADDR_PIPE_DEPTH => 3,
C_INCLUDE_S2MM => 1,
C_M_AXI_S2MM_AWID => 0,
C_M_AXI_S2MM_ID_WIDTH => 4,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_INCLUDE_S2MM_STSFIFO => 1,
C_S2MM_STSCMD_FIFO_DEPTH => 4,
C_S2MM_STSCMD_IS_ASYNC => 1,
C_INCLUDE_S2MM_DRE => 0,
C_S2MM_BURST_SIZE => 16,
C_S2MM_BTT_USED => 16,
C_S2MM_SUPPORT_INDET_BTT => 0,
C_S2MM_ADDR_PIPE_DEPTH => 4,
C_FAMILY => "zynq",
C_MM2S_INCLUDE_SF => 1,
C_S2MM_INCLUDE_SF => 1,
C_ENABLE_CACHE_USER => 0,
C_ENABLE_MM2S_TKEEP => 1,
C_ENABLE_S2MM_TKEEP => 1,
C_ENABLE_SKID_BUF => "11111",
C_ENABLE_S2MM_ADV_SIG => 0,
C_ENABLE_MM2S_ADV_SIG => 0,
C_CMD_WIDTH => 72
)
PORT MAP (
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_mm2s_aresetn => m_axi_mm2s_aresetn,
mm2s_halt => '0',
mm2s_err => mm2s_err,
m_axis_mm2s_cmdsts_aclk => m_axis_mm2s_cmdsts_aclk,
m_axis_mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn,
s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid,
s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready,
s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata,
m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid,
m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready,
m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata,
m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep,
m_axis_mm2s_sts_tlast => m_axis_mm2s_sts_tlast,
mm2s_allow_addr_req => '1',
m_axi_mm2s_arid => m_axi_mm2s_arid,
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_aruser => m_axi_mm2s_aruser,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
mm2s_dbg_sel => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
m_axi_s2mm_aresetn => m_axi_s2mm_aresetn,
s2mm_halt => '0',
s2mm_err => s2mm_err,
m_axis_s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk,
m_axis_s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn,
s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid,
s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready,
s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata,
m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid,
m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready,
m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata,
m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep,
m_axis_s2mm_sts_tlast => m_axis_s2mm_sts_tlast,
s2mm_allow_addr_req => '1',
m_axi_s2mm_awid => m_axi_s2mm_awid,
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awuser => m_axi_s2mm_awuser,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s2mm_dbg_sel => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4))
);
END system_axi_datamover_0_0_arch;
| mit | 815ba6835efb8c3c1c45ce61ea4519a4 | 0.681489 | 2.683668 | false | false | false | false |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/niosii_system_width_adapter_005.vhd | 1 | 10,497 | -- niosii_system_width_adapter_005.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:30
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_width_adapter_005 is
generic (
IN_PKT_ADDR_H : integer := 33;
IN_PKT_ADDR_L : integer := 9;
IN_PKT_DATA_H : integer := 7;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 8;
IN_PKT_BYTEEN_L : integer := 8;
IN_PKT_BYTE_CNT_H : integer := 42;
IN_PKT_BYTE_CNT_L : integer := 40;
IN_PKT_TRANS_COMPRESSED_READ : integer := 34;
IN_PKT_BURSTWRAP_H : integer := 45;
IN_PKT_BURSTWRAP_L : integer := 43;
IN_PKT_BURST_SIZE_H : integer := 48;
IN_PKT_BURST_SIZE_L : integer := 46;
IN_PKT_RESPONSE_STATUS_H : integer := 72;
IN_PKT_RESPONSE_STATUS_L : integer := 71;
IN_PKT_TRANS_EXCLUSIVE : integer := 39;
IN_PKT_BURST_TYPE_H : integer := 50;
IN_PKT_BURST_TYPE_L : integer := 49;
IN_ST_DATA_W : integer := 73;
OUT_PKT_ADDR_H : integer := 60;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 69;
OUT_PKT_BYTE_CNT_L : integer := 67;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 61;
OUT_PKT_BURST_SIZE_H : integer := 75;
OUT_PKT_BURST_SIZE_L : integer := 73;
OUT_PKT_RESPONSE_STATUS_H : integer := 99;
OUT_PKT_RESPONSE_STATUS_L : integer := 98;
OUT_PKT_TRANS_EXCLUSIVE : integer := 66;
OUT_PKT_BURST_TYPE_H : integer := 77;
OUT_PKT_BURST_TYPE_L : integer := 76;
OUT_ST_DATA_W : integer := 100;
ST_CHANNEL_W : integer := 13;
OPTIMIZE_FOR_RSP : integer := 1;
RESPONSE_PATH : integer := 1
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- clk_reset.reset
in_valid : in std_logic := '0'; -- sink.valid
in_channel : in std_logic_vector(12 downto 0) := (others => '0'); -- .channel
in_startofpacket : in std_logic := '0'; -- .startofpacket
in_endofpacket : in std_logic := '0'; -- .endofpacket
in_ready : out std_logic; -- .ready
in_data : in std_logic_vector(72 downto 0) := (others => '0'); -- .data
out_endofpacket : out std_logic; -- src.endofpacket
out_data : out std_logic_vector(99 downto 0); -- .data
out_channel : out std_logic_vector(12 downto 0); -- .channel
out_valid : out std_logic; -- .valid
out_ready : in std_logic := '0'; -- .ready
out_startofpacket : out std_logic; -- .startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => '0')
);
end entity niosii_system_width_adapter_005;
architecture rtl of niosii_system_width_adapter_005 is
component altera_merlin_width_adapter is
generic (
IN_PKT_ADDR_H : integer := 60;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 63;
IN_PKT_BYTE_CNT_L : integer := 61;
IN_PKT_TRANS_COMPRESSED_READ : integer := 65;
IN_PKT_BURSTWRAP_H : integer := 67;
IN_PKT_BURSTWRAP_L : integer := 66;
IN_PKT_BURST_SIZE_H : integer := 70;
IN_PKT_BURST_SIZE_L : integer := 68;
IN_PKT_RESPONSE_STATUS_H : integer := 72;
IN_PKT_RESPONSE_STATUS_L : integer := 71;
IN_PKT_TRANS_EXCLUSIVE : integer := 73;
IN_PKT_BURST_TYPE_H : integer := 75;
IN_PKT_BURST_TYPE_L : integer := 74;
IN_ST_DATA_W : integer := 76;
OUT_PKT_ADDR_H : integer := 60;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 63;
OUT_PKT_BYTE_CNT_L : integer := 61;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 65;
OUT_PKT_BURST_SIZE_H : integer := 68;
OUT_PKT_BURST_SIZE_L : integer := 66;
OUT_PKT_RESPONSE_STATUS_H : integer := 70;
OUT_PKT_RESPONSE_STATUS_L : integer := 69;
OUT_PKT_TRANS_EXCLUSIVE : integer := 71;
OUT_PKT_BURST_TYPE_H : integer := 73;
OUT_PKT_BURST_TYPE_L : integer := 72;
OUT_ST_DATA_W : integer := 74;
ST_CHANNEL_W : integer := 32;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(72 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(99 downto 0); -- data
out_channel : out std_logic_vector(12 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data
);
end component altera_merlin_width_adapter;
begin
width_adapter_005 : component altera_merlin_width_adapter
generic map (
IN_PKT_ADDR_H => IN_PKT_ADDR_H,
IN_PKT_ADDR_L => IN_PKT_ADDR_L,
IN_PKT_DATA_H => IN_PKT_DATA_H,
IN_PKT_DATA_L => IN_PKT_DATA_L,
IN_PKT_BYTEEN_H => IN_PKT_BYTEEN_H,
IN_PKT_BYTEEN_L => IN_PKT_BYTEEN_L,
IN_PKT_BYTE_CNT_H => IN_PKT_BYTE_CNT_H,
IN_PKT_BYTE_CNT_L => IN_PKT_BYTE_CNT_L,
IN_PKT_TRANS_COMPRESSED_READ => IN_PKT_TRANS_COMPRESSED_READ,
IN_PKT_BURSTWRAP_H => IN_PKT_BURSTWRAP_H,
IN_PKT_BURSTWRAP_L => IN_PKT_BURSTWRAP_L,
IN_PKT_BURST_SIZE_H => IN_PKT_BURST_SIZE_H,
IN_PKT_BURST_SIZE_L => IN_PKT_BURST_SIZE_L,
IN_PKT_RESPONSE_STATUS_H => IN_PKT_RESPONSE_STATUS_H,
IN_PKT_RESPONSE_STATUS_L => IN_PKT_RESPONSE_STATUS_L,
IN_PKT_TRANS_EXCLUSIVE => IN_PKT_TRANS_EXCLUSIVE,
IN_PKT_BURST_TYPE_H => IN_PKT_BURST_TYPE_H,
IN_PKT_BURST_TYPE_L => IN_PKT_BURST_TYPE_L,
IN_ST_DATA_W => IN_ST_DATA_W,
OUT_PKT_ADDR_H => OUT_PKT_ADDR_H,
OUT_PKT_ADDR_L => OUT_PKT_ADDR_L,
OUT_PKT_DATA_H => OUT_PKT_DATA_H,
OUT_PKT_DATA_L => OUT_PKT_DATA_L,
OUT_PKT_BYTEEN_H => OUT_PKT_BYTEEN_H,
OUT_PKT_BYTEEN_L => OUT_PKT_BYTEEN_L,
OUT_PKT_BYTE_CNT_H => OUT_PKT_BYTE_CNT_H,
OUT_PKT_BYTE_CNT_L => OUT_PKT_BYTE_CNT_L,
OUT_PKT_TRANS_COMPRESSED_READ => OUT_PKT_TRANS_COMPRESSED_READ,
OUT_PKT_BURST_SIZE_H => OUT_PKT_BURST_SIZE_H,
OUT_PKT_BURST_SIZE_L => OUT_PKT_BURST_SIZE_L,
OUT_PKT_RESPONSE_STATUS_H => OUT_PKT_RESPONSE_STATUS_H,
OUT_PKT_RESPONSE_STATUS_L => OUT_PKT_RESPONSE_STATUS_L,
OUT_PKT_TRANS_EXCLUSIVE => OUT_PKT_TRANS_EXCLUSIVE,
OUT_PKT_BURST_TYPE_H => OUT_PKT_BURST_TYPE_H,
OUT_PKT_BURST_TYPE_L => OUT_PKT_BURST_TYPE_L,
OUT_ST_DATA_W => OUT_ST_DATA_W,
ST_CHANNEL_W => ST_CHANNEL_W,
OPTIMIZE_FOR_RSP => OPTIMIZE_FOR_RSP,
RESPONSE_PATH => RESPONSE_PATH
)
port map (
clk => clk, -- clk.clk
reset => reset, -- clk_reset.reset
in_valid => in_valid, -- sink.valid
in_channel => in_channel, -- .channel
in_startofpacket => in_startofpacket, -- .startofpacket
in_endofpacket => in_endofpacket, -- .endofpacket
in_ready => in_ready, -- .ready
in_data => in_data, -- .data
out_endofpacket => out_endofpacket, -- src.endofpacket
out_data => out_data, -- .data
out_channel => out_channel, -- .channel
out_valid => out_valid, -- .valid
out_ready => out_ready, -- .ready
out_startofpacket => out_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
end architecture rtl; -- of niosii_system_width_adapter_005
| apache-2.0 | 1db9928de43f49d5fc5d1388f86248fa | 0.46137 | 3.371988 | false | false | false | false |
pgavin/carpe | hdl/sim/options_pkg.vhdl | 1 | 4,399 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
use std.textio.all;
package options_pkg is
procedure options_add(key : in string; value : in string);
procedure options_read(filename : in string);
signal options_ready : boolean := false;
impure function option(key : in string) return string;
end package;
package body options_pkg is
type option_type;
type option_ptr_type is access option_type;
type option_type is record
key : line;
value : line;
next_option : option_ptr_type;
end record;
type options_type is protected
procedure add(key : in string; value : in string);
procedure read(filename : in string);
impure function get(key : in string) return string;
end protected;
type options_type is protected body
variable options : option_ptr_type := null;
procedure add(key : in string; value : in string) is
begin
assert not options_ready
report "options_add called when options are ready"
severity failure;
--report "option: " & key & "=" & value;
options := new option_type'(
key => new string'(key),
value => new string'(value),
next_option => options
);
end;
procedure read(filename : in string) is
variable l : line;
variable eqpos : natural;
file options_file : text;
begin
assert not options_ready
report "options_read called when options are ready"
severity failure;
--report "reading options file " & filename;
file_open(options_file, filename, read_mode);
while not endfile(options_file) loop
readline(options_file, l);
if l.all = "=" then
deallocate(l);
exit;
end if;
eqpos := 0;
for n in l.all'left to l.all'right loop
if l.all(n) = '=' then
eqpos := n;
exit;
end if;
end loop;
assert (eqpos > l.all'left and eqpos < l.all'right)
report "invalid option: " & l.all
severity failure;
add(l.all(l.all'left to eqpos-1), l.all(eqpos+1 to l.all'right));
deallocate(l);
l := null;
end loop;
file_close(options_file);
end procedure;
impure function get(key : in string) return string is
variable option : option_ptr_type;
begin
assert options_ready
report "option " & key & " requested before options are ready"
severity failure;
option := options;
while option /= null loop
if option.all.key.all = key then
return option.all.value.all;
end if;
option := option.all.next_option;
end loop;
return "";
end;
end protected body;
shared variable the_options : options_type;
procedure options_add(key : in string; value : in string) is
begin
the_options.add(key, value);
end procedure;
procedure options_read(filename : in string) is
begin
the_options.read(filename);
end procedure;
impure function option(key : in string) return string is
begin
return the_options.get(key);
end function;
end package body;
| apache-2.0 | b3da6bdb2dee0d07188af74b2c37b623 | 0.559673 | 4.521069 | false | false | false | false |
loa-org/loa-hdl | modules/adc_ltc2351/hdl/adc_ltc2351_module.vhd | 2 | 5,114 | -------------------------------------------------------------------------------
-- ADC LTC2351 module
--
-- Operates the LTC2351 in free running mode and connects it to
-- the internal parallel bus of the beacon board.
-- Provides a 'done' signal to the bus which can be used as an interrupt
-- source
--
-- Connects the adc_ltc2351 entity to the internal bus system.
--
-- @author strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.reg_file_pkg.all;
use work.adc_ltc2351_pkg.all;
-------------------------------------------------------------------------------
entity adc_ltc2351_module is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#
);
port (
-- signals to and from real hardware
adc_out_p : out adc_ltc2351_spi_out_type;
adc_in_p : in adc_ltc2351_spi_in_type;
-- signals to and from the internal parallel bus
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
-- interrupt for signalling that new samples are available
done_p : out std_logic;
-- direct access to the read adc samples
adc_values_o : out adc_ltc2351_values_type(5 downto 0);
clk : in std_logic
);
end adc_ltc2351_module;
-------------------------------------------------------------------------------
architecture behavioral of adc_ltc2351_module is
-- The ADC operates in free running mode
type adc_ltc2351_module_state_type is (
IDLE, -- a new result is available
CONVERTING -- a conversion is in progress
);
type adc_ltc2351_module_type is record
state : adc_ltc2351_module_state_type;
start : std_logic;
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : adc_ltc2351_module_type;
signal value_s : adc_ltc2351_values_type(5 downto 0); -- TODO use generic for channel number
signal done_s : std_logic := '0';
signal reg_o : reg_file_type(7 downto 0);
signal reg_i : reg_file_type(7 downto 0);
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
begin
----------------------------------------------------------------------------
-- mapping of signals to ADC interface
----------------------------------------------------------------------------
done_p <= done_s;
copy_reg : for ii in 0 to 5 generate
reg_i(ii) <= "00" & value_s(ii);
end generate copy_reg; -- ii
-----------------------------------------------------------------------------
-- Register file to present ADC values to bus
-----------------------------------------------------------------------------
reg_file_1 : reg_file
generic map (
BASE_ADDRESS => BASE_ADDRESS,
REG_ADDR_BIT => 3 -- 2**3 = 8 registers for 6 ADC values
)
port map (
bus_o => bus_o,
bus_i => bus_i,
reg_o => reg_o,
reg_i => reg_i,
clk => clk
);
-----------------------------------------------------------------------------
-- ADC interface module
-----------------------------------------------------------------------------
adc_ltc2351_1 : adc_ltc2351
port map (
-- connection between component's signals (left) and
-- modules's signals (right)
adc_out => adc_out_p,
adc_in => adc_in_p,
values_p => value_s,
start_p => r.start,
done_p => done_s,
clk => clk
);
-----------------------------------------------------------------------------
-- seq part of FSM
-----------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
-----------------------------------------------------------------------------
-- transitions and actions of FSM
-----------------------------------------------------------------------------
comb_proc : process(done_s, r, value_s)
variable v : adc_ltc2351_module_type;
begin
v := r;
case v.state is
when IDLE =>
-- free running mode: always start a new conversion if done;
-- if (done_s = '1') then
v.start := '1';
v.state := CONVERTING;
-- end if;
when CONVERTING =>
-- conversion is in progress
v.start := '0';
if done_s = '1' then
v.state := IDLE;
end if;
end case;
rin <= v;
end process comb_proc;
end behavioral; -- adc_ltc2351_module
| bsd-3-clause | f7a6c9cf1c1bd8a57c492a46e4a5c04c | 0.405162 | 4.92204 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_pll_0_0/sim/system_vga_pll_0_0.vhd | 3 | 3,725 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_pll:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_pll_0_0 IS
PORT (
clk_100 : IN STD_LOGIC;
clk_50 : OUT STD_LOGIC;
clk_25 : OUT STD_LOGIC;
clk_12_5 : OUT STD_LOGIC;
clk_6_25 : OUT STD_LOGIC
);
END system_vga_pll_0_0;
ARCHITECTURE system_vga_pll_0_0_arch OF system_vga_pll_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_pll_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_pll IS
PORT (
clk_100 : IN STD_LOGIC;
clk_50 : OUT STD_LOGIC;
clk_25 : OUT STD_LOGIC;
clk_12_5 : OUT STD_LOGIC;
clk_6_25 : OUT STD_LOGIC
);
END COMPONENT vga_pll;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk_100: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_100 CLK";
ATTRIBUTE X_INTERFACE_INFO OF clk_50: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_50 CLK";
ATTRIBUTE X_INTERFACE_INFO OF clk_25: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_25 CLK";
ATTRIBUTE X_INTERFACE_INFO OF clk_12_5: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_12_5 CLK";
ATTRIBUTE X_INTERFACE_INFO OF clk_6_25: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_6_25 CLK";
BEGIN
U0 : vga_pll
PORT MAP (
clk_100 => clk_100,
clk_50 => clk_50,
clk_25 => clk_25,
clk_12_5 => clk_12_5,
clk_6_25 => clk_6_25
);
END system_vga_pll_0_0_arch;
| mit | aeb4cca204f6f3383fd0f7b3250e965c | 0.721342 | 3.710159 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/video_passthrough/video_passthrough.srcs/sources_1/bd/system/ip/system_zybo_hdmi_0_0/synth/system_zybo_hdmi_0_0.vhd | 2 | 4,423 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:zybo_hdmi:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_zybo_hdmi_0_0 IS
PORT (
clk_125 : IN STD_LOGIC;
clk_25 : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
active : IN STD_LOGIC;
rgb : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
tmds : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
tmdsb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
hdmi_cec : IN STD_LOGIC;
hdmi_hpd : IN STD_LOGIC;
hdmi_out_en : OUT STD_LOGIC
);
END system_zybo_hdmi_0_0;
ARCHITECTURE system_zybo_hdmi_0_0_arch OF system_zybo_hdmi_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_zybo_hdmi_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT zybo_hdmi IS
PORT (
clk_125 : IN STD_LOGIC;
clk_25 : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
active : IN STD_LOGIC;
rgb : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
tmds : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
tmdsb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
hdmi_cec : IN STD_LOGIC;
hdmi_hpd : IN STD_LOGIC;
hdmi_out_en : OUT STD_LOGIC
);
END COMPONENT zybo_hdmi;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_zybo_hdmi_0_0_arch: ARCHITECTURE IS "zybo_hdmi,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_zybo_hdmi_0_0_arch : ARCHITECTURE IS "system_zybo_hdmi_0_0,zybo_hdmi,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_zybo_hdmi_0_0_arch: ARCHITECTURE IS "system_zybo_hdmi_0_0,zybo_hdmi,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=zybo_hdmi,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : zybo_hdmi
PORT MAP (
clk_125 => clk_125,
clk_25 => clk_25,
hsync => hsync,
vsync => vsync,
active => active,
rgb => rgb,
tmds => tmds,
tmdsb => tmdsb,
hdmi_cec => hdmi_cec,
hdmi_hpd => hdmi_hpd,
hdmi_out_en => hdmi_out_en
);
END system_zybo_hdmi_0_0_arch;
| mit | a9a7cc9a40a35535aa080ceda5605340 | 0.708795 | 3.691987 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_hessian_1_0/sim/system_vga_hessian_1_0.vhd | 2 | 3,767 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_hessian:1.0
-- IP Revision: 41
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_hessian_1_0 IS
PORT (
clk_x16 : IN STD_LOGIC;
active : IN STD_LOGIC;
rst : IN STD_LOGIC;
x_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
g_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_vga_hessian_1_0;
ARCHITECTURE system_vga_hessian_1_0_arch OF system_vga_hessian_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_hessian_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_hessian IS
GENERIC (
ROW_WIDTH : INTEGER
);
PORT (
clk_x16 : IN STD_LOGIC;
active : IN STD_LOGIC;
rst : IN STD_LOGIC;
x_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
g_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT vga_hessian;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_hessian
GENERIC MAP (
ROW_WIDTH => 10
)
PORT MAP (
clk_x16 => clk_x16,
active => active,
rst => rst,
x_addr => x_addr,
y_addr => y_addr,
g_in => g_in,
hessian_out => hessian_out
);
END system_vga_hessian_1_0_arch;
| mit | 954f3581d05cc393629755b2f2168288 | 0.71038 | 3.808898 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/hdl/system.vhd | 1 | 29,595 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Tue Jun 06 02:54:53 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system.bd
--Design : system
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
clk_100 : in STD_LOGIC;
data_0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
data_1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
hdmi_clk : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hsync_0 : in STD_LOGIC;
hsync_1 : in STD_LOGIC;
pclk_0 : in STD_LOGIC;
pclk_1 : in STD_LOGIC;
ready : out STD_LOGIC_VECTOR ( 0 to 0 );
reset : in STD_LOGIC;
sioc_0 : out STD_LOGIC;
sioc_1 : out STD_LOGIC;
siod_0 : inout STD_LOGIC;
siod_1 : inout STD_LOGIC;
vsync_0 : in STD_LOGIC;
vsync_1 : in STD_LOGIC;
xclk_0 : out STD_LOGIC;
xclk_1 : out STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of system : entity is "system,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=32,numReposBlks=32,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=14,da_board_cnt=4,da_bram_cntlr_cnt=2,da_ps7_cnt=3,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system : entity is "system.hwdef";
end system;
architecture STRUCTURE of system is
component system_ov7670_controller_0_0 is
port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
end component system_ov7670_controller_0_0;
component system_zed_hdmi_0_0 is
port (
clk : in STD_LOGIC;
clk_x2 : in STD_LOGIC;
clk_100 : in STD_LOGIC;
active : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC
);
end component system_zed_hdmi_0_0;
component system_rgb565_to_rgb888_0_0 is
port (
clk : in STD_LOGIC;
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_rgb565_to_rgb888_0_0;
component system_vga_buffer_0_0 is
port (
clk_w : in STD_LOGIC;
clk_r : in STD_LOGIC;
wen : in STD_LOGIC;
x_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
data_w : in STD_LOGIC_VECTOR ( 23 downto 0 );
data_r : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_vga_buffer_0_0;
component system_vga_sync_ref_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
start : out STD_LOGIC;
active : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_vga_sync_ref_0_0;
component system_debounce_0_0 is
port (
clk : in STD_LOGIC;
signal_in : in STD_LOGIC;
signal_out : out STD_LOGIC
);
end component system_debounce_0_0;
component system_ov7670_vga_0_0 is
port (
clk_x2 : in STD_LOGIC;
active : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end component system_ov7670_vga_0_0;
component system_clock_splitter_0_0 is
port (
clk_in : in STD_LOGIC;
latch_edge : in STD_LOGIC;
clk_out : out STD_LOGIC
);
end component system_clock_splitter_0_0;
component system_rgb888_to_g8_0_0 is
port (
clk : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
g8 : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component system_rgb888_to_g8_0_0;
component system_clk_wiz_0_0 is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC
);
end component system_clk_wiz_0_0;
component system_clk_wiz_1_0 is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC
);
end component system_clk_wiz_1_0;
component system_buffer_register_0_0 is
port (
clk : in STD_LOGIC;
val_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
val_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component system_buffer_register_0_0;
component system_inverter_0_0 is
port (
x : in STD_LOGIC;
x_not : out STD_LOGIC
);
end component system_inverter_0_0;
component system_vga_nmsuppression_0_0 is
port (
clk : in STD_LOGIC;
enable : in STD_LOGIC;
active : in STD_LOGIC;
x_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
x_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component system_vga_nmsuppression_0_0;
component system_ov7670_controller_1_0 is
port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
end component system_ov7670_controller_1_0;
component system_util_vector_logic_0_0 is
port (
Op1 : in STD_LOGIC_VECTOR ( 0 to 0 );
Op2 : in STD_LOGIC_VECTOR ( 0 to 0 );
Res : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component system_util_vector_logic_0_0;
component system_clock_splitter_1_0 is
port (
clk_in : in STD_LOGIC;
latch_edge : in STD_LOGIC;
clk_out : out STD_LOGIC
);
end component system_clock_splitter_1_0;
component system_vga_sync_ref_1_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
start : out STD_LOGIC;
active : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_vga_sync_ref_1_0;
component system_ov7670_vga_1_0 is
port (
clk_x2 : in STD_LOGIC;
active : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end component system_ov7670_vga_1_0;
component system_rgb565_to_rgb888_1_0 is
port (
clk : in STD_LOGIC;
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_rgb565_to_rgb888_1_0;
component system_vga_buffer_1_0 is
port (
clk_w : in STD_LOGIC;
clk_r : in STD_LOGIC;
wen : in STD_LOGIC;
x_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
data_w : in STD_LOGIC_VECTOR ( 23 downto 0 );
data_r : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_vga_buffer_1_0;
component system_rgb888_to_g8_1_0 is
port (
clk : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
g8 : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component system_rgb888_to_g8_1_0;
component system_vga_nmsuppression_1_0 is
port (
clk : in STD_LOGIC;
enable : in STD_LOGIC;
active : in STD_LOGIC;
x_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
x_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component system_vga_nmsuppression_1_0;
component system_buffer_register_1_0 is
port (
clk : in STD_LOGIC;
val_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
val_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component system_buffer_register_1_0;
component system_vga_feature_transform_0_0 is
port (
clk : in STD_LOGIC;
clk_x2 : in STD_LOGIC;
rst : in STD_LOGIC;
active : in STD_LOGIC;
vsync : in STD_LOGIC;
x_addr_0 : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_0 : in STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
x_addr_1 : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_1 : in STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
rot_m00 : out STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m01 : out STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m10 : out STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m11 : out STD_LOGIC_VECTOR ( 15 downto 0 );
t_x : out STD_LOGIC_VECTOR ( 9 downto 0 );
t_y : out STD_LOGIC_VECTOR ( 9 downto 0 );
state : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component system_vga_feature_transform_0_0;
component system_vga_transform_0_0 is
port (
clk : in STD_LOGIC;
enable : in STD_LOGIC;
x_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
rot_m00 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m01 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m10 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m11 : in STD_LOGIC_VECTOR ( 15 downto 0 );
t_x : in STD_LOGIC_VECTOR ( 9 downto 0 );
t_y : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_vga_transform_0_0;
component system_vga_overlay_0_0 is
port (
clk : in STD_LOGIC;
rgb_0 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_1 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_vga_overlay_0_0;
component system_vga_hessian_0_0 is
port (
clk_x16 : in STD_LOGIC;
active : in STD_LOGIC;
rst : in STD_LOGIC;
x_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
g_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component system_vga_hessian_0_0;
component system_vga_hessian_1_0 is
port (
clk_x16 : in STD_LOGIC;
active : in STD_LOGIC;
rst : in STD_LOGIC;
x_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
g_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component system_vga_hessian_1_0;
component system_vga_pll_0_0 is
port (
clk_100 : in STD_LOGIC;
clk_50 : out STD_LOGIC;
clk_25 : out STD_LOGIC;
clk_12_5 : out STD_LOGIC;
clk_6_25 : out STD_LOGIC
);
end component system_vga_pll_0_0;
component system_vga_sync_reset_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_vga_sync_reset_0_0;
component system_xlconstant_0_0 is
port (
dout : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component system_xlconstant_0_0;
signal Net : STD_LOGIC;
signal Net1 : STD_LOGIC;
signal Net2 : STD_LOGIC;
signal buffer_register_0_val_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffer_register_1_val_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal clk_100_1 : STD_LOGIC;
signal clk_wiz_0_clk_out2 : STD_LOGIC;
signal clk_wiz_1_clk_out1 : STD_LOGIC;
signal clock_splitter_0_clk_out : STD_LOGIC;
signal clock_splitter_1_clk_out : STD_LOGIC;
signal \^data_1\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal data_1_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal debounce_0_o : STD_LOGIC;
signal \^hsync_1\ : STD_LOGIC;
signal hsync_1_1 : STD_LOGIC;
signal inverter_0_x_not : STD_LOGIC;
signal ov7670_controller_0_config_finished : STD_LOGIC_VECTOR ( 0 to 0 );
signal ov7670_controller_0_config_finished1 : STD_LOGIC;
signal ov7670_controller_0_sioc : STD_LOGIC;
signal ov7670_controller_1_config_finished : STD_LOGIC;
signal ov7670_controller_1_sioc : STD_LOGIC;
signal ov7670_vga_0_rgb : STD_LOGIC_VECTOR ( 15 downto 0 );
signal ov7670_vga_1_rgb : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \^pclk_1\ : STD_LOGIC;
signal pclk_1_1 : STD_LOGIC;
signal reset_1 : STD_LOGIC;
signal rgb565_to_rgb888_0_rgb_888 : STD_LOGIC_VECTOR ( 23 downto 0 );
signal rgb565_to_rgb888_1_rgb_888 : STD_LOGIC_VECTOR ( 23 downto 0 );
signal rgb888_to_g8_0_g8 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal rgb888_to_g8_1_g8 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal vdd_dout : STD_LOGIC_VECTOR ( 0 to 0 );
signal vga_buffer_0_data_r : STD_LOGIC_VECTOR ( 23 downto 0 );
signal vga_buffer_1_data_r : STD_LOGIC_VECTOR ( 23 downto 0 );
signal vga_feature_transform_0_rot_m00 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal vga_feature_transform_0_rot_m01 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal vga_feature_transform_0_rot_m10 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal vga_feature_transform_0_rot_m11 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal vga_feature_transform_0_t_x : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_feature_transform_0_t_y : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_hessian_0_hessian_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal vga_hessian_1_hessian_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal vga_nmsuppression_0_hessian_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal vga_nmsuppression_1_hessian_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal vga_overlay_0_rgb : STD_LOGIC_VECTOR ( 23 downto 0 );
signal vga_pll_0_clk_12_5 : STD_LOGIC;
signal vga_pll_0_clk_25 : STD_LOGIC;
signal vga_sync_ref_0_active : STD_LOGIC;
signal vga_sync_ref_0_start : STD_LOGIC;
signal vga_sync_ref_0_xaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_ref_0_yaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_ref_1_active : STD_LOGIC;
signal vga_sync_ref_1_xaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_ref_1_yaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_reset_0_active : STD_LOGIC;
signal vga_sync_reset_0_hsync : STD_LOGIC;
signal vga_sync_reset_0_vsync : STD_LOGIC;
signal vga_sync_reset_0_xaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_reset_0_yaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_transform_0_x_addr_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_transform_0_y_addr_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^vsync_1\ : STD_LOGIC;
signal vsync_1_1 : STD_LOGIC;
signal zed_hdmi_0_hdmi_clk : STD_LOGIC;
signal zed_hdmi_0_hdmi_d : STD_LOGIC_VECTOR ( 15 downto 0 );
signal zed_hdmi_0_hdmi_de : STD_LOGIC;
signal zed_hdmi_0_hdmi_hsync : STD_LOGIC;
signal zed_hdmi_0_hdmi_scl : STD_LOGIC;
signal zed_hdmi_0_hdmi_vsync : STD_LOGIC;
signal NLW_clk_wiz_0_locked_UNCONNECTED : STD_LOGIC;
signal NLW_clk_wiz_1_locked_UNCONNECTED : STD_LOGIC;
signal NLW_ov7670_controller_0_pwdn_UNCONNECTED : STD_LOGIC;
signal NLW_ov7670_controller_0_reset_UNCONNECTED : STD_LOGIC;
signal NLW_ov7670_controller_0_xclk_UNCONNECTED : STD_LOGIC;
signal NLW_ov7670_controller_1_pwdn_UNCONNECTED : STD_LOGIC;
signal NLW_ov7670_controller_1_reset_UNCONNECTED : STD_LOGIC;
signal NLW_ov7670_controller_1_xclk_UNCONNECTED : STD_LOGIC;
signal NLW_vga_feature_transform_0_state_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_vga_nmsuppression_0_x_addr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_vga_nmsuppression_0_y_addr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_vga_nmsuppression_1_x_addr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_vga_nmsuppression_1_y_addr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_vga_pll_0_clk_50_UNCONNECTED : STD_LOGIC;
signal NLW_vga_pll_0_clk_6_25_UNCONNECTED : STD_LOGIC;
signal NLW_vga_sync_ref_1_start_UNCONNECTED : STD_LOGIC;
begin
\^data_1\(7 downto 0) <= data_0(7 downto 0);
\^hsync_1\ <= hsync_0;
\^pclk_1\ <= pclk_0;
\^vsync_1\ <= vsync_0;
clk_100_1 <= clk_100;
data_1_1(7 downto 0) <= data_1(7 downto 0);
hdmi_clk <= zed_hdmi_0_hdmi_clk;
hdmi_d(15 downto 0) <= zed_hdmi_0_hdmi_d(15 downto 0);
hdmi_de <= zed_hdmi_0_hdmi_de;
hdmi_hsync <= zed_hdmi_0_hdmi_hsync;
hdmi_scl <= zed_hdmi_0_hdmi_scl;
hdmi_vsync <= zed_hdmi_0_hdmi_vsync;
hsync_1_1 <= hsync_1;
pclk_1_1 <= pclk_1;
ready(0) <= ov7670_controller_0_config_finished(0);
reset_1 <= reset;
sioc_0 <= ov7670_controller_0_sioc;
sioc_1 <= ov7670_controller_1_sioc;
vsync_1_1 <= vsync_1;
xclk_0 <= clk_wiz_0_clk_out2;
xclk_1 <= clk_wiz_0_clk_out2;
buffer_register_0: component system_buffer_register_0_0
port map (
clk => vga_pll_0_clk_12_5,
val_in(31 downto 0) => vga_hessian_0_hessian_out(31 downto 0),
val_out(31 downto 0) => buffer_register_0_val_out(31 downto 0)
);
buffer_register_1: component system_buffer_register_1_0
port map (
clk => vga_pll_0_clk_12_5,
val_in(31 downto 0) => vga_hessian_1_hessian_out(31 downto 0),
val_out(31 downto 0) => buffer_register_1_val_out(31 downto 0)
);
clk_wiz_0: component system_clk_wiz_0_0
port map (
clk_in1 => clk_100_1,
clk_out1 => clk_wiz_0_clk_out2,
locked => NLW_clk_wiz_0_locked_UNCONNECTED
);
clk_wiz_1: component system_clk_wiz_1_0
port map (
clk_in1 => clk_100_1,
clk_out1 => clk_wiz_1_clk_out1,
locked => NLW_clk_wiz_1_locked_UNCONNECTED
);
clock_splitter_0: component system_clock_splitter_0_0
port map (
clk_in => \^pclk_1\,
clk_out => clock_splitter_0_clk_out,
latch_edge => \^vsync_1\
);
clock_splitter_1: component system_clock_splitter_1_0
port map (
clk_in => pclk_1_1,
clk_out => clock_splitter_1_clk_out,
latch_edge => vsync_1_1
);
debounce_0: component system_debounce_0_0
port map (
clk => vga_pll_0_clk_25,
signal_in => reset_1,
signal_out => debounce_0_o
);
inverter_0: component system_inverter_0_0
port map (
x => vga_sync_ref_0_start,
x_not => inverter_0_x_not
);
ov7670_controller_0: component system_ov7670_controller_0_0
port map (
clk => vga_pll_0_clk_25,
config_finished => ov7670_controller_0_config_finished1,
pwdn => NLW_ov7670_controller_0_pwdn_UNCONNECTED,
resend => debounce_0_o,
reset => NLW_ov7670_controller_0_reset_UNCONNECTED,
sioc => ov7670_controller_0_sioc,
siod => siod_0,
xclk => NLW_ov7670_controller_0_xclk_UNCONNECTED
);
ov7670_controller_1: component system_ov7670_controller_1_0
port map (
clk => vga_pll_0_clk_25,
config_finished => ov7670_controller_1_config_finished,
pwdn => NLW_ov7670_controller_1_pwdn_UNCONNECTED,
resend => debounce_0_o,
reset => NLW_ov7670_controller_1_reset_UNCONNECTED,
sioc => ov7670_controller_1_sioc,
siod => siod_1,
xclk => NLW_ov7670_controller_1_xclk_UNCONNECTED
);
ov7670_vga_0: component system_ov7670_vga_0_0
port map (
active => vga_sync_ref_0_active,
clk_x2 => \^pclk_1\,
data(7 downto 0) => \^data_1\(7 downto 0),
rgb(15 downto 0) => ov7670_vga_0_rgb(15 downto 0)
);
ov7670_vga_1: component system_ov7670_vga_1_0
port map (
active => vga_sync_ref_1_active,
clk_x2 => pclk_1_1,
data(7 downto 0) => data_1_1(7 downto 0),
rgb(15 downto 0) => ov7670_vga_1_rgb(15 downto 0)
);
rgb565_to_rgb888_0: component system_rgb565_to_rgb888_0_0
port map (
clk => clock_splitter_0_clk_out,
rgb_565(15 downto 0) => ov7670_vga_0_rgb(15 downto 0),
rgb_888(23 downto 0) => rgb565_to_rgb888_0_rgb_888(23 downto 0)
);
rgb565_to_rgb888_1: component system_rgb565_to_rgb888_1_0
port map (
clk => clock_splitter_1_clk_out,
rgb_565(15 downto 0) => ov7670_vga_1_rgb(15 downto 0),
rgb_888(23 downto 0) => rgb565_to_rgb888_1_rgb_888(23 downto 0)
);
rgb888_to_g8_0: component system_rgb888_to_g8_0_0
port map (
clk => vga_pll_0_clk_12_5,
g8(7 downto 0) => rgb888_to_g8_0_g8(7 downto 0),
rgb888(23 downto 0) => vga_buffer_0_data_r(23 downto 0)
);
rgb888_to_g8_1: component system_rgb888_to_g8_1_0
port map (
clk => vga_pll_0_clk_12_5,
g8(7 downto 0) => rgb888_to_g8_1_g8(7 downto 0),
rgb888(23 downto 0) => vga_buffer_1_data_r(23 downto 0)
);
util_vector_logic_0: component system_util_vector_logic_0_0
port map (
Op1(0) => ov7670_controller_0_config_finished1,
Op2(0) => ov7670_controller_1_config_finished,
Res(0) => ov7670_controller_0_config_finished(0)
);
vdd: component system_xlconstant_0_0
port map (
dout(0) => vdd_dout(0)
);
vga_buffer_0: component system_vga_buffer_0_0
port map (
clk_r => vga_pll_0_clk_12_5,
clk_w => clock_splitter_0_clk_out,
data_r(23 downto 0) => vga_buffer_0_data_r(23 downto 0),
data_w(23 downto 0) => rgb565_to_rgb888_0_rgb_888(23 downto 0),
wen => vga_sync_ref_0_active,
x_addr_r(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
x_addr_w(9 downto 0) => vga_sync_ref_0_xaddr(9 downto 0),
y_addr_r(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0),
y_addr_w(9 downto 0) => vga_sync_ref_0_yaddr(9 downto 0)
);
vga_buffer_1: component system_vga_buffer_1_0
port map (
clk_r => vga_pll_0_clk_12_5,
clk_w => clock_splitter_1_clk_out,
data_r(23 downto 0) => vga_buffer_1_data_r(23 downto 0),
data_w(23 downto 0) => rgb565_to_rgb888_1_rgb_888(23 downto 0),
wen => vga_sync_ref_1_active,
x_addr_r(9 downto 0) => vga_transform_0_x_addr_out(9 downto 0),
x_addr_w(9 downto 0) => vga_sync_ref_1_xaddr(9 downto 0),
y_addr_r(9 downto 0) => vga_transform_0_y_addr_out(9 downto 0),
y_addr_w(9 downto 0) => vga_sync_ref_1_yaddr(9 downto 0)
);
vga_feature_transform_0: component system_vga_feature_transform_0_0
port map (
active => vga_sync_reset_0_active,
clk => vga_pll_0_clk_12_5,
clk_x2 => vga_pll_0_clk_25,
hessian_0(31 downto 0) => vga_nmsuppression_0_hessian_out(31 downto 0),
hessian_1(31 downto 0) => vga_nmsuppression_1_hessian_out(31 downto 0),
rot_m00(15 downto 0) => vga_feature_transform_0_rot_m00(15 downto 0),
rot_m01(15 downto 0) => vga_feature_transform_0_rot_m01(15 downto 0),
rot_m10(15 downto 0) => vga_feature_transform_0_rot_m10(15 downto 0),
rot_m11(15 downto 0) => vga_feature_transform_0_rot_m11(15 downto 0),
rst => ov7670_controller_0_config_finished1,
state(1 downto 0) => NLW_vga_feature_transform_0_state_UNCONNECTED(1 downto 0),
t_x(9 downto 0) => vga_feature_transform_0_t_x(9 downto 0),
t_y(9 downto 0) => vga_feature_transform_0_t_y(9 downto 0),
vsync => vga_sync_reset_0_vsync,
x_addr_0(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
x_addr_1(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
y_addr_0(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0),
y_addr_1(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0)
);
vga_hessian_0: component system_vga_hessian_0_0
port map (
active => vga_sync_reset_0_active,
clk_x16 => clk_wiz_1_clk_out1,
g_in(7 downto 0) => rgb888_to_g8_0_g8(7 downto 0),
hessian_out(31 downto 0) => vga_hessian_0_hessian_out(31 downto 0),
rst => vga_sync_reset_0_vsync,
x_addr(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
y_addr(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0)
);
vga_hessian_1: component system_vga_hessian_1_0
port map (
active => vga_sync_reset_0_active,
clk_x16 => clk_wiz_1_clk_out1,
g_in(7 downto 0) => rgb888_to_g8_1_g8(7 downto 0),
hessian_out(31 downto 0) => vga_hessian_1_hessian_out(31 downto 0),
rst => vga_sync_reset_0_vsync,
x_addr(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
y_addr(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0)
);
vga_nmsuppression_0: component system_vga_nmsuppression_0_0
port map (
active => vga_sync_reset_0_active,
clk => vga_pll_0_clk_12_5,
enable => vdd_dout(0),
hessian_in(31 downto 0) => buffer_register_0_val_out(31 downto 0),
hessian_out(31 downto 0) => vga_nmsuppression_0_hessian_out(31 downto 0),
x_addr_in(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
x_addr_out(9 downto 0) => NLW_vga_nmsuppression_0_x_addr_out_UNCONNECTED(9 downto 0),
y_addr_in(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0),
y_addr_out(9 downto 0) => NLW_vga_nmsuppression_0_y_addr_out_UNCONNECTED(9 downto 0)
);
vga_nmsuppression_1: component system_vga_nmsuppression_1_0
port map (
active => vga_sync_reset_0_active,
clk => vga_pll_0_clk_12_5,
enable => vdd_dout(0),
hessian_in(31 downto 0) => buffer_register_1_val_out(31 downto 0),
hessian_out(31 downto 0) => vga_nmsuppression_1_hessian_out(31 downto 0),
x_addr_in(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
x_addr_out(9 downto 0) => NLW_vga_nmsuppression_1_x_addr_out_UNCONNECTED(9 downto 0),
y_addr_in(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0),
y_addr_out(9 downto 0) => NLW_vga_nmsuppression_1_y_addr_out_UNCONNECTED(9 downto 0)
);
vga_overlay_0: component system_vga_overlay_0_0
port map (
clk => vga_pll_0_clk_12_5,
rgb(23 downto 0) => vga_overlay_0_rgb(23 downto 0),
rgb_0(23 downto 0) => vga_buffer_0_data_r(23 downto 0),
rgb_1(23 downto 0) => vga_buffer_1_data_r(23 downto 0)
);
vga_pll_0: component system_vga_pll_0_0
port map (
clk_100 => clk_100_1,
clk_12_5 => vga_pll_0_clk_12_5,
clk_25 => vga_pll_0_clk_25,
clk_50 => NLW_vga_pll_0_clk_50_UNCONNECTED,
clk_6_25 => NLW_vga_pll_0_clk_6_25_UNCONNECTED
);
vga_sync_ref_0: component system_vga_sync_ref_0_0
port map (
active => vga_sync_ref_0_active,
clk => clock_splitter_0_clk_out,
hsync => \^hsync_1\,
rst => ov7670_controller_0_config_finished(0),
start => vga_sync_ref_0_start,
vsync => \^vsync_1\,
xaddr(9 downto 0) => vga_sync_ref_0_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_ref_0_yaddr(9 downto 0)
);
vga_sync_ref_1: component system_vga_sync_ref_1_0
port map (
active => vga_sync_ref_1_active,
clk => clock_splitter_1_clk_out,
hsync => hsync_1_1,
rst => ov7670_controller_0_config_finished(0),
start => NLW_vga_sync_ref_1_start_UNCONNECTED,
vsync => vsync_1_1,
xaddr(9 downto 0) => vga_sync_ref_1_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_ref_1_yaddr(9 downto 0)
);
vga_sync_reset_0: component system_vga_sync_reset_0_0
port map (
active => vga_sync_reset_0_active,
clk => vga_pll_0_clk_12_5,
hsync => vga_sync_reset_0_hsync,
rst => inverter_0_x_not,
vsync => vga_sync_reset_0_vsync,
xaddr(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0)
);
vga_transform_0: component system_vga_transform_0_0
port map (
clk => vga_pll_0_clk_12_5,
enable => vdd_dout(0),
rot_m00(15 downto 0) => vga_feature_transform_0_rot_m00(15 downto 0),
rot_m01(15 downto 0) => vga_feature_transform_0_rot_m01(15 downto 0),
rot_m10(15 downto 0) => vga_feature_transform_0_rot_m10(15 downto 0),
rot_m11(15 downto 0) => vga_feature_transform_0_rot_m11(15 downto 0),
t_x(9 downto 0) => vga_feature_transform_0_t_x(9 downto 0),
t_y(9 downto 0) => vga_feature_transform_0_t_y(9 downto 0),
x_addr_in(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
x_addr_out(9 downto 0) => vga_transform_0_x_addr_out(9 downto 0),
y_addr_in(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
y_addr_out(9 downto 0) => vga_transform_0_y_addr_out(9 downto 0)
);
zed_hdmi_0: component system_zed_hdmi_0_0
port map (
active => vga_sync_reset_0_active,
clk => vga_pll_0_clk_12_5,
clk_100 => clk_100_1,
clk_x2 => vga_pll_0_clk_25,
hdmi_clk => zed_hdmi_0_hdmi_clk,
hdmi_d(15 downto 0) => zed_hdmi_0_hdmi_d(15 downto 0),
hdmi_de => zed_hdmi_0_hdmi_de,
hdmi_hsync => zed_hdmi_0_hdmi_hsync,
hdmi_scl => zed_hdmi_0_hdmi_scl,
hdmi_sda => hdmi_sda,
hdmi_vsync => zed_hdmi_0_hdmi_vsync,
hsync => vga_sync_reset_0_hsync,
rgb888(23 downto 0) => vga_overlay_0_rgb(23 downto 0),
vsync => vga_sync_reset_0_vsync
);
end STRUCTURE;
| mit | 70d0fa5201cc979a4e6c0396802a1b7c | 0.631897 | 2.871907 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_hessian_0_0/sim/system_vga_hessian_0_0.vhd | 1 | 3,767 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
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-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
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-- loss or damage suffered as a result of any action brought
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-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
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-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
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--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_hessian:1.0
-- IP Revision: 41
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_hessian_0_0 IS
PORT (
clk_x16 : IN STD_LOGIC;
active : IN STD_LOGIC;
rst : IN STD_LOGIC;
x_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
g_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_vga_hessian_0_0;
ARCHITECTURE system_vga_hessian_0_0_arch OF system_vga_hessian_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_hessian_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_hessian IS
GENERIC (
ROW_WIDTH : INTEGER
);
PORT (
clk_x16 : IN STD_LOGIC;
active : IN STD_LOGIC;
rst : IN STD_LOGIC;
x_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
g_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT vga_hessian;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_hessian
GENERIC MAP (
ROW_WIDTH => 10
)
PORT MAP (
clk_x16 => clk_x16,
active => active,
rst => rst,
x_addr => x_addr,
y_addr => y_addr,
g_in => g_in,
hessian_out => hessian_out
);
END system_vga_hessian_0_0_arch;
| mit | 8fbdf75f78d02d76f5b4c18a6a64d8cb | 0.71038 | 3.808898 | false | false | false | false |
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